1 //===--- Targets.cpp - Implement target feature support -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/Builtins.h"
16 #include "clang/Basic/Cuda.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetInfo.h"
22 #include "clang/Basic/TargetOptions.h"
23 #include "clang/Basic/Version.h"
24 #include "clang/Frontend/CodeGenOptions.h"
25 #include "llvm/ADT/APFloat.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/StringSwitch.h"
30 #include "llvm/ADT/Triple.h"
31 #include "llvm/MC/MCSectionMachO.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/TargetParser.h"
37 using namespace clang;
39 //===----------------------------------------------------------------------===//
40 // Common code shared among targets.
41 //===----------------------------------------------------------------------===//
43 /// DefineStd - Define a macro name and standard variants. For example if
44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
47 const LangOptions &Opts) {
48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
51 // in the user's namespace.
53 Builder.defineMacro(MacroName);
56 Builder.defineMacro("__" + MacroName);
59 Builder.defineMacro("__" + MacroName + "__");
62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
64 Builder.defineMacro("__" + CPUName);
65 Builder.defineMacro("__" + CPUName + "__");
67 Builder.defineMacro("__tune_" + CPUName + "__");
70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
71 const TargetOptions &Opts);
73 //===----------------------------------------------------------------------===//
74 // Defines specific to certain operating systems.
75 //===----------------------------------------------------------------------===//
78 template<typename TgtInfo>
79 class OSTargetInfo : public TgtInfo {
81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
82 MacroBuilder &Builder) const=0;
84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
85 : TgtInfo(Triple, Opts) {}
86 void getTargetDefines(const LangOptions &Opts,
87 MacroBuilder &Builder) const override {
88 TgtInfo::getTargetDefines(Opts, Builder);
89 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
95 template <typename Target>
96 class CloudABITargetInfo : public OSTargetInfo<Target> {
98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
99 MacroBuilder &Builder) const override {
100 Builder.defineMacro("__CloudABI__");
101 Builder.defineMacro("__ELF__");
103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
104 Builder.defineMacro("__STDC_ISO_10646__", "201206L");
105 Builder.defineMacro("__STDC_UTF_16__");
106 Builder.defineMacro("__STDC_UTF_32__");
110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
111 : OSTargetInfo<Target>(Triple, Opts) {}
114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
115 const llvm::Triple &Triple,
116 StringRef &PlatformName,
117 VersionTuple &PlatformMinVersion) {
118 Builder.defineMacro("__APPLE_CC__", "6000");
119 Builder.defineMacro("__APPLE__");
120 Builder.defineMacro("OBJC_NEW_PROPERTIES");
121 // AddressSanitizer doesn't play well with source fortification, which is on
122 // by default on Darwin.
123 if (Opts.Sanitize.has(SanitizerKind::Address))
124 Builder.defineMacro("_FORTIFY_SOURCE", "0");
126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode.
128 // __weak is always defined, for use in blocks and with objc pointers.
129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
130 Builder.defineMacro("__strong", "");
131 Builder.defineMacro("__unsafe_unretained", "");
135 Builder.defineMacro("__STATIC__");
137 Builder.defineMacro("__DYNAMIC__");
139 if (Opts.POSIXThreads)
140 Builder.defineMacro("_REENTRANT");
142 // Get the platform type and version number from the triple.
143 unsigned Maj, Min, Rev;
144 if (Triple.isMacOSX()) {
145 Triple.getMacOSXVersion(Maj, Min, Rev);
146 PlatformName = "macos";
148 Triple.getOSVersion(Maj, Min, Rev);
149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
152 // If -target arch-pc-win32-macho option specified, we're
153 // generating code for Win32 ABI. No need to emit
154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
155 if (PlatformName == "win32") {
156 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
160 // Set the appropriate OS version define.
161 if (Triple.isiOS()) {
162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
166 Str[1] = '0' + (Min / 10);
167 Str[2] = '0' + (Min % 10);
168 Str[3] = '0' + (Rev / 10);
169 Str[4] = '0' + (Rev % 10);
172 // Handle versions >= 10.
173 Str[0] = '0' + (Maj / 10);
174 Str[1] = '0' + (Maj % 10);
175 Str[2] = '0' + (Min / 10);
176 Str[3] = '0' + (Min % 10);
177 Str[4] = '0' + (Rev / 10);
178 Str[5] = '0' + (Rev % 10);
182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str);
184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
187 } else if (Triple.isWatchOS()) {
188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
191 Str[1] = '0' + (Min / 10);
192 Str[2] = '0' + (Min % 10);
193 Str[3] = '0' + (Rev / 10);
194 Str[4] = '0' + (Rev % 10);
196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str);
197 } else if (Triple.isMacOSX()) {
198 // Note that the Driver allows versions which aren't representable in the
199 // define (because we only get a single digit for the minor and micro
200 // revision numbers). So, we limit them to the maximum representable
202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
204 if (Maj < 10 || (Maj == 10 && Min < 10)) {
205 Str[0] = '0' + (Maj / 10);
206 Str[1] = '0' + (Maj % 10);
207 Str[2] = '0' + std::min(Min, 9U);
208 Str[3] = '0' + std::min(Rev, 9U);
211 // Handle versions > 10.9.
212 Str[0] = '0' + (Maj / 10);
213 Str[1] = '0' + (Maj % 10);
214 Str[2] = '0' + (Min / 10);
215 Str[3] = '0' + (Min % 10);
216 Str[4] = '0' + (Rev / 10);
217 Str[5] = '0' + (Rev % 10);
220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
223 // Tell users about the kernel if there is one.
224 if (Triple.isOSDarwin())
225 Builder.defineMacro("__MACH__");
227 // The Watch ABI uses Dwarf EH.
228 if(Triple.isWatchABI())
229 Builder.defineMacro("__ARM_DWARF_EH__");
231 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
234 template<typename Target>
235 class DarwinTargetInfo : public OSTargetInfo<Target> {
237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
238 MacroBuilder &Builder) const override {
239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
240 this->PlatformMinVersion);
244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
245 : OSTargetInfo<Target>(Triple, Opts) {
246 // By default, no TLS, and we whitelist permitted architecture/OS
248 this->TLSSupported = false;
250 if (Triple.isMacOSX())
251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7);
252 else if (Triple.isiOS()) {
253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards.
254 if (Triple.getArch() == llvm::Triple::x86_64 ||
255 Triple.getArch() == llvm::Triple::aarch64)
256 this->TLSSupported = !Triple.isOSVersionLT(8);
257 else if (Triple.getArch() == llvm::Triple::x86 ||
258 Triple.getArch() == llvm::Triple::arm ||
259 Triple.getArch() == llvm::Triple::thumb)
260 this->TLSSupported = !Triple.isOSVersionLT(9);
261 } else if (Triple.isWatchOS())
262 this->TLSSupported = !Triple.isOSVersionLT(2);
264 this->MCountName = "\01mcount";
267 std::string isValidSectionSpecifier(StringRef SR) const override {
268 // Let MCSectionMachO validate this.
269 StringRef Segment, Section;
270 unsigned TAA, StubSize;
272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
273 TAA, HasTAA, StubSize);
276 const char *getStaticInitSectionSpecifier() const override {
277 // FIXME: We should return 0 when building kexts.
278 return "__TEXT,__StaticInit,regular,pure_instructions";
281 /// Darwin does not support protected visibility. Darwin's "default"
282 /// is very similar to ELF's "protected"; Darwin requires a "weak"
283 /// attribute on declarations that can be dynamically replaced.
284 bool hasProtectedVisibility() const override {
288 unsigned getExnObjectAlignment() const override {
289 // The alignment of an exception object is 8-bytes for darwin since
290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned))
291 // and therefore doesn't guarantee 16-byte alignment.
297 // DragonFlyBSD Target
298 template<typename Target>
299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
302 MacroBuilder &Builder) const override {
303 // DragonFly defines; list based off of gcc output
304 Builder.defineMacro("__DragonFly__");
305 Builder.defineMacro("__DragonFly_cc_version", "100001");
306 Builder.defineMacro("__ELF__");
307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
308 Builder.defineMacro("__tune_i386__");
309 DefineStd(Builder, "unix", Opts);
312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
313 : OSTargetInfo<Target>(Triple, Opts) {
314 switch (Triple.getArch()) {
316 case llvm::Triple::x86:
317 case llvm::Triple::x86_64:
318 this->MCountName = ".mcount";
324 #ifndef FREEBSD_CC_VERSION
325 #define FREEBSD_CC_VERSION 0U
329 template<typename Target>
330 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
333 MacroBuilder &Builder) const override {
334 // FreeBSD defines; list based off of gcc output
336 unsigned Release = Triple.getOSMajorVersion();
339 unsigned CCVersion = FREEBSD_CC_VERSION;
341 CCVersion = Release * 100000U + 1U;
343 Builder.defineMacro("__FreeBSD__", Twine(Release));
344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion));
345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
346 DefineStd(Builder, "unix", Opts);
347 Builder.defineMacro("__ELF__");
349 // On FreeBSD, wchar_t contains the number of the code point as
350 // used by the character set of the locale. These character sets are
351 // not necessarily a superset of ASCII.
353 // FIXME: This is wrong; the macro refers to the numerical values
354 // of wchar_t *literals*, which are not locale-dependent. However,
355 // FreeBSD systems apparently depend on us getting this wrong, and
356 // setting this to 1 is conforming even if all the basic source
357 // character literals have the same encoding as char and wchar_t.
358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
362 : OSTargetInfo<Target>(Triple, Opts) {
363 switch (Triple.getArch()) {
365 case llvm::Triple::x86:
366 case llvm::Triple::x86_64:
367 this->MCountName = ".mcount";
369 case llvm::Triple::mips:
370 case llvm::Triple::mipsel:
371 case llvm::Triple::ppc:
372 case llvm::Triple::ppc64:
373 case llvm::Triple::ppc64le:
374 this->MCountName = "_mcount";
376 case llvm::Triple::arm:
377 this->MCountName = "__mcount";
383 // GNU/kFreeBSD Target
384 template<typename Target>
385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
388 MacroBuilder &Builder) const override {
389 // GNU/kFreeBSD defines; list based off of gcc output
391 DefineStd(Builder, "unix", Opts);
392 Builder.defineMacro("__FreeBSD_kernel__");
393 Builder.defineMacro("__GLIBC__");
394 Builder.defineMacro("__ELF__");
395 if (Opts.POSIXThreads)
396 Builder.defineMacro("_REENTRANT");
398 Builder.defineMacro("_GNU_SOURCE");
401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
402 : OSTargetInfo<Target>(Triple, Opts) {}
406 template<typename Target>
407 class HaikuTargetInfo : public OSTargetInfo<Target> {
409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
410 MacroBuilder &Builder) const override {
411 // Haiku defines; list based off of gcc output
412 Builder.defineMacro("__HAIKU__");
413 Builder.defineMacro("__ELF__");
414 DefineStd(Builder, "unix", Opts);
417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
418 : OSTargetInfo<Target>(Triple, Opts) {
419 this->SizeType = TargetInfo::UnsignedLong;
420 this->IntPtrType = TargetInfo::SignedLong;
421 this->PtrDiffType = TargetInfo::SignedLong;
422 this->ProcessIDType = TargetInfo::SignedLong;
423 this->TLSSupported = false;
429 template<typename Target>
430 class MinixTargetInfo : public OSTargetInfo<Target> {
432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
433 MacroBuilder &Builder) const override {
436 Builder.defineMacro("__minix", "3");
437 Builder.defineMacro("_EM_WSIZE", "4");
438 Builder.defineMacro("_EM_PSIZE", "4");
439 Builder.defineMacro("_EM_SSIZE", "2");
440 Builder.defineMacro("_EM_LSIZE", "4");
441 Builder.defineMacro("_EM_FSIZE", "4");
442 Builder.defineMacro("_EM_DSIZE", "8");
443 Builder.defineMacro("__ELF__");
444 DefineStd(Builder, "unix", Opts);
447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
448 : OSTargetInfo<Target>(Triple, Opts) {}
452 template<typename Target>
453 class LinuxTargetInfo : public OSTargetInfo<Target> {
455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
456 MacroBuilder &Builder) const override {
457 // Linux defines; list based off of gcc output
458 DefineStd(Builder, "unix", Opts);
459 DefineStd(Builder, "linux", Opts);
460 Builder.defineMacro("__gnu_linux__");
461 Builder.defineMacro("__ELF__");
462 if (Triple.isAndroid()) {
463 Builder.defineMacro("__ANDROID__", "1");
464 unsigned Maj, Min, Rev;
465 Triple.getEnvironmentVersion(Maj, Min, Rev);
466 this->PlatformName = "android";
467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
469 Builder.defineMacro("__ANDROID_API__", Twine(Maj));
471 if (Opts.POSIXThreads)
472 Builder.defineMacro("_REENTRANT");
474 Builder.defineMacro("_GNU_SOURCE");
475 if (this->HasFloat128)
476 Builder.defineMacro("__FLOAT128__");
479 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
480 : OSTargetInfo<Target>(Triple, Opts) {
481 this->WIntType = TargetInfo::UnsignedInt;
483 switch (Triple.getArch()) {
486 case llvm::Triple::ppc:
487 case llvm::Triple::ppc64:
488 case llvm::Triple::ppc64le:
489 this->MCountName = "_mcount";
491 case llvm::Triple::x86:
492 case llvm::Triple::x86_64:
493 case llvm::Triple::systemz:
494 this->HasFloat128 = true;
499 const char *getStaticInitSectionSpecifier() const override {
500 return ".text.startup";
505 template<typename Target>
506 class NetBSDTargetInfo : public OSTargetInfo<Target> {
508 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
509 MacroBuilder &Builder) const override {
510 // NetBSD defines; list based off of gcc output
511 Builder.defineMacro("__NetBSD__");
512 Builder.defineMacro("__unix__");
513 Builder.defineMacro("__ELF__");
514 if (Opts.POSIXThreads)
515 Builder.defineMacro("_POSIX_THREADS");
517 switch (Triple.getArch()) {
520 case llvm::Triple::arm:
521 case llvm::Triple::armeb:
522 case llvm::Triple::thumb:
523 case llvm::Triple::thumbeb:
524 Builder.defineMacro("__ARM_DWARF_EH__");
529 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
530 : OSTargetInfo<Target>(Triple, Opts) {
531 this->MCountName = "_mcount";
536 template<typename Target>
537 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
539 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
540 MacroBuilder &Builder) const override {
541 // OpenBSD defines; list based off of gcc output
543 Builder.defineMacro("__OpenBSD__");
544 DefineStd(Builder, "unix", Opts);
545 Builder.defineMacro("__ELF__");
546 if (Opts.POSIXThreads)
547 Builder.defineMacro("_REENTRANT");
550 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
551 : OSTargetInfo<Target>(Triple, Opts) {
552 this->TLSSupported = false;
554 switch (Triple.getArch()) {
556 case llvm::Triple::x86:
557 case llvm::Triple::x86_64:
558 case llvm::Triple::arm:
559 case llvm::Triple::sparc:
560 this->MCountName = "__mcount";
562 case llvm::Triple::mips64:
563 case llvm::Triple::mips64el:
564 case llvm::Triple::ppc:
565 case llvm::Triple::sparcv9:
566 this->MCountName = "_mcount";
573 template<typename Target>
574 class BitrigTargetInfo : public OSTargetInfo<Target> {
576 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
577 MacroBuilder &Builder) const override {
578 // Bitrig defines; list based off of gcc output
580 Builder.defineMacro("__Bitrig__");
581 DefineStd(Builder, "unix", Opts);
582 Builder.defineMacro("__ELF__");
583 if (Opts.POSIXThreads)
584 Builder.defineMacro("_REENTRANT");
586 switch (Triple.getArch()) {
589 case llvm::Triple::arm:
590 case llvm::Triple::armeb:
591 case llvm::Triple::thumb:
592 case llvm::Triple::thumbeb:
593 Builder.defineMacro("__ARM_DWARF_EH__");
598 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
599 : OSTargetInfo<Target>(Triple, Opts) {
600 this->MCountName = "__mcount";
605 template<typename Target>
606 class PSPTargetInfo : public OSTargetInfo<Target> {
608 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
609 MacroBuilder &Builder) const override {
610 // PSP defines; list based on the output of the pspdev gcc toolchain.
611 Builder.defineMacro("PSP");
612 Builder.defineMacro("_PSP");
613 Builder.defineMacro("__psp__");
614 Builder.defineMacro("__ELF__");
617 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {}
621 template<typename Target>
622 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
624 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
625 MacroBuilder &Builder) const override {
627 Builder.defineMacro("__PPC__");
628 Builder.defineMacro("__PPU__");
629 Builder.defineMacro("__CELLOS_LV2__");
630 Builder.defineMacro("__ELF__");
631 Builder.defineMacro("__LP32__");
632 Builder.defineMacro("_ARCH_PPC64");
633 Builder.defineMacro("__powerpc64__");
636 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
637 : OSTargetInfo<Target>(Triple, Opts) {
638 this->LongWidth = this->LongAlign = 32;
639 this->PointerWidth = this->PointerAlign = 32;
640 this->IntMaxType = TargetInfo::SignedLongLong;
641 this->Int64Type = TargetInfo::SignedLongLong;
642 this->SizeType = TargetInfo::UnsignedInt;
643 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64");
647 template <typename Target>
648 class PS4OSTargetInfo : public OSTargetInfo<Target> {
650 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
651 MacroBuilder &Builder) const override {
652 Builder.defineMacro("__FreeBSD__", "9");
653 Builder.defineMacro("__FreeBSD_cc_version", "900001");
654 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
655 DefineStd(Builder, "unix", Opts);
656 Builder.defineMacro("__ELF__");
657 Builder.defineMacro("__ORBIS__");
660 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
661 : OSTargetInfo<Target>(Triple, Opts) {
662 this->WCharType = this->UnsignedShort;
664 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits).
665 this->MaxTLSAlign = 256;
667 // On PS4, do not honor explicit bit field alignment,
668 // as in "__attribute__((aligned(2))) int b : 1;".
669 this->UseExplicitBitFieldAlignment = false;
671 switch (Triple.getArch()) {
673 case llvm::Triple::x86_64:
674 this->MCountName = ".mcount";
681 template<typename Target>
682 class SolarisTargetInfo : public OSTargetInfo<Target> {
684 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
685 MacroBuilder &Builder) const override {
686 DefineStd(Builder, "sun", Opts);
687 DefineStd(Builder, "unix", Opts);
688 Builder.defineMacro("__ELF__");
689 Builder.defineMacro("__svr4__");
690 Builder.defineMacro("__SVR4");
691 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
692 // newer, but to 500 for everything else. feature_test.h has a check to
693 // ensure that you are not using C99 with an old version of X/Open or C89
694 // with a new version.
696 Builder.defineMacro("_XOPEN_SOURCE", "600");
698 Builder.defineMacro("_XOPEN_SOURCE", "500");
700 Builder.defineMacro("__C99FEATURES__");
701 Builder.defineMacro("_LARGEFILE_SOURCE");
702 Builder.defineMacro("_LARGEFILE64_SOURCE");
703 Builder.defineMacro("__EXTENSIONS__");
704 Builder.defineMacro("_REENTRANT");
707 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
708 : OSTargetInfo<Target>(Triple, Opts) {
709 this->WCharType = this->SignedInt;
710 // FIXME: WIntType should be SignedLong
715 template<typename Target>
716 class WindowsTargetInfo : public OSTargetInfo<Target> {
718 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
719 MacroBuilder &Builder) const override {
720 Builder.defineMacro("_WIN32");
722 void getVisualStudioDefines(const LangOptions &Opts,
723 MacroBuilder &Builder) const {
724 if (Opts.CPlusPlus) {
726 Builder.defineMacro("_CPPRTTI");
728 if (Opts.CXXExceptions)
729 Builder.defineMacro("_CPPUNWIND");
733 Builder.defineMacro("__BOOL_DEFINED");
735 if (!Opts.CharIsSigned)
736 Builder.defineMacro("_CHAR_UNSIGNED");
738 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
739 // but it works for now.
740 if (Opts.POSIXThreads)
741 Builder.defineMacro("_MT");
743 if (Opts.MSCompatibilityVersion) {
744 Builder.defineMacro("_MSC_VER",
745 Twine(Opts.MSCompatibilityVersion / 100000));
746 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
747 // FIXME We cannot encode the revision information into 32-bits
748 Builder.defineMacro("_MSC_BUILD", Twine(1));
750 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
751 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
753 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) {
754 if (Opts.CPlusPlus1z)
755 Builder.defineMacro("_MSVC_LANG", "201403L");
756 else if (Opts.CPlusPlus14)
757 Builder.defineMacro("_MSVC_LANG", "201402L");
761 if (Opts.MicrosoftExt) {
762 Builder.defineMacro("_MSC_EXTENSIONS");
764 if (Opts.CPlusPlus11) {
765 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
766 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
767 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
771 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
775 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
776 : OSTargetInfo<Target>(Triple, Opts) {}
779 template <typename Target>
780 class NaClTargetInfo : public OSTargetInfo<Target> {
782 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
783 MacroBuilder &Builder) const override {
784 if (Opts.POSIXThreads)
785 Builder.defineMacro("_REENTRANT");
787 Builder.defineMacro("_GNU_SOURCE");
789 DefineStd(Builder, "unix", Opts);
790 Builder.defineMacro("__ELF__");
791 Builder.defineMacro("__native_client__");
795 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
796 : OSTargetInfo<Target>(Triple, Opts) {
797 this->LongAlign = 32;
798 this->LongWidth = 32;
799 this->PointerAlign = 32;
800 this->PointerWidth = 32;
801 this->IntMaxType = TargetInfo::SignedLongLong;
802 this->Int64Type = TargetInfo::SignedLongLong;
803 this->DoubleAlign = 64;
804 this->LongDoubleWidth = 64;
805 this->LongDoubleAlign = 64;
806 this->LongLongWidth = 64;
807 this->LongLongAlign = 64;
808 this->SizeType = TargetInfo::UnsignedInt;
809 this->PtrDiffType = TargetInfo::SignedInt;
810 this->IntPtrType = TargetInfo::SignedInt;
811 // RegParmMax is inherited from the underlying architecture.
812 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble();
813 if (Triple.getArch() == llvm::Triple::arm) {
814 // Handled in ARM's setABI().
815 } else if (Triple.getArch() == llvm::Triple::x86) {
816 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128");
817 } else if (Triple.getArch() == llvm::Triple::x86_64) {
818 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128");
819 } else if (Triple.getArch() == llvm::Triple::mipsel) {
820 // Handled on mips' setDataLayout.
822 assert(Triple.getArch() == llvm::Triple::le32);
823 this->resetDataLayout("e-p:32:32-i64:64");
829 template<typename Target>
830 class FuchsiaTargetInfo : public OSTargetInfo<Target> {
832 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
833 MacroBuilder &Builder) const override {
834 Builder.defineMacro("__Fuchsia__");
835 Builder.defineMacro("__ELF__");
836 if (Opts.POSIXThreads)
837 Builder.defineMacro("_REENTRANT");
838 // Required by the libc++ locale support.
840 Builder.defineMacro("_GNU_SOURCE");
843 FuchsiaTargetInfo(const llvm::Triple &Triple,
844 const TargetOptions &Opts)
845 : OSTargetInfo<Target>(Triple, Opts) {
846 this->MCountName = "__mcount";
850 // WebAssembly target
851 template <typename Target>
852 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> {
853 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
854 MacroBuilder &Builder) const final {
855 // A common platform macro.
856 if (Opts.POSIXThreads)
857 Builder.defineMacro("_REENTRANT");
858 // Follow g++ convention and predefine _GNU_SOURCE for C++.
860 Builder.defineMacro("_GNU_SOURCE");
863 // As an optimization, group static init code together in a section.
864 const char *getStaticInitSectionSpecifier() const final {
865 return ".text.__startup";
869 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple,
870 const TargetOptions &Opts)
871 : OSTargetInfo<Target>(Triple, Opts) {
872 this->MCountName = "__mcount";
873 this->TheCXXABI.set(TargetCXXABI::WebAssembly);
877 //===----------------------------------------------------------------------===//
878 // Specific target implementations.
879 //===----------------------------------------------------------------------===//
881 // PPC abstract base class
882 class PPCTargetInfo : public TargetInfo {
883 static const Builtin::Info BuiltinInfo[];
884 static const char * const GCCRegNames[];
885 static const TargetInfo::GCCRegAlias GCCRegAliases[];
888 // Target cpu features.
903 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
904 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
905 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
906 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) {
907 SimdDefaultAlign = 128;
908 LongDoubleWidth = LongDoubleAlign = 128;
909 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
912 /// \brief Flags for architecture specific defines.
915 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
916 ArchDefinePpcgr = 1 << 1,
917 ArchDefinePpcsq = 1 << 2,
918 ArchDefine440 = 1 << 3,
919 ArchDefine603 = 1 << 4,
920 ArchDefine604 = 1 << 5,
921 ArchDefinePwr4 = 1 << 6,
922 ArchDefinePwr5 = 1 << 7,
923 ArchDefinePwr5x = 1 << 8,
924 ArchDefinePwr6 = 1 << 9,
925 ArchDefinePwr6x = 1 << 10,
926 ArchDefinePwr7 = 1 << 11,
927 ArchDefinePwr8 = 1 << 12,
928 ArchDefinePwr9 = 1 << 13,
929 ArchDefineA2 = 1 << 14,
930 ArchDefineA2q = 1 << 15
933 // Note: GCC recognizes the following additional cpus:
934 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
935 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
937 bool setCPU(const std::string &Name) override {
938 bool CPUKnown = llvm::StringSwitch<bool>(Name)
939 .Case("generic", true)
961 .Case("e500mc", true)
963 .Case("power3", true)
965 .Case("power4", true)
967 .Case("power5", true)
969 .Case("power5x", true)
971 .Case("power6", true)
973 .Case("power6x", true)
975 .Case("power7", true)
977 .Case("power8", true)
979 .Case("power9", true)
981 .Case("powerpc", true)
983 .Case("powerpc64", true)
985 .Case("powerpc64le", true)
986 .Case("ppc64le", true)
996 StringRef getABI() const override { return ABI; }
998 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
999 return llvm::makeArrayRef(BuiltinInfo,
1000 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin);
1003 bool isCLZForZeroUndef() const override { return false; }
1005 void getTargetDefines(const LangOptions &Opts,
1006 MacroBuilder &Builder) const override;
1009 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
1011 const std::vector<std::string> &FeaturesVec) const override;
1013 bool handleTargetFeatures(std::vector<std::string> &Features,
1014 DiagnosticsEngine &Diags) override;
1015 bool hasFeature(StringRef Feature) const override;
1016 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
1017 bool Enabled) const override;
1019 ArrayRef<const char *> getGCCRegNames() const override;
1020 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
1021 bool validateAsmConstraint(const char *&Name,
1022 TargetInfo::ConstraintInfo &Info) const override {
1024 default: return false;
1027 case 'b': // Base register
1028 case 'f': // Floating point register
1029 Info.setAllowsRegister();
1031 // FIXME: The following are added to allow parsing.
1032 // I just took a guess at what the actions should be.
1033 // Also, is more specific checking needed? I.e. specific registers?
1034 case 'd': // Floating point register (containing 64-bit value)
1035 case 'v': // Altivec vector register
1036 Info.setAllowsRegister();
1040 case 'd':// VSX vector register to hold vector double data
1041 case 'f':// VSX vector register to hold vector float data
1042 case 's':// VSX vector register to hold scalar float data
1043 case 'a':// Any VSX register
1044 case 'c':// An individual CR bit
1049 Info.setAllowsRegister();
1050 Name++; // Skip over 'w'.
1052 case 'h': // `MQ', `CTR', or `LINK' register
1053 case 'q': // `MQ' register
1054 case 'c': // `CTR' register
1055 case 'l': // `LINK' register
1056 case 'x': // `CR' register (condition register) number 0
1057 case 'y': // `CR' register (condition register)
1058 case 'z': // `XER[CA]' carry bit (part of the XER register)
1059 Info.setAllowsRegister();
1061 case 'I': // Signed 16-bit constant
1062 case 'J': // Unsigned 16-bit constant shifted left 16 bits
1063 // (use `L' instead for SImode constants)
1064 case 'K': // Unsigned 16-bit constant
1065 case 'L': // Signed 16-bit constant shifted left 16 bits
1066 case 'M': // Constant larger than 31
1067 case 'N': // Exact power of 2
1068 case 'P': // Constant whose negation is a signed 16-bit constant
1069 case 'G': // Floating point constant that can be loaded into a
1070 // register with one instruction per word
1071 case 'H': // Integer/Floating point constant that can be loaded
1072 // into a register using three instructions
1074 case 'm': // Memory operand. Note that on PowerPC targets, m can
1075 // include addresses that update the base register. It
1076 // is therefore only safe to use `m' in an asm statement
1077 // if that asm statement accesses the operand exactly once.
1078 // The asm statement must also use `%U<opno>' as a
1079 // placeholder for the "update" flag in the corresponding
1080 // load or store instruction. For example:
1081 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
1083 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
1084 // is not. Use es rather than m if you don't want the base
1085 // register to be updated.
1089 // es: A "stable" memory operand; that is, one which does not
1090 // include any automodification of the base register. Unlike
1091 // `m', this constraint can be used in asm statements that
1092 // might access the operand several times, or that might not
1093 // access it at all.
1094 Info.setAllowsMemory();
1095 Name++; // Skip over 'e'.
1097 case 'Q': // Memory operand that is an offset from a register (it is
1098 // usually better to use `m' or `es' in asm statements)
1099 case 'Z': // Memory operand that is an indexed or indirect from a
1100 // register (it is usually better to use `m' or `es' in
1102 Info.setAllowsMemory();
1103 Info.setAllowsRegister();
1105 case 'R': // AIX TOC entry
1106 case 'a': // Address operand that is an indexed or indirect from a
1107 // register (`p' is preferable for asm statements)
1108 case 'S': // Constant suitable as a 64-bit mask operand
1109 case 'T': // Constant suitable as a 32-bit mask operand
1110 case 'U': // System V Release 4 small data area reference
1111 case 't': // AND masks that can be performed by two rldic{l, r}
1113 case 'W': // Vector constant that does not require memory
1114 case 'j': // Vector constant that is all zeros.
1120 std::string convertConstraint(const char *&Constraint) const override {
1122 switch (*Constraint) {
1125 // Two-character constraint; add "^" hint for later parsing.
1126 R = std::string("^") + std::string(Constraint, 2);
1130 return TargetInfo::convertConstraint(Constraint);
1134 const char *getClobbers() const override {
1137 int getEHDataRegisterNumber(unsigned RegNo) const override {
1138 if (RegNo == 0) return 3;
1139 if (RegNo == 1) return 4;
1143 bool hasSjLjLowering() const override {
1147 bool useFloat128ManglingForLongDouble() const override {
1148 return LongDoubleWidth == 128 &&
1149 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() &&
1150 getTriple().isOSBinFormatELF();
1154 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
1155 #define BUILTIN(ID, TYPE, ATTRS) \
1156 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1157 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1158 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1159 #include "clang/Basic/BuiltinsPPC.def"
1162 /// handleTargetFeatures - Perform initialization based on the user
1163 /// configured set of features.
1164 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1165 DiagnosticsEngine &Diags) {
1166 for (const auto &Feature : Features) {
1167 if (Feature == "+vsx") {
1169 } else if (Feature == "+bpermd") {
1171 } else if (Feature == "+extdiv") {
1173 } else if (Feature == "+power8-vector") {
1175 } else if (Feature == "+crypto") {
1177 } else if (Feature == "+direct-move") {
1178 HasDirectMove = true;
1179 } else if (Feature == "+qpx") {
1181 } else if (Feature == "+htm") {
1183 } else if (Feature == "+float128") {
1185 } else if (Feature == "+power9-vector") {
1188 // TODO: Finish this list and add an assert that we've handled them
1195 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1196 /// #defines that are not tied to a specific subtarget.
1197 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1198 MacroBuilder &Builder) const {
1199 // Target identification.
1200 Builder.defineMacro("__ppc__");
1201 Builder.defineMacro("__PPC__");
1202 Builder.defineMacro("_ARCH_PPC");
1203 Builder.defineMacro("__powerpc__");
1204 Builder.defineMacro("__POWERPC__");
1205 if (PointerWidth == 64) {
1206 Builder.defineMacro("_ARCH_PPC64");
1207 Builder.defineMacro("__powerpc64__");
1208 Builder.defineMacro("__ppc64__");
1209 Builder.defineMacro("__PPC64__");
1212 // Target properties.
1213 if (getTriple().getArch() == llvm::Triple::ppc64le) {
1214 Builder.defineMacro("_LITTLE_ENDIAN");
1216 if (getTriple().getOS() != llvm::Triple::NetBSD &&
1217 getTriple().getOS() != llvm::Triple::OpenBSD)
1218 Builder.defineMacro("_BIG_ENDIAN");
1222 if (ABI == "elfv1" || ABI == "elfv1-qpx")
1223 Builder.defineMacro("_CALL_ELF", "1");
1225 Builder.defineMacro("_CALL_ELF", "2");
1227 // Subtarget options.
1228 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1229 Builder.defineMacro("__REGISTER_PREFIX__", "");
1231 // FIXME: Should be controlled by command line option.
1232 if (LongDoubleWidth == 128)
1233 Builder.defineMacro("__LONG_DOUBLE_128__");
1236 Builder.defineMacro("__VEC__", "10206");
1237 Builder.defineMacro("__ALTIVEC__");
1240 // CPU identification.
1241 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1242 .Case("440", ArchDefineName)
1243 .Case("450", ArchDefineName | ArchDefine440)
1244 .Case("601", ArchDefineName)
1245 .Case("602", ArchDefineName | ArchDefinePpcgr)
1246 .Case("603", ArchDefineName | ArchDefinePpcgr)
1247 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1248 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1249 .Case("604", ArchDefineName | ArchDefinePpcgr)
1250 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1251 .Case("620", ArchDefineName | ArchDefinePpcgr)
1252 .Case("630", ArchDefineName | ArchDefinePpcgr)
1253 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1254 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1255 .Case("750", ArchDefineName | ArchDefinePpcgr)
1256 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1258 .Case("a2", ArchDefineA2)
1259 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1260 .Case("pwr3", ArchDefinePpcgr)
1261 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1262 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1264 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1265 | ArchDefinePpcgr | ArchDefinePpcsq)
1266 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1267 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1268 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1269 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1271 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1272 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1273 | ArchDefinePpcgr | ArchDefinePpcsq)
1274 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1275 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1276 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1277 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7
1278 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1279 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1281 .Case("power3", ArchDefinePpcgr)
1282 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1283 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1285 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1286 | ArchDefinePpcgr | ArchDefinePpcsq)
1287 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1288 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1289 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1290 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1292 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1293 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1294 | ArchDefinePpcgr | ArchDefinePpcsq)
1295 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1296 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1297 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1298 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7
1299 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1300 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1302 .Default(ArchDefineNone);
1304 if (defs & ArchDefineName)
1305 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1306 if (defs & ArchDefinePpcgr)
1307 Builder.defineMacro("_ARCH_PPCGR");
1308 if (defs & ArchDefinePpcsq)
1309 Builder.defineMacro("_ARCH_PPCSQ");
1310 if (defs & ArchDefine440)
1311 Builder.defineMacro("_ARCH_440");
1312 if (defs & ArchDefine603)
1313 Builder.defineMacro("_ARCH_603");
1314 if (defs & ArchDefine604)
1315 Builder.defineMacro("_ARCH_604");
1316 if (defs & ArchDefinePwr4)
1317 Builder.defineMacro("_ARCH_PWR4");
1318 if (defs & ArchDefinePwr5)
1319 Builder.defineMacro("_ARCH_PWR5");
1320 if (defs & ArchDefinePwr5x)
1321 Builder.defineMacro("_ARCH_PWR5X");
1322 if (defs & ArchDefinePwr6)
1323 Builder.defineMacro("_ARCH_PWR6");
1324 if (defs & ArchDefinePwr6x)
1325 Builder.defineMacro("_ARCH_PWR6X");
1326 if (defs & ArchDefinePwr7)
1327 Builder.defineMacro("_ARCH_PWR7");
1328 if (defs & ArchDefinePwr8)
1329 Builder.defineMacro("_ARCH_PWR8");
1330 if (defs & ArchDefinePwr9)
1331 Builder.defineMacro("_ARCH_PWR9");
1332 if (defs & ArchDefineA2)
1333 Builder.defineMacro("_ARCH_A2");
1334 if (defs & ArchDefineA2q) {
1335 Builder.defineMacro("_ARCH_A2Q");
1336 Builder.defineMacro("_ARCH_QP");
1339 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1340 Builder.defineMacro("__bg__");
1341 Builder.defineMacro("__THW_BLUEGENE__");
1342 Builder.defineMacro("__bgq__");
1343 Builder.defineMacro("__TOS_BGQ__");
1347 Builder.defineMacro("__VSX__");
1349 Builder.defineMacro("__POWER8_VECTOR__");
1351 Builder.defineMacro("__CRYPTO__");
1353 Builder.defineMacro("__HTM__");
1355 Builder.defineMacro("__FLOAT128__");
1357 Builder.defineMacro("__POWER9_VECTOR__");
1359 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1360 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1361 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1362 if (PointerWidth == 64)
1363 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1365 // FIXME: The following are not yet generated here by Clang, but are
1366 // generated by GCC:
1369 // __RECIP_PRECISION__
1370 // __APPLE_ALTIVEC__
1379 // __CMODEL_MEDIUM__
1386 // Handle explicit options being passed to the compiler here: if we've
1387 // explicitly turned off vsx and turned on any of:
1392 // then go ahead and error since the customer has expressed an incompatible
1394 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
1395 const std::vector<std::string> &FeaturesVec) {
1397 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") !=
1398 FeaturesVec.end()) {
1399 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") !=
1400 FeaturesVec.end()) {
1401 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
1406 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") !=
1407 FeaturesVec.end()) {
1408 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
1413 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") !=
1414 FeaturesVec.end()) {
1415 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
1420 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") !=
1421 FeaturesVec.end()) {
1422 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector"
1431 bool PPCTargetInfo::initFeatureMap(
1432 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
1433 const std::vector<std::string> &FeaturesVec) const {
1434 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1445 .Case("ppc64", true)
1446 .Case("ppc64le", true)
1449 Features["qpx"] = (CPU == "a2q");
1450 Features["power9-vector"] = (CPU == "pwr9");
1451 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1452 .Case("ppc64le", true)
1456 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1457 .Case("ppc64le", true)
1461 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1462 .Case("ppc64le", true)
1467 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1468 .Case("ppc64le", true)
1473 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1474 .Case("ppc64le", true)
1478 Features["vsx"] = llvm::StringSwitch<bool>(CPU)
1479 .Case("ppc64le", true)
1485 if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
1488 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1491 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1492 return llvm::StringSwitch<bool>(Feature)
1493 .Case("powerpc", true)
1494 .Case("vsx", HasVSX)
1495 .Case("power8-vector", HasP8Vector)
1496 .Case("crypto", HasP8Crypto)
1497 .Case("direct-move", HasDirectMove)
1498 .Case("qpx", HasQPX)
1499 .Case("htm", HasHTM)
1500 .Case("bpermd", HasBPERMD)
1501 .Case("extdiv", HasExtDiv)
1502 .Case("float128", HasFloat128)
1503 .Case("power9-vector", HasP9Vector)
1507 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1508 StringRef Name, bool Enabled) const {
1509 // If we're enabling direct-move or power8-vector go ahead and enable vsx
1510 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user
1511 // incompatible options.
1513 if (Name == "direct-move" ||
1514 Name == "power8-vector" ||
1515 Name == "float128" ||
1516 Name == "power9-vector") {
1517 // power9-vector is really a superset of power8-vector so encode that.
1518 Features[Name] = Features["vsx"] = true;
1519 if (Name == "power9-vector")
1520 Features["power8-vector"] = true;
1522 Features[Name] = true;
1525 if (Name == "vsx") {
1526 Features[Name] = Features["direct-move"] = Features["power8-vector"] =
1527 Features["float128"] = Features["power9-vector"] = false;
1529 Features[Name] = false;
1534 const char * const PPCTargetInfo::GCCRegNames[] = {
1535 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1536 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1537 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1538 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1539 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1540 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1541 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1542 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1543 "mq", "lr", "ctr", "ap",
1544 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1546 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1547 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1548 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1549 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1551 "spe_acc", "spefscr",
1555 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const {
1556 return llvm::makeArrayRef(GCCRegNames);
1559 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1560 // While some of these aliases do map to different registers
1561 // they still share the same register name.
1572 { { "10" }, "r10" },
1573 { { "11" }, "r11" },
1574 { { "12" }, "r12" },
1575 { { "13" }, "r13" },
1576 { { "14" }, "r14" },
1577 { { "15" }, "r15" },
1578 { { "16" }, "r16" },
1579 { { "17" }, "r17" },
1580 { { "18" }, "r18" },
1581 { { "19" }, "r19" },
1582 { { "20" }, "r20" },
1583 { { "21" }, "r21" },
1584 { { "22" }, "r22" },
1585 { { "23" }, "r23" },
1586 { { "24" }, "r24" },
1587 { { "25" }, "r25" },
1588 { { "26" }, "r26" },
1589 { { "27" }, "r27" },
1590 { { "28" }, "r28" },
1591 { { "29" }, "r29" },
1592 { { "30" }, "r30" },
1593 { { "31" }, "r31" },
1594 { { "fr0" }, "f0" },
1595 { { "fr1" }, "f1" },
1596 { { "fr2" }, "f2" },
1597 { { "fr3" }, "f3" },
1598 { { "fr4" }, "f4" },
1599 { { "fr5" }, "f5" },
1600 { { "fr6" }, "f6" },
1601 { { "fr7" }, "f7" },
1602 { { "fr8" }, "f8" },
1603 { { "fr9" }, "f9" },
1604 { { "fr10" }, "f10" },
1605 { { "fr11" }, "f11" },
1606 { { "fr12" }, "f12" },
1607 { { "fr13" }, "f13" },
1608 { { "fr14" }, "f14" },
1609 { { "fr15" }, "f15" },
1610 { { "fr16" }, "f16" },
1611 { { "fr17" }, "f17" },
1612 { { "fr18" }, "f18" },
1613 { { "fr19" }, "f19" },
1614 { { "fr20" }, "f20" },
1615 { { "fr21" }, "f21" },
1616 { { "fr22" }, "f22" },
1617 { { "fr23" }, "f23" },
1618 { { "fr24" }, "f24" },
1619 { { "fr25" }, "f25" },
1620 { { "fr26" }, "f26" },
1621 { { "fr27" }, "f27" },
1622 { { "fr28" }, "f28" },
1623 { { "fr29" }, "f29" },
1624 { { "fr30" }, "f30" },
1625 { { "fr31" }, "f31" },
1626 { { "cc" }, "cr0" },
1629 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
1630 return llvm::makeArrayRef(GCCRegAliases);
1633 class PPC32TargetInfo : public PPCTargetInfo {
1635 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1636 : PPCTargetInfo(Triple, Opts) {
1637 resetDataLayout("E-m:e-p:32:32-i64:64-n32");
1639 switch (getTriple().getOS()) {
1640 case llvm::Triple::Linux:
1641 case llvm::Triple::FreeBSD:
1642 case llvm::Triple::NetBSD:
1643 SizeType = UnsignedInt;
1644 PtrDiffType = SignedInt;
1645 IntPtrType = SignedInt;
1651 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1652 LongDoubleWidth = LongDoubleAlign = 64;
1653 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1656 // PPC32 supports atomics up to 4 bytes.
1657 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1660 BuiltinVaListKind getBuiltinVaListKind() const override {
1661 // This is the ELF definition, and is overridden by the Darwin sub-target
1662 return TargetInfo::PowerABIBuiltinVaList;
1666 // Note: ABI differences may eventually require us to have a separate
1667 // TargetInfo for little endian.
1668 class PPC64TargetInfo : public PPCTargetInfo {
1670 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1671 : PPCTargetInfo(Triple, Opts) {
1672 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1673 IntMaxType = SignedLong;
1674 Int64Type = SignedLong;
1676 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1677 resetDataLayout("e-m:e-i64:64-n32:64");
1680 resetDataLayout("E-m:e-i64:64-n32:64");
1684 switch (getTriple().getOS()) {
1685 case llvm::Triple::FreeBSD:
1686 LongDoubleWidth = LongDoubleAlign = 64;
1687 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1689 case llvm::Triple::NetBSD:
1690 IntMaxType = SignedLongLong;
1691 Int64Type = SignedLongLong;
1697 // PPC64 supports atomics up to 8 bytes.
1698 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1700 BuiltinVaListKind getBuiltinVaListKind() const override {
1701 return TargetInfo::CharPtrBuiltinVaList;
1703 // PPC64 Linux-specific ABI options.
1704 bool setABI(const std::string &Name) override {
1705 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1713 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> {
1715 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1716 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
1717 HasAlignMac68kSupport = true;
1718 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1719 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1721 SuitableAlign = 128;
1722 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
1724 BuiltinVaListKind getBuiltinVaListKind() const override {
1725 return TargetInfo::CharPtrBuiltinVaList;
1729 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> {
1731 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1732 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
1733 HasAlignMac68kSupport = true;
1734 SuitableAlign = 128;
1735 resetDataLayout("E-m:o-i64:64-n32:64");
1739 static const unsigned NVPTXAddrSpaceMap[] = {
1742 4, // opencl_constant
1743 // FIXME: generic has to be added to the target
1744 0, // opencl_generic
1750 class NVPTXTargetInfo : public TargetInfo {
1751 static const char *const GCCRegNames[];
1752 static const Builtin::Info BuiltinInfo[];
1754 std::unique_ptr<TargetInfo> HostTarget;
1757 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts,
1758 unsigned TargetPointerWidth)
1759 : TargetInfo(Triple) {
1760 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) &&
1761 "NVPTX only supports 32- and 64-bit modes.");
1763 TLSSupported = false;
1764 AddrSpaceMap = &NVPTXAddrSpaceMap;
1765 UseAddrSpaceMapMangling = true;
1767 // Define available target features
1768 // These must be defined in sorted order!
1769 NoAsmVariants = true;
1770 GPU = CudaArch::SM_20;
1772 if (TargetPointerWidth == 32)
1773 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64");
1775 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64");
1777 // If possible, get a TargetInfo for our host triple, so we can match its
1779 llvm::Triple HostTriple(Opts.HostTriple);
1780 if (!HostTriple.isNVPTX())
1781 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts));
1783 // If no host target, make some guesses about the data layout and return.
1785 LongWidth = LongAlign = TargetPointerWidth;
1786 PointerWidth = PointerAlign = TargetPointerWidth;
1787 switch (TargetPointerWidth) {
1789 SizeType = TargetInfo::UnsignedInt;
1790 PtrDiffType = TargetInfo::SignedInt;
1791 IntPtrType = TargetInfo::SignedInt;
1794 SizeType = TargetInfo::UnsignedLong;
1795 PtrDiffType = TargetInfo::SignedLong;
1796 IntPtrType = TargetInfo::SignedLong;
1799 llvm_unreachable("TargetPointerWidth must be 32 or 64");
1804 // Copy properties from host target.
1805 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0);
1806 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0);
1807 BoolWidth = HostTarget->getBoolWidth();
1808 BoolAlign = HostTarget->getBoolAlign();
1809 IntWidth = HostTarget->getIntWidth();
1810 IntAlign = HostTarget->getIntAlign();
1811 HalfWidth = HostTarget->getHalfWidth();
1812 HalfAlign = HostTarget->getHalfAlign();
1813 FloatWidth = HostTarget->getFloatWidth();
1814 FloatAlign = HostTarget->getFloatAlign();
1815 DoubleWidth = HostTarget->getDoubleWidth();
1816 DoubleAlign = HostTarget->getDoubleAlign();
1817 LongWidth = HostTarget->getLongWidth();
1818 LongAlign = HostTarget->getLongAlign();
1819 LongLongWidth = HostTarget->getLongLongWidth();
1820 LongLongAlign = HostTarget->getLongLongAlign();
1821 MinGlobalAlign = HostTarget->getMinGlobalAlign();
1822 NewAlign = HostTarget->getNewAlign();
1823 DefaultAlignForAttributeAligned =
1824 HostTarget->getDefaultAlignForAttributeAligned();
1825 SizeType = HostTarget->getSizeType();
1826 IntMaxType = HostTarget->getIntMaxType();
1827 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0);
1828 IntPtrType = HostTarget->getIntPtrType();
1829 WCharType = HostTarget->getWCharType();
1830 WIntType = HostTarget->getWIntType();
1831 Char16Type = HostTarget->getChar16Type();
1832 Char32Type = HostTarget->getChar32Type();
1833 Int64Type = HostTarget->getInt64Type();
1834 SigAtomicType = HostTarget->getSigAtomicType();
1835 ProcessIDType = HostTarget->getProcessIDType();
1837 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
1838 UseZeroLengthBitfieldAlignment =
1839 HostTarget->useZeroLengthBitfieldAlignment();
1840 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
1841 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
1843 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
1844 // we need those macros to be identical on host and device, because (among
1845 // other things) they affect which standard library classes are defined, and
1846 // we need all classes to be defined on both the host and device.
1847 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
1849 // Properties intentionally not copied from host:
1850 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the
1851 // host/device boundary.
1852 // - SuitableAlign: Not visible across the host/device boundary, and may
1853 // correctly be different on host/device, e.g. if host has wider vector
1854 // types than device.
1855 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same
1856 // as its double type, but that's not necessarily true on the host.
1857 // TODO: nvcc emits a warning when using long double on device; we should
1860 void getTargetDefines(const LangOptions &Opts,
1861 MacroBuilder &Builder) const override {
1862 Builder.defineMacro("__PTX__");
1863 Builder.defineMacro("__NVPTX__");
1864 if (Opts.CUDAIsDevice) {
1865 // Set __CUDA_ARCH__ for the GPU specified.
1866 std::string CUDAArchCode = [this] {
1868 case CudaArch::UNKNOWN:
1869 assert(false && "No GPU arch when compiling CUDA device code.");
1871 case CudaArch::SM_20:
1873 case CudaArch::SM_21:
1875 case CudaArch::SM_30:
1877 case CudaArch::SM_32:
1879 case CudaArch::SM_35:
1881 case CudaArch::SM_37:
1883 case CudaArch::SM_50:
1885 case CudaArch::SM_52:
1887 case CudaArch::SM_53:
1889 case CudaArch::SM_60:
1891 case CudaArch::SM_61:
1893 case CudaArch::SM_62:
1896 llvm_unreachable("unhandled CudaArch");
1898 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1901 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1902 return llvm::makeArrayRef(BuiltinInfo,
1903 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin);
1906 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
1908 const std::vector<std::string> &FeaturesVec) const override {
1909 Features["satom"] = GPU >= CudaArch::SM_60;
1910 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1913 bool hasFeature(StringRef Feature) const override {
1914 return llvm::StringSwitch<bool>(Feature)
1915 .Cases("ptx", "nvptx", true)
1916 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope.
1920 ArrayRef<const char *> getGCCRegNames() const override;
1921 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1925 bool validateAsmConstraint(const char *&Name,
1926 TargetInfo::ConstraintInfo &Info) const override {
1936 Info.setAllowsRegister();
1940 const char *getClobbers() const override {
1941 // FIXME: Is this really right?
1944 BuiltinVaListKind getBuiltinVaListKind() const override {
1946 return TargetInfo::CharPtrBuiltinVaList;
1948 bool setCPU(const std::string &Name) override {
1949 GPU = StringToCudaArch(Name);
1950 return GPU != CudaArch::UNKNOWN;
1952 void setSupportedOpenCLOpts() override {
1953 auto &Opts = getSupportedOpenCLOpts();
1954 Opts.support("cl_clang_storage_class_specifiers");
1955 Opts.support("cl_khr_gl_sharing");
1956 Opts.support("cl_khr_icd");
1958 Opts.support("cl_khr_fp64");
1959 Opts.support("cl_khr_byte_addressable_store");
1960 Opts.support("cl_khr_global_int32_base_atomics");
1961 Opts.support("cl_khr_global_int32_extended_atomics");
1962 Opts.support("cl_khr_local_int32_base_atomics");
1963 Opts.support("cl_khr_local_int32_extended_atomics");
1966 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
1967 // CUDA compilations support all of the host's calling conventions.
1969 // TODO: We should warn if you apply a non-default CC to anything other than
1972 return HostTarget->checkCallingConvention(CC);
1973 return CCCR_Warning;
1977 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1978 #define BUILTIN(ID, TYPE, ATTRS) \
1979 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1980 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1981 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1982 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
1983 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
1984 #include "clang/Basic/BuiltinsNVPTX.def"
1987 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
1989 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
1990 return llvm::makeArrayRef(GCCRegNames);
1993 static const unsigned AMDGPUAddrSpaceMap[] = {
1996 2, // opencl_constant
1997 4, // opencl_generic
2003 // If you edit the description strings, make sure you update
2004 // getPointerWidthV().
2006 static const char *const DataLayoutStringR600 =
2007 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2008 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
2010 static const char *const DataLayoutStringSI =
2011 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
2012 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2013 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
2015 class AMDGPUTargetInfo final : public TargetInfo {
2016 static const Builtin::Info BuiltinInfo[];
2017 static const char * const GCCRegNames[];
2019 /// \brief The GPU profiles supported by the AMDGPU target.
2027 GK_EVERGREEN_DOUBLE_OPS,
2028 GK_NORTHERN_ISLANDS,
2038 bool hasFullSpeedFP32Denorms:1;
2040 static bool isAMDGCN(const llvm::Triple &TT) {
2041 return TT.getArch() == llvm::Triple::amdgcn;
2045 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
2046 : TargetInfo(Triple) ,
2047 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600),
2051 hasFullSpeedFP32Denorms(false){
2052 if (getTriple().getArch() == llvm::Triple::amdgcn) {
2058 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ?
2059 DataLayoutStringSI : DataLayoutStringR600);
2061 AddrSpaceMap = &AMDGPUAddrSpaceMap;
2062 UseAddrSpaceMapMangling = true;
2065 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
2066 if (GPU <= GK_CAYMAN)
2079 uint64_t getMaxPointerWidth() const override {
2080 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32;
2083 const char * getClobbers() const override {
2087 ArrayRef<const char *> getGCCRegNames() const override;
2089 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2093 bool validateAsmConstraint(const char *&Name,
2094 TargetInfo::ConstraintInfo &Info) const override {
2099 Info.setAllowsRegister();
2105 bool initFeatureMap(llvm::StringMap<bool> &Features,
2106 DiagnosticsEngine &Diags, StringRef CPU,
2107 const std::vector<std::string> &FeatureVec) const override;
2109 void adjustTargetOptions(const CodeGenOptions &CGOpts,
2110 TargetOptions &TargetOpts) const override {
2111 bool hasFP32Denormals = false;
2112 bool hasFP64Denormals = false;
2113 for (auto &I : TargetOpts.FeaturesAsWritten) {
2114 if (I == "+fp32-denormals" || I == "-fp32-denormals")
2115 hasFP32Denormals = true;
2116 if (I == "+fp64-denormals" || I == "-fp64-denormals")
2117 hasFP64Denormals = true;
2119 if (!hasFP32Denormals)
2120 TargetOpts.Features.push_back((Twine(hasFullSpeedFP32Denorms &&
2121 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str());
2122 // Always do not flush fp64 denorms.
2123 if (!hasFP64Denormals && hasFP64)
2124 TargetOpts.Features.push_back("+fp64-denormals");
2127 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
2128 return llvm::makeArrayRef(BuiltinInfo,
2129 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin);
2132 void getTargetDefines(const LangOptions &Opts,
2133 MacroBuilder &Builder) const override {
2134 if (getTriple().getArch() == llvm::Triple::amdgcn)
2135 Builder.defineMacro("__AMDGCN__");
2137 Builder.defineMacro("__R600__");
2140 Builder.defineMacro("__HAS_FMAF__");
2142 Builder.defineMacro("__HAS_LDEXPF__");
2144 Builder.defineMacro("__HAS_FP64__");
2147 BuiltinVaListKind getBuiltinVaListKind() const override {
2148 return TargetInfo::CharPtrBuiltinVaList;
2151 static GPUKind parseR600Name(StringRef Name) {
2152 return llvm::StringSwitch<GPUKind>(Name)
2153 .Case("r600" , GK_R600)
2154 .Case("rv610", GK_R600)
2155 .Case("rv620", GK_R600)
2156 .Case("rv630", GK_R600)
2157 .Case("rv635", GK_R600)
2158 .Case("rs780", GK_R600)
2159 .Case("rs880", GK_R600)
2160 .Case("rv670", GK_R600_DOUBLE_OPS)
2161 .Case("rv710", GK_R700)
2162 .Case("rv730", GK_R700)
2163 .Case("rv740", GK_R700_DOUBLE_OPS)
2164 .Case("rv770", GK_R700_DOUBLE_OPS)
2165 .Case("palm", GK_EVERGREEN)
2166 .Case("cedar", GK_EVERGREEN)
2167 .Case("sumo", GK_EVERGREEN)
2168 .Case("sumo2", GK_EVERGREEN)
2169 .Case("redwood", GK_EVERGREEN)
2170 .Case("juniper", GK_EVERGREEN)
2171 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
2172 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
2173 .Case("barts", GK_NORTHERN_ISLANDS)
2174 .Case("turks", GK_NORTHERN_ISLANDS)
2175 .Case("caicos", GK_NORTHERN_ISLANDS)
2176 .Case("cayman", GK_CAYMAN)
2177 .Case("aruba", GK_CAYMAN)
2181 static GPUKind parseAMDGCNName(StringRef Name) {
2182 return llvm::StringSwitch<GPUKind>(Name)
2183 .Case("tahiti", GK_GFX6)
2184 .Case("pitcairn", GK_GFX6)
2185 .Case("verde", GK_GFX6)
2186 .Case("oland", GK_GFX6)
2187 .Case("hainan", GK_GFX6)
2188 .Case("bonaire", GK_GFX7)
2189 .Case("kabini", GK_GFX7)
2190 .Case("kaveri", GK_GFX7)
2191 .Case("hawaii", GK_GFX7)
2192 .Case("mullins", GK_GFX7)
2193 .Case("gfx700", GK_GFX7)
2194 .Case("gfx701", GK_GFX7)
2195 .Case("gfx702", GK_GFX7)
2196 .Case("tonga", GK_GFX8)
2197 .Case("iceland", GK_GFX8)
2198 .Case("carrizo", GK_GFX8)
2199 .Case("fiji", GK_GFX8)
2200 .Case("stoney", GK_GFX8)
2201 .Case("polaris10", GK_GFX8)
2202 .Case("polaris11", GK_GFX8)
2203 .Case("gfx800", GK_GFX8)
2204 .Case("gfx801", GK_GFX8)
2205 .Case("gfx802", GK_GFX8)
2206 .Case("gfx803", GK_GFX8)
2207 .Case("gfx804", GK_GFX8)
2208 .Case("gfx810", GK_GFX8)
2212 bool setCPU(const std::string &Name) override {
2213 if (getTriple().getArch() == llvm::Triple::amdgcn)
2214 GPU = parseAMDGCNName(Name);
2216 GPU = parseR600Name(Name);
2218 return GPU != GK_NONE;
2221 void setSupportedOpenCLOpts() override {
2222 auto &Opts = getSupportedOpenCLOpts();
2223 Opts.support("cl_clang_storage_class_specifiers");
2224 Opts.support("cl_khr_icd");
2227 Opts.support("cl_khr_fp64");
2228 if (GPU >= GK_EVERGREEN) {
2229 Opts.support("cl_khr_byte_addressable_store");
2230 Opts.support("cl_khr_global_int32_base_atomics");
2231 Opts.support("cl_khr_global_int32_extended_atomics");
2232 Opts.support("cl_khr_local_int32_base_atomics");
2233 Opts.support("cl_khr_local_int32_extended_atomics");
2235 if (GPU >= GK_GFX6) {
2236 Opts.support("cl_khr_fp16");
2237 Opts.support("cl_khr_int64_base_atomics");
2238 Opts.support("cl_khr_int64_extended_atomics");
2239 Opts.support("cl_khr_mipmap_image");
2240 Opts.support("cl_khr_subgroups");
2241 Opts.support("cl_khr_3d_image_writes");
2242 Opts.support("cl_amd_media_ops");
2243 Opts.support("cl_amd_media_ops2");
2247 LangAS::ID getOpenCLImageAddrSpace() const override {
2248 return LangAS::opencl_constant;
2251 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2254 return CCCR_Warning;
2256 case CC_OpenCLKernel:
2261 // In amdgcn target the null pointer in global, constant, and generic
2262 // address space has value 0 but in private and local address space has
2264 uint64_t getNullPointerValue(unsigned AS) const override {
2265 return AS != LangAS::opencl_local && AS != 0 ? 0 : ~0;
2269 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
2270 #define BUILTIN(ID, TYPE, ATTRS) \
2271 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2272 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2273 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2274 #include "clang/Basic/BuiltinsAMDGPU.def"
2276 const char * const AMDGPUTargetInfo::GCCRegNames[] = {
2277 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2278 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2279 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2280 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
2281 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
2282 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
2283 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
2284 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
2285 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
2286 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
2287 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
2288 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
2289 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
2290 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
2291 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
2292 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
2293 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
2294 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
2295 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
2296 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
2297 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
2298 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
2299 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
2300 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
2301 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
2302 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
2303 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
2304 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
2305 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
2306 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
2307 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
2308 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
2309 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2310 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
2311 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
2312 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
2313 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
2314 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
2315 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
2316 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
2317 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
2318 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
2319 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
2320 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
2321 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
2322 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
2323 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
2324 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127",
2325 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi",
2326 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi"
2329 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const {
2330 return llvm::makeArrayRef(GCCRegNames);
2333 bool AMDGPUTargetInfo::initFeatureMap(
2334 llvm::StringMap<bool> &Features,
2335 DiagnosticsEngine &Diags, StringRef CPU,
2336 const std::vector<std::string> &FeatureVec) const {
2338 // XXX - What does the member GPU mean if device name string passed here?
2339 if (getTriple().getArch() == llvm::Triple::amdgcn) {
2343 switch (parseAMDGCNName(CPU)) {
2349 Features["s-memrealtime"] = true;
2350 Features["16-bit-insts"] = true;
2356 llvm_unreachable("unhandled subtarget");
2362 switch (parseR600Name(CPU)) {
2366 case GK_NORTHERN_ISLANDS:
2368 case GK_R600_DOUBLE_OPS:
2369 case GK_R700_DOUBLE_OPS:
2370 case GK_EVERGREEN_DOUBLE_OPS:
2372 Features["fp64"] = true;
2377 llvm_unreachable("unhandled subtarget");
2381 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec);
2384 const Builtin::Info BuiltinInfoX86[] = {
2385 #define BUILTIN(ID, TYPE, ATTRS) \
2386 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2387 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2388 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2389 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
2390 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
2391 #include "clang/Basic/BuiltinsX86.def"
2393 #define BUILTIN(ID, TYPE, ATTRS) \
2394 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2395 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2396 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2397 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
2398 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
2399 #include "clang/Basic/BuiltinsX86_64.def"
2403 static const char* const GCCRegNames[] = {
2404 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
2405 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
2406 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
2407 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
2408 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
2409 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2410 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
2411 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
2412 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
2413 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23",
2414 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31",
2415 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23",
2416 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31",
2417 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7",
2418 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15",
2419 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23",
2420 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31",
2421 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7",
2424 const TargetInfo::AddlRegName AddlRegNames[] = {
2425 { { "al", "ah", "eax", "rax" }, 0 },
2426 { { "bl", "bh", "ebx", "rbx" }, 3 },
2427 { { "cl", "ch", "ecx", "rcx" }, 2 },
2428 { { "dl", "dh", "edx", "rdx" }, 1 },
2429 { { "esi", "rsi" }, 4 },
2430 { { "edi", "rdi" }, 5 },
2431 { { "esp", "rsp" }, 7 },
2432 { { "ebp", "rbp" }, 6 },
2433 { { "r8d", "r8w", "r8b" }, 38 },
2434 { { "r9d", "r9w", "r9b" }, 39 },
2435 { { "r10d", "r10w", "r10b" }, 40 },
2436 { { "r11d", "r11w", "r11b" }, 41 },
2437 { { "r12d", "r12w", "r12b" }, 42 },
2438 { { "r13d", "r13w", "r13b" }, 43 },
2439 { { "r14d", "r14w", "r14b" }, 44 },
2440 { { "r15d", "r15w", "r15b" }, 45 },
2443 // X86 target abstract base class; x86-32 and x86-64 are very close, so
2444 // most of the implementation can be shared.
2445 class X86TargetInfo : public TargetInfo {
2447 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
2450 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
2451 } MMX3DNowLevel = NoMMX3DNow;
2459 bool HasAES = false;
2460 bool HasPCLMUL = false;
2461 bool HasLZCNT = false;
2462 bool HasRDRND = false;
2463 bool HasFSGSBASE = false;
2464 bool HasBMI = false;
2465 bool HasBMI2 = false;
2466 bool HasPOPCNT = false;
2467 bool HasRTM = false;
2468 bool HasPRFCHW = false;
2469 bool HasRDSEED = false;
2470 bool HasADX = false;
2471 bool HasTBM = false;
2472 bool HasFMA = false;
2473 bool HasF16C = false;
2474 bool HasAVX512CD = false;
2475 bool HasAVX512ER = false;
2476 bool HasAVX512PF = false;
2477 bool HasAVX512DQ = false;
2478 bool HasAVX512BW = false;
2479 bool HasAVX512VL = false;
2480 bool HasAVX512VBMI = false;
2481 bool HasAVX512IFMA = false;
2482 bool HasSHA = false;
2483 bool HasMPX = false;
2484 bool HasSGX = false;
2485 bool HasCX16 = false;
2486 bool HasFXSR = false;
2487 bool HasXSAVE = false;
2488 bool HasXSAVEOPT = false;
2489 bool HasXSAVEC = false;
2490 bool HasXSAVES = false;
2491 bool HasMWAITX = false;
2492 bool HasPKU = false;
2493 bool HasCLFLUSHOPT = false;
2494 bool HasPCOMMIT = false;
2495 bool HasCLWB = false;
2496 bool HasUMIP = false;
2497 bool HasMOVBE = false;
2498 bool HasPREFETCHWT1 = false;
2500 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2502 /// Each enumeration represents a particular CPU supported by Clang. These
2503 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2508 /// i386-generation processors.
2514 /// i486-generation processors.
2523 /// i586-generation processors, P5 microarchitecture based.
2531 /// i686-generation processors, P6 / Pentium M microarchitecture based.
2541 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2542 /// Clang however has some logic to suport this.
2543 // FIXME: Warn, deprecate, and potentially remove this.
2548 /// Netburst microarchitecture based processors.
2557 /// Core microarchitecture based processors.
2561 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2562 /// codename which GCC no longer accepts as an option to -march, but Clang
2563 /// has some logic for recognizing it.
2564 // FIXME: Warn, deprecate, and potentially remove this.
2576 /// Nehalem microarchitecture based processors.
2580 /// Westmere microarchitecture based processors.
2583 /// \name Sandy Bridge
2584 /// Sandy Bridge microarchitecture based processors.
2587 /// \name Ivy Bridge
2588 /// Ivy Bridge microarchitecture based processors.
2592 /// Haswell microarchitecture based processors.
2596 /// Broadwell microarchitecture based processors.
2599 /// \name Skylake Client
2600 /// Skylake client microarchitecture based processors.
2603 /// \name Skylake Server
2604 /// Skylake server microarchitecture based processors.
2607 /// \name Cannonlake Client
2608 /// Cannonlake client microarchitecture based processors.
2611 /// \name Knights Landing
2612 /// Knights Landing processor.
2616 /// Lakemont microarchitecture based processors.
2620 /// K6 architecture processors.
2628 /// K7 architecture processors.
2631 CK_AthlonThunderbird,
2638 /// K8 architecture processors.
2651 /// Bobcat architecture processors.
2658 /// Bulldozer architecture processors.
2666 /// This specification is deprecated and will be removed in the future.
2667 /// Users should prefer \see CK_K8.
2668 // FIXME: Warn on this when the CPU is set to it.
2674 /// Geode processors.
2680 CPUKind getCPUKind(StringRef CPU) const {
2681 return llvm::StringSwitch<CPUKind>(CPU)
2682 .Case("i386", CK_i386)
2683 .Case("i486", CK_i486)
2684 .Case("winchip-c6", CK_WinChipC6)
2685 .Case("winchip2", CK_WinChip2)
2687 .Case("i586", CK_i586)
2688 .Case("pentium", CK_Pentium)
2689 .Case("pentium-mmx", CK_PentiumMMX)
2690 .Case("i686", CK_i686)
2691 .Case("pentiumpro", CK_PentiumPro)
2692 .Case("pentium2", CK_Pentium2)
2693 .Case("pentium3", CK_Pentium3)
2694 .Case("pentium3m", CK_Pentium3M)
2695 .Case("pentium-m", CK_PentiumM)
2696 .Case("c3-2", CK_C3_2)
2697 .Case("yonah", CK_Yonah)
2698 .Case("pentium4", CK_Pentium4)
2699 .Case("pentium4m", CK_Pentium4M)
2700 .Case("prescott", CK_Prescott)
2701 .Case("nocona", CK_Nocona)
2702 .Case("core2", CK_Core2)
2703 .Case("penryn", CK_Penryn)
2704 .Case("bonnell", CK_Bonnell)
2705 .Case("atom", CK_Bonnell) // Legacy name.
2706 .Case("silvermont", CK_Silvermont)
2707 .Case("slm", CK_Silvermont) // Legacy name.
2708 .Case("nehalem", CK_Nehalem)
2709 .Case("corei7", CK_Nehalem) // Legacy name.
2710 .Case("westmere", CK_Westmere)
2711 .Case("sandybridge", CK_SandyBridge)
2712 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2713 .Case("ivybridge", CK_IvyBridge)
2714 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2715 .Case("haswell", CK_Haswell)
2716 .Case("core-avx2", CK_Haswell) // Legacy name.
2717 .Case("broadwell", CK_Broadwell)
2718 .Case("skylake", CK_SkylakeClient)
2719 .Case("skylake-avx512", CK_SkylakeServer)
2720 .Case("skx", CK_SkylakeServer) // Legacy name.
2721 .Case("cannonlake", CK_Cannonlake)
2722 .Case("knl", CK_KNL)
2723 .Case("lakemont", CK_Lakemont)
2725 .Case("k6-2", CK_K6_2)
2726 .Case("k6-3", CK_K6_3)
2727 .Case("athlon", CK_Athlon)
2728 .Case("athlon-tbird", CK_AthlonThunderbird)
2729 .Case("athlon-4", CK_Athlon4)
2730 .Case("athlon-xp", CK_AthlonXP)
2731 .Case("athlon-mp", CK_AthlonMP)
2732 .Case("athlon64", CK_Athlon64)
2733 .Case("athlon64-sse3", CK_Athlon64SSE3)
2734 .Case("athlon-fx", CK_AthlonFX)
2736 .Case("k8-sse3", CK_K8SSE3)
2737 .Case("opteron", CK_Opteron)
2738 .Case("opteron-sse3", CK_OpteronSSE3)
2739 .Case("barcelona", CK_AMDFAM10)
2740 .Case("amdfam10", CK_AMDFAM10)
2741 .Case("btver1", CK_BTVER1)
2742 .Case("btver2", CK_BTVER2)
2743 .Case("bdver1", CK_BDVER1)
2744 .Case("bdver2", CK_BDVER2)
2745 .Case("bdver3", CK_BDVER3)
2746 .Case("bdver4", CK_BDVER4)
2747 .Case("x86-64", CK_x86_64)
2748 .Case("geode", CK_Geode)
2749 .Default(CK_Generic);
2756 } FPMath = FP_Default;
2759 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
2760 : TargetInfo(Triple) {
2761 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
2763 unsigned getFloatEvalMethod() const override {
2764 // X87 evaluates with 80 bits "long double" precision.
2765 return SSELevel == NoSSE ? 2 : 0;
2767 ArrayRef<const char *> getGCCRegNames() const override {
2768 return llvm::makeArrayRef(GCCRegNames);
2770 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2773 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
2774 return llvm::makeArrayRef(AddlRegNames);
2776 bool validateCpuSupports(StringRef Name) const override;
2777 bool validateAsmConstraint(const char *&Name,
2778 TargetInfo::ConstraintInfo &info) const override;
2780 bool validateGlobalRegisterVariable(StringRef RegName,
2782 bool &HasSizeMismatch) const override {
2783 // esp and ebp are the only 32-bit registers the x86 backend can currently
2785 if (RegName.equals("esp") || RegName.equals("ebp")) {
2786 // Check that the register size is 32-bit.
2787 HasSizeMismatch = RegSize != 32;
2794 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2796 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2798 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2800 std::string convertConstraint(const char *&Constraint) const override;
2801 const char *getClobbers() const override {
2802 return "~{dirflag},~{fpsr},~{flags}";
2805 StringRef getConstraintRegister(const StringRef &Constraint,
2806 const StringRef &Expression) const override {
2807 StringRef::iterator I, E;
2808 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) {
2815 // For the register constraints, return the matching register name
2828 // In case the constraint is 'r' we need to return Expression
2832 // Default value if there is no constraint for the register
2838 void getTargetDefines(const LangOptions &Opts,
2839 MacroBuilder &Builder) const override;
2840 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2842 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2844 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2846 void setFeatureEnabled(llvm::StringMap<bool> &Features,
2847 StringRef Name, bool Enabled) const override {
2848 setFeatureEnabledImpl(Features, Name, Enabled);
2850 // This exists purely to cut down on the number of virtual calls in
2851 // initFeatureMap which calls this repeatedly.
2852 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2853 StringRef Name, bool Enabled);
2855 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
2857 const std::vector<std::string> &FeaturesVec) const override;
2858 bool hasFeature(StringRef Feature) const override;
2859 bool handleTargetFeatures(std::vector<std::string> &Features,
2860 DiagnosticsEngine &Diags) override;
2861 StringRef getABI() const override {
2862 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
2864 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2866 if (getTriple().getArch() == llvm::Triple::x86 &&
2867 MMX3DNowLevel == NoMMX3DNow)
2871 bool setCPU(const std::string &Name) override {
2872 CPU = getCPUKind(Name);
2874 // Perform any per-CPU checks necessary to determine if this CPU is
2876 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2877 // invalid without explaining *why*.
2880 // No processor selected!
2907 case CK_AthlonThunderbird:
2912 // Only accept certain architectures when compiling in 32-bit mode.
2913 if (getTriple().getArch() != llvm::Triple::x86)
2924 case CK_SandyBridge:
2928 case CK_SkylakeClient:
2929 case CK_SkylakeServer:
2933 case CK_Athlon64SSE3:
2938 case CK_OpteronSSE3:
2949 llvm_unreachable("Unhandled CPU kind");
2952 bool setFPMath(StringRef Name) override;
2954 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2955 // Most of the non-ARM calling conventions are i386 conventions.
2957 case CC_X86ThisCall:
2958 case CC_X86FastCall:
2960 case CC_X86VectorCall:
2965 case CC_IntelOclBicc:
2968 return CCCR_Warning;
2972 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2973 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2976 bool hasSjLjLowering() const override {
2980 void setSupportedOpenCLOpts() override {
2981 getSupportedOpenCLOpts().supportAll();
2985 bool X86TargetInfo::setFPMath(StringRef Name) {
2986 if (Name == "387") {
2990 if (Name == "sse") {
2997 bool X86TargetInfo::initFeatureMap(
2998 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
2999 const std::vector<std::string> &FeaturesVec) const {
3000 // FIXME: This *really* should not be here.
3001 // X86_64 always has SSE2.
3002 if (getTriple().getArch() == llvm::Triple::x86_64)
3003 setFeatureEnabledImpl(Features, "sse2", true);
3005 const CPUKind Kind = getCPUKind(CPU);
3007 // Enable X87 for all X86 processors but Lakemont.
3008 if (Kind != CK_Lakemont)
3009 setFeatureEnabledImpl(Features, "x87", true);
3025 setFeatureEnabledImpl(Features, "mmx", true);
3030 setFeatureEnabledImpl(Features, "sse", true);
3031 setFeatureEnabledImpl(Features, "fxsr", true);
3037 setFeatureEnabledImpl(Features, "sse2", true);
3038 setFeatureEnabledImpl(Features, "fxsr", true);
3043 setFeatureEnabledImpl(Features, "sse3", true);
3044 setFeatureEnabledImpl(Features, "fxsr", true);
3045 setFeatureEnabledImpl(Features, "cx16", true);
3049 setFeatureEnabledImpl(Features, "ssse3", true);
3050 setFeatureEnabledImpl(Features, "fxsr", true);
3051 setFeatureEnabledImpl(Features, "cx16", true);
3054 setFeatureEnabledImpl(Features, "sse4.1", true);
3055 setFeatureEnabledImpl(Features, "fxsr", true);
3056 setFeatureEnabledImpl(Features, "cx16", true);
3059 setFeatureEnabledImpl(Features, "avx512ifma", true);
3060 setFeatureEnabledImpl(Features, "avx512vbmi", true);
3061 setFeatureEnabledImpl(Features, "sha", true);
3062 setFeatureEnabledImpl(Features, "umip", true);
3064 case CK_SkylakeServer:
3065 setFeatureEnabledImpl(Features, "avx512f", true);
3066 setFeatureEnabledImpl(Features, "avx512cd", true);
3067 setFeatureEnabledImpl(Features, "avx512dq", true);
3068 setFeatureEnabledImpl(Features, "avx512bw", true);
3069 setFeatureEnabledImpl(Features, "avx512vl", true);
3070 setFeatureEnabledImpl(Features, "pku", true);
3071 setFeatureEnabledImpl(Features, "pcommit", true);
3072 setFeatureEnabledImpl(Features, "clwb", true);
3074 case CK_SkylakeClient:
3075 setFeatureEnabledImpl(Features, "xsavec", true);
3076 setFeatureEnabledImpl(Features, "xsaves", true);
3077 setFeatureEnabledImpl(Features, "mpx", true);
3078 setFeatureEnabledImpl(Features, "sgx", true);
3079 setFeatureEnabledImpl(Features, "clflushopt", true);
3082 setFeatureEnabledImpl(Features, "rdseed", true);
3083 setFeatureEnabledImpl(Features, "adx", true);
3086 setFeatureEnabledImpl(Features, "avx2", true);
3087 setFeatureEnabledImpl(Features, "lzcnt", true);
3088 setFeatureEnabledImpl(Features, "bmi", true);
3089 setFeatureEnabledImpl(Features, "bmi2", true);
3090 setFeatureEnabledImpl(Features, "rtm", true);
3091 setFeatureEnabledImpl(Features, "fma", true);
3092 setFeatureEnabledImpl(Features, "movbe", true);
3095 setFeatureEnabledImpl(Features, "rdrnd", true);
3096 setFeatureEnabledImpl(Features, "f16c", true);
3097 setFeatureEnabledImpl(Features, "fsgsbase", true);
3099 case CK_SandyBridge:
3100 setFeatureEnabledImpl(Features, "avx", true);
3101 setFeatureEnabledImpl(Features, "xsave", true);
3102 setFeatureEnabledImpl(Features, "xsaveopt", true);
3106 setFeatureEnabledImpl(Features, "aes", true);
3107 setFeatureEnabledImpl(Features, "pclmul", true);
3110 setFeatureEnabledImpl(Features, "sse4.2", true);
3111 setFeatureEnabledImpl(Features, "fxsr", true);
3112 setFeatureEnabledImpl(Features, "cx16", true);
3115 setFeatureEnabledImpl(Features, "avx512f", true);
3116 setFeatureEnabledImpl(Features, "avx512cd", true);
3117 setFeatureEnabledImpl(Features, "avx512er", true);
3118 setFeatureEnabledImpl(Features, "avx512pf", true);
3119 setFeatureEnabledImpl(Features, "prefetchwt1", true);
3120 setFeatureEnabledImpl(Features, "fxsr", true);
3121 setFeatureEnabledImpl(Features, "rdseed", true);
3122 setFeatureEnabledImpl(Features, "adx", true);
3123 setFeatureEnabledImpl(Features, "lzcnt", true);
3124 setFeatureEnabledImpl(Features, "bmi", true);
3125 setFeatureEnabledImpl(Features, "bmi2", true);
3126 setFeatureEnabledImpl(Features, "rtm", true);
3127 setFeatureEnabledImpl(Features, "fma", true);
3128 setFeatureEnabledImpl(Features, "rdrnd", true);
3129 setFeatureEnabledImpl(Features, "f16c", true);
3130 setFeatureEnabledImpl(Features, "fsgsbase", true);
3131 setFeatureEnabledImpl(Features, "aes", true);
3132 setFeatureEnabledImpl(Features, "pclmul", true);
3133 setFeatureEnabledImpl(Features, "cx16", true);
3134 setFeatureEnabledImpl(Features, "xsaveopt", true);
3135 setFeatureEnabledImpl(Features, "xsave", true);
3136 setFeatureEnabledImpl(Features, "movbe", true);
3142 setFeatureEnabledImpl(Features, "3dnow", true);
3145 case CK_AthlonThunderbird:
3147 setFeatureEnabledImpl(Features, "3dnowa", true);
3152 setFeatureEnabledImpl(Features, "sse", true);
3153 setFeatureEnabledImpl(Features, "3dnowa", true);
3154 setFeatureEnabledImpl(Features, "fxsr", true);
3160 setFeatureEnabledImpl(Features, "sse2", true);
3161 setFeatureEnabledImpl(Features, "3dnowa", true);
3162 setFeatureEnabledImpl(Features, "fxsr", true);
3165 setFeatureEnabledImpl(Features, "sse4a", true);
3166 setFeatureEnabledImpl(Features, "lzcnt", true);
3167 setFeatureEnabledImpl(Features, "popcnt", true);
3170 case CK_OpteronSSE3:
3171 case CK_Athlon64SSE3:
3172 setFeatureEnabledImpl(Features, "sse3", true);
3173 setFeatureEnabledImpl(Features, "3dnowa", true);
3174 setFeatureEnabledImpl(Features, "fxsr", true);
3177 setFeatureEnabledImpl(Features, "avx", true);
3178 setFeatureEnabledImpl(Features, "aes", true);
3179 setFeatureEnabledImpl(Features, "pclmul", true);
3180 setFeatureEnabledImpl(Features, "bmi", true);
3181 setFeatureEnabledImpl(Features, "f16c", true);
3182 setFeatureEnabledImpl(Features, "xsaveopt", true);
3185 setFeatureEnabledImpl(Features, "ssse3", true);
3186 setFeatureEnabledImpl(Features, "sse4a", true);
3187 setFeatureEnabledImpl(Features, "lzcnt", true);
3188 setFeatureEnabledImpl(Features, "popcnt", true);
3189 setFeatureEnabledImpl(Features, "prfchw", true);
3190 setFeatureEnabledImpl(Features, "cx16", true);
3191 setFeatureEnabledImpl(Features, "fxsr", true);
3194 setFeatureEnabledImpl(Features, "avx2", true);
3195 setFeatureEnabledImpl(Features, "bmi2", true);
3196 setFeatureEnabledImpl(Features, "mwaitx", true);
3199 setFeatureEnabledImpl(Features, "fsgsbase", true);
3200 setFeatureEnabledImpl(Features, "xsaveopt", true);
3203 setFeatureEnabledImpl(Features, "bmi", true);
3204 setFeatureEnabledImpl(Features, "fma", true);
3205 setFeatureEnabledImpl(Features, "f16c", true);
3206 setFeatureEnabledImpl(Features, "tbm", true);
3209 // xop implies avx, sse4a and fma4.
3210 setFeatureEnabledImpl(Features, "xop", true);
3211 setFeatureEnabledImpl(Features, "lzcnt", true);
3212 setFeatureEnabledImpl(Features, "aes", true);
3213 setFeatureEnabledImpl(Features, "pclmul", true);
3214 setFeatureEnabledImpl(Features, "prfchw", true);
3215 setFeatureEnabledImpl(Features, "cx16", true);
3216 setFeatureEnabledImpl(Features, "fxsr", true);
3217 setFeatureEnabledImpl(Features, "xsave", true);
3220 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
3223 // Can't do this earlier because we need to be able to explicitly enable
3224 // or disable these features and the things that they depend upon.
3226 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
3227 auto I = Features.find("sse4.2");
3228 if (I != Features.end() && I->getValue() &&
3229 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
3231 Features["popcnt"] = true;
3233 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
3234 I = Features.find("3dnow");
3235 if (I != Features.end() && I->getValue() &&
3236 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
3238 Features["prfchw"] = true;
3240 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
3242 I = Features.find("sse");
3243 if (I != Features.end() && I->getValue() &&
3244 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
3246 Features["mmx"] = true;
3251 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
3252 X86SSEEnum Level, bool Enabled) {
3256 Features["avx512f"] = true;
3258 Features["avx2"] = true;
3260 Features["avx"] = true;
3261 Features["xsave"] = true;
3263 Features["sse4.2"] = true;
3265 Features["sse4.1"] = true;
3267 Features["ssse3"] = true;
3269 Features["sse3"] = true;
3271 Features["sse2"] = true;
3273 Features["sse"] = true;
3283 Features["sse"] = false;
3285 Features["sse2"] = Features["pclmul"] = Features["aes"] =
3286 Features["sha"] = false;
3288 Features["sse3"] = false;
3289 setXOPLevel(Features, NoXOP, false);
3291 Features["ssse3"] = false;
3293 Features["sse4.1"] = false;
3295 Features["sse4.2"] = false;
3297 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
3298 Features["xsaveopt"] = false;
3299 setXOPLevel(Features, FMA4, false);
3301 Features["avx2"] = false;
3303 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
3304 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
3305 Features["avx512vl"] = Features["avx512vbmi"] =
3306 Features["avx512ifma"] = false;
3310 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
3311 MMX3DNowEnum Level, bool Enabled) {
3314 case AMD3DNowAthlon:
3315 Features["3dnowa"] = true;
3317 Features["3dnow"] = true;
3319 Features["mmx"] = true;
3329 Features["mmx"] = false;
3331 Features["3dnow"] = false;
3332 case AMD3DNowAthlon:
3333 Features["3dnowa"] = false;
3337 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
3342 Features["xop"] = true;
3344 Features["fma4"] = true;
3345 setSSELevel(Features, AVX, true);
3347 Features["sse4a"] = true;
3348 setSSELevel(Features, SSE3, true);
3358 Features["sse4a"] = false;
3360 Features["fma4"] = false;
3362 Features["xop"] = false;
3366 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
3367 StringRef Name, bool Enabled) {
3368 // This is a bit of a hack to deal with the sse4 target feature when used
3369 // as part of the target attribute. We handle sse4 correctly everywhere
3370 // else. See below for more information on how we handle the sse4 options.
3372 Features[Name] = Enabled;
3374 if (Name == "mmx") {
3375 setMMXLevel(Features, MMX, Enabled);
3376 } else if (Name == "sse") {
3377 setSSELevel(Features, SSE1, Enabled);
3378 } else if (Name == "sse2") {
3379 setSSELevel(Features, SSE2, Enabled);
3380 } else if (Name == "sse3") {
3381 setSSELevel(Features, SSE3, Enabled);
3382 } else if (Name == "ssse3") {
3383 setSSELevel(Features, SSSE3, Enabled);
3384 } else if (Name == "sse4.2") {
3385 setSSELevel(Features, SSE42, Enabled);
3386 } else if (Name == "sse4.1") {
3387 setSSELevel(Features, SSE41, Enabled);
3388 } else if (Name == "3dnow") {
3389 setMMXLevel(Features, AMD3DNow, Enabled);
3390 } else if (Name == "3dnowa") {
3391 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
3392 } else if (Name == "aes") {
3394 setSSELevel(Features, SSE2, Enabled);
3395 } else if (Name == "pclmul") {
3397 setSSELevel(Features, SSE2, Enabled);
3398 } else if (Name == "avx") {
3399 setSSELevel(Features, AVX, Enabled);
3400 } else if (Name == "avx2") {
3401 setSSELevel(Features, AVX2, Enabled);
3402 } else if (Name == "avx512f") {
3403 setSSELevel(Features, AVX512F, Enabled);
3404 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
3405 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
3406 Name == "avx512vbmi" || Name == "avx512ifma") {
3408 setSSELevel(Features, AVX512F, Enabled);
3409 // Enable BWI instruction if VBMI is being enabled.
3410 if (Name == "avx512vbmi" && Enabled)
3411 Features["avx512bw"] = true;
3412 // Also disable VBMI if BWI is being disabled.
3413 if (Name == "avx512bw" && !Enabled)
3414 Features["avx512vbmi"] = false;
3415 } else if (Name == "fma") {
3417 setSSELevel(Features, AVX, Enabled);
3418 } else if (Name == "fma4") {
3419 setXOPLevel(Features, FMA4, Enabled);
3420 } else if (Name == "xop") {
3421 setXOPLevel(Features, XOP, Enabled);
3422 } else if (Name == "sse4a") {
3423 setXOPLevel(Features, SSE4A, Enabled);
3424 } else if (Name == "f16c") {
3426 setSSELevel(Features, AVX, Enabled);
3427 } else if (Name == "sha") {
3429 setSSELevel(Features, SSE2, Enabled);
3430 } else if (Name == "sse4") {
3431 // We can get here via the __target__ attribute since that's not controlled
3432 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
3433 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
3436 setSSELevel(Features, SSE42, Enabled);
3438 setSSELevel(Features, SSE41, Enabled);
3439 } else if (Name == "xsave") {
3441 Features["xsaveopt"] = false;
3442 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
3444 Features["xsave"] = true;
3448 /// handleTargetFeatures - Perform initialization based on the user
3449 /// configured set of features.
3450 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
3451 DiagnosticsEngine &Diags) {
3452 for (const auto &Feature : Features) {
3453 if (Feature[0] != '+')
3456 if (Feature == "+aes") {
3458 } else if (Feature == "+pclmul") {
3460 } else if (Feature == "+lzcnt") {
3462 } else if (Feature == "+rdrnd") {
3464 } else if (Feature == "+fsgsbase") {
3466 } else if (Feature == "+bmi") {
3468 } else if (Feature == "+bmi2") {
3470 } else if (Feature == "+popcnt") {
3472 } else if (Feature == "+rtm") {
3474 } else if (Feature == "+prfchw") {
3476 } else if (Feature == "+rdseed") {
3478 } else if (Feature == "+adx") {
3480 } else if (Feature == "+tbm") {
3482 } else if (Feature == "+fma") {
3484 } else if (Feature == "+f16c") {
3486 } else if (Feature == "+avx512cd") {
3488 } else if (Feature == "+avx512er") {
3490 } else if (Feature == "+avx512pf") {
3492 } else if (Feature == "+avx512dq") {
3494 } else if (Feature == "+avx512bw") {
3496 } else if (Feature == "+avx512vl") {
3498 } else if (Feature == "+avx512vbmi") {
3499 HasAVX512VBMI = true;
3500 } else if (Feature == "+avx512ifma") {
3501 HasAVX512IFMA = true;
3502 } else if (Feature == "+sha") {
3504 } else if (Feature == "+mpx") {
3506 } else if (Feature == "+movbe") {
3508 } else if (Feature == "+sgx") {
3510 } else if (Feature == "+cx16") {
3512 } else if (Feature == "+fxsr") {
3514 } else if (Feature == "+xsave") {
3516 } else if (Feature == "+xsaveopt") {
3518 } else if (Feature == "+xsavec") {
3520 } else if (Feature == "+xsaves") {
3522 } else if (Feature == "+mwaitx") {
3524 } else if (Feature == "+pku") {
3526 } else if (Feature == "+clflushopt") {
3527 HasCLFLUSHOPT = true;
3528 } else if (Feature == "+pcommit") {
3530 } else if (Feature == "+clwb") {
3532 } else if (Feature == "+umip") {
3534 } else if (Feature == "+prefetchwt1") {
3535 HasPREFETCHWT1 = true;
3538 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
3539 .Case("+avx512f", AVX512F)
3540 .Case("+avx2", AVX2)
3542 .Case("+sse4.2", SSE42)
3543 .Case("+sse4.1", SSE41)
3544 .Case("+ssse3", SSSE3)
3545 .Case("+sse3", SSE3)
3546 .Case("+sse2", SSE2)
3549 SSELevel = std::max(SSELevel, Level);
3551 MMX3DNowEnum ThreeDNowLevel =
3552 llvm::StringSwitch<MMX3DNowEnum>(Feature)
3553 .Case("+3dnowa", AMD3DNowAthlon)
3554 .Case("+3dnow", AMD3DNow)
3556 .Default(NoMMX3DNow);
3557 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
3559 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
3561 .Case("+fma4", FMA4)
3562 .Case("+sse4a", SSE4A)
3564 XOPLevel = std::max(XOPLevel, XLevel);
3567 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
3568 // matches the selected sse level.
3569 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
3570 (FPMath == FP_387 && SSELevel >= SSE1)) {
3571 Diags.Report(diag::err_target_unsupported_fpmath) <<
3572 (FPMath == FP_SSE ? "sse" : "387");
3577 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3581 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
3582 /// definitions for this particular subtarget.
3583 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
3584 MacroBuilder &Builder) const {
3585 // Target identification.
3586 if (getTriple().getArch() == llvm::Triple::x86_64) {
3587 Builder.defineMacro("__amd64__");
3588 Builder.defineMacro("__amd64");
3589 Builder.defineMacro("__x86_64");
3590 Builder.defineMacro("__x86_64__");
3591 if (getTriple().getArchName() == "x86_64h") {
3592 Builder.defineMacro("__x86_64h");
3593 Builder.defineMacro("__x86_64h__");
3596 DefineStd(Builder, "i386", Opts);
3599 // Subtarget options.
3600 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
3601 // truly should be based on -mtune options.
3606 // The rest are coming from the i386 define above.
3607 Builder.defineMacro("__tune_i386__");
3613 defineCPUMacros(Builder, "i486");
3616 Builder.defineMacro("__pentium_mmx__");
3617 Builder.defineMacro("__tune_pentium_mmx__");
3621 defineCPUMacros(Builder, "i586");
3622 defineCPUMacros(Builder, "pentium");
3627 Builder.defineMacro("__tune_pentium3__");
3631 Builder.defineMacro("__tune_pentium2__");
3634 Builder.defineMacro("__tune_i686__");
3635 Builder.defineMacro("__tune_pentiumpro__");
3638 Builder.defineMacro("__i686");
3639 Builder.defineMacro("__i686__");
3640 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3641 Builder.defineMacro("__pentiumpro");
3642 Builder.defineMacro("__pentiumpro__");
3646 defineCPUMacros(Builder, "pentium4");
3651 defineCPUMacros(Builder, "nocona");
3655 defineCPUMacros(Builder, "core2");
3658 defineCPUMacros(Builder, "atom");
3661 defineCPUMacros(Builder, "slm");
3665 case CK_SandyBridge:
3669 case CK_SkylakeClient:
3670 // FIXME: Historically, we defined this legacy name, it would be nice to
3671 // remove it at some point. We've never exposed fine-grained names for
3672 // recent primary x86 CPUs, and we should keep it that way.
3673 defineCPUMacros(Builder, "corei7");
3675 case CK_SkylakeServer:
3676 defineCPUMacros(Builder, "skx");
3681 defineCPUMacros(Builder, "knl");
3684 Builder.defineMacro("__tune_lakemont__");
3687 Builder.defineMacro("__k6_2__");
3688 Builder.defineMacro("__tune_k6_2__");
3691 if (CPU != CK_K6_2) { // In case of fallthrough
3692 // FIXME: GCC may be enabling these in cases where some other k6
3693 // architecture is specified but -m3dnow is explicitly provided. The
3694 // exact semantics need to be determined and emulated here.
3695 Builder.defineMacro("__k6_3__");
3696 Builder.defineMacro("__tune_k6_3__");
3700 defineCPUMacros(Builder, "k6");
3703 case CK_AthlonThunderbird:
3707 defineCPUMacros(Builder, "athlon");
3708 if (SSELevel != NoSSE) {
3709 Builder.defineMacro("__athlon_sse__");
3710 Builder.defineMacro("__tune_athlon_sse__");
3717 case CK_OpteronSSE3:
3719 case CK_Athlon64SSE3:
3721 defineCPUMacros(Builder, "k8");
3724 defineCPUMacros(Builder, "amdfam10");
3727 defineCPUMacros(Builder, "btver1");
3730 defineCPUMacros(Builder, "btver2");
3733 defineCPUMacros(Builder, "bdver1");
3736 defineCPUMacros(Builder, "bdver2");
3739 defineCPUMacros(Builder, "bdver3");
3742 defineCPUMacros(Builder, "bdver4");
3745 defineCPUMacros(Builder, "geode");
3749 // Target properties.
3750 Builder.defineMacro("__REGISTER_PREFIX__", "");
3752 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3753 // functions in glibc header files that use FP Stack inline asm which the
3754 // backend can't deal with (PR879).
3755 Builder.defineMacro("__NO_MATH_INLINES");
3758 Builder.defineMacro("__AES__");
3761 Builder.defineMacro("__PCLMUL__");
3764 Builder.defineMacro("__LZCNT__");
3767 Builder.defineMacro("__RDRND__");
3770 Builder.defineMacro("__FSGSBASE__");
3773 Builder.defineMacro("__BMI__");
3776 Builder.defineMacro("__BMI2__");
3779 Builder.defineMacro("__POPCNT__");
3782 Builder.defineMacro("__RTM__");
3785 Builder.defineMacro("__PRFCHW__");
3788 Builder.defineMacro("__RDSEED__");
3791 Builder.defineMacro("__ADX__");
3794 Builder.defineMacro("__TBM__");
3797 Builder.defineMacro("__MWAITX__");
3801 Builder.defineMacro("__XOP__");
3803 Builder.defineMacro("__FMA4__");
3805 Builder.defineMacro("__SSE4A__");
3811 Builder.defineMacro("__FMA__");
3814 Builder.defineMacro("__F16C__");
3817 Builder.defineMacro("__AVX512CD__");
3819 Builder.defineMacro("__AVX512ER__");
3821 Builder.defineMacro("__AVX512PF__");
3823 Builder.defineMacro("__AVX512DQ__");
3825 Builder.defineMacro("__AVX512BW__");
3827 Builder.defineMacro("__AVX512VL__");
3829 Builder.defineMacro("__AVX512VBMI__");
3831 Builder.defineMacro("__AVX512IFMA__");
3834 Builder.defineMacro("__SHA__");
3837 Builder.defineMacro("__FXSR__");
3839 Builder.defineMacro("__XSAVE__");
3841 Builder.defineMacro("__XSAVEOPT__");
3843 Builder.defineMacro("__XSAVEC__");
3845 Builder.defineMacro("__XSAVES__");
3847 Builder.defineMacro("__PKU__");
3849 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3851 // Each case falls through to the previous one here.
3854 Builder.defineMacro("__AVX512F__");
3856 Builder.defineMacro("__AVX2__");
3858 Builder.defineMacro("__AVX__");
3860 Builder.defineMacro("__SSE4_2__");
3862 Builder.defineMacro("__SSE4_1__");
3864 Builder.defineMacro("__SSSE3__");
3866 Builder.defineMacro("__SSE3__");
3868 Builder.defineMacro("__SSE2__");
3869 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
3871 Builder.defineMacro("__SSE__");
3872 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
3877 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3887 Builder.defineMacro("_M_IX86_FP", Twine(2));
3890 Builder.defineMacro("_M_IX86_FP", Twine(1));
3893 Builder.defineMacro("_M_IX86_FP", Twine(0));
3897 // Each case falls through to the previous one here.
3898 switch (MMX3DNowLevel) {
3899 case AMD3DNowAthlon:
3900 Builder.defineMacro("__3dNOW_A__");
3902 Builder.defineMacro("__3dNOW__");
3904 Builder.defineMacro("__MMX__");
3909 if (CPU >= CK_i486) {
3910 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3911 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3912 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3915 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3918 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3919 return llvm::StringSwitch<bool>(Feature)
3920 .Case("aes", HasAES)
3921 .Case("avx", SSELevel >= AVX)
3922 .Case("avx2", SSELevel >= AVX2)
3923 .Case("avx512f", SSELevel >= AVX512F)
3924 .Case("avx512cd", HasAVX512CD)
3925 .Case("avx512er", HasAVX512ER)
3926 .Case("avx512pf", HasAVX512PF)
3927 .Case("avx512dq", HasAVX512DQ)
3928 .Case("avx512bw", HasAVX512BW)
3929 .Case("avx512vl", HasAVX512VL)
3930 .Case("avx512vbmi", HasAVX512VBMI)
3931 .Case("avx512ifma", HasAVX512IFMA)
3932 .Case("bmi", HasBMI)
3933 .Case("bmi2", HasBMI2)
3934 .Case("clflushopt", HasCLFLUSHOPT)
3935 .Case("clwb", HasCLWB)
3936 .Case("cx16", HasCX16)
3937 .Case("f16c", HasF16C)
3938 .Case("fma", HasFMA)
3939 .Case("fma4", XOPLevel >= FMA4)
3940 .Case("fsgsbase", HasFSGSBASE)
3941 .Case("fxsr", HasFXSR)
3942 .Case("lzcnt", HasLZCNT)
3943 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3944 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3945 .Case("mmx", MMX3DNowLevel >= MMX)
3946 .Case("movbe", HasMOVBE)
3947 .Case("mpx", HasMPX)
3948 .Case("pclmul", HasPCLMUL)
3949 .Case("pcommit", HasPCOMMIT)
3950 .Case("pku", HasPKU)
3951 .Case("popcnt", HasPOPCNT)
3952 .Case("prefetchwt1", HasPREFETCHWT1)
3953 .Case("prfchw", HasPRFCHW)
3954 .Case("rdrnd", HasRDRND)
3955 .Case("rdseed", HasRDSEED)
3956 .Case("rtm", HasRTM)
3957 .Case("sgx", HasSGX)
3958 .Case("sha", HasSHA)
3959 .Case("sse", SSELevel >= SSE1)
3960 .Case("sse2", SSELevel >= SSE2)
3961 .Case("sse3", SSELevel >= SSE3)
3962 .Case("ssse3", SSELevel >= SSSE3)
3963 .Case("sse4.1", SSELevel >= SSE41)
3964 .Case("sse4.2", SSELevel >= SSE42)
3965 .Case("sse4a", XOPLevel >= SSE4A)
3966 .Case("tbm", HasTBM)
3967 .Case("umip", HasUMIP)
3969 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3970 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3971 .Case("xop", XOPLevel >= XOP)
3972 .Case("xsave", HasXSAVE)
3973 .Case("xsavec", HasXSAVEC)
3974 .Case("xsaves", HasXSAVES)
3975 .Case("xsaveopt", HasXSAVEOPT)
3979 // We can't use a generic validation scheme for the features accepted here
3980 // versus subtarget features accepted in the target attribute because the
3981 // bitfield structure that's initialized in the runtime only supports the
3982 // below currently rather than the full range of subtarget features. (See
3983 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
3984 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
3985 return llvm::StringSwitch<bool>(FeatureStr)
3988 .Case("popcnt", true)
3992 .Case("ssse3", true)
3993 .Case("sse4.1", true)
3994 .Case("sse4.2", true)
3997 .Case("sse4a", true)
4001 .Case("avx512f", true)
4005 .Case("pclmul", true)
4006 .Case("avx512vl", true)
4007 .Case("avx512bw", true)
4008 .Case("avx512dq", true)
4009 .Case("avx512cd", true)
4010 .Case("avx512er", true)
4011 .Case("avx512pf", true)
4012 .Case("avx512vbmi", true)
4013 .Case("avx512ifma", true)
4018 X86TargetInfo::validateAsmConstraint(const char *&Name,
4019 TargetInfo::ConstraintInfo &Info) const {
4021 default: return false;
4022 // Constant constraints.
4023 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
4025 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
4026 // x86_64 instructions.
4028 Info.setRequiresImmediate();
4031 Info.setRequiresImmediate(0, 31);
4034 Info.setRequiresImmediate(0, 63);
4037 Info.setRequiresImmediate(-128, 127);
4040 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) });
4043 Info.setRequiresImmediate(0, 3);
4046 Info.setRequiresImmediate(0, 255);
4049 Info.setRequiresImmediate(0, 127);
4051 // Register constraints.
4052 case 'Y': // 'Y' is the first character for several 2-character constraints.
4053 // Shift the pointer to the second character of the constraint.
4058 case '0': // First SSE register.
4059 case 't': // Any SSE register, when SSE2 is enabled.
4060 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
4061 case 'm': // Any MMX register, when inter-unit moves enabled.
4062 case 'k': // AVX512 arch mask registers: k1-k7.
4063 Info.setAllowsRegister();
4066 case 'f': // Any x87 floating point stack register.
4067 // Constraint 'f' cannot be used for output operands.
4068 if (Info.ConstraintStr[0] == '=')
4070 Info.setAllowsRegister();
4078 case 'A': // edx:eax.
4079 case 't': // Top of floating point stack.
4080 case 'u': // Second from top of floating point stack.
4081 case 'q': // Any register accessible as [r]l: a, b, c, and d.
4082 case 'y': // Any MMX register.
4083 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
4084 case 'x': // Any SSE register.
4085 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0
4086 // for intermideate k reg operations).
4087 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
4088 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
4089 case 'l': // "Index" registers: any general register that can be used as an
4090 // index in a base+index memory access.
4091 Info.setAllowsRegister();
4093 // Floating point constant constraints.
4094 case 'C': // SSE floating point constant.
4095 case 'G': // x87 floating point constant.
4100 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
4101 unsigned Size) const {
4102 // Strip off constraint modifiers.
4103 while (Constraint[0] == '=' ||
4104 Constraint[0] == '+' ||
4105 Constraint[0] == '&')
4106 Constraint = Constraint.substr(1);
4108 return validateOperandSize(Constraint, Size);
4111 bool X86TargetInfo::validateInputSize(StringRef Constraint,
4112 unsigned Size) const {
4113 return validateOperandSize(Constraint, Size);
4116 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
4117 unsigned Size) const {
4118 switch (Constraint[0]) {
4121 // Registers k0-k7 (AVX512) size limit is 64 bit.
4130 if (SSELevel >= AVX512F)
4131 // 512-bit zmm registers can be used if target supports AVX512F.
4132 return Size <= 512U;
4133 else if (SSELevel >= AVX)
4134 // 256-bit ymm registers can be used if target supports AVX.
4135 return Size <= 256U;
4136 return Size <= 128U;
4138 // 'Y' is the first character for several 2-character constraints.
4139 switch (Constraint[1]) {
4142 // 'Ym' is synonymous with 'y'.
4147 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
4148 if (SSELevel >= AVX512F)
4149 return Size <= 512U;
4150 else if (SSELevel >= AVX)
4151 return Size <= 256U;
4152 return SSELevel >= SSE2 && Size <= 128U;
4161 X86TargetInfo::convertConstraint(const char *&Constraint) const {
4162 switch (*Constraint) {
4163 case 'a': return std::string("{ax}");
4164 case 'b': return std::string("{bx}");
4165 case 'c': return std::string("{cx}");
4166 case 'd': return std::string("{dx}");
4167 case 'S': return std::string("{si}");
4168 case 'D': return std::string("{di}");
4169 case 'p': // address
4170 return std::string("im");
4171 case 't': // top of floating point stack.
4172 return std::string("{st}");
4173 case 'u': // second from top of floating point stack.
4174 return std::string("{st(1)}"); // second from top of floating point stack.
4176 switch (Constraint[1]) {
4178 // Break from inner switch and fall through (copy single char),
4179 // continue parsing after copying the current constraint into
4180 // the return string.
4183 // "^" hints llvm that this is a 2 letter constraint.
4184 // "Constraint++" is used to promote the string iterator
4185 // to the next constraint.
4186 return std::string("^") + std::string(Constraint++, 2);
4190 return std::string(1, *Constraint);
4194 // X86-32 generic target
4195 class X86_32TargetInfo : public X86TargetInfo {
4197 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4198 : X86TargetInfo(Triple, Opts) {
4199 DoubleAlign = LongLongAlign = 32;
4200 LongDoubleWidth = 96;
4201 LongDoubleAlign = 32;
4202 SuitableAlign = 128;
4203 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128");
4204 SizeType = UnsignedInt;
4205 PtrDiffType = SignedInt;
4206 IntPtrType = SignedInt;
4209 // Use fpret for all types.
4210 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
4211 (1 << TargetInfo::Double) |
4212 (1 << TargetInfo::LongDouble));
4214 // x86-32 has atomics up to 8 bytes
4215 // FIXME: Check that we actually have cmpxchg8b before setting
4216 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
4217 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4219 BuiltinVaListKind getBuiltinVaListKind() const override {
4220 return TargetInfo::CharPtrBuiltinVaList;
4223 int getEHDataRegisterNumber(unsigned RegNo) const override {
4224 if (RegNo == 0) return 0;
4225 if (RegNo == 1) return 2;
4228 bool validateOperandSize(StringRef Constraint,
4229 unsigned Size) const override {
4230 switch (Constraint[0]) {
4246 return X86TargetInfo::validateOperandSize(Constraint, Size);
4248 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4249 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
4250 Builtin::FirstTSBuiltin + 1);
4254 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
4256 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4257 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {}
4259 unsigned getFloatEvalMethod() const override {
4260 unsigned Major, Minor, Micro;
4261 getTriple().getOSVersion(Major, Minor, Micro);
4262 // New NetBSD uses the default rounding mode.
4263 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
4264 return X86_32TargetInfo::getFloatEvalMethod();
4265 // NetBSD before 6.99.26 defaults to "double" rounding.
4270 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
4272 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4273 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4274 SizeType = UnsignedLong;
4275 IntPtrType = SignedLong;
4276 PtrDiffType = SignedLong;
4280 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
4282 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4283 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4284 SizeType = UnsignedLong;
4285 IntPtrType = SignedLong;
4286 PtrDiffType = SignedLong;
4290 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
4292 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4293 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4294 LongDoubleWidth = 128;
4295 LongDoubleAlign = 128;
4296 SuitableAlign = 128;
4297 MaxVectorAlign = 256;
4298 // The watchOS simulator uses the builtin bool type for Objective-C.
4299 llvm::Triple T = llvm::Triple(Triple);
4301 UseSignedCharForObjCBool = false;
4302 SizeType = UnsignedLong;
4303 IntPtrType = SignedLong;
4304 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128");
4305 HasAlignMac68kSupport = true;
4308 bool handleTargetFeatures(std::vector<std::string> &Features,
4309 DiagnosticsEngine &Diags) override {
4310 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features,
4313 // We now know the features we have: we can decide how to align vectors.
4315 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4320 // x86-32 Windows target
4321 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
4323 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4324 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4325 WCharType = UnsignedShort;
4326 DoubleAlign = LongLongAlign = 64;
4328 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4329 resetDataLayout(IsWinCOFF
4330 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
4331 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4333 void getTargetDefines(const LangOptions &Opts,
4334 MacroBuilder &Builder) const override {
4335 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4339 // x86-32 Windows Visual Studio target
4340 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
4342 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple,
4343 const TargetOptions &Opts)
4344 : WindowsX86_32TargetInfo(Triple, Opts) {
4345 LongDoubleWidth = LongDoubleAlign = 64;
4346 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4348 void getTargetDefines(const LangOptions &Opts,
4349 MacroBuilder &Builder) const override {
4350 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4351 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
4352 // The value of the following reflects processor type.
4353 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
4354 // We lost the original triple, so we use the default.
4355 Builder.defineMacro("_M_IX86", "600");
4359 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4360 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang
4361 // supports __declspec natively under -fms-extensions, but we define a no-op
4362 // __declspec macro anyway for pre-processor compatibility.
4363 if (Opts.MicrosoftExt)
4364 Builder.defineMacro("__declspec", "__declspec");
4366 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
4368 if (!Opts.MicrosoftExt) {
4369 // Provide macros for all the calling convention keywords. Provide both
4370 // single and double underscore prefixed variants. These are available on
4371 // x64 as well as x86, even though they have no effect.
4372 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
4373 for (const char *CC : CCs) {
4374 std::string GCCSpelling = "__attribute__((__";
4376 GCCSpelling += "__))";
4377 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
4378 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
4383 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4384 Builder.defineMacro("__MSVCRT__");
4385 Builder.defineMacro("__MINGW32__");
4386 addCygMingDefines(Opts, Builder);
4389 // x86-32 MinGW target
4390 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
4392 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4393 : WindowsX86_32TargetInfo(Triple, Opts) {}
4394 void getTargetDefines(const LangOptions &Opts,
4395 MacroBuilder &Builder) const override {
4396 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4397 DefineStd(Builder, "WIN32", Opts);
4398 DefineStd(Builder, "WINNT", Opts);
4399 Builder.defineMacro("_X86_");
4400 addMinGWDefines(Opts, Builder);
4404 // x86-32 Cygwin target
4405 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
4407 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4408 : X86_32TargetInfo(Triple, Opts) {
4409 WCharType = UnsignedShort;
4410 DoubleAlign = LongLongAlign = 64;
4411 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4413 void getTargetDefines(const LangOptions &Opts,
4414 MacroBuilder &Builder) const override {
4415 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4416 Builder.defineMacro("_X86_");
4417 Builder.defineMacro("__CYGWIN__");
4418 Builder.defineMacro("__CYGWIN32__");
4419 addCygMingDefines(Opts, Builder);
4420 DefineStd(Builder, "unix", Opts);
4422 Builder.defineMacro("_GNU_SOURCE");
4426 // x86-32 Haiku target
4427 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> {
4429 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4430 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4432 void getTargetDefines(const LangOptions &Opts,
4433 MacroBuilder &Builder) const override {
4434 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4435 Builder.defineMacro("__INTEL__");
4439 // X86-32 MCU target
4440 class MCUX86_32TargetInfo : public X86_32TargetInfo {
4442 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4443 : X86_32TargetInfo(Triple, Opts) {
4444 LongDoubleWidth = 64;
4445 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4446 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32");
4447 WIntType = UnsignedInt;
4450 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4451 // On MCU we support only C calling convention.
4452 return CC == CC_C ? CCCR_OK : CCCR_Warning;
4455 void getTargetDefines(const LangOptions &Opts,
4456 MacroBuilder &Builder) const override {
4457 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4458 Builder.defineMacro("__iamcu");
4459 Builder.defineMacro("__iamcu__");
4462 bool allowsLargerPreferedTypeAlignment() const override {
4468 template<typename Target>
4469 class RTEMSTargetInfo : public OSTargetInfo<Target> {
4471 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4472 MacroBuilder &Builder) const override {
4473 // RTEMS defines; list based off of gcc output
4475 Builder.defineMacro("__rtems__");
4476 Builder.defineMacro("__ELF__");
4480 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4481 : OSTargetInfo<Target>(Triple, Opts) {
4482 switch (Triple.getArch()) {
4484 case llvm::Triple::x86:
4485 // this->MCountName = ".mcount";
4487 case llvm::Triple::mips:
4488 case llvm::Triple::mipsel:
4489 case llvm::Triple::ppc:
4490 case llvm::Triple::ppc64:
4491 case llvm::Triple::ppc64le:
4492 // this->MCountName = "_mcount";
4494 case llvm::Triple::arm:
4495 // this->MCountName = "__mcount";
4501 // x86-32 RTEMS target
4502 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
4504 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4505 : X86_32TargetInfo(Triple, Opts) {
4506 SizeType = UnsignedLong;
4507 IntPtrType = SignedLong;
4508 PtrDiffType = SignedLong;
4510 void getTargetDefines(const LangOptions &Opts,
4511 MacroBuilder &Builder) const override {
4512 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4513 Builder.defineMacro("__INTEL__");
4514 Builder.defineMacro("__rtems__");
4518 // x86-64 generic target
4519 class X86_64TargetInfo : public X86TargetInfo {
4521 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4522 : X86TargetInfo(Triple, Opts) {
4523 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
4525 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4526 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
4527 LongDoubleWidth = 128;
4528 LongDoubleAlign = 128;
4529 LargeArrayMinWidth = 128;
4530 LargeArrayAlign = 128;
4531 SuitableAlign = 128;
4532 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
4533 PtrDiffType = IsX32 ? SignedInt : SignedLong;
4534 IntPtrType = IsX32 ? SignedInt : SignedLong;
4535 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
4536 Int64Type = IsX32 ? SignedLongLong : SignedLong;
4539 // Pointers are 32-bit in x32.
4540 resetDataLayout(IsX32
4541 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
4542 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
4543 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128");
4545 // Use fpret only for long double.
4546 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
4548 // Use fp2ret for _Complex long double.
4549 ComplexLongDoubleUsesFP2Ret = true;
4551 // Make __builtin_ms_va_list available.
4552 HasBuiltinMSVaList = true;
4554 // x86-64 has atomics up to 16 bytes.
4555 MaxAtomicPromoteWidth = 128;
4556 MaxAtomicInlineWidth = 128;
4558 BuiltinVaListKind getBuiltinVaListKind() const override {
4559 return TargetInfo::X86_64ABIBuiltinVaList;
4562 int getEHDataRegisterNumber(unsigned RegNo) const override {
4563 if (RegNo == 0) return 0;
4564 if (RegNo == 1) return 1;
4568 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4572 case CC_X86VectorCall:
4573 case CC_IntelOclBicc:
4574 case CC_X86_64Win64:
4575 case CC_PreserveMost:
4576 case CC_PreserveAll:
4580 return CCCR_Warning;
4584 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
4588 // for x32 we need it here explicitly
4589 bool hasInt128Type() const override { return true; }
4590 unsigned getUnwindWordWidth() const override { return 64; }
4591 unsigned getRegisterWidth() const override { return 64; }
4593 bool validateGlobalRegisterVariable(StringRef RegName,
4595 bool &HasSizeMismatch) const override {
4596 // rsp and rbp are the only 64-bit registers the x86 backend can currently
4598 if (RegName.equals("rsp") || RegName.equals("rbp")) {
4599 // Check that the register size is 64-bit.
4600 HasSizeMismatch = RegSize != 64;
4604 // Check if the register is a 32-bit register the backend can handle.
4605 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize,
4608 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4609 return llvm::makeArrayRef(BuiltinInfoX86,
4610 X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
4614 // x86-64 Windows target
4615 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
4617 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4618 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4619 WCharType = UnsignedShort;
4620 LongWidth = LongAlign = 32;
4621 DoubleAlign = LongLongAlign = 64;
4622 IntMaxType = SignedLongLong;
4623 Int64Type = SignedLongLong;
4624 SizeType = UnsignedLongLong;
4625 PtrDiffType = SignedLongLong;
4626 IntPtrType = SignedLongLong;
4629 void getTargetDefines(const LangOptions &Opts,
4630 MacroBuilder &Builder) const override {
4631 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
4632 Builder.defineMacro("_WIN64");
4635 BuiltinVaListKind getBuiltinVaListKind() const override {
4636 return TargetInfo::CharPtrBuiltinVaList;
4639 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4642 case CC_X86ThisCall:
4643 case CC_X86FastCall:
4646 case CC_X86VectorCall:
4647 case CC_IntelOclBicc:
4653 return CCCR_Warning;
4658 // x86-64 Windows Visual Studio target
4659 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
4661 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple,
4662 const TargetOptions &Opts)
4663 : WindowsX86_64TargetInfo(Triple, Opts) {
4664 LongDoubleWidth = LongDoubleAlign = 64;
4665 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4667 void getTargetDefines(const LangOptions &Opts,
4668 MacroBuilder &Builder) const override {
4669 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4670 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
4671 Builder.defineMacro("_M_X64", "100");
4672 Builder.defineMacro("_M_AMD64", "100");
4676 // x86-64 MinGW target
4677 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
4679 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4680 : WindowsX86_64TargetInfo(Triple, Opts) {
4681 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
4682 // with x86 FP ops. Weird.
4683 LongDoubleWidth = LongDoubleAlign = 128;
4684 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
4687 void getTargetDefines(const LangOptions &Opts,
4688 MacroBuilder &Builder) const override {
4689 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4690 DefineStd(Builder, "WIN64", Opts);
4691 Builder.defineMacro("__MINGW64__");
4692 addMinGWDefines(Opts, Builder);
4694 // GCC defines this macro when it is using __gxx_personality_seh0.
4695 if (!Opts.SjLjExceptions)
4696 Builder.defineMacro("__SEH__");
4700 // x86-64 Cygwin target
4701 class CygwinX86_64TargetInfo : public X86_64TargetInfo {
4703 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4704 : X86_64TargetInfo(Triple, Opts) {
4705 TLSSupported = false;
4706 WCharType = UnsignedShort;
4708 void getTargetDefines(const LangOptions &Opts,
4709 MacroBuilder &Builder) const override {
4710 X86_64TargetInfo::getTargetDefines(Opts, Builder);
4711 Builder.defineMacro("__x86_64__");
4712 Builder.defineMacro("__CYGWIN__");
4713 Builder.defineMacro("__CYGWIN64__");
4714 addCygMingDefines(Opts, Builder);
4715 DefineStd(Builder, "unix", Opts);
4717 Builder.defineMacro("_GNU_SOURCE");
4719 // GCC defines this macro when it is using __gxx_personality_seh0.
4720 if (!Opts.SjLjExceptions)
4721 Builder.defineMacro("__SEH__");
4725 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
4727 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4728 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4729 Int64Type = SignedLongLong;
4730 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
4731 llvm::Triple T = llvm::Triple(Triple);
4733 UseSignedCharForObjCBool = false;
4734 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128");
4737 bool handleTargetFeatures(std::vector<std::string> &Features,
4738 DiagnosticsEngine &Diags) override {
4739 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features,
4742 // We now know the features we have: we can decide how to align vectors.
4744 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4749 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
4751 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4752 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4753 IntMaxType = SignedLongLong;
4754 Int64Type = SignedLongLong;
4758 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
4760 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4761 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4762 IntMaxType = SignedLongLong;
4763 Int64Type = SignedLongLong;
4767 class ARMTargetInfo : public TargetInfo {
4768 // Possible FPU choices.
4777 // Possible HWDiv features.
4779 HWDivThumb = (1 << 0),
4783 static bool FPUModeIsVFP(FPUMode Mode) {
4784 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
4787 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4788 static const char * const GCCRegNames[];
4790 std::string ABI, CPU;
4792 StringRef CPUProfile;
4802 unsigned ArchKind = llvm::ARM::AK_ARMV4T;
4803 unsigned ArchProfile;
4804 unsigned ArchVersion;
4808 unsigned IsAAPCS : 1;
4811 // Initialized via features.
4812 unsigned SoftFloat : 1;
4813 unsigned SoftFloatABI : 1;
4816 unsigned Crypto : 1;
4818 unsigned Unaligned : 1;
4821 LDREX_B = (1 << 0), /// byte (8-bit)
4822 LDREX_H = (1 << 1), /// half (16-bit)
4823 LDREX_W = (1 << 2), /// word (32-bit)
4824 LDREX_D = (1 << 3), /// double (64-bit)
4829 // ACLE 6.5.1 Hardware floating point
4831 HW_FP_HP = (1 << 1), /// half (16-bit)
4832 HW_FP_SP = (1 << 2), /// single (32-bit)
4833 HW_FP_DP = (1 << 3), /// double (64-bit)
4837 static const Builtin::Info BuiltinInfo[];
4839 void setABIAAPCS() {
4842 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4843 const llvm::Triple &T = getTriple();
4845 // size_t is unsigned long on MachO-derived environments, NetBSD,
4846 // OpenBSD and Bitrig.
4847 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
4848 T.getOS() == llvm::Triple::OpenBSD ||
4849 T.getOS() == llvm::Triple::Bitrig)
4850 SizeType = UnsignedLong;
4852 SizeType = UnsignedInt;
4854 switch (T.getOS()) {
4855 case llvm::Triple::NetBSD:
4856 case llvm::Triple::OpenBSD:
4857 WCharType = SignedInt;
4859 case llvm::Triple::Win32:
4860 WCharType = UnsignedShort;
4862 case llvm::Triple::Linux:
4864 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
4865 WCharType = UnsignedInt;
4869 UseBitFieldTypeAlignment = true;
4871 ZeroLengthBitfieldBoundary = 0;
4873 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
4874 // so set preferred for small types to 32.
4875 if (T.isOSBinFormatMachO()) {
4876 resetDataLayout(BigEndian
4877 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4878 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
4879 } else if (T.isOSWindows()) {
4880 assert(!BigEndian && "Windows on ARM does not support big endian");
4889 } else if (T.isOSNaCl()) {
4890 assert(!BigEndian && "NaCl on ARM does not support big endian");
4891 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128");
4893 resetDataLayout(BigEndian
4894 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4895 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
4898 // FIXME: Enumerated types are variable width in straight AAPCS.
4901 void setABIAPCS(bool IsAAPCS16) {
4902 const llvm::Triple &T = getTriple();
4907 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4909 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
4911 // size_t is unsigned int on FreeBSD.
4912 if (T.getOS() == llvm::Triple::FreeBSD)
4913 SizeType = UnsignedInt;
4915 SizeType = UnsignedLong;
4917 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
4918 WCharType = SignedInt;
4920 // Do not respect the alignment of bit-field types when laying out
4921 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
4922 UseBitFieldTypeAlignment = false;
4924 /// gcc forces the alignment to 4 bytes, regardless of the type of the
4925 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
4927 ZeroLengthBitfieldBoundary = 32;
4929 if (T.isOSBinFormatMachO() && IsAAPCS16) {
4930 assert(!BigEndian && "AAPCS16 does not support big-endian");
4931 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128");
4932 } else if (T.isOSBinFormatMachO())
4935 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4936 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
4940 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4941 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
4943 // FIXME: Override "preferred align" for double and long long.
4946 void setArchInfo() {
4947 StringRef ArchName = getTriple().getArchName();
4949 ArchISA = llvm::ARM::parseArchISA(ArchName);
4950 CPU = llvm::ARM::getDefaultCPU(ArchName);
4951 unsigned AK = llvm::ARM::parseArch(ArchName);
4952 if (AK != llvm::ARM::AK_INVALID)
4954 setArchInfo(ArchKind);
4957 void setArchInfo(unsigned Kind) {
4960 // cache TargetParser info
4962 SubArch = llvm::ARM::getSubArch(ArchKind);
4963 ArchProfile = llvm::ARM::parseArchProfile(SubArch);
4964 ArchVersion = llvm::ARM::parseArchVersion(SubArch);
4966 // cache CPU related strings
4967 CPUAttr = getCPUAttr();
4968 CPUProfile = getCPUProfile();
4972 // when triple does not specify a sub arch,
4973 // then we are not using inline atomics
4974 bool ShouldUseInlineAtomic =
4975 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) ||
4976 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
4977 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4978 if (ArchProfile == llvm::ARM::PK_M) {
4979 MaxAtomicPromoteWidth = 32;
4980 if (ShouldUseInlineAtomic)
4981 MaxAtomicInlineWidth = 32;
4984 MaxAtomicPromoteWidth = 64;
4985 if (ShouldUseInlineAtomic)
4986 MaxAtomicInlineWidth = 64;
4990 bool isThumb() const {
4991 return (ArchISA == llvm::ARM::IK_THUMB);
4994 bool supportsThumb() const {
4995 return CPUAttr.count('T') || ArchVersion >= 6;
4998 bool supportsThumb2() const {
4999 return CPUAttr.equals("6T2") ||
5000 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE"));
5003 StringRef getCPUAttr() const {
5004 // For most sub-arches, the build attribute CPU name is enough.
5005 // For Cortex variants, it's slightly different.
5008 return llvm::ARM::getCPUAttr(ArchKind);
5009 case llvm::ARM::AK_ARMV6M:
5011 case llvm::ARM::AK_ARMV7S:
5013 case llvm::ARM::AK_ARMV7A:
5015 case llvm::ARM::AK_ARMV7R:
5017 case llvm::ARM::AK_ARMV7M:
5019 case llvm::ARM::AK_ARMV7EM:
5021 case llvm::ARM::AK_ARMV8A:
5023 case llvm::ARM::AK_ARMV8_1A:
5025 case llvm::ARM::AK_ARMV8_2A:
5027 case llvm::ARM::AK_ARMV8MBaseline:
5029 case llvm::ARM::AK_ARMV8MMainline:
5031 case llvm::ARM::AK_ARMV8R:
5036 StringRef getCPUProfile() const {
5037 switch(ArchProfile) {
5038 case llvm::ARM::PK_A:
5040 case llvm::ARM::PK_R:
5042 case llvm::ARM::PK_M:
5050 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5051 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0),
5054 switch (getTriple().getOS()) {
5055 case llvm::Triple::NetBSD:
5056 case llvm::Triple::OpenBSD:
5057 PtrDiffType = SignedLong;
5060 PtrDiffType = SignedInt;
5064 // Cache arch related info.
5067 // {} in inline assembly are neon specifiers, not assembly variant
5069 NoAsmVariants = true;
5071 // FIXME: This duplicates code from the driver that sets the -target-abi
5072 // option - this code is used if -target-abi isn't passed and should
5073 // be unified in some way.
5074 if (Triple.isOSBinFormatMachO()) {
5075 // The backend is hardwired to assume AAPCS for M-class processors, ensure
5076 // the frontend matches that.
5077 if (Triple.getEnvironment() == llvm::Triple::EABI ||
5078 Triple.getOS() == llvm::Triple::UnknownOS ||
5079 ArchProfile == llvm::ARM::PK_M) {
5081 } else if (Triple.isWatchABI()) {
5086 } else if (Triple.isOSWindows()) {
5087 // FIXME: this is invalid for WindowsCE
5090 // Select the default based on the platform.
5091 switch (Triple.getEnvironment()) {
5092 case llvm::Triple::Android:
5093 case llvm::Triple::GNUEABI:
5094 case llvm::Triple::GNUEABIHF:
5095 case llvm::Triple::MuslEABI:
5096 case llvm::Triple::MuslEABIHF:
5097 setABI("aapcs-linux");
5099 case llvm::Triple::EABIHF:
5100 case llvm::Triple::EABI:
5103 case llvm::Triple::GNU:
5107 if (Triple.getOS() == llvm::Triple::NetBSD)
5115 // ARM targets default to using the ARM C++ ABI.
5116 TheCXXABI.set(TargetCXXABI::GenericARM);
5118 // ARM has atomics up to 8 bytes
5121 // Do force alignment of members that follow zero length bitfields. If
5122 // the alignment of the zero-length bitfield is greater than the member
5123 // that follows it, `bar', `bar' will be aligned as the type of the
5124 // zero length bitfield.
5125 UseZeroLengthBitfieldAlignment = true;
5127 if (Triple.getOS() == llvm::Triple::Linux ||
5128 Triple.getOS() == llvm::Triple::UnknownOS)
5130 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount";
5133 StringRef getABI() const override { return ABI; }
5135 bool setABI(const std::string &Name) override {
5138 // The defaults (above) are for AAPCS, check if we need to change them.
5140 // FIXME: We need support for -meabi... we could just mangle it into the
5142 if (Name == "apcs-gnu" || Name == "aapcs16") {
5143 setABIAPCS(Name == "aapcs16");
5146 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
5153 // FIXME: This should be based on Arch attributes, not CPU names.
5155 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
5157 const std::vector<std::string> &FeaturesVec) const override {
5159 std::vector<StringRef> TargetFeatures;
5160 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName());
5162 // get default FPU features
5163 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
5164 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
5166 // get default Extension features
5167 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
5168 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
5170 for (auto Feature : TargetFeatures)
5171 if (Feature[0] == '+')
5172 Features[Feature.drop_front(1)] = true;
5174 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
5177 bool handleTargetFeatures(std::vector<std::string> &Features,
5178 DiagnosticsEngine &Diags) override {
5184 SoftFloat = SoftFloatABI = false;
5187 // This does not diagnose illegal cases like having both
5188 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
5189 uint32_t HW_FP_remove = 0;
5190 for (const auto &Feature : Features) {
5191 if (Feature == "+soft-float") {
5193 } else if (Feature == "+soft-float-abi") {
5194 SoftFloatABI = true;
5195 } else if (Feature == "+vfp2") {
5197 HW_FP |= HW_FP_SP | HW_FP_DP;
5198 } else if (Feature == "+vfp3") {
5200 HW_FP |= HW_FP_SP | HW_FP_DP;
5201 } else if (Feature == "+vfp4") {
5203 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
5204 } else if (Feature == "+fp-armv8") {
5206 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
5207 } else if (Feature == "+neon") {
5209 HW_FP |= HW_FP_SP | HW_FP_DP;
5210 } else if (Feature == "+hwdiv") {
5211 HWDiv |= HWDivThumb;
5212 } else if (Feature == "+hwdiv-arm") {
5214 } else if (Feature == "+crc") {
5216 } else if (Feature == "+crypto") {
5218 } else if (Feature == "+dsp") {
5220 } else if (Feature == "+fp-only-sp") {
5221 HW_FP_remove |= HW_FP_DP;
5222 } else if (Feature == "+strict-align") {
5224 } else if (Feature == "+fp16") {
5228 HW_FP &= ~HW_FP_remove;
5230 switch (ArchVersion) {
5232 if (ArchProfile == llvm::ARM::PK_M)
5234 else if (ArchKind == llvm::ARM::AK_ARMV6K)
5235 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5240 if (ArchProfile == llvm::ARM::PK_M)
5241 LDREX = LDREX_W | LDREX_H | LDREX_B ;
5243 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5246 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5249 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
5250 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
5254 if (FPMath == FP_Neon)
5255 Features.push_back("+neonfp");
5256 else if (FPMath == FP_VFP)
5257 Features.push_back("-neonfp");
5259 // Remove front-end specific options which the backend handles differently.
5261 std::find(Features.begin(), Features.end(), "+soft-float-abi");
5262 if (Feature != Features.end())
5263 Features.erase(Feature);
5268 bool hasFeature(StringRef Feature) const override {
5269 return llvm::StringSwitch<bool>(Feature)
5271 .Case("aarch32", true)
5272 .Case("softfloat", SoftFloat)
5273 .Case("thumb", isThumb())
5274 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
5275 .Case("hwdiv", HWDiv & HWDivThumb)
5276 .Case("hwdiv-arm", HWDiv & HWDivARM)
5280 bool setCPU(const std::string &Name) override {
5281 if (Name != "generic")
5282 setArchInfo(llvm::ARM::parseCPUArch(Name));
5284 if (ArchKind == llvm::ARM::AK_INVALID)
5291 bool setFPMath(StringRef Name) override;
5293 void getTargetDefines(const LangOptions &Opts,
5294 MacroBuilder &Builder) const override {
5295 // Target identification.
5296 Builder.defineMacro("__arm");
5297 Builder.defineMacro("__arm__");
5298 // For bare-metal none-eabi.
5299 if (getTriple().getOS() == llvm::Triple::UnknownOS &&
5300 getTriple().getEnvironment() == llvm::Triple::EABI)
5301 Builder.defineMacro("__ELF__");
5303 // Target properties.
5304 Builder.defineMacro("__REGISTER_PREFIX__", "");
5306 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
5307 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
5308 if (getTriple().isWatchABI())
5309 Builder.defineMacro("__ARM_ARCH_7K__", "2");
5311 if (!CPUAttr.empty())
5312 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
5314 // ACLE 6.4.1 ARM/Thumb instruction set architecture
5315 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
5316 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
5318 if (ArchVersion >= 8) {
5319 // ACLE 6.5.7 Crypto Extension
5321 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
5322 // ACLE 6.5.8 CRC32 Extension
5324 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
5325 // ACLE 6.5.10 Numeric Maximum and Minimum
5326 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
5327 // ACLE 6.5.9 Directed Rounding
5328 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
5331 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
5332 // is not defined for the M-profile.
5333 // NOTE that the default profile is assumed to be 'A'
5334 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M)
5335 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
5337 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original
5338 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the
5339 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all
5340 // v7 and v8 architectures excluding v8-M Baseline.
5341 if (supportsThumb2())
5342 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
5343 else if (supportsThumb())
5344 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
5346 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
5347 // instruction set such as ARM or Thumb.
5348 Builder.defineMacro("__ARM_32BIT_STATE", "1");
5350 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
5352 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
5353 if (!CPUProfile.empty())
5354 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
5356 // ACLE 6.4.3 Unaligned access supported in hardware
5358 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
5360 // ACLE 6.4.4 LDREX/STREX
5362 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX));
5365 if (ArchVersion == 5 ||
5366 (ArchVersion == 6 && CPUProfile != "M") ||
5368 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
5370 // ACLE 6.5.1 Hardware Floating Point
5372 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
5375 Builder.defineMacro("__ARM_ACLE", "200");
5377 // FP16 support (we currently only support IEEE format).
5378 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
5379 Builder.defineMacro("__ARM_FP16_ARGS", "1");
5381 // ACLE 6.5.3 Fused multiply-accumulate (FMA)
5382 if (ArchVersion >= 7 && (FPU & VFP4FPU))
5383 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
5385 // Subtarget options.
5387 // FIXME: It's more complicated than this and we don't really support
5389 // Windows on ARM does not "support" interworking
5390 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows())
5391 Builder.defineMacro("__THUMB_INTERWORK__");
5393 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
5394 // Embedded targets on Darwin follow AAPCS, but not EABI.
5395 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
5396 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows())
5397 Builder.defineMacro("__ARM_EABI__");
5398 Builder.defineMacro("__ARM_PCS", "1");
5401 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" ||
5403 Builder.defineMacro("__ARM_PCS_VFP", "1");
5406 Builder.defineMacro("__SOFTFP__");
5408 if (ArchKind == llvm::ARM::AK_XSCALE)
5409 Builder.defineMacro("__XSCALE__");
5412 Builder.defineMacro("__THUMBEL__");
5413 Builder.defineMacro("__thumb__");
5414 if (supportsThumb2())
5415 Builder.defineMacro("__thumb2__");
5418 // ACLE 6.4.9 32-bit SIMD instructions
5419 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
5420 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
5422 // ACLE 6.4.10 Hardware Integer Divide
5423 if (((HWDiv & HWDivThumb) && isThumb()) ||
5424 ((HWDiv & HWDivARM) && !isThumb())) {
5425 Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
5426 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
5429 // Note, this is always on in gcc, even though it doesn't make sense.
5430 Builder.defineMacro("__APCS_32__");
5432 if (FPUModeIsVFP((FPUMode) FPU)) {
5433 Builder.defineMacro("__VFP_FP__");
5435 Builder.defineMacro("__ARM_VFPV2__");
5437 Builder.defineMacro("__ARM_VFPV3__");
5439 Builder.defineMacro("__ARM_VFPV4__");
5441 Builder.defineMacro("__ARM_FPV5__");
5444 // This only gets set when Neon instructions are actually available, unlike
5445 // the VFP define, hence the soft float and arch check. This is subtly
5446 // different from gcc, we follow the intent which was that it should be set
5447 // when Neon instructions are actually available.
5448 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
5449 Builder.defineMacro("__ARM_NEON", "1");
5450 Builder.defineMacro("__ARM_NEON__");
5451 // current AArch32 NEON implementations do not support double-precision
5452 // floating-point even when it is present in VFP.
5453 Builder.defineMacro("__ARM_NEON_FP",
5454 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP));
5457 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
5458 Opts.ShortWChar ? "2" : "4");
5460 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5461 Opts.ShortEnums ? "1" : "4");
5463 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") {
5464 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
5465 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
5466 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
5467 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
5470 // ACLE 6.4.7 DSP instructions
5472 Builder.defineMacro("__ARM_FEATURE_DSP", "1");
5475 // ACLE 6.4.8 Saturation instructions
5477 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) {
5478 Builder.defineMacro("__ARM_FEATURE_SAT", "1");
5482 // ACLE 6.4.6 Q (saturation) flag
5484 Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
5486 if (Opts.UnsafeFPMath)
5487 Builder.defineMacro("__ARM_FP_FAST", "1");
5489 if (ArchKind == llvm::ARM::AK_ARMV8_1A)
5490 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
5493 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5494 return llvm::makeArrayRef(BuiltinInfo,
5495 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin);
5497 bool isCLZForZeroUndef() const override { return false; }
5498 BuiltinVaListKind getBuiltinVaListKind() const override {
5500 ? AAPCSABIBuiltinVaList
5501 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList
5502 : TargetInfo::VoidPtrBuiltinVaList);
5504 ArrayRef<const char *> getGCCRegNames() const override;
5505 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5506 bool validateAsmConstraint(const char *&Name,
5507 TargetInfo::ConstraintInfo &Info) const override {
5512 case 't': // VFP Floating point register single precision
5513 case 'w': // VFP Floating point register double precision
5514 Info.setAllowsRegister();
5523 case 'Q': // A memory address that is a single base register.
5524 Info.setAllowsMemory();
5526 case 'U': // a memory reference...
5528 case 'q': // ...ARMV4 ldrsb
5529 case 'v': // ...VFP load/store (reg+constant offset)
5530 case 'y': // ...iWMMXt load/store
5531 case 't': // address valid for load/store opaque types wider
5533 case 'n': // valid address for Neon doubleword vector load/store
5534 case 'm': // valid address for Neon element and structure load/store
5535 case 's': // valid address for non-offset loads/stores of quad-word
5536 // values in four ARM registers
5537 Info.setAllowsMemory();
5544 std::string convertConstraint(const char *&Constraint) const override {
5546 switch (*Constraint) {
5547 case 'U': // Two-character constraint; add "^" hint for later parsing.
5548 R = std::string("^") + std::string(Constraint, 2);
5551 case 'p': // 'p' should be translated to 'r' by default.
5552 R = std::string("r");
5555 return std::string(1, *Constraint);
5560 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5561 std::string &SuggestedModifier) const override {
5562 bool isOutput = (Constraint[0] == '=');
5563 bool isInOut = (Constraint[0] == '+');
5565 // Strip off constraint modifiers.
5566 while (Constraint[0] == '=' ||
5567 Constraint[0] == '+' ||
5568 Constraint[0] == '&')
5569 Constraint = Constraint.substr(1);
5571 switch (Constraint[0]) {
5576 return (isInOut || isOutput || Size <= 64);
5578 // A register of size 32 cannot fit a vector type.
5586 const char *getClobbers() const override {
5587 // FIXME: Is this really right?
5591 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5598 return CCCR_Warning;
5602 int getEHDataRegisterNumber(unsigned RegNo) const override {
5603 if (RegNo == 0) return 0;
5604 if (RegNo == 1) return 1;
5608 bool hasSjLjLowering() const override {
5613 bool ARMTargetInfo::setFPMath(StringRef Name) {
5614 if (Name == "neon") {
5617 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
5625 const char * const ARMTargetInfo::GCCRegNames[] = {
5626 // Integer registers
5627 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5628 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
5631 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
5632 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
5633 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
5634 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5637 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
5638 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
5639 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
5640 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5643 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
5644 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
5647 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
5648 return llvm::makeArrayRef(GCCRegNames);
5651 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
5661 { { "v6", "rfp" }, "r9" },
5662 { { "sl" }, "r10" },
5663 { { "fp" }, "r11" },
5664 { { "ip" }, "r12" },
5665 { { "r13" }, "sp" },
5666 { { "r14" }, "lr" },
5667 { { "r15" }, "pc" },
5668 // The S, D and Q registers overlap, but aren't really aliases; we
5669 // don't want to substitute one of these for a different-sized one.
5672 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
5673 return llvm::makeArrayRef(GCCRegAliases);
5676 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
5677 #define BUILTIN(ID, TYPE, ATTRS) \
5678 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5679 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5680 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5681 #include "clang/Basic/BuiltinsNEON.def"
5683 #define BUILTIN(ID, TYPE, ATTRS) \
5684 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5685 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \
5686 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr },
5687 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5688 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5689 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
5690 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
5691 #include "clang/Basic/BuiltinsARM.def"
5694 class ARMleTargetInfo : public ARMTargetInfo {
5696 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5697 : ARMTargetInfo(Triple, Opts) {}
5698 void getTargetDefines(const LangOptions &Opts,
5699 MacroBuilder &Builder) const override {
5700 Builder.defineMacro("__ARMEL__");
5701 ARMTargetInfo::getTargetDefines(Opts, Builder);
5705 class ARMbeTargetInfo : public ARMTargetInfo {
5707 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5708 : ARMTargetInfo(Triple, Opts) {}
5709 void getTargetDefines(const LangOptions &Opts,
5710 MacroBuilder &Builder) const override {
5711 Builder.defineMacro("__ARMEB__");
5712 Builder.defineMacro("__ARM_BIG_ENDIAN");
5713 ARMTargetInfo::getTargetDefines(Opts, Builder);
5717 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
5718 const llvm::Triple Triple;
5720 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5721 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
5722 WCharType = UnsignedShort;
5723 SizeType = UnsignedInt;
5725 void getVisualStudioDefines(const LangOptions &Opts,
5726 MacroBuilder &Builder) const {
5727 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
5729 // FIXME: this is invalid for WindowsCE
5730 Builder.defineMacro("_M_ARM_NT", "1");
5731 Builder.defineMacro("_M_ARMT", "_M_ARM");
5732 Builder.defineMacro("_M_THUMB", "_M_ARM");
5734 assert((Triple.getArch() == llvm::Triple::arm ||
5735 Triple.getArch() == llvm::Triple::thumb) &&
5736 "invalid architecture for Windows ARM target info");
5737 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
5738 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
5740 // TODO map the complete set of values
5741 // 31: VFPv3 40: VFPv4
5742 Builder.defineMacro("_M_ARM_FP", "31");
5744 BuiltinVaListKind getBuiltinVaListKind() const override {
5745 return TargetInfo::CharPtrBuiltinVaList;
5747 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5750 case CC_X86ThisCall:
5751 case CC_X86FastCall:
5752 case CC_X86VectorCall:
5757 return CCCR_Warning;
5762 // Windows ARM + Itanium C++ ABI Target
5763 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
5765 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple,
5766 const TargetOptions &Opts)
5767 : WindowsARMTargetInfo(Triple, Opts) {
5768 TheCXXABI.set(TargetCXXABI::GenericARM);
5771 void getTargetDefines(const LangOptions &Opts,
5772 MacroBuilder &Builder) const override {
5773 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5775 if (Opts.MSVCCompat)
5776 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5780 // Windows ARM, MS (C++) ABI
5781 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
5783 MicrosoftARMleTargetInfo(const llvm::Triple &Triple,
5784 const TargetOptions &Opts)
5785 : WindowsARMTargetInfo(Triple, Opts) {
5786 TheCXXABI.set(TargetCXXABI::Microsoft);
5789 void getTargetDefines(const LangOptions &Opts,
5790 MacroBuilder &Builder) const override {
5791 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5792 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5797 class MinGWARMTargetInfo : public WindowsARMTargetInfo {
5799 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5800 : WindowsARMTargetInfo(Triple, Opts) {
5801 TheCXXABI.set(TargetCXXABI::GenericARM);
5804 void getTargetDefines(const LangOptions &Opts,
5805 MacroBuilder &Builder) const override {
5806 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5807 DefineStd(Builder, "WIN32", Opts);
5808 DefineStd(Builder, "WINNT", Opts);
5809 Builder.defineMacro("_ARM_");
5810 addMinGWDefines(Opts, Builder);
5814 // ARM Cygwin target
5815 class CygwinARMTargetInfo : public ARMleTargetInfo {
5817 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5818 : ARMleTargetInfo(Triple, Opts) {
5819 TLSSupported = false;
5820 WCharType = UnsignedShort;
5821 DoubleAlign = LongLongAlign = 64;
5822 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
5824 void getTargetDefines(const LangOptions &Opts,
5825 MacroBuilder &Builder) const override {
5826 ARMleTargetInfo::getTargetDefines(Opts, Builder);
5827 Builder.defineMacro("_ARM_");
5828 Builder.defineMacro("__CYGWIN__");
5829 Builder.defineMacro("__CYGWIN32__");
5830 DefineStd(Builder, "unix", Opts);
5832 Builder.defineMacro("_GNU_SOURCE");
5836 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> {
5838 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5839 MacroBuilder &Builder) const override {
5840 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5844 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5845 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
5846 HasAlignMac68kSupport = true;
5847 // iOS always has 64-bit atomic instructions.
5848 // FIXME: This should be based off of the target features in
5850 MaxAtomicInlineWidth = 64;
5852 if (Triple.isWatchABI()) {
5853 // Darwin on iOS uses a variant of the ARM C++ ABI.
5854 TheCXXABI.set(TargetCXXABI::WatchOS);
5856 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that
5857 // size_t is long, it's a bit weird for it to be int.
5858 PtrDiffType = SignedLong;
5860 // BOOL should be a real boolean on the new ABI
5861 UseSignedCharForObjCBool = false;
5863 TheCXXABI.set(TargetCXXABI::iOS);
5867 class AArch64TargetInfo : public TargetInfo {
5868 virtual void setDataLayout() = 0;
5869 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5870 static const char *const GCCRegNames[];
5883 static const Builtin::Info BuiltinInfo[];
5888 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5889 : TargetInfo(Triple), ABI("aapcs") {
5890 if (getTriple().getOS() == llvm::Triple::NetBSD) {
5891 WCharType = SignedInt;
5893 // NetBSD apparently prefers consistency across ARM targets to consistency
5894 // across 64-bit targets.
5895 Int64Type = SignedLongLong;
5896 IntMaxType = SignedLongLong;
5898 WCharType = UnsignedInt;
5899 Int64Type = SignedLong;
5900 IntMaxType = SignedLong;
5903 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5904 MaxVectorAlign = 128;
5905 MaxAtomicInlineWidth = 128;
5906 MaxAtomicPromoteWidth = 128;
5908 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
5909 LongDoubleFormat = &llvm::APFloat::IEEEquad();
5911 // {} in inline assembly are neon specifiers, not assembly variant
5913 NoAsmVariants = true;
5915 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
5916 // contributes to the alignment of the containing aggregate in the same way
5917 // a plain (non bit-field) member of that type would, without exception for
5918 // zero-sized or anonymous bit-fields."
5919 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
5920 UseZeroLengthBitfieldAlignment = true;
5922 // AArch64 targets default to using the ARM C++ ABI.
5923 TheCXXABI.set(TargetCXXABI::GenericAArch64);
5925 if (Triple.getOS() == llvm::Triple::Linux ||
5926 Triple.getOS() == llvm::Triple::UnknownOS)
5927 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount";
5930 StringRef getABI() const override { return ABI; }
5931 bool setABI(const std::string &Name) override {
5932 if (Name != "aapcs" && Name != "darwinpcs")
5939 bool setCPU(const std::string &Name) override {
5940 return Name == "generic" ||
5941 llvm::AArch64::parseCPUArch(Name) !=
5942 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID);
5945 void getTargetDefines(const LangOptions &Opts,
5946 MacroBuilder &Builder) const override {
5947 // Target identification.
5948 Builder.defineMacro("__aarch64__");
5950 // Target properties.
5951 Builder.defineMacro("_LP64");
5952 Builder.defineMacro("__LP64__");
5954 // ACLE predefines. Many can only have one possible value on v8 AArch64.
5955 Builder.defineMacro("__ARM_ACLE", "200");
5956 Builder.defineMacro("__ARM_ARCH", "8");
5957 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
5959 Builder.defineMacro("__ARM_64BIT_STATE", "1");
5960 Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
5961 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
5963 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
5964 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
5965 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
5966 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
5967 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
5968 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
5969 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
5971 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
5973 // 0xe implies support for half, single and double precision operations.
5974 Builder.defineMacro("__ARM_FP", "0xE");
5976 // PCS specifies this for SysV variants, which is all we support. Other ABIs
5977 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
5978 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
5979 Builder.defineMacro("__ARM_FP16_ARGS", "1");
5981 if (Opts.UnsafeFPMath)
5982 Builder.defineMacro("__ARM_FP_FAST", "1");
5984 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
5986 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5987 Opts.ShortEnums ? "1" : "4");
5989 if (FPU == NeonMode) {
5990 Builder.defineMacro("__ARM_NEON", "1");
5991 // 64-bit NEON supports half, single and double precision operations.
5992 Builder.defineMacro("__ARM_NEON_FP", "0xE");
5996 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
5999 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
6002 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
6005 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
6007 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
6008 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
6009 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
6010 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
6011 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
6014 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6015 return llvm::makeArrayRef(BuiltinInfo,
6016 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin);
6019 bool hasFeature(StringRef Feature) const override {
6020 return Feature == "aarch64" ||
6021 Feature == "arm64" ||
6023 (Feature == "neon" && FPU == NeonMode);
6026 bool handleTargetFeatures(std::vector<std::string> &Features,
6027 DiagnosticsEngine &Diags) override {
6034 for (const auto &Feature : Features) {
6035 if (Feature == "+neon")
6037 if (Feature == "+crc")
6039 if (Feature == "+crypto")
6041 if (Feature == "+strict-align")
6043 if (Feature == "+v8.1a")
6052 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6056 case CC_PreserveMost:
6057 case CC_PreserveAll:
6060 return CCCR_Warning;
6064 bool isCLZForZeroUndef() const override { return false; }
6066 BuiltinVaListKind getBuiltinVaListKind() const override {
6067 return TargetInfo::AArch64ABIBuiltinVaList;
6070 ArrayRef<const char *> getGCCRegNames() const override;
6071 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6073 bool validateAsmConstraint(const char *&Name,
6074 TargetInfo::ConstraintInfo &Info) const override {
6078 case 'w': // Floating point and SIMD registers (V0-V31)
6079 Info.setAllowsRegister();
6081 case 'I': // Constant that can be used with an ADD instruction
6082 case 'J': // Constant that can be used with a SUB instruction
6083 case 'K': // Constant that can be used with a 32-bit logical instruction
6084 case 'L': // Constant that can be used with a 64-bit logical instruction
6085 case 'M': // Constant that can be used as a 32-bit MOV immediate
6086 case 'N': // Constant that can be used as a 64-bit MOV immediate
6087 case 'Y': // Floating point constant zero
6088 case 'Z': // Integer constant zero
6090 case 'Q': // A memory reference with base register and no offset
6091 Info.setAllowsMemory();
6093 case 'S': // A symbolic address
6094 Info.setAllowsRegister();
6097 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
6098 // Utf: A memory address suitable for ldp/stp in TF mode.
6099 // Usa: An absolute symbolic address.
6100 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
6101 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
6102 case 'z': // Zero register, wzr or xzr
6103 Info.setAllowsRegister();
6105 case 'x': // Floating point and SIMD registers (V0-V15)
6106 Info.setAllowsRegister();
6113 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
6114 std::string &SuggestedModifier) const override {
6115 // Strip off constraint modifiers.
6116 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
6117 Constraint = Constraint.substr(1);
6119 switch (Constraint[0]) {
6127 // For now assume that the person knows what they're
6128 // doing with the modifier.
6131 // By default an 'r' constraint will be in the 'x'
6136 SuggestedModifier = "w";
6143 const char *getClobbers() const override { return ""; }
6145 int getEHDataRegisterNumber(unsigned RegNo) const override {
6154 const char *const AArch64TargetInfo::GCCRegNames[] = {
6155 // 32-bit Integer registers
6156 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
6157 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
6158 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
6160 // 64-bit Integer registers
6161 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
6162 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
6163 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
6165 // 32-bit floating point regsisters
6166 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
6167 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
6168 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
6170 // 64-bit floating point regsisters
6171 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
6172 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
6173 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
6176 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
6177 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
6178 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
6181 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
6182 return llvm::makeArrayRef(GCCRegNames);
6185 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
6186 { { "w31" }, "wsp" },
6187 { { "x29" }, "fp" },
6188 { { "x30" }, "lr" },
6189 { { "x31" }, "sp" },
6190 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
6191 // don't want to substitute one of these for a different-sized one.
6194 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
6195 return llvm::makeArrayRef(GCCRegAliases);
6198 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
6199 #define BUILTIN(ID, TYPE, ATTRS) \
6200 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6201 #include "clang/Basic/BuiltinsNEON.def"
6203 #define BUILTIN(ID, TYPE, ATTRS) \
6204 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6205 #include "clang/Basic/BuiltinsAArch64.def"
6208 class AArch64leTargetInfo : public AArch64TargetInfo {
6209 void setDataLayout() override {
6210 if (getTriple().isOSBinFormatMachO())
6211 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128");
6213 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6217 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6218 : AArch64TargetInfo(Triple, Opts) {
6220 void getTargetDefines(const LangOptions &Opts,
6221 MacroBuilder &Builder) const override {
6222 Builder.defineMacro("__AARCH64EL__");
6223 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6227 class AArch64beTargetInfo : public AArch64TargetInfo {
6228 void setDataLayout() override {
6229 assert(!getTriple().isOSBinFormatMachO());
6230 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6234 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6235 : AArch64TargetInfo(Triple, Opts) {}
6236 void getTargetDefines(const LangOptions &Opts,
6237 MacroBuilder &Builder) const override {
6238 Builder.defineMacro("__AARCH64EB__");
6239 Builder.defineMacro("__AARCH_BIG_ENDIAN");
6240 Builder.defineMacro("__ARM_BIG_ENDIAN");
6241 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6245 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
6247 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
6248 MacroBuilder &Builder) const override {
6249 Builder.defineMacro("__AARCH64_SIMD__");
6250 Builder.defineMacro("__ARM64_ARCH_8__");
6251 Builder.defineMacro("__ARM_NEON__");
6252 Builder.defineMacro("__LITTLE_ENDIAN__");
6253 Builder.defineMacro("__REGISTER_PREFIX__", "");
6254 Builder.defineMacro("__arm64", "1");
6255 Builder.defineMacro("__arm64__", "1");
6257 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
6261 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6262 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
6263 Int64Type = SignedLongLong;
6264 WCharType = SignedInt;
6265 UseSignedCharForObjCBool = false;
6267 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
6268 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
6270 TheCXXABI.set(TargetCXXABI::iOS64);
6273 BuiltinVaListKind getBuiltinVaListKind() const override {
6274 return TargetInfo::CharPtrBuiltinVaList;
6278 // Hexagon abstract base class
6279 class HexagonTargetInfo : public TargetInfo {
6280 static const Builtin::Info BuiltinInfo[];
6281 static const char * const GCCRegNames[];
6282 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6284 bool HasHVX, HasHVXDouble;
6288 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6289 : TargetInfo(Triple) {
6290 // Specify the vector alignment explicitly. For v512x1, the calculated
6291 // alignment would be 512*alignment(i1), which is 512 bytes, instead of
6292 // the required minimum of 64 bytes.
6293 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-"
6294 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
6295 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048");
6296 SizeType = UnsignedInt;
6297 PtrDiffType = SignedInt;
6298 IntPtrType = SignedInt;
6300 // {} in inline assembly are packet specifiers, not assembly variant
6302 NoAsmVariants = true;
6304 LargeArrayMinWidth = 64;
6305 LargeArrayAlign = 64;
6306 UseBitFieldTypeAlignment = true;
6307 ZeroLengthBitfieldBoundary = 32;
6308 HasHVX = HasHVXDouble = false;
6309 UseLongCalls = false;
6312 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6313 return llvm::makeArrayRef(BuiltinInfo,
6314 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin);
6317 bool validateAsmConstraint(const char *&Name,
6318 TargetInfo::ConstraintInfo &Info) const override {
6323 Info.setAllowsRegister();
6328 // Relocatable constant.
6334 void getTargetDefines(const LangOptions &Opts,
6335 MacroBuilder &Builder) const override;
6337 bool isCLZForZeroUndef() const override { return false; }
6339 bool hasFeature(StringRef Feature) const override {
6340 return llvm::StringSwitch<bool>(Feature)
6341 .Case("hexagon", true)
6342 .Case("hvx", HasHVX)
6343 .Case("hvx-double", HasHVXDouble)
6344 .Case("long-calls", UseLongCalls)
6348 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6349 StringRef CPU, const std::vector<std::string> &FeaturesVec)
6352 bool handleTargetFeatures(std::vector<std::string> &Features,
6353 DiagnosticsEngine &Diags) override;
6355 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
6356 bool Enabled) const override;
6358 BuiltinVaListKind getBuiltinVaListKind() const override {
6359 return TargetInfo::CharPtrBuiltinVaList;
6361 ArrayRef<const char *> getGCCRegNames() const override;
6362 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6363 const char *getClobbers() const override {
6367 static const char *getHexagonCPUSuffix(StringRef Name) {
6368 return llvm::StringSwitch<const char*>(Name)
6369 .Case("hexagonv4", "4")
6370 .Case("hexagonv5", "5")
6371 .Case("hexagonv55", "55")
6372 .Case("hexagonv60", "60")
6376 bool setCPU(const std::string &Name) override {
6377 if (!getHexagonCPUSuffix(Name))
6383 int getEHDataRegisterNumber(unsigned RegNo) const override {
6384 return RegNo < 2 ? RegNo : -1;
6388 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
6389 MacroBuilder &Builder) const {
6390 Builder.defineMacro("__qdsp6__", "1");
6391 Builder.defineMacro("__hexagon__", "1");
6393 if (CPU == "hexagonv4") {
6394 Builder.defineMacro("__HEXAGON_V4__");
6395 Builder.defineMacro("__HEXAGON_ARCH__", "4");
6396 if (Opts.HexagonQdsp6Compat) {
6397 Builder.defineMacro("__QDSP6_V4__");
6398 Builder.defineMacro("__QDSP6_ARCH__", "4");
6400 } else if (CPU == "hexagonv5") {
6401 Builder.defineMacro("__HEXAGON_V5__");
6402 Builder.defineMacro("__HEXAGON_ARCH__", "5");
6403 if(Opts.HexagonQdsp6Compat) {
6404 Builder.defineMacro("__QDSP6_V5__");
6405 Builder.defineMacro("__QDSP6_ARCH__", "5");
6407 } else if (CPU == "hexagonv55") {
6408 Builder.defineMacro("__HEXAGON_V55__");
6409 Builder.defineMacro("__HEXAGON_ARCH__", "55");
6410 Builder.defineMacro("__QDSP6_V55__");
6411 Builder.defineMacro("__QDSP6_ARCH__", "55");
6412 } else if (CPU == "hexagonv60") {
6413 Builder.defineMacro("__HEXAGON_V60__");
6414 Builder.defineMacro("__HEXAGON_ARCH__", "60");
6415 Builder.defineMacro("__QDSP6_V60__");
6416 Builder.defineMacro("__QDSP6_ARCH__", "60");
6419 if (hasFeature("hvx")) {
6420 Builder.defineMacro("__HVX__");
6421 if (hasFeature("hvx-double"))
6422 Builder.defineMacro("__HVXDBL__");
6426 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features,
6427 DiagnosticsEngine &Diags, StringRef CPU,
6428 const std::vector<std::string> &FeaturesVec) const {
6429 // Default for v60: -hvx, -hvx-double.
6430 Features["hvx"] = false;
6431 Features["hvx-double"] = false;
6432 Features["long-calls"] = false;
6434 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6437 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
6438 DiagnosticsEngine &Diags) {
6439 for (auto &F : Features) {
6442 else if (F == "-hvx")
6443 HasHVX = HasHVXDouble = false;
6444 else if (F == "+hvx-double")
6445 HasHVX = HasHVXDouble = true;
6446 else if (F == "-hvx-double")
6447 HasHVXDouble = false;
6449 if (F == "+long-calls")
6450 UseLongCalls = true;
6451 else if (F == "-long-calls")
6452 UseLongCalls = false;
6457 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
6458 StringRef Name, bool Enabled) const {
6460 if (Name == "hvx-double")
6461 Features["hvx"] = true;
6464 Features["hvx-double"] = false;
6466 Features[Name] = Enabled;
6469 const char *const HexagonTargetInfo::GCCRegNames[] = {
6470 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6471 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6472 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6473 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
6474 "p0", "p1", "p2", "p3",
6475 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
6478 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const {
6479 return llvm::makeArrayRef(GCCRegNames);
6482 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
6483 { { "sp" }, "r29" },
6484 { { "fp" }, "r30" },
6485 { { "lr" }, "r31" },
6488 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const {
6489 return llvm::makeArrayRef(GCCRegAliases);
6493 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
6494 #define BUILTIN(ID, TYPE, ATTRS) \
6495 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6496 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6497 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6498 #include "clang/Basic/BuiltinsHexagon.def"
6501 class LanaiTargetInfo : public TargetInfo {
6502 // Class for Lanai (32-bit).
6503 // The CPU profiles supported by the Lanai backend
6509 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6510 static const char *const GCCRegNames[];
6513 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6514 : TargetInfo(Triple) {
6515 // Description string has to be kept in sync with backend.
6516 resetDataLayout("E" // Big endian
6517 "-m:e" // ELF name manging
6518 "-p:32:32" // 32 bit pointers, 32 bit aligned
6519 "-i64:64" // 64 bit integers, 64 bit aligned
6520 "-a:0:32" // 32 bit alignment of objects of aggregate type
6521 "-n32" // 32 bit native integer width
6522 "-S64" // 64 bit natural stack alignment
6525 // Setting RegParmMax equal to what mregparm was set to in the old
6529 // Set the default CPU to V11
6532 // Temporary approach to make everything at least word-aligned and allow for
6533 // safely casting between pointers with different alignment requirements.
6534 // TODO: Remove this when there are no more cast align warnings on the
6536 MinGlobalAlign = 32;
6539 void getTargetDefines(const LangOptions &Opts,
6540 MacroBuilder &Builder) const override {
6541 // Define __lanai__ when building for target lanai.
6542 Builder.defineMacro("__lanai__");
6544 // Set define for the CPU specified.
6547 Builder.defineMacro("__LANAI_V11__");
6550 llvm_unreachable("Unhandled target CPU");
6554 bool setCPU(const std::string &Name) override {
6555 CPU = llvm::StringSwitch<CPUKind>(Name)
6556 .Case("v11", CK_V11)
6559 return CPU != CK_NONE;
6562 bool hasFeature(StringRef Feature) const override {
6563 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false);
6566 ArrayRef<const char *> getGCCRegNames() const override;
6568 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6570 BuiltinVaListKind getBuiltinVaListKind() const override {
6571 return TargetInfo::VoidPtrBuiltinVaList;
6574 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
6576 bool validateAsmConstraint(const char *&Name,
6577 TargetInfo::ConstraintInfo &info) const override {
6581 const char *getClobbers() const override { return ""; }
6584 const char *const LanaiTargetInfo::GCCRegNames[] = {
6585 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
6586 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
6587 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
6589 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const {
6590 return llvm::makeArrayRef(GCCRegNames);
6593 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = {
6603 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const {
6604 return llvm::makeArrayRef(GCCRegAliases);
6607 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
6608 class SparcTargetInfo : public TargetInfo {
6609 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6610 static const char * const GCCRegNames[];
6613 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6614 : TargetInfo(Triple), SoftFloat(false) {}
6616 int getEHDataRegisterNumber(unsigned RegNo) const override {
6617 if (RegNo == 0) return 24;
6618 if (RegNo == 1) return 25;
6622 bool handleTargetFeatures(std::vector<std::string> &Features,
6623 DiagnosticsEngine &Diags) override {
6624 // Check if software floating point is enabled
6625 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
6626 if (Feature != Features.end()) {
6631 void getTargetDefines(const LangOptions &Opts,
6632 MacroBuilder &Builder) const override {
6633 DefineStd(Builder, "sparc", Opts);
6634 Builder.defineMacro("__REGISTER_PREFIX__", "");
6637 Builder.defineMacro("SOFT_FLOAT", "1");
6640 bool hasFeature(StringRef Feature) const override {
6641 return llvm::StringSwitch<bool>(Feature)
6642 .Case("softfloat", SoftFloat)
6643 .Case("sparc", true)
6647 bool hasSjLjLowering() const override {
6651 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6652 // FIXME: Implement!
6655 BuiltinVaListKind getBuiltinVaListKind() const override {
6656 return TargetInfo::VoidPtrBuiltinVaList;
6658 ArrayRef<const char *> getGCCRegNames() const override;
6659 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6660 bool validateAsmConstraint(const char *&Name,
6661 TargetInfo::ConstraintInfo &info) const override {
6662 // FIXME: Implement!
6664 case 'I': // Signed 13-bit constant
6666 case 'K': // 32-bit constant with the low 12 bits clear
6667 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
6668 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
6669 case 'N': // Same as 'K' but zext (required for SIMode)
6670 case 'O': // The constant 4096
6675 const char *getClobbers() const override {
6676 // FIXME: Implement!
6680 // No Sparc V7 for now, the backend doesn't support it anyway.
6711 enum CPUGeneration {
6716 CPUGeneration getCPUGeneration(CPUKind Kind) const {
6724 case CK_SPARCLITE86X:
6731 case CK_LEON2_AT697E:
6732 case CK_LEON2_AT697F:
6734 case CK_LEON3_UT699:
6735 case CK_LEON3_GR712RC:
6737 case CK_LEON4_GR740:
6741 case CK_ULTRASPARC3:
6748 llvm_unreachable("Unexpected CPU kind");
6751 CPUKind getCPUKind(StringRef Name) const {
6752 return llvm::StringSwitch<CPUKind>(Name)
6754 .Case("supersparc", CK_SUPERSPARC)
6755 .Case("sparclite", CK_SPARCLITE)
6756 .Case("f934", CK_F934)
6757 .Case("hypersparc", CK_HYPERSPARC)
6758 .Case("sparclite86x", CK_SPARCLITE86X)
6759 .Case("sparclet", CK_SPARCLET)
6760 .Case("tsc701", CK_TSC701)
6762 .Case("ultrasparc", CK_ULTRASPARC)
6763 .Case("ultrasparc3", CK_ULTRASPARC3)
6764 .Case("niagara", CK_NIAGARA)
6765 .Case("niagara2", CK_NIAGARA2)
6766 .Case("niagara3", CK_NIAGARA3)
6767 .Case("niagara4", CK_NIAGARA4)
6768 .Case("ma2100", CK_MYRIAD2100)
6769 .Case("ma2150", CK_MYRIAD2150)
6770 .Case("ma2450", CK_MYRIAD2450)
6771 // FIXME: the myriad2[.n] spellings are obsolete,
6772 // but a grace period is needed to allow updating dependent builds.
6773 .Case("myriad2", CK_MYRIAD2100)
6774 .Case("myriad2.1", CK_MYRIAD2100)
6775 .Case("myriad2.2", CK_MYRIAD2150)
6776 .Case("leon2", CK_LEON2)
6777 .Case("at697e", CK_LEON2_AT697E)
6778 .Case("at697f", CK_LEON2_AT697F)
6779 .Case("leon3", CK_LEON3)
6780 .Case("ut699", CK_LEON3_UT699)
6781 .Case("gr712rc", CK_LEON3_GR712RC)
6782 .Case("leon4", CK_LEON4)
6783 .Case("gr740", CK_LEON4_GR740)
6784 .Default(CK_GENERIC);
6787 bool setCPU(const std::string &Name) override {
6788 CPU = getCPUKind(Name);
6789 return CPU != CK_GENERIC;
6793 const char * const SparcTargetInfo::GCCRegNames[] = {
6794 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6795 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6796 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6797 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6800 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
6801 return llvm::makeArrayRef(GCCRegNames);
6804 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
6815 { { "o2" }, "r10" },
6816 { { "o3" }, "r11" },
6817 { { "o4" }, "r12" },
6818 { { "o5" }, "r13" },
6819 { { "o6", "sp" }, "r14" },
6820 { { "o7" }, "r15" },
6821 { { "l0" }, "r16" },
6822 { { "l1" }, "r17" },
6823 { { "l2" }, "r18" },
6824 { { "l3" }, "r19" },
6825 { { "l4" }, "r20" },
6826 { { "l5" }, "r21" },
6827 { { "l6" }, "r22" },
6828 { { "l7" }, "r23" },
6829 { { "i0" }, "r24" },
6830 { { "i1" }, "r25" },
6831 { { "i2" }, "r26" },
6832 { { "i3" }, "r27" },
6833 { { "i4" }, "r28" },
6834 { { "i5" }, "r29" },
6835 { { "i6", "fp" }, "r30" },
6836 { { "i7" }, "r31" },
6839 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
6840 return llvm::makeArrayRef(GCCRegAliases);
6843 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
6844 class SparcV8TargetInfo : public SparcTargetInfo {
6846 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6847 : SparcTargetInfo(Triple, Opts) {
6848 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64");
6849 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
6850 switch (getTriple().getOS()) {
6852 SizeType = UnsignedInt;
6853 IntPtrType = SignedInt;
6854 PtrDiffType = SignedInt;
6856 case llvm::Triple::NetBSD:
6857 case llvm::Triple::OpenBSD:
6858 SizeType = UnsignedLong;
6859 IntPtrType = SignedLong;
6860 PtrDiffType = SignedLong;
6863 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops
6864 // on up to 64 bits.
6865 MaxAtomicPromoteWidth = 64;
6866 MaxAtomicInlineWidth = 32;
6869 void getTargetDefines(const LangOptions &Opts,
6870 MacroBuilder &Builder) const override {
6871 SparcTargetInfo::getTargetDefines(Opts, Builder);
6872 switch (getCPUGeneration(CPU)) {
6874 Builder.defineMacro("__sparcv8");
6875 if (getTriple().getOS() != llvm::Triple::Solaris)
6876 Builder.defineMacro("__sparcv8__");
6879 Builder.defineMacro("__sparcv9");
6880 if (getTriple().getOS() != llvm::Triple::Solaris) {
6881 Builder.defineMacro("__sparcv9__");
6882 Builder.defineMacro("__sparc_v9__");
6886 if (getTriple().getVendor() == llvm::Triple::Myriad) {
6887 std::string MyriadArchValue, Myriad2Value;
6888 Builder.defineMacro("__sparc_v8__");
6889 Builder.defineMacro("__leon__");
6892 MyriadArchValue = "__ma2150";
6896 MyriadArchValue = "__ma2450";
6900 MyriadArchValue = "__ma2100";
6904 Builder.defineMacro(MyriadArchValue, "1");
6905 Builder.defineMacro(MyriadArchValue+"__", "1");
6906 Builder.defineMacro("__myriad2__", Myriad2Value);
6907 Builder.defineMacro("__myriad2", Myriad2Value);
6911 bool hasSjLjLowering() const override {
6916 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
6917 class SparcV8elTargetInfo : public SparcV8TargetInfo {
6919 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6920 : SparcV8TargetInfo(Triple, Opts) {
6921 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64");
6925 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
6926 class SparcV9TargetInfo : public SparcTargetInfo {
6928 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6929 : SparcTargetInfo(Triple, Opts) {
6930 // FIXME: Support Sparc quad-precision long double?
6931 resetDataLayout("E-m:e-i64:64-n32:64-S128");
6932 // This is an LP64 platform.
6933 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6935 // OpenBSD uses long long for int64_t and intmax_t.
6936 if (getTriple().getOS() == llvm::Triple::OpenBSD)
6937 IntMaxType = SignedLongLong;
6939 IntMaxType = SignedLong;
6940 Int64Type = IntMaxType;
6942 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
6943 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
6944 LongDoubleWidth = 128;
6945 LongDoubleAlign = 128;
6946 LongDoubleFormat = &llvm::APFloat::IEEEquad();
6947 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6950 void getTargetDefines(const LangOptions &Opts,
6951 MacroBuilder &Builder) const override {
6952 SparcTargetInfo::getTargetDefines(Opts, Builder);
6953 Builder.defineMacro("__sparcv9");
6954 Builder.defineMacro("__arch64__");
6955 // Solaris doesn't need these variants, but the BSDs do.
6956 if (getTriple().getOS() != llvm::Triple::Solaris) {
6957 Builder.defineMacro("__sparc64__");
6958 Builder.defineMacro("__sparc_v9__");
6959 Builder.defineMacro("__sparcv9__");
6963 bool setCPU(const std::string &Name) override {
6964 if (!SparcTargetInfo::setCPU(Name))
6966 return getCPUGeneration(CPU) == CG_V9;
6970 class SystemZTargetInfo : public TargetInfo {
6971 static const Builtin::Info BuiltinInfo[];
6972 static const char *const GCCRegNames[];
6974 bool HasTransactionalExecution;
6978 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6979 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false),
6981 IntMaxType = SignedLong;
6982 Int64Type = SignedLong;
6983 TLSSupported = true;
6984 IntWidth = IntAlign = 32;
6985 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
6986 PointerWidth = PointerAlign = 64;
6987 LongDoubleWidth = 128;
6988 LongDoubleAlign = 64;
6989 LongDoubleFormat = &llvm::APFloat::IEEEquad();
6990 DefaultAlignForAttributeAligned = 64;
6991 MinGlobalAlign = 16;
6992 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64");
6993 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6995 void getTargetDefines(const LangOptions &Opts,
6996 MacroBuilder &Builder) const override {
6997 Builder.defineMacro("__s390__");
6998 Builder.defineMacro("__s390x__");
6999 Builder.defineMacro("__zarch__");
7000 Builder.defineMacro("__LONG_DOUBLE_128__");
7002 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
7003 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
7004 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
7005 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
7007 if (HasTransactionalExecution)
7008 Builder.defineMacro("__HTM__");
7010 Builder.defineMacro("__VEC__", "10301");
7012 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7013 return llvm::makeArrayRef(BuiltinInfo,
7014 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin);
7017 ArrayRef<const char *> getGCCRegNames() const override;
7018 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7022 bool validateAsmConstraint(const char *&Name,
7023 TargetInfo::ConstraintInfo &info) const override;
7024 const char *getClobbers() const override {
7025 // FIXME: Is this really right?
7028 BuiltinVaListKind getBuiltinVaListKind() const override {
7029 return TargetInfo::SystemZBuiltinVaList;
7031 bool setCPU(const std::string &Name) override {
7033 bool CPUKnown = llvm::StringSwitch<bool>(Name)
7035 .Case("arch8", true)
7037 .Case("arch9", true)
7038 .Case("zEC12", true)
7039 .Case("arch10", true)
7041 .Case("arch11", true)
7047 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7049 const std::vector<std::string> &FeaturesVec) const override {
7050 if (CPU == "zEC12" || CPU == "arch10")
7051 Features["transactional-execution"] = true;
7052 if (CPU == "z13" || CPU == "arch11") {
7053 Features["transactional-execution"] = true;
7054 Features["vector"] = true;
7056 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7059 bool handleTargetFeatures(std::vector<std::string> &Features,
7060 DiagnosticsEngine &Diags) override {
7061 HasTransactionalExecution = false;
7062 for (const auto &Feature : Features) {
7063 if (Feature == "+transactional-execution")
7064 HasTransactionalExecution = true;
7065 else if (Feature == "+vector")
7068 // If we use the vector ABI, vector types are 64-bit aligned.
7070 MaxVectorAlign = 64;
7071 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
7072 "-v128:64-a:8:16-n32:64");
7077 bool hasFeature(StringRef Feature) const override {
7078 return llvm::StringSwitch<bool>(Feature)
7079 .Case("systemz", true)
7080 .Case("htm", HasTransactionalExecution)
7081 .Case("vx", HasVector)
7085 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
7091 return CCCR_Warning;
7095 StringRef getABI() const override {
7101 bool useFloat128ManglingForLongDouble() const override {
7106 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
7107 #define BUILTIN(ID, TYPE, ATTRS) \
7108 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7109 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
7110 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
7111 #include "clang/Basic/BuiltinsSystemZ.def"
7114 const char *const SystemZTargetInfo::GCCRegNames[] = {
7115 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7116 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7117 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
7118 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
7121 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
7122 return llvm::makeArrayRef(GCCRegNames);
7125 bool SystemZTargetInfo::
7126 validateAsmConstraint(const char *&Name,
7127 TargetInfo::ConstraintInfo &Info) const {
7132 case 'a': // Address register
7133 case 'd': // Data register (equivalent to 'r')
7134 case 'f': // Floating-point register
7135 Info.setAllowsRegister();
7138 case 'I': // Unsigned 8-bit constant
7139 case 'J': // Unsigned 12-bit constant
7140 case 'K': // Signed 16-bit constant
7141 case 'L': // Signed 20-bit displacement (on all targets we support)
7142 case 'M': // 0x7fffffff
7145 case 'Q': // Memory with base and unsigned 12-bit displacement
7146 case 'R': // Likewise, plus an index
7147 case 'S': // Memory with base and signed 20-bit displacement
7148 case 'T': // Likewise, plus an index
7149 Info.setAllowsMemory();
7154 class MSP430TargetInfo : public TargetInfo {
7155 static const char *const GCCRegNames[];
7158 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7159 : TargetInfo(Triple) {
7160 TLSSupported = false;
7165 LongAlign = LongLongAlign = 16;
7169 SizeType = UnsignedInt;
7170 IntMaxType = SignedLongLong;
7171 IntPtrType = SignedInt;
7172 PtrDiffType = SignedInt;
7173 SigAtomicType = SignedLong;
7174 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16");
7176 void getTargetDefines(const LangOptions &Opts,
7177 MacroBuilder &Builder) const override {
7178 Builder.defineMacro("MSP430");
7179 Builder.defineMacro("__MSP430__");
7180 // FIXME: defines for different 'flavours' of MCU
7182 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7183 // FIXME: Implement.
7186 bool hasFeature(StringRef Feature) const override {
7187 return Feature == "msp430";
7189 ArrayRef<const char *> getGCCRegNames() const override;
7190 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7194 bool validateAsmConstraint(const char *&Name,
7195 TargetInfo::ConstraintInfo &info) const override {
7198 case 'K': // the constant 1
7199 case 'L': // constant -1^20 .. 1^19
7200 case 'M': // constant 1-4:
7203 // No target constraints for now.
7206 const char *getClobbers() const override {
7207 // FIXME: Is this really right?
7210 BuiltinVaListKind getBuiltinVaListKind() const override {
7212 return TargetInfo::CharPtrBuiltinVaList;
7216 const char *const MSP430TargetInfo::GCCRegNames[] = {
7217 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7218 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
7220 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const {
7221 return llvm::makeArrayRef(GCCRegNames);
7224 // LLVM and Clang cannot be used directly to output native binaries for
7225 // target, but is used to compile C code to llvm bitcode with correct
7226 // type and alignment information.
7228 // TCE uses the llvm bitcode as input and uses it for generating customized
7229 // target processor and program binary. TCE co-design environment is
7230 // publicly available in http://tce.cs.tut.fi
7232 static const unsigned TCEOpenCLAddrSpaceMap[] = {
7235 5, // opencl_constant
7236 // FIXME: generic has to be added to the target
7237 0, // opencl_generic
7243 class TCETargetInfo : public TargetInfo {
7245 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7246 : TargetInfo(Triple) {
7247 TLSSupported = false;
7249 LongWidth = LongLongWidth = 32;
7252 LongAlign = LongLongAlign = 32;
7255 SizeType = UnsignedInt;
7256 IntMaxType = SignedLong;
7257 IntPtrType = SignedInt;
7258 PtrDiffType = SignedInt;
7263 LongDoubleWidth = 32;
7264 LongDoubleAlign = 32;
7265 FloatFormat = &llvm::APFloat::IEEEsingle();
7266 DoubleFormat = &llvm::APFloat::IEEEsingle();
7267 LongDoubleFormat = &llvm::APFloat::IEEEsingle();
7268 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-"
7269 "i16:16:32-i32:32:32-i64:32:32-"
7270 "f32:32:32-f64:32:32-v64:32:32-"
7271 "v128:32:32-v256:32:32-v512:32:32-"
7272 "v1024:32:32-a0:0:32-n32");
7273 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
7274 UseAddrSpaceMapMangling = true;
7277 void getTargetDefines(const LangOptions &Opts,
7278 MacroBuilder &Builder) const override {
7279 DefineStd(Builder, "tce", Opts);
7280 Builder.defineMacro("__TCE__");
7281 Builder.defineMacro("__TCE_V1__");
7283 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; }
7285 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7286 const char *getClobbers() const override { return ""; }
7287 BuiltinVaListKind getBuiltinVaListKind() const override {
7288 return TargetInfo::VoidPtrBuiltinVaList;
7290 ArrayRef<const char *> getGCCRegNames() const override { return None; }
7291 bool validateAsmConstraint(const char *&Name,
7292 TargetInfo::ConstraintInfo &info) const override {
7295 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7300 class TCELETargetInfo : public TCETargetInfo {
7302 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7303 : TCETargetInfo(Triple, Opts) {
7306 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-"
7307 "i16:16:32-i32:32:32-i64:32:32-"
7308 "f32:32:32-f64:32:32-v64:32:32-"
7309 "v128:32:32-v256:32:32-v512:32:32-"
7310 "v1024:32:32-a0:0:32-n32");
7314 virtual void getTargetDefines(const LangOptions &Opts,
7315 MacroBuilder &Builder) const {
7316 DefineStd(Builder, "tcele", Opts);
7317 Builder.defineMacro("__TCE__");
7318 Builder.defineMacro("__TCE_V1__");
7319 Builder.defineMacro("__TCELE__");
7320 Builder.defineMacro("__TCELE_V1__");
7325 class BPFTargetInfo : public TargetInfo {
7327 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7328 : TargetInfo(Triple) {
7329 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7330 SizeType = UnsignedLong;
7331 PtrDiffType = SignedLong;
7332 IntPtrType = SignedLong;
7333 IntMaxType = SignedLong;
7334 Int64Type = SignedLong;
7336 if (Triple.getArch() == llvm::Triple::bpfeb) {
7337 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128");
7339 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
7341 MaxAtomicPromoteWidth = 64;
7342 MaxAtomicInlineWidth = 64;
7343 TLSSupported = false;
7345 void getTargetDefines(const LangOptions &Opts,
7346 MacroBuilder &Builder) const override {
7347 DefineStd(Builder, "bpf", Opts);
7348 Builder.defineMacro("__BPF__");
7350 bool hasFeature(StringRef Feature) const override {
7351 return Feature == "bpf";
7354 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7355 const char *getClobbers() const override {
7358 BuiltinVaListKind getBuiltinVaListKind() const override {
7359 return TargetInfo::VoidPtrBuiltinVaList;
7361 ArrayRef<const char *> getGCCRegNames() const override {
7364 bool validateAsmConstraint(const char *&Name,
7365 TargetInfo::ConstraintInfo &info) const override {
7368 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7373 class MipsTargetInfo : public TargetInfo {
7374 void setDataLayout() {
7378 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
7379 else if (ABI == "n32")
7380 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7381 else if (ABI == "n64")
7382 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7384 llvm_unreachable("Invalid ABI");
7387 resetDataLayout(("E-" + Layout).str());
7389 resetDataLayout(("e-" + Layout).str());
7393 static const Builtin::Info BuiltinInfo[];
7400 HardFloat, SoftFloat
7412 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7413 : TargetInfo(Triple), IsMips16(false), IsMicromips(false),
7414 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
7415 DspRev(NoDSP), HasMSA(false), HasFP64(false) {
7416 TheCXXABI.set(TargetCXXABI::GenericMIPS);
7418 setABI((getTriple().getArch() == llvm::Triple::mips ||
7419 getTriple().getArch() == llvm::Triple::mipsel)
7423 CPU = ABI == "o32" ? "mips32r2" : "mips64r2";
7426 bool isNaN2008Default() const {
7427 return CPU == "mips32r6" || CPU == "mips64r6";
7430 bool isFP64Default() const {
7431 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
7434 bool isNan2008() const override {
7438 bool processorSupportsGPR64() const {
7439 return llvm::StringSwitch<bool>(CPU)
7440 .Case("mips3", true)
7441 .Case("mips4", true)
7442 .Case("mips5", true)
7443 .Case("mips64", true)
7444 .Case("mips64r2", true)
7445 .Case("mips64r3", true)
7446 .Case("mips64r5", true)
7447 .Case("mips64r6", true)
7448 .Case("octeon", true)
7453 StringRef getABI() const override { return ABI; }
7454 bool setABI(const std::string &Name) override {
7455 if (Name == "o32") {
7461 if (Name == "n32") {
7466 if (Name == "n64") {
7474 void setO32ABITypes() {
7475 Int64Type = SignedLongLong;
7476 IntMaxType = Int64Type;
7477 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
7478 LongDoubleWidth = LongDoubleAlign = 64;
7479 LongWidth = LongAlign = 32;
7480 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
7481 PointerWidth = PointerAlign = 32;
7482 PtrDiffType = SignedInt;
7483 SizeType = UnsignedInt;
7487 void setN32N64ABITypes() {
7488 LongDoubleWidth = LongDoubleAlign = 128;
7489 LongDoubleFormat = &llvm::APFloat::IEEEquad();
7490 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
7491 LongDoubleWidth = LongDoubleAlign = 64;
7492 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
7494 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7495 SuitableAlign = 128;
7498 void setN64ABITypes() {
7499 setN32N64ABITypes();
7500 Int64Type = SignedLong;
7501 IntMaxType = Int64Type;
7502 LongWidth = LongAlign = 64;
7503 PointerWidth = PointerAlign = 64;
7504 PtrDiffType = SignedLong;
7505 SizeType = UnsignedLong;
7508 void setN32ABITypes() {
7509 setN32N64ABITypes();
7510 Int64Type = SignedLongLong;
7511 IntMaxType = Int64Type;
7512 LongWidth = LongAlign = 32;
7513 PointerWidth = PointerAlign = 32;
7514 PtrDiffType = SignedInt;
7515 SizeType = UnsignedInt;
7518 bool setCPU(const std::string &Name) override {
7520 return llvm::StringSwitch<bool>(Name)
7521 .Case("mips1", true)
7522 .Case("mips2", true)
7523 .Case("mips3", true)
7524 .Case("mips4", true)
7525 .Case("mips5", true)
7526 .Case("mips32", true)
7527 .Case("mips32r2", true)
7528 .Case("mips32r3", true)
7529 .Case("mips32r5", true)
7530 .Case("mips32r6", true)
7531 .Case("mips64", true)
7532 .Case("mips64r2", true)
7533 .Case("mips64r3", true)
7534 .Case("mips64r5", true)
7535 .Case("mips64r6", true)
7536 .Case("octeon", true)
7537 .Case("p5600", true)
7540 const std::string& getCPU() const { return CPU; }
7542 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7544 const std::vector<std::string> &FeaturesVec) const override {
7547 if (CPU == "octeon")
7548 Features["mips64r2"] = Features["cnmips"] = true;
7550 Features[CPU] = true;
7551 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7554 void getTargetDefines(const LangOptions &Opts,
7555 MacroBuilder &Builder) const override {
7557 DefineStd(Builder, "MIPSEB", Opts);
7558 Builder.defineMacro("_MIPSEB");
7560 DefineStd(Builder, "MIPSEL", Opts);
7561 Builder.defineMacro("_MIPSEL");
7564 Builder.defineMacro("__mips__");
7565 Builder.defineMacro("_mips");
7567 Builder.defineMacro("mips");
7570 Builder.defineMacro("__mips", "32");
7571 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
7573 Builder.defineMacro("__mips", "64");
7574 Builder.defineMacro("__mips64");
7575 Builder.defineMacro("__mips64__");
7576 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
7579 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU())
7580 .Cases("mips32", "mips64", "1")
7581 .Cases("mips32r2", "mips64r2", "2")
7582 .Cases("mips32r3", "mips64r3", "3")
7583 .Cases("mips32r5", "mips64r5", "5")
7584 .Cases("mips32r6", "mips64r6", "6")
7586 if (!ISARev.empty())
7587 Builder.defineMacro("__mips_isa_rev", ISARev);
7590 Builder.defineMacro("__mips_o32");
7591 Builder.defineMacro("_ABIO32", "1");
7592 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
7593 } else if (ABI == "n32") {
7594 Builder.defineMacro("__mips_n32");
7595 Builder.defineMacro("_ABIN32", "2");
7596 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
7597 } else if (ABI == "n64") {
7598 Builder.defineMacro("__mips_n64");
7599 Builder.defineMacro("_ABI64", "3");
7600 Builder.defineMacro("_MIPS_SIM", "_ABI64");
7602 llvm_unreachable("Invalid ABI.");
7604 Builder.defineMacro("__REGISTER_PREFIX__", "");
7608 Builder.defineMacro("__mips_hard_float", Twine(1));
7611 Builder.defineMacro("__mips_soft_float", Twine(1));
7616 Builder.defineMacro("__mips_single_float", Twine(1));
7618 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
7619 Builder.defineMacro("_MIPS_FPSET",
7620 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
7623 Builder.defineMacro("__mips16", Twine(1));
7626 Builder.defineMacro("__mips_micromips", Twine(1));
7629 Builder.defineMacro("__mips_nan2008", Twine(1));
7635 Builder.defineMacro("__mips_dsp_rev", Twine(1));
7636 Builder.defineMacro("__mips_dsp", Twine(1));
7639 Builder.defineMacro("__mips_dsp_rev", Twine(2));
7640 Builder.defineMacro("__mips_dspr2", Twine(1));
7641 Builder.defineMacro("__mips_dsp", Twine(1));
7646 Builder.defineMacro("__mips_msa", Twine(1));
7648 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
7649 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
7650 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
7652 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
7653 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
7655 // These shouldn't be defined for MIPS-I but there's no need to check
7656 // for that since MIPS-I isn't supported.
7657 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
7658 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
7659 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
7661 // 32-bit MIPS processors don't have the necessary lld/scd instructions
7662 // found in 64-bit processors. In the case of O32 on a 64-bit processor,
7663 // the instructions exist but using them violates the ABI since they
7664 // require 64-bit GPRs and O32 only supports 32-bit GPRs.
7665 if (ABI == "n32" || ABI == "n64")
7666 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
7669 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7670 return llvm::makeArrayRef(BuiltinInfo,
7671 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin);
7673 bool hasFeature(StringRef Feature) const override {
7674 return llvm::StringSwitch<bool>(Feature)
7676 .Case("fp64", HasFP64)
7679 BuiltinVaListKind getBuiltinVaListKind() const override {
7680 return TargetInfo::VoidPtrBuiltinVaList;
7682 ArrayRef<const char *> getGCCRegNames() const override {
7683 static const char *const GCCRegNames[] = {
7684 // CPU register names
7685 // Must match second column of GCCRegAliases
7686 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
7687 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
7688 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
7689 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
7690 // Floating point register names
7691 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
7692 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
7693 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
7694 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
7695 // Hi/lo and condition register names
7696 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
7697 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo",
7699 // MSA register names
7700 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
7701 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
7702 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
7703 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
7704 // MSA control register names
7705 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
7706 "$msarequest", "$msamap", "$msaunmap"
7708 return llvm::makeArrayRef(GCCRegNames);
7710 bool validateAsmConstraint(const char *&Name,
7711 TargetInfo::ConstraintInfo &Info) const override {
7715 case 'r': // CPU registers.
7716 case 'd': // Equivalent to "r" unless generating MIPS16 code.
7717 case 'y': // Equivalent to "r", backward compatibility only.
7718 case 'f': // floating-point registers.
7719 case 'c': // $25 for indirect jumps
7720 case 'l': // lo register
7721 case 'x': // hilo register pair
7722 Info.setAllowsRegister();
7724 case 'I': // Signed 16-bit constant
7725 case 'J': // Integer 0
7726 case 'K': // Unsigned 16-bit constant
7727 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
7728 case 'M': // Constants not loadable via lui, addiu, or ori
7729 case 'N': // Constant -1 to -65535
7730 case 'O': // A signed 15-bit constant
7731 case 'P': // A constant between 1 go 65535
7733 case 'R': // An address that can be used in a non-macro load or store
7734 Info.setAllowsMemory();
7737 if (Name[1] == 'C') { // An address usable by ll, and sc.
7738 Info.setAllowsMemory();
7739 Name++; // Skip over 'Z'.
7746 std::string convertConstraint(const char *&Constraint) const override {
7748 switch (*Constraint) {
7749 case 'Z': // Two-character constraint; add "^" hint for later parsing.
7750 if (Constraint[1] == 'C') {
7751 R = std::string("^") + std::string(Constraint, 2);
7757 return TargetInfo::convertConstraint(Constraint);
7760 const char *getClobbers() const override {
7761 // In GCC, $1 is not widely used in generated code (it's used only in a few
7762 // specific situations), so there is no real need for users to add it to
7763 // the clobbers list if they want to use it in their inline assembly code.
7765 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
7766 // code generation, so using it in inline assembly without adding it to the
7767 // clobbers list can cause conflicts between the inline assembly code and
7768 // the surrounding generated code.
7770 // Another problem is that LLVM is allowed to choose $1 for inline assembly
7771 // operands, which will conflict with the ".set at" assembler option (which
7772 // we use only for inline assembly, in order to maintain compatibility with
7773 // GCC) and will also conflict with the user's usage of $1.
7775 // The easiest way to avoid these conflicts and keep $1 as an allocatable
7776 // register for generated code is to automatically clobber $1 for all inline
7779 // FIXME: We should automatically clobber $1 only for inline assembly code
7780 // which actually uses it. This would allow LLVM to use $1 for inline
7781 // assembly operands if the user's assembly code doesn't use it.
7785 bool handleTargetFeatures(std::vector<std::string> &Features,
7786 DiagnosticsEngine &Diags) override {
7788 IsMicromips = false;
7789 IsNan2008 = isNaN2008Default();
7790 IsSingleFloat = false;
7791 FloatABI = HardFloat;
7793 HasFP64 = isFP64Default();
7795 for (const auto &Feature : Features) {
7796 if (Feature == "+single-float")
7797 IsSingleFloat = true;
7798 else if (Feature == "+soft-float")
7799 FloatABI = SoftFloat;
7800 else if (Feature == "+mips16")
7802 else if (Feature == "+micromips")
7804 else if (Feature == "+dsp")
7805 DspRev = std::max(DspRev, DSP1);
7806 else if (Feature == "+dspr2")
7807 DspRev = std::max(DspRev, DSP2);
7808 else if (Feature == "+msa")
7810 else if (Feature == "+fp64")
7812 else if (Feature == "-fp64")
7814 else if (Feature == "+nan2008")
7816 else if (Feature == "-nan2008")
7825 int getEHDataRegisterNumber(unsigned RegNo) const override {
7826 if (RegNo == 0) return 4;
7827 if (RegNo == 1) return 5;
7831 bool isCLZForZeroUndef() const override { return false; }
7833 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7834 static const TargetInfo::GCCRegAlias O32RegAliases[] = {
7835 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
7836 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
7837 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"},
7838 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"},
7839 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"},
7840 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
7841 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
7842 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
7843 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
7844 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
7846 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = {
7847 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
7848 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
7849 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"},
7850 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"},
7851 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"},
7852 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
7853 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
7854 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
7855 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
7856 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
7859 return llvm::makeArrayRef(O32RegAliases);
7860 return llvm::makeArrayRef(NewABIRegAliases);
7863 bool hasInt128Type() const override {
7864 return ABI == "n32" || ABI == "n64";
7867 bool validateTarget(DiagnosticsEngine &Diags) const override {
7868 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle
7869 // this yet. It's better to fail here than on the backend assertion.
7870 if (processorSupportsGPR64() && ABI == "o32") {
7871 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
7875 // 64-bit ABI's require 64-bit CPU's.
7876 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) {
7877 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
7881 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend
7882 // can't handle this yet. It's better to fail here than on the
7883 // backend assertion.
7884 if ((getTriple().getArch() == llvm::Triple::mips64 ||
7885 getTriple().getArch() == llvm::Triple::mips64el) &&
7887 Diags.Report(diag::err_target_unsupported_abi_for_triple)
7888 << ABI << getTriple().str();
7892 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend
7893 // can't handle this yet. It's better to fail here than on the
7894 // backend assertion.
7895 if ((getTriple().getArch() == llvm::Triple::mips ||
7896 getTriple().getArch() == llvm::Triple::mipsel) &&
7897 (ABI == "n32" || ABI == "n64")) {
7898 Diags.Report(diag::err_target_unsupported_abi_for_triple)
7899 << ABI << getTriple().str();
7907 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = {
7908 #define BUILTIN(ID, TYPE, ATTRS) \
7909 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7910 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
7911 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
7912 #include "clang/Basic/BuiltinsMips.def"
7915 class PNaClTargetInfo : public TargetInfo {
7917 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7918 : TargetInfo(Triple) {
7919 this->LongAlign = 32;
7920 this->LongWidth = 32;
7921 this->PointerAlign = 32;
7922 this->PointerWidth = 32;
7923 this->IntMaxType = TargetInfo::SignedLongLong;
7924 this->Int64Type = TargetInfo::SignedLongLong;
7925 this->DoubleAlign = 64;
7926 this->LongDoubleWidth = 64;
7927 this->LongDoubleAlign = 64;
7928 this->SizeType = TargetInfo::UnsignedInt;
7929 this->PtrDiffType = TargetInfo::SignedInt;
7930 this->IntPtrType = TargetInfo::SignedInt;
7931 this->RegParmMax = 0; // Disallow regparm
7934 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
7935 Builder.defineMacro("__le32__");
7936 Builder.defineMacro("__pnacl__");
7938 void getTargetDefines(const LangOptions &Opts,
7939 MacroBuilder &Builder) const override {
7940 getArchDefines(Opts, Builder);
7942 bool hasFeature(StringRef Feature) const override {
7943 return Feature == "pnacl";
7945 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7946 BuiltinVaListKind getBuiltinVaListKind() const override {
7947 return TargetInfo::PNaClABIBuiltinVaList;
7949 ArrayRef<const char *> getGCCRegNames() const override;
7950 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
7951 bool validateAsmConstraint(const char *&Name,
7952 TargetInfo::ConstraintInfo &Info) const override {
7956 const char *getClobbers() const override {
7961 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const {
7965 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const {
7969 // We attempt to use PNaCl (le32) frontend and Mips32EL backend.
7970 class NaClMips32TargetInfo : public MipsTargetInfo {
7972 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7973 : MipsTargetInfo(Triple, Opts) {}
7975 BuiltinVaListKind getBuiltinVaListKind() const override {
7976 return TargetInfo::PNaClABIBuiltinVaList;
7980 class Le64TargetInfo : public TargetInfo {
7981 static const Builtin::Info BuiltinInfo[];
7984 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7985 : TargetInfo(Triple) {
7986 NoAsmVariants = true;
7987 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7988 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7989 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128");
7992 void getTargetDefines(const LangOptions &Opts,
7993 MacroBuilder &Builder) const override {
7994 DefineStd(Builder, "unix", Opts);
7995 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
7996 Builder.defineMacro("__ELF__");
7998 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7999 return llvm::makeArrayRef(BuiltinInfo,
8000 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin);
8002 BuiltinVaListKind getBuiltinVaListKind() const override {
8003 return TargetInfo::PNaClABIBuiltinVaList;
8005 const char *getClobbers() const override { return ""; }
8006 ArrayRef<const char *> getGCCRegNames() const override {
8009 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8012 bool validateAsmConstraint(const char *&Name,
8013 TargetInfo::ConstraintInfo &Info) const override {
8017 bool hasProtectedVisibility() const override { return false; }
8020 class WebAssemblyTargetInfo : public TargetInfo {
8021 static const Builtin::Info BuiltinInfo[];
8029 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &)
8030 : TargetInfo(T), SIMDLevel(NoSIMD) {
8031 NoAsmVariants = true;
8032 SuitableAlign = 128;
8033 LargeArrayMinWidth = 128;
8034 LargeArrayAlign = 128;
8035 SimdDefaultAlign = 128;
8036 SigAtomicType = SignedLong;
8037 LongDoubleWidth = LongDoubleAlign = 128;
8038 LongDoubleFormat = &llvm::APFloat::IEEEquad();
8039 SizeType = UnsignedInt;
8040 PtrDiffType = SignedInt;
8041 IntPtrType = SignedInt;
8045 void getTargetDefines(const LangOptions &Opts,
8046 MacroBuilder &Builder) const override {
8047 defineCPUMacros(Builder, "wasm", /*Tuning=*/false);
8048 if (SIMDLevel >= SIMD128)
8049 Builder.defineMacro("__wasm_simd128__");
8054 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
8056 const std::vector<std::string> &FeaturesVec) const override {
8057 if (CPU == "bleeding-edge")
8058 Features["simd128"] = true;
8059 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
8061 bool hasFeature(StringRef Feature) const final {
8062 return llvm::StringSwitch<bool>(Feature)
8063 .Case("simd128", SIMDLevel >= SIMD128)
8066 bool handleTargetFeatures(std::vector<std::string> &Features,
8067 DiagnosticsEngine &Diags) final {
8068 for (const auto &Feature : Features) {
8069 if (Feature == "+simd128") {
8070 SIMDLevel = std::max(SIMDLevel, SIMD128);
8073 if (Feature == "-simd128") {
8074 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1));
8078 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature
8079 << "-target-feature";
8084 bool setCPU(const std::string &Name) final {
8085 return llvm::StringSwitch<bool>(Name)
8087 .Case("bleeding-edge", true)
8088 .Case("generic", true)
8091 ArrayRef<Builtin::Info> getTargetBuiltins() const final {
8092 return llvm::makeArrayRef(BuiltinInfo,
8093 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin);
8095 BuiltinVaListKind getBuiltinVaListKind() const final {
8096 return VoidPtrBuiltinVaList;
8098 ArrayRef<const char *> getGCCRegNames() const final {
8101 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final {
8105 validateAsmConstraint(const char *&Name,
8106 TargetInfo::ConstraintInfo &Info) const final {
8109 const char *getClobbers() const final { return ""; }
8110 bool isCLZForZeroUndef() const final { return false; }
8111 bool hasInt128Type() const final { return true; }
8112 IntType getIntTypeByWidth(unsigned BitWidth,
8113 bool IsSigned) const final {
8114 // WebAssembly prefers long long for explicitly 64-bit integers.
8115 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
8116 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
8118 IntType getLeastIntTypeByWidth(unsigned BitWidth,
8119 bool IsSigned) const final {
8120 // WebAssembly uses long long for int_least64_t and int_fast64_t.
8121 return BitWidth == 64
8122 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
8123 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
8127 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = {
8128 #define BUILTIN(ID, TYPE, ATTRS) \
8129 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8130 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8131 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8132 #include "clang/Basic/BuiltinsWebAssembly.def"
8135 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo {
8137 explicit WebAssembly32TargetInfo(const llvm::Triple &T,
8138 const TargetOptions &Opts)
8139 : WebAssemblyTargetInfo(T, Opts) {
8140 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
8141 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128");
8145 void getTargetDefines(const LangOptions &Opts,
8146 MacroBuilder &Builder) const override {
8147 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
8148 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false);
8152 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo {
8154 explicit WebAssembly64TargetInfo(const llvm::Triple &T,
8155 const TargetOptions &Opts)
8156 : WebAssemblyTargetInfo(T, Opts) {
8157 LongAlign = LongWidth = 64;
8158 PointerAlign = PointerWidth = 64;
8159 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8160 SizeType = UnsignedLong;
8161 PtrDiffType = SignedLong;
8162 IntPtrType = SignedLong;
8163 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
8167 void getTargetDefines(const LangOptions &Opts,
8168 MacroBuilder &Builder) const override {
8169 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
8170 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false);
8174 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
8175 #define BUILTIN(ID, TYPE, ATTRS) \
8176 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8177 #include "clang/Basic/BuiltinsLe64.def"
8180 static const unsigned SPIRAddrSpaceMap[] = {
8183 2, // opencl_constant
8184 4, // opencl_generic
8189 class SPIRTargetInfo : public TargetInfo {
8191 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8192 : TargetInfo(Triple) {
8193 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
8194 "SPIR target must use unknown OS");
8195 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
8196 "SPIR target must use unknown environment type");
8197 TLSSupported = false;
8198 LongWidth = LongAlign = 64;
8199 AddrSpaceMap = &SPIRAddrSpaceMap;
8200 UseAddrSpaceMapMangling = true;
8201 // Define available target features
8202 // These must be defined in sorted order!
8203 NoAsmVariants = true;
8205 void getTargetDefines(const LangOptions &Opts,
8206 MacroBuilder &Builder) const override {
8207 DefineStd(Builder, "SPIR", Opts);
8209 bool hasFeature(StringRef Feature) const override {
8210 return Feature == "spir";
8213 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
8214 const char *getClobbers() const override { return ""; }
8215 ArrayRef<const char *> getGCCRegNames() const override { return None; }
8216 bool validateAsmConstraint(const char *&Name,
8217 TargetInfo::ConstraintInfo &info) const override {
8220 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8223 BuiltinVaListKind getBuiltinVaListKind() const override {
8224 return TargetInfo::VoidPtrBuiltinVaList;
8227 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
8228 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK
8232 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
8233 return CC_SpirFunction;
8236 void setSupportedOpenCLOpts() override {
8237 // Assume all OpenCL extensions and optional core features are supported
8238 // for SPIR since it is a generic target.
8239 getSupportedOpenCLOpts().supportAll();
8243 class SPIR32TargetInfo : public SPIRTargetInfo {
8245 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8246 : SPIRTargetInfo(Triple, Opts) {
8247 PointerWidth = PointerAlign = 32;
8248 SizeType = TargetInfo::UnsignedInt;
8249 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
8250 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
8251 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
8253 void getTargetDefines(const LangOptions &Opts,
8254 MacroBuilder &Builder) const override {
8255 DefineStd(Builder, "SPIR32", Opts);
8259 class SPIR64TargetInfo : public SPIRTargetInfo {
8261 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8262 : SPIRTargetInfo(Triple, Opts) {
8263 PointerWidth = PointerAlign = 64;
8264 SizeType = TargetInfo::UnsignedLong;
8265 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
8266 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
8267 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
8269 void getTargetDefines(const LangOptions &Opts,
8270 MacroBuilder &Builder) const override {
8271 DefineStd(Builder, "SPIR64", Opts);
8275 class XCoreTargetInfo : public TargetInfo {
8276 static const Builtin::Info BuiltinInfo[];
8278 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8279 : TargetInfo(Triple) {
8280 NoAsmVariants = true;
8283 DoubleAlign = LongDoubleAlign = 32;
8284 SizeType = UnsignedInt;
8285 PtrDiffType = SignedInt;
8286 IntPtrType = SignedInt;
8287 WCharType = UnsignedChar;
8288 WIntType = UnsignedInt;
8289 UseZeroLengthBitfieldAlignment = true;
8290 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
8291 "-f64:32-a:0:32-n32");
8293 void getTargetDefines(const LangOptions &Opts,
8294 MacroBuilder &Builder) const override {
8295 Builder.defineMacro("__XS1B__");
8297 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8298 return llvm::makeArrayRef(BuiltinInfo,
8299 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin);
8301 BuiltinVaListKind getBuiltinVaListKind() const override {
8302 return TargetInfo::VoidPtrBuiltinVaList;
8304 const char *getClobbers() const override {
8307 ArrayRef<const char *> getGCCRegNames() const override {
8308 static const char * const GCCRegNames[] = {
8309 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8310 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
8312 return llvm::makeArrayRef(GCCRegNames);
8314 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8317 bool validateAsmConstraint(const char *&Name,
8318 TargetInfo::ConstraintInfo &Info) const override {
8321 int getEHDataRegisterNumber(unsigned RegNo) const override {
8322 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
8323 return (RegNo < 2)? RegNo : -1;
8325 bool allowsLargerPreferedTypeAlignment() const override {
8330 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
8331 #define BUILTIN(ID, TYPE, ATTRS) \
8332 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8333 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8334 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8335 #include "clang/Basic/BuiltinsXCore.def"
8338 // x86_32 Android target
8339 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
8341 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8342 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) {
8344 LongDoubleWidth = 64;
8345 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
8349 // x86_64 Android target
8350 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
8352 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8353 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) {
8354 LongDoubleFormat = &llvm::APFloat::IEEEquad();
8357 bool useFloat128ManglingForLongDouble() const override {
8362 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes
8363 class RenderScript32TargetInfo : public ARMleTargetInfo {
8365 RenderScript32TargetInfo(const llvm::Triple &Triple,
8366 const TargetOptions &Opts)
8367 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(),
8369 Triple.getEnvironmentName()),
8371 IsRenderScriptTarget = true;
8372 LongWidth = LongAlign = 64;
8374 void getTargetDefines(const LangOptions &Opts,
8375 MacroBuilder &Builder) const override {
8376 Builder.defineMacro("__RENDERSCRIPT__");
8377 ARMleTargetInfo::getTargetDefines(Opts, Builder);
8381 // 64-bit RenderScript is aarch64
8382 class RenderScript64TargetInfo : public AArch64leTargetInfo {
8384 RenderScript64TargetInfo(const llvm::Triple &Triple,
8385 const TargetOptions &Opts)
8386 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(),
8388 Triple.getEnvironmentName()),
8390 IsRenderScriptTarget = true;
8393 void getTargetDefines(const LangOptions &Opts,
8394 MacroBuilder &Builder) const override {
8395 Builder.defineMacro("__RENDERSCRIPT__");
8396 AArch64leTargetInfo::getTargetDefines(Opts, Builder);
8402 class AVRTargetInfo : public TargetInfo {
8404 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8405 : TargetInfo(Triple) {
8406 TLSSupported = false;
8416 DefaultAlignForAttributeAligned = 8;
8423 DoubleFormat = &llvm::APFloat::IEEEsingle();
8424 LongDoubleWidth = 32;
8425 LongDoubleAlign = 8;
8426 LongDoubleFormat = &llvm::APFloat::IEEEsingle();
8427 SizeType = UnsignedInt;
8428 PtrDiffType = SignedInt;
8429 IntPtrType = SignedInt;
8430 Char16Type = UnsignedInt;
8431 WCharType = SignedInt;
8432 WIntType = SignedInt;
8433 Char32Type = UnsignedLong;
8434 SigAtomicType = SignedChar;
8435 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64"
8436 "-f32:32:32-f64:64:64-n8");
8439 void getTargetDefines(const LangOptions &Opts,
8440 MacroBuilder &Builder) const override {
8441 Builder.defineMacro("__AVR__");
8444 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8448 BuiltinVaListKind getBuiltinVaListKind() const override {
8449 return TargetInfo::VoidPtrBuiltinVaList;
8452 const char *getClobbers() const override {
8456 ArrayRef<const char *> getGCCRegNames() const override {
8457 static const char * const GCCRegNames[] = {
8458 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8459 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8460 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8461 "r24", "r25", "X", "Y", "Z", "SP"
8463 return llvm::makeArrayRef(GCCRegNames);
8466 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8470 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
8471 static const TargetInfo::AddlRegName AddlRegNames[] = {
8472 { { "r26", "r27"}, 26 },
8473 { { "r28", "r29"}, 27 },
8474 { { "r30", "r31"}, 28 },
8475 { { "SPL", "SPH"}, 29 },
8477 return llvm::makeArrayRef(AddlRegNames);
8480 bool validateAsmConstraint(const char *&Name,
8481 TargetInfo::ConstraintInfo &Info) const override {
8485 IntType getIntTypeByWidth(unsigned BitWidth,
8486 bool IsSigned) const final {
8487 // AVR prefers int for 16-bit integers.
8488 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt)
8489 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
8492 IntType getLeastIntTypeByWidth(unsigned BitWidth,
8493 bool IsSigned) const final {
8494 // AVR uses int for int_least16_t and int_fast16_t.
8495 return BitWidth == 16
8496 ? (IsSigned ? SignedInt : UnsignedInt)
8497 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
8501 } // end anonymous namespace
8503 //===----------------------------------------------------------------------===//
8505 //===----------------------------------------------------------------------===//
8507 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
8508 const TargetOptions &Opts) {
8509 llvm::Triple::OSType os = Triple.getOS();
8511 switch (Triple.getArch()) {
8515 case llvm::Triple::xcore:
8516 return new XCoreTargetInfo(Triple, Opts);
8518 case llvm::Triple::hexagon:
8519 return new HexagonTargetInfo(Triple, Opts);
8521 case llvm::Triple::lanai:
8522 return new LanaiTargetInfo(Triple, Opts);
8524 case llvm::Triple::aarch64:
8525 if (Triple.isOSDarwin())
8526 return new DarwinAArch64TargetInfo(Triple, Opts);
8529 case llvm::Triple::CloudABI:
8530 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts);
8531 case llvm::Triple::FreeBSD:
8532 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
8533 case llvm::Triple::Fuchsia:
8534 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts);
8535 case llvm::Triple::Linux:
8536 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts);
8537 case llvm::Triple::NetBSD:
8538 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
8540 return new AArch64leTargetInfo(Triple, Opts);
8543 case llvm::Triple::aarch64_be:
8545 case llvm::Triple::FreeBSD:
8546 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
8547 case llvm::Triple::Fuchsia:
8548 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts);
8549 case llvm::Triple::Linux:
8550 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts);
8551 case llvm::Triple::NetBSD:
8552 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
8554 return new AArch64beTargetInfo(Triple, Opts);
8557 case llvm::Triple::arm:
8558 case llvm::Triple::thumb:
8559 if (Triple.isOSBinFormatMachO())
8560 return new DarwinARMTargetInfo(Triple, Opts);
8563 case llvm::Triple::CloudABI:
8564 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts);
8565 case llvm::Triple::Linux:
8566 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts);
8567 case llvm::Triple::FreeBSD:
8568 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
8569 case llvm::Triple::Fuchsia:
8570 return new FuchsiaTargetInfo<ARMleTargetInfo>(Triple, Opts);
8571 case llvm::Triple::NetBSD:
8572 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
8573 case llvm::Triple::OpenBSD:
8574 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
8575 case llvm::Triple::Bitrig:
8576 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts);
8577 case llvm::Triple::RTEMS:
8578 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts);
8579 case llvm::Triple::NaCl:
8580 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts);
8581 case llvm::Triple::Win32:
8582 switch (Triple.getEnvironment()) {
8583 case llvm::Triple::Cygnus:
8584 return new CygwinARMTargetInfo(Triple, Opts);
8585 case llvm::Triple::GNU:
8586 return new MinGWARMTargetInfo(Triple, Opts);
8587 case llvm::Triple::Itanium:
8588 return new ItaniumWindowsARMleTargetInfo(Triple, Opts);
8589 case llvm::Triple::MSVC:
8590 default: // Assume MSVC for unknown environments
8591 return new MicrosoftARMleTargetInfo(Triple, Opts);
8594 return new ARMleTargetInfo(Triple, Opts);
8597 case llvm::Triple::armeb:
8598 case llvm::Triple::thumbeb:
8599 if (Triple.isOSDarwin())
8600 return new DarwinARMTargetInfo(Triple, Opts);
8603 case llvm::Triple::Linux:
8604 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8605 case llvm::Triple::FreeBSD:
8606 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8607 case llvm::Triple::Fuchsia:
8608 return new FuchsiaTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8609 case llvm::Triple::NetBSD:
8610 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8611 case llvm::Triple::OpenBSD:
8612 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8613 case llvm::Triple::Bitrig:
8614 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8615 case llvm::Triple::RTEMS:
8616 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8617 case llvm::Triple::NaCl:
8618 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8620 return new ARMbeTargetInfo(Triple, Opts);
8623 case llvm::Triple::avr:
8624 return new AVRTargetInfo(Triple, Opts);
8625 case llvm::Triple::bpfeb:
8626 case llvm::Triple::bpfel:
8627 return new BPFTargetInfo(Triple, Opts);
8629 case llvm::Triple::msp430:
8630 return new MSP430TargetInfo(Triple, Opts);
8632 case llvm::Triple::mips:
8634 case llvm::Triple::Linux:
8635 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
8636 case llvm::Triple::RTEMS:
8637 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
8638 case llvm::Triple::FreeBSD:
8639 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8640 case llvm::Triple::NetBSD:
8641 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8643 return new MipsTargetInfo(Triple, Opts);
8646 case llvm::Triple::mipsel:
8648 case llvm::Triple::Linux:
8649 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
8650 case llvm::Triple::RTEMS:
8651 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
8652 case llvm::Triple::FreeBSD:
8653 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8654 case llvm::Triple::NetBSD:
8655 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8656 case llvm::Triple::NaCl:
8657 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts);
8659 return new MipsTargetInfo(Triple, Opts);
8662 case llvm::Triple::mips64:
8664 case llvm::Triple::Linux:
8665 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
8666 case llvm::Triple::RTEMS:
8667 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
8668 case llvm::Triple::FreeBSD:
8669 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8670 case llvm::Triple::NetBSD:
8671 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8672 case llvm::Triple::OpenBSD:
8673 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8675 return new MipsTargetInfo(Triple, Opts);
8678 case llvm::Triple::mips64el:
8680 case llvm::Triple::Linux:
8681 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
8682 case llvm::Triple::RTEMS:
8683 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
8684 case llvm::Triple::FreeBSD:
8685 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8686 case llvm::Triple::NetBSD:
8687 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8688 case llvm::Triple::OpenBSD:
8689 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8691 return new MipsTargetInfo(Triple, Opts);
8694 case llvm::Triple::le32:
8696 case llvm::Triple::NaCl:
8697 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts);
8702 case llvm::Triple::le64:
8703 return new Le64TargetInfo(Triple, Opts);
8705 case llvm::Triple::ppc:
8706 if (Triple.isOSDarwin())
8707 return new DarwinPPC32TargetInfo(Triple, Opts);
8709 case llvm::Triple::Linux:
8710 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts);
8711 case llvm::Triple::FreeBSD:
8712 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
8713 case llvm::Triple::NetBSD:
8714 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
8715 case llvm::Triple::OpenBSD:
8716 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
8717 case llvm::Triple::RTEMS:
8718 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts);
8720 return new PPC32TargetInfo(Triple, Opts);
8723 case llvm::Triple::ppc64:
8724 if (Triple.isOSDarwin())
8725 return new DarwinPPC64TargetInfo(Triple, Opts);
8727 case llvm::Triple::Linux:
8728 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
8729 case llvm::Triple::Lv2:
8730 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts);
8731 case llvm::Triple::FreeBSD:
8732 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
8733 case llvm::Triple::NetBSD:
8734 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
8736 return new PPC64TargetInfo(Triple, Opts);
8739 case llvm::Triple::ppc64le:
8741 case llvm::Triple::Linux:
8742 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
8743 case llvm::Triple::NetBSD:
8744 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
8746 return new PPC64TargetInfo(Triple, Opts);
8749 case llvm::Triple::nvptx:
8750 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32);
8751 case llvm::Triple::nvptx64:
8752 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64);
8754 case llvm::Triple::amdgcn:
8755 case llvm::Triple::r600:
8756 return new AMDGPUTargetInfo(Triple, Opts);
8758 case llvm::Triple::sparc:
8760 case llvm::Triple::Linux:
8761 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8762 case llvm::Triple::Solaris:
8763 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8764 case llvm::Triple::NetBSD:
8765 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8766 case llvm::Triple::OpenBSD:
8767 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8768 case llvm::Triple::RTEMS:
8769 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8771 return new SparcV8TargetInfo(Triple, Opts);
8774 // The 'sparcel' architecture copies all the above cases except for Solaris.
8775 case llvm::Triple::sparcel:
8777 case llvm::Triple::Linux:
8778 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
8779 case llvm::Triple::NetBSD:
8780 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
8781 case llvm::Triple::OpenBSD:
8782 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
8783 case llvm::Triple::RTEMS:
8784 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
8786 return new SparcV8elTargetInfo(Triple, Opts);
8789 case llvm::Triple::sparcv9:
8791 case llvm::Triple::Linux:
8792 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8793 case llvm::Triple::Solaris:
8794 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8795 case llvm::Triple::NetBSD:
8796 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8797 case llvm::Triple::OpenBSD:
8798 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8799 case llvm::Triple::FreeBSD:
8800 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8802 return new SparcV9TargetInfo(Triple, Opts);
8805 case llvm::Triple::systemz:
8807 case llvm::Triple::Linux:
8808 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts);
8810 return new SystemZTargetInfo(Triple, Opts);
8813 case llvm::Triple::tce:
8814 return new TCETargetInfo(Triple, Opts);
8816 case llvm::Triple::tcele:
8817 return new TCELETargetInfo(Triple, Opts);
8819 case llvm::Triple::x86:
8820 if (Triple.isOSDarwin())
8821 return new DarwinI386TargetInfo(Triple, Opts);
8824 case llvm::Triple::CloudABI:
8825 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts);
8826 case llvm::Triple::Linux: {
8827 switch (Triple.getEnvironment()) {
8829 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts);
8830 case llvm::Triple::Android:
8831 return new AndroidX86_32TargetInfo(Triple, Opts);
8834 case llvm::Triple::DragonFly:
8835 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
8836 case llvm::Triple::NetBSD:
8837 return new NetBSDI386TargetInfo(Triple, Opts);
8838 case llvm::Triple::OpenBSD:
8839 return new OpenBSDI386TargetInfo(Triple, Opts);
8840 case llvm::Triple::Bitrig:
8841 return new BitrigI386TargetInfo(Triple, Opts);
8842 case llvm::Triple::FreeBSD:
8843 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
8844 case llvm::Triple::Fuchsia:
8845 return new FuchsiaTargetInfo<X86_32TargetInfo>(Triple, Opts);
8846 case llvm::Triple::KFreeBSD:
8847 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
8848 case llvm::Triple::Minix:
8849 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts);
8850 case llvm::Triple::Solaris:
8851 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts);
8852 case llvm::Triple::Win32: {
8853 switch (Triple.getEnvironment()) {
8854 case llvm::Triple::Cygnus:
8855 return new CygwinX86_32TargetInfo(Triple, Opts);
8856 case llvm::Triple::GNU:
8857 return new MinGWX86_32TargetInfo(Triple, Opts);
8858 case llvm::Triple::Itanium:
8859 case llvm::Triple::MSVC:
8860 default: // Assume MSVC for unknown environments
8861 return new MicrosoftX86_32TargetInfo(Triple, Opts);
8864 case llvm::Triple::Haiku:
8865 return new HaikuX86_32TargetInfo(Triple, Opts);
8866 case llvm::Triple::RTEMS:
8867 return new RTEMSX86_32TargetInfo(Triple, Opts);
8868 case llvm::Triple::NaCl:
8869 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts);
8870 case llvm::Triple::ELFIAMCU:
8871 return new MCUX86_32TargetInfo(Triple, Opts);
8873 return new X86_32TargetInfo(Triple, Opts);
8876 case llvm::Triple::x86_64:
8877 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
8878 return new DarwinX86_64TargetInfo(Triple, Opts);
8881 case llvm::Triple::CloudABI:
8882 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts);
8883 case llvm::Triple::Linux: {
8884 switch (Triple.getEnvironment()) {
8886 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts);
8887 case llvm::Triple::Android:
8888 return new AndroidX86_64TargetInfo(Triple, Opts);
8891 case llvm::Triple::DragonFly:
8892 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
8893 case llvm::Triple::NetBSD:
8894 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
8895 case llvm::Triple::OpenBSD:
8896 return new OpenBSDX86_64TargetInfo(Triple, Opts);
8897 case llvm::Triple::Bitrig:
8898 return new BitrigX86_64TargetInfo(Triple, Opts);
8899 case llvm::Triple::FreeBSD:
8900 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
8901 case llvm::Triple::Fuchsia:
8902 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts);
8903 case llvm::Triple::KFreeBSD:
8904 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
8905 case llvm::Triple::Solaris:
8906 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts);
8907 case llvm::Triple::Win32: {
8908 switch (Triple.getEnvironment()) {
8909 case llvm::Triple::Cygnus:
8910 return new CygwinX86_64TargetInfo(Triple, Opts);
8911 case llvm::Triple::GNU:
8912 return new MinGWX86_64TargetInfo(Triple, Opts);
8913 case llvm::Triple::MSVC:
8914 default: // Assume MSVC for unknown environments
8915 return new MicrosoftX86_64TargetInfo(Triple, Opts);
8918 case llvm::Triple::Haiku:
8919 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts);
8920 case llvm::Triple::NaCl:
8921 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts);
8922 case llvm::Triple::PS4:
8923 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts);
8925 return new X86_64TargetInfo(Triple, Opts);
8928 case llvm::Triple::spir: {
8929 if (Triple.getOS() != llvm::Triple::UnknownOS ||
8930 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
8932 return new SPIR32TargetInfo(Triple, Opts);
8934 case llvm::Triple::spir64: {
8935 if (Triple.getOS() != llvm::Triple::UnknownOS ||
8936 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
8938 return new SPIR64TargetInfo(Triple, Opts);
8940 case llvm::Triple::wasm32:
8941 if (!(Triple == llvm::Triple("wasm32-unknown-unknown")))
8943 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts);
8944 case llvm::Triple::wasm64:
8945 if (!(Triple == llvm::Triple("wasm64-unknown-unknown")))
8947 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts);
8949 case llvm::Triple::renderscript32:
8950 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts);
8951 case llvm::Triple::renderscript64:
8952 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts);
8956 /// CreateTargetInfo - Return the target info object for the specified target
8959 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
8960 const std::shared_ptr<TargetOptions> &Opts) {
8961 llvm::Triple Triple(Opts->Triple);
8963 // Construct the target
8964 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts));
8966 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
8969 Target->TargetOpts = Opts;
8971 // Set the target CPU if specified.
8972 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
8973 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
8977 // Set the target ABI if specified.
8978 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
8979 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
8983 // Set the fp math unit.
8984 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
8985 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
8989 // Compute the default target features, we need the target to handle this
8990 // because features may have dependencies on one another.
8991 llvm::StringMap<bool> Features;
8992 if (!Target->initFeatureMap(Features, Diags, Opts->CPU,
8993 Opts->FeaturesAsWritten))
8996 // Add the features to the compile options.
8997 Opts->Features.clear();
8998 for (const auto &F : Features)
8999 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str());
9001 if (!Target->handleTargetFeatures(Opts->Features, Diags))
9004 Target->setSupportedOpenCLOpts();
9005 Target->setOpenCLExtensionOpts();
9007 if (!Target->validateTarget(Diags))
9010 return Target.release();