1 //===--- Targets.cpp - Implement target feature support -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/Builtins.h"
16 #include "clang/Basic/Cuda.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetInfo.h"
22 #include "clang/Basic/TargetOptions.h"
23 #include "clang/Basic/Version.h"
24 #include "clang/Frontend/CodeGenOptions.h"
25 #include "llvm/ADT/APFloat.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/StringSwitch.h"
30 #include "llvm/ADT/Triple.h"
31 #include "llvm/MC/MCSectionMachO.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/TargetParser.h"
37 using namespace clang;
39 //===----------------------------------------------------------------------===//
40 // Common code shared among targets.
41 //===----------------------------------------------------------------------===//
43 /// DefineStd - Define a macro name and standard variants. For example if
44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
47 const LangOptions &Opts) {
48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
51 // in the user's namespace.
53 Builder.defineMacro(MacroName);
56 Builder.defineMacro("__" + MacroName);
59 Builder.defineMacro("__" + MacroName + "__");
62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
64 Builder.defineMacro("__" + CPUName);
65 Builder.defineMacro("__" + CPUName + "__");
67 Builder.defineMacro("__tune_" + CPUName + "__");
70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
71 const TargetOptions &Opts);
73 //===----------------------------------------------------------------------===//
74 // Defines specific to certain operating systems.
75 //===----------------------------------------------------------------------===//
78 template<typename TgtInfo>
79 class OSTargetInfo : public TgtInfo {
81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
82 MacroBuilder &Builder) const=0;
84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
85 : TgtInfo(Triple, Opts) {}
86 void getTargetDefines(const LangOptions &Opts,
87 MacroBuilder &Builder) const override {
88 TgtInfo::getTargetDefines(Opts, Builder);
89 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
95 template <typename Target>
96 class CloudABITargetInfo : public OSTargetInfo<Target> {
98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
99 MacroBuilder &Builder) const override {
100 Builder.defineMacro("__CloudABI__");
101 Builder.defineMacro("__ELF__");
103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
104 Builder.defineMacro("__STDC_ISO_10646__", "201206L");
105 Builder.defineMacro("__STDC_UTF_16__");
106 Builder.defineMacro("__STDC_UTF_32__");
110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
111 : OSTargetInfo<Target>(Triple, Opts) {}
115 template<typename Target>
116 class AnanasTargetInfo : public OSTargetInfo<Target> {
118 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
119 MacroBuilder &Builder) const override {
121 Builder.defineMacro("__Ananas__");
122 Builder.defineMacro("__ELF__");
125 AnanasTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
126 : OSTargetInfo<Target>(Triple, Opts) {}
129 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
130 const llvm::Triple &Triple,
131 StringRef &PlatformName,
132 VersionTuple &PlatformMinVersion) {
133 Builder.defineMacro("__APPLE_CC__", "6000");
134 Builder.defineMacro("__APPLE__");
135 Builder.defineMacro("__STDC_NO_THREADS__");
136 Builder.defineMacro("OBJC_NEW_PROPERTIES");
137 // AddressSanitizer doesn't play well with source fortification, which is on
138 // by default on Darwin.
139 if (Opts.Sanitize.has(SanitizerKind::Address))
140 Builder.defineMacro("_FORTIFY_SOURCE", "0");
142 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode.
144 // __weak is always defined, for use in blocks and with objc pointers.
145 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
146 Builder.defineMacro("__strong", "");
147 Builder.defineMacro("__unsafe_unretained", "");
151 Builder.defineMacro("__STATIC__");
153 Builder.defineMacro("__DYNAMIC__");
155 if (Opts.POSIXThreads)
156 Builder.defineMacro("_REENTRANT");
158 // Get the platform type and version number from the triple.
159 unsigned Maj, Min, Rev;
160 if (Triple.isMacOSX()) {
161 Triple.getMacOSXVersion(Maj, Min, Rev);
162 PlatformName = "macos";
164 Triple.getOSVersion(Maj, Min, Rev);
165 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
168 // If -target arch-pc-win32-macho option specified, we're
169 // generating code for Win32 ABI. No need to emit
170 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
171 if (PlatformName == "win32") {
172 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
176 // Set the appropriate OS version define.
177 if (Triple.isiOS()) {
178 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
182 Str[1] = '0' + (Min / 10);
183 Str[2] = '0' + (Min % 10);
184 Str[3] = '0' + (Rev / 10);
185 Str[4] = '0' + (Rev % 10);
188 // Handle versions >= 10.
189 Str[0] = '0' + (Maj / 10);
190 Str[1] = '0' + (Maj % 10);
191 Str[2] = '0' + (Min / 10);
192 Str[3] = '0' + (Min % 10);
193 Str[4] = '0' + (Rev / 10);
194 Str[5] = '0' + (Rev % 10);
198 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str);
200 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
203 } else if (Triple.isWatchOS()) {
204 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
207 Str[1] = '0' + (Min / 10);
208 Str[2] = '0' + (Min % 10);
209 Str[3] = '0' + (Rev / 10);
210 Str[4] = '0' + (Rev % 10);
212 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str);
213 } else if (Triple.isMacOSX()) {
214 // Note that the Driver allows versions which aren't representable in the
215 // define (because we only get a single digit for the minor and micro
216 // revision numbers). So, we limit them to the maximum representable
218 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
220 if (Maj < 10 || (Maj == 10 && Min < 10)) {
221 Str[0] = '0' + (Maj / 10);
222 Str[1] = '0' + (Maj % 10);
223 Str[2] = '0' + std::min(Min, 9U);
224 Str[3] = '0' + std::min(Rev, 9U);
227 // Handle versions > 10.9.
228 Str[0] = '0' + (Maj / 10);
229 Str[1] = '0' + (Maj % 10);
230 Str[2] = '0' + (Min / 10);
231 Str[3] = '0' + (Min % 10);
232 Str[4] = '0' + (Rev / 10);
233 Str[5] = '0' + (Rev % 10);
236 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
239 // Tell users about the kernel if there is one.
240 if (Triple.isOSDarwin())
241 Builder.defineMacro("__MACH__");
243 // The Watch ABI uses Dwarf EH.
244 if(Triple.isWatchABI())
245 Builder.defineMacro("__ARM_DWARF_EH__");
247 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
250 template<typename Target>
251 class DarwinTargetInfo : public OSTargetInfo<Target> {
253 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
254 MacroBuilder &Builder) const override {
255 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
256 this->PlatformMinVersion);
260 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
261 : OSTargetInfo<Target>(Triple, Opts) {
262 // By default, no TLS, and we whitelist permitted architecture/OS
264 this->TLSSupported = false;
266 if (Triple.isMacOSX())
267 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7);
268 else if (Triple.isiOS()) {
269 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards.
270 if (Triple.getArch() == llvm::Triple::x86_64 ||
271 Triple.getArch() == llvm::Triple::aarch64)
272 this->TLSSupported = !Triple.isOSVersionLT(8);
273 else if (Triple.getArch() == llvm::Triple::x86 ||
274 Triple.getArch() == llvm::Triple::arm ||
275 Triple.getArch() == llvm::Triple::thumb)
276 this->TLSSupported = !Triple.isOSVersionLT(9);
277 } else if (Triple.isWatchOS())
278 this->TLSSupported = !Triple.isOSVersionLT(2);
280 this->MCountName = "\01mcount";
283 std::string isValidSectionSpecifier(StringRef SR) const override {
284 // Let MCSectionMachO validate this.
285 StringRef Segment, Section;
286 unsigned TAA, StubSize;
288 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
289 TAA, HasTAA, StubSize);
292 const char *getStaticInitSectionSpecifier() const override {
293 // FIXME: We should return 0 when building kexts.
294 return "__TEXT,__StaticInit,regular,pure_instructions";
297 /// Darwin does not support protected visibility. Darwin's "default"
298 /// is very similar to ELF's "protected"; Darwin requires a "weak"
299 /// attribute on declarations that can be dynamically replaced.
300 bool hasProtectedVisibility() const override {
304 unsigned getExnObjectAlignment() const override {
305 // The alignment of an exception object is 8-bytes for darwin since
306 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned))
307 // and therefore doesn't guarantee 16-byte alignment.
313 // DragonFlyBSD Target
314 template<typename Target>
315 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
317 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
318 MacroBuilder &Builder) const override {
319 // DragonFly defines; list based off of gcc output
320 Builder.defineMacro("__DragonFly__");
321 Builder.defineMacro("__DragonFly_cc_version", "100001");
322 Builder.defineMacro("__ELF__");
323 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
324 Builder.defineMacro("__tune_i386__");
325 DefineStd(Builder, "unix", Opts);
328 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
329 : OSTargetInfo<Target>(Triple, Opts) {
330 switch (Triple.getArch()) {
332 case llvm::Triple::x86:
333 case llvm::Triple::x86_64:
334 this->MCountName = ".mcount";
340 #ifndef FREEBSD_CC_VERSION
341 #define FREEBSD_CC_VERSION 0U
345 template<typename Target>
346 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
348 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
349 MacroBuilder &Builder) const override {
350 // FreeBSD defines; list based off of gcc output
352 unsigned Release = Triple.getOSMajorVersion();
355 unsigned CCVersion = FREEBSD_CC_VERSION;
357 CCVersion = Release * 100000U + 1U;
359 Builder.defineMacro("__FreeBSD__", Twine(Release));
360 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion));
361 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
362 DefineStd(Builder, "unix", Opts);
363 Builder.defineMacro("__ELF__");
365 // On FreeBSD, wchar_t contains the number of the code point as
366 // used by the character set of the locale. These character sets are
367 // not necessarily a superset of ASCII.
369 // FIXME: This is wrong; the macro refers to the numerical values
370 // of wchar_t *literals*, which are not locale-dependent. However,
371 // FreeBSD systems apparently depend on us getting this wrong, and
372 // setting this to 1 is conforming even if all the basic source
373 // character literals have the same encoding as char and wchar_t.
374 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
377 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
378 : OSTargetInfo<Target>(Triple, Opts) {
379 switch (Triple.getArch()) {
381 case llvm::Triple::x86:
382 case llvm::Triple::x86_64:
383 this->MCountName = ".mcount";
385 case llvm::Triple::mips:
386 case llvm::Triple::mipsel:
387 case llvm::Triple::ppc:
388 case llvm::Triple::ppc64:
389 case llvm::Triple::ppc64le:
390 this->MCountName = "_mcount";
392 case llvm::Triple::arm:
393 this->MCountName = "__mcount";
399 // GNU/kFreeBSD Target
400 template<typename Target>
401 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
403 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
404 MacroBuilder &Builder) const override {
405 // GNU/kFreeBSD defines; list based off of gcc output
407 DefineStd(Builder, "unix", Opts);
408 Builder.defineMacro("__FreeBSD_kernel__");
409 Builder.defineMacro("__GLIBC__");
410 Builder.defineMacro("__ELF__");
411 if (Opts.POSIXThreads)
412 Builder.defineMacro("_REENTRANT");
414 Builder.defineMacro("_GNU_SOURCE");
417 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
418 : OSTargetInfo<Target>(Triple, Opts) {}
422 template<typename Target>
423 class HaikuTargetInfo : public OSTargetInfo<Target> {
425 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
426 MacroBuilder &Builder) const override {
427 // Haiku defines; list based off of gcc output
428 Builder.defineMacro("__HAIKU__");
429 Builder.defineMacro("__ELF__");
430 DefineStd(Builder, "unix", Opts);
433 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
434 : OSTargetInfo<Target>(Triple, Opts) {
435 this->SizeType = TargetInfo::UnsignedLong;
436 this->IntPtrType = TargetInfo::SignedLong;
437 this->PtrDiffType = TargetInfo::SignedLong;
438 this->ProcessIDType = TargetInfo::SignedLong;
439 this->TLSSupported = false;
445 template<typename Target>
446 class MinixTargetInfo : public OSTargetInfo<Target> {
448 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
449 MacroBuilder &Builder) const override {
452 Builder.defineMacro("__minix", "3");
453 Builder.defineMacro("_EM_WSIZE", "4");
454 Builder.defineMacro("_EM_PSIZE", "4");
455 Builder.defineMacro("_EM_SSIZE", "2");
456 Builder.defineMacro("_EM_LSIZE", "4");
457 Builder.defineMacro("_EM_FSIZE", "4");
458 Builder.defineMacro("_EM_DSIZE", "8");
459 Builder.defineMacro("__ELF__");
460 DefineStd(Builder, "unix", Opts);
463 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
464 : OSTargetInfo<Target>(Triple, Opts) {}
468 template<typename Target>
469 class LinuxTargetInfo : public OSTargetInfo<Target> {
471 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
472 MacroBuilder &Builder) const override {
473 // Linux defines; list based off of gcc output
474 DefineStd(Builder, "unix", Opts);
475 DefineStd(Builder, "linux", Opts);
476 Builder.defineMacro("__gnu_linux__");
477 Builder.defineMacro("__ELF__");
478 if (Triple.isAndroid()) {
479 Builder.defineMacro("__ANDROID__", "1");
480 unsigned Maj, Min, Rev;
481 Triple.getEnvironmentVersion(Maj, Min, Rev);
482 this->PlatformName = "android";
483 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
485 Builder.defineMacro("__ANDROID_API__", Twine(Maj));
487 if (Opts.POSIXThreads)
488 Builder.defineMacro("_REENTRANT");
490 Builder.defineMacro("_GNU_SOURCE");
491 if (this->HasFloat128)
492 Builder.defineMacro("__FLOAT128__");
495 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
496 : OSTargetInfo<Target>(Triple, Opts) {
497 this->WIntType = TargetInfo::UnsignedInt;
499 switch (Triple.getArch()) {
502 case llvm::Triple::mips:
503 case llvm::Triple::mipsel:
504 case llvm::Triple::mips64:
505 case llvm::Triple::mips64el:
506 case llvm::Triple::ppc:
507 case llvm::Triple::ppc64:
508 case llvm::Triple::ppc64le:
509 this->MCountName = "_mcount";
511 case llvm::Triple::x86:
512 case llvm::Triple::x86_64:
513 case llvm::Triple::systemz:
514 this->HasFloat128 = true;
519 const char *getStaticInitSectionSpecifier() const override {
520 return ".text.startup";
525 template<typename Target>
526 class NetBSDTargetInfo : public OSTargetInfo<Target> {
528 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
529 MacroBuilder &Builder) const override {
530 // NetBSD defines; list based off of gcc output
531 Builder.defineMacro("__NetBSD__");
532 Builder.defineMacro("__unix__");
533 Builder.defineMacro("__ELF__");
534 if (Opts.POSIXThreads)
535 Builder.defineMacro("_REENTRANT");
537 switch (Triple.getArch()) {
540 case llvm::Triple::arm:
541 case llvm::Triple::armeb:
542 case llvm::Triple::thumb:
543 case llvm::Triple::thumbeb:
544 Builder.defineMacro("__ARM_DWARF_EH__");
549 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
550 : OSTargetInfo<Target>(Triple, Opts) {
551 this->MCountName = "_mcount";
556 template<typename Target>
557 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
559 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
560 MacroBuilder &Builder) const override {
561 // OpenBSD defines; list based off of gcc output
563 Builder.defineMacro("__OpenBSD__");
564 DefineStd(Builder, "unix", Opts);
565 Builder.defineMacro("__ELF__");
566 if (Opts.POSIXThreads)
567 Builder.defineMacro("_REENTRANT");
568 if (this->HasFloat128)
569 Builder.defineMacro("__FLOAT128__");
572 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
573 : OSTargetInfo<Target>(Triple, Opts) {
574 switch (Triple.getArch()) {
575 case llvm::Triple::x86:
576 case llvm::Triple::x86_64:
577 this->HasFloat128 = true;
580 this->MCountName = "__mcount";
582 case llvm::Triple::mips64:
583 case llvm::Triple::mips64el:
584 case llvm::Triple::ppc:
585 case llvm::Triple::sparcv9:
586 this->MCountName = "_mcount";
593 template<typename Target>
594 class BitrigTargetInfo : public OSTargetInfo<Target> {
596 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
597 MacroBuilder &Builder) const override {
598 // Bitrig defines; list based off of gcc output
600 Builder.defineMacro("__Bitrig__");
601 DefineStd(Builder, "unix", Opts);
602 Builder.defineMacro("__ELF__");
603 if (Opts.POSIXThreads)
604 Builder.defineMacro("_REENTRANT");
606 switch (Triple.getArch()) {
609 case llvm::Triple::arm:
610 case llvm::Triple::armeb:
611 case llvm::Triple::thumb:
612 case llvm::Triple::thumbeb:
613 Builder.defineMacro("__ARM_DWARF_EH__");
618 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
619 : OSTargetInfo<Target>(Triple, Opts) {
620 this->MCountName = "__mcount";
625 template<typename Target>
626 class PSPTargetInfo : public OSTargetInfo<Target> {
628 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
629 MacroBuilder &Builder) const override {
630 // PSP defines; list based on the output of the pspdev gcc toolchain.
631 Builder.defineMacro("PSP");
632 Builder.defineMacro("_PSP");
633 Builder.defineMacro("__psp__");
634 Builder.defineMacro("__ELF__");
637 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {}
641 template<typename Target>
642 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
644 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
645 MacroBuilder &Builder) const override {
647 Builder.defineMacro("__PPC__");
648 Builder.defineMacro("__PPU__");
649 Builder.defineMacro("__CELLOS_LV2__");
650 Builder.defineMacro("__ELF__");
651 Builder.defineMacro("__LP32__");
652 Builder.defineMacro("_ARCH_PPC64");
653 Builder.defineMacro("__powerpc64__");
656 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
657 : OSTargetInfo<Target>(Triple, Opts) {
658 this->LongWidth = this->LongAlign = 32;
659 this->PointerWidth = this->PointerAlign = 32;
660 this->IntMaxType = TargetInfo::SignedLongLong;
661 this->Int64Type = TargetInfo::SignedLongLong;
662 this->SizeType = TargetInfo::UnsignedInt;
663 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64");
667 template <typename Target>
668 class PS4OSTargetInfo : public OSTargetInfo<Target> {
670 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
671 MacroBuilder &Builder) const override {
672 Builder.defineMacro("__FreeBSD__", "9");
673 Builder.defineMacro("__FreeBSD_cc_version", "900001");
674 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
675 DefineStd(Builder, "unix", Opts);
676 Builder.defineMacro("__ELF__");
677 Builder.defineMacro("__ORBIS__");
680 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
681 : OSTargetInfo<Target>(Triple, Opts) {
682 this->WCharType = this->UnsignedShort;
684 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits).
685 this->MaxTLSAlign = 256;
687 // On PS4, do not honor explicit bit field alignment,
688 // as in "__attribute__((aligned(2))) int b : 1;".
689 this->UseExplicitBitFieldAlignment = false;
691 switch (Triple.getArch()) {
693 case llvm::Triple::x86_64:
694 this->MCountName = ".mcount";
701 template<typename Target>
702 class SolarisTargetInfo : public OSTargetInfo<Target> {
704 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
705 MacroBuilder &Builder) const override {
706 DefineStd(Builder, "sun", Opts);
707 DefineStd(Builder, "unix", Opts);
708 Builder.defineMacro("__ELF__");
709 Builder.defineMacro("__svr4__");
710 Builder.defineMacro("__SVR4");
711 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
712 // newer, but to 500 for everything else. feature_test.h has a check to
713 // ensure that you are not using C99 with an old version of X/Open or C89
714 // with a new version.
716 Builder.defineMacro("_XOPEN_SOURCE", "600");
718 Builder.defineMacro("_XOPEN_SOURCE", "500");
720 Builder.defineMacro("__C99FEATURES__");
721 Builder.defineMacro("_LARGEFILE_SOURCE");
722 Builder.defineMacro("_LARGEFILE64_SOURCE");
723 Builder.defineMacro("__EXTENSIONS__");
724 Builder.defineMacro("_REENTRANT");
727 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
728 : OSTargetInfo<Target>(Triple, Opts) {
729 this->WCharType = this->SignedInt;
730 // FIXME: WIntType should be SignedLong
735 template<typename Target>
736 class WindowsTargetInfo : public OSTargetInfo<Target> {
738 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
739 MacroBuilder &Builder) const override {
740 Builder.defineMacro("_WIN32");
742 void getVisualStudioDefines(const LangOptions &Opts,
743 MacroBuilder &Builder) const {
744 if (Opts.CPlusPlus) {
746 Builder.defineMacro("_CPPRTTI");
748 if (Opts.CXXExceptions)
749 Builder.defineMacro("_CPPUNWIND");
753 Builder.defineMacro("__BOOL_DEFINED");
755 if (!Opts.CharIsSigned)
756 Builder.defineMacro("_CHAR_UNSIGNED");
758 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
759 // but it works for now.
760 if (Opts.POSIXThreads)
761 Builder.defineMacro("_MT");
763 if (Opts.MSCompatibilityVersion) {
764 Builder.defineMacro("_MSC_VER",
765 Twine(Opts.MSCompatibilityVersion / 100000));
766 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
767 // FIXME We cannot encode the revision information into 32-bits
768 Builder.defineMacro("_MSC_BUILD", Twine(1));
770 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
771 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
773 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) {
774 if (Opts.CPlusPlus1z)
775 Builder.defineMacro("_MSVC_LANG", "201403L");
776 else if (Opts.CPlusPlus14)
777 Builder.defineMacro("_MSVC_LANG", "201402L");
781 if (Opts.MicrosoftExt) {
782 Builder.defineMacro("_MSC_EXTENSIONS");
784 if (Opts.CPlusPlus11) {
785 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
786 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
787 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
791 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
795 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
796 : OSTargetInfo<Target>(Triple, Opts) {}
799 template <typename Target>
800 class NaClTargetInfo : public OSTargetInfo<Target> {
802 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
803 MacroBuilder &Builder) const override {
804 if (Opts.POSIXThreads)
805 Builder.defineMacro("_REENTRANT");
807 Builder.defineMacro("_GNU_SOURCE");
809 DefineStd(Builder, "unix", Opts);
810 Builder.defineMacro("__ELF__");
811 Builder.defineMacro("__native_client__");
815 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
816 : OSTargetInfo<Target>(Triple, Opts) {
817 this->LongAlign = 32;
818 this->LongWidth = 32;
819 this->PointerAlign = 32;
820 this->PointerWidth = 32;
821 this->IntMaxType = TargetInfo::SignedLongLong;
822 this->Int64Type = TargetInfo::SignedLongLong;
823 this->DoubleAlign = 64;
824 this->LongDoubleWidth = 64;
825 this->LongDoubleAlign = 64;
826 this->LongLongWidth = 64;
827 this->LongLongAlign = 64;
828 this->SizeType = TargetInfo::UnsignedInt;
829 this->PtrDiffType = TargetInfo::SignedInt;
830 this->IntPtrType = TargetInfo::SignedInt;
831 // RegParmMax is inherited from the underlying architecture.
832 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble();
833 if (Triple.getArch() == llvm::Triple::arm) {
834 // Handled in ARM's setABI().
835 } else if (Triple.getArch() == llvm::Triple::x86) {
836 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128");
837 } else if (Triple.getArch() == llvm::Triple::x86_64) {
838 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128");
839 } else if (Triple.getArch() == llvm::Triple::mipsel) {
840 // Handled on mips' setDataLayout.
842 assert(Triple.getArch() == llvm::Triple::le32);
843 this->resetDataLayout("e-p:32:32-i64:64");
849 template<typename Target>
850 class FuchsiaTargetInfo : public OSTargetInfo<Target> {
852 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
853 MacroBuilder &Builder) const override {
854 Builder.defineMacro("__Fuchsia__");
855 Builder.defineMacro("__ELF__");
856 if (Opts.POSIXThreads)
857 Builder.defineMacro("_REENTRANT");
858 // Required by the libc++ locale support.
860 Builder.defineMacro("_GNU_SOURCE");
863 FuchsiaTargetInfo(const llvm::Triple &Triple,
864 const TargetOptions &Opts)
865 : OSTargetInfo<Target>(Triple, Opts) {
866 this->MCountName = "__mcount";
870 // WebAssembly target
871 template <typename Target>
872 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> {
873 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
874 MacroBuilder &Builder) const final {
875 // A common platform macro.
876 if (Opts.POSIXThreads)
877 Builder.defineMacro("_REENTRANT");
878 // Follow g++ convention and predefine _GNU_SOURCE for C++.
880 Builder.defineMacro("_GNU_SOURCE");
883 // As an optimization, group static init code together in a section.
884 const char *getStaticInitSectionSpecifier() const final {
885 return ".text.__startup";
889 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple,
890 const TargetOptions &Opts)
891 : OSTargetInfo<Target>(Triple, Opts) {
892 this->MCountName = "__mcount";
893 this->TheCXXABI.set(TargetCXXABI::WebAssembly);
897 //===----------------------------------------------------------------------===//
898 // Specific target implementations.
899 //===----------------------------------------------------------------------===//
901 // PPC abstract base class
902 class PPCTargetInfo : public TargetInfo {
903 static const Builtin::Info BuiltinInfo[];
904 static const char * const GCCRegNames[];
905 static const TargetInfo::GCCRegAlias GCCRegAliases[];
908 // Target cpu features.
924 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
925 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false),
926 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
927 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) {
929 SimdDefaultAlign = 128;
930 LongDoubleWidth = LongDoubleAlign = 128;
931 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
934 /// \brief Flags for architecture specific defines.
937 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
938 ArchDefinePpcgr = 1 << 1,
939 ArchDefinePpcsq = 1 << 2,
940 ArchDefine440 = 1 << 3,
941 ArchDefine603 = 1 << 4,
942 ArchDefine604 = 1 << 5,
943 ArchDefinePwr4 = 1 << 6,
944 ArchDefinePwr5 = 1 << 7,
945 ArchDefinePwr5x = 1 << 8,
946 ArchDefinePwr6 = 1 << 9,
947 ArchDefinePwr6x = 1 << 10,
948 ArchDefinePwr7 = 1 << 11,
949 ArchDefinePwr8 = 1 << 12,
950 ArchDefinePwr9 = 1 << 13,
951 ArchDefineA2 = 1 << 14,
952 ArchDefineA2q = 1 << 15
955 // Set the language option for altivec based on our value.
956 void adjust(LangOptions &Opts) override {
959 TargetInfo::adjust(Opts);
962 // Note: GCC recognizes the following additional cpus:
963 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
964 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
966 bool setCPU(const std::string &Name) override {
967 bool CPUKnown = llvm::StringSwitch<bool>(Name)
968 .Case("generic", true)
990 .Case("e500mc", true)
992 .Case("power3", true)
994 .Case("power4", true)
996 .Case("power5", true)
998 .Case("power5x", true)
1000 .Case("power6", true)
1002 .Case("power6x", true)
1003 .Case("pwr6x", true)
1004 .Case("power7", true)
1006 .Case("power8", true)
1008 .Case("power9", true)
1010 .Case("powerpc", true)
1012 .Case("powerpc64", true)
1013 .Case("ppc64", true)
1014 .Case("powerpc64le", true)
1015 .Case("ppc64le", true)
1025 StringRef getABI() const override { return ABI; }
1027 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1028 return llvm::makeArrayRef(BuiltinInfo,
1029 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin);
1032 bool isCLZForZeroUndef() const override { return false; }
1034 void getTargetDefines(const LangOptions &Opts,
1035 MacroBuilder &Builder) const override;
1038 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
1040 const std::vector<std::string> &FeaturesVec) const override;
1042 bool handleTargetFeatures(std::vector<std::string> &Features,
1043 DiagnosticsEngine &Diags) override;
1044 bool hasFeature(StringRef Feature) const override;
1045 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
1046 bool Enabled) const override;
1048 ArrayRef<const char *> getGCCRegNames() const override;
1049 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
1050 bool validateAsmConstraint(const char *&Name,
1051 TargetInfo::ConstraintInfo &Info) const override {
1053 default: return false;
1056 case 'b': // Base register
1057 case 'f': // Floating point register
1058 Info.setAllowsRegister();
1060 // FIXME: The following are added to allow parsing.
1061 // I just took a guess at what the actions should be.
1062 // Also, is more specific checking needed? I.e. specific registers?
1063 case 'd': // Floating point register (containing 64-bit value)
1064 case 'v': // Altivec vector register
1065 Info.setAllowsRegister();
1069 case 'd':// VSX vector register to hold vector double data
1070 case 'f':// VSX vector register to hold vector float data
1071 case 's':// VSX vector register to hold scalar float data
1072 case 'a':// Any VSX register
1073 case 'c':// An individual CR bit
1078 Info.setAllowsRegister();
1079 Name++; // Skip over 'w'.
1081 case 'h': // `MQ', `CTR', or `LINK' register
1082 case 'q': // `MQ' register
1083 case 'c': // `CTR' register
1084 case 'l': // `LINK' register
1085 case 'x': // `CR' register (condition register) number 0
1086 case 'y': // `CR' register (condition register)
1087 case 'z': // `XER[CA]' carry bit (part of the XER register)
1088 Info.setAllowsRegister();
1090 case 'I': // Signed 16-bit constant
1091 case 'J': // Unsigned 16-bit constant shifted left 16 bits
1092 // (use `L' instead for SImode constants)
1093 case 'K': // Unsigned 16-bit constant
1094 case 'L': // Signed 16-bit constant shifted left 16 bits
1095 case 'M': // Constant larger than 31
1096 case 'N': // Exact power of 2
1097 case 'P': // Constant whose negation is a signed 16-bit constant
1098 case 'G': // Floating point constant that can be loaded into a
1099 // register with one instruction per word
1100 case 'H': // Integer/Floating point constant that can be loaded
1101 // into a register using three instructions
1103 case 'm': // Memory operand. Note that on PowerPC targets, m can
1104 // include addresses that update the base register. It
1105 // is therefore only safe to use `m' in an asm statement
1106 // if that asm statement accesses the operand exactly once.
1107 // The asm statement must also use `%U<opno>' as a
1108 // placeholder for the "update" flag in the corresponding
1109 // load or store instruction. For example:
1110 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
1112 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
1113 // is not. Use es rather than m if you don't want the base
1114 // register to be updated.
1118 // es: A "stable" memory operand; that is, one which does not
1119 // include any automodification of the base register. Unlike
1120 // `m', this constraint can be used in asm statements that
1121 // might access the operand several times, or that might not
1122 // access it at all.
1123 Info.setAllowsMemory();
1124 Name++; // Skip over 'e'.
1126 case 'Q': // Memory operand that is an offset from a register (it is
1127 // usually better to use `m' or `es' in asm statements)
1128 case 'Z': // Memory operand that is an indexed or indirect from a
1129 // register (it is usually better to use `m' or `es' in
1131 Info.setAllowsMemory();
1132 Info.setAllowsRegister();
1134 case 'R': // AIX TOC entry
1135 case 'a': // Address operand that is an indexed or indirect from a
1136 // register (`p' is preferable for asm statements)
1137 case 'S': // Constant suitable as a 64-bit mask operand
1138 case 'T': // Constant suitable as a 32-bit mask operand
1139 case 'U': // System V Release 4 small data area reference
1140 case 't': // AND masks that can be performed by two rldic{l, r}
1142 case 'W': // Vector constant that does not require memory
1143 case 'j': // Vector constant that is all zeros.
1149 std::string convertConstraint(const char *&Constraint) const override {
1151 switch (*Constraint) {
1154 // Two-character constraint; add "^" hint for later parsing.
1155 R = std::string("^") + std::string(Constraint, 2);
1159 return TargetInfo::convertConstraint(Constraint);
1163 const char *getClobbers() const override {
1166 int getEHDataRegisterNumber(unsigned RegNo) const override {
1167 if (RegNo == 0) return 3;
1168 if (RegNo == 1) return 4;
1172 bool hasSjLjLowering() const override {
1176 bool useFloat128ManglingForLongDouble() const override {
1177 return LongDoubleWidth == 128 &&
1178 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() &&
1179 getTriple().isOSBinFormatELF();
1183 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
1184 #define BUILTIN(ID, TYPE, ATTRS) \
1185 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1186 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1187 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1188 #include "clang/Basic/BuiltinsPPC.def"
1191 /// handleTargetFeatures - Perform initialization based on the user
1192 /// configured set of features.
1193 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1194 DiagnosticsEngine &Diags) {
1195 for (const auto &Feature : Features) {
1196 if (Feature == "+altivec") {
1198 } else if (Feature == "+vsx") {
1200 } else if (Feature == "+bpermd") {
1202 } else if (Feature == "+extdiv") {
1204 } else if (Feature == "+power8-vector") {
1206 } else if (Feature == "+crypto") {
1208 } else if (Feature == "+direct-move") {
1209 HasDirectMove = true;
1210 } else if (Feature == "+qpx") {
1212 } else if (Feature == "+htm") {
1214 } else if (Feature == "+float128") {
1216 } else if (Feature == "+power9-vector") {
1219 // TODO: Finish this list and add an assert that we've handled them
1226 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1227 /// #defines that are not tied to a specific subtarget.
1228 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1229 MacroBuilder &Builder) const {
1230 // Target identification.
1231 Builder.defineMacro("__ppc__");
1232 Builder.defineMacro("__PPC__");
1233 Builder.defineMacro("_ARCH_PPC");
1234 Builder.defineMacro("__powerpc__");
1235 Builder.defineMacro("__POWERPC__");
1236 if (PointerWidth == 64) {
1237 Builder.defineMacro("_ARCH_PPC64");
1238 Builder.defineMacro("__powerpc64__");
1239 Builder.defineMacro("__ppc64__");
1240 Builder.defineMacro("__PPC64__");
1243 // Target properties.
1244 if (getTriple().getArch() == llvm::Triple::ppc64le) {
1245 Builder.defineMacro("_LITTLE_ENDIAN");
1247 if (getTriple().getOS() != llvm::Triple::NetBSD &&
1248 getTriple().getOS() != llvm::Triple::OpenBSD)
1249 Builder.defineMacro("_BIG_ENDIAN");
1253 if (ABI == "elfv1" || ABI == "elfv1-qpx")
1254 Builder.defineMacro("_CALL_ELF", "1");
1256 Builder.defineMacro("_CALL_ELF", "2");
1258 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but
1259 // our suppport post-dates this and it should work on all 64-bit ppc linux
1260 // platforms. It is guaranteed to work on all elfv2 platforms.
1261 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64)
1262 Builder.defineMacro("_CALL_LINUX", "1");
1264 // Subtarget options.
1265 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1266 Builder.defineMacro("__REGISTER_PREFIX__", "");
1268 // FIXME: Should be controlled by command line option.
1269 if (LongDoubleWidth == 128) {
1270 Builder.defineMacro("__LONG_DOUBLE_128__");
1271 Builder.defineMacro("__LONGDOUBLE128");
1274 // Define this for elfv2 (64-bit only) or 64-bit darwin.
1275 if (ABI == "elfv2" ||
1276 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64))
1277 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16");
1279 // CPU identification.
1280 ArchDefineTypes defs =
1281 (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1282 .Case("440", ArchDefineName)
1283 .Case("450", ArchDefineName | ArchDefine440)
1284 .Case("601", ArchDefineName)
1285 .Case("602", ArchDefineName | ArchDefinePpcgr)
1286 .Case("603", ArchDefineName | ArchDefinePpcgr)
1287 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1288 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1289 .Case("604", ArchDefineName | ArchDefinePpcgr)
1290 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1291 .Case("620", ArchDefineName | ArchDefinePpcgr)
1292 .Case("630", ArchDefineName | ArchDefinePpcgr)
1293 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1294 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1295 .Case("750", ArchDefineName | ArchDefinePpcgr)
1296 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
1298 .Case("a2", ArchDefineA2)
1299 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1300 .Case("pwr3", ArchDefinePpcgr)
1301 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1302 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
1304 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 |
1305 ArchDefinePpcgr | ArchDefinePpcsq)
1306 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 |
1307 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1308 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x |
1309 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
1311 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 |
1312 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
1313 ArchDefinePpcgr | ArchDefinePpcsq)
1314 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x |
1315 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
1316 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1317 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 |
1318 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
1319 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
1321 .Case("power3", ArchDefinePpcgr)
1322 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1323 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
1325 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
1326 ArchDefinePpcgr | ArchDefinePpcsq)
1327 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
1328 ArchDefinePwr4 | ArchDefinePpcgr |
1330 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
1331 ArchDefinePwr5 | ArchDefinePwr4 |
1332 ArchDefinePpcgr | ArchDefinePpcsq)
1333 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 |
1334 ArchDefinePwr5x | ArchDefinePwr5 |
1335 ArchDefinePwr4 | ArchDefinePpcgr |
1337 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x |
1338 ArchDefinePwr6 | ArchDefinePwr5x |
1339 ArchDefinePwr5 | ArchDefinePwr4 |
1340 ArchDefinePpcgr | ArchDefinePpcsq)
1341 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
1342 ArchDefinePwr6x | ArchDefinePwr6 |
1343 ArchDefinePwr5x | ArchDefinePwr5 |
1344 ArchDefinePwr4 | ArchDefinePpcgr |
1346 // powerpc64le automatically defaults to at least power8.
1347 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x |
1348 ArchDefinePwr6 | ArchDefinePwr5x |
1349 ArchDefinePwr5 | ArchDefinePwr4 |
1350 ArchDefinePpcgr | ArchDefinePpcsq)
1351 .Default(ArchDefineNone);
1353 if (defs & ArchDefineName)
1354 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1355 if (defs & ArchDefinePpcgr)
1356 Builder.defineMacro("_ARCH_PPCGR");
1357 if (defs & ArchDefinePpcsq)
1358 Builder.defineMacro("_ARCH_PPCSQ");
1359 if (defs & ArchDefine440)
1360 Builder.defineMacro("_ARCH_440");
1361 if (defs & ArchDefine603)
1362 Builder.defineMacro("_ARCH_603");
1363 if (defs & ArchDefine604)
1364 Builder.defineMacro("_ARCH_604");
1365 if (defs & ArchDefinePwr4)
1366 Builder.defineMacro("_ARCH_PWR4");
1367 if (defs & ArchDefinePwr5)
1368 Builder.defineMacro("_ARCH_PWR5");
1369 if (defs & ArchDefinePwr5x)
1370 Builder.defineMacro("_ARCH_PWR5X");
1371 if (defs & ArchDefinePwr6)
1372 Builder.defineMacro("_ARCH_PWR6");
1373 if (defs & ArchDefinePwr6x)
1374 Builder.defineMacro("_ARCH_PWR6X");
1375 if (defs & ArchDefinePwr7)
1376 Builder.defineMacro("_ARCH_PWR7");
1377 if (defs & ArchDefinePwr8)
1378 Builder.defineMacro("_ARCH_PWR8");
1379 if (defs & ArchDefinePwr9)
1380 Builder.defineMacro("_ARCH_PWR9");
1381 if (defs & ArchDefineA2)
1382 Builder.defineMacro("_ARCH_A2");
1383 if (defs & ArchDefineA2q) {
1384 Builder.defineMacro("_ARCH_A2Q");
1385 Builder.defineMacro("_ARCH_QP");
1388 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1389 Builder.defineMacro("__bg__");
1390 Builder.defineMacro("__THW_BLUEGENE__");
1391 Builder.defineMacro("__bgq__");
1392 Builder.defineMacro("__TOS_BGQ__");
1396 Builder.defineMacro("__VEC__", "10206");
1397 Builder.defineMacro("__ALTIVEC__");
1400 Builder.defineMacro("__VSX__");
1402 Builder.defineMacro("__POWER8_VECTOR__");
1404 Builder.defineMacro("__CRYPTO__");
1406 Builder.defineMacro("__HTM__");
1408 Builder.defineMacro("__FLOAT128__");
1410 Builder.defineMacro("__POWER9_VECTOR__");
1412 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1413 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1414 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1415 if (PointerWidth == 64)
1416 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1418 // We have support for the bswap intrinsics so we can define this.
1419 Builder.defineMacro("__HAVE_BSWAP__", "1");
1421 // FIXME: The following are not yet generated here by Clang, but are
1422 // generated by GCC:
1425 // __RECIP_PRECISION__
1426 // __APPLE_ALTIVEC__
1433 // __CMODEL_MEDIUM__
1440 // Handle explicit options being passed to the compiler here: if we've
1441 // explicitly turned off vsx and turned on any of:
1446 // then go ahead and error since the customer has expressed an incompatible
1448 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
1449 const std::vector<std::string> &FeaturesVec) {
1451 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") !=
1452 FeaturesVec.end()) {
1453 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") !=
1454 FeaturesVec.end()) {
1455 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
1460 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") !=
1461 FeaturesVec.end()) {
1462 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
1467 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") !=
1468 FeaturesVec.end()) {
1469 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
1474 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") !=
1475 FeaturesVec.end()) {
1476 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector"
1485 bool PPCTargetInfo::initFeatureMap(
1486 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
1487 const std::vector<std::string> &FeaturesVec) const {
1488 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1499 .Case("ppc64", true)
1500 .Case("ppc64le", true)
1503 Features["qpx"] = (CPU == "a2q");
1504 Features["power9-vector"] = (CPU == "pwr9");
1505 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1506 .Case("ppc64le", true)
1510 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1511 .Case("ppc64le", true)
1515 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1516 .Case("ppc64le", true)
1521 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1522 .Case("ppc64le", true)
1527 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1528 .Case("ppc64le", true)
1532 Features["vsx"] = llvm::StringSwitch<bool>(CPU)
1533 .Case("ppc64le", true)
1538 Features["htm"] = llvm::StringSwitch<bool>(CPU)
1539 .Case("ppc64le", true)
1544 if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
1547 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1550 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1551 return llvm::StringSwitch<bool>(Feature)
1552 .Case("powerpc", true)
1553 .Case("altivec", HasAltivec)
1554 .Case("vsx", HasVSX)
1555 .Case("power8-vector", HasP8Vector)
1556 .Case("crypto", HasP8Crypto)
1557 .Case("direct-move", HasDirectMove)
1558 .Case("qpx", HasQPX)
1559 .Case("htm", HasHTM)
1560 .Case("bpermd", HasBPERMD)
1561 .Case("extdiv", HasExtDiv)
1562 .Case("float128", HasFloat128)
1563 .Case("power9-vector", HasP9Vector)
1567 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1568 StringRef Name, bool Enabled) const {
1570 // If we're enabling any of the vsx based features then enable vsx and
1571 // altivec. We'll diagnose any problems later.
1572 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name)
1574 .Case("direct-move", true)
1575 .Case("power8-vector", true)
1576 .Case("power9-vector", true)
1577 .Case("float128", true)
1580 Features["vsx"] = Features["altivec"] = true;
1581 if (Name == "power9-vector")
1582 Features["power8-vector"] = true;
1583 Features[Name] = true;
1585 // If we're disabling altivec or vsx go ahead and disable all of the vsx
1587 if ((Name == "altivec") || (Name == "vsx"))
1588 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] =
1589 Features["float128"] = Features["power9-vector"] = false;
1590 if (Name == "power8-vector")
1591 Features["power9-vector"] = false;
1592 Features[Name] = false;
1596 const char * const PPCTargetInfo::GCCRegNames[] = {
1597 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1598 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1599 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1600 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1601 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1602 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1603 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1604 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1605 "mq", "lr", "ctr", "ap",
1606 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1608 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1609 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1610 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1611 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1613 "spe_acc", "spefscr",
1617 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const {
1618 return llvm::makeArrayRef(GCCRegNames);
1621 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1622 // While some of these aliases do map to different registers
1623 // they still share the same register name.
1634 { { "10" }, "r10" },
1635 { { "11" }, "r11" },
1636 { { "12" }, "r12" },
1637 { { "13" }, "r13" },
1638 { { "14" }, "r14" },
1639 { { "15" }, "r15" },
1640 { { "16" }, "r16" },
1641 { { "17" }, "r17" },
1642 { { "18" }, "r18" },
1643 { { "19" }, "r19" },
1644 { { "20" }, "r20" },
1645 { { "21" }, "r21" },
1646 { { "22" }, "r22" },
1647 { { "23" }, "r23" },
1648 { { "24" }, "r24" },
1649 { { "25" }, "r25" },
1650 { { "26" }, "r26" },
1651 { { "27" }, "r27" },
1652 { { "28" }, "r28" },
1653 { { "29" }, "r29" },
1654 { { "30" }, "r30" },
1655 { { "31" }, "r31" },
1656 { { "fr0" }, "f0" },
1657 { { "fr1" }, "f1" },
1658 { { "fr2" }, "f2" },
1659 { { "fr3" }, "f3" },
1660 { { "fr4" }, "f4" },
1661 { { "fr5" }, "f5" },
1662 { { "fr6" }, "f6" },
1663 { { "fr7" }, "f7" },
1664 { { "fr8" }, "f8" },
1665 { { "fr9" }, "f9" },
1666 { { "fr10" }, "f10" },
1667 { { "fr11" }, "f11" },
1668 { { "fr12" }, "f12" },
1669 { { "fr13" }, "f13" },
1670 { { "fr14" }, "f14" },
1671 { { "fr15" }, "f15" },
1672 { { "fr16" }, "f16" },
1673 { { "fr17" }, "f17" },
1674 { { "fr18" }, "f18" },
1675 { { "fr19" }, "f19" },
1676 { { "fr20" }, "f20" },
1677 { { "fr21" }, "f21" },
1678 { { "fr22" }, "f22" },
1679 { { "fr23" }, "f23" },
1680 { { "fr24" }, "f24" },
1681 { { "fr25" }, "f25" },
1682 { { "fr26" }, "f26" },
1683 { { "fr27" }, "f27" },
1684 { { "fr28" }, "f28" },
1685 { { "fr29" }, "f29" },
1686 { { "fr30" }, "f30" },
1687 { { "fr31" }, "f31" },
1688 { { "cc" }, "cr0" },
1691 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
1692 return llvm::makeArrayRef(GCCRegAliases);
1695 class PPC32TargetInfo : public PPCTargetInfo {
1697 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1698 : PPCTargetInfo(Triple, Opts) {
1699 resetDataLayout("E-m:e-p:32:32-i64:64-n32");
1701 switch (getTriple().getOS()) {
1702 case llvm::Triple::Linux:
1703 case llvm::Triple::FreeBSD:
1704 case llvm::Triple::NetBSD:
1705 SizeType = UnsignedInt;
1706 PtrDiffType = SignedInt;
1707 IntPtrType = SignedInt;
1713 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1714 LongDoubleWidth = LongDoubleAlign = 64;
1715 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1718 // PPC32 supports atomics up to 4 bytes.
1719 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1722 BuiltinVaListKind getBuiltinVaListKind() const override {
1723 // This is the ELF definition, and is overridden by the Darwin sub-target
1724 return TargetInfo::PowerABIBuiltinVaList;
1728 // Note: ABI differences may eventually require us to have a separate
1729 // TargetInfo for little endian.
1730 class PPC64TargetInfo : public PPCTargetInfo {
1732 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1733 : PPCTargetInfo(Triple, Opts) {
1734 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1735 IntMaxType = SignedLong;
1736 Int64Type = SignedLong;
1738 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1739 resetDataLayout("e-m:e-i64:64-n32:64");
1742 resetDataLayout("E-m:e-i64:64-n32:64");
1746 switch (getTriple().getOS()) {
1747 case llvm::Triple::FreeBSD:
1748 LongDoubleWidth = LongDoubleAlign = 64;
1749 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1751 case llvm::Triple::NetBSD:
1752 IntMaxType = SignedLongLong;
1753 Int64Type = SignedLongLong;
1759 // PPC64 supports atomics up to 8 bytes.
1760 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1762 BuiltinVaListKind getBuiltinVaListKind() const override {
1763 return TargetInfo::CharPtrBuiltinVaList;
1765 // PPC64 Linux-specific ABI options.
1766 bool setABI(const std::string &Name) override {
1767 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1775 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> {
1777 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1778 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
1779 HasAlignMac68kSupport = true;
1780 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1781 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1783 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
1785 BuiltinVaListKind getBuiltinVaListKind() const override {
1786 return TargetInfo::CharPtrBuiltinVaList;
1790 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> {
1792 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1793 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
1794 HasAlignMac68kSupport = true;
1795 resetDataLayout("E-m:o-i64:64-n32:64");
1799 static const unsigned NVPTXAddrSpaceMap[] = {
1803 4, // opencl_constant
1804 // FIXME: generic has to be added to the target
1805 0, // opencl_generic
1811 class NVPTXTargetInfo : public TargetInfo {
1812 static const char *const GCCRegNames[];
1813 static const Builtin::Info BuiltinInfo[];
1815 std::unique_ptr<TargetInfo> HostTarget;
1818 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts,
1819 unsigned TargetPointerWidth)
1820 : TargetInfo(Triple) {
1821 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) &&
1822 "NVPTX only supports 32- and 64-bit modes.");
1824 TLSSupported = false;
1825 AddrSpaceMap = &NVPTXAddrSpaceMap;
1826 UseAddrSpaceMapMangling = true;
1828 // Define available target features
1829 // These must be defined in sorted order!
1830 NoAsmVariants = true;
1831 GPU = CudaArch::SM_20;
1833 if (TargetPointerWidth == 32)
1834 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64");
1836 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64");
1838 // If possible, get a TargetInfo for our host triple, so we can match its
1840 llvm::Triple HostTriple(Opts.HostTriple);
1841 if (!HostTriple.isNVPTX())
1842 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts));
1844 // If no host target, make some guesses about the data layout and return.
1846 LongWidth = LongAlign = TargetPointerWidth;
1847 PointerWidth = PointerAlign = TargetPointerWidth;
1848 switch (TargetPointerWidth) {
1850 SizeType = TargetInfo::UnsignedInt;
1851 PtrDiffType = TargetInfo::SignedInt;
1852 IntPtrType = TargetInfo::SignedInt;
1855 SizeType = TargetInfo::UnsignedLong;
1856 PtrDiffType = TargetInfo::SignedLong;
1857 IntPtrType = TargetInfo::SignedLong;
1860 llvm_unreachable("TargetPointerWidth must be 32 or 64");
1865 // Copy properties from host target.
1866 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0);
1867 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0);
1868 BoolWidth = HostTarget->getBoolWidth();
1869 BoolAlign = HostTarget->getBoolAlign();
1870 IntWidth = HostTarget->getIntWidth();
1871 IntAlign = HostTarget->getIntAlign();
1872 HalfWidth = HostTarget->getHalfWidth();
1873 HalfAlign = HostTarget->getHalfAlign();
1874 FloatWidth = HostTarget->getFloatWidth();
1875 FloatAlign = HostTarget->getFloatAlign();
1876 DoubleWidth = HostTarget->getDoubleWidth();
1877 DoubleAlign = HostTarget->getDoubleAlign();
1878 LongWidth = HostTarget->getLongWidth();
1879 LongAlign = HostTarget->getLongAlign();
1880 LongLongWidth = HostTarget->getLongLongWidth();
1881 LongLongAlign = HostTarget->getLongLongAlign();
1882 MinGlobalAlign = HostTarget->getMinGlobalAlign();
1883 NewAlign = HostTarget->getNewAlign();
1884 DefaultAlignForAttributeAligned =
1885 HostTarget->getDefaultAlignForAttributeAligned();
1886 SizeType = HostTarget->getSizeType();
1887 IntMaxType = HostTarget->getIntMaxType();
1888 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0);
1889 IntPtrType = HostTarget->getIntPtrType();
1890 WCharType = HostTarget->getWCharType();
1891 WIntType = HostTarget->getWIntType();
1892 Char16Type = HostTarget->getChar16Type();
1893 Char32Type = HostTarget->getChar32Type();
1894 Int64Type = HostTarget->getInt64Type();
1895 SigAtomicType = HostTarget->getSigAtomicType();
1896 ProcessIDType = HostTarget->getProcessIDType();
1898 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
1899 UseZeroLengthBitfieldAlignment =
1900 HostTarget->useZeroLengthBitfieldAlignment();
1901 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
1902 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
1904 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
1905 // we need those macros to be identical on host and device, because (among
1906 // other things) they affect which standard library classes are defined, and
1907 // we need all classes to be defined on both the host and device.
1908 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
1910 // Properties intentionally not copied from host:
1911 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the
1912 // host/device boundary.
1913 // - SuitableAlign: Not visible across the host/device boundary, and may
1914 // correctly be different on host/device, e.g. if host has wider vector
1915 // types than device.
1916 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same
1917 // as its double type, but that's not necessarily true on the host.
1918 // TODO: nvcc emits a warning when using long double on device; we should
1921 void getTargetDefines(const LangOptions &Opts,
1922 MacroBuilder &Builder) const override {
1923 Builder.defineMacro("__PTX__");
1924 Builder.defineMacro("__NVPTX__");
1925 if (Opts.CUDAIsDevice) {
1926 // Set __CUDA_ARCH__ for the GPU specified.
1927 std::string CUDAArchCode = [this] {
1929 case CudaArch::UNKNOWN:
1930 assert(false && "No GPU arch when compiling CUDA device code.");
1932 case CudaArch::SM_20:
1934 case CudaArch::SM_21:
1936 case CudaArch::SM_30:
1938 case CudaArch::SM_32:
1940 case CudaArch::SM_35:
1942 case CudaArch::SM_37:
1944 case CudaArch::SM_50:
1946 case CudaArch::SM_52:
1948 case CudaArch::SM_53:
1950 case CudaArch::SM_60:
1952 case CudaArch::SM_61:
1954 case CudaArch::SM_62:
1957 llvm_unreachable("unhandled CudaArch");
1959 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1962 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1963 return llvm::makeArrayRef(BuiltinInfo,
1964 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin);
1967 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
1969 const std::vector<std::string> &FeaturesVec) const override {
1970 Features["satom"] = GPU >= CudaArch::SM_60;
1971 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1974 bool hasFeature(StringRef Feature) const override {
1975 return llvm::StringSwitch<bool>(Feature)
1976 .Cases("ptx", "nvptx", true)
1977 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope.
1981 ArrayRef<const char *> getGCCRegNames() const override;
1982 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1986 bool validateAsmConstraint(const char *&Name,
1987 TargetInfo::ConstraintInfo &Info) const override {
1997 Info.setAllowsRegister();
2001 const char *getClobbers() const override {
2002 // FIXME: Is this really right?
2005 BuiltinVaListKind getBuiltinVaListKind() const override {
2007 return TargetInfo::CharPtrBuiltinVaList;
2009 bool setCPU(const std::string &Name) override {
2010 GPU = StringToCudaArch(Name);
2011 return GPU != CudaArch::UNKNOWN;
2013 void setSupportedOpenCLOpts() override {
2014 auto &Opts = getSupportedOpenCLOpts();
2015 Opts.support("cl_clang_storage_class_specifiers");
2016 Opts.support("cl_khr_gl_sharing");
2017 Opts.support("cl_khr_icd");
2019 Opts.support("cl_khr_fp64");
2020 Opts.support("cl_khr_byte_addressable_store");
2021 Opts.support("cl_khr_global_int32_base_atomics");
2022 Opts.support("cl_khr_global_int32_extended_atomics");
2023 Opts.support("cl_khr_local_int32_base_atomics");
2024 Opts.support("cl_khr_local_int32_extended_atomics");
2027 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2028 // CUDA compilations support all of the host's calling conventions.
2030 // TODO: We should warn if you apply a non-default CC to anything other than
2033 return HostTarget->checkCallingConvention(CC);
2034 return CCCR_Warning;
2038 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
2039 #define BUILTIN(ID, TYPE, ATTRS) \
2040 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2041 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
2042 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
2043 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2044 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2045 #include "clang/Basic/BuiltinsNVPTX.def"
2048 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
2050 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
2051 return llvm::makeArrayRef(GCCRegNames);
2054 static const LangAS::Map AMDGPUPrivIsZeroDefIsGenMap = {
2058 2, // opencl_constant
2059 4, // opencl_generic
2064 static const LangAS::Map AMDGPUGenIsZeroDefIsGenMap = {
2068 2, // opencl_constant
2069 0, // opencl_generic
2074 static const LangAS::Map AMDGPUPrivIsZeroDefIsPrivMap = {
2078 2, // opencl_constant
2079 4, // opencl_generic
2084 static const LangAS::Map AMDGPUGenIsZeroDefIsPrivMap = {
2088 2, // opencl_constant
2089 0, // opencl_generic
2095 // If you edit the description strings, make sure you update
2096 // getPointerWidthV().
2098 static const char *const DataLayoutStringR600 =
2099 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2100 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
2102 static const char *const DataLayoutStringSIPrivateIsZero =
2103 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
2104 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2105 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
2107 static const char *const DataLayoutStringSIGenericIsZero =
2108 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
2109 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2110 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
2112 class AMDGPUTargetInfo final : public TargetInfo {
2113 static const Builtin::Info BuiltinInfo[];
2114 static const char * const GCCRegNames[];
2117 unsigned Generic, Global, Local, Constant, Private;
2118 AddrSpace(bool IsGenericZero_ = false){
2119 if (IsGenericZero_) {
2135 /// \brief The GPU profiles supported by the AMDGPU target.
2143 GK_EVERGREEN_DOUBLE_OPS,
2144 GK_NORTHERN_ISLANDS,
2157 static bool hasFullSpeedFMAF32(StringRef GPUName) {
2158 return parseAMDGCNName(GPUName) >= GK_GFX9;
2161 static bool isAMDGCN(const llvm::Triple &TT) {
2162 return TT.getArch() == llvm::Triple::amdgcn;
2165 static bool isGenericZero(const llvm::Triple &TT) {
2166 return TT.getEnvironmentName() == "amdgiz" ||
2167 TT.getEnvironmentName() == "amdgizcl";
2170 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
2171 : TargetInfo(Triple) ,
2172 GPU(isAMDGCN(Triple) ? GK_GFX6 : parseR600Name(Opts.CPU)),
2176 AS(isGenericZero(Triple)){
2177 if (getTriple().getArch() == llvm::Triple::amdgcn) {
2182 if (getTriple().getArch() == llvm::Triple::r600) {
2183 if (GPU == GK_EVERGREEN_DOUBLE_OPS || GPU == GK_CAYMAN) {
2188 auto IsGenericZero = isGenericZero(Triple);
2189 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ?
2190 (IsGenericZero ? DataLayoutStringSIGenericIsZero :
2191 DataLayoutStringSIPrivateIsZero)
2192 : DataLayoutStringR600);
2193 assert(DataLayout->getAllocaAddrSpace() == AS.Private);
2195 setAddressSpaceMap(Triple.getOS() == llvm::Triple::Mesa3D ||
2196 Triple.getEnvironment() == llvm::Triple::OpenCL ||
2197 Triple.getEnvironmentName() == "amdgizcl" ||
2199 UseAddrSpaceMapMangling = true;
2201 // Set pointer width and alignment for target address space 0.
2202 PointerWidth = PointerAlign = DataLayout->getPointerSizeInBits();
2203 if (getMaxPointerWidth() == 64) {
2204 LongWidth = LongAlign = 64;
2205 SizeType = UnsignedLong;
2206 PtrDiffType = SignedLong;
2207 IntPtrType = SignedLong;
2211 void setAddressSpaceMap(bool DefaultIsPrivate) {
2212 if (isGenericZero(getTriple())) {
2213 AddrSpaceMap = DefaultIsPrivate ? &AMDGPUGenIsZeroDefIsPrivMap
2214 : &AMDGPUGenIsZeroDefIsGenMap;
2216 AddrSpaceMap = DefaultIsPrivate ? &AMDGPUPrivIsZeroDefIsPrivMap
2217 : &AMDGPUPrivIsZeroDefIsGenMap;
2221 void adjust(LangOptions &Opts) override {
2222 TargetInfo::adjust(Opts);
2223 setAddressSpaceMap(Opts.OpenCL || !isAMDGCN(getTriple()));
2226 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
2227 if (GPU <= GK_CAYMAN)
2230 if (AddrSpace == AS.Private || AddrSpace == AS.Local) {
2236 uint64_t getPointerAlignV(unsigned AddrSpace) const override {
2237 return getPointerWidthV(AddrSpace);
2240 uint64_t getMaxPointerWidth() const override {
2241 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32;
2244 const char * getClobbers() const override {
2248 ArrayRef<const char *> getGCCRegNames() const override;
2250 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2254 bool validateAsmConstraint(const char *&Name,
2255 TargetInfo::ConstraintInfo &Info) const override {
2260 Info.setAllowsRegister();
2266 bool initFeatureMap(llvm::StringMap<bool> &Features,
2267 DiagnosticsEngine &Diags, StringRef CPU,
2268 const std::vector<std::string> &FeatureVec) const override;
2270 void adjustTargetOptions(const CodeGenOptions &CGOpts,
2271 TargetOptions &TargetOpts) const override {
2272 bool hasFP32Denormals = false;
2273 bool hasFP64Denormals = false;
2274 for (auto &I : TargetOpts.FeaturesAsWritten) {
2275 if (I == "+fp32-denormals" || I == "-fp32-denormals")
2276 hasFP32Denormals = true;
2277 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals")
2278 hasFP64Denormals = true;
2280 if (!hasFP32Denormals)
2281 TargetOpts.Features.push_back(
2282 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) &&
2283 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str());
2284 // Always do not flush fp64 or fp16 denorms.
2285 if (!hasFP64Denormals && hasFP64)
2286 TargetOpts.Features.push_back("+fp64-fp16-denormals");
2289 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
2290 return llvm::makeArrayRef(BuiltinInfo,
2291 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin);
2294 void getTargetDefines(const LangOptions &Opts,
2295 MacroBuilder &Builder) const override {
2296 if (getTriple().getArch() == llvm::Triple::amdgcn)
2297 Builder.defineMacro("__AMDGCN__");
2299 Builder.defineMacro("__R600__");
2302 Builder.defineMacro("__HAS_FMAF__");
2304 Builder.defineMacro("__HAS_LDEXPF__");
2306 Builder.defineMacro("__HAS_FP64__");
2309 BuiltinVaListKind getBuiltinVaListKind() const override {
2310 return TargetInfo::CharPtrBuiltinVaList;
2313 static GPUKind parseR600Name(StringRef Name) {
2314 return llvm::StringSwitch<GPUKind>(Name)
2315 .Case("r600" , GK_R600)
2316 .Case("rv610", GK_R600)
2317 .Case("rv620", GK_R600)
2318 .Case("rv630", GK_R600)
2319 .Case("rv635", GK_R600)
2320 .Case("rs780", GK_R600)
2321 .Case("rs880", GK_R600)
2322 .Case("rv670", GK_R600_DOUBLE_OPS)
2323 .Case("rv710", GK_R700)
2324 .Case("rv730", GK_R700)
2325 .Case("rv740", GK_R700_DOUBLE_OPS)
2326 .Case("rv770", GK_R700_DOUBLE_OPS)
2327 .Case("palm", GK_EVERGREEN)
2328 .Case("cedar", GK_EVERGREEN)
2329 .Case("sumo", GK_EVERGREEN)
2330 .Case("sumo2", GK_EVERGREEN)
2331 .Case("redwood", GK_EVERGREEN)
2332 .Case("juniper", GK_EVERGREEN)
2333 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
2334 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
2335 .Case("barts", GK_NORTHERN_ISLANDS)
2336 .Case("turks", GK_NORTHERN_ISLANDS)
2337 .Case("caicos", GK_NORTHERN_ISLANDS)
2338 .Case("cayman", GK_CAYMAN)
2339 .Case("aruba", GK_CAYMAN)
2343 static GPUKind parseAMDGCNName(StringRef Name) {
2344 return llvm::StringSwitch<GPUKind>(Name)
2345 .Case("tahiti", GK_GFX6)
2346 .Case("pitcairn", GK_GFX6)
2347 .Case("verde", GK_GFX6)
2348 .Case("oland", GK_GFX6)
2349 .Case("hainan", GK_GFX6)
2350 .Case("bonaire", GK_GFX7)
2351 .Case("kabini", GK_GFX7)
2352 .Case("kaveri", GK_GFX7)
2353 .Case("hawaii", GK_GFX7)
2354 .Case("mullins", GK_GFX7)
2355 .Case("gfx700", GK_GFX7)
2356 .Case("gfx701", GK_GFX7)
2357 .Case("gfx702", GK_GFX7)
2358 .Case("tonga", GK_GFX8)
2359 .Case("iceland", GK_GFX8)
2360 .Case("carrizo", GK_GFX8)
2361 .Case("fiji", GK_GFX8)
2362 .Case("stoney", GK_GFX8)
2363 .Case("polaris10", GK_GFX8)
2364 .Case("polaris11", GK_GFX8)
2365 .Case("gfx800", GK_GFX8)
2366 .Case("gfx801", GK_GFX8)
2367 .Case("gfx802", GK_GFX8)
2368 .Case("gfx803", GK_GFX8)
2369 .Case("gfx804", GK_GFX8)
2370 .Case("gfx810", GK_GFX8)
2371 .Case("gfx900", GK_GFX9)
2372 .Case("gfx901", GK_GFX9)
2376 bool setCPU(const std::string &Name) override {
2377 if (getTriple().getArch() == llvm::Triple::amdgcn)
2378 GPU = parseAMDGCNName(Name);
2380 GPU = parseR600Name(Name);
2382 return GPU != GK_NONE;
2385 void setSupportedOpenCLOpts() override {
2386 auto &Opts = getSupportedOpenCLOpts();
2387 Opts.support("cl_clang_storage_class_specifiers");
2388 Opts.support("cl_khr_icd");
2391 Opts.support("cl_khr_fp64");
2392 if (GPU >= GK_EVERGREEN) {
2393 Opts.support("cl_khr_byte_addressable_store");
2394 Opts.support("cl_khr_global_int32_base_atomics");
2395 Opts.support("cl_khr_global_int32_extended_atomics");
2396 Opts.support("cl_khr_local_int32_base_atomics");
2397 Opts.support("cl_khr_local_int32_extended_atomics");
2399 if (GPU >= GK_GFX6) {
2400 Opts.support("cl_khr_fp16");
2401 Opts.support("cl_khr_int64_base_atomics");
2402 Opts.support("cl_khr_int64_extended_atomics");
2403 Opts.support("cl_khr_mipmap_image");
2404 Opts.support("cl_khr_subgroups");
2405 Opts.support("cl_khr_3d_image_writes");
2406 Opts.support("cl_amd_media_ops");
2407 Opts.support("cl_amd_media_ops2");
2411 LangAS::ID getOpenCLImageAddrSpace() const override {
2412 return LangAS::opencl_constant;
2415 llvm::Optional<unsigned> getConstantAddressSpace() const override {
2416 return LangAS::FirstTargetAddressSpace + AS.Constant;
2419 /// \returns Target specific vtbl ptr address space.
2420 unsigned getVtblPtrAddressSpace() const override { return AS.Constant; }
2422 /// \returns If a target requires an address within a target specific address
2423 /// space \p AddressSpace to be converted in order to be used, then return the
2424 /// corresponding target specific DWARF address space.
2426 /// \returns Otherwise return None and no conversion will be emitted in the
2428 Optional<unsigned> getDWARFAddressSpace(
2429 unsigned AddressSpace) const override {
2430 const unsigned DWARF_Private = 1;
2431 const unsigned DWARF_Local = 2;
2432 if (AddressSpace == AS.Private) {
2433 return DWARF_Private;
2434 } else if (AddressSpace == AS.Local) {
2441 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2444 return CCCR_Warning;
2446 case CC_OpenCLKernel:
2451 // In amdgcn target the null pointer in global, constant, and generic
2452 // address space has value 0 but in private and local address space has
2454 uint64_t getNullPointerValue(unsigned AS) const override {
2455 return AS == LangAS::opencl_local ? ~0 : 0;
2459 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
2460 #define BUILTIN(ID, TYPE, ATTRS) \
2461 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2462 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2463 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2464 #include "clang/Basic/BuiltinsAMDGPU.def"
2466 const char * const AMDGPUTargetInfo::GCCRegNames[] = {
2467 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2468 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2469 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2470 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
2471 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
2472 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
2473 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
2474 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
2475 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
2476 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
2477 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
2478 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
2479 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
2480 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
2481 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
2482 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
2483 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
2484 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
2485 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
2486 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
2487 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
2488 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
2489 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
2490 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
2491 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
2492 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
2493 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
2494 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
2495 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
2496 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
2497 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
2498 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
2499 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2500 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
2501 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
2502 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
2503 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
2504 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
2505 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
2506 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
2507 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
2508 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
2509 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
2510 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
2511 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
2512 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
2513 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
2514 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127",
2515 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi",
2516 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi"
2519 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const {
2520 return llvm::makeArrayRef(GCCRegNames);
2523 bool AMDGPUTargetInfo::initFeatureMap(
2524 llvm::StringMap<bool> &Features,
2525 DiagnosticsEngine &Diags, StringRef CPU,
2526 const std::vector<std::string> &FeatureVec) const {
2528 // XXX - What does the member GPU mean if device name string passed here?
2529 if (getTriple().getArch() == llvm::Triple::amdgcn) {
2533 switch (parseAMDGCNName(CPU)) {
2539 Features["gfx9-insts"] = true;
2542 Features["s-memrealtime"] = true;
2543 Features["16-bit-insts"] = true;
2544 Features["dpp"] = true;
2550 llvm_unreachable("unhandled subtarget");
2556 switch (parseR600Name(CPU)) {
2560 case GK_NORTHERN_ISLANDS:
2562 case GK_R600_DOUBLE_OPS:
2563 case GK_R700_DOUBLE_OPS:
2564 case GK_EVERGREEN_DOUBLE_OPS:
2566 Features["fp64"] = true;
2571 llvm_unreachable("unhandled subtarget");
2575 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec);
2578 const Builtin::Info BuiltinInfoX86[] = {
2579 #define BUILTIN(ID, TYPE, ATTRS) \
2580 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2581 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2582 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2583 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
2584 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
2585 #include "clang/Basic/BuiltinsX86.def"
2587 #define BUILTIN(ID, TYPE, ATTRS) \
2588 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2589 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2590 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2591 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
2592 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
2593 #include "clang/Basic/BuiltinsX86_64.def"
2597 static const char* const GCCRegNames[] = {
2598 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
2599 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
2600 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
2601 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
2602 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
2603 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2604 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
2605 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
2606 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
2607 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23",
2608 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31",
2609 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23",
2610 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31",
2611 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7",
2612 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15",
2613 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23",
2614 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31",
2615 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7",
2618 const TargetInfo::AddlRegName AddlRegNames[] = {
2619 { { "al", "ah", "eax", "rax" }, 0 },
2620 { { "bl", "bh", "ebx", "rbx" }, 3 },
2621 { { "cl", "ch", "ecx", "rcx" }, 2 },
2622 { { "dl", "dh", "edx", "rdx" }, 1 },
2623 { { "esi", "rsi" }, 4 },
2624 { { "edi", "rdi" }, 5 },
2625 { { "esp", "rsp" }, 7 },
2626 { { "ebp", "rbp" }, 6 },
2627 { { "r8d", "r8w", "r8b" }, 38 },
2628 { { "r9d", "r9w", "r9b" }, 39 },
2629 { { "r10d", "r10w", "r10b" }, 40 },
2630 { { "r11d", "r11w", "r11b" }, 41 },
2631 { { "r12d", "r12w", "r12b" }, 42 },
2632 { { "r13d", "r13w", "r13b" }, 43 },
2633 { { "r14d", "r14w", "r14b" }, 44 },
2634 { { "r15d", "r15w", "r15b" }, 45 },
2637 // X86 target abstract base class; x86-32 and x86-64 are very close, so
2638 // most of the implementation can be shared.
2639 class X86TargetInfo : public TargetInfo {
2641 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
2644 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
2645 } MMX3DNowLevel = NoMMX3DNow;
2653 bool HasAES = false;
2654 bool HasPCLMUL = false;
2655 bool HasLZCNT = false;
2656 bool HasRDRND = false;
2657 bool HasFSGSBASE = false;
2658 bool HasBMI = false;
2659 bool HasBMI2 = false;
2660 bool HasPOPCNT = false;
2661 bool HasRTM = false;
2662 bool HasPRFCHW = false;
2663 bool HasRDSEED = false;
2664 bool HasADX = false;
2665 bool HasTBM = false;
2666 bool HasLWP = false;
2667 bool HasFMA = false;
2668 bool HasF16C = false;
2669 bool HasAVX512CD = false;
2670 bool HasAVX512VPOPCNTDQ = false;
2671 bool HasAVX512ER = false;
2672 bool HasAVX512PF = false;
2673 bool HasAVX512DQ = false;
2674 bool HasAVX512BW = false;
2675 bool HasAVX512VL = false;
2676 bool HasAVX512VBMI = false;
2677 bool HasAVX512IFMA = false;
2678 bool HasSHA = false;
2679 bool HasMPX = false;
2680 bool HasSGX = false;
2681 bool HasCX16 = false;
2682 bool HasFXSR = false;
2683 bool HasXSAVE = false;
2684 bool HasXSAVEOPT = false;
2685 bool HasXSAVEC = false;
2686 bool HasXSAVES = false;
2687 bool HasMWAITX = false;
2688 bool HasCLZERO = false;
2689 bool HasPKU = false;
2690 bool HasCLFLUSHOPT = false;
2691 bool HasCLWB = false;
2692 bool HasMOVBE = false;
2693 bool HasPREFETCHWT1 = false;
2695 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2697 /// Each enumeration represents a particular CPU supported by Clang. These
2698 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2703 /// i386-generation processors.
2709 /// i486-generation processors.
2718 /// i586-generation processors, P5 microarchitecture based.
2726 /// i686-generation processors, P6 / Pentium M microarchitecture based.
2736 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2737 /// Clang however has some logic to support this.
2738 // FIXME: Warn, deprecate, and potentially remove this.
2743 /// Netburst microarchitecture based processors.
2752 /// Core microarchitecture based processors.
2756 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2757 /// codename which GCC no longer accepts as an option to -march, but Clang
2758 /// has some logic for recognizing it.
2759 // FIXME: Warn, deprecate, and potentially remove this.
2772 /// Nehalem microarchitecture based processors.
2776 /// Westmere microarchitecture based processors.
2779 /// \name Sandy Bridge
2780 /// Sandy Bridge microarchitecture based processors.
2783 /// \name Ivy Bridge
2784 /// Ivy Bridge microarchitecture based processors.
2788 /// Haswell microarchitecture based processors.
2792 /// Broadwell microarchitecture based processors.
2795 /// \name Skylake Client
2796 /// Skylake client microarchitecture based processors.
2799 /// \name Skylake Server
2800 /// Skylake server microarchitecture based processors.
2803 /// \name Cannonlake Client
2804 /// Cannonlake client microarchitecture based processors.
2807 /// \name Knights Landing
2808 /// Knights Landing processor.
2812 /// Lakemont microarchitecture based processors.
2816 /// K6 architecture processors.
2824 /// K7 architecture processors.
2827 CK_AthlonThunderbird,
2834 /// K8 architecture processors.
2847 /// Bobcat architecture processors.
2854 /// Bulldozer architecture processors.
2863 /// Zen architecture processors.
2868 /// This specification is deprecated and will be removed in the future.
2869 /// Users should prefer \see CK_K8.
2870 // FIXME: Warn on this when the CPU is set to it.
2876 /// Geode processors.
2882 CPUKind getCPUKind(StringRef CPU) const {
2883 return llvm::StringSwitch<CPUKind>(CPU)
2884 .Case("i386", CK_i386)
2885 .Case("i486", CK_i486)
2886 .Case("winchip-c6", CK_WinChipC6)
2887 .Case("winchip2", CK_WinChip2)
2889 .Case("i586", CK_i586)
2890 .Case("pentium", CK_Pentium)
2891 .Case("pentium-mmx", CK_PentiumMMX)
2892 .Case("i686", CK_i686)
2893 .Case("pentiumpro", CK_PentiumPro)
2894 .Case("pentium2", CK_Pentium2)
2895 .Case("pentium3", CK_Pentium3)
2896 .Case("pentium3m", CK_Pentium3M)
2897 .Case("pentium-m", CK_PentiumM)
2898 .Case("c3-2", CK_C3_2)
2899 .Case("yonah", CK_Yonah)
2900 .Case("pentium4", CK_Pentium4)
2901 .Case("pentium4m", CK_Pentium4M)
2902 .Case("prescott", CK_Prescott)
2903 .Case("nocona", CK_Nocona)
2904 .Case("core2", CK_Core2)
2905 .Case("penryn", CK_Penryn)
2906 .Case("bonnell", CK_Bonnell)
2907 .Case("atom", CK_Bonnell) // Legacy name.
2908 .Case("silvermont", CK_Silvermont)
2909 .Case("slm", CK_Silvermont) // Legacy name.
2910 .Case("goldmont", CK_Goldmont)
2911 .Case("nehalem", CK_Nehalem)
2912 .Case("corei7", CK_Nehalem) // Legacy name.
2913 .Case("westmere", CK_Westmere)
2914 .Case("sandybridge", CK_SandyBridge)
2915 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2916 .Case("ivybridge", CK_IvyBridge)
2917 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2918 .Case("haswell", CK_Haswell)
2919 .Case("core-avx2", CK_Haswell) // Legacy name.
2920 .Case("broadwell", CK_Broadwell)
2921 .Case("skylake", CK_SkylakeClient)
2922 .Case("skylake-avx512", CK_SkylakeServer)
2923 .Case("skx", CK_SkylakeServer) // Legacy name.
2924 .Case("cannonlake", CK_Cannonlake)
2925 .Case("knl", CK_KNL)
2926 .Case("lakemont", CK_Lakemont)
2928 .Case("k6-2", CK_K6_2)
2929 .Case("k6-3", CK_K6_3)
2930 .Case("athlon", CK_Athlon)
2931 .Case("athlon-tbird", CK_AthlonThunderbird)
2932 .Case("athlon-4", CK_Athlon4)
2933 .Case("athlon-xp", CK_AthlonXP)
2934 .Case("athlon-mp", CK_AthlonMP)
2935 .Case("athlon64", CK_Athlon64)
2936 .Case("athlon64-sse3", CK_Athlon64SSE3)
2937 .Case("athlon-fx", CK_AthlonFX)
2939 .Case("k8-sse3", CK_K8SSE3)
2940 .Case("opteron", CK_Opteron)
2941 .Case("opteron-sse3", CK_OpteronSSE3)
2942 .Case("barcelona", CK_AMDFAM10)
2943 .Case("amdfam10", CK_AMDFAM10)
2944 .Case("btver1", CK_BTVER1)
2945 .Case("btver2", CK_BTVER2)
2946 .Case("bdver1", CK_BDVER1)
2947 .Case("bdver2", CK_BDVER2)
2948 .Case("bdver3", CK_BDVER3)
2949 .Case("bdver4", CK_BDVER4)
2950 .Case("znver1", CK_ZNVER1)
2951 .Case("x86-64", CK_x86_64)
2952 .Case("geode", CK_Geode)
2953 .Default(CK_Generic);
2960 } FPMath = FP_Default;
2963 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
2964 : TargetInfo(Triple) {
2965 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
2967 unsigned getFloatEvalMethod() const override {
2968 // X87 evaluates with 80 bits "long double" precision.
2969 return SSELevel == NoSSE ? 2 : 0;
2971 ArrayRef<const char *> getGCCRegNames() const override {
2972 return llvm::makeArrayRef(GCCRegNames);
2974 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2977 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
2978 return llvm::makeArrayRef(AddlRegNames);
2980 bool validateCpuSupports(StringRef Name) const override;
2981 bool validateAsmConstraint(const char *&Name,
2982 TargetInfo::ConstraintInfo &info) const override;
2984 bool validateGlobalRegisterVariable(StringRef RegName,
2986 bool &HasSizeMismatch) const override {
2987 // esp and ebp are the only 32-bit registers the x86 backend can currently
2989 if (RegName.equals("esp") || RegName.equals("ebp")) {
2990 // Check that the register size is 32-bit.
2991 HasSizeMismatch = RegSize != 32;
2998 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
3000 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
3002 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
3004 std::string convertConstraint(const char *&Constraint) const override;
3005 const char *getClobbers() const override {
3006 return "~{dirflag},~{fpsr},~{flags}";
3009 StringRef getConstraintRegister(const StringRef &Constraint,
3010 const StringRef &Expression) const override {
3011 StringRef::iterator I, E;
3012 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) {
3019 // For the register constraints, return the matching register name
3032 // In case the constraint is 'r' we need to return Expression
3036 // Default value if there is no constraint for the register
3042 void getTargetDefines(const LangOptions &Opts,
3043 MacroBuilder &Builder) const override;
3044 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
3046 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
3048 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
3050 void setFeatureEnabled(llvm::StringMap<bool> &Features,
3051 StringRef Name, bool Enabled) const override {
3052 setFeatureEnabledImpl(Features, Name, Enabled);
3054 // This exists purely to cut down on the number of virtual calls in
3055 // initFeatureMap which calls this repeatedly.
3056 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
3057 StringRef Name, bool Enabled);
3059 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
3061 const std::vector<std::string> &FeaturesVec) const override;
3062 bool hasFeature(StringRef Feature) const override;
3063 bool handleTargetFeatures(std::vector<std::string> &Features,
3064 DiagnosticsEngine &Diags) override;
3065 StringRef getABI() const override {
3066 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
3068 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
3070 if (getTriple().getArch() == llvm::Triple::x86 &&
3071 MMX3DNowLevel == NoMMX3DNow)
3075 bool setCPU(const std::string &Name) override {
3076 CPU = getCPUKind(Name);
3078 // Perform any per-CPU checks necessary to determine if this CPU is
3080 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
3081 // invalid without explaining *why*.
3084 // No processor selected!
3111 case CK_AthlonThunderbird:
3116 // Only accept certain architectures when compiling in 32-bit mode.
3117 if (getTriple().getArch() != llvm::Triple::x86)
3129 case CK_SandyBridge:
3133 case CK_SkylakeClient:
3134 case CK_SkylakeServer:
3138 case CK_Athlon64SSE3:
3143 case CK_OpteronSSE3:
3155 llvm_unreachable("Unhandled CPU kind");
3158 bool setFPMath(StringRef Name) override;
3160 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3161 // Most of the non-ARM calling conventions are i386 conventions.
3163 case CC_X86ThisCall:
3164 case CC_X86FastCall:
3166 case CC_X86VectorCall:
3171 case CC_IntelOclBicc:
3172 case CC_OpenCLKernel:
3175 return CCCR_Warning;
3179 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3180 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
3183 bool hasSjLjLowering() const override {
3187 void setSupportedOpenCLOpts() override {
3188 getSupportedOpenCLOpts().supportAll();
3192 bool X86TargetInfo::setFPMath(StringRef Name) {
3193 if (Name == "387") {
3197 if (Name == "sse") {
3204 bool X86TargetInfo::initFeatureMap(
3205 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
3206 const std::vector<std::string> &FeaturesVec) const {
3207 // FIXME: This *really* should not be here.
3208 // X86_64 always has SSE2.
3209 if (getTriple().getArch() == llvm::Triple::x86_64)
3210 setFeatureEnabledImpl(Features, "sse2", true);
3212 const CPUKind Kind = getCPUKind(CPU);
3214 // Enable X87 for all X86 processors but Lakemont.
3215 if (Kind != CK_Lakemont)
3216 setFeatureEnabledImpl(Features, "x87", true);
3232 setFeatureEnabledImpl(Features, "mmx", true);
3237 setFeatureEnabledImpl(Features, "sse", true);
3238 setFeatureEnabledImpl(Features, "fxsr", true);
3244 setFeatureEnabledImpl(Features, "sse2", true);
3245 setFeatureEnabledImpl(Features, "fxsr", true);
3250 setFeatureEnabledImpl(Features, "sse3", true);
3251 setFeatureEnabledImpl(Features, "fxsr", true);
3252 setFeatureEnabledImpl(Features, "cx16", true);
3255 setFeatureEnabledImpl(Features, "ssse3", true);
3256 setFeatureEnabledImpl(Features, "fxsr", true);
3257 setFeatureEnabledImpl(Features, "cx16", true);
3260 setFeatureEnabledImpl(Features, "sse4.1", true);
3261 setFeatureEnabledImpl(Features, "fxsr", true);
3262 setFeatureEnabledImpl(Features, "cx16", true);
3265 setFeatureEnabledImpl(Features, "avx512ifma", true);
3266 setFeatureEnabledImpl(Features, "avx512vbmi", true);
3267 setFeatureEnabledImpl(Features, "sha", true);
3269 case CK_SkylakeServer:
3270 setFeatureEnabledImpl(Features, "avx512f", true);
3271 setFeatureEnabledImpl(Features, "avx512cd", true);
3272 setFeatureEnabledImpl(Features, "avx512dq", true);
3273 setFeatureEnabledImpl(Features, "avx512bw", true);
3274 setFeatureEnabledImpl(Features, "avx512vl", true);
3275 setFeatureEnabledImpl(Features, "pku", true);
3276 setFeatureEnabledImpl(Features, "clwb", true);
3278 case CK_SkylakeClient:
3279 setFeatureEnabledImpl(Features, "xsavec", true);
3280 setFeatureEnabledImpl(Features, "xsaves", true);
3281 setFeatureEnabledImpl(Features, "mpx", true);
3282 setFeatureEnabledImpl(Features, "sgx", true);
3283 setFeatureEnabledImpl(Features, "clflushopt", true);
3284 setFeatureEnabledImpl(Features, "rtm", true);
3287 setFeatureEnabledImpl(Features, "rdseed", true);
3288 setFeatureEnabledImpl(Features, "adx", true);
3291 setFeatureEnabledImpl(Features, "avx2", true);
3292 setFeatureEnabledImpl(Features, "lzcnt", true);
3293 setFeatureEnabledImpl(Features, "bmi", true);
3294 setFeatureEnabledImpl(Features, "bmi2", true);
3295 setFeatureEnabledImpl(Features, "fma", true);
3296 setFeatureEnabledImpl(Features, "movbe", true);
3299 setFeatureEnabledImpl(Features, "rdrnd", true);
3300 setFeatureEnabledImpl(Features, "f16c", true);
3301 setFeatureEnabledImpl(Features, "fsgsbase", true);
3303 case CK_SandyBridge:
3304 setFeatureEnabledImpl(Features, "avx", true);
3305 setFeatureEnabledImpl(Features, "xsave", true);
3306 setFeatureEnabledImpl(Features, "xsaveopt", true);
3309 setFeatureEnabledImpl(Features, "aes", true);
3310 setFeatureEnabledImpl(Features, "pclmul", true);
3313 setFeatureEnabledImpl(Features, "sse4.2", true);
3314 setFeatureEnabledImpl(Features, "fxsr", true);
3315 setFeatureEnabledImpl(Features, "cx16", true);
3318 setFeatureEnabledImpl(Features, "sha", true);
3319 setFeatureEnabledImpl(Features, "rdrnd", true);
3320 setFeatureEnabledImpl(Features, "rdseed", true);
3321 setFeatureEnabledImpl(Features, "xsave", true);
3322 setFeatureEnabledImpl(Features, "xsaveopt", true);
3323 setFeatureEnabledImpl(Features, "xsavec", true);
3324 setFeatureEnabledImpl(Features, "xsaves", true);
3325 setFeatureEnabledImpl(Features, "clflushopt", true);
3326 setFeatureEnabledImpl(Features, "mpx", true);
3329 setFeatureEnabledImpl(Features, "aes", true);
3330 setFeatureEnabledImpl(Features, "pclmul", true);
3331 setFeatureEnabledImpl(Features, "sse4.2", true);
3334 setFeatureEnabledImpl(Features, "movbe", true);
3335 setFeatureEnabledImpl(Features, "ssse3", true);
3336 setFeatureEnabledImpl(Features, "fxsr", true);
3337 setFeatureEnabledImpl(Features, "cx16", true);
3340 setFeatureEnabledImpl(Features, "avx512f", true);
3341 setFeatureEnabledImpl(Features, "avx512cd", true);
3342 setFeatureEnabledImpl(Features, "avx512er", true);
3343 setFeatureEnabledImpl(Features, "avx512pf", true);
3344 setFeatureEnabledImpl(Features, "prefetchwt1", true);
3345 setFeatureEnabledImpl(Features, "fxsr", true);
3346 setFeatureEnabledImpl(Features, "rdseed", true);
3347 setFeatureEnabledImpl(Features, "adx", true);
3348 setFeatureEnabledImpl(Features, "lzcnt", true);
3349 setFeatureEnabledImpl(Features, "bmi", true);
3350 setFeatureEnabledImpl(Features, "bmi2", true);
3351 setFeatureEnabledImpl(Features, "rtm", true);
3352 setFeatureEnabledImpl(Features, "fma", true);
3353 setFeatureEnabledImpl(Features, "rdrnd", true);
3354 setFeatureEnabledImpl(Features, "f16c", true);
3355 setFeatureEnabledImpl(Features, "fsgsbase", true);
3356 setFeatureEnabledImpl(Features, "aes", true);
3357 setFeatureEnabledImpl(Features, "pclmul", true);
3358 setFeatureEnabledImpl(Features, "cx16", true);
3359 setFeatureEnabledImpl(Features, "xsaveopt", true);
3360 setFeatureEnabledImpl(Features, "xsave", true);
3361 setFeatureEnabledImpl(Features, "movbe", true);
3367 setFeatureEnabledImpl(Features, "3dnow", true);
3370 case CK_AthlonThunderbird:
3372 setFeatureEnabledImpl(Features, "3dnowa", true);
3377 setFeatureEnabledImpl(Features, "sse", true);
3378 setFeatureEnabledImpl(Features, "3dnowa", true);
3379 setFeatureEnabledImpl(Features, "fxsr", true);
3385 setFeatureEnabledImpl(Features, "sse2", true);
3386 setFeatureEnabledImpl(Features, "3dnowa", true);
3387 setFeatureEnabledImpl(Features, "fxsr", true);
3390 setFeatureEnabledImpl(Features, "sse4a", true);
3391 setFeatureEnabledImpl(Features, "lzcnt", true);
3392 setFeatureEnabledImpl(Features, "popcnt", true);
3395 case CK_OpteronSSE3:
3396 case CK_Athlon64SSE3:
3397 setFeatureEnabledImpl(Features, "sse3", true);
3398 setFeatureEnabledImpl(Features, "3dnowa", true);
3399 setFeatureEnabledImpl(Features, "fxsr", true);
3402 setFeatureEnabledImpl(Features, "avx", true);
3403 setFeatureEnabledImpl(Features, "aes", true);
3404 setFeatureEnabledImpl(Features, "pclmul", true);
3405 setFeatureEnabledImpl(Features, "bmi", true);
3406 setFeatureEnabledImpl(Features, "f16c", true);
3407 setFeatureEnabledImpl(Features, "xsaveopt", true);
3408 setFeatureEnabledImpl(Features, "movbe", true);
3411 setFeatureEnabledImpl(Features, "ssse3", true);
3412 setFeatureEnabledImpl(Features, "sse4a", true);
3413 setFeatureEnabledImpl(Features, "lzcnt", true);
3414 setFeatureEnabledImpl(Features, "popcnt", true);
3415 setFeatureEnabledImpl(Features, "prfchw", true);
3416 setFeatureEnabledImpl(Features, "cx16", true);
3417 setFeatureEnabledImpl(Features, "fxsr", true);
3420 setFeatureEnabledImpl(Features, "adx", true);
3421 setFeatureEnabledImpl(Features, "aes", true);
3422 setFeatureEnabledImpl(Features, "avx2", true);
3423 setFeatureEnabledImpl(Features, "bmi", true);
3424 setFeatureEnabledImpl(Features, "bmi2", true);
3425 setFeatureEnabledImpl(Features, "clflushopt", true);
3426 setFeatureEnabledImpl(Features, "clzero", true);
3427 setFeatureEnabledImpl(Features, "cx16", true);
3428 setFeatureEnabledImpl(Features, "f16c", true);
3429 setFeatureEnabledImpl(Features, "fma", true);
3430 setFeatureEnabledImpl(Features, "fsgsbase", true);
3431 setFeatureEnabledImpl(Features, "fxsr", true);
3432 setFeatureEnabledImpl(Features, "lzcnt", true);
3433 setFeatureEnabledImpl(Features, "mwaitx", true);
3434 setFeatureEnabledImpl(Features, "movbe", true);
3435 setFeatureEnabledImpl(Features, "pclmul", true);
3436 setFeatureEnabledImpl(Features, "popcnt", true);
3437 setFeatureEnabledImpl(Features, "prfchw", true);
3438 setFeatureEnabledImpl(Features, "rdrnd", true);
3439 setFeatureEnabledImpl(Features, "rdseed", true);
3440 setFeatureEnabledImpl(Features, "sha", true);
3441 setFeatureEnabledImpl(Features, "sse4a", true);
3442 setFeatureEnabledImpl(Features, "xsave", true);
3443 setFeatureEnabledImpl(Features, "xsavec", true);
3444 setFeatureEnabledImpl(Features, "xsaveopt", true);
3445 setFeatureEnabledImpl(Features, "xsaves", true);
3448 setFeatureEnabledImpl(Features, "avx2", true);
3449 setFeatureEnabledImpl(Features, "bmi2", true);
3450 setFeatureEnabledImpl(Features, "mwaitx", true);
3453 setFeatureEnabledImpl(Features, "fsgsbase", true);
3454 setFeatureEnabledImpl(Features, "xsaveopt", true);
3457 setFeatureEnabledImpl(Features, "bmi", true);
3458 setFeatureEnabledImpl(Features, "fma", true);
3459 setFeatureEnabledImpl(Features, "f16c", true);
3460 setFeatureEnabledImpl(Features, "tbm", true);
3463 // xop implies avx, sse4a and fma4.
3464 setFeatureEnabledImpl(Features, "xop", true);
3465 setFeatureEnabledImpl(Features, "lwp", true);
3466 setFeatureEnabledImpl(Features, "lzcnt", true);
3467 setFeatureEnabledImpl(Features, "aes", true);
3468 setFeatureEnabledImpl(Features, "pclmul", true);
3469 setFeatureEnabledImpl(Features, "prfchw", true);
3470 setFeatureEnabledImpl(Features, "cx16", true);
3471 setFeatureEnabledImpl(Features, "fxsr", true);
3472 setFeatureEnabledImpl(Features, "xsave", true);
3475 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
3478 // Can't do this earlier because we need to be able to explicitly enable
3479 // or disable these features and the things that they depend upon.
3481 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
3482 auto I = Features.find("sse4.2");
3483 if (I != Features.end() && I->getValue() &&
3484 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
3486 Features["popcnt"] = true;
3488 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
3489 I = Features.find("3dnow");
3490 if (I != Features.end() && I->getValue() &&
3491 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
3493 Features["prfchw"] = true;
3495 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
3497 I = Features.find("sse");
3498 if (I != Features.end() && I->getValue() &&
3499 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
3501 Features["mmx"] = true;
3506 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
3507 X86SSEEnum Level, bool Enabled) {
3511 Features["avx512f"] = true;
3514 Features["avx2"] = true;
3517 Features["avx"] = true;
3518 Features["xsave"] = true;
3521 Features["sse4.2"] = true;
3524 Features["sse4.1"] = true;
3527 Features["ssse3"] = true;
3530 Features["sse3"] = true;
3533 Features["sse2"] = true;
3536 Features["sse"] = true;
3547 Features["sse"] = false;
3550 Features["sse2"] = Features["pclmul"] = Features["aes"] =
3551 Features["sha"] = false;
3554 Features["sse3"] = false;
3555 setXOPLevel(Features, NoXOP, false);
3558 Features["ssse3"] = false;
3561 Features["sse4.1"] = false;
3564 Features["sse4.2"] = false;
3567 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
3568 Features["xsaveopt"] = false;
3569 setXOPLevel(Features, FMA4, false);
3572 Features["avx2"] = false;
3575 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
3576 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
3577 Features["avx512vl"] = Features["avx512vbmi"] =
3578 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false;
3583 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
3584 MMX3DNowEnum Level, bool Enabled) {
3587 case AMD3DNowAthlon:
3588 Features["3dnowa"] = true;
3591 Features["3dnow"] = true;
3594 Features["mmx"] = true;
3605 Features["mmx"] = false;
3608 Features["3dnow"] = false;
3610 case AMD3DNowAthlon:
3611 Features["3dnowa"] = false;
3616 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
3621 Features["xop"] = true;
3624 Features["fma4"] = true;
3625 setSSELevel(Features, AVX, true);
3628 Features["sse4a"] = true;
3629 setSSELevel(Features, SSE3, true);
3640 Features["sse4a"] = false;
3643 Features["fma4"] = false;
3646 Features["xop"] = false;
3651 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
3652 StringRef Name, bool Enabled) {
3653 // This is a bit of a hack to deal with the sse4 target feature when used
3654 // as part of the target attribute. We handle sse4 correctly everywhere
3655 // else. See below for more information on how we handle the sse4 options.
3657 Features[Name] = Enabled;
3659 if (Name == "mmx") {
3660 setMMXLevel(Features, MMX, Enabled);
3661 } else if (Name == "sse") {
3662 setSSELevel(Features, SSE1, Enabled);
3663 } else if (Name == "sse2") {
3664 setSSELevel(Features, SSE2, Enabled);
3665 } else if (Name == "sse3") {
3666 setSSELevel(Features, SSE3, Enabled);
3667 } else if (Name == "ssse3") {
3668 setSSELevel(Features, SSSE3, Enabled);
3669 } else if (Name == "sse4.2") {
3670 setSSELevel(Features, SSE42, Enabled);
3671 } else if (Name == "sse4.1") {
3672 setSSELevel(Features, SSE41, Enabled);
3673 } else if (Name == "3dnow") {
3674 setMMXLevel(Features, AMD3DNow, Enabled);
3675 } else if (Name == "3dnowa") {
3676 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
3677 } else if (Name == "aes") {
3679 setSSELevel(Features, SSE2, Enabled);
3680 } else if (Name == "pclmul") {
3682 setSSELevel(Features, SSE2, Enabled);
3683 } else if (Name == "avx") {
3684 setSSELevel(Features, AVX, Enabled);
3685 } else if (Name == "avx2") {
3686 setSSELevel(Features, AVX2, Enabled);
3687 } else if (Name == "avx512f") {
3688 setSSELevel(Features, AVX512F, Enabled);
3689 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
3690 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
3691 Name == "avx512vbmi" || Name == "avx512ifma" ||
3692 Name == "avx512vpopcntdq") {
3694 setSSELevel(Features, AVX512F, Enabled);
3695 // Enable BWI instruction if VBMI is being enabled.
3696 if (Name == "avx512vbmi" && Enabled)
3697 Features["avx512bw"] = true;
3698 // Also disable VBMI if BWI is being disabled.
3699 if (Name == "avx512bw" && !Enabled)
3700 Features["avx512vbmi"] = false;
3701 } else if (Name == "fma") {
3703 setSSELevel(Features, AVX, Enabled);
3704 } else if (Name == "fma4") {
3705 setXOPLevel(Features, FMA4, Enabled);
3706 } else if (Name == "xop") {
3707 setXOPLevel(Features, XOP, Enabled);
3708 } else if (Name == "sse4a") {
3709 setXOPLevel(Features, SSE4A, Enabled);
3710 } else if (Name == "f16c") {
3712 setSSELevel(Features, AVX, Enabled);
3713 } else if (Name == "sha") {
3715 setSSELevel(Features, SSE2, Enabled);
3716 } else if (Name == "sse4") {
3717 // We can get here via the __target__ attribute since that's not controlled
3718 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
3719 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
3722 setSSELevel(Features, SSE42, Enabled);
3724 setSSELevel(Features, SSE41, Enabled);
3725 } else if (Name == "xsave") {
3727 Features["xsaveopt"] = false;
3728 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
3730 Features["xsave"] = true;
3734 /// handleTargetFeatures - Perform initialization based on the user
3735 /// configured set of features.
3736 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
3737 DiagnosticsEngine &Diags) {
3738 for (const auto &Feature : Features) {
3739 if (Feature[0] != '+')
3742 if (Feature == "+aes") {
3744 } else if (Feature == "+pclmul") {
3746 } else if (Feature == "+lzcnt") {
3748 } else if (Feature == "+rdrnd") {
3750 } else if (Feature == "+fsgsbase") {
3752 } else if (Feature == "+bmi") {
3754 } else if (Feature == "+bmi2") {
3756 } else if (Feature == "+popcnt") {
3758 } else if (Feature == "+rtm") {
3760 } else if (Feature == "+prfchw") {
3762 } else if (Feature == "+rdseed") {
3764 } else if (Feature == "+adx") {
3766 } else if (Feature == "+tbm") {
3768 } else if (Feature == "+lwp") {
3770 } else if (Feature == "+fma") {
3772 } else if (Feature == "+f16c") {
3774 } else if (Feature == "+avx512cd") {
3776 } else if (Feature == "+avx512vpopcntdq") {
3777 HasAVX512VPOPCNTDQ = true;
3778 } else if (Feature == "+avx512er") {
3780 } else if (Feature == "+avx512pf") {
3782 } else if (Feature == "+avx512dq") {
3784 } else if (Feature == "+avx512bw") {
3786 } else if (Feature == "+avx512vl") {
3788 } else if (Feature == "+avx512vbmi") {
3789 HasAVX512VBMI = true;
3790 } else if (Feature == "+avx512ifma") {
3791 HasAVX512IFMA = true;
3792 } else if (Feature == "+sha") {
3794 } else if (Feature == "+mpx") {
3796 } else if (Feature == "+movbe") {
3798 } else if (Feature == "+sgx") {
3800 } else if (Feature == "+cx16") {
3802 } else if (Feature == "+fxsr") {
3804 } else if (Feature == "+xsave") {
3806 } else if (Feature == "+xsaveopt") {
3808 } else if (Feature == "+xsavec") {
3810 } else if (Feature == "+xsaves") {
3812 } else if (Feature == "+mwaitx") {
3814 } else if (Feature == "+pku") {
3816 } else if (Feature == "+clflushopt") {
3817 HasCLFLUSHOPT = true;
3818 } else if (Feature == "+clwb") {
3820 } else if (Feature == "+prefetchwt1") {
3821 HasPREFETCHWT1 = true;
3822 } else if (Feature == "+clzero") {
3826 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
3827 .Case("+avx512f", AVX512F)
3828 .Case("+avx2", AVX2)
3830 .Case("+sse4.2", SSE42)
3831 .Case("+sse4.1", SSE41)
3832 .Case("+ssse3", SSSE3)
3833 .Case("+sse3", SSE3)
3834 .Case("+sse2", SSE2)
3837 SSELevel = std::max(SSELevel, Level);
3839 MMX3DNowEnum ThreeDNowLevel =
3840 llvm::StringSwitch<MMX3DNowEnum>(Feature)
3841 .Case("+3dnowa", AMD3DNowAthlon)
3842 .Case("+3dnow", AMD3DNow)
3844 .Default(NoMMX3DNow);
3845 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
3847 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
3849 .Case("+fma4", FMA4)
3850 .Case("+sse4a", SSE4A)
3852 XOPLevel = std::max(XOPLevel, XLevel);
3855 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
3856 // matches the selected sse level.
3857 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
3858 (FPMath == FP_387 && SSELevel >= SSE1)) {
3859 Diags.Report(diag::err_target_unsupported_fpmath) <<
3860 (FPMath == FP_SSE ? "sse" : "387");
3865 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3869 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
3870 /// definitions for this particular subtarget.
3871 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
3872 MacroBuilder &Builder) const {
3873 // Target identification.
3874 if (getTriple().getArch() == llvm::Triple::x86_64) {
3875 Builder.defineMacro("__amd64__");
3876 Builder.defineMacro("__amd64");
3877 Builder.defineMacro("__x86_64");
3878 Builder.defineMacro("__x86_64__");
3879 if (getTriple().getArchName() == "x86_64h") {
3880 Builder.defineMacro("__x86_64h");
3881 Builder.defineMacro("__x86_64h__");
3884 DefineStd(Builder, "i386", Opts);
3887 // Subtarget options.
3888 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
3889 // truly should be based on -mtune options.
3894 // The rest are coming from the i386 define above.
3895 Builder.defineMacro("__tune_i386__");
3901 defineCPUMacros(Builder, "i486");
3904 Builder.defineMacro("__pentium_mmx__");
3905 Builder.defineMacro("__tune_pentium_mmx__");
3909 defineCPUMacros(Builder, "i586");
3910 defineCPUMacros(Builder, "pentium");
3915 Builder.defineMacro("__tune_pentium3__");
3919 Builder.defineMacro("__tune_pentium2__");
3922 Builder.defineMacro("__tune_i686__");
3923 Builder.defineMacro("__tune_pentiumpro__");
3926 Builder.defineMacro("__i686");
3927 Builder.defineMacro("__i686__");
3928 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3929 Builder.defineMacro("__pentiumpro");
3930 Builder.defineMacro("__pentiumpro__");
3934 defineCPUMacros(Builder, "pentium4");
3939 defineCPUMacros(Builder, "nocona");
3943 defineCPUMacros(Builder, "core2");
3946 defineCPUMacros(Builder, "atom");
3949 defineCPUMacros(Builder, "slm");
3952 defineCPUMacros(Builder, "goldmont");
3956 case CK_SandyBridge:
3960 case CK_SkylakeClient:
3961 // FIXME: Historically, we defined this legacy name, it would be nice to
3962 // remove it at some point. We've never exposed fine-grained names for
3963 // recent primary x86 CPUs, and we should keep it that way.
3964 defineCPUMacros(Builder, "corei7");
3966 case CK_SkylakeServer:
3967 defineCPUMacros(Builder, "skx");
3972 defineCPUMacros(Builder, "knl");
3975 Builder.defineMacro("__tune_lakemont__");
3978 Builder.defineMacro("__k6_2__");
3979 Builder.defineMacro("__tune_k6_2__");
3982 if (CPU != CK_K6_2) { // In case of fallthrough
3983 // FIXME: GCC may be enabling these in cases where some other k6
3984 // architecture is specified but -m3dnow is explicitly provided. The
3985 // exact semantics need to be determined and emulated here.
3986 Builder.defineMacro("__k6_3__");
3987 Builder.defineMacro("__tune_k6_3__");
3991 defineCPUMacros(Builder, "k6");
3994 case CK_AthlonThunderbird:
3998 defineCPUMacros(Builder, "athlon");
3999 if (SSELevel != NoSSE) {
4000 Builder.defineMacro("__athlon_sse__");
4001 Builder.defineMacro("__tune_athlon_sse__");
4008 case CK_OpteronSSE3:
4010 case CK_Athlon64SSE3:
4012 defineCPUMacros(Builder, "k8");
4015 defineCPUMacros(Builder, "amdfam10");
4018 defineCPUMacros(Builder, "btver1");
4021 defineCPUMacros(Builder, "btver2");
4024 defineCPUMacros(Builder, "bdver1");
4027 defineCPUMacros(Builder, "bdver2");
4030 defineCPUMacros(Builder, "bdver3");
4033 defineCPUMacros(Builder, "bdver4");
4036 defineCPUMacros(Builder, "znver1");
4039 defineCPUMacros(Builder, "geode");
4043 // Target properties.
4044 Builder.defineMacro("__REGISTER_PREFIX__", "");
4046 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
4047 // functions in glibc header files that use FP Stack inline asm which the
4048 // backend can't deal with (PR879).
4049 Builder.defineMacro("__NO_MATH_INLINES");
4052 Builder.defineMacro("__AES__");
4055 Builder.defineMacro("__PCLMUL__");
4058 Builder.defineMacro("__LZCNT__");
4061 Builder.defineMacro("__RDRND__");
4064 Builder.defineMacro("__FSGSBASE__");
4067 Builder.defineMacro("__BMI__");
4070 Builder.defineMacro("__BMI2__");
4073 Builder.defineMacro("__POPCNT__");
4076 Builder.defineMacro("__RTM__");
4079 Builder.defineMacro("__PRFCHW__");
4082 Builder.defineMacro("__RDSEED__");
4085 Builder.defineMacro("__ADX__");
4088 Builder.defineMacro("__TBM__");
4091 Builder.defineMacro("__LWP__");
4094 Builder.defineMacro("__MWAITX__");
4098 Builder.defineMacro("__XOP__");
4101 Builder.defineMacro("__FMA4__");
4104 Builder.defineMacro("__SSE4A__");
4111 Builder.defineMacro("__FMA__");
4114 Builder.defineMacro("__F16C__");
4117 Builder.defineMacro("__AVX512CD__");
4118 if (HasAVX512VPOPCNTDQ)
4119 Builder.defineMacro("__AVX512VPOPCNTDQ__");
4121 Builder.defineMacro("__AVX512ER__");
4123 Builder.defineMacro("__AVX512PF__");
4125 Builder.defineMacro("__AVX512DQ__");
4127 Builder.defineMacro("__AVX512BW__");
4129 Builder.defineMacro("__AVX512VL__");
4131 Builder.defineMacro("__AVX512VBMI__");
4133 Builder.defineMacro("__AVX512IFMA__");
4136 Builder.defineMacro("__SHA__");
4139 Builder.defineMacro("__FXSR__");
4141 Builder.defineMacro("__XSAVE__");
4143 Builder.defineMacro("__XSAVEOPT__");
4145 Builder.defineMacro("__XSAVEC__");
4147 Builder.defineMacro("__XSAVES__");
4149 Builder.defineMacro("__PKU__");
4151 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
4153 Builder.defineMacro("__CLFLUSHOPT__");
4155 Builder.defineMacro("__CLWB__");
4157 Builder.defineMacro("__MPX__");
4159 Builder.defineMacro("__SGX__");
4161 Builder.defineMacro("__PREFETCHWT1__");
4163 Builder.defineMacro("__CLZERO__");
4165 // Each case falls through to the previous one here.
4168 Builder.defineMacro("__AVX512F__");
4171 Builder.defineMacro("__AVX2__");
4174 Builder.defineMacro("__AVX__");
4177 Builder.defineMacro("__SSE4_2__");
4180 Builder.defineMacro("__SSE4_1__");
4183 Builder.defineMacro("__SSSE3__");
4186 Builder.defineMacro("__SSE3__");
4189 Builder.defineMacro("__SSE2__");
4190 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
4193 Builder.defineMacro("__SSE__");
4194 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
4200 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
4210 Builder.defineMacro("_M_IX86_FP", Twine(2));
4213 Builder.defineMacro("_M_IX86_FP", Twine(1));
4216 Builder.defineMacro("_M_IX86_FP", Twine(0));
4221 // Each case falls through to the previous one here.
4222 switch (MMX3DNowLevel) {
4223 case AMD3DNowAthlon:
4224 Builder.defineMacro("__3dNOW_A__");
4227 Builder.defineMacro("__3dNOW__");
4230 Builder.defineMacro("__MMX__");
4236 if (CPU >= CK_i486) {
4237 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4238 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4239 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4242 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4245 Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
4248 bool X86TargetInfo::hasFeature(StringRef Feature) const {
4249 return llvm::StringSwitch<bool>(Feature)
4250 .Case("aes", HasAES)
4251 .Case("avx", SSELevel >= AVX)
4252 .Case("avx2", SSELevel >= AVX2)
4253 .Case("avx512f", SSELevel >= AVX512F)
4254 .Case("avx512cd", HasAVX512CD)
4255 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
4256 .Case("avx512er", HasAVX512ER)
4257 .Case("avx512pf", HasAVX512PF)
4258 .Case("avx512dq", HasAVX512DQ)
4259 .Case("avx512bw", HasAVX512BW)
4260 .Case("avx512vl", HasAVX512VL)
4261 .Case("avx512vbmi", HasAVX512VBMI)
4262 .Case("avx512ifma", HasAVX512IFMA)
4263 .Case("bmi", HasBMI)
4264 .Case("bmi2", HasBMI2)
4265 .Case("clflushopt", HasCLFLUSHOPT)
4266 .Case("clwb", HasCLWB)
4267 .Case("clzero", HasCLZERO)
4268 .Case("cx16", HasCX16)
4269 .Case("f16c", HasF16C)
4270 .Case("fma", HasFMA)
4271 .Case("fma4", XOPLevel >= FMA4)
4272 .Case("fsgsbase", HasFSGSBASE)
4273 .Case("fxsr", HasFXSR)
4274 .Case("lzcnt", HasLZCNT)
4275 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
4276 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
4277 .Case("mmx", MMX3DNowLevel >= MMX)
4278 .Case("movbe", HasMOVBE)
4279 .Case("mpx", HasMPX)
4280 .Case("pclmul", HasPCLMUL)
4281 .Case("pku", HasPKU)
4282 .Case("popcnt", HasPOPCNT)
4283 .Case("prefetchwt1", HasPREFETCHWT1)
4284 .Case("prfchw", HasPRFCHW)
4285 .Case("rdrnd", HasRDRND)
4286 .Case("rdseed", HasRDSEED)
4287 .Case("rtm", HasRTM)
4288 .Case("sgx", HasSGX)
4289 .Case("sha", HasSHA)
4290 .Case("sse", SSELevel >= SSE1)
4291 .Case("sse2", SSELevel >= SSE2)
4292 .Case("sse3", SSELevel >= SSE3)
4293 .Case("ssse3", SSELevel >= SSSE3)
4294 .Case("sse4.1", SSELevel >= SSE41)
4295 .Case("sse4.2", SSELevel >= SSE42)
4296 .Case("sse4a", XOPLevel >= SSE4A)
4297 .Case("tbm", HasTBM)
4298 .Case("lwp", HasLWP)
4300 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
4301 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
4302 .Case("xop", XOPLevel >= XOP)
4303 .Case("xsave", HasXSAVE)
4304 .Case("xsavec", HasXSAVEC)
4305 .Case("xsaves", HasXSAVES)
4306 .Case("xsaveopt", HasXSAVEOPT)
4310 // We can't use a generic validation scheme for the features accepted here
4311 // versus subtarget features accepted in the target attribute because the
4312 // bitfield structure that's initialized in the runtime only supports the
4313 // below currently rather than the full range of subtarget features. (See
4314 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
4315 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
4316 return llvm::StringSwitch<bool>(FeatureStr)
4319 .Case("popcnt", true)
4323 .Case("ssse3", true)
4324 .Case("sse4.1", true)
4325 .Case("sse4.2", true)
4328 .Case("sse4a", true)
4332 .Case("avx512f", true)
4336 .Case("pclmul", true)
4337 .Case("avx512vl", true)
4338 .Case("avx512bw", true)
4339 .Case("avx512dq", true)
4340 .Case("avx512cd", true)
4341 .Case("avx512vpopcntdq", true)
4342 .Case("avx512er", true)
4343 .Case("avx512pf", true)
4344 .Case("avx512vbmi", true)
4345 .Case("avx512ifma", true)
4350 X86TargetInfo::validateAsmConstraint(const char *&Name,
4351 TargetInfo::ConstraintInfo &Info) const {
4353 default: return false;
4354 // Constant constraints.
4355 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
4357 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
4358 // x86_64 instructions.
4360 Info.setRequiresImmediate();
4363 Info.setRequiresImmediate(0, 31);
4366 Info.setRequiresImmediate(0, 63);
4369 Info.setRequiresImmediate(-128, 127);
4372 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) });
4375 Info.setRequiresImmediate(0, 3);
4378 Info.setRequiresImmediate(0, 255);
4381 Info.setRequiresImmediate(0, 127);
4383 // Register constraints.
4384 case 'Y': // 'Y' is the first character for several 2-character constraints.
4385 // Shift the pointer to the second character of the constraint.
4390 case '0': // First SSE register.
4391 case 't': // Any SSE register, when SSE2 is enabled.
4392 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
4393 case 'm': // Any MMX register, when inter-unit moves enabled.
4394 case 'k': // AVX512 arch mask registers: k1-k7.
4395 Info.setAllowsRegister();
4398 case 'f': // Any x87 floating point stack register.
4399 // Constraint 'f' cannot be used for output operands.
4400 if (Info.ConstraintStr[0] == '=')
4402 Info.setAllowsRegister();
4410 case 'A': // edx:eax.
4411 case 't': // Top of floating point stack.
4412 case 'u': // Second from top of floating point stack.
4413 case 'q': // Any register accessible as [r]l: a, b, c, and d.
4414 case 'y': // Any MMX register.
4415 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
4416 case 'x': // Any SSE register.
4417 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0
4418 // for intermideate k reg operations).
4419 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
4420 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
4421 case 'l': // "Index" registers: any general register that can be used as an
4422 // index in a base+index memory access.
4423 Info.setAllowsRegister();
4425 // Floating point constant constraints.
4426 case 'C': // SSE floating point constant.
4427 case 'G': // x87 floating point constant.
4432 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
4433 unsigned Size) const {
4434 // Strip off constraint modifiers.
4435 while (Constraint[0] == '=' ||
4436 Constraint[0] == '+' ||
4437 Constraint[0] == '&')
4438 Constraint = Constraint.substr(1);
4440 return validateOperandSize(Constraint, Size);
4443 bool X86TargetInfo::validateInputSize(StringRef Constraint,
4444 unsigned Size) const {
4445 return validateOperandSize(Constraint, Size);
4448 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
4449 unsigned Size) const {
4450 switch (Constraint[0]) {
4453 // Registers k0-k7 (AVX512) size limit is 64 bit.
4462 if (SSELevel >= AVX512F)
4463 // 512-bit zmm registers can be used if target supports AVX512F.
4464 return Size <= 512U;
4465 else if (SSELevel >= AVX)
4466 // 256-bit ymm registers can be used if target supports AVX.
4467 return Size <= 256U;
4468 return Size <= 128U;
4470 // 'Y' is the first character for several 2-character constraints.
4471 switch (Constraint[1]) {
4474 // 'Ym' is synonymous with 'y'.
4479 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
4480 if (SSELevel >= AVX512F)
4481 return Size <= 512U;
4482 else if (SSELevel >= AVX)
4483 return Size <= 256U;
4484 return SSELevel >= SSE2 && Size <= 128U;
4493 X86TargetInfo::convertConstraint(const char *&Constraint) const {
4494 switch (*Constraint) {
4495 case 'a': return std::string("{ax}");
4496 case 'b': return std::string("{bx}");
4497 case 'c': return std::string("{cx}");
4498 case 'd': return std::string("{dx}");
4499 case 'S': return std::string("{si}");
4500 case 'D': return std::string("{di}");
4501 case 'p': // address
4502 return std::string("im");
4503 case 't': // top of floating point stack.
4504 return std::string("{st}");
4505 case 'u': // second from top of floating point stack.
4506 return std::string("{st(1)}"); // second from top of floating point stack.
4508 switch (Constraint[1]) {
4510 // Break from inner switch and fall through (copy single char),
4511 // continue parsing after copying the current constraint into
4512 // the return string.
4515 // "^" hints llvm that this is a 2 letter constraint.
4516 // "Constraint++" is used to promote the string iterator
4517 // to the next constraint.
4518 return std::string("^") + std::string(Constraint++, 2);
4522 return std::string(1, *Constraint);
4526 // X86-32 generic target
4527 class X86_32TargetInfo : public X86TargetInfo {
4529 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4530 : X86TargetInfo(Triple, Opts) {
4531 DoubleAlign = LongLongAlign = 32;
4532 LongDoubleWidth = 96;
4533 LongDoubleAlign = 32;
4534 SuitableAlign = 128;
4535 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128");
4536 SizeType = UnsignedInt;
4537 PtrDiffType = SignedInt;
4538 IntPtrType = SignedInt;
4541 // Use fpret for all types.
4542 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
4543 (1 << TargetInfo::Double) |
4544 (1 << TargetInfo::LongDouble));
4546 // x86-32 has atomics up to 8 bytes
4547 // FIXME: Check that we actually have cmpxchg8b before setting
4548 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
4549 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4551 BuiltinVaListKind getBuiltinVaListKind() const override {
4552 return TargetInfo::CharPtrBuiltinVaList;
4555 int getEHDataRegisterNumber(unsigned RegNo) const override {
4556 if (RegNo == 0) return 0;
4557 if (RegNo == 1) return 2;
4560 bool validateOperandSize(StringRef Constraint,
4561 unsigned Size) const override {
4562 switch (Constraint[0]) {
4578 return X86TargetInfo::validateOperandSize(Constraint, Size);
4580 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4581 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
4582 Builtin::FirstTSBuiltin + 1);
4586 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
4588 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4589 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {}
4591 unsigned getFloatEvalMethod() const override {
4592 unsigned Major, Minor, Micro;
4593 getTriple().getOSVersion(Major, Minor, Micro);
4594 // New NetBSD uses the default rounding mode.
4595 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
4596 return X86_32TargetInfo::getFloatEvalMethod();
4597 // NetBSD before 6.99.26 defaults to "double" rounding.
4602 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
4604 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4605 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4606 SizeType = UnsignedLong;
4607 IntPtrType = SignedLong;
4608 PtrDiffType = SignedLong;
4612 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
4614 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4615 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4616 SizeType = UnsignedLong;
4617 IntPtrType = SignedLong;
4618 PtrDiffType = SignedLong;
4622 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
4624 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4625 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4626 LongDoubleWidth = 128;
4627 LongDoubleAlign = 128;
4628 SuitableAlign = 128;
4629 MaxVectorAlign = 256;
4630 // The watchOS simulator uses the builtin bool type for Objective-C.
4631 llvm::Triple T = llvm::Triple(Triple);
4633 UseSignedCharForObjCBool = false;
4634 SizeType = UnsignedLong;
4635 IntPtrType = SignedLong;
4636 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128");
4637 HasAlignMac68kSupport = true;
4640 bool handleTargetFeatures(std::vector<std::string> &Features,
4641 DiagnosticsEngine &Diags) override {
4642 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features,
4645 // We now know the features we have: we can decide how to align vectors.
4647 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4652 // x86-32 Windows target
4653 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
4655 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4656 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4657 WCharType = UnsignedShort;
4658 DoubleAlign = LongLongAlign = 64;
4660 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4661 resetDataLayout(IsWinCOFF
4662 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
4663 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4665 void getTargetDefines(const LangOptions &Opts,
4666 MacroBuilder &Builder) const override {
4667 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4671 // x86-32 Windows Visual Studio target
4672 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
4674 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple,
4675 const TargetOptions &Opts)
4676 : WindowsX86_32TargetInfo(Triple, Opts) {
4677 LongDoubleWidth = LongDoubleAlign = 64;
4678 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4680 void getTargetDefines(const LangOptions &Opts,
4681 MacroBuilder &Builder) const override {
4682 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4683 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
4684 // The value of the following reflects processor type.
4685 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
4686 // We lost the original triple, so we use the default.
4687 Builder.defineMacro("_M_IX86", "600");
4691 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4692 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang
4693 // supports __declspec natively under -fms-extensions, but we define a no-op
4694 // __declspec macro anyway for pre-processor compatibility.
4695 if (Opts.MicrosoftExt)
4696 Builder.defineMacro("__declspec", "__declspec");
4698 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
4700 if (!Opts.MicrosoftExt) {
4701 // Provide macros for all the calling convention keywords. Provide both
4702 // single and double underscore prefixed variants. These are available on
4703 // x64 as well as x86, even though they have no effect.
4704 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
4705 for (const char *CC : CCs) {
4706 std::string GCCSpelling = "__attribute__((__";
4708 GCCSpelling += "__))";
4709 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
4710 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
4715 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4716 Builder.defineMacro("__MSVCRT__");
4717 Builder.defineMacro("__MINGW32__");
4718 addCygMingDefines(Opts, Builder);
4721 // x86-32 MinGW target
4722 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
4724 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4725 : WindowsX86_32TargetInfo(Triple, Opts) {
4728 void getTargetDefines(const LangOptions &Opts,
4729 MacroBuilder &Builder) const override {
4730 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4731 DefineStd(Builder, "WIN32", Opts);
4732 DefineStd(Builder, "WINNT", Opts);
4733 Builder.defineMacro("_X86_");
4734 addMinGWDefines(Opts, Builder);
4738 // x86-32 Cygwin target
4739 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
4741 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4742 : X86_32TargetInfo(Triple, Opts) {
4743 WCharType = UnsignedShort;
4744 DoubleAlign = LongLongAlign = 64;
4745 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4747 void getTargetDefines(const LangOptions &Opts,
4748 MacroBuilder &Builder) const override {
4749 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4750 Builder.defineMacro("_X86_");
4751 Builder.defineMacro("__CYGWIN__");
4752 Builder.defineMacro("__CYGWIN32__");
4753 addCygMingDefines(Opts, Builder);
4754 DefineStd(Builder, "unix", Opts);
4756 Builder.defineMacro("_GNU_SOURCE");
4760 // x86-32 Haiku target
4761 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> {
4763 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4764 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4766 void getTargetDefines(const LangOptions &Opts,
4767 MacroBuilder &Builder) const override {
4768 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4769 Builder.defineMacro("__INTEL__");
4773 // X86-32 MCU target
4774 class MCUX86_32TargetInfo : public X86_32TargetInfo {
4776 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4777 : X86_32TargetInfo(Triple, Opts) {
4778 LongDoubleWidth = 64;
4779 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4780 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32");
4781 WIntType = UnsignedInt;
4784 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4785 // On MCU we support only C calling convention.
4786 return CC == CC_C ? CCCR_OK : CCCR_Warning;
4789 void getTargetDefines(const LangOptions &Opts,
4790 MacroBuilder &Builder) const override {
4791 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4792 Builder.defineMacro("__iamcu");
4793 Builder.defineMacro("__iamcu__");
4796 bool allowsLargerPreferedTypeAlignment() const override {
4802 template<typename Target>
4803 class RTEMSTargetInfo : public OSTargetInfo<Target> {
4805 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4806 MacroBuilder &Builder) const override {
4807 // RTEMS defines; list based off of gcc output
4809 Builder.defineMacro("__rtems__");
4810 Builder.defineMacro("__ELF__");
4814 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4815 : OSTargetInfo<Target>(Triple, Opts) {
4816 switch (Triple.getArch()) {
4818 case llvm::Triple::x86:
4819 // this->MCountName = ".mcount";
4821 case llvm::Triple::mips:
4822 case llvm::Triple::mipsel:
4823 case llvm::Triple::ppc:
4824 case llvm::Triple::ppc64:
4825 case llvm::Triple::ppc64le:
4826 // this->MCountName = "_mcount";
4828 case llvm::Triple::arm:
4829 // this->MCountName = "__mcount";
4835 // x86-32 RTEMS target
4836 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
4838 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4839 : X86_32TargetInfo(Triple, Opts) {
4840 SizeType = UnsignedLong;
4841 IntPtrType = SignedLong;
4842 PtrDiffType = SignedLong;
4844 void getTargetDefines(const LangOptions &Opts,
4845 MacroBuilder &Builder) const override {
4846 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4847 Builder.defineMacro("__INTEL__");
4848 Builder.defineMacro("__rtems__");
4852 // x86-64 generic target
4853 class X86_64TargetInfo : public X86TargetInfo {
4855 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4856 : X86TargetInfo(Triple, Opts) {
4857 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
4859 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4860 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
4861 LongDoubleWidth = 128;
4862 LongDoubleAlign = 128;
4863 LargeArrayMinWidth = 128;
4864 LargeArrayAlign = 128;
4865 SuitableAlign = 128;
4866 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
4867 PtrDiffType = IsX32 ? SignedInt : SignedLong;
4868 IntPtrType = IsX32 ? SignedInt : SignedLong;
4869 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
4870 Int64Type = IsX32 ? SignedLongLong : SignedLong;
4873 // Pointers are 32-bit in x32.
4874 resetDataLayout(IsX32
4875 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
4876 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
4877 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128");
4879 // Use fpret only for long double.
4880 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
4882 // Use fp2ret for _Complex long double.
4883 ComplexLongDoubleUsesFP2Ret = true;
4885 // Make __builtin_ms_va_list available.
4886 HasBuiltinMSVaList = true;
4888 // x86-64 has atomics up to 16 bytes.
4889 MaxAtomicPromoteWidth = 128;
4890 MaxAtomicInlineWidth = 128;
4892 BuiltinVaListKind getBuiltinVaListKind() const override {
4893 return TargetInfo::X86_64ABIBuiltinVaList;
4896 int getEHDataRegisterNumber(unsigned RegNo) const override {
4897 if (RegNo == 0) return 0;
4898 if (RegNo == 1) return 1;
4902 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4906 case CC_X86VectorCall:
4907 case CC_IntelOclBicc:
4909 case CC_PreserveMost:
4910 case CC_PreserveAll:
4912 case CC_OpenCLKernel:
4915 return CCCR_Warning;
4919 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
4923 // for x32 we need it here explicitly
4924 bool hasInt128Type() const override { return true; }
4925 unsigned getUnwindWordWidth() const override { return 64; }
4926 unsigned getRegisterWidth() const override { return 64; }
4928 bool validateGlobalRegisterVariable(StringRef RegName,
4930 bool &HasSizeMismatch) const override {
4931 // rsp and rbp are the only 64-bit registers the x86 backend can currently
4933 if (RegName.equals("rsp") || RegName.equals("rbp")) {
4934 // Check that the register size is 64-bit.
4935 HasSizeMismatch = RegSize != 64;
4939 // Check if the register is a 32-bit register the backend can handle.
4940 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize,
4943 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4944 return llvm::makeArrayRef(BuiltinInfoX86,
4945 X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
4949 // x86-64 Windows target
4950 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
4952 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4953 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4954 WCharType = UnsignedShort;
4955 LongWidth = LongAlign = 32;
4956 DoubleAlign = LongLongAlign = 64;
4957 IntMaxType = SignedLongLong;
4958 Int64Type = SignedLongLong;
4959 SizeType = UnsignedLongLong;
4960 PtrDiffType = SignedLongLong;
4961 IntPtrType = SignedLongLong;
4964 void getTargetDefines(const LangOptions &Opts,
4965 MacroBuilder &Builder) const override {
4966 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
4967 Builder.defineMacro("_WIN64");
4970 BuiltinVaListKind getBuiltinVaListKind() const override {
4971 return TargetInfo::CharPtrBuiltinVaList;
4974 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4977 case CC_X86ThisCall:
4978 case CC_X86FastCall:
4981 case CC_X86VectorCall:
4982 case CC_IntelOclBicc:
4986 case CC_OpenCLKernel:
4989 return CCCR_Warning;
4994 // x86-64 Windows Visual Studio target
4995 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
4997 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple,
4998 const TargetOptions &Opts)
4999 : WindowsX86_64TargetInfo(Triple, Opts) {
5000 LongDoubleWidth = LongDoubleAlign = 64;
5001 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
5003 void getTargetDefines(const LangOptions &Opts,
5004 MacroBuilder &Builder) const override {
5005 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
5006 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
5007 Builder.defineMacro("_M_X64", "100");
5008 Builder.defineMacro("_M_AMD64", "100");
5012 // x86-64 MinGW target
5013 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
5015 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5016 : WindowsX86_64TargetInfo(Triple, Opts) {
5017 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
5018 // with x86 FP ops. Weird.
5019 LongDoubleWidth = LongDoubleAlign = 128;
5020 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
5024 void getTargetDefines(const LangOptions &Opts,
5025 MacroBuilder &Builder) const override {
5026 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
5027 DefineStd(Builder, "WIN64", Opts);
5028 Builder.defineMacro("__MINGW64__");
5029 addMinGWDefines(Opts, Builder);
5031 // GCC defines this macro when it is using __gxx_personality_seh0.
5032 if (!Opts.SjLjExceptions)
5033 Builder.defineMacro("__SEH__");
5037 // x86-64 Cygwin target
5038 class CygwinX86_64TargetInfo : public X86_64TargetInfo {
5040 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5041 : X86_64TargetInfo(Triple, Opts) {
5042 TLSSupported = false;
5043 WCharType = UnsignedShort;
5045 void getTargetDefines(const LangOptions &Opts,
5046 MacroBuilder &Builder) const override {
5047 X86_64TargetInfo::getTargetDefines(Opts, Builder);
5048 Builder.defineMacro("__x86_64__");
5049 Builder.defineMacro("__CYGWIN__");
5050 Builder.defineMacro("__CYGWIN64__");
5051 addCygMingDefines(Opts, Builder);
5052 DefineStd(Builder, "unix", Opts);
5054 Builder.defineMacro("_GNU_SOURCE");
5056 // GCC defines this macro when it is using __gxx_personality_seh0.
5057 if (!Opts.SjLjExceptions)
5058 Builder.defineMacro("__SEH__");
5062 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
5064 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5065 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) {
5066 Int64Type = SignedLongLong;
5067 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
5068 llvm::Triple T = llvm::Triple(Triple);
5070 UseSignedCharForObjCBool = false;
5071 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128");
5074 bool handleTargetFeatures(std::vector<std::string> &Features,
5075 DiagnosticsEngine &Diags) override {
5076 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features,
5079 // We now know the features we have: we can decide how to align vectors.
5081 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
5086 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
5088 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5089 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) {
5090 IntMaxType = SignedLongLong;
5091 Int64Type = SignedLongLong;
5095 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
5097 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5098 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) {
5099 IntMaxType = SignedLongLong;
5100 Int64Type = SignedLongLong;
5104 class ARMTargetInfo : public TargetInfo {
5105 // Possible FPU choices.
5114 // Possible HWDiv features.
5116 HWDivThumb = (1 << 0),
5120 static bool FPUModeIsVFP(FPUMode Mode) {
5121 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
5124 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5125 static const char * const GCCRegNames[];
5127 std::string ABI, CPU;
5129 StringRef CPUProfile;
5139 unsigned ArchKind = llvm::ARM::AK_ARMV4T;
5140 unsigned ArchProfile;
5141 unsigned ArchVersion;
5145 unsigned IsAAPCS : 1;
5148 // Initialized via features.
5149 unsigned SoftFloat : 1;
5150 unsigned SoftFloatABI : 1;
5153 unsigned Crypto : 1;
5155 unsigned Unaligned : 1;
5158 LDREX_B = (1 << 0), /// byte (8-bit)
5159 LDREX_H = (1 << 1), /// half (16-bit)
5160 LDREX_W = (1 << 2), /// word (32-bit)
5161 LDREX_D = (1 << 3), /// double (64-bit)
5166 // ACLE 6.5.1 Hardware floating point
5168 HW_FP_HP = (1 << 1), /// half (16-bit)
5169 HW_FP_SP = (1 << 2), /// single (32-bit)
5170 HW_FP_DP = (1 << 3), /// double (64-bit)
5174 static const Builtin::Info BuiltinInfo[];
5176 void setABIAAPCS() {
5179 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
5180 const llvm::Triple &T = getTriple();
5182 // size_t is unsigned long on MachO-derived environments, NetBSD,
5183 // OpenBSD and Bitrig.
5184 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
5185 T.getOS() == llvm::Triple::OpenBSD ||
5186 T.getOS() == llvm::Triple::Bitrig)
5187 SizeType = UnsignedLong;
5189 SizeType = UnsignedInt;
5191 switch (T.getOS()) {
5192 case llvm::Triple::NetBSD:
5193 case llvm::Triple::OpenBSD:
5194 WCharType = SignedInt;
5196 case llvm::Triple::Win32:
5197 WCharType = UnsignedShort;
5199 case llvm::Triple::Linux:
5201 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
5202 WCharType = UnsignedInt;
5206 UseBitFieldTypeAlignment = true;
5208 ZeroLengthBitfieldBoundary = 0;
5210 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
5211 // so set preferred for small types to 32.
5212 if (T.isOSBinFormatMachO()) {
5213 resetDataLayout(BigEndian
5214 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
5215 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
5216 } else if (T.isOSWindows()) {
5217 assert(!BigEndian && "Windows on ARM does not support big endian");
5226 } else if (T.isOSNaCl()) {
5227 assert(!BigEndian && "NaCl on ARM does not support big endian");
5228 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128");
5230 resetDataLayout(BigEndian
5231 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
5232 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
5235 // FIXME: Enumerated types are variable width in straight AAPCS.
5238 void setABIAPCS(bool IsAAPCS16) {
5239 const llvm::Triple &T = getTriple();
5244 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
5246 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
5248 // size_t is unsigned int on FreeBSD.
5249 if (T.getOS() == llvm::Triple::FreeBSD)
5250 SizeType = UnsignedInt;
5252 SizeType = UnsignedLong;
5254 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
5255 WCharType = SignedInt;
5257 // Do not respect the alignment of bit-field types when laying out
5258 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
5259 UseBitFieldTypeAlignment = false;
5261 /// gcc forces the alignment to 4 bytes, regardless of the type of the
5262 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
5264 ZeroLengthBitfieldBoundary = 32;
5266 if (T.isOSBinFormatMachO() && IsAAPCS16) {
5267 assert(!BigEndian && "AAPCS16 does not support big-endian");
5268 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128");
5269 } else if (T.isOSBinFormatMachO())
5272 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
5273 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
5277 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
5278 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
5280 // FIXME: Override "preferred align" for double and long long.
5283 void setArchInfo() {
5284 StringRef ArchName = getTriple().getArchName();
5286 ArchISA = llvm::ARM::parseArchISA(ArchName);
5287 CPU = llvm::ARM::getDefaultCPU(ArchName);
5288 unsigned AK = llvm::ARM::parseArch(ArchName);
5289 if (AK != llvm::ARM::AK_INVALID)
5291 setArchInfo(ArchKind);
5294 void setArchInfo(unsigned Kind) {
5297 // cache TargetParser info
5299 SubArch = llvm::ARM::getSubArch(ArchKind);
5300 ArchProfile = llvm::ARM::parseArchProfile(SubArch);
5301 ArchVersion = llvm::ARM::parseArchVersion(SubArch);
5303 // cache CPU related strings
5304 CPUAttr = getCPUAttr();
5305 CPUProfile = getCPUProfile();
5309 // when triple does not specify a sub arch,
5310 // then we are not using inline atomics
5311 bool ShouldUseInlineAtomic =
5312 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) ||
5313 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
5314 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
5315 if (ArchProfile == llvm::ARM::PK_M) {
5316 MaxAtomicPromoteWidth = 32;
5317 if (ShouldUseInlineAtomic)
5318 MaxAtomicInlineWidth = 32;
5321 MaxAtomicPromoteWidth = 64;
5322 if (ShouldUseInlineAtomic)
5323 MaxAtomicInlineWidth = 64;
5327 bool isThumb() const {
5328 return (ArchISA == llvm::ARM::IK_THUMB);
5331 bool supportsThumb() const {
5332 return CPUAttr.count('T') || ArchVersion >= 6;
5335 bool supportsThumb2() const {
5336 return CPUAttr.equals("6T2") ||
5337 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE"));
5340 StringRef getCPUAttr() const {
5341 // For most sub-arches, the build attribute CPU name is enough.
5342 // For Cortex variants, it's slightly different.
5345 return llvm::ARM::getCPUAttr(ArchKind);
5346 case llvm::ARM::AK_ARMV6M:
5348 case llvm::ARM::AK_ARMV7S:
5350 case llvm::ARM::AK_ARMV7A:
5352 case llvm::ARM::AK_ARMV7R:
5354 case llvm::ARM::AK_ARMV7M:
5356 case llvm::ARM::AK_ARMV7EM:
5358 case llvm::ARM::AK_ARMV7VE:
5360 case llvm::ARM::AK_ARMV8A:
5362 case llvm::ARM::AK_ARMV8_1A:
5364 case llvm::ARM::AK_ARMV8_2A:
5366 case llvm::ARM::AK_ARMV8MBaseline:
5368 case llvm::ARM::AK_ARMV8MMainline:
5370 case llvm::ARM::AK_ARMV8R:
5375 StringRef getCPUProfile() const {
5376 switch(ArchProfile) {
5377 case llvm::ARM::PK_A:
5379 case llvm::ARM::PK_R:
5381 case llvm::ARM::PK_M:
5389 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5390 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0),
5393 switch (getTriple().getOS()) {
5394 case llvm::Triple::NetBSD:
5395 case llvm::Triple::OpenBSD:
5396 PtrDiffType = SignedLong;
5399 PtrDiffType = SignedInt;
5403 // Cache arch related info.
5406 // {} in inline assembly are neon specifiers, not assembly variant
5408 NoAsmVariants = true;
5410 // FIXME: This duplicates code from the driver that sets the -target-abi
5411 // option - this code is used if -target-abi isn't passed and should
5412 // be unified in some way.
5413 if (Triple.isOSBinFormatMachO()) {
5414 // The backend is hardwired to assume AAPCS for M-class processors, ensure
5415 // the frontend matches that.
5416 if (Triple.getEnvironment() == llvm::Triple::EABI ||
5417 Triple.getOS() == llvm::Triple::UnknownOS ||
5418 ArchProfile == llvm::ARM::PK_M) {
5420 } else if (Triple.isWatchABI()) {
5425 } else if (Triple.isOSWindows()) {
5426 // FIXME: this is invalid for WindowsCE
5429 // Select the default based on the platform.
5430 switch (Triple.getEnvironment()) {
5431 case llvm::Triple::Android:
5432 case llvm::Triple::GNUEABI:
5433 case llvm::Triple::GNUEABIHF:
5434 case llvm::Triple::MuslEABI:
5435 case llvm::Triple::MuslEABIHF:
5436 setABI("aapcs-linux");
5438 case llvm::Triple::EABIHF:
5439 case llvm::Triple::EABI:
5442 case llvm::Triple::GNU:
5446 if (Triple.getOS() == llvm::Triple::NetBSD)
5448 else if (Triple.getOS() == llvm::Triple::OpenBSD)
5449 setABI("aapcs-linux");
5456 // ARM targets default to using the ARM C++ ABI.
5457 TheCXXABI.set(TargetCXXABI::GenericARM);
5459 // ARM has atomics up to 8 bytes
5462 // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS)
5463 if (IsAAPCS && (Triple.getEnvironment() != llvm::Triple::Android))
5464 MaxVectorAlign = 64;
5466 // Do force alignment of members that follow zero length bitfields. If
5467 // the alignment of the zero-length bitfield is greater than the member
5468 // that follows it, `bar', `bar' will be aligned as the type of the
5469 // zero length bitfield.
5470 UseZeroLengthBitfieldAlignment = true;
5472 if (Triple.getOS() == llvm::Triple::Linux ||
5473 Triple.getOS() == llvm::Triple::UnknownOS)
5475 Opts.EABIVersion == llvm::EABI::GNU ? "\01__gnu_mcount_nc" : "\01mcount";
5478 StringRef getABI() const override { return ABI; }
5480 bool setABI(const std::string &Name) override {
5483 // The defaults (above) are for AAPCS, check if we need to change them.
5485 // FIXME: We need support for -meabi... we could just mangle it into the
5487 if (Name == "apcs-gnu" || Name == "aapcs16") {
5488 setABIAPCS(Name == "aapcs16");
5491 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
5498 // FIXME: This should be based on Arch attributes, not CPU names.
5500 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
5502 const std::vector<std::string> &FeaturesVec) const override {
5504 std::vector<StringRef> TargetFeatures;
5505 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName());
5507 // get default FPU features
5508 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
5509 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
5511 // get default Extension features
5512 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
5513 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
5515 for (auto Feature : TargetFeatures)
5516 if (Feature[0] == '+')
5517 Features[Feature.drop_front(1)] = true;
5519 // Enable or disable thumb-mode explicitly per function to enable mixed
5520 // ARM and Thumb code generation.
5522 Features["thumb-mode"] = true;
5524 Features["thumb-mode"] = false;
5526 // Convert user-provided arm and thumb GNU target attributes to
5527 // [-|+]thumb-mode target features respectively.
5528 std::vector<std::string> UpdatedFeaturesVec(FeaturesVec);
5529 for (auto &Feature : UpdatedFeaturesVec) {
5530 if (Feature.compare("+arm") == 0)
5531 Feature = "-thumb-mode";
5532 else if (Feature.compare("+thumb") == 0)
5533 Feature = "+thumb-mode";
5536 return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec);
5539 bool handleTargetFeatures(std::vector<std::string> &Features,
5540 DiagnosticsEngine &Diags) override {
5546 SoftFloat = SoftFloatABI = false;
5549 // This does not diagnose illegal cases like having both
5550 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
5551 uint32_t HW_FP_remove = 0;
5552 for (const auto &Feature : Features) {
5553 if (Feature == "+soft-float") {
5555 } else if (Feature == "+soft-float-abi") {
5556 SoftFloatABI = true;
5557 } else if (Feature == "+vfp2") {
5559 HW_FP |= HW_FP_SP | HW_FP_DP;
5560 } else if (Feature == "+vfp3") {
5562 HW_FP |= HW_FP_SP | HW_FP_DP;
5563 } else if (Feature == "+vfp4") {
5565 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
5566 } else if (Feature == "+fp-armv8") {
5568 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
5569 } else if (Feature == "+neon") {
5571 HW_FP |= HW_FP_SP | HW_FP_DP;
5572 } else if (Feature == "+hwdiv") {
5573 HWDiv |= HWDivThumb;
5574 } else if (Feature == "+hwdiv-arm") {
5576 } else if (Feature == "+crc") {
5578 } else if (Feature == "+crypto") {
5580 } else if (Feature == "+dsp") {
5582 } else if (Feature == "+fp-only-sp") {
5583 HW_FP_remove |= HW_FP_DP;
5584 } else if (Feature == "+strict-align") {
5586 } else if (Feature == "+fp16") {
5590 HW_FP &= ~HW_FP_remove;
5592 switch (ArchVersion) {
5594 if (ArchProfile == llvm::ARM::PK_M)
5596 else if (ArchKind == llvm::ARM::AK_ARMV6K)
5597 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5602 if (ArchProfile == llvm::ARM::PK_M)
5603 LDREX = LDREX_W | LDREX_H | LDREX_B ;
5605 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5608 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5611 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
5612 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
5616 if (FPMath == FP_Neon)
5617 Features.push_back("+neonfp");
5618 else if (FPMath == FP_VFP)
5619 Features.push_back("-neonfp");
5621 // Remove front-end specific options which the backend handles differently.
5623 std::find(Features.begin(), Features.end(), "+soft-float-abi");
5624 if (Feature != Features.end())
5625 Features.erase(Feature);
5630 bool hasFeature(StringRef Feature) const override {
5631 return llvm::StringSwitch<bool>(Feature)
5633 .Case("aarch32", true)
5634 .Case("softfloat", SoftFloat)
5635 .Case("thumb", isThumb())
5636 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
5637 .Case("vfp", FPU && !SoftFloat)
5638 .Case("hwdiv", HWDiv & HWDivThumb)
5639 .Case("hwdiv-arm", HWDiv & HWDivARM)
5643 bool setCPU(const std::string &Name) override {
5644 if (Name != "generic")
5645 setArchInfo(llvm::ARM::parseCPUArch(Name));
5647 if (ArchKind == llvm::ARM::AK_INVALID)
5654 bool setFPMath(StringRef Name) override;
5656 void getTargetDefinesARMV81A(const LangOptions &Opts,
5657 MacroBuilder &Builder) const {
5658 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
5661 void getTargetDefinesARMV82A(const LangOptions &Opts,
5662 MacroBuilder &Builder) const {
5663 // Also include the ARMv8.1-A defines
5664 getTargetDefinesARMV81A(Opts, Builder);
5667 void getTargetDefines(const LangOptions &Opts,
5668 MacroBuilder &Builder) const override {
5669 // Target identification.
5670 Builder.defineMacro("__arm");
5671 Builder.defineMacro("__arm__");
5672 // For bare-metal none-eabi.
5673 if (getTriple().getOS() == llvm::Triple::UnknownOS &&
5674 (getTriple().getEnvironment() == llvm::Triple::EABI ||
5675 getTriple().getEnvironment() == llvm::Triple::EABIHF))
5676 Builder.defineMacro("__ELF__");
5679 // Target properties.
5680 Builder.defineMacro("__REGISTER_PREFIX__", "");
5682 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
5683 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
5684 if (getTriple().isWatchABI())
5685 Builder.defineMacro("__ARM_ARCH_7K__", "2");
5687 if (!CPUAttr.empty())
5688 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
5690 // ACLE 6.4.1 ARM/Thumb instruction set architecture
5691 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
5692 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
5694 if (ArchVersion >= 8) {
5695 // ACLE 6.5.7 Crypto Extension
5697 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
5698 // ACLE 6.5.8 CRC32 Extension
5700 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
5701 // ACLE 6.5.10 Numeric Maximum and Minimum
5702 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
5703 // ACLE 6.5.9 Directed Rounding
5704 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
5707 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
5708 // is not defined for the M-profile.
5709 // NOTE that the default profile is assumed to be 'A'
5710 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M)
5711 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
5713 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original
5714 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the
5715 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all
5716 // v7 and v8 architectures excluding v8-M Baseline.
5717 if (supportsThumb2())
5718 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
5719 else if (supportsThumb())
5720 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
5722 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
5723 // instruction set such as ARM or Thumb.
5724 Builder.defineMacro("__ARM_32BIT_STATE", "1");
5726 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
5728 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
5729 if (!CPUProfile.empty())
5730 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
5732 // ACLE 6.4.3 Unaligned access supported in hardware
5734 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
5736 // ACLE 6.4.4 LDREX/STREX
5738 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX));
5741 if (ArchVersion == 5 ||
5742 (ArchVersion == 6 && CPUProfile != "M") ||
5744 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
5746 // ACLE 6.5.1 Hardware Floating Point
5748 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
5751 Builder.defineMacro("__ARM_ACLE", "200");
5753 // FP16 support (we currently only support IEEE format).
5754 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
5755 Builder.defineMacro("__ARM_FP16_ARGS", "1");
5757 // ACLE 6.5.3 Fused multiply-accumulate (FMA)
5758 if (ArchVersion >= 7 && (FPU & VFP4FPU))
5759 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
5761 // Subtarget options.
5763 // FIXME: It's more complicated than this and we don't really support
5765 // Windows on ARM does not "support" interworking
5766 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows())
5767 Builder.defineMacro("__THUMB_INTERWORK__");
5769 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
5770 // Embedded targets on Darwin follow AAPCS, but not EABI.
5771 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
5772 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows())
5773 Builder.defineMacro("__ARM_EABI__");
5774 Builder.defineMacro("__ARM_PCS", "1");
5777 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" ||
5779 Builder.defineMacro("__ARM_PCS_VFP", "1");
5782 Builder.defineMacro("__SOFTFP__");
5784 if (ArchKind == llvm::ARM::AK_XSCALE)
5785 Builder.defineMacro("__XSCALE__");
5788 Builder.defineMacro("__THUMBEL__");
5789 Builder.defineMacro("__thumb__");
5790 if (supportsThumb2())
5791 Builder.defineMacro("__thumb2__");
5794 // ACLE 6.4.9 32-bit SIMD instructions
5795 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
5796 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
5798 // ACLE 6.4.10 Hardware Integer Divide
5799 if (((HWDiv & HWDivThumb) && isThumb()) ||
5800 ((HWDiv & HWDivARM) && !isThumb())) {
5801 Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
5802 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
5805 // Note, this is always on in gcc, even though it doesn't make sense.
5806 Builder.defineMacro("__APCS_32__");
5808 if (FPUModeIsVFP((FPUMode) FPU)) {
5809 Builder.defineMacro("__VFP_FP__");
5811 Builder.defineMacro("__ARM_VFPV2__");
5813 Builder.defineMacro("__ARM_VFPV3__");
5815 Builder.defineMacro("__ARM_VFPV4__");
5817 Builder.defineMacro("__ARM_FPV5__");
5820 // This only gets set when Neon instructions are actually available, unlike
5821 // the VFP define, hence the soft float and arch check. This is subtly
5822 // different from gcc, we follow the intent which was that it should be set
5823 // when Neon instructions are actually available.
5824 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
5825 Builder.defineMacro("__ARM_NEON", "1");
5826 Builder.defineMacro("__ARM_NEON__");
5827 // current AArch32 NEON implementations do not support double-precision
5828 // floating-point even when it is present in VFP.
5829 Builder.defineMacro("__ARM_NEON_FP",
5830 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP));
5833 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
5834 Opts.ShortWChar ? "2" : "4");
5836 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5837 Opts.ShortEnums ? "1" : "4");
5839 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") {
5840 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
5841 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
5842 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
5843 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
5846 // ACLE 6.4.7 DSP instructions
5848 Builder.defineMacro("__ARM_FEATURE_DSP", "1");
5851 // ACLE 6.4.8 Saturation instructions
5853 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) {
5854 Builder.defineMacro("__ARM_FEATURE_SAT", "1");
5858 // ACLE 6.4.6 Q (saturation) flag
5860 Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
5862 if (Opts.UnsafeFPMath)
5863 Builder.defineMacro("__ARM_FP_FAST", "1");
5867 case llvm::ARM::AK_ARMV8_1A:
5868 getTargetDefinesARMV81A(Opts, Builder);
5870 case llvm::ARM::AK_ARMV8_2A:
5871 getTargetDefinesARMV82A(Opts, Builder);
5876 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5877 return llvm::makeArrayRef(BuiltinInfo,
5878 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin);
5880 bool isCLZForZeroUndef() const override { return false; }
5881 BuiltinVaListKind getBuiltinVaListKind() const override {
5883 ? AAPCSABIBuiltinVaList
5884 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList
5885 : TargetInfo::VoidPtrBuiltinVaList);
5887 ArrayRef<const char *> getGCCRegNames() const override;
5888 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5889 bool validateAsmConstraint(const char *&Name,
5890 TargetInfo::ConstraintInfo &Info) const override {
5895 case 't': // VFP Floating point register single precision
5896 case 'w': // VFP Floating point register double precision
5897 Info.setAllowsRegister();
5906 case 'Q': // A memory address that is a single base register.
5907 Info.setAllowsMemory();
5909 case 'U': // a memory reference...
5911 case 'q': // ...ARMV4 ldrsb
5912 case 'v': // ...VFP load/store (reg+constant offset)
5913 case 'y': // ...iWMMXt load/store
5914 case 't': // address valid for load/store opaque types wider
5916 case 'n': // valid address for Neon doubleword vector load/store
5917 case 'm': // valid address for Neon element and structure load/store
5918 case 's': // valid address for non-offset loads/stores of quad-word
5919 // values in four ARM registers
5920 Info.setAllowsMemory();
5927 std::string convertConstraint(const char *&Constraint) const override {
5929 switch (*Constraint) {
5930 case 'U': // Two-character constraint; add "^" hint for later parsing.
5931 R = std::string("^") + std::string(Constraint, 2);
5934 case 'p': // 'p' should be translated to 'r' by default.
5935 R = std::string("r");
5938 return std::string(1, *Constraint);
5943 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5944 std::string &SuggestedModifier) const override {
5945 bool isOutput = (Constraint[0] == '=');
5946 bool isInOut = (Constraint[0] == '+');
5948 // Strip off constraint modifiers.
5949 while (Constraint[0] == '=' ||
5950 Constraint[0] == '+' ||
5951 Constraint[0] == '&')
5952 Constraint = Constraint.substr(1);
5954 switch (Constraint[0]) {
5959 return (isInOut || isOutput || Size <= 64);
5961 // A register of size 32 cannot fit a vector type.
5969 const char *getClobbers() const override {
5970 // FIXME: Is this really right?
5974 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5979 case CC_OpenCLKernel:
5982 return CCCR_Warning;
5986 int getEHDataRegisterNumber(unsigned RegNo) const override {
5987 if (RegNo == 0) return 0;
5988 if (RegNo == 1) return 1;
5992 bool hasSjLjLowering() const override {
5997 bool ARMTargetInfo::setFPMath(StringRef Name) {
5998 if (Name == "neon") {
6001 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
6009 const char * const ARMTargetInfo::GCCRegNames[] = {
6010 // Integer registers
6011 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6012 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
6015 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
6016 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
6017 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
6018 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
6021 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
6022 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
6023 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
6024 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
6027 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
6028 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
6031 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
6032 return llvm::makeArrayRef(GCCRegNames);
6035 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
6045 { { "v6", "rfp" }, "r9" },
6046 { { "sl" }, "r10" },
6047 { { "fp" }, "r11" },
6048 { { "ip" }, "r12" },
6049 { { "r13" }, "sp" },
6050 { { "r14" }, "lr" },
6051 { { "r15" }, "pc" },
6052 // The S, D and Q registers overlap, but aren't really aliases; we
6053 // don't want to substitute one of these for a different-sized one.
6056 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
6057 return llvm::makeArrayRef(GCCRegAliases);
6060 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
6061 #define BUILTIN(ID, TYPE, ATTRS) \
6062 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6063 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6064 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6065 #include "clang/Basic/BuiltinsNEON.def"
6067 #define BUILTIN(ID, TYPE, ATTRS) \
6068 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6069 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \
6070 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr },
6071 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6072 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6073 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
6074 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
6075 #include "clang/Basic/BuiltinsARM.def"
6078 class ARMleTargetInfo : public ARMTargetInfo {
6080 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6081 : ARMTargetInfo(Triple, Opts) {}
6082 void getTargetDefines(const LangOptions &Opts,
6083 MacroBuilder &Builder) const override {
6084 Builder.defineMacro("__ARMEL__");
6085 ARMTargetInfo::getTargetDefines(Opts, Builder);
6089 class ARMbeTargetInfo : public ARMTargetInfo {
6091 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6092 : ARMTargetInfo(Triple, Opts) {}
6093 void getTargetDefines(const LangOptions &Opts,
6094 MacroBuilder &Builder) const override {
6095 Builder.defineMacro("__ARMEB__");
6096 Builder.defineMacro("__ARM_BIG_ENDIAN");
6097 ARMTargetInfo::getTargetDefines(Opts, Builder);
6101 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
6102 const llvm::Triple Triple;
6104 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6105 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
6106 WCharType = UnsignedShort;
6107 SizeType = UnsignedInt;
6109 void getVisualStudioDefines(const LangOptions &Opts,
6110 MacroBuilder &Builder) const {
6111 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
6113 // FIXME: this is invalid for WindowsCE
6114 Builder.defineMacro("_M_ARM_NT", "1");
6115 Builder.defineMacro("_M_ARMT", "_M_ARM");
6116 Builder.defineMacro("_M_THUMB", "_M_ARM");
6118 assert((Triple.getArch() == llvm::Triple::arm ||
6119 Triple.getArch() == llvm::Triple::thumb) &&
6120 "invalid architecture for Windows ARM target info");
6121 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
6122 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
6124 // TODO map the complete set of values
6125 // 31: VFPv3 40: VFPv4
6126 Builder.defineMacro("_M_ARM_FP", "31");
6128 BuiltinVaListKind getBuiltinVaListKind() const override {
6129 return TargetInfo::CharPtrBuiltinVaList;
6131 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6134 case CC_X86ThisCall:
6135 case CC_X86FastCall:
6136 case CC_X86VectorCall:
6139 case CC_OpenCLKernel:
6142 return CCCR_Warning;
6147 // Windows ARM + Itanium C++ ABI Target
6148 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
6150 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple,
6151 const TargetOptions &Opts)
6152 : WindowsARMTargetInfo(Triple, Opts) {
6153 TheCXXABI.set(TargetCXXABI::GenericARM);
6156 void getTargetDefines(const LangOptions &Opts,
6157 MacroBuilder &Builder) const override {
6158 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
6160 if (Opts.MSVCCompat)
6161 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
6165 // Windows ARM, MS (C++) ABI
6166 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
6168 MicrosoftARMleTargetInfo(const llvm::Triple &Triple,
6169 const TargetOptions &Opts)
6170 : WindowsARMTargetInfo(Triple, Opts) {
6171 TheCXXABI.set(TargetCXXABI::Microsoft);
6174 void getTargetDefines(const LangOptions &Opts,
6175 MacroBuilder &Builder) const override {
6176 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
6177 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
6182 class MinGWARMTargetInfo : public WindowsARMTargetInfo {
6184 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6185 : WindowsARMTargetInfo(Triple, Opts) {
6186 TheCXXABI.set(TargetCXXABI::GenericARM);
6189 void getTargetDefines(const LangOptions &Opts,
6190 MacroBuilder &Builder) const override {
6191 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
6192 DefineStd(Builder, "WIN32", Opts);
6193 DefineStd(Builder, "WINNT", Opts);
6194 Builder.defineMacro("_ARM_");
6195 addMinGWDefines(Opts, Builder);
6199 // ARM Cygwin target
6200 class CygwinARMTargetInfo : public ARMleTargetInfo {
6202 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6203 : ARMleTargetInfo(Triple, Opts) {
6204 TLSSupported = false;
6205 WCharType = UnsignedShort;
6206 DoubleAlign = LongLongAlign = 64;
6207 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
6209 void getTargetDefines(const LangOptions &Opts,
6210 MacroBuilder &Builder) const override {
6211 ARMleTargetInfo::getTargetDefines(Opts, Builder);
6212 Builder.defineMacro("_ARM_");
6213 Builder.defineMacro("__CYGWIN__");
6214 Builder.defineMacro("__CYGWIN32__");
6215 DefineStd(Builder, "unix", Opts);
6217 Builder.defineMacro("_GNU_SOURCE");
6221 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> {
6223 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
6224 MacroBuilder &Builder) const override {
6225 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
6229 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6230 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
6231 HasAlignMac68kSupport = true;
6232 // iOS always has 64-bit atomic instructions.
6233 // FIXME: This should be based off of the target features in
6235 MaxAtomicInlineWidth = 64;
6237 if (Triple.isWatchABI()) {
6238 // Darwin on iOS uses a variant of the ARM C++ ABI.
6239 TheCXXABI.set(TargetCXXABI::WatchOS);
6241 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that
6242 // size_t is long, it's a bit weird for it to be int.
6243 PtrDiffType = SignedLong;
6245 // BOOL should be a real boolean on the new ABI
6246 UseSignedCharForObjCBool = false;
6248 TheCXXABI.set(TargetCXXABI::iOS);
6252 class AArch64TargetInfo : public TargetInfo {
6253 virtual void setDataLayout() = 0;
6254 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6255 static const char *const GCCRegNames[];
6259 NeonMode = (1 << 0),
6267 unsigned HasFullFP16;
6268 llvm::AArch64::ArchKind ArchKind;
6270 static const Builtin::Info BuiltinInfo[];
6275 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6276 : TargetInfo(Triple), ABI("aapcs") {
6277 if (getTriple().getOS() == llvm::Triple::NetBSD ||
6278 getTriple().getOS() == llvm::Triple::OpenBSD) {
6279 WCharType = SignedInt;
6281 // NetBSD apparently prefers consistency across ARM targets to consistency
6282 // across 64-bit targets.
6283 Int64Type = SignedLongLong;
6284 IntMaxType = SignedLongLong;
6286 WCharType = UnsignedInt;
6287 Int64Type = SignedLong;
6288 IntMaxType = SignedLong;
6291 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6292 MaxVectorAlign = 128;
6293 MaxAtomicInlineWidth = 128;
6294 MaxAtomicPromoteWidth = 128;
6296 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
6297 LongDoubleFormat = &llvm::APFloat::IEEEquad();
6299 // Make __builtin_ms_va_list available.
6300 HasBuiltinMSVaList = true;
6302 // {} in inline assembly are neon specifiers, not assembly variant
6304 NoAsmVariants = true;
6306 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
6307 // contributes to the alignment of the containing aggregate in the same way
6308 // a plain (non bit-field) member of that type would, without exception for
6309 // zero-sized or anonymous bit-fields."
6310 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
6311 UseZeroLengthBitfieldAlignment = true;
6313 // AArch64 targets default to using the ARM C++ ABI.
6314 TheCXXABI.set(TargetCXXABI::GenericAArch64);
6316 if (Triple.getOS() == llvm::Triple::Linux)
6317 this->MCountName = "\01_mcount";
6318 else if (Triple.getOS() == llvm::Triple::UnknownOS)
6319 this->MCountName = Opts.EABIVersion == llvm::EABI::GNU ? "\01_mcount" : "mcount";
6322 StringRef getABI() const override { return ABI; }
6323 bool setABI(const std::string &Name) override {
6324 if (Name != "aapcs" && Name != "darwinpcs")
6331 bool setCPU(const std::string &Name) override {
6332 return Name == "generic" ||
6333 llvm::AArch64::parseCPUArch(Name) !=
6334 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID);
6337 void getTargetDefinesARMV81A(const LangOptions &Opts,
6338 MacroBuilder &Builder) const {
6339 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
6342 void getTargetDefinesARMV82A(const LangOptions &Opts,
6343 MacroBuilder &Builder) const {
6344 // Also include the ARMv8.1 defines
6345 getTargetDefinesARMV81A(Opts, Builder);
6348 void getTargetDefines(const LangOptions &Opts,
6349 MacroBuilder &Builder) const override {
6350 // Target identification.
6351 Builder.defineMacro("__aarch64__");
6352 // For bare-metal none-eabi.
6353 if (getTriple().getOS() == llvm::Triple::UnknownOS &&
6354 (getTriple().getEnvironment() == llvm::Triple::EABI ||
6355 getTriple().getEnvironment() == llvm::Triple::EABIHF))
6356 Builder.defineMacro("__ELF__");
6358 // Target properties.
6359 Builder.defineMacro("_LP64");
6360 Builder.defineMacro("__LP64__");
6362 // ACLE predefines. Many can only have one possible value on v8 AArch64.
6363 Builder.defineMacro("__ARM_ACLE", "200");
6364 Builder.defineMacro("__ARM_ARCH", "8");
6365 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
6367 Builder.defineMacro("__ARM_64BIT_STATE", "1");
6368 Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
6369 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
6371 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
6372 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
6373 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
6374 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
6375 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
6376 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
6377 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
6379 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
6381 // 0xe implies support for half, single and double precision operations.
6382 Builder.defineMacro("__ARM_FP", "0xE");
6384 // PCS specifies this for SysV variants, which is all we support. Other ABIs
6385 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
6386 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
6387 Builder.defineMacro("__ARM_FP16_ARGS", "1");
6389 if (Opts.UnsafeFPMath)
6390 Builder.defineMacro("__ARM_FP_FAST", "1");
6392 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
6394 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
6395 Opts.ShortEnums ? "1" : "4");
6397 if (FPU & NeonMode) {
6398 Builder.defineMacro("__ARM_NEON", "1");
6399 // 64-bit NEON supports half, single and double precision operations.
6400 Builder.defineMacro("__ARM_NEON_FP", "0xE");
6404 Builder.defineMacro("__ARM_FEATURE_SVE", "1");
6407 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
6410 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
6413 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
6417 case llvm::AArch64::ArchKind::AK_ARMV8_1A:
6418 getTargetDefinesARMV81A(Opts, Builder);
6420 case llvm::AArch64::ArchKind::AK_ARMV8_2A:
6421 getTargetDefinesARMV82A(Opts, Builder);
6425 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
6426 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
6427 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
6428 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
6429 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
6432 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6433 return llvm::makeArrayRef(BuiltinInfo,
6434 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin);
6437 bool hasFeature(StringRef Feature) const override {
6438 return Feature == "aarch64" ||
6439 Feature == "arm64" ||
6441 (Feature == "neon" && (FPU & NeonMode)) ||
6442 (Feature == "sve" && (FPU & SveMode));
6445 bool handleTargetFeatures(std::vector<std::string> &Features,
6446 DiagnosticsEngine &Diags) override {
6452 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8A;
6454 for (const auto &Feature : Features) {
6455 if (Feature == "+neon")
6457 if (Feature == "+sve")
6459 if (Feature == "+crc")
6461 if (Feature == "+crypto")
6463 if (Feature == "+strict-align")
6465 if (Feature == "+v8.1a")
6466 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_1A;
6467 if (Feature == "+v8.2a")
6468 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_2A;
6469 if (Feature == "+fullfp16")
6478 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6482 case CC_PreserveMost:
6483 case CC_PreserveAll:
6484 case CC_OpenCLKernel:
6488 return CCCR_Warning;
6492 bool isCLZForZeroUndef() const override { return false; }
6494 BuiltinVaListKind getBuiltinVaListKind() const override {
6495 return TargetInfo::AArch64ABIBuiltinVaList;
6498 ArrayRef<const char *> getGCCRegNames() const override;
6499 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6501 bool validateAsmConstraint(const char *&Name,
6502 TargetInfo::ConstraintInfo &Info) const override {
6506 case 'w': // Floating point and SIMD registers (V0-V31)
6507 Info.setAllowsRegister();
6509 case 'I': // Constant that can be used with an ADD instruction
6510 case 'J': // Constant that can be used with a SUB instruction
6511 case 'K': // Constant that can be used with a 32-bit logical instruction
6512 case 'L': // Constant that can be used with a 64-bit logical instruction
6513 case 'M': // Constant that can be used as a 32-bit MOV immediate
6514 case 'N': // Constant that can be used as a 64-bit MOV immediate
6515 case 'Y': // Floating point constant zero
6516 case 'Z': // Integer constant zero
6518 case 'Q': // A memory reference with base register and no offset
6519 Info.setAllowsMemory();
6521 case 'S': // A symbolic address
6522 Info.setAllowsRegister();
6525 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
6526 // Utf: A memory address suitable for ldp/stp in TF mode.
6527 // Usa: An absolute symbolic address.
6528 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
6529 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
6530 case 'z': // Zero register, wzr or xzr
6531 Info.setAllowsRegister();
6533 case 'x': // Floating point and SIMD registers (V0-V15)
6534 Info.setAllowsRegister();
6541 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
6542 std::string &SuggestedModifier) const override {
6543 // Strip off constraint modifiers.
6544 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
6545 Constraint = Constraint.substr(1);
6547 switch (Constraint[0]) {
6555 // For now assume that the person knows what they're
6556 // doing with the modifier.
6559 // By default an 'r' constraint will be in the 'x'
6564 SuggestedModifier = "w";
6571 const char *getClobbers() const override { return ""; }
6573 int getEHDataRegisterNumber(unsigned RegNo) const override {
6582 const char *const AArch64TargetInfo::GCCRegNames[] = {
6583 // 32-bit Integer registers
6584 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
6585 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
6586 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
6588 // 64-bit Integer registers
6589 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
6590 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
6591 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
6593 // 32-bit floating point regsisters
6594 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
6595 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
6596 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
6598 // 64-bit floating point regsisters
6599 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
6600 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
6601 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
6604 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
6605 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
6606 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
6609 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
6610 return llvm::makeArrayRef(GCCRegNames);
6613 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
6614 { { "w31" }, "wsp" },
6615 { { "x29" }, "fp" },
6616 { { "x30" }, "lr" },
6617 { { "x31" }, "sp" },
6618 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
6619 // don't want to substitute one of these for a different-sized one.
6622 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
6623 return llvm::makeArrayRef(GCCRegAliases);
6626 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
6627 #define BUILTIN(ID, TYPE, ATTRS) \
6628 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6629 #include "clang/Basic/BuiltinsNEON.def"
6631 #define BUILTIN(ID, TYPE, ATTRS) \
6632 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6633 #include "clang/Basic/BuiltinsAArch64.def"
6636 class AArch64leTargetInfo : public AArch64TargetInfo {
6637 void setDataLayout() override {
6638 if (getTriple().isOSBinFormatMachO())
6639 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128");
6641 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6645 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6646 : AArch64TargetInfo(Triple, Opts) {
6648 void getTargetDefines(const LangOptions &Opts,
6649 MacroBuilder &Builder) const override {
6650 Builder.defineMacro("__AARCH64EL__");
6651 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6655 class MicrosoftARM64TargetInfo
6656 : public WindowsTargetInfo<AArch64leTargetInfo> {
6657 const llvm::Triple Triple;
6660 MicrosoftARM64TargetInfo(const llvm::Triple &Triple,
6661 const TargetOptions &Opts)
6662 : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) {
6664 // This is an LLP64 platform.
6665 // int:4, long:4, long long:8, long double:8.
6666 WCharType = UnsignedShort;
6667 IntWidth = IntAlign = 32;
6668 LongWidth = LongAlign = 32;
6669 DoubleAlign = LongLongAlign = 64;
6670 LongDoubleWidth = LongDoubleAlign = 64;
6671 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
6672 IntMaxType = SignedLongLong;
6673 Int64Type = SignedLongLong;
6674 SizeType = UnsignedLongLong;
6675 PtrDiffType = SignedLongLong;
6676 IntPtrType = SignedLongLong;
6678 TheCXXABI.set(TargetCXXABI::Microsoft);
6681 void setDataLayout() override {
6682 resetDataLayout("e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128");
6685 void getVisualStudioDefines(const LangOptions &Opts,
6686 MacroBuilder &Builder) const {
6687 WindowsTargetInfo<AArch64leTargetInfo>::getVisualStudioDefines(Opts,
6689 Builder.defineMacro("_WIN32", "1");
6690 Builder.defineMacro("_WIN64", "1");
6691 Builder.defineMacro("_M_ARM64", "1");
6694 void getTargetDefines(const LangOptions &Opts,
6695 MacroBuilder &Builder) const override {
6696 WindowsTargetInfo::getTargetDefines(Opts, Builder);
6697 getVisualStudioDefines(Opts, Builder);
6700 BuiltinVaListKind getBuiltinVaListKind() const override {
6701 return TargetInfo::CharPtrBuiltinVaList;
6705 class AArch64beTargetInfo : public AArch64TargetInfo {
6706 void setDataLayout() override {
6707 assert(!getTriple().isOSBinFormatMachO());
6708 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6712 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6713 : AArch64TargetInfo(Triple, Opts) {}
6714 void getTargetDefines(const LangOptions &Opts,
6715 MacroBuilder &Builder) const override {
6716 Builder.defineMacro("__AARCH64EB__");
6717 Builder.defineMacro("__AARCH_BIG_ENDIAN");
6718 Builder.defineMacro("__ARM_BIG_ENDIAN");
6719 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6723 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
6725 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
6726 MacroBuilder &Builder) const override {
6727 Builder.defineMacro("__AARCH64_SIMD__");
6728 Builder.defineMacro("__ARM64_ARCH_8__");
6729 Builder.defineMacro("__ARM_NEON__");
6730 Builder.defineMacro("__LITTLE_ENDIAN__");
6731 Builder.defineMacro("__REGISTER_PREFIX__", "");
6732 Builder.defineMacro("__arm64", "1");
6733 Builder.defineMacro("__arm64__", "1");
6735 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
6739 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6740 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
6741 Int64Type = SignedLongLong;
6742 WCharType = SignedInt;
6743 UseSignedCharForObjCBool = false;
6745 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
6746 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
6748 TheCXXABI.set(TargetCXXABI::iOS64);
6751 BuiltinVaListKind getBuiltinVaListKind() const override {
6752 return TargetInfo::CharPtrBuiltinVaList;
6756 // Hexagon abstract base class
6757 class HexagonTargetInfo : public TargetInfo {
6758 static const Builtin::Info BuiltinInfo[];
6759 static const char * const GCCRegNames[];
6760 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6762 bool HasHVX, HasHVXDouble;
6766 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6767 : TargetInfo(Triple) {
6768 // Specify the vector alignment explicitly. For v512x1, the calculated
6769 // alignment would be 512*alignment(i1), which is 512 bytes, instead of
6770 // the required minimum of 64 bytes.
6771 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-"
6772 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
6773 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048");
6774 SizeType = UnsignedInt;
6775 PtrDiffType = SignedInt;
6776 IntPtrType = SignedInt;
6778 // {} in inline assembly are packet specifiers, not assembly variant
6780 NoAsmVariants = true;
6782 LargeArrayMinWidth = 64;
6783 LargeArrayAlign = 64;
6784 UseBitFieldTypeAlignment = true;
6785 ZeroLengthBitfieldBoundary = 32;
6786 HasHVX = HasHVXDouble = false;
6787 UseLongCalls = false;
6790 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6791 return llvm::makeArrayRef(BuiltinInfo,
6792 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin);
6795 bool validateAsmConstraint(const char *&Name,
6796 TargetInfo::ConstraintInfo &Info) const override {
6801 Info.setAllowsRegister();
6806 // Relocatable constant.
6812 void getTargetDefines(const LangOptions &Opts,
6813 MacroBuilder &Builder) const override;
6815 bool isCLZForZeroUndef() const override { return false; }
6817 bool hasFeature(StringRef Feature) const override {
6818 return llvm::StringSwitch<bool>(Feature)
6819 .Case("hexagon", true)
6820 .Case("hvx", HasHVX)
6821 .Case("hvx-double", HasHVXDouble)
6822 .Case("long-calls", UseLongCalls)
6826 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6827 StringRef CPU, const std::vector<std::string> &FeaturesVec)
6830 bool handleTargetFeatures(std::vector<std::string> &Features,
6831 DiagnosticsEngine &Diags) override;
6833 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
6834 bool Enabled) const override;
6836 BuiltinVaListKind getBuiltinVaListKind() const override {
6837 return TargetInfo::CharPtrBuiltinVaList;
6839 ArrayRef<const char *> getGCCRegNames() const override;
6840 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6841 const char *getClobbers() const override {
6845 static const char *getHexagonCPUSuffix(StringRef Name) {
6846 return llvm::StringSwitch<const char*>(Name)
6847 .Case("hexagonv4", "4")
6848 .Case("hexagonv5", "5")
6849 .Case("hexagonv55", "55")
6850 .Case("hexagonv60", "60")
6851 .Case("hexagonv62", "62")
6855 bool setCPU(const std::string &Name) override {
6856 if (!getHexagonCPUSuffix(Name))
6862 int getEHDataRegisterNumber(unsigned RegNo) const override {
6863 return RegNo < 2 ? RegNo : -1;
6867 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
6868 MacroBuilder &Builder) const {
6869 Builder.defineMacro("__qdsp6__", "1");
6870 Builder.defineMacro("__hexagon__", "1");
6872 if (CPU == "hexagonv4") {
6873 Builder.defineMacro("__HEXAGON_V4__");
6874 Builder.defineMacro("__HEXAGON_ARCH__", "4");
6875 if (Opts.HexagonQdsp6Compat) {
6876 Builder.defineMacro("__QDSP6_V4__");
6877 Builder.defineMacro("__QDSP6_ARCH__", "4");
6879 } else if (CPU == "hexagonv5") {
6880 Builder.defineMacro("__HEXAGON_V5__");
6881 Builder.defineMacro("__HEXAGON_ARCH__", "5");
6882 if(Opts.HexagonQdsp6Compat) {
6883 Builder.defineMacro("__QDSP6_V5__");
6884 Builder.defineMacro("__QDSP6_ARCH__", "5");
6886 } else if (CPU == "hexagonv55") {
6887 Builder.defineMacro("__HEXAGON_V55__");
6888 Builder.defineMacro("__HEXAGON_ARCH__", "55");
6889 Builder.defineMacro("__QDSP6_V55__");
6890 Builder.defineMacro("__QDSP6_ARCH__", "55");
6891 } else if (CPU == "hexagonv60") {
6892 Builder.defineMacro("__HEXAGON_V60__");
6893 Builder.defineMacro("__HEXAGON_ARCH__", "60");
6894 Builder.defineMacro("__QDSP6_V60__");
6895 Builder.defineMacro("__QDSP6_ARCH__", "60");
6896 } else if (CPU == "hexagonv62") {
6897 Builder.defineMacro("__HEXAGON_V62__");
6898 Builder.defineMacro("__HEXAGON_ARCH__", "62");
6901 if (hasFeature("hvx")) {
6902 Builder.defineMacro("__HVX__");
6903 if (hasFeature("hvx-double"))
6904 Builder.defineMacro("__HVXDBL__");
6908 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features,
6909 DiagnosticsEngine &Diags, StringRef CPU,
6910 const std::vector<std::string> &FeaturesVec) const {
6911 // Default for v60: -hvx, -hvx-double.
6912 Features["hvx"] = false;
6913 Features["hvx-double"] = false;
6914 Features["long-calls"] = false;
6916 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6919 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
6920 DiagnosticsEngine &Diags) {
6921 for (auto &F : Features) {
6924 else if (F == "-hvx")
6925 HasHVX = HasHVXDouble = false;
6926 else if (F == "+hvx-double")
6927 HasHVX = HasHVXDouble = true;
6928 else if (F == "-hvx-double")
6929 HasHVXDouble = false;
6931 if (F == "+long-calls")
6932 UseLongCalls = true;
6933 else if (F == "-long-calls")
6934 UseLongCalls = false;
6939 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
6940 StringRef Name, bool Enabled) const {
6942 if (Name == "hvx-double")
6943 Features["hvx"] = true;
6946 Features["hvx-double"] = false;
6948 Features[Name] = Enabled;
6951 const char *const HexagonTargetInfo::GCCRegNames[] = {
6952 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6953 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6954 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6955 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
6956 "p0", "p1", "p2", "p3",
6957 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
6960 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const {
6961 return llvm::makeArrayRef(GCCRegNames);
6964 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
6965 { { "sp" }, "r29" },
6966 { { "fp" }, "r30" },
6967 { { "lr" }, "r31" },
6970 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const {
6971 return llvm::makeArrayRef(GCCRegAliases);
6975 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
6976 #define BUILTIN(ID, TYPE, ATTRS) \
6977 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6978 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6979 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6980 #include "clang/Basic/BuiltinsHexagon.def"
6983 class LanaiTargetInfo : public TargetInfo {
6984 // Class for Lanai (32-bit).
6985 // The CPU profiles supported by the Lanai backend
6991 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6992 static const char *const GCCRegNames[];
6995 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6996 : TargetInfo(Triple) {
6997 // Description string has to be kept in sync with backend.
6998 resetDataLayout("E" // Big endian
6999 "-m:e" // ELF name manging
7000 "-p:32:32" // 32 bit pointers, 32 bit aligned
7001 "-i64:64" // 64 bit integers, 64 bit aligned
7002 "-a:0:32" // 32 bit alignment of objects of aggregate type
7003 "-n32" // 32 bit native integer width
7004 "-S64" // 64 bit natural stack alignment
7007 // Setting RegParmMax equal to what mregparm was set to in the old
7011 // Set the default CPU to V11
7014 // Temporary approach to make everything at least word-aligned and allow for
7015 // safely casting between pointers with different alignment requirements.
7016 // TODO: Remove this when there are no more cast align warnings on the
7018 MinGlobalAlign = 32;
7021 void getTargetDefines(const LangOptions &Opts,
7022 MacroBuilder &Builder) const override {
7023 // Define __lanai__ when building for target lanai.
7024 Builder.defineMacro("__lanai__");
7026 // Set define for the CPU specified.
7029 Builder.defineMacro("__LANAI_V11__");
7032 llvm_unreachable("Unhandled target CPU");
7036 bool setCPU(const std::string &Name) override {
7037 CPU = llvm::StringSwitch<CPUKind>(Name)
7038 .Case("v11", CK_V11)
7041 return CPU != CK_NONE;
7044 bool hasFeature(StringRef Feature) const override {
7045 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false);
7048 ArrayRef<const char *> getGCCRegNames() const override;
7050 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
7052 BuiltinVaListKind getBuiltinVaListKind() const override {
7053 return TargetInfo::VoidPtrBuiltinVaList;
7056 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7058 bool validateAsmConstraint(const char *&Name,
7059 TargetInfo::ConstraintInfo &info) const override {
7063 const char *getClobbers() const override { return ""; }
7066 const char *const LanaiTargetInfo::GCCRegNames[] = {
7067 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
7068 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
7069 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
7071 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const {
7072 return llvm::makeArrayRef(GCCRegNames);
7075 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = {
7085 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const {
7086 return llvm::makeArrayRef(GCCRegAliases);
7089 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
7090 class SparcTargetInfo : public TargetInfo {
7091 static const TargetInfo::GCCRegAlias GCCRegAliases[];
7092 static const char * const GCCRegNames[];
7095 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7096 : TargetInfo(Triple), SoftFloat(false) {}
7098 int getEHDataRegisterNumber(unsigned RegNo) const override {
7099 if (RegNo == 0) return 24;
7100 if (RegNo == 1) return 25;
7104 bool handleTargetFeatures(std::vector<std::string> &Features,
7105 DiagnosticsEngine &Diags) override {
7106 // Check if software floating point is enabled
7107 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
7108 if (Feature != Features.end()) {
7113 void getTargetDefines(const LangOptions &Opts,
7114 MacroBuilder &Builder) const override {
7115 DefineStd(Builder, "sparc", Opts);
7116 Builder.defineMacro("__REGISTER_PREFIX__", "");
7119 Builder.defineMacro("SOFT_FLOAT", "1");
7122 bool hasFeature(StringRef Feature) const override {
7123 return llvm::StringSwitch<bool>(Feature)
7124 .Case("softfloat", SoftFloat)
7125 .Case("sparc", true)
7129 bool hasSjLjLowering() const override {
7133 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7134 // FIXME: Implement!
7137 BuiltinVaListKind getBuiltinVaListKind() const override {
7138 return TargetInfo::VoidPtrBuiltinVaList;
7140 ArrayRef<const char *> getGCCRegNames() const override;
7141 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
7142 bool validateAsmConstraint(const char *&Name,
7143 TargetInfo::ConstraintInfo &info) const override {
7144 // FIXME: Implement!
7146 case 'I': // Signed 13-bit constant
7148 case 'K': // 32-bit constant with the low 12 bits clear
7149 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
7150 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
7151 case 'N': // Same as 'K' but zext (required for SIMode)
7152 case 'O': // The constant 4096
7157 info.setAllowsRegister();
7162 const char *getClobbers() const override {
7163 // FIXME: Implement!
7167 // No Sparc V7 for now, the backend doesn't support it anyway.
7198 enum CPUGeneration {
7203 CPUGeneration getCPUGeneration(CPUKind Kind) const {
7211 case CK_SPARCLITE86X:
7218 case CK_LEON2_AT697E:
7219 case CK_LEON2_AT697F:
7221 case CK_LEON3_UT699:
7222 case CK_LEON3_GR712RC:
7224 case CK_LEON4_GR740:
7228 case CK_ULTRASPARC3:
7235 llvm_unreachable("Unexpected CPU kind");
7238 CPUKind getCPUKind(StringRef Name) const {
7239 return llvm::StringSwitch<CPUKind>(Name)
7241 .Case("supersparc", CK_SUPERSPARC)
7242 .Case("sparclite", CK_SPARCLITE)
7243 .Case("f934", CK_F934)
7244 .Case("hypersparc", CK_HYPERSPARC)
7245 .Case("sparclite86x", CK_SPARCLITE86X)
7246 .Case("sparclet", CK_SPARCLET)
7247 .Case("tsc701", CK_TSC701)
7249 .Case("ultrasparc", CK_ULTRASPARC)
7250 .Case("ultrasparc3", CK_ULTRASPARC3)
7251 .Case("niagara", CK_NIAGARA)
7252 .Case("niagara2", CK_NIAGARA2)
7253 .Case("niagara3", CK_NIAGARA3)
7254 .Case("niagara4", CK_NIAGARA4)
7255 .Case("ma2100", CK_MYRIAD2100)
7256 .Case("ma2150", CK_MYRIAD2150)
7257 .Case("ma2450", CK_MYRIAD2450)
7258 // FIXME: the myriad2[.n] spellings are obsolete,
7259 // but a grace period is needed to allow updating dependent builds.
7260 .Case("myriad2", CK_MYRIAD2100)
7261 .Case("myriad2.1", CK_MYRIAD2100)
7262 .Case("myriad2.2", CK_MYRIAD2150)
7263 .Case("leon2", CK_LEON2)
7264 .Case("at697e", CK_LEON2_AT697E)
7265 .Case("at697f", CK_LEON2_AT697F)
7266 .Case("leon3", CK_LEON3)
7267 .Case("ut699", CK_LEON3_UT699)
7268 .Case("gr712rc", CK_LEON3_GR712RC)
7269 .Case("leon4", CK_LEON4)
7270 .Case("gr740", CK_LEON4_GR740)
7271 .Default(CK_GENERIC);
7274 bool setCPU(const std::string &Name) override {
7275 CPU = getCPUKind(Name);
7276 return CPU != CK_GENERIC;
7280 const char * const SparcTargetInfo::GCCRegNames[] = {
7281 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7282 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7283 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
7284 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
7287 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
7288 return llvm::makeArrayRef(GCCRegNames);
7291 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
7302 { { "o2" }, "r10" },
7303 { { "o3" }, "r11" },
7304 { { "o4" }, "r12" },
7305 { { "o5" }, "r13" },
7306 { { "o6", "sp" }, "r14" },
7307 { { "o7" }, "r15" },
7308 { { "l0" }, "r16" },
7309 { { "l1" }, "r17" },
7310 { { "l2" }, "r18" },
7311 { { "l3" }, "r19" },
7312 { { "l4" }, "r20" },
7313 { { "l5" }, "r21" },
7314 { { "l6" }, "r22" },
7315 { { "l7" }, "r23" },
7316 { { "i0" }, "r24" },
7317 { { "i1" }, "r25" },
7318 { { "i2" }, "r26" },
7319 { { "i3" }, "r27" },
7320 { { "i4" }, "r28" },
7321 { { "i5" }, "r29" },
7322 { { "i6", "fp" }, "r30" },
7323 { { "i7" }, "r31" },
7326 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
7327 return llvm::makeArrayRef(GCCRegAliases);
7330 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
7331 class SparcV8TargetInfo : public SparcTargetInfo {
7333 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7334 : SparcTargetInfo(Triple, Opts) {
7335 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64");
7336 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
7337 switch (getTriple().getOS()) {
7339 SizeType = UnsignedInt;
7340 IntPtrType = SignedInt;
7341 PtrDiffType = SignedInt;
7343 case llvm::Triple::NetBSD:
7344 case llvm::Triple::OpenBSD:
7345 SizeType = UnsignedLong;
7346 IntPtrType = SignedLong;
7347 PtrDiffType = SignedLong;
7350 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops
7351 // on up to 64 bits.
7352 MaxAtomicPromoteWidth = 64;
7353 MaxAtomicInlineWidth = 32;
7356 void getTargetDefines(const LangOptions &Opts,
7357 MacroBuilder &Builder) const override {
7358 SparcTargetInfo::getTargetDefines(Opts, Builder);
7359 switch (getCPUGeneration(CPU)) {
7361 Builder.defineMacro("__sparcv8");
7362 if (getTriple().getOS() != llvm::Triple::Solaris)
7363 Builder.defineMacro("__sparcv8__");
7366 Builder.defineMacro("__sparcv9");
7367 if (getTriple().getOS() != llvm::Triple::Solaris) {
7368 Builder.defineMacro("__sparcv9__");
7369 Builder.defineMacro("__sparc_v9__");
7373 if (getTriple().getVendor() == llvm::Triple::Myriad) {
7374 std::string MyriadArchValue, Myriad2Value;
7375 Builder.defineMacro("__sparc_v8__");
7376 Builder.defineMacro("__leon__");
7379 MyriadArchValue = "__ma2150";
7383 MyriadArchValue = "__ma2450";
7387 MyriadArchValue = "__ma2100";
7391 Builder.defineMacro(MyriadArchValue, "1");
7392 Builder.defineMacro(MyriadArchValue+"__", "1");
7393 Builder.defineMacro("__myriad2__", Myriad2Value);
7394 Builder.defineMacro("__myriad2", Myriad2Value);
7398 bool hasSjLjLowering() const override {
7403 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
7404 class SparcV8elTargetInfo : public SparcV8TargetInfo {
7406 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7407 : SparcV8TargetInfo(Triple, Opts) {
7408 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64");
7412 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
7413 class SparcV9TargetInfo : public SparcTargetInfo {
7415 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7416 : SparcTargetInfo(Triple, Opts) {
7417 // FIXME: Support Sparc quad-precision long double?
7418 resetDataLayout("E-m:e-i64:64-n32:64-S128");
7419 // This is an LP64 platform.
7420 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7422 // OpenBSD uses long long for int64_t and intmax_t.
7423 if (getTriple().getOS() == llvm::Triple::OpenBSD)
7424 IntMaxType = SignedLongLong;
7426 IntMaxType = SignedLong;
7427 Int64Type = IntMaxType;
7429 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
7430 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
7431 LongDoubleWidth = 128;
7432 LongDoubleAlign = 128;
7433 LongDoubleFormat = &llvm::APFloat::IEEEquad();
7434 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7437 void getTargetDefines(const LangOptions &Opts,
7438 MacroBuilder &Builder) const override {
7439 SparcTargetInfo::getTargetDefines(Opts, Builder);
7440 Builder.defineMacro("__sparcv9");
7441 Builder.defineMacro("__arch64__");
7442 // Solaris doesn't need these variants, but the BSDs do.
7443 if (getTriple().getOS() != llvm::Triple::Solaris) {
7444 Builder.defineMacro("__sparc64__");
7445 Builder.defineMacro("__sparc_v9__");
7446 Builder.defineMacro("__sparcv9__");
7450 bool setCPU(const std::string &Name) override {
7451 if (!SparcTargetInfo::setCPU(Name))
7453 return getCPUGeneration(CPU) == CG_V9;
7457 class SystemZTargetInfo : public TargetInfo {
7458 static const Builtin::Info BuiltinInfo[];
7459 static const char *const GCCRegNames[];
7462 bool HasTransactionalExecution;
7466 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7467 : TargetInfo(Triple), CPU("z10"), ISARevision(8),
7468 HasTransactionalExecution(false), HasVector(false) {
7469 IntMaxType = SignedLong;
7470 Int64Type = SignedLong;
7471 TLSSupported = true;
7472 IntWidth = IntAlign = 32;
7473 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
7474 PointerWidth = PointerAlign = 64;
7475 LongDoubleWidth = 128;
7476 LongDoubleAlign = 64;
7477 LongDoubleFormat = &llvm::APFloat::IEEEquad();
7478 DefaultAlignForAttributeAligned = 64;
7479 MinGlobalAlign = 16;
7480 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64");
7481 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7483 void getTargetDefines(const LangOptions &Opts,
7484 MacroBuilder &Builder) const override {
7485 Builder.defineMacro("__s390__");
7486 Builder.defineMacro("__s390x__");
7487 Builder.defineMacro("__zarch__");
7488 Builder.defineMacro("__LONG_DOUBLE_128__");
7490 Builder.defineMacro("__ARCH__", Twine(ISARevision));
7492 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
7493 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
7494 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
7495 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
7497 if (HasTransactionalExecution)
7498 Builder.defineMacro("__HTM__");
7500 Builder.defineMacro("__VX__");
7502 Builder.defineMacro("__VEC__", "10302");
7504 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7505 return llvm::makeArrayRef(BuiltinInfo,
7506 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin);
7509 ArrayRef<const char *> getGCCRegNames() const override;
7510 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7514 bool validateAsmConstraint(const char *&Name,
7515 TargetInfo::ConstraintInfo &info) const override;
7516 const char *getClobbers() const override {
7517 // FIXME: Is this really right?
7520 BuiltinVaListKind getBuiltinVaListKind() const override {
7521 return TargetInfo::SystemZBuiltinVaList;
7523 int getISARevision(const StringRef &Name) const {
7524 return llvm::StringSwitch<int>(Name)
7525 .Cases("arch8", "z10", 8)
7526 .Cases("arch9", "z196", 9)
7527 .Cases("arch10", "zEC12", 10)
7528 .Cases("arch11", "z13", 11)
7529 .Cases("arch12", "z14", 12)
7532 bool setCPU(const std::string &Name) override {
7534 ISARevision = getISARevision(CPU);
7535 return ISARevision != -1;
7538 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7540 const std::vector<std::string> &FeaturesVec) const override {
7541 int ISARevision = getISARevision(CPU);
7542 if (ISARevision >= 10)
7543 Features["transactional-execution"] = true;
7544 if (ISARevision >= 11)
7545 Features["vector"] = true;
7546 if (ISARevision >= 12)
7547 Features["vector-enhancements-1"] = true;
7548 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7551 bool handleTargetFeatures(std::vector<std::string> &Features,
7552 DiagnosticsEngine &Diags) override {
7553 HasTransactionalExecution = false;
7555 for (const auto &Feature : Features) {
7556 if (Feature == "+transactional-execution")
7557 HasTransactionalExecution = true;
7558 else if (Feature == "+vector")
7561 // If we use the vector ABI, vector types are 64-bit aligned.
7563 MaxVectorAlign = 64;
7564 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
7565 "-v128:64-a:8:16-n32:64");
7570 bool hasFeature(StringRef Feature) const override {
7571 return llvm::StringSwitch<bool>(Feature)
7572 .Case("systemz", true)
7573 .Case("arch8", ISARevision >= 8)
7574 .Case("arch9", ISARevision >= 9)
7575 .Case("arch10", ISARevision >= 10)
7576 .Case("arch11", ISARevision >= 11)
7577 .Case("arch12", ISARevision >= 12)
7578 .Case("htm", HasTransactionalExecution)
7579 .Case("vx", HasVector)
7583 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
7587 case CC_OpenCLKernel:
7590 return CCCR_Warning;
7594 StringRef getABI() const override {
7600 bool useFloat128ManglingForLongDouble() const override {
7605 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
7606 #define BUILTIN(ID, TYPE, ATTRS) \
7607 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7608 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
7609 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
7610 #include "clang/Basic/BuiltinsSystemZ.def"
7613 const char *const SystemZTargetInfo::GCCRegNames[] = {
7614 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7615 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7616 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
7617 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
7620 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
7621 return llvm::makeArrayRef(GCCRegNames);
7624 bool SystemZTargetInfo::
7625 validateAsmConstraint(const char *&Name,
7626 TargetInfo::ConstraintInfo &Info) const {
7631 case 'a': // Address register
7632 case 'd': // Data register (equivalent to 'r')
7633 case 'f': // Floating-point register
7634 Info.setAllowsRegister();
7637 case 'I': // Unsigned 8-bit constant
7638 case 'J': // Unsigned 12-bit constant
7639 case 'K': // Signed 16-bit constant
7640 case 'L': // Signed 20-bit displacement (on all targets we support)
7641 case 'M': // 0x7fffffff
7644 case 'Q': // Memory with base and unsigned 12-bit displacement
7645 case 'R': // Likewise, plus an index
7646 case 'S': // Memory with base and signed 20-bit displacement
7647 case 'T': // Likewise, plus an index
7648 Info.setAllowsMemory();
7653 class MSP430TargetInfo : public TargetInfo {
7654 static const char *const GCCRegNames[];
7657 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7658 : TargetInfo(Triple) {
7659 TLSSupported = false;
7664 LongAlign = LongLongAlign = 16;
7668 SizeType = UnsignedInt;
7669 IntMaxType = SignedLongLong;
7670 IntPtrType = SignedInt;
7671 PtrDiffType = SignedInt;
7672 SigAtomicType = SignedLong;
7673 resetDataLayout("e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16");
7675 void getTargetDefines(const LangOptions &Opts,
7676 MacroBuilder &Builder) const override {
7677 Builder.defineMacro("MSP430");
7678 Builder.defineMacro("__MSP430__");
7679 // FIXME: defines for different 'flavours' of MCU
7681 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7682 // FIXME: Implement.
7685 bool hasFeature(StringRef Feature) const override {
7686 return Feature == "msp430";
7688 ArrayRef<const char *> getGCCRegNames() const override;
7689 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7693 bool validateAsmConstraint(const char *&Name,
7694 TargetInfo::ConstraintInfo &info) const override {
7697 case 'K': // the constant 1
7698 case 'L': // constant -1^20 .. 1^19
7699 case 'M': // constant 1-4:
7702 // No target constraints for now.
7705 const char *getClobbers() const override {
7706 // FIXME: Is this really right?
7709 BuiltinVaListKind getBuiltinVaListKind() const override {
7711 return TargetInfo::CharPtrBuiltinVaList;
7715 const char *const MSP430TargetInfo::GCCRegNames[] = {
7716 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7717 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
7719 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const {
7720 return llvm::makeArrayRef(GCCRegNames);
7723 // LLVM and Clang cannot be used directly to output native binaries for
7724 // target, but is used to compile C code to llvm bitcode with correct
7725 // type and alignment information.
7727 // TCE uses the llvm bitcode as input and uses it for generating customized
7728 // target processor and program binary. TCE co-design environment is
7729 // publicly available in http://tce.cs.tut.fi
7731 static const unsigned TCEOpenCLAddrSpaceMap[] = {
7735 5, // opencl_constant
7736 // FIXME: generic has to be added to the target
7737 0, // opencl_generic
7743 class TCETargetInfo : public TargetInfo {
7745 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7746 : TargetInfo(Triple) {
7747 TLSSupported = false;
7749 LongWidth = LongLongWidth = 32;
7752 LongAlign = LongLongAlign = 32;
7755 SizeType = UnsignedInt;
7756 IntMaxType = SignedLong;
7757 IntPtrType = SignedInt;
7758 PtrDiffType = SignedInt;
7763 LongDoubleWidth = 32;
7764 LongDoubleAlign = 32;
7765 FloatFormat = &llvm::APFloat::IEEEsingle();
7766 DoubleFormat = &llvm::APFloat::IEEEsingle();
7767 LongDoubleFormat = &llvm::APFloat::IEEEsingle();
7768 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-"
7769 "i16:16:32-i32:32:32-i64:32:32-"
7770 "f32:32:32-f64:32:32-v64:32:32-"
7771 "v128:32:32-v256:32:32-v512:32:32-"
7772 "v1024:32:32-a0:0:32-n32");
7773 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
7774 UseAddrSpaceMapMangling = true;
7777 void getTargetDefines(const LangOptions &Opts,
7778 MacroBuilder &Builder) const override {
7779 DefineStd(Builder, "tce", Opts);
7780 Builder.defineMacro("__TCE__");
7781 Builder.defineMacro("__TCE_V1__");
7783 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; }
7785 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7786 const char *getClobbers() const override { return ""; }
7787 BuiltinVaListKind getBuiltinVaListKind() const override {
7788 return TargetInfo::VoidPtrBuiltinVaList;
7790 ArrayRef<const char *> getGCCRegNames() const override { return None; }
7791 bool validateAsmConstraint(const char *&Name,
7792 TargetInfo::ConstraintInfo &info) const override {
7795 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7800 class TCELETargetInfo : public TCETargetInfo {
7802 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7803 : TCETargetInfo(Triple, Opts) {
7806 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-"
7807 "i16:16:32-i32:32:32-i64:32:32-"
7808 "f32:32:32-f64:32:32-v64:32:32-"
7809 "v128:32:32-v256:32:32-v512:32:32-"
7810 "v1024:32:32-a0:0:32-n32");
7814 virtual void getTargetDefines(const LangOptions &Opts,
7815 MacroBuilder &Builder) const {
7816 DefineStd(Builder, "tcele", Opts);
7817 Builder.defineMacro("__TCE__");
7818 Builder.defineMacro("__TCE_V1__");
7819 Builder.defineMacro("__TCELE__");
7820 Builder.defineMacro("__TCELE_V1__");
7825 class BPFTargetInfo : public TargetInfo {
7827 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7828 : TargetInfo(Triple) {
7829 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7830 SizeType = UnsignedLong;
7831 PtrDiffType = SignedLong;
7832 IntPtrType = SignedLong;
7833 IntMaxType = SignedLong;
7834 Int64Type = SignedLong;
7836 if (Triple.getArch() == llvm::Triple::bpfeb) {
7837 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128");
7839 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
7841 MaxAtomicPromoteWidth = 64;
7842 MaxAtomicInlineWidth = 64;
7843 TLSSupported = false;
7845 void getTargetDefines(const LangOptions &Opts,
7846 MacroBuilder &Builder) const override {
7847 DefineStd(Builder, "bpf", Opts);
7848 Builder.defineMacro("__BPF__");
7850 bool hasFeature(StringRef Feature) const override {
7851 return Feature == "bpf";
7854 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7855 const char *getClobbers() const override {
7858 BuiltinVaListKind getBuiltinVaListKind() const override {
7859 return TargetInfo::VoidPtrBuiltinVaList;
7861 ArrayRef<const char *> getGCCRegNames() const override {
7864 bool validateAsmConstraint(const char *&Name,
7865 TargetInfo::ConstraintInfo &info) const override {
7868 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7871 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
7874 return CCCR_Warning;
7876 case CC_OpenCLKernel:
7882 class Nios2TargetInfo : public TargetInfo {
7883 void setDataLayout() {
7885 resetDataLayout("E-p:32:32:32-i8:8:32-i16:16:32-n32");
7887 resetDataLayout("e-p:32:32:32-i8:8:32-i16:16:32-n32");
7890 static const Builtin::Info BuiltinInfo[];
7895 Nios2TargetInfo(const llvm::Triple &triple, const TargetOptions &opts)
7896 : TargetInfo(triple), CPU(opts.CPU), ABI(opts.ABI) {
7897 SizeType = UnsignedInt;
7898 PtrDiffType = SignedInt;
7899 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
7903 StringRef getABI() const override { return ABI; }
7904 bool setABI(const std::string &Name) override {
7905 if (Name == "o32" || Name == "eabi") {
7912 bool setCPU(const std::string &Name) override {
7913 if (Name == "nios2r1" || Name == "nios2r2") {
7920 void getTargetDefines(const LangOptions &Opts,
7921 MacroBuilder &Builder) const override {
7922 DefineStd(Builder, "nios2", Opts);
7923 DefineStd(Builder, "NIOS2", Opts);
7925 Builder.defineMacro("__nios2");
7926 Builder.defineMacro("__NIOS2");
7927 Builder.defineMacro("__nios2__");
7928 Builder.defineMacro("__NIOS2__");
7931 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7932 return llvm::makeArrayRef(BuiltinInfo, clang::Nios2::LastTSBuiltin -
7933 Builtin::FirstTSBuiltin);
7936 bool isFeatureSupportedByCPU(StringRef Feature, StringRef CPU) const {
7937 const bool isR2 = CPU == "nios2r2";
7938 return llvm::StringSwitch<bool>(Feature)
7939 .Case("nios2r2mandatory", isR2)
7940 .Case("nios2r2bmx", isR2)
7941 .Case("nios2r2mpx", isR2)
7942 .Case("nios2r2cdx", isR2)
7946 bool initFeatureMap(llvm::StringMap<bool> &Features,
7947 DiagnosticsEngine &Diags, StringRef CPU,
7948 const std::vector<std::string> &FeatureVec) const override {
7949 static const char *allFeatures[] = {
7950 "nios2r2mandatory", "nios2r2bmx", "nios2r2mpx", "nios2r2cdx"
7952 for (const char *feature : allFeatures) {
7953 Features[feature] = isFeatureSupportedByCPU(feature, CPU);
7958 bool hasFeature(StringRef Feature) const override {
7959 return isFeatureSupportedByCPU(Feature, CPU);
7962 BuiltinVaListKind getBuiltinVaListKind() const override {
7963 return TargetInfo::VoidPtrBuiltinVaList;
7966 ArrayRef<const char *> getGCCRegNames() const override {
7967 static const char *const GCCRegNames[] = {
7968 // CPU register names
7969 // Must match second column of GCCRegAliases
7970 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
7971 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20",
7972 "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30",
7974 // Floating point register names
7975 "ctl0", "ctl1", "ctl2", "ctl3", "ctl4", "ctl5", "ctl6", "ctl7", "ctl8",
7976 "ctl9", "ctl10", "ctl11", "ctl12", "ctl13", "ctl14", "ctl15"
7978 return llvm::makeArrayRef(GCCRegNames);
7981 bool validateAsmConstraint(const char *&Name,
7982 TargetInfo::ConstraintInfo &Info) const override {
7987 case 'r': // CPU registers.
7988 case 'd': // Equivalent to "r" unless generating MIPS16 code.
7989 case 'y': // Equivalent to "r", backwards compatibility only.
7990 case 'f': // floating-point registers.
7991 case 'c': // $25 for indirect jumps
7992 case 'l': // lo register
7993 case 'x': // hilo register pair
7994 Info.setAllowsRegister();
7999 const char *getClobbers() const override { return ""; }
8001 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8002 static const TargetInfo::GCCRegAlias aliases[] = {
8003 {{"zero"}, "r0"}, {{"at"}, "r1"}, {{"et"}, "r24"},
8004 {{"bt"}, "r25"}, {{"gp"}, "r26"}, {{"sp"}, "r27"},
8005 {{"fp"}, "r28"}, {{"ea"}, "r29"}, {{"ba"}, "r30"},
8006 {{"ra"}, "r31"}, {{"status"}, "ctl0"}, {{"estatus"}, "ctl1"},
8007 {{"bstatus"}, "ctl2"}, {{"ienable"}, "ctl3"}, {{"ipending"}, "ctl4"},
8008 {{"cpuid"}, "ctl5"}, {{"exception"}, "ctl7"}, {{"pteaddr"}, "ctl8"},
8009 {{"tlbacc"}, "ctl9"}, {{"tlbmisc"}, "ctl10"}, {{"badaddr"}, "ctl12"},
8010 {{"config"}, "ctl13"}, {{"mpubase"}, "ctl14"}, {{"mpuacc"}, "ctl15"},
8012 return llvm::makeArrayRef(aliases);
8016 const Builtin::Info Nios2TargetInfo::BuiltinInfo[] = {
8017 #define BUILTIN(ID, TYPE, ATTRS) \
8018 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
8019 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
8020 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
8021 #include "clang/Basic/BuiltinsNios2.def"
8024 class MipsTargetInfo : public TargetInfo {
8025 void setDataLayout() {
8029 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
8030 else if (ABI == "n32")
8031 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
8032 else if (ABI == "n64")
8033 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128";
8035 llvm_unreachable("Invalid ABI");
8038 resetDataLayout(("E-" + Layout).str());
8040 resetDataLayout(("e-" + Layout).str());
8044 static const Builtin::Info BuiltinInfo[];
8051 bool CanUseBSDABICalls;
8053 HardFloat, SoftFloat
8066 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8067 : TargetInfo(Triple), IsMips16(false), IsMicromips(false),
8068 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false),
8069 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP),
8070 HasMSA(false), DisableMadd4(false), HasFP64(false) {
8071 TheCXXABI.set(TargetCXXABI::GenericMIPS);
8073 setABI((getTriple().getArch() == llvm::Triple::mips ||
8074 getTriple().getArch() == llvm::Triple::mipsel)
8078 CPU = ABI == "o32" ? "mips32r2" : "mips64r2";
8080 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD ||
8081 Triple.getOS() == llvm::Triple::OpenBSD;
8084 bool isNaN2008Default() const {
8085 return CPU == "mips32r6" || CPU == "mips64r6";
8088 bool isFP64Default() const {
8089 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
8092 bool isNan2008() const override {
8096 bool processorSupportsGPR64() const {
8097 return llvm::StringSwitch<bool>(CPU)
8098 .Case("mips3", true)
8099 .Case("mips4", true)
8100 .Case("mips5", true)
8101 .Case("mips64", true)
8102 .Case("mips64r2", true)
8103 .Case("mips64r3", true)
8104 .Case("mips64r5", true)
8105 .Case("mips64r6", true)
8106 .Case("octeon", true)
8111 StringRef getABI() const override { return ABI; }
8112 bool setABI(const std::string &Name) override {
8113 if (Name == "o32") {
8119 if (Name == "n32") {
8124 if (Name == "n64") {
8132 void setO32ABITypes() {
8133 Int64Type = SignedLongLong;
8134 IntMaxType = Int64Type;
8135 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
8136 LongDoubleWidth = LongDoubleAlign = 64;
8137 LongWidth = LongAlign = 32;
8138 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
8139 PointerWidth = PointerAlign = 32;
8140 PtrDiffType = SignedInt;
8141 SizeType = UnsignedInt;
8145 void setN32N64ABITypes() {
8146 LongDoubleWidth = LongDoubleAlign = 128;
8147 LongDoubleFormat = &llvm::APFloat::IEEEquad();
8148 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
8149 LongDoubleWidth = LongDoubleAlign = 64;
8150 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
8152 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8153 SuitableAlign = 128;
8156 void setN64ABITypes() {
8157 setN32N64ABITypes();
8158 if (getTriple().getOS() == llvm::Triple::OpenBSD) {
8159 Int64Type = SignedLongLong;
8161 Int64Type = SignedLong;
8163 IntMaxType = Int64Type;
8164 LongWidth = LongAlign = 64;
8165 PointerWidth = PointerAlign = 64;
8166 PtrDiffType = SignedLong;
8167 SizeType = UnsignedLong;
8170 void setN32ABITypes() {
8171 setN32N64ABITypes();
8172 Int64Type = SignedLongLong;
8173 IntMaxType = Int64Type;
8174 LongWidth = LongAlign = 32;
8175 PointerWidth = PointerAlign = 32;
8176 PtrDiffType = SignedInt;
8177 SizeType = UnsignedInt;
8180 bool setCPU(const std::string &Name) override {
8182 return llvm::StringSwitch<bool>(Name)
8183 .Case("mips1", true)
8184 .Case("mips2", true)
8185 .Case("mips3", true)
8186 .Case("mips4", true)
8187 .Case("mips5", true)
8188 .Case("mips32", true)
8189 .Case("mips32r2", true)
8190 .Case("mips32r3", true)
8191 .Case("mips32r5", true)
8192 .Case("mips32r6", true)
8193 .Case("mips64", true)
8194 .Case("mips64r2", true)
8195 .Case("mips64r3", true)
8196 .Case("mips64r5", true)
8197 .Case("mips64r6", true)
8198 .Case("octeon", true)
8199 .Case("p5600", true)
8202 const std::string& getCPU() const { return CPU; }
8204 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
8206 const std::vector<std::string> &FeaturesVec) const override {
8209 if (CPU == "octeon")
8210 Features["mips64r2"] = Features["cnmips"] = true;
8212 Features[CPU] = true;
8213 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
8216 void getTargetDefines(const LangOptions &Opts,
8217 MacroBuilder &Builder) const override {
8219 DefineStd(Builder, "MIPSEB", Opts);
8220 Builder.defineMacro("_MIPSEB");
8222 DefineStd(Builder, "MIPSEL", Opts);
8223 Builder.defineMacro("_MIPSEL");
8226 Builder.defineMacro("__mips__");
8227 Builder.defineMacro("_mips");
8229 Builder.defineMacro("mips");
8232 Builder.defineMacro("__mips", "32");
8233 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
8235 Builder.defineMacro("__mips", "64");
8236 Builder.defineMacro("__mips64");
8237 Builder.defineMacro("__mips64__");
8238 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
8241 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU())
8242 .Cases("mips32", "mips64", "1")
8243 .Cases("mips32r2", "mips64r2", "2")
8244 .Cases("mips32r3", "mips64r3", "3")
8245 .Cases("mips32r5", "mips64r5", "5")
8246 .Cases("mips32r6", "mips64r6", "6")
8248 if (!ISARev.empty())
8249 Builder.defineMacro("__mips_isa_rev", ISARev);
8252 Builder.defineMacro("__mips_o32");
8253 Builder.defineMacro("_ABIO32", "1");
8254 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
8255 } else if (ABI == "n32") {
8256 Builder.defineMacro("__mips_n32");
8257 Builder.defineMacro("_ABIN32", "2");
8258 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
8259 } else if (ABI == "n64") {
8260 Builder.defineMacro("__mips_n64");
8261 Builder.defineMacro("_ABI64", "3");
8262 Builder.defineMacro("_MIPS_SIM", "_ABI64");
8264 llvm_unreachable("Invalid ABI.");
8266 if (!IsNoABICalls) {
8267 Builder.defineMacro("__mips_abicalls");
8268 if (CanUseBSDABICalls)
8269 Builder.defineMacro("__ABICALLS__");
8272 Builder.defineMacro("__REGISTER_PREFIX__", "");
8276 Builder.defineMacro("__mips_hard_float", Twine(1));
8279 Builder.defineMacro("__mips_soft_float", Twine(1));
8284 Builder.defineMacro("__mips_single_float", Twine(1));
8286 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
8287 Builder.defineMacro("_MIPS_FPSET",
8288 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
8291 Builder.defineMacro("__mips16", Twine(1));
8294 Builder.defineMacro("__mips_micromips", Twine(1));
8297 Builder.defineMacro("__mips_nan2008", Twine(1));
8303 Builder.defineMacro("__mips_dsp_rev", Twine(1));
8304 Builder.defineMacro("__mips_dsp", Twine(1));
8307 Builder.defineMacro("__mips_dsp_rev", Twine(2));
8308 Builder.defineMacro("__mips_dspr2", Twine(1));
8309 Builder.defineMacro("__mips_dsp", Twine(1));
8314 Builder.defineMacro("__mips_msa", Twine(1));
8317 Builder.defineMacro("__mips_no_madd4", Twine(1));
8319 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
8320 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
8321 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
8323 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
8324 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
8326 // These shouldn't be defined for MIPS-I but there's no need to check
8327 // for that since MIPS-I isn't supported.
8328 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
8329 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
8330 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
8332 // 32-bit MIPS processors don't have the necessary lld/scd instructions
8333 // found in 64-bit processors. In the case of O32 on a 64-bit processor,
8334 // the instructions exist but using them violates the ABI since they
8335 // require 64-bit GPRs and O32 only supports 32-bit GPRs.
8336 if (ABI == "n32" || ABI == "n64")
8337 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
8340 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8341 return llvm::makeArrayRef(BuiltinInfo,
8342 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin);
8344 bool hasFeature(StringRef Feature) const override {
8345 return llvm::StringSwitch<bool>(Feature)
8347 .Case("fp64", HasFP64)
8350 BuiltinVaListKind getBuiltinVaListKind() const override {
8351 return TargetInfo::VoidPtrBuiltinVaList;
8353 ArrayRef<const char *> getGCCRegNames() const override {
8354 static const char *const GCCRegNames[] = {
8355 // CPU register names
8356 // Must match second column of GCCRegAliases
8357 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
8358 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
8359 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
8360 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
8361 // Floating point register names
8362 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
8363 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
8364 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
8365 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
8366 // Hi/lo and condition register names
8367 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
8368 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo",
8370 // MSA register names
8371 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
8372 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
8373 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
8374 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
8375 // MSA control register names
8376 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
8377 "$msarequest", "$msamap", "$msaunmap"
8379 return llvm::makeArrayRef(GCCRegNames);
8381 bool validateAsmConstraint(const char *&Name,
8382 TargetInfo::ConstraintInfo &Info) const override {
8386 case 'r': // CPU registers.
8387 case 'd': // Equivalent to "r" unless generating MIPS16 code.
8388 case 'y': // Equivalent to "r", backward compatibility only.
8389 case 'f': // floating-point registers.
8390 case 'c': // $25 for indirect jumps
8391 case 'l': // lo register
8392 case 'x': // hilo register pair
8393 Info.setAllowsRegister();
8395 case 'I': // Signed 16-bit constant
8396 case 'J': // Integer 0
8397 case 'K': // Unsigned 16-bit constant
8398 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
8399 case 'M': // Constants not loadable via lui, addiu, or ori
8400 case 'N': // Constant -1 to -65535
8401 case 'O': // A signed 15-bit constant
8402 case 'P': // A constant between 1 go 65535
8404 case 'R': // An address that can be used in a non-macro load or store
8405 Info.setAllowsMemory();
8408 if (Name[1] == 'C') { // An address usable by ll, and sc.
8409 Info.setAllowsMemory();
8410 Name++; // Skip over 'Z'.
8417 std::string convertConstraint(const char *&Constraint) const override {
8419 switch (*Constraint) {
8420 case 'Z': // Two-character constraint; add "^" hint for later parsing.
8421 if (Constraint[1] == 'C') {
8422 R = std::string("^") + std::string(Constraint, 2);
8428 return TargetInfo::convertConstraint(Constraint);
8431 const char *getClobbers() const override {
8432 // In GCC, $1 is not widely used in generated code (it's used only in a few
8433 // specific situations), so there is no real need for users to add it to
8434 // the clobbers list if they want to use it in their inline assembly code.
8436 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
8437 // code generation, so using it in inline assembly without adding it to the
8438 // clobbers list can cause conflicts between the inline assembly code and
8439 // the surrounding generated code.
8441 // Another problem is that LLVM is allowed to choose $1 for inline assembly
8442 // operands, which will conflict with the ".set at" assembler option (which
8443 // we use only for inline assembly, in order to maintain compatibility with
8444 // GCC) and will also conflict with the user's usage of $1.
8446 // The easiest way to avoid these conflicts and keep $1 as an allocatable
8447 // register for generated code is to automatically clobber $1 for all inline
8450 // FIXME: We should automatically clobber $1 only for inline assembly code
8451 // which actually uses it. This would allow LLVM to use $1 for inline
8452 // assembly operands if the user's assembly code doesn't use it.
8456 bool handleTargetFeatures(std::vector<std::string> &Features,
8457 DiagnosticsEngine &Diags) override {
8459 IsMicromips = false;
8460 IsNan2008 = isNaN2008Default();
8461 IsSingleFloat = false;
8462 FloatABI = HardFloat;
8464 HasFP64 = isFP64Default();
8466 for (const auto &Feature : Features) {
8467 if (Feature == "+single-float")
8468 IsSingleFloat = true;
8469 else if (Feature == "+soft-float")
8470 FloatABI = SoftFloat;
8471 else if (Feature == "+mips16")
8473 else if (Feature == "+micromips")
8475 else if (Feature == "+dsp")
8476 DspRev = std::max(DspRev, DSP1);
8477 else if (Feature == "+dspr2")
8478 DspRev = std::max(DspRev, DSP2);
8479 else if (Feature == "+msa")
8481 else if (Feature == "+nomadd4")
8482 DisableMadd4 = true;
8483 else if (Feature == "+fp64")
8485 else if (Feature == "-fp64")
8487 else if (Feature == "+nan2008")
8489 else if (Feature == "-nan2008")
8491 else if (Feature == "+noabicalls")
8492 IsNoABICalls = true;
8500 int getEHDataRegisterNumber(unsigned RegNo) const override {
8501 if (RegNo == 0) return 4;
8502 if (RegNo == 1) return 5;
8506 bool isCLZForZeroUndef() const override { return false; }
8508 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8509 static const TargetInfo::GCCRegAlias O32RegAliases[] = {
8510 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
8511 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
8512 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"},
8513 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"},
8514 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"},
8515 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
8516 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
8517 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
8518 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
8519 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
8521 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = {
8522 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
8523 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
8524 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"},
8525 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"},
8526 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"},
8527 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
8528 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
8529 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
8530 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
8531 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
8534 return llvm::makeArrayRef(O32RegAliases);
8535 return llvm::makeArrayRef(NewABIRegAliases);
8538 bool hasInt128Type() const override {
8539 return ABI == "n32" || ABI == "n64";
8542 bool validateTarget(DiagnosticsEngine &Diags) const override {
8543 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle
8544 // this yet. It's better to fail here than on the backend assertion.
8545 if (processorSupportsGPR64() && ABI == "o32") {
8546 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
8550 // 64-bit ABI's require 64-bit CPU's.
8551 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) {
8552 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
8556 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend
8557 // can't handle this yet. It's better to fail here than on the
8558 // backend assertion.
8559 if ((getTriple().getArch() == llvm::Triple::mips64 ||
8560 getTriple().getArch() == llvm::Triple::mips64el) &&
8562 Diags.Report(diag::err_target_unsupported_abi_for_triple)
8563 << ABI << getTriple().str();
8567 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend
8568 // can't handle this yet. It's better to fail here than on the
8569 // backend assertion.
8570 if ((getTriple().getArch() == llvm::Triple::mips ||
8571 getTriple().getArch() == llvm::Triple::mipsel) &&
8572 (ABI == "n32" || ABI == "n64")) {
8573 Diags.Report(diag::err_target_unsupported_abi_for_triple)
8574 << ABI << getTriple().str();
8582 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = {
8583 #define BUILTIN(ID, TYPE, ATTRS) \
8584 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8585 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8586 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8587 #include "clang/Basic/BuiltinsMips.def"
8590 class PNaClTargetInfo : public TargetInfo {
8592 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8593 : TargetInfo(Triple) {
8594 this->LongAlign = 32;
8595 this->LongWidth = 32;
8596 this->PointerAlign = 32;
8597 this->PointerWidth = 32;
8598 this->IntMaxType = TargetInfo::SignedLongLong;
8599 this->Int64Type = TargetInfo::SignedLongLong;
8600 this->DoubleAlign = 64;
8601 this->LongDoubleWidth = 64;
8602 this->LongDoubleAlign = 64;
8603 this->SizeType = TargetInfo::UnsignedInt;
8604 this->PtrDiffType = TargetInfo::SignedInt;
8605 this->IntPtrType = TargetInfo::SignedInt;
8606 this->RegParmMax = 0; // Disallow regparm
8609 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
8610 Builder.defineMacro("__le32__");
8611 Builder.defineMacro("__pnacl__");
8613 void getTargetDefines(const LangOptions &Opts,
8614 MacroBuilder &Builder) const override {
8615 getArchDefines(Opts, Builder);
8617 bool hasFeature(StringRef Feature) const override {
8618 return Feature == "pnacl";
8620 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
8621 BuiltinVaListKind getBuiltinVaListKind() const override {
8622 return TargetInfo::PNaClABIBuiltinVaList;
8624 ArrayRef<const char *> getGCCRegNames() const override;
8625 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
8626 bool validateAsmConstraint(const char *&Name,
8627 TargetInfo::ConstraintInfo &Info) const override {
8631 const char *getClobbers() const override {
8636 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const {
8640 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const {
8644 // We attempt to use PNaCl (le32) frontend and Mips32EL backend.
8645 class NaClMips32TargetInfo : public MipsTargetInfo {
8647 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8648 : MipsTargetInfo(Triple, Opts) {}
8650 BuiltinVaListKind getBuiltinVaListKind() const override {
8651 return TargetInfo::PNaClABIBuiltinVaList;
8655 class Le64TargetInfo : public TargetInfo {
8656 static const Builtin::Info BuiltinInfo[];
8659 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8660 : TargetInfo(Triple) {
8661 NoAsmVariants = true;
8662 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
8663 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8664 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128");
8667 void getTargetDefines(const LangOptions &Opts,
8668 MacroBuilder &Builder) const override {
8669 DefineStd(Builder, "unix", Opts);
8670 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
8671 Builder.defineMacro("__ELF__");
8673 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8674 return llvm::makeArrayRef(BuiltinInfo,
8675 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin);
8677 BuiltinVaListKind getBuiltinVaListKind() const override {
8678 return TargetInfo::PNaClABIBuiltinVaList;
8680 const char *getClobbers() const override { return ""; }
8681 ArrayRef<const char *> getGCCRegNames() const override {
8684 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8687 bool validateAsmConstraint(const char *&Name,
8688 TargetInfo::ConstraintInfo &Info) const override {
8692 bool hasProtectedVisibility() const override { return false; }
8695 class WebAssemblyTargetInfo : public TargetInfo {
8696 static const Builtin::Info BuiltinInfo[];
8704 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &)
8705 : TargetInfo(T), SIMDLevel(NoSIMD) {
8706 NoAsmVariants = true;
8707 SuitableAlign = 128;
8708 LargeArrayMinWidth = 128;
8709 LargeArrayAlign = 128;
8710 SimdDefaultAlign = 128;
8711 SigAtomicType = SignedLong;
8712 LongDoubleWidth = LongDoubleAlign = 128;
8713 LongDoubleFormat = &llvm::APFloat::IEEEquad();
8714 SizeType = UnsignedInt;
8715 PtrDiffType = SignedInt;
8716 IntPtrType = SignedInt;
8720 void getTargetDefines(const LangOptions &Opts,
8721 MacroBuilder &Builder) const override {
8722 defineCPUMacros(Builder, "wasm", /*Tuning=*/false);
8723 if (SIMDLevel >= SIMD128)
8724 Builder.defineMacro("__wasm_simd128__");
8729 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
8731 const std::vector<std::string> &FeaturesVec) const override {
8732 if (CPU == "bleeding-edge")
8733 Features["simd128"] = true;
8734 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
8736 bool hasFeature(StringRef Feature) const final {
8737 return llvm::StringSwitch<bool>(Feature)
8738 .Case("simd128", SIMDLevel >= SIMD128)
8741 bool handleTargetFeatures(std::vector<std::string> &Features,
8742 DiagnosticsEngine &Diags) final {
8743 for (const auto &Feature : Features) {
8744 if (Feature == "+simd128") {
8745 SIMDLevel = std::max(SIMDLevel, SIMD128);
8748 if (Feature == "-simd128") {
8749 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1));
8753 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature
8754 << "-target-feature";
8759 bool setCPU(const std::string &Name) final {
8760 return llvm::StringSwitch<bool>(Name)
8762 .Case("bleeding-edge", true)
8763 .Case("generic", true)
8766 ArrayRef<Builtin::Info> getTargetBuiltins() const final {
8767 return llvm::makeArrayRef(BuiltinInfo,
8768 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin);
8770 BuiltinVaListKind getBuiltinVaListKind() const final {
8771 return VoidPtrBuiltinVaList;
8773 ArrayRef<const char *> getGCCRegNames() const final {
8776 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final {
8780 validateAsmConstraint(const char *&Name,
8781 TargetInfo::ConstraintInfo &Info) const final {
8784 const char *getClobbers() const final { return ""; }
8785 bool isCLZForZeroUndef() const final { return false; }
8786 bool hasInt128Type() const final { return true; }
8787 IntType getIntTypeByWidth(unsigned BitWidth,
8788 bool IsSigned) const final {
8789 // WebAssembly prefers long long for explicitly 64-bit integers.
8790 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
8791 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
8793 IntType getLeastIntTypeByWidth(unsigned BitWidth,
8794 bool IsSigned) const final {
8795 // WebAssembly uses long long for int_least64_t and int_fast64_t.
8796 return BitWidth == 64
8797 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
8798 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
8802 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = {
8803 #define BUILTIN(ID, TYPE, ATTRS) \
8804 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8805 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8806 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8807 #include "clang/Basic/BuiltinsWebAssembly.def"
8810 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo {
8812 explicit WebAssembly32TargetInfo(const llvm::Triple &T,
8813 const TargetOptions &Opts)
8814 : WebAssemblyTargetInfo(T, Opts) {
8815 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8816 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128");
8820 void getTargetDefines(const LangOptions &Opts,
8821 MacroBuilder &Builder) const override {
8822 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
8823 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false);
8827 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo {
8829 explicit WebAssembly64TargetInfo(const llvm::Triple &T,
8830 const TargetOptions &Opts)
8831 : WebAssemblyTargetInfo(T, Opts) {
8832 LongAlign = LongWidth = 64;
8833 PointerAlign = PointerWidth = 64;
8834 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8835 SizeType = UnsignedLong;
8836 PtrDiffType = SignedLong;
8837 IntPtrType = SignedLong;
8838 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
8842 void getTargetDefines(const LangOptions &Opts,
8843 MacroBuilder &Builder) const override {
8844 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
8845 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false);
8849 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
8850 #define BUILTIN(ID, TYPE, ATTRS) \
8851 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8852 #include "clang/Basic/BuiltinsLe64.def"
8855 static const unsigned SPIRAddrSpaceMap[] = {
8859 2, // opencl_constant
8860 4, // opencl_generic
8865 class SPIRTargetInfo : public TargetInfo {
8867 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8868 : TargetInfo(Triple) {
8869 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
8870 "SPIR target must use unknown OS");
8871 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
8872 "SPIR target must use unknown environment type");
8873 TLSSupported = false;
8874 LongWidth = LongAlign = 64;
8875 AddrSpaceMap = &SPIRAddrSpaceMap;
8876 UseAddrSpaceMapMangling = true;
8877 // Define available target features
8878 // These must be defined in sorted order!
8879 NoAsmVariants = true;
8881 void getTargetDefines(const LangOptions &Opts,
8882 MacroBuilder &Builder) const override {
8883 DefineStd(Builder, "SPIR", Opts);
8885 bool hasFeature(StringRef Feature) const override {
8886 return Feature == "spir";
8889 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
8890 const char *getClobbers() const override { return ""; }
8891 ArrayRef<const char *> getGCCRegNames() const override { return None; }
8892 bool validateAsmConstraint(const char *&Name,
8893 TargetInfo::ConstraintInfo &info) const override {
8896 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8899 BuiltinVaListKind getBuiltinVaListKind() const override {
8900 return TargetInfo::VoidPtrBuiltinVaList;
8903 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
8904 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK
8908 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
8909 return CC_SpirFunction;
8912 void setSupportedOpenCLOpts() override {
8913 // Assume all OpenCL extensions and optional core features are supported
8914 // for SPIR since it is a generic target.
8915 getSupportedOpenCLOpts().supportAll();
8919 class SPIR32TargetInfo : public SPIRTargetInfo {
8921 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8922 : SPIRTargetInfo(Triple, Opts) {
8923 PointerWidth = PointerAlign = 32;
8924 SizeType = TargetInfo::UnsignedInt;
8925 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
8926 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
8927 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
8929 void getTargetDefines(const LangOptions &Opts,
8930 MacroBuilder &Builder) const override {
8931 DefineStd(Builder, "SPIR32", Opts);
8935 class SPIR64TargetInfo : public SPIRTargetInfo {
8937 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8938 : SPIRTargetInfo(Triple, Opts) {
8939 PointerWidth = PointerAlign = 64;
8940 SizeType = TargetInfo::UnsignedLong;
8941 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
8942 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
8943 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
8945 void getTargetDefines(const LangOptions &Opts,
8946 MacroBuilder &Builder) const override {
8947 DefineStd(Builder, "SPIR64", Opts);
8951 class XCoreTargetInfo : public TargetInfo {
8952 static const Builtin::Info BuiltinInfo[];
8954 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8955 : TargetInfo(Triple) {
8956 NoAsmVariants = true;
8959 DoubleAlign = LongDoubleAlign = 32;
8960 SizeType = UnsignedInt;
8961 PtrDiffType = SignedInt;
8962 IntPtrType = SignedInt;
8963 WCharType = UnsignedChar;
8964 WIntType = UnsignedInt;
8965 UseZeroLengthBitfieldAlignment = true;
8966 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
8967 "-f64:32-a:0:32-n32");
8969 void getTargetDefines(const LangOptions &Opts,
8970 MacroBuilder &Builder) const override {
8971 Builder.defineMacro("__XS1B__");
8973 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8974 return llvm::makeArrayRef(BuiltinInfo,
8975 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin);
8977 BuiltinVaListKind getBuiltinVaListKind() const override {
8978 return TargetInfo::VoidPtrBuiltinVaList;
8980 const char *getClobbers() const override {
8983 ArrayRef<const char *> getGCCRegNames() const override {
8984 static const char * const GCCRegNames[] = {
8985 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8986 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
8988 return llvm::makeArrayRef(GCCRegNames);
8990 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8993 bool validateAsmConstraint(const char *&Name,
8994 TargetInfo::ConstraintInfo &Info) const override {
8997 int getEHDataRegisterNumber(unsigned RegNo) const override {
8998 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
8999 return (RegNo < 2)? RegNo : -1;
9001 bool allowsLargerPreferedTypeAlignment() const override {
9006 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
9007 #define BUILTIN(ID, TYPE, ATTRS) \
9008 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
9009 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
9010 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
9011 #include "clang/Basic/BuiltinsXCore.def"
9014 // x86_32 Android target
9015 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
9017 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
9018 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) {
9020 LongDoubleWidth = 64;
9021 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
9025 // x86_64 Android target
9026 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
9028 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
9029 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) {
9030 LongDoubleFormat = &llvm::APFloat::IEEEquad();
9033 bool useFloat128ManglingForLongDouble() const override {
9038 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes
9039 class RenderScript32TargetInfo : public ARMleTargetInfo {
9041 RenderScript32TargetInfo(const llvm::Triple &Triple,
9042 const TargetOptions &Opts)
9043 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(),
9045 Triple.getEnvironmentName()),
9047 IsRenderScriptTarget = true;
9048 LongWidth = LongAlign = 64;
9050 void getTargetDefines(const LangOptions &Opts,
9051 MacroBuilder &Builder) const override {
9052 Builder.defineMacro("__RENDERSCRIPT__");
9053 ARMleTargetInfo::getTargetDefines(Opts, Builder);
9057 // 64-bit RenderScript is aarch64
9058 class RenderScript64TargetInfo : public AArch64leTargetInfo {
9060 RenderScript64TargetInfo(const llvm::Triple &Triple,
9061 const TargetOptions &Opts)
9062 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(),
9064 Triple.getEnvironmentName()),
9066 IsRenderScriptTarget = true;
9069 void getTargetDefines(const LangOptions &Opts,
9070 MacroBuilder &Builder) const override {
9071 Builder.defineMacro("__RENDERSCRIPT__");
9072 AArch64leTargetInfo::getTargetDefines(Opts, Builder);
9076 /// Information about a specific microcontroller.
9079 const char *DefineName;
9082 // This list should be kept up-to-date with AVRDevices.td in LLVM.
9083 static ArrayRef<MCUInfo> AVRMcus = {
9084 { "at90s1200", "__AVR_AT90S1200__" },
9085 { "attiny11", "__AVR_ATtiny11__" },
9086 { "attiny12", "__AVR_ATtiny12__" },
9087 { "attiny15", "__AVR_ATtiny15__" },
9088 { "attiny28", "__AVR_ATtiny28__" },
9089 { "at90s2313", "__AVR_AT90S2313__" },
9090 { "at90s2323", "__AVR_AT90S2323__" },
9091 { "at90s2333", "__AVR_AT90S2333__" },
9092 { "at90s2343", "__AVR_AT90S2343__" },
9093 { "attiny22", "__AVR_ATtiny22__" },
9094 { "attiny26", "__AVR_ATtiny26__" },
9095 { "at86rf401", "__AVR_AT86RF401__" },
9096 { "at90s4414", "__AVR_AT90S4414__" },
9097 { "at90s4433", "__AVR_AT90S4433__" },
9098 { "at90s4434", "__AVR_AT90S4434__" },
9099 { "at90s8515", "__AVR_AT90S8515__" },
9100 { "at90c8534", "__AVR_AT90c8534__" },
9101 { "at90s8535", "__AVR_AT90S8535__" },
9102 { "ata5272", "__AVR_ATA5272__" },
9103 { "attiny13", "__AVR_ATtiny13__" },
9104 { "attiny13a", "__AVR_ATtiny13A__" },
9105 { "attiny2313", "__AVR_ATtiny2313__" },
9106 { "attiny2313a", "__AVR_ATtiny2313A__" },
9107 { "attiny24", "__AVR_ATtiny24__" },
9108 { "attiny24a", "__AVR_ATtiny24A__" },
9109 { "attiny4313", "__AVR_ATtiny4313__" },
9110 { "attiny44", "__AVR_ATtiny44__" },
9111 { "attiny44a", "__AVR_ATtiny44A__" },
9112 { "attiny84", "__AVR_ATtiny84__" },
9113 { "attiny84a", "__AVR_ATtiny84A__" },
9114 { "attiny25", "__AVR_ATtiny25__" },
9115 { "attiny45", "__AVR_ATtiny45__" },
9116 { "attiny85", "__AVR_ATtiny85__" },
9117 { "attiny261", "__AVR_ATtiny261__" },
9118 { "attiny261a", "__AVR_ATtiny261A__" },
9119 { "attiny461", "__AVR_ATtiny461__" },
9120 { "attiny461a", "__AVR_ATtiny461A__" },
9121 { "attiny861", "__AVR_ATtiny861__" },
9122 { "attiny861a", "__AVR_ATtiny861A__" },
9123 { "attiny87", "__AVR_ATtiny87__" },
9124 { "attiny43u", "__AVR_ATtiny43U__" },
9125 { "attiny48", "__AVR_ATtiny48__" },
9126 { "attiny88", "__AVR_ATtiny88__" },
9127 { "attiny828", "__AVR_ATtiny828__" },
9128 { "at43usb355", "__AVR_AT43USB355__" },
9129 { "at76c711", "__AVR_AT76C711__" },
9130 { "atmega103", "__AVR_ATmega103__" },
9131 { "at43usb320", "__AVR_AT43USB320__" },
9132 { "attiny167", "__AVR_ATtiny167__" },
9133 { "at90usb82", "__AVR_AT90USB82__" },
9134 { "at90usb162", "__AVR_AT90USB162__" },
9135 { "ata5505", "__AVR_ATA5505__" },
9136 { "atmega8u2", "__AVR_ATmega8U2__" },
9137 { "atmega16u2", "__AVR_ATmega16U2__" },
9138 { "atmega32u2", "__AVR_ATmega32U2__" },
9139 { "attiny1634", "__AVR_ATtiny1634__" },
9140 { "atmega8", "__AVR_ATmega8__" },
9141 { "ata6289", "__AVR_ATA6289__" },
9142 { "atmega8a", "__AVR_ATmega8A__" },
9143 { "ata6285", "__AVR_ATA6285__" },
9144 { "ata6286", "__AVR_ATA6286__" },
9145 { "atmega48", "__AVR_ATmega48__" },
9146 { "atmega48a", "__AVR_ATmega48A__" },
9147 { "atmega48pa", "__AVR_ATmega48PA__" },
9148 { "atmega48p", "__AVR_ATmega48P__" },
9149 { "atmega88", "__AVR_ATmega88__" },
9150 { "atmega88a", "__AVR_ATmega88A__" },
9151 { "atmega88p", "__AVR_ATmega88P__" },
9152 { "atmega88pa", "__AVR_ATmega88PA__" },
9153 { "atmega8515", "__AVR_ATmega8515__" },
9154 { "atmega8535", "__AVR_ATmega8535__" },
9155 { "atmega8hva", "__AVR_ATmega8HVA__" },
9156 { "at90pwm1", "__AVR_AT90PWM1__" },
9157 { "at90pwm2", "__AVR_AT90PWM2__" },
9158 { "at90pwm2b", "__AVR_AT90PWM2B__" },
9159 { "at90pwm3", "__AVR_AT90PWM3__" },
9160 { "at90pwm3b", "__AVR_AT90PWM3B__" },
9161 { "at90pwm81", "__AVR_AT90PWM81__" },
9162 { "ata5790", "__AVR_ATA5790__" },
9163 { "ata5795", "__AVR_ATA5795__" },
9164 { "atmega16", "__AVR_ATmega16__" },
9165 { "atmega16a", "__AVR_ATmega16A__" },
9166 { "atmega161", "__AVR_ATmega161__" },
9167 { "atmega162", "__AVR_ATmega162__" },
9168 { "atmega163", "__AVR_ATmega163__" },
9169 { "atmega164a", "__AVR_ATmega164A__" },
9170 { "atmega164p", "__AVR_ATmega164P__" },
9171 { "atmega164pa", "__AVR_ATmega164PA__" },
9172 { "atmega165", "__AVR_ATmega165__" },
9173 { "atmega165a", "__AVR_ATmega165A__" },
9174 { "atmega165p", "__AVR_ATmega165P__" },
9175 { "atmega165pa", "__AVR_ATmega165PA__" },
9176 { "atmega168", "__AVR_ATmega168__" },
9177 { "atmega168a", "__AVR_ATmega168A__" },
9178 { "atmega168p", "__AVR_ATmega168P__" },
9179 { "atmega168pa", "__AVR_ATmega168PA__" },
9180 { "atmega169", "__AVR_ATmega169__" },
9181 { "atmega169a", "__AVR_ATmega169A__" },
9182 { "atmega169p", "__AVR_ATmega169P__" },
9183 { "atmega169pa", "__AVR_ATmega169PA__" },
9184 { "atmega32", "__AVR_ATmega32__" },
9185 { "atmega32a", "__AVR_ATmega32A__" },
9186 { "atmega323", "__AVR_ATmega323__" },
9187 { "atmega324a", "__AVR_ATmega324A__" },
9188 { "atmega324p", "__AVR_ATmega324P__" },
9189 { "atmega324pa", "__AVR_ATmega324PA__" },
9190 { "atmega325", "__AVR_ATmega325__" },
9191 { "atmega325a", "__AVR_ATmega325A__" },
9192 { "atmega325p", "__AVR_ATmega325P__" },
9193 { "atmega325pa", "__AVR_ATmega325PA__" },
9194 { "atmega3250", "__AVR_ATmega3250__" },
9195 { "atmega3250a", "__AVR_ATmega3250A__" },
9196 { "atmega3250p", "__AVR_ATmega3250P__" },
9197 { "atmega3250pa", "__AVR_ATmega3250PA__" },
9198 { "atmega328", "__AVR_ATmega328__" },
9199 { "atmega328p", "__AVR_ATmega328P__" },
9200 { "atmega329", "__AVR_ATmega329__" },
9201 { "atmega329a", "__AVR_ATmega329A__" },
9202 { "atmega329p", "__AVR_ATmega329P__" },
9203 { "atmega329pa", "__AVR_ATmega329PA__" },
9204 { "atmega3290", "__AVR_ATmega3290__" },
9205 { "atmega3290a", "__AVR_ATmega3290A__" },
9206 { "atmega3290p", "__AVR_ATmega3290P__" },
9207 { "atmega3290pa", "__AVR_ATmega3290PA__" },
9208 { "atmega406", "__AVR_ATmega406__" },
9209 { "atmega64", "__AVR_ATmega64__" },
9210 { "atmega64a", "__AVR_ATmega64A__" },
9211 { "atmega640", "__AVR_ATmega640__" },
9212 { "atmega644", "__AVR_ATmega644__" },
9213 { "atmega644a", "__AVR_ATmega644A__" },
9214 { "atmega644p", "__AVR_ATmega644P__" },
9215 { "atmega644pa", "__AVR_ATmega644PA__" },
9216 { "atmega645", "__AVR_ATmega645__" },
9217 { "atmega645a", "__AVR_ATmega645A__" },
9218 { "atmega645p", "__AVR_ATmega645P__" },
9219 { "atmega649", "__AVR_ATmega649__" },
9220 { "atmega649a", "__AVR_ATmega649A__" },
9221 { "atmega649p", "__AVR_ATmega649P__" },
9222 { "atmega6450", "__AVR_ATmega6450__" },
9223 { "atmega6450a", "__AVR_ATmega6450A__" },
9224 { "atmega6450p", "__AVR_ATmega6450P__" },
9225 { "atmega6490", "__AVR_ATmega6490__" },
9226 { "atmega6490a", "__AVR_ATmega6490A__" },
9227 { "atmega6490p", "__AVR_ATmega6490P__" },
9228 { "atmega64rfr2", "__AVR_ATmega64RFR2__" },
9229 { "atmega644rfr2", "__AVR_ATmega644RFR2__" },
9230 { "atmega16hva", "__AVR_ATmega16HVA__" },
9231 { "atmega16hva2", "__AVR_ATmega16HVA2__" },
9232 { "atmega16hvb", "__AVR_ATmega16HVB__" },
9233 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" },
9234 { "atmega32hvb", "__AVR_ATmega32HVB__" },
9235 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" },
9236 { "atmega64hve", "__AVR_ATmega64HVE__" },
9237 { "at90can32", "__AVR_AT90CAN32__" },
9238 { "at90can64", "__AVR_AT90CAN64__" },
9239 { "at90pwm161", "__AVR_AT90PWM161__" },
9240 { "at90pwm216", "__AVR_AT90PWM216__" },
9241 { "at90pwm316", "__AVR_AT90PWM316__" },
9242 { "atmega32c1", "__AVR_ATmega32C1__" },
9243 { "atmega64c1", "__AVR_ATmega64C1__" },
9244 { "atmega16m1", "__AVR_ATmega16M1__" },
9245 { "atmega32m1", "__AVR_ATmega32M1__" },
9246 { "atmega64m1", "__AVR_ATmega64M1__" },
9247 { "atmega16u4", "__AVR_ATmega16U4__" },
9248 { "atmega32u4", "__AVR_ATmega32U4__" },
9249 { "atmega32u6", "__AVR_ATmega32U6__" },
9250 { "at90usb646", "__AVR_AT90USB646__" },
9251 { "at90usb647", "__AVR_AT90USB647__" },
9252 { "at90scr100", "__AVR_AT90SCR100__" },
9253 { "at94k", "__AVR_AT94K__" },
9254 { "m3000", "__AVR_AT000__" },
9255 { "atmega128", "__AVR_ATmega128__" },
9256 { "atmega128a", "__AVR_ATmega128A__" },
9257 { "atmega1280", "__AVR_ATmega1280__" },
9258 { "atmega1281", "__AVR_ATmega1281__" },
9259 { "atmega1284", "__AVR_ATmega1284__" },
9260 { "atmega1284p", "__AVR_ATmega1284P__" },
9261 { "atmega128rfa1", "__AVR_ATmega128RFA1__" },
9262 { "atmega128rfr2", "__AVR_ATmega128RFR2__" },
9263 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" },
9264 { "at90can128", "__AVR_AT90CAN128__" },
9265 { "at90usb1286", "__AVR_AT90USB1286__" },
9266 { "at90usb1287", "__AVR_AT90USB1287__" },
9267 { "atmega2560", "__AVR_ATmega2560__" },
9268 { "atmega2561", "__AVR_ATmega2561__" },
9269 { "atmega256rfr2", "__AVR_ATmega256RFR2__" },
9270 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" },
9271 { "atxmega16a4", "__AVR_ATxmega16A4__" },
9272 { "atxmega16a4u", "__AVR_ATxmega16a4U__" },
9273 { "atxmega16c4", "__AVR_ATxmega16C4__" },
9274 { "atxmega16d4", "__AVR_ATxmega16D4__" },
9275 { "atxmega32a4", "__AVR_ATxmega32A4__" },
9276 { "atxmega32a4u", "__AVR_ATxmega32A4U__" },
9277 { "atxmega32c4", "__AVR_ATxmega32C4__" },
9278 { "atxmega32d4", "__AVR_ATxmega32D4__" },
9279 { "atxmega32e5", "__AVR_ATxmega32E5__" },
9280 { "atxmega16e5", "__AVR_ATxmega16E5__" },
9281 { "atxmega8e5", "__AVR_ATxmega8E5__" },
9282 { "atxmega32x1", "__AVR_ATxmega32X1__" },
9283 { "atxmega64a3", "__AVR_ATxmega64A3__" },
9284 { "atxmega64a3u", "__AVR_ATxmega64A3U__" },
9285 { "atxmega64a4u", "__AVR_ATxmega64A4U__" },
9286 { "atxmega64b1", "__AVR_ATxmega64B1__" },
9287 { "atxmega64b3", "__AVR_ATxmega64B3__" },
9288 { "atxmega64c3", "__AVR_ATxmega64C3__" },
9289 { "atxmega64d3", "__AVR_ATxmega64D3__" },
9290 { "atxmega64d4", "__AVR_ATxmega64D4__" },
9291 { "atxmega64a1", "__AVR_ATxmega64A1__" },
9292 { "atxmega64a1u", "__AVR_ATxmega64A1U__" },
9293 { "atxmega128a3", "__AVR_ATxmega128A3__" },
9294 { "atxmega128a3u", "__AVR_ATxmega128A3U__" },
9295 { "atxmega128b1", "__AVR_ATxmega128B1__" },
9296 { "atxmega128b3", "__AVR_ATxmega128B3__" },
9297 { "atxmega128c3", "__AVR_ATxmega128C3__" },
9298 { "atxmega128d3", "__AVR_ATxmega128D3__" },
9299 { "atxmega128d4", "__AVR_ATxmega128D4__" },
9300 { "atxmega192a3", "__AVR_ATxmega192A3__" },
9301 { "atxmega192a3u", "__AVR_ATxmega192A3U__" },
9302 { "atxmega192c3", "__AVR_ATxmega192C3__" },
9303 { "atxmega192d3", "__AVR_ATxmega192D3__" },
9304 { "atxmega256a3", "__AVR_ATxmega256A3__" },
9305 { "atxmega256a3u", "__AVR_ATxmega256A3U__" },
9306 { "atxmega256a3b", "__AVR_ATxmega256A3B__" },
9307 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" },
9308 { "atxmega256c3", "__AVR_ATxmega256C3__" },
9309 { "atxmega256d3", "__AVR_ATxmega256D3__" },
9310 { "atxmega384c3", "__AVR_ATxmega384C3__" },
9311 { "atxmega384d3", "__AVR_ATxmega384D3__" },
9312 { "atxmega128a1", "__AVR_ATxmega128A1__" },
9313 { "atxmega128a1u", "__AVR_ATxmega128A1U__" },
9314 { "atxmega128a4u", "__AVR_ATxmega128a4U__" },
9315 { "attiny4", "__AVR_ATtiny4__" },
9316 { "attiny5", "__AVR_ATtiny5__" },
9317 { "attiny9", "__AVR_ATtiny9__" },
9318 { "attiny10", "__AVR_ATtiny10__" },
9319 { "attiny20", "__AVR_ATtiny20__" },
9320 { "attiny40", "__AVR_ATtiny40__" },
9321 { "attiny102", "__AVR_ATtiny102__" },
9322 { "attiny104", "__AVR_ATtiny104__" },
9326 class AVRTargetInfo : public TargetInfo {
9328 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
9329 : TargetInfo(Triple) {
9330 TLSSupported = false;
9340 DefaultAlignForAttributeAligned = 8;
9347 DoubleFormat = &llvm::APFloat::IEEEsingle();
9348 LongDoubleWidth = 32;
9349 LongDoubleAlign = 8;
9350 LongDoubleFormat = &llvm::APFloat::IEEEsingle();
9351 SizeType = UnsignedInt;
9352 PtrDiffType = SignedInt;
9353 IntPtrType = SignedInt;
9354 Char16Type = UnsignedInt;
9355 WCharType = SignedInt;
9356 WIntType = SignedInt;
9357 Char32Type = UnsignedLong;
9358 SigAtomicType = SignedChar;
9359 resetDataLayout("e-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8");
9362 void getTargetDefines(const LangOptions &Opts,
9363 MacroBuilder &Builder) const override {
9364 Builder.defineMacro("AVR");
9365 Builder.defineMacro("__AVR");
9366 Builder.defineMacro("__AVR__");
9368 if (!this->CPU.empty()) {
9369 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(),
9370 [&](const MCUInfo &Info) { return Info.Name == this->CPU; });
9372 if (It != AVRMcus.end())
9373 Builder.defineMacro(It->DefineName);
9377 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
9381 BuiltinVaListKind getBuiltinVaListKind() const override {
9382 return TargetInfo::VoidPtrBuiltinVaList;
9385 const char *getClobbers() const override {
9389 ArrayRef<const char *> getGCCRegNames() const override {
9390 static const char * const GCCRegNames[] = {
9391 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
9392 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
9393 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
9394 "r24", "r25", "X", "Y", "Z", "SP"
9396 return llvm::makeArrayRef(GCCRegNames);
9399 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
9403 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
9404 static const TargetInfo::AddlRegName AddlRegNames[] = {
9405 { { "r26", "r27"}, 26 },
9406 { { "r28", "r29"}, 27 },
9407 { { "r30", "r31"}, 28 },
9408 { { "SPL", "SPH"}, 29 },
9410 return llvm::makeArrayRef(AddlRegNames);
9413 bool validateAsmConstraint(const char *&Name,
9414 TargetInfo::ConstraintInfo &Info) const override {
9415 // There aren't any multi-character AVR specific constraints.
9416 if (StringRef(Name).size() > 1) return false;
9419 default: return false;
9420 case 'a': // Simple upper registers
9421 case 'b': // Base pointer registers pairs
9422 case 'd': // Upper register
9423 case 'l': // Lower registers
9424 case 'e': // Pointer register pairs
9425 case 'q': // Stack pointer register
9426 case 'r': // Any register
9427 case 'w': // Special upper register pairs
9428 case 't': // Temporary register
9429 case 'x': case 'X': // Pointer register pair X
9430 case 'y': case 'Y': // Pointer register pair Y
9431 case 'z': case 'Z': // Pointer register pair Z
9432 Info.setAllowsRegister();
9434 case 'I': // 6-bit positive integer constant
9435 Info.setRequiresImmediate(0, 63);
9437 case 'J': // 6-bit negative integer constant
9438 Info.setRequiresImmediate(-63, 0);
9440 case 'K': // Integer constant (Range: 2)
9441 Info.setRequiresImmediate(2);
9443 case 'L': // Integer constant (Range: 0)
9444 Info.setRequiresImmediate(0);
9446 case 'M': // 8-bit integer constant
9447 Info.setRequiresImmediate(0, 0xff);
9449 case 'N': // Integer constant (Range: -1)
9450 Info.setRequiresImmediate(-1);
9452 case 'O': // Integer constant (Range: 8, 16, 24)
9453 Info.setRequiresImmediate({8, 16, 24});
9455 case 'P': // Integer constant (Range: 1)
9456 Info.setRequiresImmediate(1);
9458 case 'R': // Integer constant (Range: -6 to 5)
9459 Info.setRequiresImmediate(-6, 5);
9461 case 'G': // Floating point constant
9462 case 'Q': // A memory address based on Y or Z pointer with displacement.
9469 IntType getIntTypeByWidth(unsigned BitWidth,
9470 bool IsSigned) const final {
9471 // AVR prefers int for 16-bit integers.
9472 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt)
9473 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
9476 IntType getLeastIntTypeByWidth(unsigned BitWidth,
9477 bool IsSigned) const final {
9478 // AVR uses int for int_least16_t and int_fast16_t.
9479 return BitWidth == 16
9480 ? (IsSigned ? SignedInt : UnsignedInt)
9481 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
9484 bool setCPU(const std::string &Name) override {
9485 bool IsFamily = llvm::StringSwitch<bool>(Name)
9488 .Case("avr25", true)
9490 .Case("avr31", true)
9491 .Case("avr35", true)
9494 .Case("avr51", true)
9496 .Case("avrxmega1", true)
9497 .Case("avrxmega2", true)
9498 .Case("avrxmega3", true)
9499 .Case("avrxmega4", true)
9500 .Case("avrxmega5", true)
9501 .Case("avrxmega6", true)
9502 .Case("avrxmega7", true)
9503 .Case("avrtiny", true)
9506 if (IsFamily) this->CPU = Name;
9508 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(),
9509 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end();
9511 if (IsMCU) this->CPU = Name;
9513 return IsFamily || IsMCU;
9520 } // end anonymous namespace
9522 //===----------------------------------------------------------------------===//
9524 //===----------------------------------------------------------------------===//
9526 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
9527 const TargetOptions &Opts) {
9528 llvm::Triple::OSType os = Triple.getOS();
9530 switch (Triple.getArch()) {
9534 case llvm::Triple::xcore:
9535 return new XCoreTargetInfo(Triple, Opts);
9537 case llvm::Triple::hexagon:
9538 return new HexagonTargetInfo(Triple, Opts);
9540 case llvm::Triple::lanai:
9541 return new LanaiTargetInfo(Triple, Opts);
9543 case llvm::Triple::aarch64:
9544 if (Triple.isOSDarwin())
9545 return new DarwinAArch64TargetInfo(Triple, Opts);
9548 case llvm::Triple::CloudABI:
9549 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts);
9550 case llvm::Triple::FreeBSD:
9551 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9552 case llvm::Triple::Fuchsia:
9553 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9554 case llvm::Triple::Linux:
9555 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9556 case llvm::Triple::NetBSD:
9557 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9558 case llvm::Triple::OpenBSD:
9559 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9560 case llvm::Triple::Win32:
9561 return new MicrosoftARM64TargetInfo(Triple, Opts);
9563 return new AArch64leTargetInfo(Triple, Opts);
9566 case llvm::Triple::aarch64_be:
9568 case llvm::Triple::FreeBSD:
9569 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9570 case llvm::Triple::Fuchsia:
9571 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9572 case llvm::Triple::Linux:
9573 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9574 case llvm::Triple::NetBSD:
9575 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9577 return new AArch64beTargetInfo(Triple, Opts);
9580 case llvm::Triple::arm:
9581 case llvm::Triple::thumb:
9582 if (Triple.isOSBinFormatMachO())
9583 return new DarwinARMTargetInfo(Triple, Opts);
9586 case llvm::Triple::CloudABI:
9587 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts);
9588 case llvm::Triple::Linux:
9589 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts);
9590 case llvm::Triple::FreeBSD:
9591 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
9592 case llvm::Triple::NetBSD:
9593 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
9594 case llvm::Triple::OpenBSD:
9595 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
9596 case llvm::Triple::Bitrig:
9597 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts);
9598 case llvm::Triple::RTEMS:
9599 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts);
9600 case llvm::Triple::NaCl:
9601 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts);
9602 case llvm::Triple::Win32:
9603 switch (Triple.getEnvironment()) {
9604 case llvm::Triple::Cygnus:
9605 return new CygwinARMTargetInfo(Triple, Opts);
9606 case llvm::Triple::GNU:
9607 return new MinGWARMTargetInfo(Triple, Opts);
9608 case llvm::Triple::Itanium:
9609 return new ItaniumWindowsARMleTargetInfo(Triple, Opts);
9610 case llvm::Triple::MSVC:
9611 default: // Assume MSVC for unknown environments
9612 return new MicrosoftARMleTargetInfo(Triple, Opts);
9615 return new ARMleTargetInfo(Triple, Opts);
9618 case llvm::Triple::armeb:
9619 case llvm::Triple::thumbeb:
9620 if (Triple.isOSDarwin())
9621 return new DarwinARMTargetInfo(Triple, Opts);
9624 case llvm::Triple::Linux:
9625 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9626 case llvm::Triple::FreeBSD:
9627 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9628 case llvm::Triple::NetBSD:
9629 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9630 case llvm::Triple::OpenBSD:
9631 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9632 case llvm::Triple::Bitrig:
9633 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9634 case llvm::Triple::RTEMS:
9635 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9636 case llvm::Triple::NaCl:
9637 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9639 return new ARMbeTargetInfo(Triple, Opts);
9642 case llvm::Triple::avr:
9643 return new AVRTargetInfo(Triple, Opts);
9644 case llvm::Triple::bpfeb:
9645 case llvm::Triple::bpfel:
9646 return new BPFTargetInfo(Triple, Opts);
9648 case llvm::Triple::msp430:
9649 return new MSP430TargetInfo(Triple, Opts);
9651 case llvm::Triple::nios2:
9652 return new LinuxTargetInfo<Nios2TargetInfo>(Triple, Opts);
9654 case llvm::Triple::mips:
9656 case llvm::Triple::Linux:
9657 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9658 case llvm::Triple::RTEMS:
9659 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9660 case llvm::Triple::FreeBSD:
9661 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9662 case llvm::Triple::NetBSD:
9663 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9665 return new MipsTargetInfo(Triple, Opts);
9668 case llvm::Triple::mipsel:
9670 case llvm::Triple::Linux:
9671 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9672 case llvm::Triple::RTEMS:
9673 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9674 case llvm::Triple::FreeBSD:
9675 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9676 case llvm::Triple::NetBSD:
9677 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9678 case llvm::Triple::NaCl:
9679 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts);
9681 return new MipsTargetInfo(Triple, Opts);
9684 case llvm::Triple::mips64:
9686 case llvm::Triple::Linux:
9687 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9688 case llvm::Triple::RTEMS:
9689 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9690 case llvm::Triple::FreeBSD:
9691 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9692 case llvm::Triple::NetBSD:
9693 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9694 case llvm::Triple::OpenBSD:
9695 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9697 return new MipsTargetInfo(Triple, Opts);
9700 case llvm::Triple::mips64el:
9702 case llvm::Triple::Linux:
9703 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9704 case llvm::Triple::RTEMS:
9705 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9706 case llvm::Triple::FreeBSD:
9707 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9708 case llvm::Triple::NetBSD:
9709 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9710 case llvm::Triple::OpenBSD:
9711 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9713 return new MipsTargetInfo(Triple, Opts);
9716 case llvm::Triple::le32:
9718 case llvm::Triple::NaCl:
9719 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts);
9724 case llvm::Triple::le64:
9725 return new Le64TargetInfo(Triple, Opts);
9727 case llvm::Triple::ppc:
9728 if (Triple.isOSDarwin())
9729 return new DarwinPPC32TargetInfo(Triple, Opts);
9731 case llvm::Triple::Linux:
9732 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts);
9733 case llvm::Triple::FreeBSD:
9734 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
9735 case llvm::Triple::NetBSD:
9736 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
9737 case llvm::Triple::OpenBSD:
9738 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
9739 case llvm::Triple::RTEMS:
9740 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts);
9742 return new PPC32TargetInfo(Triple, Opts);
9745 case llvm::Triple::ppc64:
9746 if (Triple.isOSDarwin())
9747 return new DarwinPPC64TargetInfo(Triple, Opts);
9749 case llvm::Triple::Linux:
9750 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
9751 case llvm::Triple::Lv2:
9752 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts);
9753 case llvm::Triple::FreeBSD:
9754 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
9755 case llvm::Triple::NetBSD:
9756 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
9758 return new PPC64TargetInfo(Triple, Opts);
9761 case llvm::Triple::ppc64le:
9763 case llvm::Triple::Linux:
9764 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
9765 case llvm::Triple::NetBSD:
9766 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
9768 return new PPC64TargetInfo(Triple, Opts);
9771 case llvm::Triple::nvptx:
9772 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32);
9773 case llvm::Triple::nvptx64:
9774 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64);
9776 case llvm::Triple::amdgcn:
9777 case llvm::Triple::r600:
9778 return new AMDGPUTargetInfo(Triple, Opts);
9780 case llvm::Triple::sparc:
9782 case llvm::Triple::Linux:
9783 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9784 case llvm::Triple::Solaris:
9785 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9786 case llvm::Triple::NetBSD:
9787 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9788 case llvm::Triple::OpenBSD:
9789 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9790 case llvm::Triple::RTEMS:
9791 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9793 return new SparcV8TargetInfo(Triple, Opts);
9796 // The 'sparcel' architecture copies all the above cases except for Solaris.
9797 case llvm::Triple::sparcel:
9799 case llvm::Triple::Linux:
9800 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9801 case llvm::Triple::NetBSD:
9802 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9803 case llvm::Triple::OpenBSD:
9804 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9805 case llvm::Triple::RTEMS:
9806 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9808 return new SparcV8elTargetInfo(Triple, Opts);
9811 case llvm::Triple::sparcv9:
9813 case llvm::Triple::Linux:
9814 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9815 case llvm::Triple::Solaris:
9816 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9817 case llvm::Triple::NetBSD:
9818 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9819 case llvm::Triple::OpenBSD:
9820 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9821 case llvm::Triple::FreeBSD:
9822 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9824 return new SparcV9TargetInfo(Triple, Opts);
9827 case llvm::Triple::systemz:
9829 case llvm::Triple::Linux:
9830 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts);
9832 return new SystemZTargetInfo(Triple, Opts);
9835 case llvm::Triple::tce:
9836 return new TCETargetInfo(Triple, Opts);
9838 case llvm::Triple::tcele:
9839 return new TCELETargetInfo(Triple, Opts);
9841 case llvm::Triple::x86:
9842 if (Triple.isOSDarwin())
9843 return new DarwinI386TargetInfo(Triple, Opts);
9846 case llvm::Triple::Ananas:
9847 return new AnanasTargetInfo<X86_32TargetInfo>(Triple, Opts);
9848 case llvm::Triple::CloudABI:
9849 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts);
9850 case llvm::Triple::Linux: {
9851 switch (Triple.getEnvironment()) {
9853 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts);
9854 case llvm::Triple::Android:
9855 return new AndroidX86_32TargetInfo(Triple, Opts);
9858 case llvm::Triple::DragonFly:
9859 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
9860 case llvm::Triple::NetBSD:
9861 return new NetBSDI386TargetInfo(Triple, Opts);
9862 case llvm::Triple::OpenBSD:
9863 return new OpenBSDI386TargetInfo(Triple, Opts);
9864 case llvm::Triple::Bitrig:
9865 return new BitrigI386TargetInfo(Triple, Opts);
9866 case llvm::Triple::FreeBSD:
9867 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
9868 case llvm::Triple::KFreeBSD:
9869 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
9870 case llvm::Triple::Minix:
9871 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts);
9872 case llvm::Triple::Solaris:
9873 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts);
9874 case llvm::Triple::Win32: {
9875 switch (Triple.getEnvironment()) {
9876 case llvm::Triple::Cygnus:
9877 return new CygwinX86_32TargetInfo(Triple, Opts);
9878 case llvm::Triple::GNU:
9879 return new MinGWX86_32TargetInfo(Triple, Opts);
9880 case llvm::Triple::Itanium:
9881 case llvm::Triple::MSVC:
9882 default: // Assume MSVC for unknown environments
9883 return new MicrosoftX86_32TargetInfo(Triple, Opts);
9886 case llvm::Triple::Haiku:
9887 return new HaikuX86_32TargetInfo(Triple, Opts);
9888 case llvm::Triple::RTEMS:
9889 return new RTEMSX86_32TargetInfo(Triple, Opts);
9890 case llvm::Triple::NaCl:
9891 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts);
9892 case llvm::Triple::ELFIAMCU:
9893 return new MCUX86_32TargetInfo(Triple, Opts);
9895 return new X86_32TargetInfo(Triple, Opts);
9898 case llvm::Triple::x86_64:
9899 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
9900 return new DarwinX86_64TargetInfo(Triple, Opts);
9903 case llvm::Triple::Ananas:
9904 return new AnanasTargetInfo<X86_64TargetInfo>(Triple, Opts);
9905 case llvm::Triple::CloudABI:
9906 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts);
9907 case llvm::Triple::Linux: {
9908 switch (Triple.getEnvironment()) {
9910 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts);
9911 case llvm::Triple::Android:
9912 return new AndroidX86_64TargetInfo(Triple, Opts);
9915 case llvm::Triple::DragonFly:
9916 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9917 case llvm::Triple::NetBSD:
9918 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9919 case llvm::Triple::OpenBSD:
9920 return new OpenBSDX86_64TargetInfo(Triple, Opts);
9921 case llvm::Triple::Bitrig:
9922 return new BitrigX86_64TargetInfo(Triple, Opts);
9923 case llvm::Triple::FreeBSD:
9924 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9925 case llvm::Triple::Fuchsia:
9926 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts);
9927 case llvm::Triple::KFreeBSD:
9928 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9929 case llvm::Triple::Solaris:
9930 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts);
9931 case llvm::Triple::Win32: {
9932 switch (Triple.getEnvironment()) {
9933 case llvm::Triple::Cygnus:
9934 return new CygwinX86_64TargetInfo(Triple, Opts);
9935 case llvm::Triple::GNU:
9936 return new MinGWX86_64TargetInfo(Triple, Opts);
9937 case llvm::Triple::MSVC:
9938 default: // Assume MSVC for unknown environments
9939 return new MicrosoftX86_64TargetInfo(Triple, Opts);
9942 case llvm::Triple::Haiku:
9943 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts);
9944 case llvm::Triple::NaCl:
9945 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts);
9946 case llvm::Triple::PS4:
9947 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts);
9949 return new X86_64TargetInfo(Triple, Opts);
9952 case llvm::Triple::spir: {
9953 if (Triple.getOS() != llvm::Triple::UnknownOS ||
9954 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
9956 return new SPIR32TargetInfo(Triple, Opts);
9958 case llvm::Triple::spir64: {
9959 if (Triple.getOS() != llvm::Triple::UnknownOS ||
9960 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
9962 return new SPIR64TargetInfo(Triple, Opts);
9964 case llvm::Triple::wasm32:
9965 if (Triple.getSubArch() != llvm::Triple::NoSubArch ||
9966 Triple.getVendor() != llvm::Triple::UnknownVendor ||
9967 Triple.getOS() != llvm::Triple::UnknownOS ||
9968 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment ||
9969 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm()))
9971 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts);
9972 case llvm::Triple::wasm64:
9973 if (Triple.getSubArch() != llvm::Triple::NoSubArch ||
9974 Triple.getVendor() != llvm::Triple::UnknownVendor ||
9975 Triple.getOS() != llvm::Triple::UnknownOS ||
9976 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment ||
9977 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm()))
9979 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts);
9981 case llvm::Triple::renderscript32:
9982 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts);
9983 case llvm::Triple::renderscript64:
9984 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts);
9988 /// CreateTargetInfo - Return the target info object for the specified target
9991 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
9992 const std::shared_ptr<TargetOptions> &Opts) {
9993 llvm::Triple Triple(Opts->Triple);
9995 // Construct the target
9996 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts));
9998 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
10001 Target->TargetOpts = Opts;
10003 // Set the target CPU if specified.
10004 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
10005 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
10009 // Set the target ABI if specified.
10010 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
10011 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
10015 // Set the fp math unit.
10016 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
10017 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
10021 // Compute the default target features, we need the target to handle this
10022 // because features may have dependencies on one another.
10023 llvm::StringMap<bool> Features;
10024 if (!Target->initFeatureMap(Features, Diags, Opts->CPU,
10025 Opts->FeaturesAsWritten))
10028 // Add the features to the compile options.
10029 Opts->Features.clear();
10030 for (const auto &F : Features)
10031 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str());
10033 if (!Target->handleTargetFeatures(Opts->Features, Diags))
10036 Target->setSupportedOpenCLOpts();
10037 Target->setOpenCLExtensionOpts();
10039 if (!Target->validateTarget(Diags))
10042 return Target.release();