1 //===--- Targets.cpp - Implement target feature support -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/Builtins.h"
16 #include "clang/Basic/Cuda.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetInfo.h"
22 #include "clang/Basic/TargetOptions.h"
23 #include "clang/Basic/Version.h"
24 #include "clang/Frontend/CodeGenOptions.h"
25 #include "llvm/ADT/APFloat.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/StringSwitch.h"
30 #include "llvm/ADT/Triple.h"
31 #include "llvm/MC/MCSectionMachO.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/TargetParser.h"
37 using namespace clang;
39 //===----------------------------------------------------------------------===//
40 // Common code shared among targets.
41 //===----------------------------------------------------------------------===//
43 /// DefineStd - Define a macro name and standard variants. For example if
44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
47 const LangOptions &Opts) {
48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
51 // in the user's namespace.
53 Builder.defineMacro(MacroName);
56 Builder.defineMacro("__" + MacroName);
59 Builder.defineMacro("__" + MacroName + "__");
62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
64 Builder.defineMacro("__" + CPUName);
65 Builder.defineMacro("__" + CPUName + "__");
67 Builder.defineMacro("__tune_" + CPUName + "__");
70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
71 const TargetOptions &Opts);
73 //===----------------------------------------------------------------------===//
74 // Defines specific to certain operating systems.
75 //===----------------------------------------------------------------------===//
78 template<typename TgtInfo>
79 class OSTargetInfo : public TgtInfo {
81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
82 MacroBuilder &Builder) const=0;
84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
85 : TgtInfo(Triple, Opts) {}
86 void getTargetDefines(const LangOptions &Opts,
87 MacroBuilder &Builder) const override {
88 TgtInfo::getTargetDefines(Opts, Builder);
89 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
95 template <typename Target>
96 class CloudABITargetInfo : public OSTargetInfo<Target> {
98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
99 MacroBuilder &Builder) const override {
100 Builder.defineMacro("__CloudABI__");
101 Builder.defineMacro("__ELF__");
103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
104 Builder.defineMacro("__STDC_ISO_10646__", "201206L");
105 Builder.defineMacro("__STDC_UTF_16__");
106 Builder.defineMacro("__STDC_UTF_32__");
110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
111 : OSTargetInfo<Target>(Triple, Opts) {}
114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
115 const llvm::Triple &Triple,
116 StringRef &PlatformName,
117 VersionTuple &PlatformMinVersion) {
118 Builder.defineMacro("__APPLE_CC__", "6000");
119 Builder.defineMacro("__APPLE__");
120 Builder.defineMacro("OBJC_NEW_PROPERTIES");
121 // AddressSanitizer doesn't play well with source fortification, which is on
122 // by default on Darwin.
123 if (Opts.Sanitize.has(SanitizerKind::Address))
124 Builder.defineMacro("_FORTIFY_SOURCE", "0");
126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode.
128 // __weak is always defined, for use in blocks and with objc pointers.
129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
130 Builder.defineMacro("__strong", "");
131 Builder.defineMacro("__unsafe_unretained", "");
135 Builder.defineMacro("__STATIC__");
137 Builder.defineMacro("__DYNAMIC__");
139 if (Opts.POSIXThreads)
140 Builder.defineMacro("_REENTRANT");
142 // Get the platform type and version number from the triple.
143 unsigned Maj, Min, Rev;
144 if (Triple.isMacOSX()) {
145 Triple.getMacOSXVersion(Maj, Min, Rev);
146 PlatformName = "macos";
148 Triple.getOSVersion(Maj, Min, Rev);
149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
152 // If -target arch-pc-win32-macho option specified, we're
153 // generating code for Win32 ABI. No need to emit
154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
155 if (PlatformName == "win32") {
156 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
160 // Set the appropriate OS version define.
161 if (Triple.isiOS()) {
162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
166 Str[1] = '0' + (Min / 10);
167 Str[2] = '0' + (Min % 10);
168 Str[3] = '0' + (Rev / 10);
169 Str[4] = '0' + (Rev % 10);
172 // Handle versions >= 10.
173 Str[0] = '0' + (Maj / 10);
174 Str[1] = '0' + (Maj % 10);
175 Str[2] = '0' + (Min / 10);
176 Str[3] = '0' + (Min % 10);
177 Str[4] = '0' + (Rev / 10);
178 Str[5] = '0' + (Rev % 10);
182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str);
184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
187 } else if (Triple.isWatchOS()) {
188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
191 Str[1] = '0' + (Min / 10);
192 Str[2] = '0' + (Min % 10);
193 Str[3] = '0' + (Rev / 10);
194 Str[4] = '0' + (Rev % 10);
196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str);
197 } else if (Triple.isMacOSX()) {
198 // Note that the Driver allows versions which aren't representable in the
199 // define (because we only get a single digit for the minor and micro
200 // revision numbers). So, we limit them to the maximum representable
202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
204 if (Maj < 10 || (Maj == 10 && Min < 10)) {
205 Str[0] = '0' + (Maj / 10);
206 Str[1] = '0' + (Maj % 10);
207 Str[2] = '0' + std::min(Min, 9U);
208 Str[3] = '0' + std::min(Rev, 9U);
211 // Handle versions > 10.9.
212 Str[0] = '0' + (Maj / 10);
213 Str[1] = '0' + (Maj % 10);
214 Str[2] = '0' + (Min / 10);
215 Str[3] = '0' + (Min % 10);
216 Str[4] = '0' + (Rev / 10);
217 Str[5] = '0' + (Rev % 10);
220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
223 // Tell users about the kernel if there is one.
224 if (Triple.isOSDarwin())
225 Builder.defineMacro("__MACH__");
227 // The Watch ABI uses Dwarf EH.
228 if(Triple.isWatchABI())
229 Builder.defineMacro("__ARM_DWARF_EH__");
231 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
234 template<typename Target>
235 class DarwinTargetInfo : public OSTargetInfo<Target> {
237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
238 MacroBuilder &Builder) const override {
239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
240 this->PlatformMinVersion);
244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
245 : OSTargetInfo<Target>(Triple, Opts) {
246 // By default, no TLS, and we whitelist permitted architecture/OS
248 this->TLSSupported = false;
250 if (Triple.isMacOSX())
251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7);
252 else if (Triple.isiOS()) {
253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards.
254 if (Triple.getArch() == llvm::Triple::x86_64 ||
255 Triple.getArch() == llvm::Triple::aarch64)
256 this->TLSSupported = !Triple.isOSVersionLT(8);
257 else if (Triple.getArch() == llvm::Triple::x86 ||
258 Triple.getArch() == llvm::Triple::arm ||
259 Triple.getArch() == llvm::Triple::thumb)
260 this->TLSSupported = !Triple.isOSVersionLT(9);
261 } else if (Triple.isWatchOS())
262 this->TLSSupported = !Triple.isOSVersionLT(2);
264 this->MCountName = "\01mcount";
267 std::string isValidSectionSpecifier(StringRef SR) const override {
268 // Let MCSectionMachO validate this.
269 StringRef Segment, Section;
270 unsigned TAA, StubSize;
272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
273 TAA, HasTAA, StubSize);
276 const char *getStaticInitSectionSpecifier() const override {
277 // FIXME: We should return 0 when building kexts.
278 return "__TEXT,__StaticInit,regular,pure_instructions";
281 /// Darwin does not support protected visibility. Darwin's "default"
282 /// is very similar to ELF's "protected"; Darwin requires a "weak"
283 /// attribute on declarations that can be dynamically replaced.
284 bool hasProtectedVisibility() const override {
288 unsigned getExnObjectAlignment() const override {
289 // The alignment of an exception object is 8-bytes for darwin since
290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned))
291 // and therefore doesn't guarantee 16-byte alignment.
297 // DragonFlyBSD Target
298 template<typename Target>
299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
302 MacroBuilder &Builder) const override {
303 // DragonFly defines; list based off of gcc output
304 Builder.defineMacro("__DragonFly__");
305 Builder.defineMacro("__DragonFly_cc_version", "100001");
306 Builder.defineMacro("__ELF__");
307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
308 Builder.defineMacro("__tune_i386__");
309 DefineStd(Builder, "unix", Opts);
312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
313 : OSTargetInfo<Target>(Triple, Opts) {
314 switch (Triple.getArch()) {
316 case llvm::Triple::x86:
317 case llvm::Triple::x86_64:
318 this->MCountName = ".mcount";
324 #ifndef FREEBSD_CC_VERSION
325 #define FREEBSD_CC_VERSION 0U
329 template<typename Target>
330 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
333 MacroBuilder &Builder) const override {
334 // FreeBSD defines; list based off of gcc output
336 unsigned Release = Triple.getOSMajorVersion();
339 unsigned CCVersion = FREEBSD_CC_VERSION;
341 CCVersion = Release * 100000U + 1U;
343 Builder.defineMacro("__FreeBSD__", Twine(Release));
344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion));
345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
346 DefineStd(Builder, "unix", Opts);
347 Builder.defineMacro("__ELF__");
349 // On FreeBSD, wchar_t contains the number of the code point as
350 // used by the character set of the locale. These character sets are
351 // not necessarily a superset of ASCII.
353 // FIXME: This is wrong; the macro refers to the numerical values
354 // of wchar_t *literals*, which are not locale-dependent. However,
355 // FreeBSD systems apparently depend on us getting this wrong, and
356 // setting this to 1 is conforming even if all the basic source
357 // character literals have the same encoding as char and wchar_t.
358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
362 : OSTargetInfo<Target>(Triple, Opts) {
363 switch (Triple.getArch()) {
365 case llvm::Triple::x86:
366 case llvm::Triple::x86_64:
367 this->MCountName = ".mcount";
369 case llvm::Triple::mips:
370 case llvm::Triple::mipsel:
371 case llvm::Triple::ppc:
372 case llvm::Triple::ppc64:
373 case llvm::Triple::ppc64le:
374 this->MCountName = "_mcount";
376 case llvm::Triple::arm:
377 this->MCountName = "__mcount";
383 // GNU/kFreeBSD Target
384 template<typename Target>
385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
388 MacroBuilder &Builder) const override {
389 // GNU/kFreeBSD defines; list based off of gcc output
391 DefineStd(Builder, "unix", Opts);
392 Builder.defineMacro("__FreeBSD_kernel__");
393 Builder.defineMacro("__GLIBC__");
394 Builder.defineMacro("__ELF__");
395 if (Opts.POSIXThreads)
396 Builder.defineMacro("_REENTRANT");
398 Builder.defineMacro("_GNU_SOURCE");
401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
402 : OSTargetInfo<Target>(Triple, Opts) {}
406 template<typename Target>
407 class HaikuTargetInfo : public OSTargetInfo<Target> {
409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
410 MacroBuilder &Builder) const override {
411 // Haiku defines; list based off of gcc output
412 Builder.defineMacro("__HAIKU__");
413 Builder.defineMacro("__ELF__");
414 DefineStd(Builder, "unix", Opts);
417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
418 : OSTargetInfo<Target>(Triple, Opts) {
419 this->SizeType = TargetInfo::UnsignedLong;
420 this->IntPtrType = TargetInfo::SignedLong;
421 this->PtrDiffType = TargetInfo::SignedLong;
422 this->ProcessIDType = TargetInfo::SignedLong;
423 this->TLSSupported = false;
429 template<typename Target>
430 class MinixTargetInfo : public OSTargetInfo<Target> {
432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
433 MacroBuilder &Builder) const override {
436 Builder.defineMacro("__minix", "3");
437 Builder.defineMacro("_EM_WSIZE", "4");
438 Builder.defineMacro("_EM_PSIZE", "4");
439 Builder.defineMacro("_EM_SSIZE", "2");
440 Builder.defineMacro("_EM_LSIZE", "4");
441 Builder.defineMacro("_EM_FSIZE", "4");
442 Builder.defineMacro("_EM_DSIZE", "8");
443 Builder.defineMacro("__ELF__");
444 DefineStd(Builder, "unix", Opts);
447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
448 : OSTargetInfo<Target>(Triple, Opts) {}
452 template<typename Target>
453 class LinuxTargetInfo : public OSTargetInfo<Target> {
455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
456 MacroBuilder &Builder) const override {
457 // Linux defines; list based off of gcc output
458 DefineStd(Builder, "unix", Opts);
459 DefineStd(Builder, "linux", Opts);
460 Builder.defineMacro("__gnu_linux__");
461 Builder.defineMacro("__ELF__");
462 if (Triple.isAndroid()) {
463 Builder.defineMacro("__ANDROID__", "1");
464 unsigned Maj, Min, Rev;
465 Triple.getEnvironmentVersion(Maj, Min, Rev);
466 this->PlatformName = "android";
467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
469 Builder.defineMacro("__ANDROID_API__", Twine(Maj));
471 if (Opts.POSIXThreads)
472 Builder.defineMacro("_REENTRANT");
474 Builder.defineMacro("_GNU_SOURCE");
475 if (this->HasFloat128)
476 Builder.defineMacro("__FLOAT128__");
479 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
480 : OSTargetInfo<Target>(Triple, Opts) {
481 this->WIntType = TargetInfo::UnsignedInt;
483 switch (Triple.getArch()) {
486 case llvm::Triple::ppc:
487 case llvm::Triple::ppc64:
488 case llvm::Triple::ppc64le:
489 this->MCountName = "_mcount";
491 case llvm::Triple::x86:
492 case llvm::Triple::x86_64:
493 case llvm::Triple::systemz:
494 this->HasFloat128 = true;
499 const char *getStaticInitSectionSpecifier() const override {
500 return ".text.startup";
505 template<typename Target>
506 class NetBSDTargetInfo : public OSTargetInfo<Target> {
508 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
509 MacroBuilder &Builder) const override {
510 // NetBSD defines; list based off of gcc output
511 Builder.defineMacro("__NetBSD__");
512 Builder.defineMacro("__unix__");
513 Builder.defineMacro("__ELF__");
514 if (Opts.POSIXThreads)
515 Builder.defineMacro("_REENTRANT");
517 switch (Triple.getArch()) {
520 case llvm::Triple::arm:
521 case llvm::Triple::armeb:
522 case llvm::Triple::thumb:
523 case llvm::Triple::thumbeb:
524 Builder.defineMacro("__ARM_DWARF_EH__");
529 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
530 : OSTargetInfo<Target>(Triple, Opts) {
531 this->MCountName = "_mcount";
536 template<typename Target>
537 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
539 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
540 MacroBuilder &Builder) const override {
541 // OpenBSD defines; list based off of gcc output
543 Builder.defineMacro("__OpenBSD__");
544 DefineStd(Builder, "unix", Opts);
545 Builder.defineMacro("__ELF__");
546 if (Opts.POSIXThreads)
547 Builder.defineMacro("_REENTRANT");
548 if (this->HasFloat128)
549 Builder.defineMacro("__FLOAT128__");
552 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
553 : OSTargetInfo<Target>(Triple, Opts) {
554 this->TLSSupported = false;
556 switch (Triple.getArch()) {
557 case llvm::Triple::x86:
558 case llvm::Triple::x86_64:
559 this->HasFloat128 = true;
562 this->MCountName = "__mcount";
564 case llvm::Triple::mips64:
565 case llvm::Triple::mips64el:
566 case llvm::Triple::ppc:
567 case llvm::Triple::sparcv9:
568 this->MCountName = "_mcount";
575 template<typename Target>
576 class BitrigTargetInfo : public OSTargetInfo<Target> {
578 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
579 MacroBuilder &Builder) const override {
580 // Bitrig defines; list based off of gcc output
582 Builder.defineMacro("__Bitrig__");
583 DefineStd(Builder, "unix", Opts);
584 Builder.defineMacro("__ELF__");
585 if (Opts.POSIXThreads)
586 Builder.defineMacro("_REENTRANT");
588 switch (Triple.getArch()) {
591 case llvm::Triple::arm:
592 case llvm::Triple::armeb:
593 case llvm::Triple::thumb:
594 case llvm::Triple::thumbeb:
595 Builder.defineMacro("__ARM_DWARF_EH__");
600 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
601 : OSTargetInfo<Target>(Triple, Opts) {
602 this->MCountName = "__mcount";
607 template<typename Target>
608 class PSPTargetInfo : public OSTargetInfo<Target> {
610 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
611 MacroBuilder &Builder) const override {
612 // PSP defines; list based on the output of the pspdev gcc toolchain.
613 Builder.defineMacro("PSP");
614 Builder.defineMacro("_PSP");
615 Builder.defineMacro("__psp__");
616 Builder.defineMacro("__ELF__");
619 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {}
623 template<typename Target>
624 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
626 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
627 MacroBuilder &Builder) const override {
629 Builder.defineMacro("__PPC__");
630 Builder.defineMacro("__PPU__");
631 Builder.defineMacro("__CELLOS_LV2__");
632 Builder.defineMacro("__ELF__");
633 Builder.defineMacro("__LP32__");
634 Builder.defineMacro("_ARCH_PPC64");
635 Builder.defineMacro("__powerpc64__");
638 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
639 : OSTargetInfo<Target>(Triple, Opts) {
640 this->LongWidth = this->LongAlign = 32;
641 this->PointerWidth = this->PointerAlign = 32;
642 this->IntMaxType = TargetInfo::SignedLongLong;
643 this->Int64Type = TargetInfo::SignedLongLong;
644 this->SizeType = TargetInfo::UnsignedInt;
645 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64");
649 template <typename Target>
650 class PS4OSTargetInfo : public OSTargetInfo<Target> {
652 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
653 MacroBuilder &Builder) const override {
654 Builder.defineMacro("__FreeBSD__", "9");
655 Builder.defineMacro("__FreeBSD_cc_version", "900001");
656 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
657 DefineStd(Builder, "unix", Opts);
658 Builder.defineMacro("__ELF__");
659 Builder.defineMacro("__ORBIS__");
662 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
663 : OSTargetInfo<Target>(Triple, Opts) {
664 this->WCharType = this->UnsignedShort;
666 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits).
667 this->MaxTLSAlign = 256;
669 // On PS4, do not honor explicit bit field alignment,
670 // as in "__attribute__((aligned(2))) int b : 1;".
671 this->UseExplicitBitFieldAlignment = false;
673 switch (Triple.getArch()) {
675 case llvm::Triple::x86_64:
676 this->MCountName = ".mcount";
683 template<typename Target>
684 class SolarisTargetInfo : public OSTargetInfo<Target> {
686 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
687 MacroBuilder &Builder) const override {
688 DefineStd(Builder, "sun", Opts);
689 DefineStd(Builder, "unix", Opts);
690 Builder.defineMacro("__ELF__");
691 Builder.defineMacro("__svr4__");
692 Builder.defineMacro("__SVR4");
693 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
694 // newer, but to 500 for everything else. feature_test.h has a check to
695 // ensure that you are not using C99 with an old version of X/Open or C89
696 // with a new version.
698 Builder.defineMacro("_XOPEN_SOURCE", "600");
700 Builder.defineMacro("_XOPEN_SOURCE", "500");
702 Builder.defineMacro("__C99FEATURES__");
703 Builder.defineMacro("_LARGEFILE_SOURCE");
704 Builder.defineMacro("_LARGEFILE64_SOURCE");
705 Builder.defineMacro("__EXTENSIONS__");
706 Builder.defineMacro("_REENTRANT");
709 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
710 : OSTargetInfo<Target>(Triple, Opts) {
711 this->WCharType = this->SignedInt;
712 // FIXME: WIntType should be SignedLong
717 template<typename Target>
718 class WindowsTargetInfo : public OSTargetInfo<Target> {
720 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
721 MacroBuilder &Builder) const override {
722 Builder.defineMacro("_WIN32");
724 void getVisualStudioDefines(const LangOptions &Opts,
725 MacroBuilder &Builder) const {
726 if (Opts.CPlusPlus) {
728 Builder.defineMacro("_CPPRTTI");
730 if (Opts.CXXExceptions)
731 Builder.defineMacro("_CPPUNWIND");
735 Builder.defineMacro("__BOOL_DEFINED");
737 if (!Opts.CharIsSigned)
738 Builder.defineMacro("_CHAR_UNSIGNED");
740 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
741 // but it works for now.
742 if (Opts.POSIXThreads)
743 Builder.defineMacro("_MT");
745 if (Opts.MSCompatibilityVersion) {
746 Builder.defineMacro("_MSC_VER",
747 Twine(Opts.MSCompatibilityVersion / 100000));
748 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
749 // FIXME We cannot encode the revision information into 32-bits
750 Builder.defineMacro("_MSC_BUILD", Twine(1));
752 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
753 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
755 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) {
756 if (Opts.CPlusPlus1z)
757 Builder.defineMacro("_MSVC_LANG", "201403L");
758 else if (Opts.CPlusPlus14)
759 Builder.defineMacro("_MSVC_LANG", "201402L");
763 if (Opts.MicrosoftExt) {
764 Builder.defineMacro("_MSC_EXTENSIONS");
766 if (Opts.CPlusPlus11) {
767 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
768 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
769 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
773 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
777 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
778 : OSTargetInfo<Target>(Triple, Opts) {}
781 template <typename Target>
782 class NaClTargetInfo : public OSTargetInfo<Target> {
784 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
785 MacroBuilder &Builder) const override {
786 if (Opts.POSIXThreads)
787 Builder.defineMacro("_REENTRANT");
789 Builder.defineMacro("_GNU_SOURCE");
791 DefineStd(Builder, "unix", Opts);
792 Builder.defineMacro("__ELF__");
793 Builder.defineMacro("__native_client__");
797 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
798 : OSTargetInfo<Target>(Triple, Opts) {
799 this->LongAlign = 32;
800 this->LongWidth = 32;
801 this->PointerAlign = 32;
802 this->PointerWidth = 32;
803 this->IntMaxType = TargetInfo::SignedLongLong;
804 this->Int64Type = TargetInfo::SignedLongLong;
805 this->DoubleAlign = 64;
806 this->LongDoubleWidth = 64;
807 this->LongDoubleAlign = 64;
808 this->LongLongWidth = 64;
809 this->LongLongAlign = 64;
810 this->SizeType = TargetInfo::UnsignedInt;
811 this->PtrDiffType = TargetInfo::SignedInt;
812 this->IntPtrType = TargetInfo::SignedInt;
813 // RegParmMax is inherited from the underlying architecture.
814 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble();
815 if (Triple.getArch() == llvm::Triple::arm) {
816 // Handled in ARM's setABI().
817 } else if (Triple.getArch() == llvm::Triple::x86) {
818 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128");
819 } else if (Triple.getArch() == llvm::Triple::x86_64) {
820 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128");
821 } else if (Triple.getArch() == llvm::Triple::mipsel) {
822 // Handled on mips' setDataLayout.
824 assert(Triple.getArch() == llvm::Triple::le32);
825 this->resetDataLayout("e-p:32:32-i64:64");
831 template<typename Target>
832 class FuchsiaTargetInfo : public OSTargetInfo<Target> {
834 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
835 MacroBuilder &Builder) const override {
836 Builder.defineMacro("__Fuchsia__");
837 Builder.defineMacro("__ELF__");
838 if (Opts.POSIXThreads)
839 Builder.defineMacro("_REENTRANT");
840 // Required by the libc++ locale support.
842 Builder.defineMacro("_GNU_SOURCE");
845 FuchsiaTargetInfo(const llvm::Triple &Triple,
846 const TargetOptions &Opts)
847 : OSTargetInfo<Target>(Triple, Opts) {
848 this->MCountName = "__mcount";
852 // WebAssembly target
853 template <typename Target>
854 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> {
855 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
856 MacroBuilder &Builder) const final {
857 // A common platform macro.
858 if (Opts.POSIXThreads)
859 Builder.defineMacro("_REENTRANT");
860 // Follow g++ convention and predefine _GNU_SOURCE for C++.
862 Builder.defineMacro("_GNU_SOURCE");
865 // As an optimization, group static init code together in a section.
866 const char *getStaticInitSectionSpecifier() const final {
867 return ".text.__startup";
871 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple,
872 const TargetOptions &Opts)
873 : OSTargetInfo<Target>(Triple, Opts) {
874 this->MCountName = "__mcount";
875 this->TheCXXABI.set(TargetCXXABI::WebAssembly);
879 //===----------------------------------------------------------------------===//
880 // Specific target implementations.
881 //===----------------------------------------------------------------------===//
883 // PPC abstract base class
884 class PPCTargetInfo : public TargetInfo {
885 static const Builtin::Info BuiltinInfo[];
886 static const char * const GCCRegNames[];
887 static const TargetInfo::GCCRegAlias GCCRegAliases[];
890 // Target cpu features.
906 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
907 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false),
908 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
909 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) {
911 SimdDefaultAlign = 128;
912 LongDoubleWidth = LongDoubleAlign = 128;
913 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
916 /// \brief Flags for architecture specific defines.
919 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
920 ArchDefinePpcgr = 1 << 1,
921 ArchDefinePpcsq = 1 << 2,
922 ArchDefine440 = 1 << 3,
923 ArchDefine603 = 1 << 4,
924 ArchDefine604 = 1 << 5,
925 ArchDefinePwr4 = 1 << 6,
926 ArchDefinePwr5 = 1 << 7,
927 ArchDefinePwr5x = 1 << 8,
928 ArchDefinePwr6 = 1 << 9,
929 ArchDefinePwr6x = 1 << 10,
930 ArchDefinePwr7 = 1 << 11,
931 ArchDefinePwr8 = 1 << 12,
932 ArchDefinePwr9 = 1 << 13,
933 ArchDefineA2 = 1 << 14,
934 ArchDefineA2q = 1 << 15
937 // Set the language option for altivec based on our value.
938 void adjust(LangOptions &Opts) override {
941 TargetInfo::adjust(Opts);
944 // Note: GCC recognizes the following additional cpus:
945 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
946 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
948 bool setCPU(const std::string &Name) override {
949 bool CPUKnown = llvm::StringSwitch<bool>(Name)
950 .Case("generic", true)
972 .Case("e500mc", true)
974 .Case("power3", true)
976 .Case("power4", true)
978 .Case("power5", true)
980 .Case("power5x", true)
982 .Case("power6", true)
984 .Case("power6x", true)
986 .Case("power7", true)
988 .Case("power8", true)
990 .Case("power9", true)
992 .Case("powerpc", true)
994 .Case("powerpc64", true)
996 .Case("powerpc64le", true)
997 .Case("ppc64le", true)
1007 StringRef getABI() const override { return ABI; }
1009 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1010 return llvm::makeArrayRef(BuiltinInfo,
1011 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin);
1014 bool isCLZForZeroUndef() const override { return false; }
1016 void getTargetDefines(const LangOptions &Opts,
1017 MacroBuilder &Builder) const override;
1020 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
1022 const std::vector<std::string> &FeaturesVec) const override;
1024 bool handleTargetFeatures(std::vector<std::string> &Features,
1025 DiagnosticsEngine &Diags) override;
1026 bool hasFeature(StringRef Feature) const override;
1027 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
1028 bool Enabled) const override;
1030 ArrayRef<const char *> getGCCRegNames() const override;
1031 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
1032 bool validateAsmConstraint(const char *&Name,
1033 TargetInfo::ConstraintInfo &Info) const override {
1035 default: return false;
1038 case 'b': // Base register
1039 case 'f': // Floating point register
1040 Info.setAllowsRegister();
1042 // FIXME: The following are added to allow parsing.
1043 // I just took a guess at what the actions should be.
1044 // Also, is more specific checking needed? I.e. specific registers?
1045 case 'd': // Floating point register (containing 64-bit value)
1046 case 'v': // Altivec vector register
1047 Info.setAllowsRegister();
1051 case 'd':// VSX vector register to hold vector double data
1052 case 'f':// VSX vector register to hold vector float data
1053 case 's':// VSX vector register to hold scalar float data
1054 case 'a':// Any VSX register
1055 case 'c':// An individual CR bit
1060 Info.setAllowsRegister();
1061 Name++; // Skip over 'w'.
1063 case 'h': // `MQ', `CTR', or `LINK' register
1064 case 'q': // `MQ' register
1065 case 'c': // `CTR' register
1066 case 'l': // `LINK' register
1067 case 'x': // `CR' register (condition register) number 0
1068 case 'y': // `CR' register (condition register)
1069 case 'z': // `XER[CA]' carry bit (part of the XER register)
1070 Info.setAllowsRegister();
1072 case 'I': // Signed 16-bit constant
1073 case 'J': // Unsigned 16-bit constant shifted left 16 bits
1074 // (use `L' instead for SImode constants)
1075 case 'K': // Unsigned 16-bit constant
1076 case 'L': // Signed 16-bit constant shifted left 16 bits
1077 case 'M': // Constant larger than 31
1078 case 'N': // Exact power of 2
1079 case 'P': // Constant whose negation is a signed 16-bit constant
1080 case 'G': // Floating point constant that can be loaded into a
1081 // register with one instruction per word
1082 case 'H': // Integer/Floating point constant that can be loaded
1083 // into a register using three instructions
1085 case 'm': // Memory operand. Note that on PowerPC targets, m can
1086 // include addresses that update the base register. It
1087 // is therefore only safe to use `m' in an asm statement
1088 // if that asm statement accesses the operand exactly once.
1089 // The asm statement must also use `%U<opno>' as a
1090 // placeholder for the "update" flag in the corresponding
1091 // load or store instruction. For example:
1092 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
1094 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
1095 // is not. Use es rather than m if you don't want the base
1096 // register to be updated.
1100 // es: A "stable" memory operand; that is, one which does not
1101 // include any automodification of the base register. Unlike
1102 // `m', this constraint can be used in asm statements that
1103 // might access the operand several times, or that might not
1104 // access it at all.
1105 Info.setAllowsMemory();
1106 Name++; // Skip over 'e'.
1108 case 'Q': // Memory operand that is an offset from a register (it is
1109 // usually better to use `m' or `es' in asm statements)
1110 case 'Z': // Memory operand that is an indexed or indirect from a
1111 // register (it is usually better to use `m' or `es' in
1113 Info.setAllowsMemory();
1114 Info.setAllowsRegister();
1116 case 'R': // AIX TOC entry
1117 case 'a': // Address operand that is an indexed or indirect from a
1118 // register (`p' is preferable for asm statements)
1119 case 'S': // Constant suitable as a 64-bit mask operand
1120 case 'T': // Constant suitable as a 32-bit mask operand
1121 case 'U': // System V Release 4 small data area reference
1122 case 't': // AND masks that can be performed by two rldic{l, r}
1124 case 'W': // Vector constant that does not require memory
1125 case 'j': // Vector constant that is all zeros.
1131 std::string convertConstraint(const char *&Constraint) const override {
1133 switch (*Constraint) {
1136 // Two-character constraint; add "^" hint for later parsing.
1137 R = std::string("^") + std::string(Constraint, 2);
1141 return TargetInfo::convertConstraint(Constraint);
1145 const char *getClobbers() const override {
1148 int getEHDataRegisterNumber(unsigned RegNo) const override {
1149 if (RegNo == 0) return 3;
1150 if (RegNo == 1) return 4;
1154 bool hasSjLjLowering() const override {
1158 bool useFloat128ManglingForLongDouble() const override {
1159 return LongDoubleWidth == 128 &&
1160 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() &&
1161 getTriple().isOSBinFormatELF();
1165 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
1166 #define BUILTIN(ID, TYPE, ATTRS) \
1167 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1168 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1169 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1170 #include "clang/Basic/BuiltinsPPC.def"
1173 /// handleTargetFeatures - Perform initialization based on the user
1174 /// configured set of features.
1175 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1176 DiagnosticsEngine &Diags) {
1177 for (const auto &Feature : Features) {
1178 if (Feature == "+altivec") {
1180 } else if (Feature == "+vsx") {
1182 } else if (Feature == "+bpermd") {
1184 } else if (Feature == "+extdiv") {
1186 } else if (Feature == "+power8-vector") {
1188 } else if (Feature == "+crypto") {
1190 } else if (Feature == "+direct-move") {
1191 HasDirectMove = true;
1192 } else if (Feature == "+qpx") {
1194 } else if (Feature == "+htm") {
1196 } else if (Feature == "+float128") {
1198 } else if (Feature == "+power9-vector") {
1201 // TODO: Finish this list and add an assert that we've handled them
1208 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1209 /// #defines that are not tied to a specific subtarget.
1210 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1211 MacroBuilder &Builder) const {
1212 // Target identification.
1213 Builder.defineMacro("__ppc__");
1214 Builder.defineMacro("__PPC__");
1215 Builder.defineMacro("_ARCH_PPC");
1216 Builder.defineMacro("__powerpc__");
1217 Builder.defineMacro("__POWERPC__");
1218 if (PointerWidth == 64) {
1219 Builder.defineMacro("_ARCH_PPC64");
1220 Builder.defineMacro("__powerpc64__");
1221 Builder.defineMacro("__ppc64__");
1222 Builder.defineMacro("__PPC64__");
1225 // Target properties.
1226 if (getTriple().getArch() == llvm::Triple::ppc64le) {
1227 Builder.defineMacro("_LITTLE_ENDIAN");
1229 if (getTriple().getOS() != llvm::Triple::NetBSD &&
1230 getTriple().getOS() != llvm::Triple::OpenBSD)
1231 Builder.defineMacro("_BIG_ENDIAN");
1235 if (ABI == "elfv1" || ABI == "elfv1-qpx")
1236 Builder.defineMacro("_CALL_ELF", "1");
1238 Builder.defineMacro("_CALL_ELF", "2");
1240 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but
1241 // our suppport post-dates this and it should work on all 64-bit ppc linux
1242 // platforms. It is guaranteed to work on all elfv2 platforms.
1243 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64)
1244 Builder.defineMacro("_CALL_LINUX", "1");
1246 // Subtarget options.
1247 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1248 Builder.defineMacro("__REGISTER_PREFIX__", "");
1250 // FIXME: Should be controlled by command line option.
1251 if (LongDoubleWidth == 128) {
1252 Builder.defineMacro("__LONG_DOUBLE_128__");
1253 Builder.defineMacro("__LONGDOUBLE128");
1256 // Define this for elfv2 (64-bit only) or 64-bit darwin.
1257 if (ABI == "elfv2" ||
1258 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64))
1259 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16");
1261 // CPU identification.
1262 ArchDefineTypes defs =
1263 (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1264 .Case("440", ArchDefineName)
1265 .Case("450", ArchDefineName | ArchDefine440)
1266 .Case("601", ArchDefineName)
1267 .Case("602", ArchDefineName | ArchDefinePpcgr)
1268 .Case("603", ArchDefineName | ArchDefinePpcgr)
1269 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1270 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1271 .Case("604", ArchDefineName | ArchDefinePpcgr)
1272 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1273 .Case("620", ArchDefineName | ArchDefinePpcgr)
1274 .Case("630", ArchDefineName | ArchDefinePpcgr)
1275 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1276 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1277 .Case("750", ArchDefineName | ArchDefinePpcgr)
1278 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
1280 .Case("a2", ArchDefineA2)
1281 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1282 .Case("pwr3", ArchDefinePpcgr)
1283 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1284 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
1286 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 |
1287 ArchDefinePpcgr | ArchDefinePpcsq)
1288 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 |
1289 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1290 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x |
1291 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
1293 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 |
1294 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
1295 ArchDefinePpcgr | ArchDefinePpcsq)
1296 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x |
1297 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
1298 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1299 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 |
1300 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
1301 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
1303 .Case("power3", ArchDefinePpcgr)
1304 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1305 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
1307 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
1308 ArchDefinePpcgr | ArchDefinePpcsq)
1309 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
1310 ArchDefinePwr4 | ArchDefinePpcgr |
1312 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
1313 ArchDefinePwr5 | ArchDefinePwr4 |
1314 ArchDefinePpcgr | ArchDefinePpcsq)
1315 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 |
1316 ArchDefinePwr5x | ArchDefinePwr5 |
1317 ArchDefinePwr4 | ArchDefinePpcgr |
1319 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x |
1320 ArchDefinePwr6 | ArchDefinePwr5x |
1321 ArchDefinePwr5 | ArchDefinePwr4 |
1322 ArchDefinePpcgr | ArchDefinePpcsq)
1323 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
1324 ArchDefinePwr6x | ArchDefinePwr6 |
1325 ArchDefinePwr5x | ArchDefinePwr5 |
1326 ArchDefinePwr4 | ArchDefinePpcgr |
1328 // powerpc64le automatically defaults to at least power8.
1329 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x |
1330 ArchDefinePwr6 | ArchDefinePwr5x |
1331 ArchDefinePwr5 | ArchDefinePwr4 |
1332 ArchDefinePpcgr | ArchDefinePpcsq)
1333 .Default(ArchDefineNone);
1335 if (defs & ArchDefineName)
1336 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1337 if (defs & ArchDefinePpcgr)
1338 Builder.defineMacro("_ARCH_PPCGR");
1339 if (defs & ArchDefinePpcsq)
1340 Builder.defineMacro("_ARCH_PPCSQ");
1341 if (defs & ArchDefine440)
1342 Builder.defineMacro("_ARCH_440");
1343 if (defs & ArchDefine603)
1344 Builder.defineMacro("_ARCH_603");
1345 if (defs & ArchDefine604)
1346 Builder.defineMacro("_ARCH_604");
1347 if (defs & ArchDefinePwr4)
1348 Builder.defineMacro("_ARCH_PWR4");
1349 if (defs & ArchDefinePwr5)
1350 Builder.defineMacro("_ARCH_PWR5");
1351 if (defs & ArchDefinePwr5x)
1352 Builder.defineMacro("_ARCH_PWR5X");
1353 if (defs & ArchDefinePwr6)
1354 Builder.defineMacro("_ARCH_PWR6");
1355 if (defs & ArchDefinePwr6x)
1356 Builder.defineMacro("_ARCH_PWR6X");
1357 if (defs & ArchDefinePwr7)
1358 Builder.defineMacro("_ARCH_PWR7");
1359 if (defs & ArchDefinePwr8)
1360 Builder.defineMacro("_ARCH_PWR8");
1361 if (defs & ArchDefinePwr9)
1362 Builder.defineMacro("_ARCH_PWR9");
1363 if (defs & ArchDefineA2)
1364 Builder.defineMacro("_ARCH_A2");
1365 if (defs & ArchDefineA2q) {
1366 Builder.defineMacro("_ARCH_A2Q");
1367 Builder.defineMacro("_ARCH_QP");
1370 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1371 Builder.defineMacro("__bg__");
1372 Builder.defineMacro("__THW_BLUEGENE__");
1373 Builder.defineMacro("__bgq__");
1374 Builder.defineMacro("__TOS_BGQ__");
1378 Builder.defineMacro("__VEC__", "10206");
1379 Builder.defineMacro("__ALTIVEC__");
1382 Builder.defineMacro("__VSX__");
1384 Builder.defineMacro("__POWER8_VECTOR__");
1386 Builder.defineMacro("__CRYPTO__");
1388 Builder.defineMacro("__HTM__");
1390 Builder.defineMacro("__FLOAT128__");
1392 Builder.defineMacro("__POWER9_VECTOR__");
1394 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1395 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1396 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1397 if (PointerWidth == 64)
1398 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1400 // We have support for the bswap intrinsics so we can define this.
1401 Builder.defineMacro("__HAVE_BSWAP__", "1");
1403 // FIXME: The following are not yet generated here by Clang, but are
1404 // generated by GCC:
1407 // __RECIP_PRECISION__
1408 // __APPLE_ALTIVEC__
1415 // __CMODEL_MEDIUM__
1422 // Handle explicit options being passed to the compiler here: if we've
1423 // explicitly turned off vsx and turned on any of:
1428 // then go ahead and error since the customer has expressed an incompatible
1430 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
1431 const std::vector<std::string> &FeaturesVec) {
1433 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") !=
1434 FeaturesVec.end()) {
1435 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") !=
1436 FeaturesVec.end()) {
1437 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
1442 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") !=
1443 FeaturesVec.end()) {
1444 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
1449 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") !=
1450 FeaturesVec.end()) {
1451 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
1456 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") !=
1457 FeaturesVec.end()) {
1458 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector"
1467 bool PPCTargetInfo::initFeatureMap(
1468 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
1469 const std::vector<std::string> &FeaturesVec) const {
1470 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1481 .Case("ppc64", true)
1482 .Case("ppc64le", true)
1485 Features["qpx"] = (CPU == "a2q");
1486 Features["power9-vector"] = (CPU == "pwr9");
1487 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1488 .Case("ppc64le", true)
1492 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1493 .Case("ppc64le", true)
1497 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1498 .Case("ppc64le", true)
1503 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1504 .Case("ppc64le", true)
1509 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1510 .Case("ppc64le", true)
1514 Features["vsx"] = llvm::StringSwitch<bool>(CPU)
1515 .Case("ppc64le", true)
1520 Features["htm"] = llvm::StringSwitch<bool>(CPU)
1521 .Case("ppc64le", true)
1526 if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
1529 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1532 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1533 return llvm::StringSwitch<bool>(Feature)
1534 .Case("powerpc", true)
1535 .Case("altivec", HasAltivec)
1536 .Case("vsx", HasVSX)
1537 .Case("power8-vector", HasP8Vector)
1538 .Case("crypto", HasP8Crypto)
1539 .Case("direct-move", HasDirectMove)
1540 .Case("qpx", HasQPX)
1541 .Case("htm", HasHTM)
1542 .Case("bpermd", HasBPERMD)
1543 .Case("extdiv", HasExtDiv)
1544 .Case("float128", HasFloat128)
1545 .Case("power9-vector", HasP9Vector)
1549 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1550 StringRef Name, bool Enabled) const {
1552 // If we're enabling any of the vsx based features then enable vsx and
1553 // altivec. We'll diagnose any problems later.
1554 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name)
1556 .Case("direct-move", true)
1557 .Case("power8-vector", true)
1558 .Case("power9-vector", true)
1559 .Case("float128", true)
1562 Features["vsx"] = Features["altivec"] = true;
1563 if (Name == "power9-vector")
1564 Features["power8-vector"] = true;
1565 Features[Name] = true;
1567 // If we're disabling altivec or vsx go ahead and disable all of the vsx
1569 if ((Name == "altivec") || (Name == "vsx"))
1570 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] =
1571 Features["float128"] = Features["power9-vector"] = false;
1572 if (Name == "power8-vector")
1573 Features["power9-vector"] = false;
1574 Features[Name] = false;
1578 const char * const PPCTargetInfo::GCCRegNames[] = {
1579 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1580 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1581 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1582 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1583 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1584 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1585 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1586 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1587 "mq", "lr", "ctr", "ap",
1588 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1590 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1591 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1592 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1593 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1595 "spe_acc", "spefscr",
1599 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const {
1600 return llvm::makeArrayRef(GCCRegNames);
1603 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1604 // While some of these aliases do map to different registers
1605 // they still share the same register name.
1616 { { "10" }, "r10" },
1617 { { "11" }, "r11" },
1618 { { "12" }, "r12" },
1619 { { "13" }, "r13" },
1620 { { "14" }, "r14" },
1621 { { "15" }, "r15" },
1622 { { "16" }, "r16" },
1623 { { "17" }, "r17" },
1624 { { "18" }, "r18" },
1625 { { "19" }, "r19" },
1626 { { "20" }, "r20" },
1627 { { "21" }, "r21" },
1628 { { "22" }, "r22" },
1629 { { "23" }, "r23" },
1630 { { "24" }, "r24" },
1631 { { "25" }, "r25" },
1632 { { "26" }, "r26" },
1633 { { "27" }, "r27" },
1634 { { "28" }, "r28" },
1635 { { "29" }, "r29" },
1636 { { "30" }, "r30" },
1637 { { "31" }, "r31" },
1638 { { "fr0" }, "f0" },
1639 { { "fr1" }, "f1" },
1640 { { "fr2" }, "f2" },
1641 { { "fr3" }, "f3" },
1642 { { "fr4" }, "f4" },
1643 { { "fr5" }, "f5" },
1644 { { "fr6" }, "f6" },
1645 { { "fr7" }, "f7" },
1646 { { "fr8" }, "f8" },
1647 { { "fr9" }, "f9" },
1648 { { "fr10" }, "f10" },
1649 { { "fr11" }, "f11" },
1650 { { "fr12" }, "f12" },
1651 { { "fr13" }, "f13" },
1652 { { "fr14" }, "f14" },
1653 { { "fr15" }, "f15" },
1654 { { "fr16" }, "f16" },
1655 { { "fr17" }, "f17" },
1656 { { "fr18" }, "f18" },
1657 { { "fr19" }, "f19" },
1658 { { "fr20" }, "f20" },
1659 { { "fr21" }, "f21" },
1660 { { "fr22" }, "f22" },
1661 { { "fr23" }, "f23" },
1662 { { "fr24" }, "f24" },
1663 { { "fr25" }, "f25" },
1664 { { "fr26" }, "f26" },
1665 { { "fr27" }, "f27" },
1666 { { "fr28" }, "f28" },
1667 { { "fr29" }, "f29" },
1668 { { "fr30" }, "f30" },
1669 { { "fr31" }, "f31" },
1670 { { "cc" }, "cr0" },
1673 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
1674 return llvm::makeArrayRef(GCCRegAliases);
1677 class PPC32TargetInfo : public PPCTargetInfo {
1679 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1680 : PPCTargetInfo(Triple, Opts) {
1681 resetDataLayout("E-m:e-p:32:32-i64:64-n32");
1683 switch (getTriple().getOS()) {
1684 case llvm::Triple::Linux:
1685 case llvm::Triple::FreeBSD:
1686 case llvm::Triple::NetBSD:
1687 SizeType = UnsignedInt;
1688 PtrDiffType = SignedInt;
1689 IntPtrType = SignedInt;
1695 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1696 LongDoubleWidth = LongDoubleAlign = 64;
1697 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1700 // PPC32 supports atomics up to 4 bytes.
1701 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1704 BuiltinVaListKind getBuiltinVaListKind() const override {
1705 // This is the ELF definition, and is overridden by the Darwin sub-target
1706 return TargetInfo::PowerABIBuiltinVaList;
1710 // Note: ABI differences may eventually require us to have a separate
1711 // TargetInfo for little endian.
1712 class PPC64TargetInfo : public PPCTargetInfo {
1714 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1715 : PPCTargetInfo(Triple, Opts) {
1716 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1717 IntMaxType = SignedLong;
1718 Int64Type = SignedLong;
1720 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1721 resetDataLayout("e-m:e-i64:64-n32:64");
1724 resetDataLayout("E-m:e-i64:64-n32:64");
1728 switch (getTriple().getOS()) {
1729 case llvm::Triple::FreeBSD:
1730 LongDoubleWidth = LongDoubleAlign = 64;
1731 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1733 case llvm::Triple::NetBSD:
1734 IntMaxType = SignedLongLong;
1735 Int64Type = SignedLongLong;
1741 // PPC64 supports atomics up to 8 bytes.
1742 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1744 BuiltinVaListKind getBuiltinVaListKind() const override {
1745 return TargetInfo::CharPtrBuiltinVaList;
1747 // PPC64 Linux-specific ABI options.
1748 bool setABI(const std::string &Name) override {
1749 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1757 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> {
1759 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1760 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
1761 HasAlignMac68kSupport = true;
1762 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1763 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1765 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
1767 BuiltinVaListKind getBuiltinVaListKind() const override {
1768 return TargetInfo::CharPtrBuiltinVaList;
1772 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> {
1774 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1775 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
1776 HasAlignMac68kSupport = true;
1777 resetDataLayout("E-m:o-i64:64-n32:64");
1781 static const unsigned NVPTXAddrSpaceMap[] = {
1785 4, // opencl_constant
1786 // FIXME: generic has to be added to the target
1787 0, // opencl_generic
1793 class NVPTXTargetInfo : public TargetInfo {
1794 static const char *const GCCRegNames[];
1795 static const Builtin::Info BuiltinInfo[];
1797 std::unique_ptr<TargetInfo> HostTarget;
1800 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts,
1801 unsigned TargetPointerWidth)
1802 : TargetInfo(Triple) {
1803 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) &&
1804 "NVPTX only supports 32- and 64-bit modes.");
1806 TLSSupported = false;
1807 AddrSpaceMap = &NVPTXAddrSpaceMap;
1808 UseAddrSpaceMapMangling = true;
1810 // Define available target features
1811 // These must be defined in sorted order!
1812 NoAsmVariants = true;
1813 GPU = CudaArch::SM_20;
1815 if (TargetPointerWidth == 32)
1816 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64");
1818 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64");
1820 // If possible, get a TargetInfo for our host triple, so we can match its
1822 llvm::Triple HostTriple(Opts.HostTriple);
1823 if (!HostTriple.isNVPTX())
1824 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts));
1826 // If no host target, make some guesses about the data layout and return.
1828 LongWidth = LongAlign = TargetPointerWidth;
1829 PointerWidth = PointerAlign = TargetPointerWidth;
1830 switch (TargetPointerWidth) {
1832 SizeType = TargetInfo::UnsignedInt;
1833 PtrDiffType = TargetInfo::SignedInt;
1834 IntPtrType = TargetInfo::SignedInt;
1837 SizeType = TargetInfo::UnsignedLong;
1838 PtrDiffType = TargetInfo::SignedLong;
1839 IntPtrType = TargetInfo::SignedLong;
1842 llvm_unreachable("TargetPointerWidth must be 32 or 64");
1847 // Copy properties from host target.
1848 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0);
1849 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0);
1850 BoolWidth = HostTarget->getBoolWidth();
1851 BoolAlign = HostTarget->getBoolAlign();
1852 IntWidth = HostTarget->getIntWidth();
1853 IntAlign = HostTarget->getIntAlign();
1854 HalfWidth = HostTarget->getHalfWidth();
1855 HalfAlign = HostTarget->getHalfAlign();
1856 FloatWidth = HostTarget->getFloatWidth();
1857 FloatAlign = HostTarget->getFloatAlign();
1858 DoubleWidth = HostTarget->getDoubleWidth();
1859 DoubleAlign = HostTarget->getDoubleAlign();
1860 LongWidth = HostTarget->getLongWidth();
1861 LongAlign = HostTarget->getLongAlign();
1862 LongLongWidth = HostTarget->getLongLongWidth();
1863 LongLongAlign = HostTarget->getLongLongAlign();
1864 MinGlobalAlign = HostTarget->getMinGlobalAlign();
1865 NewAlign = HostTarget->getNewAlign();
1866 DefaultAlignForAttributeAligned =
1867 HostTarget->getDefaultAlignForAttributeAligned();
1868 SizeType = HostTarget->getSizeType();
1869 IntMaxType = HostTarget->getIntMaxType();
1870 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0);
1871 IntPtrType = HostTarget->getIntPtrType();
1872 WCharType = HostTarget->getWCharType();
1873 WIntType = HostTarget->getWIntType();
1874 Char16Type = HostTarget->getChar16Type();
1875 Char32Type = HostTarget->getChar32Type();
1876 Int64Type = HostTarget->getInt64Type();
1877 SigAtomicType = HostTarget->getSigAtomicType();
1878 ProcessIDType = HostTarget->getProcessIDType();
1880 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
1881 UseZeroLengthBitfieldAlignment =
1882 HostTarget->useZeroLengthBitfieldAlignment();
1883 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
1884 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
1886 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
1887 // we need those macros to be identical on host and device, because (among
1888 // other things) they affect which standard library classes are defined, and
1889 // we need all classes to be defined on both the host and device.
1890 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
1892 // Properties intentionally not copied from host:
1893 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the
1894 // host/device boundary.
1895 // - SuitableAlign: Not visible across the host/device boundary, and may
1896 // correctly be different on host/device, e.g. if host has wider vector
1897 // types than device.
1898 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same
1899 // as its double type, but that's not necessarily true on the host.
1900 // TODO: nvcc emits a warning when using long double on device; we should
1903 void getTargetDefines(const LangOptions &Opts,
1904 MacroBuilder &Builder) const override {
1905 Builder.defineMacro("__PTX__");
1906 Builder.defineMacro("__NVPTX__");
1907 if (Opts.CUDAIsDevice) {
1908 // Set __CUDA_ARCH__ for the GPU specified.
1909 std::string CUDAArchCode = [this] {
1911 case CudaArch::UNKNOWN:
1912 assert(false && "No GPU arch when compiling CUDA device code.");
1914 case CudaArch::SM_20:
1916 case CudaArch::SM_21:
1918 case CudaArch::SM_30:
1920 case CudaArch::SM_32:
1922 case CudaArch::SM_35:
1924 case CudaArch::SM_37:
1926 case CudaArch::SM_50:
1928 case CudaArch::SM_52:
1930 case CudaArch::SM_53:
1932 case CudaArch::SM_60:
1934 case CudaArch::SM_61:
1936 case CudaArch::SM_62:
1939 llvm_unreachable("unhandled CudaArch");
1941 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1944 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1945 return llvm::makeArrayRef(BuiltinInfo,
1946 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin);
1949 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
1951 const std::vector<std::string> &FeaturesVec) const override {
1952 Features["satom"] = GPU >= CudaArch::SM_60;
1953 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1956 bool hasFeature(StringRef Feature) const override {
1957 return llvm::StringSwitch<bool>(Feature)
1958 .Cases("ptx", "nvptx", true)
1959 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope.
1963 ArrayRef<const char *> getGCCRegNames() const override;
1964 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1968 bool validateAsmConstraint(const char *&Name,
1969 TargetInfo::ConstraintInfo &Info) const override {
1979 Info.setAllowsRegister();
1983 const char *getClobbers() const override {
1984 // FIXME: Is this really right?
1987 BuiltinVaListKind getBuiltinVaListKind() const override {
1989 return TargetInfo::CharPtrBuiltinVaList;
1991 bool setCPU(const std::string &Name) override {
1992 GPU = StringToCudaArch(Name);
1993 return GPU != CudaArch::UNKNOWN;
1995 void setSupportedOpenCLOpts() override {
1996 auto &Opts = getSupportedOpenCLOpts();
1997 Opts.support("cl_clang_storage_class_specifiers");
1998 Opts.support("cl_khr_gl_sharing");
1999 Opts.support("cl_khr_icd");
2001 Opts.support("cl_khr_fp64");
2002 Opts.support("cl_khr_byte_addressable_store");
2003 Opts.support("cl_khr_global_int32_base_atomics");
2004 Opts.support("cl_khr_global_int32_extended_atomics");
2005 Opts.support("cl_khr_local_int32_base_atomics");
2006 Opts.support("cl_khr_local_int32_extended_atomics");
2009 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2010 // CUDA compilations support all of the host's calling conventions.
2012 // TODO: We should warn if you apply a non-default CC to anything other than
2015 return HostTarget->checkCallingConvention(CC);
2016 return CCCR_Warning;
2020 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
2021 #define BUILTIN(ID, TYPE, ATTRS) \
2022 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2023 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
2024 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
2025 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2026 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2027 #include "clang/Basic/BuiltinsNVPTX.def"
2030 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
2032 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
2033 return llvm::makeArrayRef(GCCRegNames);
2036 static const LangAS::Map AMDGPUPrivateIsZeroMap = {
2040 2, // opencl_constant
2041 4, // opencl_generic
2046 static const LangAS::Map AMDGPUGenericIsZeroMap = {
2050 2, // opencl_constant
2051 0, // opencl_generic
2057 // If you edit the description strings, make sure you update
2058 // getPointerWidthV().
2060 static const char *const DataLayoutStringR600 =
2061 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2062 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
2064 static const char *const DataLayoutStringSIPrivateIsZero =
2065 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
2066 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2067 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
2069 static const char *const DataLayoutStringSIGenericIsZero =
2070 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
2071 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2072 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
2074 class AMDGPUTargetInfo final : public TargetInfo {
2075 static const Builtin::Info BuiltinInfo[];
2076 static const char * const GCCRegNames[];
2079 unsigned Generic, Global, Local, Constant, Private;
2080 AddrSpace(bool IsGenericZero_ = false){
2081 if (IsGenericZero_) {
2097 /// \brief The GPU profiles supported by the AMDGPU target.
2105 GK_EVERGREEN_DOUBLE_OPS,
2106 GK_NORTHERN_ISLANDS,
2119 static bool hasFullSpeedFMAF32(StringRef GPUName) {
2120 return parseAMDGCNName(GPUName) >= GK_GFX9;
2123 static bool isAMDGCN(const llvm::Triple &TT) {
2124 return TT.getArch() == llvm::Triple::amdgcn;
2127 static bool isGenericZero(const llvm::Triple &TT) {
2128 return TT.getEnvironmentName() == "amdgiz" ||
2129 TT.getEnvironmentName() == "amdgizcl";
2132 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
2133 : TargetInfo(Triple) ,
2134 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600),
2138 AS(isGenericZero(Triple)){
2139 if (getTriple().getArch() == llvm::Triple::amdgcn) {
2144 auto IsGenericZero = isGenericZero(Triple);
2145 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ?
2146 (IsGenericZero ? DataLayoutStringSIGenericIsZero :
2147 DataLayoutStringSIPrivateIsZero)
2148 : DataLayoutStringR600);
2149 assert(DataLayout->getAllocaAddrSpace() == AS.Private);
2151 AddrSpaceMap = IsGenericZero ? &AMDGPUGenericIsZeroMap :
2152 &AMDGPUPrivateIsZeroMap;
2153 UseAddrSpaceMapMangling = true;
2156 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
2157 if (GPU <= GK_CAYMAN)
2160 if (AddrSpace == AS.Private || AddrSpace == AS.Local) {
2166 uint64_t getMaxPointerWidth() const override {
2167 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32;
2170 const char * getClobbers() const override {
2174 ArrayRef<const char *> getGCCRegNames() const override;
2176 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2180 bool validateAsmConstraint(const char *&Name,
2181 TargetInfo::ConstraintInfo &Info) const override {
2186 Info.setAllowsRegister();
2192 bool initFeatureMap(llvm::StringMap<bool> &Features,
2193 DiagnosticsEngine &Diags, StringRef CPU,
2194 const std::vector<std::string> &FeatureVec) const override;
2196 void adjustTargetOptions(const CodeGenOptions &CGOpts,
2197 TargetOptions &TargetOpts) const override {
2198 bool hasFP32Denormals = false;
2199 bool hasFP64Denormals = false;
2200 for (auto &I : TargetOpts.FeaturesAsWritten) {
2201 if (I == "+fp32-denormals" || I == "-fp32-denormals")
2202 hasFP32Denormals = true;
2203 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals")
2204 hasFP64Denormals = true;
2206 if (!hasFP32Denormals)
2207 TargetOpts.Features.push_back(
2208 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) &&
2209 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str());
2210 // Always do not flush fp64 or fp16 denorms.
2211 if (!hasFP64Denormals && hasFP64)
2212 TargetOpts.Features.push_back("+fp64-fp16-denormals");
2215 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
2216 return llvm::makeArrayRef(BuiltinInfo,
2217 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin);
2220 void getTargetDefines(const LangOptions &Opts,
2221 MacroBuilder &Builder) const override {
2222 if (getTriple().getArch() == llvm::Triple::amdgcn)
2223 Builder.defineMacro("__AMDGCN__");
2225 Builder.defineMacro("__R600__");
2228 Builder.defineMacro("__HAS_FMAF__");
2230 Builder.defineMacro("__HAS_LDEXPF__");
2232 Builder.defineMacro("__HAS_FP64__");
2235 BuiltinVaListKind getBuiltinVaListKind() const override {
2236 return TargetInfo::CharPtrBuiltinVaList;
2239 static GPUKind parseR600Name(StringRef Name) {
2240 return llvm::StringSwitch<GPUKind>(Name)
2241 .Case("r600" , GK_R600)
2242 .Case("rv610", GK_R600)
2243 .Case("rv620", GK_R600)
2244 .Case("rv630", GK_R600)
2245 .Case("rv635", GK_R600)
2246 .Case("rs780", GK_R600)
2247 .Case("rs880", GK_R600)
2248 .Case("rv670", GK_R600_DOUBLE_OPS)
2249 .Case("rv710", GK_R700)
2250 .Case("rv730", GK_R700)
2251 .Case("rv740", GK_R700_DOUBLE_OPS)
2252 .Case("rv770", GK_R700_DOUBLE_OPS)
2253 .Case("palm", GK_EVERGREEN)
2254 .Case("cedar", GK_EVERGREEN)
2255 .Case("sumo", GK_EVERGREEN)
2256 .Case("sumo2", GK_EVERGREEN)
2257 .Case("redwood", GK_EVERGREEN)
2258 .Case("juniper", GK_EVERGREEN)
2259 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
2260 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
2261 .Case("barts", GK_NORTHERN_ISLANDS)
2262 .Case("turks", GK_NORTHERN_ISLANDS)
2263 .Case("caicos", GK_NORTHERN_ISLANDS)
2264 .Case("cayman", GK_CAYMAN)
2265 .Case("aruba", GK_CAYMAN)
2269 static GPUKind parseAMDGCNName(StringRef Name) {
2270 return llvm::StringSwitch<GPUKind>(Name)
2271 .Case("tahiti", GK_GFX6)
2272 .Case("pitcairn", GK_GFX6)
2273 .Case("verde", GK_GFX6)
2274 .Case("oland", GK_GFX6)
2275 .Case("hainan", GK_GFX6)
2276 .Case("bonaire", GK_GFX7)
2277 .Case("kabini", GK_GFX7)
2278 .Case("kaveri", GK_GFX7)
2279 .Case("hawaii", GK_GFX7)
2280 .Case("mullins", GK_GFX7)
2281 .Case("gfx700", GK_GFX7)
2282 .Case("gfx701", GK_GFX7)
2283 .Case("gfx702", GK_GFX7)
2284 .Case("tonga", GK_GFX8)
2285 .Case("iceland", GK_GFX8)
2286 .Case("carrizo", GK_GFX8)
2287 .Case("fiji", GK_GFX8)
2288 .Case("stoney", GK_GFX8)
2289 .Case("polaris10", GK_GFX8)
2290 .Case("polaris11", GK_GFX8)
2291 .Case("gfx800", GK_GFX8)
2292 .Case("gfx801", GK_GFX8)
2293 .Case("gfx802", GK_GFX8)
2294 .Case("gfx803", GK_GFX8)
2295 .Case("gfx804", GK_GFX8)
2296 .Case("gfx810", GK_GFX8)
2297 .Case("gfx900", GK_GFX9)
2298 .Case("gfx901", GK_GFX9)
2302 bool setCPU(const std::string &Name) override {
2303 if (getTriple().getArch() == llvm::Triple::amdgcn)
2304 GPU = parseAMDGCNName(Name);
2306 GPU = parseR600Name(Name);
2308 return GPU != GK_NONE;
2311 void setSupportedOpenCLOpts() override {
2312 auto &Opts = getSupportedOpenCLOpts();
2313 Opts.support("cl_clang_storage_class_specifiers");
2314 Opts.support("cl_khr_icd");
2317 Opts.support("cl_khr_fp64");
2318 if (GPU >= GK_EVERGREEN) {
2319 Opts.support("cl_khr_byte_addressable_store");
2320 Opts.support("cl_khr_global_int32_base_atomics");
2321 Opts.support("cl_khr_global_int32_extended_atomics");
2322 Opts.support("cl_khr_local_int32_base_atomics");
2323 Opts.support("cl_khr_local_int32_extended_atomics");
2325 if (GPU >= GK_GFX6) {
2326 Opts.support("cl_khr_fp16");
2327 Opts.support("cl_khr_int64_base_atomics");
2328 Opts.support("cl_khr_int64_extended_atomics");
2329 Opts.support("cl_khr_mipmap_image");
2330 Opts.support("cl_khr_subgroups");
2331 Opts.support("cl_khr_3d_image_writes");
2332 Opts.support("cl_amd_media_ops");
2333 Opts.support("cl_amd_media_ops2");
2337 LangAS::ID getOpenCLImageAddrSpace() const override {
2338 return LangAS::opencl_constant;
2341 /// \returns Target specific vtbl ptr address space.
2342 unsigned getVtblPtrAddressSpace() const override {
2343 // \todo: We currently have address spaces defined in AMDGPU Backend. It
2344 // would be nice if we could use it here instead of using bare numbers (same
2345 // applies to getDWARFAddressSpace).
2346 return 2; // constant.
2349 /// \returns If a target requires an address within a target specific address
2350 /// space \p AddressSpace to be converted in order to be used, then return the
2351 /// corresponding target specific DWARF address space.
2353 /// \returns Otherwise return None and no conversion will be emitted in the
2355 Optional<unsigned> getDWARFAddressSpace(
2356 unsigned AddressSpace) const override {
2357 const unsigned DWARF_Private = 1;
2358 const unsigned DWARF_Local = 2;
2359 if (AddressSpace == AS.Private) {
2360 return DWARF_Private;
2361 } else if (AddressSpace == AS.Local) {
2368 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2371 return CCCR_Warning;
2373 case CC_OpenCLKernel:
2378 // In amdgcn target the null pointer in global, constant, and generic
2379 // address space has value 0 but in private and local address space has
2381 uint64_t getNullPointerValue(unsigned AS) const override {
2382 return AS == LangAS::opencl_local ? ~0 : 0;
2386 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
2387 #define BUILTIN(ID, TYPE, ATTRS) \
2388 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2389 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2390 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2391 #include "clang/Basic/BuiltinsAMDGPU.def"
2393 const char * const AMDGPUTargetInfo::GCCRegNames[] = {
2394 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2395 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2396 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2397 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
2398 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
2399 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
2400 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
2401 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
2402 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
2403 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
2404 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
2405 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
2406 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
2407 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
2408 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
2409 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
2410 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
2411 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
2412 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
2413 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
2414 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
2415 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
2416 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
2417 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
2418 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
2419 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
2420 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
2421 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
2422 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
2423 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
2424 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
2425 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
2426 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2427 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
2428 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
2429 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
2430 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
2431 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
2432 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
2433 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
2434 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
2435 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
2436 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
2437 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
2438 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
2439 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
2440 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
2441 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127",
2442 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi",
2443 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi"
2446 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const {
2447 return llvm::makeArrayRef(GCCRegNames);
2450 bool AMDGPUTargetInfo::initFeatureMap(
2451 llvm::StringMap<bool> &Features,
2452 DiagnosticsEngine &Diags, StringRef CPU,
2453 const std::vector<std::string> &FeatureVec) const {
2455 // XXX - What does the member GPU mean if device name string passed here?
2456 if (getTriple().getArch() == llvm::Triple::amdgcn) {
2460 switch (parseAMDGCNName(CPU)) {
2466 Features["gfx9-insts"] = true;
2469 Features["s-memrealtime"] = true;
2470 Features["16-bit-insts"] = true;
2471 Features["dpp"] = true;
2477 llvm_unreachable("unhandled subtarget");
2483 switch (parseR600Name(CPU)) {
2487 case GK_NORTHERN_ISLANDS:
2489 case GK_R600_DOUBLE_OPS:
2490 case GK_R700_DOUBLE_OPS:
2491 case GK_EVERGREEN_DOUBLE_OPS:
2493 Features["fp64"] = true;
2498 llvm_unreachable("unhandled subtarget");
2502 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec);
2505 const Builtin::Info BuiltinInfoX86[] = {
2506 #define BUILTIN(ID, TYPE, ATTRS) \
2507 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2508 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2509 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2510 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
2511 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
2512 #include "clang/Basic/BuiltinsX86.def"
2514 #define BUILTIN(ID, TYPE, ATTRS) \
2515 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2516 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2517 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2518 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
2519 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
2520 #include "clang/Basic/BuiltinsX86_64.def"
2524 static const char* const GCCRegNames[] = {
2525 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
2526 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
2527 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
2528 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
2529 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
2530 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2531 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
2532 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
2533 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
2534 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23",
2535 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31",
2536 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23",
2537 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31",
2538 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7",
2539 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15",
2540 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23",
2541 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31",
2542 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7",
2545 const TargetInfo::AddlRegName AddlRegNames[] = {
2546 { { "al", "ah", "eax", "rax" }, 0 },
2547 { { "bl", "bh", "ebx", "rbx" }, 3 },
2548 { { "cl", "ch", "ecx", "rcx" }, 2 },
2549 { { "dl", "dh", "edx", "rdx" }, 1 },
2550 { { "esi", "rsi" }, 4 },
2551 { { "edi", "rdi" }, 5 },
2552 { { "esp", "rsp" }, 7 },
2553 { { "ebp", "rbp" }, 6 },
2554 { { "r8d", "r8w", "r8b" }, 38 },
2555 { { "r9d", "r9w", "r9b" }, 39 },
2556 { { "r10d", "r10w", "r10b" }, 40 },
2557 { { "r11d", "r11w", "r11b" }, 41 },
2558 { { "r12d", "r12w", "r12b" }, 42 },
2559 { { "r13d", "r13w", "r13b" }, 43 },
2560 { { "r14d", "r14w", "r14b" }, 44 },
2561 { { "r15d", "r15w", "r15b" }, 45 },
2564 // X86 target abstract base class; x86-32 and x86-64 are very close, so
2565 // most of the implementation can be shared.
2566 class X86TargetInfo : public TargetInfo {
2568 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
2571 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
2572 } MMX3DNowLevel = NoMMX3DNow;
2580 bool HasAES = false;
2581 bool HasPCLMUL = false;
2582 bool HasLZCNT = false;
2583 bool HasRDRND = false;
2584 bool HasFSGSBASE = false;
2585 bool HasBMI = false;
2586 bool HasBMI2 = false;
2587 bool HasPOPCNT = false;
2588 bool HasRTM = false;
2589 bool HasPRFCHW = false;
2590 bool HasRDSEED = false;
2591 bool HasADX = false;
2592 bool HasTBM = false;
2593 bool HasFMA = false;
2594 bool HasF16C = false;
2595 bool HasAVX512CD = false;
2596 bool HasAVX512ER = false;
2597 bool HasAVX512PF = false;
2598 bool HasAVX512DQ = false;
2599 bool HasAVX512BW = false;
2600 bool HasAVX512VL = false;
2601 bool HasAVX512VBMI = false;
2602 bool HasAVX512IFMA = false;
2603 bool HasSHA = false;
2604 bool HasMPX = false;
2605 bool HasSGX = false;
2606 bool HasCX16 = false;
2607 bool HasFXSR = false;
2608 bool HasXSAVE = false;
2609 bool HasXSAVEOPT = false;
2610 bool HasXSAVEC = false;
2611 bool HasXSAVES = false;
2612 bool HasMWAITX = false;
2613 bool HasCLZERO = false;
2614 bool HasPKU = false;
2615 bool HasCLFLUSHOPT = false;
2616 bool HasCLWB = false;
2617 bool HasMOVBE = false;
2618 bool HasPREFETCHWT1 = false;
2620 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2622 /// Each enumeration represents a particular CPU supported by Clang. These
2623 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2628 /// i386-generation processors.
2634 /// i486-generation processors.
2643 /// i586-generation processors, P5 microarchitecture based.
2651 /// i686-generation processors, P6 / Pentium M microarchitecture based.
2661 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2662 /// Clang however has some logic to suport this.
2663 // FIXME: Warn, deprecate, and potentially remove this.
2668 /// Netburst microarchitecture based processors.
2677 /// Core microarchitecture based processors.
2681 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2682 /// codename which GCC no longer accepts as an option to -march, but Clang
2683 /// has some logic for recognizing it.
2684 // FIXME: Warn, deprecate, and potentially remove this.
2696 /// Nehalem microarchitecture based processors.
2700 /// Westmere microarchitecture based processors.
2703 /// \name Sandy Bridge
2704 /// Sandy Bridge microarchitecture based processors.
2707 /// \name Ivy Bridge
2708 /// Ivy Bridge microarchitecture based processors.
2712 /// Haswell microarchitecture based processors.
2716 /// Broadwell microarchitecture based processors.
2719 /// \name Skylake Client
2720 /// Skylake client microarchitecture based processors.
2723 /// \name Skylake Server
2724 /// Skylake server microarchitecture based processors.
2727 /// \name Cannonlake Client
2728 /// Cannonlake client microarchitecture based processors.
2731 /// \name Knights Landing
2732 /// Knights Landing processor.
2736 /// Lakemont microarchitecture based processors.
2740 /// K6 architecture processors.
2748 /// K7 architecture processors.
2751 CK_AthlonThunderbird,
2758 /// K8 architecture processors.
2771 /// Bobcat architecture processors.
2778 /// Bulldozer architecture processors.
2787 /// Zen architecture processors.
2792 /// This specification is deprecated and will be removed in the future.
2793 /// Users should prefer \see CK_K8.
2794 // FIXME: Warn on this when the CPU is set to it.
2800 /// Geode processors.
2806 CPUKind getCPUKind(StringRef CPU) const {
2807 return llvm::StringSwitch<CPUKind>(CPU)
2808 .Case("i386", CK_i386)
2809 .Case("i486", CK_i486)
2810 .Case("winchip-c6", CK_WinChipC6)
2811 .Case("winchip2", CK_WinChip2)
2813 .Case("i586", CK_i586)
2814 .Case("pentium", CK_Pentium)
2815 .Case("pentium-mmx", CK_PentiumMMX)
2816 .Case("i686", CK_i686)
2817 .Case("pentiumpro", CK_PentiumPro)
2818 .Case("pentium2", CK_Pentium2)
2819 .Case("pentium3", CK_Pentium3)
2820 .Case("pentium3m", CK_Pentium3M)
2821 .Case("pentium-m", CK_PentiumM)
2822 .Case("c3-2", CK_C3_2)
2823 .Case("yonah", CK_Yonah)
2824 .Case("pentium4", CK_Pentium4)
2825 .Case("pentium4m", CK_Pentium4M)
2826 .Case("prescott", CK_Prescott)
2827 .Case("nocona", CK_Nocona)
2828 .Case("core2", CK_Core2)
2829 .Case("penryn", CK_Penryn)
2830 .Case("bonnell", CK_Bonnell)
2831 .Case("atom", CK_Bonnell) // Legacy name.
2832 .Case("silvermont", CK_Silvermont)
2833 .Case("slm", CK_Silvermont) // Legacy name.
2834 .Case("nehalem", CK_Nehalem)
2835 .Case("corei7", CK_Nehalem) // Legacy name.
2836 .Case("westmere", CK_Westmere)
2837 .Case("sandybridge", CK_SandyBridge)
2838 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2839 .Case("ivybridge", CK_IvyBridge)
2840 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2841 .Case("haswell", CK_Haswell)
2842 .Case("core-avx2", CK_Haswell) // Legacy name.
2843 .Case("broadwell", CK_Broadwell)
2844 .Case("skylake", CK_SkylakeClient)
2845 .Case("skylake-avx512", CK_SkylakeServer)
2846 .Case("skx", CK_SkylakeServer) // Legacy name.
2847 .Case("cannonlake", CK_Cannonlake)
2848 .Case("knl", CK_KNL)
2849 .Case("lakemont", CK_Lakemont)
2851 .Case("k6-2", CK_K6_2)
2852 .Case("k6-3", CK_K6_3)
2853 .Case("athlon", CK_Athlon)
2854 .Case("athlon-tbird", CK_AthlonThunderbird)
2855 .Case("athlon-4", CK_Athlon4)
2856 .Case("athlon-xp", CK_AthlonXP)
2857 .Case("athlon-mp", CK_AthlonMP)
2858 .Case("athlon64", CK_Athlon64)
2859 .Case("athlon64-sse3", CK_Athlon64SSE3)
2860 .Case("athlon-fx", CK_AthlonFX)
2862 .Case("k8-sse3", CK_K8SSE3)
2863 .Case("opteron", CK_Opteron)
2864 .Case("opteron-sse3", CK_OpteronSSE3)
2865 .Case("barcelona", CK_AMDFAM10)
2866 .Case("amdfam10", CK_AMDFAM10)
2867 .Case("btver1", CK_BTVER1)
2868 .Case("btver2", CK_BTVER2)
2869 .Case("bdver1", CK_BDVER1)
2870 .Case("bdver2", CK_BDVER2)
2871 .Case("bdver3", CK_BDVER3)
2872 .Case("bdver4", CK_BDVER4)
2873 .Case("znver1", CK_ZNVER1)
2874 .Case("x86-64", CK_x86_64)
2875 .Case("geode", CK_Geode)
2876 .Default(CK_Generic);
2883 } FPMath = FP_Default;
2886 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
2887 : TargetInfo(Triple) {
2888 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
2890 unsigned getFloatEvalMethod() const override {
2891 // X87 evaluates with 80 bits "long double" precision.
2892 return SSELevel == NoSSE ? 2 : 0;
2894 ArrayRef<const char *> getGCCRegNames() const override {
2895 return llvm::makeArrayRef(GCCRegNames);
2897 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2900 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
2901 return llvm::makeArrayRef(AddlRegNames);
2903 bool validateCpuSupports(StringRef Name) const override;
2904 bool validateAsmConstraint(const char *&Name,
2905 TargetInfo::ConstraintInfo &info) const override;
2907 bool validateGlobalRegisterVariable(StringRef RegName,
2909 bool &HasSizeMismatch) const override {
2910 // esp and ebp are the only 32-bit registers the x86 backend can currently
2912 if (RegName.equals("esp") || RegName.equals("ebp")) {
2913 // Check that the register size is 32-bit.
2914 HasSizeMismatch = RegSize != 32;
2921 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2923 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2925 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2927 std::string convertConstraint(const char *&Constraint) const override;
2928 const char *getClobbers() const override {
2929 return "~{dirflag},~{fpsr},~{flags}";
2932 StringRef getConstraintRegister(const StringRef &Constraint,
2933 const StringRef &Expression) const override {
2934 StringRef::iterator I, E;
2935 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) {
2942 // For the register constraints, return the matching register name
2955 // In case the constraint is 'r' we need to return Expression
2959 // Default value if there is no constraint for the register
2965 void getTargetDefines(const LangOptions &Opts,
2966 MacroBuilder &Builder) const override;
2967 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2969 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2971 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2973 void setFeatureEnabled(llvm::StringMap<bool> &Features,
2974 StringRef Name, bool Enabled) const override {
2975 setFeatureEnabledImpl(Features, Name, Enabled);
2977 // This exists purely to cut down on the number of virtual calls in
2978 // initFeatureMap which calls this repeatedly.
2979 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2980 StringRef Name, bool Enabled);
2982 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
2984 const std::vector<std::string> &FeaturesVec) const override;
2985 bool hasFeature(StringRef Feature) const override;
2986 bool handleTargetFeatures(std::vector<std::string> &Features,
2987 DiagnosticsEngine &Diags) override;
2988 StringRef getABI() const override {
2989 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
2991 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2993 if (getTriple().getArch() == llvm::Triple::x86 &&
2994 MMX3DNowLevel == NoMMX3DNow)
2998 bool setCPU(const std::string &Name) override {
2999 CPU = getCPUKind(Name);
3001 // Perform any per-CPU checks necessary to determine if this CPU is
3003 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
3004 // invalid without explaining *why*.
3007 // No processor selected!
3034 case CK_AthlonThunderbird:
3039 // Only accept certain architectures when compiling in 32-bit mode.
3040 if (getTriple().getArch() != llvm::Triple::x86)
3051 case CK_SandyBridge:
3055 case CK_SkylakeClient:
3056 case CK_SkylakeServer:
3060 case CK_Athlon64SSE3:
3065 case CK_OpteronSSE3:
3077 llvm_unreachable("Unhandled CPU kind");
3080 bool setFPMath(StringRef Name) override;
3082 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3083 // Most of the non-ARM calling conventions are i386 conventions.
3085 case CC_X86ThisCall:
3086 case CC_X86FastCall:
3088 case CC_X86VectorCall:
3093 case CC_IntelOclBicc:
3096 return CCCR_Warning;
3100 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3101 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
3104 bool hasSjLjLowering() const override {
3108 void setSupportedOpenCLOpts() override {
3109 getSupportedOpenCLOpts().supportAll();
3113 bool X86TargetInfo::setFPMath(StringRef Name) {
3114 if (Name == "387") {
3118 if (Name == "sse") {
3125 bool X86TargetInfo::initFeatureMap(
3126 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
3127 const std::vector<std::string> &FeaturesVec) const {
3128 // FIXME: This *really* should not be here.
3129 // X86_64 always has SSE2.
3130 if (getTriple().getArch() == llvm::Triple::x86_64)
3131 setFeatureEnabledImpl(Features, "sse2", true);
3133 const CPUKind Kind = getCPUKind(CPU);
3135 // Enable X87 for all X86 processors but Lakemont.
3136 if (Kind != CK_Lakemont)
3137 setFeatureEnabledImpl(Features, "x87", true);
3153 setFeatureEnabledImpl(Features, "mmx", true);
3158 setFeatureEnabledImpl(Features, "sse", true);
3159 setFeatureEnabledImpl(Features, "fxsr", true);
3165 setFeatureEnabledImpl(Features, "sse2", true);
3166 setFeatureEnabledImpl(Features, "fxsr", true);
3171 setFeatureEnabledImpl(Features, "sse3", true);
3172 setFeatureEnabledImpl(Features, "fxsr", true);
3173 setFeatureEnabledImpl(Features, "cx16", true);
3177 setFeatureEnabledImpl(Features, "ssse3", true);
3178 setFeatureEnabledImpl(Features, "fxsr", true);
3179 setFeatureEnabledImpl(Features, "cx16", true);
3182 setFeatureEnabledImpl(Features, "sse4.1", true);
3183 setFeatureEnabledImpl(Features, "fxsr", true);
3184 setFeatureEnabledImpl(Features, "cx16", true);
3187 setFeatureEnabledImpl(Features, "avx512ifma", true);
3188 setFeatureEnabledImpl(Features, "avx512vbmi", true);
3189 setFeatureEnabledImpl(Features, "sha", true);
3191 case CK_SkylakeServer:
3192 setFeatureEnabledImpl(Features, "avx512f", true);
3193 setFeatureEnabledImpl(Features, "avx512cd", true);
3194 setFeatureEnabledImpl(Features, "avx512dq", true);
3195 setFeatureEnabledImpl(Features, "avx512bw", true);
3196 setFeatureEnabledImpl(Features, "avx512vl", true);
3197 setFeatureEnabledImpl(Features, "pku", true);
3198 setFeatureEnabledImpl(Features, "clwb", true);
3200 case CK_SkylakeClient:
3201 setFeatureEnabledImpl(Features, "xsavec", true);
3202 setFeatureEnabledImpl(Features, "xsaves", true);
3203 setFeatureEnabledImpl(Features, "mpx", true);
3204 setFeatureEnabledImpl(Features, "sgx", true);
3205 setFeatureEnabledImpl(Features, "clflushopt", true);
3206 setFeatureEnabledImpl(Features, "rtm", true);
3209 setFeatureEnabledImpl(Features, "rdseed", true);
3210 setFeatureEnabledImpl(Features, "adx", true);
3213 setFeatureEnabledImpl(Features, "avx2", true);
3214 setFeatureEnabledImpl(Features, "lzcnt", true);
3215 setFeatureEnabledImpl(Features, "bmi", true);
3216 setFeatureEnabledImpl(Features, "bmi2", true);
3217 setFeatureEnabledImpl(Features, "fma", true);
3218 setFeatureEnabledImpl(Features, "movbe", true);
3221 setFeatureEnabledImpl(Features, "rdrnd", true);
3222 setFeatureEnabledImpl(Features, "f16c", true);
3223 setFeatureEnabledImpl(Features, "fsgsbase", true);
3225 case CK_SandyBridge:
3226 setFeatureEnabledImpl(Features, "avx", true);
3227 setFeatureEnabledImpl(Features, "xsave", true);
3228 setFeatureEnabledImpl(Features, "xsaveopt", true);
3232 setFeatureEnabledImpl(Features, "aes", true);
3233 setFeatureEnabledImpl(Features, "pclmul", true);
3236 setFeatureEnabledImpl(Features, "sse4.2", true);
3237 setFeatureEnabledImpl(Features, "fxsr", true);
3238 setFeatureEnabledImpl(Features, "cx16", true);
3241 setFeatureEnabledImpl(Features, "avx512f", true);
3242 setFeatureEnabledImpl(Features, "avx512cd", true);
3243 setFeatureEnabledImpl(Features, "avx512er", true);
3244 setFeatureEnabledImpl(Features, "avx512pf", true);
3245 setFeatureEnabledImpl(Features, "prefetchwt1", true);
3246 setFeatureEnabledImpl(Features, "fxsr", true);
3247 setFeatureEnabledImpl(Features, "rdseed", true);
3248 setFeatureEnabledImpl(Features, "adx", true);
3249 setFeatureEnabledImpl(Features, "lzcnt", true);
3250 setFeatureEnabledImpl(Features, "bmi", true);
3251 setFeatureEnabledImpl(Features, "bmi2", true);
3252 setFeatureEnabledImpl(Features, "rtm", true);
3253 setFeatureEnabledImpl(Features, "fma", true);
3254 setFeatureEnabledImpl(Features, "rdrnd", true);
3255 setFeatureEnabledImpl(Features, "f16c", true);
3256 setFeatureEnabledImpl(Features, "fsgsbase", true);
3257 setFeatureEnabledImpl(Features, "aes", true);
3258 setFeatureEnabledImpl(Features, "pclmul", true);
3259 setFeatureEnabledImpl(Features, "cx16", true);
3260 setFeatureEnabledImpl(Features, "xsaveopt", true);
3261 setFeatureEnabledImpl(Features, "xsave", true);
3262 setFeatureEnabledImpl(Features, "movbe", true);
3268 setFeatureEnabledImpl(Features, "3dnow", true);
3271 case CK_AthlonThunderbird:
3273 setFeatureEnabledImpl(Features, "3dnowa", true);
3278 setFeatureEnabledImpl(Features, "sse", true);
3279 setFeatureEnabledImpl(Features, "3dnowa", true);
3280 setFeatureEnabledImpl(Features, "fxsr", true);
3286 setFeatureEnabledImpl(Features, "sse2", true);
3287 setFeatureEnabledImpl(Features, "3dnowa", true);
3288 setFeatureEnabledImpl(Features, "fxsr", true);
3291 setFeatureEnabledImpl(Features, "sse4a", true);
3292 setFeatureEnabledImpl(Features, "lzcnt", true);
3293 setFeatureEnabledImpl(Features, "popcnt", true);
3296 case CK_OpteronSSE3:
3297 case CK_Athlon64SSE3:
3298 setFeatureEnabledImpl(Features, "sse3", true);
3299 setFeatureEnabledImpl(Features, "3dnowa", true);
3300 setFeatureEnabledImpl(Features, "fxsr", true);
3303 setFeatureEnabledImpl(Features, "avx", true);
3304 setFeatureEnabledImpl(Features, "aes", true);
3305 setFeatureEnabledImpl(Features, "pclmul", true);
3306 setFeatureEnabledImpl(Features, "bmi", true);
3307 setFeatureEnabledImpl(Features, "f16c", true);
3308 setFeatureEnabledImpl(Features, "xsaveopt", true);
3311 setFeatureEnabledImpl(Features, "ssse3", true);
3312 setFeatureEnabledImpl(Features, "sse4a", true);
3313 setFeatureEnabledImpl(Features, "lzcnt", true);
3314 setFeatureEnabledImpl(Features, "popcnt", true);
3315 setFeatureEnabledImpl(Features, "prfchw", true);
3316 setFeatureEnabledImpl(Features, "cx16", true);
3317 setFeatureEnabledImpl(Features, "fxsr", true);
3320 setFeatureEnabledImpl(Features, "adx", true);
3321 setFeatureEnabledImpl(Features, "aes", true);
3322 setFeatureEnabledImpl(Features, "avx2", true);
3323 setFeatureEnabledImpl(Features, "bmi", true);
3324 setFeatureEnabledImpl(Features, "bmi2", true);
3325 setFeatureEnabledImpl(Features, "clflushopt", true);
3326 setFeatureEnabledImpl(Features, "clzero", true);
3327 setFeatureEnabledImpl(Features, "cx16", true);
3328 setFeatureEnabledImpl(Features, "f16c", true);
3329 setFeatureEnabledImpl(Features, "fma", true);
3330 setFeatureEnabledImpl(Features, "fsgsbase", true);
3331 setFeatureEnabledImpl(Features, "fxsr", true);
3332 setFeatureEnabledImpl(Features, "lzcnt", true);
3333 setFeatureEnabledImpl(Features, "mwaitx", true);
3334 setFeatureEnabledImpl(Features, "movbe", true);
3335 setFeatureEnabledImpl(Features, "pclmul", true);
3336 setFeatureEnabledImpl(Features, "popcnt", true);
3337 setFeatureEnabledImpl(Features, "prfchw", true);
3338 setFeatureEnabledImpl(Features, "rdrnd", true);
3339 setFeatureEnabledImpl(Features, "rdseed", true);
3340 setFeatureEnabledImpl(Features, "sha", true);
3341 setFeatureEnabledImpl(Features, "sse4a", true);
3342 setFeatureEnabledImpl(Features, "xsave", true);
3343 setFeatureEnabledImpl(Features, "xsavec", true);
3344 setFeatureEnabledImpl(Features, "xsaveopt", true);
3345 setFeatureEnabledImpl(Features, "xsaves", true);
3348 setFeatureEnabledImpl(Features, "avx2", true);
3349 setFeatureEnabledImpl(Features, "bmi2", true);
3350 setFeatureEnabledImpl(Features, "mwaitx", true);
3353 setFeatureEnabledImpl(Features, "fsgsbase", true);
3354 setFeatureEnabledImpl(Features, "xsaveopt", true);
3357 setFeatureEnabledImpl(Features, "bmi", true);
3358 setFeatureEnabledImpl(Features, "fma", true);
3359 setFeatureEnabledImpl(Features, "f16c", true);
3360 setFeatureEnabledImpl(Features, "tbm", true);
3363 // xop implies avx, sse4a and fma4.
3364 setFeatureEnabledImpl(Features, "xop", true);
3365 setFeatureEnabledImpl(Features, "lzcnt", true);
3366 setFeatureEnabledImpl(Features, "aes", true);
3367 setFeatureEnabledImpl(Features, "pclmul", true);
3368 setFeatureEnabledImpl(Features, "prfchw", true);
3369 setFeatureEnabledImpl(Features, "cx16", true);
3370 setFeatureEnabledImpl(Features, "fxsr", true);
3371 setFeatureEnabledImpl(Features, "xsave", true);
3374 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
3377 // Can't do this earlier because we need to be able to explicitly enable
3378 // or disable these features and the things that they depend upon.
3380 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
3381 auto I = Features.find("sse4.2");
3382 if (I != Features.end() && I->getValue() &&
3383 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
3385 Features["popcnt"] = true;
3387 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
3388 I = Features.find("3dnow");
3389 if (I != Features.end() && I->getValue() &&
3390 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
3392 Features["prfchw"] = true;
3394 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
3396 I = Features.find("sse");
3397 if (I != Features.end() && I->getValue() &&
3398 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
3400 Features["mmx"] = true;
3405 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
3406 X86SSEEnum Level, bool Enabled) {
3410 Features["avx512f"] = true;
3412 Features["avx2"] = true;
3414 Features["avx"] = true;
3415 Features["xsave"] = true;
3417 Features["sse4.2"] = true;
3419 Features["sse4.1"] = true;
3421 Features["ssse3"] = true;
3423 Features["sse3"] = true;
3425 Features["sse2"] = true;
3427 Features["sse"] = true;
3437 Features["sse"] = false;
3439 Features["sse2"] = Features["pclmul"] = Features["aes"] =
3440 Features["sha"] = false;
3442 Features["sse3"] = false;
3443 setXOPLevel(Features, NoXOP, false);
3445 Features["ssse3"] = false;
3447 Features["sse4.1"] = false;
3449 Features["sse4.2"] = false;
3451 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
3452 Features["xsaveopt"] = false;
3453 setXOPLevel(Features, FMA4, false);
3455 Features["avx2"] = false;
3457 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
3458 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
3459 Features["avx512vl"] = Features["avx512vbmi"] =
3460 Features["avx512ifma"] = false;
3464 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
3465 MMX3DNowEnum Level, bool Enabled) {
3468 case AMD3DNowAthlon:
3469 Features["3dnowa"] = true;
3471 Features["3dnow"] = true;
3473 Features["mmx"] = true;
3483 Features["mmx"] = false;
3485 Features["3dnow"] = false;
3486 case AMD3DNowAthlon:
3487 Features["3dnowa"] = false;
3491 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
3496 Features["xop"] = true;
3498 Features["fma4"] = true;
3499 setSSELevel(Features, AVX, true);
3501 Features["sse4a"] = true;
3502 setSSELevel(Features, SSE3, true);
3512 Features["sse4a"] = false;
3514 Features["fma4"] = false;
3516 Features["xop"] = false;
3520 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
3521 StringRef Name, bool Enabled) {
3522 // This is a bit of a hack to deal with the sse4 target feature when used
3523 // as part of the target attribute. We handle sse4 correctly everywhere
3524 // else. See below for more information on how we handle the sse4 options.
3526 Features[Name] = Enabled;
3528 if (Name == "mmx") {
3529 setMMXLevel(Features, MMX, Enabled);
3530 } else if (Name == "sse") {
3531 setSSELevel(Features, SSE1, Enabled);
3532 } else if (Name == "sse2") {
3533 setSSELevel(Features, SSE2, Enabled);
3534 } else if (Name == "sse3") {
3535 setSSELevel(Features, SSE3, Enabled);
3536 } else if (Name == "ssse3") {
3537 setSSELevel(Features, SSSE3, Enabled);
3538 } else if (Name == "sse4.2") {
3539 setSSELevel(Features, SSE42, Enabled);
3540 } else if (Name == "sse4.1") {
3541 setSSELevel(Features, SSE41, Enabled);
3542 } else if (Name == "3dnow") {
3543 setMMXLevel(Features, AMD3DNow, Enabled);
3544 } else if (Name == "3dnowa") {
3545 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
3546 } else if (Name == "aes") {
3548 setSSELevel(Features, SSE2, Enabled);
3549 } else if (Name == "pclmul") {
3551 setSSELevel(Features, SSE2, Enabled);
3552 } else if (Name == "avx") {
3553 setSSELevel(Features, AVX, Enabled);
3554 } else if (Name == "avx2") {
3555 setSSELevel(Features, AVX2, Enabled);
3556 } else if (Name == "avx512f") {
3557 setSSELevel(Features, AVX512F, Enabled);
3558 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
3559 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
3560 Name == "avx512vbmi" || Name == "avx512ifma") {
3562 setSSELevel(Features, AVX512F, Enabled);
3563 // Enable BWI instruction if VBMI is being enabled.
3564 if (Name == "avx512vbmi" && Enabled)
3565 Features["avx512bw"] = true;
3566 // Also disable VBMI if BWI is being disabled.
3567 if (Name == "avx512bw" && !Enabled)
3568 Features["avx512vbmi"] = false;
3569 } else if (Name == "fma") {
3571 setSSELevel(Features, AVX, Enabled);
3572 } else if (Name == "fma4") {
3573 setXOPLevel(Features, FMA4, Enabled);
3574 } else if (Name == "xop") {
3575 setXOPLevel(Features, XOP, Enabled);
3576 } else if (Name == "sse4a") {
3577 setXOPLevel(Features, SSE4A, Enabled);
3578 } else if (Name == "f16c") {
3580 setSSELevel(Features, AVX, Enabled);
3581 } else if (Name == "sha") {
3583 setSSELevel(Features, SSE2, Enabled);
3584 } else if (Name == "sse4") {
3585 // We can get here via the __target__ attribute since that's not controlled
3586 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
3587 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
3590 setSSELevel(Features, SSE42, Enabled);
3592 setSSELevel(Features, SSE41, Enabled);
3593 } else if (Name == "xsave") {
3595 Features["xsaveopt"] = false;
3596 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
3598 Features["xsave"] = true;
3602 /// handleTargetFeatures - Perform initialization based on the user
3603 /// configured set of features.
3604 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
3605 DiagnosticsEngine &Diags) {
3606 for (const auto &Feature : Features) {
3607 if (Feature[0] != '+')
3610 if (Feature == "+aes") {
3612 } else if (Feature == "+pclmul") {
3614 } else if (Feature == "+lzcnt") {
3616 } else if (Feature == "+rdrnd") {
3618 } else if (Feature == "+fsgsbase") {
3620 } else if (Feature == "+bmi") {
3622 } else if (Feature == "+bmi2") {
3624 } else if (Feature == "+popcnt") {
3626 } else if (Feature == "+rtm") {
3628 } else if (Feature == "+prfchw") {
3630 } else if (Feature == "+rdseed") {
3632 } else if (Feature == "+adx") {
3634 } else if (Feature == "+tbm") {
3636 } else if (Feature == "+fma") {
3638 } else if (Feature == "+f16c") {
3640 } else if (Feature == "+avx512cd") {
3642 } else if (Feature == "+avx512er") {
3644 } else if (Feature == "+avx512pf") {
3646 } else if (Feature == "+avx512dq") {
3648 } else if (Feature == "+avx512bw") {
3650 } else if (Feature == "+avx512vl") {
3652 } else if (Feature == "+avx512vbmi") {
3653 HasAVX512VBMI = true;
3654 } else if (Feature == "+avx512ifma") {
3655 HasAVX512IFMA = true;
3656 } else if (Feature == "+sha") {
3658 } else if (Feature == "+mpx") {
3660 } else if (Feature == "+movbe") {
3662 } else if (Feature == "+sgx") {
3664 } else if (Feature == "+cx16") {
3666 } else if (Feature == "+fxsr") {
3668 } else if (Feature == "+xsave") {
3670 } else if (Feature == "+xsaveopt") {
3672 } else if (Feature == "+xsavec") {
3674 } else if (Feature == "+xsaves") {
3676 } else if (Feature == "+mwaitx") {
3678 } else if (Feature == "+pku") {
3680 } else if (Feature == "+clflushopt") {
3681 HasCLFLUSHOPT = true;
3682 } else if (Feature == "+clwb") {
3684 } else if (Feature == "+prefetchwt1") {
3685 HasPREFETCHWT1 = true;
3686 } else if (Feature == "+clzero") {
3690 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
3691 .Case("+avx512f", AVX512F)
3692 .Case("+avx2", AVX2)
3694 .Case("+sse4.2", SSE42)
3695 .Case("+sse4.1", SSE41)
3696 .Case("+ssse3", SSSE3)
3697 .Case("+sse3", SSE3)
3698 .Case("+sse2", SSE2)
3701 SSELevel = std::max(SSELevel, Level);
3703 MMX3DNowEnum ThreeDNowLevel =
3704 llvm::StringSwitch<MMX3DNowEnum>(Feature)
3705 .Case("+3dnowa", AMD3DNowAthlon)
3706 .Case("+3dnow", AMD3DNow)
3708 .Default(NoMMX3DNow);
3709 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
3711 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
3713 .Case("+fma4", FMA4)
3714 .Case("+sse4a", SSE4A)
3716 XOPLevel = std::max(XOPLevel, XLevel);
3719 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
3720 // matches the selected sse level.
3721 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
3722 (FPMath == FP_387 && SSELevel >= SSE1)) {
3723 Diags.Report(diag::err_target_unsupported_fpmath) <<
3724 (FPMath == FP_SSE ? "sse" : "387");
3729 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3733 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
3734 /// definitions for this particular subtarget.
3735 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
3736 MacroBuilder &Builder) const {
3737 // Target identification.
3738 if (getTriple().getArch() == llvm::Triple::x86_64) {
3739 Builder.defineMacro("__amd64__");
3740 Builder.defineMacro("__amd64");
3741 Builder.defineMacro("__x86_64");
3742 Builder.defineMacro("__x86_64__");
3743 if (getTriple().getArchName() == "x86_64h") {
3744 Builder.defineMacro("__x86_64h");
3745 Builder.defineMacro("__x86_64h__");
3748 DefineStd(Builder, "i386", Opts);
3751 // Subtarget options.
3752 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
3753 // truly should be based on -mtune options.
3758 // The rest are coming from the i386 define above.
3759 Builder.defineMacro("__tune_i386__");
3765 defineCPUMacros(Builder, "i486");
3768 Builder.defineMacro("__pentium_mmx__");
3769 Builder.defineMacro("__tune_pentium_mmx__");
3773 defineCPUMacros(Builder, "i586");
3774 defineCPUMacros(Builder, "pentium");
3779 Builder.defineMacro("__tune_pentium3__");
3783 Builder.defineMacro("__tune_pentium2__");
3786 Builder.defineMacro("__tune_i686__");
3787 Builder.defineMacro("__tune_pentiumpro__");
3790 Builder.defineMacro("__i686");
3791 Builder.defineMacro("__i686__");
3792 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3793 Builder.defineMacro("__pentiumpro");
3794 Builder.defineMacro("__pentiumpro__");
3798 defineCPUMacros(Builder, "pentium4");
3803 defineCPUMacros(Builder, "nocona");
3807 defineCPUMacros(Builder, "core2");
3810 defineCPUMacros(Builder, "atom");
3813 defineCPUMacros(Builder, "slm");
3817 case CK_SandyBridge:
3821 case CK_SkylakeClient:
3822 // FIXME: Historically, we defined this legacy name, it would be nice to
3823 // remove it at some point. We've never exposed fine-grained names for
3824 // recent primary x86 CPUs, and we should keep it that way.
3825 defineCPUMacros(Builder, "corei7");
3827 case CK_SkylakeServer:
3828 defineCPUMacros(Builder, "skx");
3833 defineCPUMacros(Builder, "knl");
3836 Builder.defineMacro("__tune_lakemont__");
3839 Builder.defineMacro("__k6_2__");
3840 Builder.defineMacro("__tune_k6_2__");
3843 if (CPU != CK_K6_2) { // In case of fallthrough
3844 // FIXME: GCC may be enabling these in cases where some other k6
3845 // architecture is specified but -m3dnow is explicitly provided. The
3846 // exact semantics need to be determined and emulated here.
3847 Builder.defineMacro("__k6_3__");
3848 Builder.defineMacro("__tune_k6_3__");
3852 defineCPUMacros(Builder, "k6");
3855 case CK_AthlonThunderbird:
3859 defineCPUMacros(Builder, "athlon");
3860 if (SSELevel != NoSSE) {
3861 Builder.defineMacro("__athlon_sse__");
3862 Builder.defineMacro("__tune_athlon_sse__");
3869 case CK_OpteronSSE3:
3871 case CK_Athlon64SSE3:
3873 defineCPUMacros(Builder, "k8");
3876 defineCPUMacros(Builder, "amdfam10");
3879 defineCPUMacros(Builder, "btver1");
3882 defineCPUMacros(Builder, "btver2");
3885 defineCPUMacros(Builder, "bdver1");
3888 defineCPUMacros(Builder, "bdver2");
3891 defineCPUMacros(Builder, "bdver3");
3894 defineCPUMacros(Builder, "bdver4");
3897 defineCPUMacros(Builder, "znver1");
3900 defineCPUMacros(Builder, "geode");
3904 // Target properties.
3905 Builder.defineMacro("__REGISTER_PREFIX__", "");
3907 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3908 // functions in glibc header files that use FP Stack inline asm which the
3909 // backend can't deal with (PR879).
3910 Builder.defineMacro("__NO_MATH_INLINES");
3913 Builder.defineMacro("__AES__");
3916 Builder.defineMacro("__PCLMUL__");
3919 Builder.defineMacro("__LZCNT__");
3922 Builder.defineMacro("__RDRND__");
3925 Builder.defineMacro("__FSGSBASE__");
3928 Builder.defineMacro("__BMI__");
3931 Builder.defineMacro("__BMI2__");
3934 Builder.defineMacro("__POPCNT__");
3937 Builder.defineMacro("__RTM__");
3940 Builder.defineMacro("__PRFCHW__");
3943 Builder.defineMacro("__RDSEED__");
3946 Builder.defineMacro("__ADX__");
3949 Builder.defineMacro("__TBM__");
3952 Builder.defineMacro("__MWAITX__");
3956 Builder.defineMacro("__XOP__");
3958 Builder.defineMacro("__FMA4__");
3960 Builder.defineMacro("__SSE4A__");
3966 Builder.defineMacro("__FMA__");
3969 Builder.defineMacro("__F16C__");
3972 Builder.defineMacro("__AVX512CD__");
3974 Builder.defineMacro("__AVX512ER__");
3976 Builder.defineMacro("__AVX512PF__");
3978 Builder.defineMacro("__AVX512DQ__");
3980 Builder.defineMacro("__AVX512BW__");
3982 Builder.defineMacro("__AVX512VL__");
3984 Builder.defineMacro("__AVX512VBMI__");
3986 Builder.defineMacro("__AVX512IFMA__");
3989 Builder.defineMacro("__SHA__");
3992 Builder.defineMacro("__FXSR__");
3994 Builder.defineMacro("__XSAVE__");
3996 Builder.defineMacro("__XSAVEOPT__");
3998 Builder.defineMacro("__XSAVEC__");
4000 Builder.defineMacro("__XSAVES__");
4002 Builder.defineMacro("__PKU__");
4004 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
4006 Builder.defineMacro("__CLFLUSHOPT__");
4008 Builder.defineMacro("__CLWB__");
4010 Builder.defineMacro("__MPX__");
4012 Builder.defineMacro("__SGX__");
4014 Builder.defineMacro("__PREFETCHWT1__");
4016 Builder.defineMacro("__CLZERO__");
4018 // Each case falls through to the previous one here.
4021 Builder.defineMacro("__AVX512F__");
4023 Builder.defineMacro("__AVX2__");
4025 Builder.defineMacro("__AVX__");
4027 Builder.defineMacro("__SSE4_2__");
4029 Builder.defineMacro("__SSE4_1__");
4031 Builder.defineMacro("__SSSE3__");
4033 Builder.defineMacro("__SSE3__");
4035 Builder.defineMacro("__SSE2__");
4036 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
4038 Builder.defineMacro("__SSE__");
4039 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
4044 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
4054 Builder.defineMacro("_M_IX86_FP", Twine(2));
4057 Builder.defineMacro("_M_IX86_FP", Twine(1));
4060 Builder.defineMacro("_M_IX86_FP", Twine(0));
4064 // Each case falls through to the previous one here.
4065 switch (MMX3DNowLevel) {
4066 case AMD3DNowAthlon:
4067 Builder.defineMacro("__3dNOW_A__");
4069 Builder.defineMacro("__3dNOW__");
4071 Builder.defineMacro("__MMX__");
4076 if (CPU >= CK_i486) {
4077 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4078 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4079 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4082 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4085 bool X86TargetInfo::hasFeature(StringRef Feature) const {
4086 return llvm::StringSwitch<bool>(Feature)
4087 .Case("aes", HasAES)
4088 .Case("avx", SSELevel >= AVX)
4089 .Case("avx2", SSELevel >= AVX2)
4090 .Case("avx512f", SSELevel >= AVX512F)
4091 .Case("avx512cd", HasAVX512CD)
4092 .Case("avx512er", HasAVX512ER)
4093 .Case("avx512pf", HasAVX512PF)
4094 .Case("avx512dq", HasAVX512DQ)
4095 .Case("avx512bw", HasAVX512BW)
4096 .Case("avx512vl", HasAVX512VL)
4097 .Case("avx512vbmi", HasAVX512VBMI)
4098 .Case("avx512ifma", HasAVX512IFMA)
4099 .Case("bmi", HasBMI)
4100 .Case("bmi2", HasBMI2)
4101 .Case("clflushopt", HasCLFLUSHOPT)
4102 .Case("clwb", HasCLWB)
4103 .Case("clzero", HasCLZERO)
4104 .Case("cx16", HasCX16)
4105 .Case("f16c", HasF16C)
4106 .Case("fma", HasFMA)
4107 .Case("fma4", XOPLevel >= FMA4)
4108 .Case("fsgsbase", HasFSGSBASE)
4109 .Case("fxsr", HasFXSR)
4110 .Case("lzcnt", HasLZCNT)
4111 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
4112 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
4113 .Case("mmx", MMX3DNowLevel >= MMX)
4114 .Case("movbe", HasMOVBE)
4115 .Case("mpx", HasMPX)
4116 .Case("pclmul", HasPCLMUL)
4117 .Case("pku", HasPKU)
4118 .Case("popcnt", HasPOPCNT)
4119 .Case("prefetchwt1", HasPREFETCHWT1)
4120 .Case("prfchw", HasPRFCHW)
4121 .Case("rdrnd", HasRDRND)
4122 .Case("rdseed", HasRDSEED)
4123 .Case("rtm", HasRTM)
4124 .Case("sgx", HasSGX)
4125 .Case("sha", HasSHA)
4126 .Case("sse", SSELevel >= SSE1)
4127 .Case("sse2", SSELevel >= SSE2)
4128 .Case("sse3", SSELevel >= SSE3)
4129 .Case("ssse3", SSELevel >= SSSE3)
4130 .Case("sse4.1", SSELevel >= SSE41)
4131 .Case("sse4.2", SSELevel >= SSE42)
4132 .Case("sse4a", XOPLevel >= SSE4A)
4133 .Case("tbm", HasTBM)
4135 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
4136 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
4137 .Case("xop", XOPLevel >= XOP)
4138 .Case("xsave", HasXSAVE)
4139 .Case("xsavec", HasXSAVEC)
4140 .Case("xsaves", HasXSAVES)
4141 .Case("xsaveopt", HasXSAVEOPT)
4145 // We can't use a generic validation scheme for the features accepted here
4146 // versus subtarget features accepted in the target attribute because the
4147 // bitfield structure that's initialized in the runtime only supports the
4148 // below currently rather than the full range of subtarget features. (See
4149 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
4150 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
4151 return llvm::StringSwitch<bool>(FeatureStr)
4154 .Case("popcnt", true)
4158 .Case("ssse3", true)
4159 .Case("sse4.1", true)
4160 .Case("sse4.2", true)
4163 .Case("sse4a", true)
4167 .Case("avx512f", true)
4171 .Case("pclmul", true)
4172 .Case("avx512vl", true)
4173 .Case("avx512bw", true)
4174 .Case("avx512dq", true)
4175 .Case("avx512cd", true)
4176 .Case("avx512er", true)
4177 .Case("avx512pf", true)
4178 .Case("avx512vbmi", true)
4179 .Case("avx512ifma", true)
4184 X86TargetInfo::validateAsmConstraint(const char *&Name,
4185 TargetInfo::ConstraintInfo &Info) const {
4187 default: return false;
4188 // Constant constraints.
4189 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
4191 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
4192 // x86_64 instructions.
4194 Info.setRequiresImmediate();
4197 Info.setRequiresImmediate(0, 31);
4200 Info.setRequiresImmediate(0, 63);
4203 Info.setRequiresImmediate(-128, 127);
4206 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) });
4209 Info.setRequiresImmediate(0, 3);
4212 Info.setRequiresImmediate(0, 255);
4215 Info.setRequiresImmediate(0, 127);
4217 // Register constraints.
4218 case 'Y': // 'Y' is the first character for several 2-character constraints.
4219 // Shift the pointer to the second character of the constraint.
4224 case '0': // First SSE register.
4225 case 't': // Any SSE register, when SSE2 is enabled.
4226 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
4227 case 'm': // Any MMX register, when inter-unit moves enabled.
4228 case 'k': // AVX512 arch mask registers: k1-k7.
4229 Info.setAllowsRegister();
4232 case 'f': // Any x87 floating point stack register.
4233 // Constraint 'f' cannot be used for output operands.
4234 if (Info.ConstraintStr[0] == '=')
4236 Info.setAllowsRegister();
4244 case 'A': // edx:eax.
4245 case 't': // Top of floating point stack.
4246 case 'u': // Second from top of floating point stack.
4247 case 'q': // Any register accessible as [r]l: a, b, c, and d.
4248 case 'y': // Any MMX register.
4249 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
4250 case 'x': // Any SSE register.
4251 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0
4252 // for intermideate k reg operations).
4253 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
4254 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
4255 case 'l': // "Index" registers: any general register that can be used as an
4256 // index in a base+index memory access.
4257 Info.setAllowsRegister();
4259 // Floating point constant constraints.
4260 case 'C': // SSE floating point constant.
4261 case 'G': // x87 floating point constant.
4266 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
4267 unsigned Size) const {
4268 // Strip off constraint modifiers.
4269 while (Constraint[0] == '=' ||
4270 Constraint[0] == '+' ||
4271 Constraint[0] == '&')
4272 Constraint = Constraint.substr(1);
4274 return validateOperandSize(Constraint, Size);
4277 bool X86TargetInfo::validateInputSize(StringRef Constraint,
4278 unsigned Size) const {
4279 return validateOperandSize(Constraint, Size);
4282 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
4283 unsigned Size) const {
4284 switch (Constraint[0]) {
4287 // Registers k0-k7 (AVX512) size limit is 64 bit.
4296 if (SSELevel >= AVX512F)
4297 // 512-bit zmm registers can be used if target supports AVX512F.
4298 return Size <= 512U;
4299 else if (SSELevel >= AVX)
4300 // 256-bit ymm registers can be used if target supports AVX.
4301 return Size <= 256U;
4302 return Size <= 128U;
4304 // 'Y' is the first character for several 2-character constraints.
4305 switch (Constraint[1]) {
4308 // 'Ym' is synonymous with 'y'.
4313 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
4314 if (SSELevel >= AVX512F)
4315 return Size <= 512U;
4316 else if (SSELevel >= AVX)
4317 return Size <= 256U;
4318 return SSELevel >= SSE2 && Size <= 128U;
4327 X86TargetInfo::convertConstraint(const char *&Constraint) const {
4328 switch (*Constraint) {
4329 case 'a': return std::string("{ax}");
4330 case 'b': return std::string("{bx}");
4331 case 'c': return std::string("{cx}");
4332 case 'd': return std::string("{dx}");
4333 case 'S': return std::string("{si}");
4334 case 'D': return std::string("{di}");
4335 case 'p': // address
4336 return std::string("im");
4337 case 't': // top of floating point stack.
4338 return std::string("{st}");
4339 case 'u': // second from top of floating point stack.
4340 return std::string("{st(1)}"); // second from top of floating point stack.
4342 switch (Constraint[1]) {
4344 // Break from inner switch and fall through (copy single char),
4345 // continue parsing after copying the current constraint into
4346 // the return string.
4349 // "^" hints llvm that this is a 2 letter constraint.
4350 // "Constraint++" is used to promote the string iterator
4351 // to the next constraint.
4352 return std::string("^") + std::string(Constraint++, 2);
4356 return std::string(1, *Constraint);
4360 // X86-32 generic target
4361 class X86_32TargetInfo : public X86TargetInfo {
4363 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4364 : X86TargetInfo(Triple, Opts) {
4365 DoubleAlign = LongLongAlign = 32;
4366 LongDoubleWidth = 96;
4367 LongDoubleAlign = 32;
4368 SuitableAlign = 128;
4369 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128");
4370 SizeType = UnsignedInt;
4371 PtrDiffType = SignedInt;
4372 IntPtrType = SignedInt;
4375 // Use fpret for all types.
4376 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
4377 (1 << TargetInfo::Double) |
4378 (1 << TargetInfo::LongDouble));
4380 // x86-32 has atomics up to 8 bytes
4381 // FIXME: Check that we actually have cmpxchg8b before setting
4382 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
4383 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4385 BuiltinVaListKind getBuiltinVaListKind() const override {
4386 return TargetInfo::CharPtrBuiltinVaList;
4389 int getEHDataRegisterNumber(unsigned RegNo) const override {
4390 if (RegNo == 0) return 0;
4391 if (RegNo == 1) return 2;
4394 bool validateOperandSize(StringRef Constraint,
4395 unsigned Size) const override {
4396 switch (Constraint[0]) {
4412 return X86TargetInfo::validateOperandSize(Constraint, Size);
4414 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4415 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
4416 Builtin::FirstTSBuiltin + 1);
4420 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
4422 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4423 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {}
4425 unsigned getFloatEvalMethod() const override {
4426 unsigned Major, Minor, Micro;
4427 getTriple().getOSVersion(Major, Minor, Micro);
4428 // New NetBSD uses the default rounding mode.
4429 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
4430 return X86_32TargetInfo::getFloatEvalMethod();
4431 // NetBSD before 6.99.26 defaults to "double" rounding.
4436 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
4438 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4439 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4440 SizeType = UnsignedLong;
4441 IntPtrType = SignedLong;
4442 PtrDiffType = SignedLong;
4446 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
4448 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4449 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4450 SizeType = UnsignedLong;
4451 IntPtrType = SignedLong;
4452 PtrDiffType = SignedLong;
4456 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
4458 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4459 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4460 LongDoubleWidth = 128;
4461 LongDoubleAlign = 128;
4462 SuitableAlign = 128;
4463 MaxVectorAlign = 256;
4464 // The watchOS simulator uses the builtin bool type for Objective-C.
4465 llvm::Triple T = llvm::Triple(Triple);
4467 UseSignedCharForObjCBool = false;
4468 SizeType = UnsignedLong;
4469 IntPtrType = SignedLong;
4470 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128");
4471 HasAlignMac68kSupport = true;
4474 bool handleTargetFeatures(std::vector<std::string> &Features,
4475 DiagnosticsEngine &Diags) override {
4476 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features,
4479 // We now know the features we have: we can decide how to align vectors.
4481 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4486 // x86-32 Windows target
4487 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
4489 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4490 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4491 WCharType = UnsignedShort;
4492 DoubleAlign = LongLongAlign = 64;
4494 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4495 resetDataLayout(IsWinCOFF
4496 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
4497 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4499 void getTargetDefines(const LangOptions &Opts,
4500 MacroBuilder &Builder) const override {
4501 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4505 // x86-32 Windows Visual Studio target
4506 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
4508 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple,
4509 const TargetOptions &Opts)
4510 : WindowsX86_32TargetInfo(Triple, Opts) {
4511 LongDoubleWidth = LongDoubleAlign = 64;
4512 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4514 void getTargetDefines(const LangOptions &Opts,
4515 MacroBuilder &Builder) const override {
4516 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4517 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
4518 // The value of the following reflects processor type.
4519 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
4520 // We lost the original triple, so we use the default.
4521 Builder.defineMacro("_M_IX86", "600");
4525 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4526 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang
4527 // supports __declspec natively under -fms-extensions, but we define a no-op
4528 // __declspec macro anyway for pre-processor compatibility.
4529 if (Opts.MicrosoftExt)
4530 Builder.defineMacro("__declspec", "__declspec");
4532 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
4534 if (!Opts.MicrosoftExt) {
4535 // Provide macros for all the calling convention keywords. Provide both
4536 // single and double underscore prefixed variants. These are available on
4537 // x64 as well as x86, even though they have no effect.
4538 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
4539 for (const char *CC : CCs) {
4540 std::string GCCSpelling = "__attribute__((__";
4542 GCCSpelling += "__))";
4543 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
4544 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
4549 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4550 Builder.defineMacro("__MSVCRT__");
4551 Builder.defineMacro("__MINGW32__");
4552 addCygMingDefines(Opts, Builder);
4555 // x86-32 MinGW target
4556 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
4558 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4559 : WindowsX86_32TargetInfo(Triple, Opts) {}
4560 void getTargetDefines(const LangOptions &Opts,
4561 MacroBuilder &Builder) const override {
4562 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4563 DefineStd(Builder, "WIN32", Opts);
4564 DefineStd(Builder, "WINNT", Opts);
4565 Builder.defineMacro("_X86_");
4566 addMinGWDefines(Opts, Builder);
4570 // x86-32 Cygwin target
4571 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
4573 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4574 : X86_32TargetInfo(Triple, Opts) {
4575 WCharType = UnsignedShort;
4576 DoubleAlign = LongLongAlign = 64;
4577 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4579 void getTargetDefines(const LangOptions &Opts,
4580 MacroBuilder &Builder) const override {
4581 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4582 Builder.defineMacro("_X86_");
4583 Builder.defineMacro("__CYGWIN__");
4584 Builder.defineMacro("__CYGWIN32__");
4585 addCygMingDefines(Opts, Builder);
4586 DefineStd(Builder, "unix", Opts);
4588 Builder.defineMacro("_GNU_SOURCE");
4592 // x86-32 Haiku target
4593 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> {
4595 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4596 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4598 void getTargetDefines(const LangOptions &Opts,
4599 MacroBuilder &Builder) const override {
4600 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4601 Builder.defineMacro("__INTEL__");
4605 // X86-32 MCU target
4606 class MCUX86_32TargetInfo : public X86_32TargetInfo {
4608 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4609 : X86_32TargetInfo(Triple, Opts) {
4610 LongDoubleWidth = 64;
4611 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4612 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32");
4613 WIntType = UnsignedInt;
4616 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4617 // On MCU we support only C calling convention.
4618 return CC == CC_C ? CCCR_OK : CCCR_Warning;
4621 void getTargetDefines(const LangOptions &Opts,
4622 MacroBuilder &Builder) const override {
4623 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4624 Builder.defineMacro("__iamcu");
4625 Builder.defineMacro("__iamcu__");
4628 bool allowsLargerPreferedTypeAlignment() const override {
4634 template<typename Target>
4635 class RTEMSTargetInfo : public OSTargetInfo<Target> {
4637 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4638 MacroBuilder &Builder) const override {
4639 // RTEMS defines; list based off of gcc output
4641 Builder.defineMacro("__rtems__");
4642 Builder.defineMacro("__ELF__");
4646 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4647 : OSTargetInfo<Target>(Triple, Opts) {
4648 switch (Triple.getArch()) {
4650 case llvm::Triple::x86:
4651 // this->MCountName = ".mcount";
4653 case llvm::Triple::mips:
4654 case llvm::Triple::mipsel:
4655 case llvm::Triple::ppc:
4656 case llvm::Triple::ppc64:
4657 case llvm::Triple::ppc64le:
4658 // this->MCountName = "_mcount";
4660 case llvm::Triple::arm:
4661 // this->MCountName = "__mcount";
4667 // x86-32 RTEMS target
4668 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
4670 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4671 : X86_32TargetInfo(Triple, Opts) {
4672 SizeType = UnsignedLong;
4673 IntPtrType = SignedLong;
4674 PtrDiffType = SignedLong;
4676 void getTargetDefines(const LangOptions &Opts,
4677 MacroBuilder &Builder) const override {
4678 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4679 Builder.defineMacro("__INTEL__");
4680 Builder.defineMacro("__rtems__");
4684 // x86-64 generic target
4685 class X86_64TargetInfo : public X86TargetInfo {
4687 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4688 : X86TargetInfo(Triple, Opts) {
4689 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
4691 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4692 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
4693 LongDoubleWidth = 128;
4694 LongDoubleAlign = 128;
4695 LargeArrayMinWidth = 128;
4696 LargeArrayAlign = 128;
4697 SuitableAlign = 128;
4698 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
4699 PtrDiffType = IsX32 ? SignedInt : SignedLong;
4700 IntPtrType = IsX32 ? SignedInt : SignedLong;
4701 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
4702 Int64Type = IsX32 ? SignedLongLong : SignedLong;
4705 // Pointers are 32-bit in x32.
4706 resetDataLayout(IsX32
4707 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
4708 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
4709 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128");
4711 // Use fpret only for long double.
4712 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
4714 // Use fp2ret for _Complex long double.
4715 ComplexLongDoubleUsesFP2Ret = true;
4717 // Make __builtin_ms_va_list available.
4718 HasBuiltinMSVaList = true;
4720 // x86-64 has atomics up to 16 bytes.
4721 MaxAtomicPromoteWidth = 128;
4722 MaxAtomicInlineWidth = 128;
4724 BuiltinVaListKind getBuiltinVaListKind() const override {
4725 return TargetInfo::X86_64ABIBuiltinVaList;
4728 int getEHDataRegisterNumber(unsigned RegNo) const override {
4729 if (RegNo == 0) return 0;
4730 if (RegNo == 1) return 1;
4734 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4738 case CC_X86VectorCall:
4739 case CC_IntelOclBicc:
4740 case CC_X86_64Win64:
4741 case CC_PreserveMost:
4742 case CC_PreserveAll:
4746 return CCCR_Warning;
4750 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
4754 // for x32 we need it here explicitly
4755 bool hasInt128Type() const override { return true; }
4756 unsigned getUnwindWordWidth() const override { return 64; }
4757 unsigned getRegisterWidth() const override { return 64; }
4759 bool validateGlobalRegisterVariable(StringRef RegName,
4761 bool &HasSizeMismatch) const override {
4762 // rsp and rbp are the only 64-bit registers the x86 backend can currently
4764 if (RegName.equals("rsp") || RegName.equals("rbp")) {
4765 // Check that the register size is 64-bit.
4766 HasSizeMismatch = RegSize != 64;
4770 // Check if the register is a 32-bit register the backend can handle.
4771 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize,
4774 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4775 return llvm::makeArrayRef(BuiltinInfoX86,
4776 X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
4780 // x86-64 Windows target
4781 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
4783 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4784 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4785 WCharType = UnsignedShort;
4786 LongWidth = LongAlign = 32;
4787 DoubleAlign = LongLongAlign = 64;
4788 IntMaxType = SignedLongLong;
4789 Int64Type = SignedLongLong;
4790 SizeType = UnsignedLongLong;
4791 PtrDiffType = SignedLongLong;
4792 IntPtrType = SignedLongLong;
4795 void getTargetDefines(const LangOptions &Opts,
4796 MacroBuilder &Builder) const override {
4797 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
4798 Builder.defineMacro("_WIN64");
4801 BuiltinVaListKind getBuiltinVaListKind() const override {
4802 return TargetInfo::CharPtrBuiltinVaList;
4805 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4808 case CC_X86ThisCall:
4809 case CC_X86FastCall:
4812 case CC_X86VectorCall:
4813 case CC_IntelOclBicc:
4819 return CCCR_Warning;
4824 // x86-64 Windows Visual Studio target
4825 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
4827 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple,
4828 const TargetOptions &Opts)
4829 : WindowsX86_64TargetInfo(Triple, Opts) {
4830 LongDoubleWidth = LongDoubleAlign = 64;
4831 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4833 void getTargetDefines(const LangOptions &Opts,
4834 MacroBuilder &Builder) const override {
4835 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4836 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
4837 Builder.defineMacro("_M_X64", "100");
4838 Builder.defineMacro("_M_AMD64", "100");
4842 // x86-64 MinGW target
4843 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
4845 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4846 : WindowsX86_64TargetInfo(Triple, Opts) {
4847 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
4848 // with x86 FP ops. Weird.
4849 LongDoubleWidth = LongDoubleAlign = 128;
4850 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
4853 void getTargetDefines(const LangOptions &Opts,
4854 MacroBuilder &Builder) const override {
4855 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4856 DefineStd(Builder, "WIN64", Opts);
4857 Builder.defineMacro("__MINGW64__");
4858 addMinGWDefines(Opts, Builder);
4860 // GCC defines this macro when it is using __gxx_personality_seh0.
4861 if (!Opts.SjLjExceptions)
4862 Builder.defineMacro("__SEH__");
4866 // x86-64 Cygwin target
4867 class CygwinX86_64TargetInfo : public X86_64TargetInfo {
4869 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4870 : X86_64TargetInfo(Triple, Opts) {
4871 TLSSupported = false;
4872 WCharType = UnsignedShort;
4874 void getTargetDefines(const LangOptions &Opts,
4875 MacroBuilder &Builder) const override {
4876 X86_64TargetInfo::getTargetDefines(Opts, Builder);
4877 Builder.defineMacro("__x86_64__");
4878 Builder.defineMacro("__CYGWIN__");
4879 Builder.defineMacro("__CYGWIN64__");
4880 addCygMingDefines(Opts, Builder);
4881 DefineStd(Builder, "unix", Opts);
4883 Builder.defineMacro("_GNU_SOURCE");
4885 // GCC defines this macro when it is using __gxx_personality_seh0.
4886 if (!Opts.SjLjExceptions)
4887 Builder.defineMacro("__SEH__");
4891 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
4893 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4894 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4895 Int64Type = SignedLongLong;
4896 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
4897 llvm::Triple T = llvm::Triple(Triple);
4899 UseSignedCharForObjCBool = false;
4900 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128");
4903 bool handleTargetFeatures(std::vector<std::string> &Features,
4904 DiagnosticsEngine &Diags) override {
4905 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features,
4908 // We now know the features we have: we can decide how to align vectors.
4910 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4915 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
4917 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4918 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4919 IntMaxType = SignedLongLong;
4920 Int64Type = SignedLongLong;
4924 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
4926 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4927 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4928 IntMaxType = SignedLongLong;
4929 Int64Type = SignedLongLong;
4933 class ARMTargetInfo : public TargetInfo {
4934 // Possible FPU choices.
4943 // Possible HWDiv features.
4945 HWDivThumb = (1 << 0),
4949 static bool FPUModeIsVFP(FPUMode Mode) {
4950 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
4953 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4954 static const char * const GCCRegNames[];
4956 std::string ABI, CPU;
4958 StringRef CPUProfile;
4968 unsigned ArchKind = llvm::ARM::AK_ARMV4T;
4969 unsigned ArchProfile;
4970 unsigned ArchVersion;
4974 unsigned IsAAPCS : 1;
4977 // Initialized via features.
4978 unsigned SoftFloat : 1;
4979 unsigned SoftFloatABI : 1;
4982 unsigned Crypto : 1;
4984 unsigned Unaligned : 1;
4987 LDREX_B = (1 << 0), /// byte (8-bit)
4988 LDREX_H = (1 << 1), /// half (16-bit)
4989 LDREX_W = (1 << 2), /// word (32-bit)
4990 LDREX_D = (1 << 3), /// double (64-bit)
4995 // ACLE 6.5.1 Hardware floating point
4997 HW_FP_HP = (1 << 1), /// half (16-bit)
4998 HW_FP_SP = (1 << 2), /// single (32-bit)
4999 HW_FP_DP = (1 << 3), /// double (64-bit)
5003 static const Builtin::Info BuiltinInfo[];
5005 void setABIAAPCS() {
5008 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
5009 const llvm::Triple &T = getTriple();
5011 // size_t is unsigned long on MachO-derived environments, NetBSD,
5012 // OpenBSD and Bitrig.
5013 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
5014 T.getOS() == llvm::Triple::OpenBSD ||
5015 T.getOS() == llvm::Triple::Bitrig)
5016 SizeType = UnsignedLong;
5018 SizeType = UnsignedInt;
5020 switch (T.getOS()) {
5021 case llvm::Triple::NetBSD:
5022 case llvm::Triple::OpenBSD:
5023 WCharType = SignedInt;
5025 case llvm::Triple::Win32:
5026 WCharType = UnsignedShort;
5028 case llvm::Triple::Linux:
5030 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
5031 WCharType = UnsignedInt;
5035 UseBitFieldTypeAlignment = true;
5037 ZeroLengthBitfieldBoundary = 0;
5039 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
5040 // so set preferred for small types to 32.
5041 if (T.isOSBinFormatMachO()) {
5042 resetDataLayout(BigEndian
5043 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
5044 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
5045 } else if (T.isOSWindows()) {
5046 assert(!BigEndian && "Windows on ARM does not support big endian");
5055 } else if (T.isOSNaCl()) {
5056 assert(!BigEndian && "NaCl on ARM does not support big endian");
5057 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128");
5059 resetDataLayout(BigEndian
5060 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
5061 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
5064 // FIXME: Enumerated types are variable width in straight AAPCS.
5067 void setABIAPCS(bool IsAAPCS16) {
5068 const llvm::Triple &T = getTriple();
5073 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
5075 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
5077 // size_t is unsigned int on FreeBSD.
5078 if (T.getOS() == llvm::Triple::FreeBSD)
5079 SizeType = UnsignedInt;
5081 SizeType = UnsignedLong;
5083 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
5084 WCharType = SignedInt;
5086 // Do not respect the alignment of bit-field types when laying out
5087 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
5088 UseBitFieldTypeAlignment = false;
5090 /// gcc forces the alignment to 4 bytes, regardless of the type of the
5091 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
5093 ZeroLengthBitfieldBoundary = 32;
5095 if (T.isOSBinFormatMachO() && IsAAPCS16) {
5096 assert(!BigEndian && "AAPCS16 does not support big-endian");
5097 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128");
5098 } else if (T.isOSBinFormatMachO())
5101 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
5102 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
5106 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
5107 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
5109 // FIXME: Override "preferred align" for double and long long.
5112 void setArchInfo() {
5113 StringRef ArchName = getTriple().getArchName();
5115 ArchISA = llvm::ARM::parseArchISA(ArchName);
5116 CPU = llvm::ARM::getDefaultCPU(ArchName);
5117 unsigned AK = llvm::ARM::parseArch(ArchName);
5118 if (AK != llvm::ARM::AK_INVALID)
5120 setArchInfo(ArchKind);
5123 void setArchInfo(unsigned Kind) {
5126 // cache TargetParser info
5128 SubArch = llvm::ARM::getSubArch(ArchKind);
5129 ArchProfile = llvm::ARM::parseArchProfile(SubArch);
5130 ArchVersion = llvm::ARM::parseArchVersion(SubArch);
5132 // cache CPU related strings
5133 CPUAttr = getCPUAttr();
5134 CPUProfile = getCPUProfile();
5138 // when triple does not specify a sub arch,
5139 // then we are not using inline atomics
5140 bool ShouldUseInlineAtomic =
5141 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) ||
5142 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
5143 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
5144 if (ArchProfile == llvm::ARM::PK_M) {
5145 MaxAtomicPromoteWidth = 32;
5146 if (ShouldUseInlineAtomic)
5147 MaxAtomicInlineWidth = 32;
5150 MaxAtomicPromoteWidth = 64;
5151 if (ShouldUseInlineAtomic)
5152 MaxAtomicInlineWidth = 64;
5156 bool isThumb() const {
5157 return (ArchISA == llvm::ARM::IK_THUMB);
5160 bool supportsThumb() const {
5161 return CPUAttr.count('T') || ArchVersion >= 6;
5164 bool supportsThumb2() const {
5165 return CPUAttr.equals("6T2") ||
5166 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE"));
5169 StringRef getCPUAttr() const {
5170 // For most sub-arches, the build attribute CPU name is enough.
5171 // For Cortex variants, it's slightly different.
5174 return llvm::ARM::getCPUAttr(ArchKind);
5175 case llvm::ARM::AK_ARMV6M:
5177 case llvm::ARM::AK_ARMV7S:
5179 case llvm::ARM::AK_ARMV7A:
5181 case llvm::ARM::AK_ARMV7R:
5183 case llvm::ARM::AK_ARMV7M:
5185 case llvm::ARM::AK_ARMV7EM:
5187 case llvm::ARM::AK_ARMV7VE:
5189 case llvm::ARM::AK_ARMV8A:
5191 case llvm::ARM::AK_ARMV8_1A:
5193 case llvm::ARM::AK_ARMV8_2A:
5195 case llvm::ARM::AK_ARMV8MBaseline:
5197 case llvm::ARM::AK_ARMV8MMainline:
5199 case llvm::ARM::AK_ARMV8R:
5204 StringRef getCPUProfile() const {
5205 switch(ArchProfile) {
5206 case llvm::ARM::PK_A:
5208 case llvm::ARM::PK_R:
5210 case llvm::ARM::PK_M:
5218 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5219 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0),
5222 switch (getTriple().getOS()) {
5223 case llvm::Triple::NetBSD:
5224 case llvm::Triple::OpenBSD:
5225 PtrDiffType = SignedLong;
5228 PtrDiffType = SignedInt;
5232 // Cache arch related info.
5235 // {} in inline assembly are neon specifiers, not assembly variant
5237 NoAsmVariants = true;
5239 // FIXME: This duplicates code from the driver that sets the -target-abi
5240 // option - this code is used if -target-abi isn't passed and should
5241 // be unified in some way.
5242 if (Triple.isOSBinFormatMachO()) {
5243 // The backend is hardwired to assume AAPCS for M-class processors, ensure
5244 // the frontend matches that.
5245 if (Triple.getEnvironment() == llvm::Triple::EABI ||
5246 Triple.getOS() == llvm::Triple::UnknownOS ||
5247 ArchProfile == llvm::ARM::PK_M) {
5249 } else if (Triple.isWatchABI()) {
5254 } else if (Triple.isOSWindows()) {
5255 // FIXME: this is invalid for WindowsCE
5258 // Select the default based on the platform.
5259 switch (Triple.getEnvironment()) {
5260 case llvm::Triple::Android:
5261 case llvm::Triple::GNUEABI:
5262 case llvm::Triple::GNUEABIHF:
5263 case llvm::Triple::MuslEABI:
5264 case llvm::Triple::MuslEABIHF:
5265 setABI("aapcs-linux");
5267 case llvm::Triple::EABIHF:
5268 case llvm::Triple::EABI:
5271 case llvm::Triple::GNU:
5275 if (Triple.getOS() == llvm::Triple::NetBSD)
5277 else if (Triple.getOS() == llvm::Triple::OpenBSD)
5278 setABI("aapcs-linux");
5285 // ARM targets default to using the ARM C++ ABI.
5286 TheCXXABI.set(TargetCXXABI::GenericARM);
5288 // ARM has atomics up to 8 bytes
5291 // Do force alignment of members that follow zero length bitfields. If
5292 // the alignment of the zero-length bitfield is greater than the member
5293 // that follows it, `bar', `bar' will be aligned as the type of the
5294 // zero length bitfield.
5295 UseZeroLengthBitfieldAlignment = true;
5297 if (Triple.getOS() == llvm::Triple::Linux ||
5298 Triple.getOS() == llvm::Triple::UnknownOS)
5300 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount";
5303 StringRef getABI() const override { return ABI; }
5305 bool setABI(const std::string &Name) override {
5308 // The defaults (above) are for AAPCS, check if we need to change them.
5310 // FIXME: We need support for -meabi... we could just mangle it into the
5312 if (Name == "apcs-gnu" || Name == "aapcs16") {
5313 setABIAPCS(Name == "aapcs16");
5316 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
5323 // FIXME: This should be based on Arch attributes, not CPU names.
5325 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
5327 const std::vector<std::string> &FeaturesVec) const override {
5329 std::vector<StringRef> TargetFeatures;
5330 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName());
5332 // get default FPU features
5333 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
5334 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
5336 // get default Extension features
5337 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
5338 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
5340 for (auto Feature : TargetFeatures)
5341 if (Feature[0] == '+')
5342 Features[Feature.drop_front(1)] = true;
5344 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
5347 bool handleTargetFeatures(std::vector<std::string> &Features,
5348 DiagnosticsEngine &Diags) override {
5354 SoftFloat = SoftFloatABI = false;
5357 // This does not diagnose illegal cases like having both
5358 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
5359 uint32_t HW_FP_remove = 0;
5360 for (const auto &Feature : Features) {
5361 if (Feature == "+soft-float") {
5363 } else if (Feature == "+soft-float-abi") {
5364 SoftFloatABI = true;
5365 } else if (Feature == "+vfp2") {
5367 HW_FP |= HW_FP_SP | HW_FP_DP;
5368 } else if (Feature == "+vfp3") {
5370 HW_FP |= HW_FP_SP | HW_FP_DP;
5371 } else if (Feature == "+vfp4") {
5373 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
5374 } else if (Feature == "+fp-armv8") {
5376 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
5377 } else if (Feature == "+neon") {
5379 HW_FP |= HW_FP_SP | HW_FP_DP;
5380 } else if (Feature == "+hwdiv") {
5381 HWDiv |= HWDivThumb;
5382 } else if (Feature == "+hwdiv-arm") {
5384 } else if (Feature == "+crc") {
5386 } else if (Feature == "+crypto") {
5388 } else if (Feature == "+dsp") {
5390 } else if (Feature == "+fp-only-sp") {
5391 HW_FP_remove |= HW_FP_DP;
5392 } else if (Feature == "+strict-align") {
5394 } else if (Feature == "+fp16") {
5398 HW_FP &= ~HW_FP_remove;
5400 switch (ArchVersion) {
5402 if (ArchProfile == llvm::ARM::PK_M)
5404 else if (ArchKind == llvm::ARM::AK_ARMV6K)
5405 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5410 if (ArchProfile == llvm::ARM::PK_M)
5411 LDREX = LDREX_W | LDREX_H | LDREX_B ;
5413 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5416 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5419 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
5420 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
5424 if (FPMath == FP_Neon)
5425 Features.push_back("+neonfp");
5426 else if (FPMath == FP_VFP)
5427 Features.push_back("-neonfp");
5429 // Remove front-end specific options which the backend handles differently.
5431 std::find(Features.begin(), Features.end(), "+soft-float-abi");
5432 if (Feature != Features.end())
5433 Features.erase(Feature);
5438 bool hasFeature(StringRef Feature) const override {
5439 return llvm::StringSwitch<bool>(Feature)
5441 .Case("aarch32", true)
5442 .Case("softfloat", SoftFloat)
5443 .Case("thumb", isThumb())
5444 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
5445 .Case("hwdiv", HWDiv & HWDivThumb)
5446 .Case("hwdiv-arm", HWDiv & HWDivARM)
5450 bool setCPU(const std::string &Name) override {
5451 if (Name != "generic")
5452 setArchInfo(llvm::ARM::parseCPUArch(Name));
5454 if (ArchKind == llvm::ARM::AK_INVALID)
5461 bool setFPMath(StringRef Name) override;
5463 void getTargetDefines(const LangOptions &Opts,
5464 MacroBuilder &Builder) const override {
5465 // Target identification.
5466 Builder.defineMacro("__arm");
5467 Builder.defineMacro("__arm__");
5468 // For bare-metal none-eabi.
5469 if (getTriple().getOS() == llvm::Triple::UnknownOS &&
5470 (getTriple().getEnvironment() == llvm::Triple::EABI ||
5471 getTriple().getEnvironment() == llvm::Triple::EABIHF))
5472 Builder.defineMacro("__ELF__");
5475 // Target properties.
5476 Builder.defineMacro("__REGISTER_PREFIX__", "");
5478 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
5479 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
5480 if (getTriple().isWatchABI())
5481 Builder.defineMacro("__ARM_ARCH_7K__", "2");
5483 if (!CPUAttr.empty())
5484 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
5486 // ACLE 6.4.1 ARM/Thumb instruction set architecture
5487 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
5488 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
5490 if (ArchVersion >= 8) {
5491 // ACLE 6.5.7 Crypto Extension
5493 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
5494 // ACLE 6.5.8 CRC32 Extension
5496 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
5497 // ACLE 6.5.10 Numeric Maximum and Minimum
5498 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
5499 // ACLE 6.5.9 Directed Rounding
5500 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
5503 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
5504 // is not defined for the M-profile.
5505 // NOTE that the default profile is assumed to be 'A'
5506 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M)
5507 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
5509 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original
5510 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the
5511 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all
5512 // v7 and v8 architectures excluding v8-M Baseline.
5513 if (supportsThumb2())
5514 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
5515 else if (supportsThumb())
5516 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
5518 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
5519 // instruction set such as ARM or Thumb.
5520 Builder.defineMacro("__ARM_32BIT_STATE", "1");
5522 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
5524 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
5525 if (!CPUProfile.empty())
5526 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
5528 // ACLE 6.4.3 Unaligned access supported in hardware
5530 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
5532 // ACLE 6.4.4 LDREX/STREX
5534 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX));
5537 if (ArchVersion == 5 ||
5538 (ArchVersion == 6 && CPUProfile != "M") ||
5540 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
5542 // ACLE 6.5.1 Hardware Floating Point
5544 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
5547 Builder.defineMacro("__ARM_ACLE", "200");
5549 // FP16 support (we currently only support IEEE format).
5550 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
5551 Builder.defineMacro("__ARM_FP16_ARGS", "1");
5553 // ACLE 6.5.3 Fused multiply-accumulate (FMA)
5554 if (ArchVersion >= 7 && (FPU & VFP4FPU))
5555 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
5557 // Subtarget options.
5559 // FIXME: It's more complicated than this and we don't really support
5561 // Windows on ARM does not "support" interworking
5562 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows())
5563 Builder.defineMacro("__THUMB_INTERWORK__");
5565 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
5566 // Embedded targets on Darwin follow AAPCS, but not EABI.
5567 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
5568 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows())
5569 Builder.defineMacro("__ARM_EABI__");
5570 Builder.defineMacro("__ARM_PCS", "1");
5573 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" ||
5575 Builder.defineMacro("__ARM_PCS_VFP", "1");
5578 Builder.defineMacro("__SOFTFP__");
5580 if (ArchKind == llvm::ARM::AK_XSCALE)
5581 Builder.defineMacro("__XSCALE__");
5584 Builder.defineMacro("__THUMBEL__");
5585 Builder.defineMacro("__thumb__");
5586 if (supportsThumb2())
5587 Builder.defineMacro("__thumb2__");
5590 // ACLE 6.4.9 32-bit SIMD instructions
5591 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
5592 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
5594 // ACLE 6.4.10 Hardware Integer Divide
5595 if (((HWDiv & HWDivThumb) && isThumb()) ||
5596 ((HWDiv & HWDivARM) && !isThumb())) {
5597 Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
5598 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
5601 // Note, this is always on in gcc, even though it doesn't make sense.
5602 Builder.defineMacro("__APCS_32__");
5604 if (FPUModeIsVFP((FPUMode) FPU)) {
5605 Builder.defineMacro("__VFP_FP__");
5607 Builder.defineMacro("__ARM_VFPV2__");
5609 Builder.defineMacro("__ARM_VFPV3__");
5611 Builder.defineMacro("__ARM_VFPV4__");
5613 Builder.defineMacro("__ARM_FPV5__");
5616 // This only gets set when Neon instructions are actually available, unlike
5617 // the VFP define, hence the soft float and arch check. This is subtly
5618 // different from gcc, we follow the intent which was that it should be set
5619 // when Neon instructions are actually available.
5620 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
5621 Builder.defineMacro("__ARM_NEON", "1");
5622 Builder.defineMacro("__ARM_NEON__");
5623 // current AArch32 NEON implementations do not support double-precision
5624 // floating-point even when it is present in VFP.
5625 Builder.defineMacro("__ARM_NEON_FP",
5626 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP));
5629 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
5630 Opts.ShortWChar ? "2" : "4");
5632 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5633 Opts.ShortEnums ? "1" : "4");
5635 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") {
5636 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
5637 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
5638 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
5639 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
5642 // ACLE 6.4.7 DSP instructions
5644 Builder.defineMacro("__ARM_FEATURE_DSP", "1");
5647 // ACLE 6.4.8 Saturation instructions
5649 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) {
5650 Builder.defineMacro("__ARM_FEATURE_SAT", "1");
5654 // ACLE 6.4.6 Q (saturation) flag
5656 Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
5658 if (Opts.UnsafeFPMath)
5659 Builder.defineMacro("__ARM_FP_FAST", "1");
5661 if (ArchKind == llvm::ARM::AK_ARMV8_1A)
5662 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
5665 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5666 return llvm::makeArrayRef(BuiltinInfo,
5667 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin);
5669 bool isCLZForZeroUndef() const override { return false; }
5670 BuiltinVaListKind getBuiltinVaListKind() const override {
5672 ? AAPCSABIBuiltinVaList
5673 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList
5674 : TargetInfo::VoidPtrBuiltinVaList);
5676 ArrayRef<const char *> getGCCRegNames() const override;
5677 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5678 bool validateAsmConstraint(const char *&Name,
5679 TargetInfo::ConstraintInfo &Info) const override {
5684 case 't': // VFP Floating point register single precision
5685 case 'w': // VFP Floating point register double precision
5686 Info.setAllowsRegister();
5695 case 'Q': // A memory address that is a single base register.
5696 Info.setAllowsMemory();
5698 case 'U': // a memory reference...
5700 case 'q': // ...ARMV4 ldrsb
5701 case 'v': // ...VFP load/store (reg+constant offset)
5702 case 'y': // ...iWMMXt load/store
5703 case 't': // address valid for load/store opaque types wider
5705 case 'n': // valid address for Neon doubleword vector load/store
5706 case 'm': // valid address for Neon element and structure load/store
5707 case 's': // valid address for non-offset loads/stores of quad-word
5708 // values in four ARM registers
5709 Info.setAllowsMemory();
5716 std::string convertConstraint(const char *&Constraint) const override {
5718 switch (*Constraint) {
5719 case 'U': // Two-character constraint; add "^" hint for later parsing.
5720 R = std::string("^") + std::string(Constraint, 2);
5723 case 'p': // 'p' should be translated to 'r' by default.
5724 R = std::string("r");
5727 return std::string(1, *Constraint);
5732 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5733 std::string &SuggestedModifier) const override {
5734 bool isOutput = (Constraint[0] == '=');
5735 bool isInOut = (Constraint[0] == '+');
5737 // Strip off constraint modifiers.
5738 while (Constraint[0] == '=' ||
5739 Constraint[0] == '+' ||
5740 Constraint[0] == '&')
5741 Constraint = Constraint.substr(1);
5743 switch (Constraint[0]) {
5748 return (isInOut || isOutput || Size <= 64);
5750 // A register of size 32 cannot fit a vector type.
5758 const char *getClobbers() const override {
5759 // FIXME: Is this really right?
5763 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5770 return CCCR_Warning;
5774 int getEHDataRegisterNumber(unsigned RegNo) const override {
5775 if (RegNo == 0) return 0;
5776 if (RegNo == 1) return 1;
5780 bool hasSjLjLowering() const override {
5785 bool ARMTargetInfo::setFPMath(StringRef Name) {
5786 if (Name == "neon") {
5789 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
5797 const char * const ARMTargetInfo::GCCRegNames[] = {
5798 // Integer registers
5799 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5800 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
5803 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
5804 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
5805 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
5806 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5809 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
5810 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
5811 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
5812 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5815 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
5816 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
5819 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
5820 return llvm::makeArrayRef(GCCRegNames);
5823 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
5833 { { "v6", "rfp" }, "r9" },
5834 { { "sl" }, "r10" },
5835 { { "fp" }, "r11" },
5836 { { "ip" }, "r12" },
5837 { { "r13" }, "sp" },
5838 { { "r14" }, "lr" },
5839 { { "r15" }, "pc" },
5840 // The S, D and Q registers overlap, but aren't really aliases; we
5841 // don't want to substitute one of these for a different-sized one.
5844 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
5845 return llvm::makeArrayRef(GCCRegAliases);
5848 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
5849 #define BUILTIN(ID, TYPE, ATTRS) \
5850 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5851 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5852 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5853 #include "clang/Basic/BuiltinsNEON.def"
5855 #define BUILTIN(ID, TYPE, ATTRS) \
5856 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5857 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \
5858 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr },
5859 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5860 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5861 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
5862 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
5863 #include "clang/Basic/BuiltinsARM.def"
5866 class ARMleTargetInfo : public ARMTargetInfo {
5868 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5869 : ARMTargetInfo(Triple, Opts) {}
5870 void getTargetDefines(const LangOptions &Opts,
5871 MacroBuilder &Builder) const override {
5872 Builder.defineMacro("__ARMEL__");
5873 ARMTargetInfo::getTargetDefines(Opts, Builder);
5877 class ARMbeTargetInfo : public ARMTargetInfo {
5879 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5880 : ARMTargetInfo(Triple, Opts) {}
5881 void getTargetDefines(const LangOptions &Opts,
5882 MacroBuilder &Builder) const override {
5883 Builder.defineMacro("__ARMEB__");
5884 Builder.defineMacro("__ARM_BIG_ENDIAN");
5885 ARMTargetInfo::getTargetDefines(Opts, Builder);
5889 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
5890 const llvm::Triple Triple;
5892 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5893 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
5894 WCharType = UnsignedShort;
5895 SizeType = UnsignedInt;
5897 void getVisualStudioDefines(const LangOptions &Opts,
5898 MacroBuilder &Builder) const {
5899 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
5901 // FIXME: this is invalid for WindowsCE
5902 Builder.defineMacro("_M_ARM_NT", "1");
5903 Builder.defineMacro("_M_ARMT", "_M_ARM");
5904 Builder.defineMacro("_M_THUMB", "_M_ARM");
5906 assert((Triple.getArch() == llvm::Triple::arm ||
5907 Triple.getArch() == llvm::Triple::thumb) &&
5908 "invalid architecture for Windows ARM target info");
5909 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
5910 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
5912 // TODO map the complete set of values
5913 // 31: VFPv3 40: VFPv4
5914 Builder.defineMacro("_M_ARM_FP", "31");
5916 BuiltinVaListKind getBuiltinVaListKind() const override {
5917 return TargetInfo::CharPtrBuiltinVaList;
5919 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5922 case CC_X86ThisCall:
5923 case CC_X86FastCall:
5924 case CC_X86VectorCall:
5929 return CCCR_Warning;
5934 // Windows ARM + Itanium C++ ABI Target
5935 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
5937 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple,
5938 const TargetOptions &Opts)
5939 : WindowsARMTargetInfo(Triple, Opts) {
5940 TheCXXABI.set(TargetCXXABI::GenericARM);
5943 void getTargetDefines(const LangOptions &Opts,
5944 MacroBuilder &Builder) const override {
5945 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5947 if (Opts.MSVCCompat)
5948 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5952 // Windows ARM, MS (C++) ABI
5953 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
5955 MicrosoftARMleTargetInfo(const llvm::Triple &Triple,
5956 const TargetOptions &Opts)
5957 : WindowsARMTargetInfo(Triple, Opts) {
5958 TheCXXABI.set(TargetCXXABI::Microsoft);
5961 void getTargetDefines(const LangOptions &Opts,
5962 MacroBuilder &Builder) const override {
5963 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5964 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5969 class MinGWARMTargetInfo : public WindowsARMTargetInfo {
5971 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5972 : WindowsARMTargetInfo(Triple, Opts) {
5973 TheCXXABI.set(TargetCXXABI::GenericARM);
5976 void getTargetDefines(const LangOptions &Opts,
5977 MacroBuilder &Builder) const override {
5978 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5979 DefineStd(Builder, "WIN32", Opts);
5980 DefineStd(Builder, "WINNT", Opts);
5981 Builder.defineMacro("_ARM_");
5982 addMinGWDefines(Opts, Builder);
5986 // ARM Cygwin target
5987 class CygwinARMTargetInfo : public ARMleTargetInfo {
5989 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5990 : ARMleTargetInfo(Triple, Opts) {
5991 TLSSupported = false;
5992 WCharType = UnsignedShort;
5993 DoubleAlign = LongLongAlign = 64;
5994 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
5996 void getTargetDefines(const LangOptions &Opts,
5997 MacroBuilder &Builder) const override {
5998 ARMleTargetInfo::getTargetDefines(Opts, Builder);
5999 Builder.defineMacro("_ARM_");
6000 Builder.defineMacro("__CYGWIN__");
6001 Builder.defineMacro("__CYGWIN32__");
6002 DefineStd(Builder, "unix", Opts);
6004 Builder.defineMacro("_GNU_SOURCE");
6008 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> {
6010 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
6011 MacroBuilder &Builder) const override {
6012 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
6016 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6017 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
6018 HasAlignMac68kSupport = true;
6019 // iOS always has 64-bit atomic instructions.
6020 // FIXME: This should be based off of the target features in
6022 MaxAtomicInlineWidth = 64;
6024 if (Triple.isWatchABI()) {
6025 // Darwin on iOS uses a variant of the ARM C++ ABI.
6026 TheCXXABI.set(TargetCXXABI::WatchOS);
6028 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that
6029 // size_t is long, it's a bit weird for it to be int.
6030 PtrDiffType = SignedLong;
6032 // BOOL should be a real boolean on the new ABI
6033 UseSignedCharForObjCBool = false;
6035 TheCXXABI.set(TargetCXXABI::iOS);
6039 class AArch64TargetInfo : public TargetInfo {
6040 virtual void setDataLayout() = 0;
6041 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6042 static const char *const GCCRegNames[];
6055 static const Builtin::Info BuiltinInfo[];
6060 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6061 : TargetInfo(Triple), ABI("aapcs") {
6062 if (getTriple().getOS() == llvm::Triple::NetBSD ||
6063 getTriple().getOS() == llvm::Triple::OpenBSD) {
6064 WCharType = SignedInt;
6066 // NetBSD apparently prefers consistency across ARM targets to consistency
6067 // across 64-bit targets.
6068 Int64Type = SignedLongLong;
6069 IntMaxType = SignedLongLong;
6071 WCharType = UnsignedInt;
6072 Int64Type = SignedLong;
6073 IntMaxType = SignedLong;
6076 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6077 MaxVectorAlign = 128;
6078 MaxAtomicInlineWidth = 128;
6079 MaxAtomicPromoteWidth = 128;
6081 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
6082 LongDoubleFormat = &llvm::APFloat::IEEEquad();
6084 // {} in inline assembly are neon specifiers, not assembly variant
6086 NoAsmVariants = true;
6088 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
6089 // contributes to the alignment of the containing aggregate in the same way
6090 // a plain (non bit-field) member of that type would, without exception for
6091 // zero-sized or anonymous bit-fields."
6092 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
6093 UseZeroLengthBitfieldAlignment = true;
6095 // AArch64 targets default to using the ARM C++ ABI.
6096 TheCXXABI.set(TargetCXXABI::GenericAArch64);
6098 if (Triple.getOS() == llvm::Triple::Linux)
6099 this->MCountName = "\01_mcount";
6100 else if (Triple.getOS() == llvm::Triple::UnknownOS)
6101 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount";
6104 StringRef getABI() const override { return ABI; }
6105 bool setABI(const std::string &Name) override {
6106 if (Name != "aapcs" && Name != "darwinpcs")
6113 bool setCPU(const std::string &Name) override {
6114 return Name == "generic" ||
6115 llvm::AArch64::parseCPUArch(Name) !=
6116 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID);
6119 void getTargetDefines(const LangOptions &Opts,
6120 MacroBuilder &Builder) const override {
6121 // Target identification.
6122 Builder.defineMacro("__aarch64__");
6123 // For bare-metal none-eabi.
6124 if (getTriple().getOS() == llvm::Triple::UnknownOS &&
6125 (getTriple().getEnvironment() == llvm::Triple::EABI ||
6126 getTriple().getEnvironment() == llvm::Triple::EABIHF))
6127 Builder.defineMacro("__ELF__");
6129 // Target properties.
6130 Builder.defineMacro("_LP64");
6131 Builder.defineMacro("__LP64__");
6133 // ACLE predefines. Many can only have one possible value on v8 AArch64.
6134 Builder.defineMacro("__ARM_ACLE", "200");
6135 Builder.defineMacro("__ARM_ARCH", "8");
6136 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
6138 Builder.defineMacro("__ARM_64BIT_STATE", "1");
6139 Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
6140 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
6142 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
6143 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
6144 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
6145 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
6146 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
6147 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
6148 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
6150 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
6152 // 0xe implies support for half, single and double precision operations.
6153 Builder.defineMacro("__ARM_FP", "0xE");
6155 // PCS specifies this for SysV variants, which is all we support. Other ABIs
6156 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
6157 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
6158 Builder.defineMacro("__ARM_FP16_ARGS", "1");
6160 if (Opts.UnsafeFPMath)
6161 Builder.defineMacro("__ARM_FP_FAST", "1");
6163 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
6165 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
6166 Opts.ShortEnums ? "1" : "4");
6168 if (FPU == NeonMode) {
6169 Builder.defineMacro("__ARM_NEON", "1");
6170 // 64-bit NEON supports half, single and double precision operations.
6171 Builder.defineMacro("__ARM_NEON_FP", "0xE");
6175 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
6178 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
6181 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
6184 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
6186 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
6187 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
6188 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
6189 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
6190 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
6193 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6194 return llvm::makeArrayRef(BuiltinInfo,
6195 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin);
6198 bool hasFeature(StringRef Feature) const override {
6199 return Feature == "aarch64" ||
6200 Feature == "arm64" ||
6202 (Feature == "neon" && FPU == NeonMode);
6205 bool handleTargetFeatures(std::vector<std::string> &Features,
6206 DiagnosticsEngine &Diags) override {
6213 for (const auto &Feature : Features) {
6214 if (Feature == "+neon")
6216 if (Feature == "+crc")
6218 if (Feature == "+crypto")
6220 if (Feature == "+strict-align")
6222 if (Feature == "+v8.1a")
6231 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6235 case CC_PreserveMost:
6236 case CC_PreserveAll:
6239 return CCCR_Warning;
6243 bool isCLZForZeroUndef() const override { return false; }
6245 BuiltinVaListKind getBuiltinVaListKind() const override {
6246 return TargetInfo::AArch64ABIBuiltinVaList;
6249 ArrayRef<const char *> getGCCRegNames() const override;
6250 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6252 bool validateAsmConstraint(const char *&Name,
6253 TargetInfo::ConstraintInfo &Info) const override {
6257 case 'w': // Floating point and SIMD registers (V0-V31)
6258 Info.setAllowsRegister();
6260 case 'I': // Constant that can be used with an ADD instruction
6261 case 'J': // Constant that can be used with a SUB instruction
6262 case 'K': // Constant that can be used with a 32-bit logical instruction
6263 case 'L': // Constant that can be used with a 64-bit logical instruction
6264 case 'M': // Constant that can be used as a 32-bit MOV immediate
6265 case 'N': // Constant that can be used as a 64-bit MOV immediate
6266 case 'Y': // Floating point constant zero
6267 case 'Z': // Integer constant zero
6269 case 'Q': // A memory reference with base register and no offset
6270 Info.setAllowsMemory();
6272 case 'S': // A symbolic address
6273 Info.setAllowsRegister();
6276 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
6277 // Utf: A memory address suitable for ldp/stp in TF mode.
6278 // Usa: An absolute symbolic address.
6279 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
6280 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
6281 case 'z': // Zero register, wzr or xzr
6282 Info.setAllowsRegister();
6284 case 'x': // Floating point and SIMD registers (V0-V15)
6285 Info.setAllowsRegister();
6292 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
6293 std::string &SuggestedModifier) const override {
6294 // Strip off constraint modifiers.
6295 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
6296 Constraint = Constraint.substr(1);
6298 switch (Constraint[0]) {
6306 // For now assume that the person knows what they're
6307 // doing with the modifier.
6310 // By default an 'r' constraint will be in the 'x'
6315 SuggestedModifier = "w";
6322 const char *getClobbers() const override { return ""; }
6324 int getEHDataRegisterNumber(unsigned RegNo) const override {
6333 const char *const AArch64TargetInfo::GCCRegNames[] = {
6334 // 32-bit Integer registers
6335 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
6336 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
6337 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
6339 // 64-bit Integer registers
6340 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
6341 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
6342 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
6344 // 32-bit floating point regsisters
6345 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
6346 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
6347 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
6349 // 64-bit floating point regsisters
6350 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
6351 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
6352 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
6355 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
6356 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
6357 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
6360 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
6361 return llvm::makeArrayRef(GCCRegNames);
6364 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
6365 { { "w31" }, "wsp" },
6366 { { "x29" }, "fp" },
6367 { { "x30" }, "lr" },
6368 { { "x31" }, "sp" },
6369 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
6370 // don't want to substitute one of these for a different-sized one.
6373 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
6374 return llvm::makeArrayRef(GCCRegAliases);
6377 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
6378 #define BUILTIN(ID, TYPE, ATTRS) \
6379 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6380 #include "clang/Basic/BuiltinsNEON.def"
6382 #define BUILTIN(ID, TYPE, ATTRS) \
6383 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6384 #include "clang/Basic/BuiltinsAArch64.def"
6387 class AArch64leTargetInfo : public AArch64TargetInfo {
6388 void setDataLayout() override {
6389 if (getTriple().isOSBinFormatMachO())
6390 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128");
6392 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6396 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6397 : AArch64TargetInfo(Triple, Opts) {
6399 void getTargetDefines(const LangOptions &Opts,
6400 MacroBuilder &Builder) const override {
6401 Builder.defineMacro("__AARCH64EL__");
6402 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6406 class AArch64beTargetInfo : public AArch64TargetInfo {
6407 void setDataLayout() override {
6408 assert(!getTriple().isOSBinFormatMachO());
6409 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6413 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6414 : AArch64TargetInfo(Triple, Opts) {}
6415 void getTargetDefines(const LangOptions &Opts,
6416 MacroBuilder &Builder) const override {
6417 Builder.defineMacro("__AARCH64EB__");
6418 Builder.defineMacro("__AARCH_BIG_ENDIAN");
6419 Builder.defineMacro("__ARM_BIG_ENDIAN");
6420 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6424 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
6426 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
6427 MacroBuilder &Builder) const override {
6428 Builder.defineMacro("__AARCH64_SIMD__");
6429 Builder.defineMacro("__ARM64_ARCH_8__");
6430 Builder.defineMacro("__ARM_NEON__");
6431 Builder.defineMacro("__LITTLE_ENDIAN__");
6432 Builder.defineMacro("__REGISTER_PREFIX__", "");
6433 Builder.defineMacro("__arm64", "1");
6434 Builder.defineMacro("__arm64__", "1");
6436 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
6440 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6441 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
6442 Int64Type = SignedLongLong;
6443 WCharType = SignedInt;
6444 UseSignedCharForObjCBool = false;
6446 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
6447 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
6449 TheCXXABI.set(TargetCXXABI::iOS64);
6452 BuiltinVaListKind getBuiltinVaListKind() const override {
6453 return TargetInfo::CharPtrBuiltinVaList;
6457 // Hexagon abstract base class
6458 class HexagonTargetInfo : public TargetInfo {
6459 static const Builtin::Info BuiltinInfo[];
6460 static const char * const GCCRegNames[];
6461 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6463 bool HasHVX, HasHVXDouble;
6467 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6468 : TargetInfo(Triple) {
6469 // Specify the vector alignment explicitly. For v512x1, the calculated
6470 // alignment would be 512*alignment(i1), which is 512 bytes, instead of
6471 // the required minimum of 64 bytes.
6472 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-"
6473 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
6474 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048");
6475 SizeType = UnsignedInt;
6476 PtrDiffType = SignedInt;
6477 IntPtrType = SignedInt;
6479 // {} in inline assembly are packet specifiers, not assembly variant
6481 NoAsmVariants = true;
6483 LargeArrayMinWidth = 64;
6484 LargeArrayAlign = 64;
6485 UseBitFieldTypeAlignment = true;
6486 ZeroLengthBitfieldBoundary = 32;
6487 HasHVX = HasHVXDouble = false;
6488 UseLongCalls = false;
6491 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6492 return llvm::makeArrayRef(BuiltinInfo,
6493 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin);
6496 bool validateAsmConstraint(const char *&Name,
6497 TargetInfo::ConstraintInfo &Info) const override {
6502 Info.setAllowsRegister();
6507 // Relocatable constant.
6513 void getTargetDefines(const LangOptions &Opts,
6514 MacroBuilder &Builder) const override;
6516 bool isCLZForZeroUndef() const override { return false; }
6518 bool hasFeature(StringRef Feature) const override {
6519 return llvm::StringSwitch<bool>(Feature)
6520 .Case("hexagon", true)
6521 .Case("hvx", HasHVX)
6522 .Case("hvx-double", HasHVXDouble)
6523 .Case("long-calls", UseLongCalls)
6527 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6528 StringRef CPU, const std::vector<std::string> &FeaturesVec)
6531 bool handleTargetFeatures(std::vector<std::string> &Features,
6532 DiagnosticsEngine &Diags) override;
6534 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
6535 bool Enabled) const override;
6537 BuiltinVaListKind getBuiltinVaListKind() const override {
6538 return TargetInfo::CharPtrBuiltinVaList;
6540 ArrayRef<const char *> getGCCRegNames() const override;
6541 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6542 const char *getClobbers() const override {
6546 static const char *getHexagonCPUSuffix(StringRef Name) {
6547 return llvm::StringSwitch<const char*>(Name)
6548 .Case("hexagonv4", "4")
6549 .Case("hexagonv5", "5")
6550 .Case("hexagonv55", "55")
6551 .Case("hexagonv60", "60")
6552 .Case("hexagonv62", "62")
6556 bool setCPU(const std::string &Name) override {
6557 if (!getHexagonCPUSuffix(Name))
6563 int getEHDataRegisterNumber(unsigned RegNo) const override {
6564 return RegNo < 2 ? RegNo : -1;
6568 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
6569 MacroBuilder &Builder) const {
6570 Builder.defineMacro("__qdsp6__", "1");
6571 Builder.defineMacro("__hexagon__", "1");
6573 if (CPU == "hexagonv4") {
6574 Builder.defineMacro("__HEXAGON_V4__");
6575 Builder.defineMacro("__HEXAGON_ARCH__", "4");
6576 if (Opts.HexagonQdsp6Compat) {
6577 Builder.defineMacro("__QDSP6_V4__");
6578 Builder.defineMacro("__QDSP6_ARCH__", "4");
6580 } else if (CPU == "hexagonv5") {
6581 Builder.defineMacro("__HEXAGON_V5__");
6582 Builder.defineMacro("__HEXAGON_ARCH__", "5");
6583 if(Opts.HexagonQdsp6Compat) {
6584 Builder.defineMacro("__QDSP6_V5__");
6585 Builder.defineMacro("__QDSP6_ARCH__", "5");
6587 } else if (CPU == "hexagonv55") {
6588 Builder.defineMacro("__HEXAGON_V55__");
6589 Builder.defineMacro("__HEXAGON_ARCH__", "55");
6590 Builder.defineMacro("__QDSP6_V55__");
6591 Builder.defineMacro("__QDSP6_ARCH__", "55");
6592 } else if (CPU == "hexagonv60") {
6593 Builder.defineMacro("__HEXAGON_V60__");
6594 Builder.defineMacro("__HEXAGON_ARCH__", "60");
6595 Builder.defineMacro("__QDSP6_V60__");
6596 Builder.defineMacro("__QDSP6_ARCH__", "60");
6597 } else if (CPU == "hexagonv62") {
6598 Builder.defineMacro("__HEXAGON_V62__");
6599 Builder.defineMacro("__HEXAGON_ARCH__", "62");
6602 if (hasFeature("hvx")) {
6603 Builder.defineMacro("__HVX__");
6604 if (hasFeature("hvx-double"))
6605 Builder.defineMacro("__HVXDBL__");
6609 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features,
6610 DiagnosticsEngine &Diags, StringRef CPU,
6611 const std::vector<std::string> &FeaturesVec) const {
6612 // Default for v60: -hvx, -hvx-double.
6613 Features["hvx"] = false;
6614 Features["hvx-double"] = false;
6615 Features["long-calls"] = false;
6617 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6620 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
6621 DiagnosticsEngine &Diags) {
6622 for (auto &F : Features) {
6625 else if (F == "-hvx")
6626 HasHVX = HasHVXDouble = false;
6627 else if (F == "+hvx-double")
6628 HasHVX = HasHVXDouble = true;
6629 else if (F == "-hvx-double")
6630 HasHVXDouble = false;
6632 if (F == "+long-calls")
6633 UseLongCalls = true;
6634 else if (F == "-long-calls")
6635 UseLongCalls = false;
6640 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
6641 StringRef Name, bool Enabled) const {
6643 if (Name == "hvx-double")
6644 Features["hvx"] = true;
6647 Features["hvx-double"] = false;
6649 Features[Name] = Enabled;
6652 const char *const HexagonTargetInfo::GCCRegNames[] = {
6653 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6654 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6655 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6656 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
6657 "p0", "p1", "p2", "p3",
6658 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
6661 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const {
6662 return llvm::makeArrayRef(GCCRegNames);
6665 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
6666 { { "sp" }, "r29" },
6667 { { "fp" }, "r30" },
6668 { { "lr" }, "r31" },
6671 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const {
6672 return llvm::makeArrayRef(GCCRegAliases);
6676 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
6677 #define BUILTIN(ID, TYPE, ATTRS) \
6678 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6679 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6680 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6681 #include "clang/Basic/BuiltinsHexagon.def"
6684 class LanaiTargetInfo : public TargetInfo {
6685 // Class for Lanai (32-bit).
6686 // The CPU profiles supported by the Lanai backend
6692 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6693 static const char *const GCCRegNames[];
6696 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6697 : TargetInfo(Triple) {
6698 // Description string has to be kept in sync with backend.
6699 resetDataLayout("E" // Big endian
6700 "-m:e" // ELF name manging
6701 "-p:32:32" // 32 bit pointers, 32 bit aligned
6702 "-i64:64" // 64 bit integers, 64 bit aligned
6703 "-a:0:32" // 32 bit alignment of objects of aggregate type
6704 "-n32" // 32 bit native integer width
6705 "-S64" // 64 bit natural stack alignment
6708 // Setting RegParmMax equal to what mregparm was set to in the old
6712 // Set the default CPU to V11
6715 // Temporary approach to make everything at least word-aligned and allow for
6716 // safely casting between pointers with different alignment requirements.
6717 // TODO: Remove this when there are no more cast align warnings on the
6719 MinGlobalAlign = 32;
6722 void getTargetDefines(const LangOptions &Opts,
6723 MacroBuilder &Builder) const override {
6724 // Define __lanai__ when building for target lanai.
6725 Builder.defineMacro("__lanai__");
6727 // Set define for the CPU specified.
6730 Builder.defineMacro("__LANAI_V11__");
6733 llvm_unreachable("Unhandled target CPU");
6737 bool setCPU(const std::string &Name) override {
6738 CPU = llvm::StringSwitch<CPUKind>(Name)
6739 .Case("v11", CK_V11)
6742 return CPU != CK_NONE;
6745 bool hasFeature(StringRef Feature) const override {
6746 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false);
6749 ArrayRef<const char *> getGCCRegNames() const override;
6751 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6753 BuiltinVaListKind getBuiltinVaListKind() const override {
6754 return TargetInfo::VoidPtrBuiltinVaList;
6757 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
6759 bool validateAsmConstraint(const char *&Name,
6760 TargetInfo::ConstraintInfo &info) const override {
6764 const char *getClobbers() const override { return ""; }
6767 const char *const LanaiTargetInfo::GCCRegNames[] = {
6768 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
6769 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
6770 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
6772 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const {
6773 return llvm::makeArrayRef(GCCRegNames);
6776 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = {
6786 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const {
6787 return llvm::makeArrayRef(GCCRegAliases);
6790 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
6791 class SparcTargetInfo : public TargetInfo {
6792 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6793 static const char * const GCCRegNames[];
6796 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6797 : TargetInfo(Triple), SoftFloat(false) {}
6799 int getEHDataRegisterNumber(unsigned RegNo) const override {
6800 if (RegNo == 0) return 24;
6801 if (RegNo == 1) return 25;
6805 bool handleTargetFeatures(std::vector<std::string> &Features,
6806 DiagnosticsEngine &Diags) override {
6807 // Check if software floating point is enabled
6808 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
6809 if (Feature != Features.end()) {
6814 void getTargetDefines(const LangOptions &Opts,
6815 MacroBuilder &Builder) const override {
6816 DefineStd(Builder, "sparc", Opts);
6817 Builder.defineMacro("__REGISTER_PREFIX__", "");
6820 Builder.defineMacro("SOFT_FLOAT", "1");
6823 bool hasFeature(StringRef Feature) const override {
6824 return llvm::StringSwitch<bool>(Feature)
6825 .Case("softfloat", SoftFloat)
6826 .Case("sparc", true)
6830 bool hasSjLjLowering() const override {
6834 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6835 // FIXME: Implement!
6838 BuiltinVaListKind getBuiltinVaListKind() const override {
6839 return TargetInfo::VoidPtrBuiltinVaList;
6841 ArrayRef<const char *> getGCCRegNames() const override;
6842 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6843 bool validateAsmConstraint(const char *&Name,
6844 TargetInfo::ConstraintInfo &info) const override {
6845 // FIXME: Implement!
6847 case 'I': // Signed 13-bit constant
6849 case 'K': // 32-bit constant with the low 12 bits clear
6850 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
6851 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
6852 case 'N': // Same as 'K' but zext (required for SIMode)
6853 case 'O': // The constant 4096
6858 const char *getClobbers() const override {
6859 // FIXME: Implement!
6863 // No Sparc V7 for now, the backend doesn't support it anyway.
6894 enum CPUGeneration {
6899 CPUGeneration getCPUGeneration(CPUKind Kind) const {
6907 case CK_SPARCLITE86X:
6914 case CK_LEON2_AT697E:
6915 case CK_LEON2_AT697F:
6917 case CK_LEON3_UT699:
6918 case CK_LEON3_GR712RC:
6920 case CK_LEON4_GR740:
6924 case CK_ULTRASPARC3:
6931 llvm_unreachable("Unexpected CPU kind");
6934 CPUKind getCPUKind(StringRef Name) const {
6935 return llvm::StringSwitch<CPUKind>(Name)
6937 .Case("supersparc", CK_SUPERSPARC)
6938 .Case("sparclite", CK_SPARCLITE)
6939 .Case("f934", CK_F934)
6940 .Case("hypersparc", CK_HYPERSPARC)
6941 .Case("sparclite86x", CK_SPARCLITE86X)
6942 .Case("sparclet", CK_SPARCLET)
6943 .Case("tsc701", CK_TSC701)
6945 .Case("ultrasparc", CK_ULTRASPARC)
6946 .Case("ultrasparc3", CK_ULTRASPARC3)
6947 .Case("niagara", CK_NIAGARA)
6948 .Case("niagara2", CK_NIAGARA2)
6949 .Case("niagara3", CK_NIAGARA3)
6950 .Case("niagara4", CK_NIAGARA4)
6951 .Case("ma2100", CK_MYRIAD2100)
6952 .Case("ma2150", CK_MYRIAD2150)
6953 .Case("ma2450", CK_MYRIAD2450)
6954 // FIXME: the myriad2[.n] spellings are obsolete,
6955 // but a grace period is needed to allow updating dependent builds.
6956 .Case("myriad2", CK_MYRIAD2100)
6957 .Case("myriad2.1", CK_MYRIAD2100)
6958 .Case("myriad2.2", CK_MYRIAD2150)
6959 .Case("leon2", CK_LEON2)
6960 .Case("at697e", CK_LEON2_AT697E)
6961 .Case("at697f", CK_LEON2_AT697F)
6962 .Case("leon3", CK_LEON3)
6963 .Case("ut699", CK_LEON3_UT699)
6964 .Case("gr712rc", CK_LEON3_GR712RC)
6965 .Case("leon4", CK_LEON4)
6966 .Case("gr740", CK_LEON4_GR740)
6967 .Default(CK_GENERIC);
6970 bool setCPU(const std::string &Name) override {
6971 CPU = getCPUKind(Name);
6972 return CPU != CK_GENERIC;
6976 const char * const SparcTargetInfo::GCCRegNames[] = {
6977 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6978 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6979 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6980 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6983 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
6984 return llvm::makeArrayRef(GCCRegNames);
6987 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
6998 { { "o2" }, "r10" },
6999 { { "o3" }, "r11" },
7000 { { "o4" }, "r12" },
7001 { { "o5" }, "r13" },
7002 { { "o6", "sp" }, "r14" },
7003 { { "o7" }, "r15" },
7004 { { "l0" }, "r16" },
7005 { { "l1" }, "r17" },
7006 { { "l2" }, "r18" },
7007 { { "l3" }, "r19" },
7008 { { "l4" }, "r20" },
7009 { { "l5" }, "r21" },
7010 { { "l6" }, "r22" },
7011 { { "l7" }, "r23" },
7012 { { "i0" }, "r24" },
7013 { { "i1" }, "r25" },
7014 { { "i2" }, "r26" },
7015 { { "i3" }, "r27" },
7016 { { "i4" }, "r28" },
7017 { { "i5" }, "r29" },
7018 { { "i6", "fp" }, "r30" },
7019 { { "i7" }, "r31" },
7022 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
7023 return llvm::makeArrayRef(GCCRegAliases);
7026 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
7027 class SparcV8TargetInfo : public SparcTargetInfo {
7029 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7030 : SparcTargetInfo(Triple, Opts) {
7031 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64");
7032 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
7033 switch (getTriple().getOS()) {
7035 SizeType = UnsignedInt;
7036 IntPtrType = SignedInt;
7037 PtrDiffType = SignedInt;
7039 case llvm::Triple::NetBSD:
7040 case llvm::Triple::OpenBSD:
7041 SizeType = UnsignedLong;
7042 IntPtrType = SignedLong;
7043 PtrDiffType = SignedLong;
7046 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops
7047 // on up to 64 bits.
7048 MaxAtomicPromoteWidth = 64;
7049 MaxAtomicInlineWidth = 32;
7052 void getTargetDefines(const LangOptions &Opts,
7053 MacroBuilder &Builder) const override {
7054 SparcTargetInfo::getTargetDefines(Opts, Builder);
7055 switch (getCPUGeneration(CPU)) {
7057 Builder.defineMacro("__sparcv8");
7058 if (getTriple().getOS() != llvm::Triple::Solaris)
7059 Builder.defineMacro("__sparcv8__");
7062 Builder.defineMacro("__sparcv9");
7063 if (getTriple().getOS() != llvm::Triple::Solaris) {
7064 Builder.defineMacro("__sparcv9__");
7065 Builder.defineMacro("__sparc_v9__");
7069 if (getTriple().getVendor() == llvm::Triple::Myriad) {
7070 std::string MyriadArchValue, Myriad2Value;
7071 Builder.defineMacro("__sparc_v8__");
7072 Builder.defineMacro("__leon__");
7075 MyriadArchValue = "__ma2150";
7079 MyriadArchValue = "__ma2450";
7083 MyriadArchValue = "__ma2100";
7087 Builder.defineMacro(MyriadArchValue, "1");
7088 Builder.defineMacro(MyriadArchValue+"__", "1");
7089 Builder.defineMacro("__myriad2__", Myriad2Value);
7090 Builder.defineMacro("__myriad2", Myriad2Value);
7094 bool hasSjLjLowering() const override {
7099 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
7100 class SparcV8elTargetInfo : public SparcV8TargetInfo {
7102 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7103 : SparcV8TargetInfo(Triple, Opts) {
7104 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64");
7108 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
7109 class SparcV9TargetInfo : public SparcTargetInfo {
7111 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7112 : SparcTargetInfo(Triple, Opts) {
7113 // FIXME: Support Sparc quad-precision long double?
7114 resetDataLayout("E-m:e-i64:64-n32:64-S128");
7115 // This is an LP64 platform.
7116 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7118 // OpenBSD uses long long for int64_t and intmax_t.
7119 if (getTriple().getOS() == llvm::Triple::OpenBSD)
7120 IntMaxType = SignedLongLong;
7122 IntMaxType = SignedLong;
7123 Int64Type = IntMaxType;
7125 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
7126 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
7127 LongDoubleWidth = 128;
7128 LongDoubleAlign = 128;
7129 LongDoubleFormat = &llvm::APFloat::IEEEquad();
7130 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7133 void getTargetDefines(const LangOptions &Opts,
7134 MacroBuilder &Builder) const override {
7135 SparcTargetInfo::getTargetDefines(Opts, Builder);
7136 Builder.defineMacro("__sparcv9");
7137 Builder.defineMacro("__arch64__");
7138 // Solaris doesn't need these variants, but the BSDs do.
7139 if (getTriple().getOS() != llvm::Triple::Solaris) {
7140 Builder.defineMacro("__sparc64__");
7141 Builder.defineMacro("__sparc_v9__");
7142 Builder.defineMacro("__sparcv9__");
7146 bool setCPU(const std::string &Name) override {
7147 if (!SparcTargetInfo::setCPU(Name))
7149 return getCPUGeneration(CPU) == CG_V9;
7153 class SystemZTargetInfo : public TargetInfo {
7154 static const Builtin::Info BuiltinInfo[];
7155 static const char *const GCCRegNames[];
7157 bool HasTransactionalExecution;
7161 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7162 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false),
7164 IntMaxType = SignedLong;
7165 Int64Type = SignedLong;
7166 TLSSupported = true;
7167 IntWidth = IntAlign = 32;
7168 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
7169 PointerWidth = PointerAlign = 64;
7170 LongDoubleWidth = 128;
7171 LongDoubleAlign = 64;
7172 LongDoubleFormat = &llvm::APFloat::IEEEquad();
7173 DefaultAlignForAttributeAligned = 64;
7174 MinGlobalAlign = 16;
7175 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64");
7176 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7178 void getTargetDefines(const LangOptions &Opts,
7179 MacroBuilder &Builder) const override {
7180 Builder.defineMacro("__s390__");
7181 Builder.defineMacro("__s390x__");
7182 Builder.defineMacro("__zarch__");
7183 Builder.defineMacro("__LONG_DOUBLE_128__");
7185 const std::string ISARev = llvm::StringSwitch<std::string>(CPU)
7186 .Cases("arch8", "z10", "8")
7187 .Cases("arch9", "z196", "9")
7188 .Cases("arch10", "zEC12", "10")
7189 .Cases("arch11", "z13", "11")
7191 if (!ISARev.empty())
7192 Builder.defineMacro("__ARCH__", ISARev);
7194 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
7195 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
7196 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
7197 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
7199 if (HasTransactionalExecution)
7200 Builder.defineMacro("__HTM__");
7202 Builder.defineMacro("__VX__");
7204 Builder.defineMacro("__VEC__", "10301");
7206 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7207 return llvm::makeArrayRef(BuiltinInfo,
7208 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin);
7211 ArrayRef<const char *> getGCCRegNames() const override;
7212 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7216 bool validateAsmConstraint(const char *&Name,
7217 TargetInfo::ConstraintInfo &info) const override;
7218 const char *getClobbers() const override {
7219 // FIXME: Is this really right?
7222 BuiltinVaListKind getBuiltinVaListKind() const override {
7223 return TargetInfo::SystemZBuiltinVaList;
7225 bool setCPU(const std::string &Name) override {
7227 bool CPUKnown = llvm::StringSwitch<bool>(Name)
7229 .Case("arch8", true)
7231 .Case("arch9", true)
7232 .Case("zEC12", true)
7233 .Case("arch10", true)
7235 .Case("arch11", true)
7241 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7243 const std::vector<std::string> &FeaturesVec) const override {
7244 if (CPU == "zEC12" || CPU == "arch10")
7245 Features["transactional-execution"] = true;
7246 if (CPU == "z13" || CPU == "arch11") {
7247 Features["transactional-execution"] = true;
7248 Features["vector"] = true;
7250 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7253 bool handleTargetFeatures(std::vector<std::string> &Features,
7254 DiagnosticsEngine &Diags) override {
7255 HasTransactionalExecution = false;
7256 for (const auto &Feature : Features) {
7257 if (Feature == "+transactional-execution")
7258 HasTransactionalExecution = true;
7259 else if (Feature == "+vector")
7262 // If we use the vector ABI, vector types are 64-bit aligned.
7264 MaxVectorAlign = 64;
7265 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
7266 "-v128:64-a:8:16-n32:64");
7271 bool hasFeature(StringRef Feature) const override {
7272 return llvm::StringSwitch<bool>(Feature)
7273 .Case("systemz", true)
7274 .Case("htm", HasTransactionalExecution)
7275 .Case("vx", HasVector)
7279 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
7285 return CCCR_Warning;
7289 StringRef getABI() const override {
7295 bool useFloat128ManglingForLongDouble() const override {
7300 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
7301 #define BUILTIN(ID, TYPE, ATTRS) \
7302 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7303 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
7304 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
7305 #include "clang/Basic/BuiltinsSystemZ.def"
7308 const char *const SystemZTargetInfo::GCCRegNames[] = {
7309 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7310 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7311 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
7312 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
7315 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
7316 return llvm::makeArrayRef(GCCRegNames);
7319 bool SystemZTargetInfo::
7320 validateAsmConstraint(const char *&Name,
7321 TargetInfo::ConstraintInfo &Info) const {
7326 case 'a': // Address register
7327 case 'd': // Data register (equivalent to 'r')
7328 case 'f': // Floating-point register
7329 Info.setAllowsRegister();
7332 case 'I': // Unsigned 8-bit constant
7333 case 'J': // Unsigned 12-bit constant
7334 case 'K': // Signed 16-bit constant
7335 case 'L': // Signed 20-bit displacement (on all targets we support)
7336 case 'M': // 0x7fffffff
7339 case 'Q': // Memory with base and unsigned 12-bit displacement
7340 case 'R': // Likewise, plus an index
7341 case 'S': // Memory with base and signed 20-bit displacement
7342 case 'T': // Likewise, plus an index
7343 Info.setAllowsMemory();
7348 class MSP430TargetInfo : public TargetInfo {
7349 static const char *const GCCRegNames[];
7352 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7353 : TargetInfo(Triple) {
7354 TLSSupported = false;
7359 LongAlign = LongLongAlign = 16;
7363 SizeType = UnsignedInt;
7364 IntMaxType = SignedLongLong;
7365 IntPtrType = SignedInt;
7366 PtrDiffType = SignedInt;
7367 SigAtomicType = SignedLong;
7368 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16");
7370 void getTargetDefines(const LangOptions &Opts,
7371 MacroBuilder &Builder) const override {
7372 Builder.defineMacro("MSP430");
7373 Builder.defineMacro("__MSP430__");
7374 // FIXME: defines for different 'flavours' of MCU
7376 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7377 // FIXME: Implement.
7380 bool hasFeature(StringRef Feature) const override {
7381 return Feature == "msp430";
7383 ArrayRef<const char *> getGCCRegNames() const override;
7384 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7388 bool validateAsmConstraint(const char *&Name,
7389 TargetInfo::ConstraintInfo &info) const override {
7392 case 'K': // the constant 1
7393 case 'L': // constant -1^20 .. 1^19
7394 case 'M': // constant 1-4:
7397 // No target constraints for now.
7400 const char *getClobbers() const override {
7401 // FIXME: Is this really right?
7404 BuiltinVaListKind getBuiltinVaListKind() const override {
7406 return TargetInfo::CharPtrBuiltinVaList;
7410 const char *const MSP430TargetInfo::GCCRegNames[] = {
7411 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7412 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
7414 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const {
7415 return llvm::makeArrayRef(GCCRegNames);
7418 // LLVM and Clang cannot be used directly to output native binaries for
7419 // target, but is used to compile C code to llvm bitcode with correct
7420 // type and alignment information.
7422 // TCE uses the llvm bitcode as input and uses it for generating customized
7423 // target processor and program binary. TCE co-design environment is
7424 // publicly available in http://tce.cs.tut.fi
7426 static const unsigned TCEOpenCLAddrSpaceMap[] = {
7430 5, // opencl_constant
7431 // FIXME: generic has to be added to the target
7432 0, // opencl_generic
7438 class TCETargetInfo : public TargetInfo {
7440 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7441 : TargetInfo(Triple) {
7442 TLSSupported = false;
7444 LongWidth = LongLongWidth = 32;
7447 LongAlign = LongLongAlign = 32;
7450 SizeType = UnsignedInt;
7451 IntMaxType = SignedLong;
7452 IntPtrType = SignedInt;
7453 PtrDiffType = SignedInt;
7458 LongDoubleWidth = 32;
7459 LongDoubleAlign = 32;
7460 FloatFormat = &llvm::APFloat::IEEEsingle();
7461 DoubleFormat = &llvm::APFloat::IEEEsingle();
7462 LongDoubleFormat = &llvm::APFloat::IEEEsingle();
7463 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-"
7464 "i16:16:32-i32:32:32-i64:32:32-"
7465 "f32:32:32-f64:32:32-v64:32:32-"
7466 "v128:32:32-v256:32:32-v512:32:32-"
7467 "v1024:32:32-a0:0:32-n32");
7468 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
7469 UseAddrSpaceMapMangling = true;
7472 void getTargetDefines(const LangOptions &Opts,
7473 MacroBuilder &Builder) const override {
7474 DefineStd(Builder, "tce", Opts);
7475 Builder.defineMacro("__TCE__");
7476 Builder.defineMacro("__TCE_V1__");
7478 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; }
7480 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7481 const char *getClobbers() const override { return ""; }
7482 BuiltinVaListKind getBuiltinVaListKind() const override {
7483 return TargetInfo::VoidPtrBuiltinVaList;
7485 ArrayRef<const char *> getGCCRegNames() const override { return None; }
7486 bool validateAsmConstraint(const char *&Name,
7487 TargetInfo::ConstraintInfo &info) const override {
7490 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7495 class TCELETargetInfo : public TCETargetInfo {
7497 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7498 : TCETargetInfo(Triple, Opts) {
7501 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-"
7502 "i16:16:32-i32:32:32-i64:32:32-"
7503 "f32:32:32-f64:32:32-v64:32:32-"
7504 "v128:32:32-v256:32:32-v512:32:32-"
7505 "v1024:32:32-a0:0:32-n32");
7509 virtual void getTargetDefines(const LangOptions &Opts,
7510 MacroBuilder &Builder) const {
7511 DefineStd(Builder, "tcele", Opts);
7512 Builder.defineMacro("__TCE__");
7513 Builder.defineMacro("__TCE_V1__");
7514 Builder.defineMacro("__TCELE__");
7515 Builder.defineMacro("__TCELE_V1__");
7520 class BPFTargetInfo : public TargetInfo {
7522 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7523 : TargetInfo(Triple) {
7524 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7525 SizeType = UnsignedLong;
7526 PtrDiffType = SignedLong;
7527 IntPtrType = SignedLong;
7528 IntMaxType = SignedLong;
7529 Int64Type = SignedLong;
7531 if (Triple.getArch() == llvm::Triple::bpfeb) {
7532 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128");
7534 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
7536 MaxAtomicPromoteWidth = 64;
7537 MaxAtomicInlineWidth = 64;
7538 TLSSupported = false;
7540 void getTargetDefines(const LangOptions &Opts,
7541 MacroBuilder &Builder) const override {
7542 DefineStd(Builder, "bpf", Opts);
7543 Builder.defineMacro("__BPF__");
7545 bool hasFeature(StringRef Feature) const override {
7546 return Feature == "bpf";
7549 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7550 const char *getClobbers() const override {
7553 BuiltinVaListKind getBuiltinVaListKind() const override {
7554 return TargetInfo::VoidPtrBuiltinVaList;
7556 ArrayRef<const char *> getGCCRegNames() const override {
7559 bool validateAsmConstraint(const char *&Name,
7560 TargetInfo::ConstraintInfo &info) const override {
7563 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7568 class MipsTargetInfo : public TargetInfo {
7569 void setDataLayout() {
7573 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
7574 else if (ABI == "n32")
7575 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7576 else if (ABI == "n64")
7577 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7579 llvm_unreachable("Invalid ABI");
7582 resetDataLayout(("E-" + Layout).str());
7584 resetDataLayout(("e-" + Layout).str());
7588 static const Builtin::Info BuiltinInfo[];
7595 bool CanUseBSDABICalls;
7597 HardFloat, SoftFloat
7609 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7610 : TargetInfo(Triple), IsMips16(false), IsMicromips(false),
7611 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false),
7612 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP),
7613 HasMSA(false), HasFP64(false) {
7614 TheCXXABI.set(TargetCXXABI::GenericMIPS);
7616 setABI((getTriple().getArch() == llvm::Triple::mips ||
7617 getTriple().getArch() == llvm::Triple::mipsel)
7621 CPU = ABI == "o32" ? "mips32r2" : "mips64r2";
7623 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD ||
7624 Triple.getOS() == llvm::Triple::OpenBSD;
7627 bool isNaN2008Default() const {
7628 return CPU == "mips32r6" || CPU == "mips64r6";
7631 bool isFP64Default() const {
7632 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
7635 bool isNan2008() const override {
7639 bool processorSupportsGPR64() const {
7640 return llvm::StringSwitch<bool>(CPU)
7641 .Case("mips3", true)
7642 .Case("mips4", true)
7643 .Case("mips5", true)
7644 .Case("mips64", true)
7645 .Case("mips64r2", true)
7646 .Case("mips64r3", true)
7647 .Case("mips64r5", true)
7648 .Case("mips64r6", true)
7649 .Case("octeon", true)
7654 StringRef getABI() const override { return ABI; }
7655 bool setABI(const std::string &Name) override {
7656 if (Name == "o32") {
7662 if (Name == "n32") {
7667 if (Name == "n64") {
7675 void setO32ABITypes() {
7676 Int64Type = SignedLongLong;
7677 IntMaxType = Int64Type;
7678 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
7679 LongDoubleWidth = LongDoubleAlign = 64;
7680 LongWidth = LongAlign = 32;
7681 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
7682 PointerWidth = PointerAlign = 32;
7683 PtrDiffType = SignedInt;
7684 SizeType = UnsignedInt;
7688 void setN32N64ABITypes() {
7689 LongDoubleWidth = LongDoubleAlign = 128;
7690 LongDoubleFormat = &llvm::APFloat::IEEEquad();
7691 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
7692 LongDoubleWidth = LongDoubleAlign = 64;
7693 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
7695 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7696 SuitableAlign = 128;
7699 void setN64ABITypes() {
7700 setN32N64ABITypes();
7701 if (getTriple().getOS() == llvm::Triple::OpenBSD) {
7702 Int64Type = SignedLongLong;
7704 Int64Type = SignedLong;
7706 IntMaxType = Int64Type;
7707 LongWidth = LongAlign = 64;
7708 PointerWidth = PointerAlign = 64;
7709 PtrDiffType = SignedLong;
7710 SizeType = UnsignedLong;
7713 void setN32ABITypes() {
7714 setN32N64ABITypes();
7715 Int64Type = SignedLongLong;
7716 IntMaxType = Int64Type;
7717 LongWidth = LongAlign = 32;
7718 PointerWidth = PointerAlign = 32;
7719 PtrDiffType = SignedInt;
7720 SizeType = UnsignedInt;
7723 bool setCPU(const std::string &Name) override {
7725 return llvm::StringSwitch<bool>(Name)
7726 .Case("mips1", true)
7727 .Case("mips2", true)
7728 .Case("mips3", true)
7729 .Case("mips4", true)
7730 .Case("mips5", true)
7731 .Case("mips32", true)
7732 .Case("mips32r2", true)
7733 .Case("mips32r3", true)
7734 .Case("mips32r5", true)
7735 .Case("mips32r6", true)
7736 .Case("mips64", true)
7737 .Case("mips64r2", true)
7738 .Case("mips64r3", true)
7739 .Case("mips64r5", true)
7740 .Case("mips64r6", true)
7741 .Case("octeon", true)
7742 .Case("p5600", true)
7745 const std::string& getCPU() const { return CPU; }
7747 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7749 const std::vector<std::string> &FeaturesVec) const override {
7752 if (CPU == "octeon")
7753 Features["mips64r2"] = Features["cnmips"] = true;
7755 Features[CPU] = true;
7756 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7759 void getTargetDefines(const LangOptions &Opts,
7760 MacroBuilder &Builder) const override {
7762 DefineStd(Builder, "MIPSEB", Opts);
7763 Builder.defineMacro("_MIPSEB");
7765 DefineStd(Builder, "MIPSEL", Opts);
7766 Builder.defineMacro("_MIPSEL");
7769 Builder.defineMacro("__mips__");
7770 Builder.defineMacro("_mips");
7772 Builder.defineMacro("mips");
7775 Builder.defineMacro("__mips", "32");
7776 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
7778 Builder.defineMacro("__mips", "64");
7779 Builder.defineMacro("__mips64");
7780 Builder.defineMacro("__mips64__");
7781 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
7784 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU())
7785 .Cases("mips32", "mips64", "1")
7786 .Cases("mips32r2", "mips64r2", "2")
7787 .Cases("mips32r3", "mips64r3", "3")
7788 .Cases("mips32r5", "mips64r5", "5")
7789 .Cases("mips32r6", "mips64r6", "6")
7791 if (!ISARev.empty())
7792 Builder.defineMacro("__mips_isa_rev", ISARev);
7795 Builder.defineMacro("__mips_o32");
7796 Builder.defineMacro("_ABIO32", "1");
7797 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
7798 } else if (ABI == "n32") {
7799 Builder.defineMacro("__mips_n32");
7800 Builder.defineMacro("_ABIN32", "2");
7801 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
7802 } else if (ABI == "n64") {
7803 Builder.defineMacro("__mips_n64");
7804 Builder.defineMacro("_ABI64", "3");
7805 Builder.defineMacro("_MIPS_SIM", "_ABI64");
7807 llvm_unreachable("Invalid ABI.");
7809 if (!IsNoABICalls) {
7810 Builder.defineMacro("__mips_abicalls");
7811 if (CanUseBSDABICalls)
7812 Builder.defineMacro("__ABICALLS__");
7815 Builder.defineMacro("__REGISTER_PREFIX__", "");
7819 Builder.defineMacro("__mips_hard_float", Twine(1));
7822 Builder.defineMacro("__mips_soft_float", Twine(1));
7827 Builder.defineMacro("__mips_single_float", Twine(1));
7829 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
7830 Builder.defineMacro("_MIPS_FPSET",
7831 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
7834 Builder.defineMacro("__mips16", Twine(1));
7837 Builder.defineMacro("__mips_micromips", Twine(1));
7840 Builder.defineMacro("__mips_nan2008", Twine(1));
7846 Builder.defineMacro("__mips_dsp_rev", Twine(1));
7847 Builder.defineMacro("__mips_dsp", Twine(1));
7850 Builder.defineMacro("__mips_dsp_rev", Twine(2));
7851 Builder.defineMacro("__mips_dspr2", Twine(1));
7852 Builder.defineMacro("__mips_dsp", Twine(1));
7857 Builder.defineMacro("__mips_msa", Twine(1));
7859 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
7860 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
7861 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
7863 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
7864 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
7866 // These shouldn't be defined for MIPS-I but there's no need to check
7867 // for that since MIPS-I isn't supported.
7868 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
7869 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
7870 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
7872 // 32-bit MIPS processors don't have the necessary lld/scd instructions
7873 // found in 64-bit processors. In the case of O32 on a 64-bit processor,
7874 // the instructions exist but using them violates the ABI since they
7875 // require 64-bit GPRs and O32 only supports 32-bit GPRs.
7876 if (ABI == "n32" || ABI == "n64")
7877 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
7880 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7881 return llvm::makeArrayRef(BuiltinInfo,
7882 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin);
7884 bool hasFeature(StringRef Feature) const override {
7885 return llvm::StringSwitch<bool>(Feature)
7887 .Case("fp64", HasFP64)
7890 BuiltinVaListKind getBuiltinVaListKind() const override {
7891 return TargetInfo::VoidPtrBuiltinVaList;
7893 ArrayRef<const char *> getGCCRegNames() const override {
7894 static const char *const GCCRegNames[] = {
7895 // CPU register names
7896 // Must match second column of GCCRegAliases
7897 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
7898 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
7899 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
7900 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
7901 // Floating point register names
7902 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
7903 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
7904 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
7905 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
7906 // Hi/lo and condition register names
7907 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
7908 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo",
7910 // MSA register names
7911 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
7912 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
7913 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
7914 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
7915 // MSA control register names
7916 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
7917 "$msarequest", "$msamap", "$msaunmap"
7919 return llvm::makeArrayRef(GCCRegNames);
7921 bool validateAsmConstraint(const char *&Name,
7922 TargetInfo::ConstraintInfo &Info) const override {
7926 case 'r': // CPU registers.
7927 case 'd': // Equivalent to "r" unless generating MIPS16 code.
7928 case 'y': // Equivalent to "r", backward compatibility only.
7929 case 'f': // floating-point registers.
7930 case 'c': // $25 for indirect jumps
7931 case 'l': // lo register
7932 case 'x': // hilo register pair
7933 Info.setAllowsRegister();
7935 case 'I': // Signed 16-bit constant
7936 case 'J': // Integer 0
7937 case 'K': // Unsigned 16-bit constant
7938 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
7939 case 'M': // Constants not loadable via lui, addiu, or ori
7940 case 'N': // Constant -1 to -65535
7941 case 'O': // A signed 15-bit constant
7942 case 'P': // A constant between 1 go 65535
7944 case 'R': // An address that can be used in a non-macro load or store
7945 Info.setAllowsMemory();
7948 if (Name[1] == 'C') { // An address usable by ll, and sc.
7949 Info.setAllowsMemory();
7950 Name++; // Skip over 'Z'.
7957 std::string convertConstraint(const char *&Constraint) const override {
7959 switch (*Constraint) {
7960 case 'Z': // Two-character constraint; add "^" hint for later parsing.
7961 if (Constraint[1] == 'C') {
7962 R = std::string("^") + std::string(Constraint, 2);
7968 return TargetInfo::convertConstraint(Constraint);
7971 const char *getClobbers() const override {
7972 // In GCC, $1 is not widely used in generated code (it's used only in a few
7973 // specific situations), so there is no real need for users to add it to
7974 // the clobbers list if they want to use it in their inline assembly code.
7976 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
7977 // code generation, so using it in inline assembly without adding it to the
7978 // clobbers list can cause conflicts between the inline assembly code and
7979 // the surrounding generated code.
7981 // Another problem is that LLVM is allowed to choose $1 for inline assembly
7982 // operands, which will conflict with the ".set at" assembler option (which
7983 // we use only for inline assembly, in order to maintain compatibility with
7984 // GCC) and will also conflict with the user's usage of $1.
7986 // The easiest way to avoid these conflicts and keep $1 as an allocatable
7987 // register for generated code is to automatically clobber $1 for all inline
7990 // FIXME: We should automatically clobber $1 only for inline assembly code
7991 // which actually uses it. This would allow LLVM to use $1 for inline
7992 // assembly operands if the user's assembly code doesn't use it.
7996 bool handleTargetFeatures(std::vector<std::string> &Features,
7997 DiagnosticsEngine &Diags) override {
7999 IsMicromips = false;
8000 IsNan2008 = isNaN2008Default();
8001 IsSingleFloat = false;
8002 FloatABI = HardFloat;
8004 HasFP64 = isFP64Default();
8006 for (const auto &Feature : Features) {
8007 if (Feature == "+single-float")
8008 IsSingleFloat = true;
8009 else if (Feature == "+soft-float")
8010 FloatABI = SoftFloat;
8011 else if (Feature == "+mips16")
8013 else if (Feature == "+micromips")
8015 else if (Feature == "+dsp")
8016 DspRev = std::max(DspRev, DSP1);
8017 else if (Feature == "+dspr2")
8018 DspRev = std::max(DspRev, DSP2);
8019 else if (Feature == "+msa")
8021 else if (Feature == "+fp64")
8023 else if (Feature == "-fp64")
8025 else if (Feature == "+nan2008")
8027 else if (Feature == "-nan2008")
8029 else if (Feature == "+noabicalls")
8030 IsNoABICalls = true;
8038 int getEHDataRegisterNumber(unsigned RegNo) const override {
8039 if (RegNo == 0) return 4;
8040 if (RegNo == 1) return 5;
8044 bool isCLZForZeroUndef() const override { return false; }
8046 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8047 static const TargetInfo::GCCRegAlias O32RegAliases[] = {
8048 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
8049 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
8050 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"},
8051 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"},
8052 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"},
8053 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
8054 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
8055 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
8056 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
8057 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
8059 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = {
8060 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
8061 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
8062 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"},
8063 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"},
8064 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"},
8065 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
8066 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
8067 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
8068 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
8069 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
8072 return llvm::makeArrayRef(O32RegAliases);
8073 return llvm::makeArrayRef(NewABIRegAliases);
8076 bool hasInt128Type() const override {
8077 return ABI == "n32" || ABI == "n64";
8080 bool validateTarget(DiagnosticsEngine &Diags) const override {
8081 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle
8082 // this yet. It's better to fail here than on the backend assertion.
8083 if (processorSupportsGPR64() && ABI == "o32") {
8084 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
8088 // 64-bit ABI's require 64-bit CPU's.
8089 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) {
8090 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
8094 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend
8095 // can't handle this yet. It's better to fail here than on the
8096 // backend assertion.
8097 if ((getTriple().getArch() == llvm::Triple::mips64 ||
8098 getTriple().getArch() == llvm::Triple::mips64el) &&
8100 Diags.Report(diag::err_target_unsupported_abi_for_triple)
8101 << ABI << getTriple().str();
8105 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend
8106 // can't handle this yet. It's better to fail here than on the
8107 // backend assertion.
8108 if ((getTriple().getArch() == llvm::Triple::mips ||
8109 getTriple().getArch() == llvm::Triple::mipsel) &&
8110 (ABI == "n32" || ABI == "n64")) {
8111 Diags.Report(diag::err_target_unsupported_abi_for_triple)
8112 << ABI << getTriple().str();
8120 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = {
8121 #define BUILTIN(ID, TYPE, ATTRS) \
8122 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8123 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8124 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8125 #include "clang/Basic/BuiltinsMips.def"
8128 class PNaClTargetInfo : public TargetInfo {
8130 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8131 : TargetInfo(Triple) {
8132 this->LongAlign = 32;
8133 this->LongWidth = 32;
8134 this->PointerAlign = 32;
8135 this->PointerWidth = 32;
8136 this->IntMaxType = TargetInfo::SignedLongLong;
8137 this->Int64Type = TargetInfo::SignedLongLong;
8138 this->DoubleAlign = 64;
8139 this->LongDoubleWidth = 64;
8140 this->LongDoubleAlign = 64;
8141 this->SizeType = TargetInfo::UnsignedInt;
8142 this->PtrDiffType = TargetInfo::SignedInt;
8143 this->IntPtrType = TargetInfo::SignedInt;
8144 this->RegParmMax = 0; // Disallow regparm
8147 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
8148 Builder.defineMacro("__le32__");
8149 Builder.defineMacro("__pnacl__");
8151 void getTargetDefines(const LangOptions &Opts,
8152 MacroBuilder &Builder) const override {
8153 getArchDefines(Opts, Builder);
8155 bool hasFeature(StringRef Feature) const override {
8156 return Feature == "pnacl";
8158 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
8159 BuiltinVaListKind getBuiltinVaListKind() const override {
8160 return TargetInfo::PNaClABIBuiltinVaList;
8162 ArrayRef<const char *> getGCCRegNames() const override;
8163 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
8164 bool validateAsmConstraint(const char *&Name,
8165 TargetInfo::ConstraintInfo &Info) const override {
8169 const char *getClobbers() const override {
8174 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const {
8178 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const {
8182 // We attempt to use PNaCl (le32) frontend and Mips32EL backend.
8183 class NaClMips32TargetInfo : public MipsTargetInfo {
8185 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8186 : MipsTargetInfo(Triple, Opts) {}
8188 BuiltinVaListKind getBuiltinVaListKind() const override {
8189 return TargetInfo::PNaClABIBuiltinVaList;
8193 class Le64TargetInfo : public TargetInfo {
8194 static const Builtin::Info BuiltinInfo[];
8197 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8198 : TargetInfo(Triple) {
8199 NoAsmVariants = true;
8200 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
8201 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8202 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128");
8205 void getTargetDefines(const LangOptions &Opts,
8206 MacroBuilder &Builder) const override {
8207 DefineStd(Builder, "unix", Opts);
8208 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
8209 Builder.defineMacro("__ELF__");
8211 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8212 return llvm::makeArrayRef(BuiltinInfo,
8213 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin);
8215 BuiltinVaListKind getBuiltinVaListKind() const override {
8216 return TargetInfo::PNaClABIBuiltinVaList;
8218 const char *getClobbers() const override { return ""; }
8219 ArrayRef<const char *> getGCCRegNames() const override {
8222 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8225 bool validateAsmConstraint(const char *&Name,
8226 TargetInfo::ConstraintInfo &Info) const override {
8230 bool hasProtectedVisibility() const override { return false; }
8233 class WebAssemblyTargetInfo : public TargetInfo {
8234 static const Builtin::Info BuiltinInfo[];
8242 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &)
8243 : TargetInfo(T), SIMDLevel(NoSIMD) {
8244 NoAsmVariants = true;
8245 SuitableAlign = 128;
8246 LargeArrayMinWidth = 128;
8247 LargeArrayAlign = 128;
8248 SimdDefaultAlign = 128;
8249 SigAtomicType = SignedLong;
8250 LongDoubleWidth = LongDoubleAlign = 128;
8251 LongDoubleFormat = &llvm::APFloat::IEEEquad();
8252 SizeType = UnsignedInt;
8253 PtrDiffType = SignedInt;
8254 IntPtrType = SignedInt;
8258 void getTargetDefines(const LangOptions &Opts,
8259 MacroBuilder &Builder) const override {
8260 defineCPUMacros(Builder, "wasm", /*Tuning=*/false);
8261 if (SIMDLevel >= SIMD128)
8262 Builder.defineMacro("__wasm_simd128__");
8267 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
8269 const std::vector<std::string> &FeaturesVec) const override {
8270 if (CPU == "bleeding-edge")
8271 Features["simd128"] = true;
8272 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
8274 bool hasFeature(StringRef Feature) const final {
8275 return llvm::StringSwitch<bool>(Feature)
8276 .Case("simd128", SIMDLevel >= SIMD128)
8279 bool handleTargetFeatures(std::vector<std::string> &Features,
8280 DiagnosticsEngine &Diags) final {
8281 for (const auto &Feature : Features) {
8282 if (Feature == "+simd128") {
8283 SIMDLevel = std::max(SIMDLevel, SIMD128);
8286 if (Feature == "-simd128") {
8287 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1));
8291 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature
8292 << "-target-feature";
8297 bool setCPU(const std::string &Name) final {
8298 return llvm::StringSwitch<bool>(Name)
8300 .Case("bleeding-edge", true)
8301 .Case("generic", true)
8304 ArrayRef<Builtin::Info> getTargetBuiltins() const final {
8305 return llvm::makeArrayRef(BuiltinInfo,
8306 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin);
8308 BuiltinVaListKind getBuiltinVaListKind() const final {
8309 return VoidPtrBuiltinVaList;
8311 ArrayRef<const char *> getGCCRegNames() const final {
8314 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final {
8318 validateAsmConstraint(const char *&Name,
8319 TargetInfo::ConstraintInfo &Info) const final {
8322 const char *getClobbers() const final { return ""; }
8323 bool isCLZForZeroUndef() const final { return false; }
8324 bool hasInt128Type() const final { return true; }
8325 IntType getIntTypeByWidth(unsigned BitWidth,
8326 bool IsSigned) const final {
8327 // WebAssembly prefers long long for explicitly 64-bit integers.
8328 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
8329 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
8331 IntType getLeastIntTypeByWidth(unsigned BitWidth,
8332 bool IsSigned) const final {
8333 // WebAssembly uses long long for int_least64_t and int_fast64_t.
8334 return BitWidth == 64
8335 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
8336 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
8340 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = {
8341 #define BUILTIN(ID, TYPE, ATTRS) \
8342 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8343 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8344 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8345 #include "clang/Basic/BuiltinsWebAssembly.def"
8348 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo {
8350 explicit WebAssembly32TargetInfo(const llvm::Triple &T,
8351 const TargetOptions &Opts)
8352 : WebAssemblyTargetInfo(T, Opts) {
8353 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
8354 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128");
8358 void getTargetDefines(const LangOptions &Opts,
8359 MacroBuilder &Builder) const override {
8360 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
8361 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false);
8365 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo {
8367 explicit WebAssembly64TargetInfo(const llvm::Triple &T,
8368 const TargetOptions &Opts)
8369 : WebAssemblyTargetInfo(T, Opts) {
8370 LongAlign = LongWidth = 64;
8371 PointerAlign = PointerWidth = 64;
8372 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8373 SizeType = UnsignedLong;
8374 PtrDiffType = SignedLong;
8375 IntPtrType = SignedLong;
8376 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
8380 void getTargetDefines(const LangOptions &Opts,
8381 MacroBuilder &Builder) const override {
8382 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
8383 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false);
8387 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
8388 #define BUILTIN(ID, TYPE, ATTRS) \
8389 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8390 #include "clang/Basic/BuiltinsLe64.def"
8393 static const unsigned SPIRAddrSpaceMap[] = {
8397 2, // opencl_constant
8398 4, // opencl_generic
8403 class SPIRTargetInfo : public TargetInfo {
8405 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8406 : TargetInfo(Triple) {
8407 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
8408 "SPIR target must use unknown OS");
8409 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
8410 "SPIR target must use unknown environment type");
8411 TLSSupported = false;
8412 LongWidth = LongAlign = 64;
8413 AddrSpaceMap = &SPIRAddrSpaceMap;
8414 UseAddrSpaceMapMangling = true;
8415 // Define available target features
8416 // These must be defined in sorted order!
8417 NoAsmVariants = true;
8419 void getTargetDefines(const LangOptions &Opts,
8420 MacroBuilder &Builder) const override {
8421 DefineStd(Builder, "SPIR", Opts);
8423 bool hasFeature(StringRef Feature) const override {
8424 return Feature == "spir";
8427 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
8428 const char *getClobbers() const override { return ""; }
8429 ArrayRef<const char *> getGCCRegNames() const override { return None; }
8430 bool validateAsmConstraint(const char *&Name,
8431 TargetInfo::ConstraintInfo &info) const override {
8434 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8437 BuiltinVaListKind getBuiltinVaListKind() const override {
8438 return TargetInfo::VoidPtrBuiltinVaList;
8441 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
8442 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK
8446 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
8447 return CC_SpirFunction;
8450 void setSupportedOpenCLOpts() override {
8451 // Assume all OpenCL extensions and optional core features are supported
8452 // for SPIR since it is a generic target.
8453 getSupportedOpenCLOpts().supportAll();
8457 class SPIR32TargetInfo : public SPIRTargetInfo {
8459 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8460 : SPIRTargetInfo(Triple, Opts) {
8461 PointerWidth = PointerAlign = 32;
8462 SizeType = TargetInfo::UnsignedInt;
8463 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
8464 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
8465 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
8467 void getTargetDefines(const LangOptions &Opts,
8468 MacroBuilder &Builder) const override {
8469 DefineStd(Builder, "SPIR32", Opts);
8473 class SPIR64TargetInfo : public SPIRTargetInfo {
8475 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8476 : SPIRTargetInfo(Triple, Opts) {
8477 PointerWidth = PointerAlign = 64;
8478 SizeType = TargetInfo::UnsignedLong;
8479 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
8480 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
8481 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
8483 void getTargetDefines(const LangOptions &Opts,
8484 MacroBuilder &Builder) const override {
8485 DefineStd(Builder, "SPIR64", Opts);
8489 class XCoreTargetInfo : public TargetInfo {
8490 static const Builtin::Info BuiltinInfo[];
8492 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8493 : TargetInfo(Triple) {
8494 NoAsmVariants = true;
8497 DoubleAlign = LongDoubleAlign = 32;
8498 SizeType = UnsignedInt;
8499 PtrDiffType = SignedInt;
8500 IntPtrType = SignedInt;
8501 WCharType = UnsignedChar;
8502 WIntType = UnsignedInt;
8503 UseZeroLengthBitfieldAlignment = true;
8504 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
8505 "-f64:32-a:0:32-n32");
8507 void getTargetDefines(const LangOptions &Opts,
8508 MacroBuilder &Builder) const override {
8509 Builder.defineMacro("__XS1B__");
8511 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8512 return llvm::makeArrayRef(BuiltinInfo,
8513 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin);
8515 BuiltinVaListKind getBuiltinVaListKind() const override {
8516 return TargetInfo::VoidPtrBuiltinVaList;
8518 const char *getClobbers() const override {
8521 ArrayRef<const char *> getGCCRegNames() const override {
8522 static const char * const GCCRegNames[] = {
8523 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8524 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
8526 return llvm::makeArrayRef(GCCRegNames);
8528 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8531 bool validateAsmConstraint(const char *&Name,
8532 TargetInfo::ConstraintInfo &Info) const override {
8535 int getEHDataRegisterNumber(unsigned RegNo) const override {
8536 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
8537 return (RegNo < 2)? RegNo : -1;
8539 bool allowsLargerPreferedTypeAlignment() const override {
8544 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
8545 #define BUILTIN(ID, TYPE, ATTRS) \
8546 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8547 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8548 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8549 #include "clang/Basic/BuiltinsXCore.def"
8552 // x86_32 Android target
8553 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
8555 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8556 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) {
8558 LongDoubleWidth = 64;
8559 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
8563 // x86_64 Android target
8564 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
8566 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8567 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) {
8568 LongDoubleFormat = &llvm::APFloat::IEEEquad();
8571 bool useFloat128ManglingForLongDouble() const override {
8576 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes
8577 class RenderScript32TargetInfo : public ARMleTargetInfo {
8579 RenderScript32TargetInfo(const llvm::Triple &Triple,
8580 const TargetOptions &Opts)
8581 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(),
8583 Triple.getEnvironmentName()),
8585 IsRenderScriptTarget = true;
8586 LongWidth = LongAlign = 64;
8588 void getTargetDefines(const LangOptions &Opts,
8589 MacroBuilder &Builder) const override {
8590 Builder.defineMacro("__RENDERSCRIPT__");
8591 ARMleTargetInfo::getTargetDefines(Opts, Builder);
8595 // 64-bit RenderScript is aarch64
8596 class RenderScript64TargetInfo : public AArch64leTargetInfo {
8598 RenderScript64TargetInfo(const llvm::Triple &Triple,
8599 const TargetOptions &Opts)
8600 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(),
8602 Triple.getEnvironmentName()),
8604 IsRenderScriptTarget = true;
8607 void getTargetDefines(const LangOptions &Opts,
8608 MacroBuilder &Builder) const override {
8609 Builder.defineMacro("__RENDERSCRIPT__");
8610 AArch64leTargetInfo::getTargetDefines(Opts, Builder);
8614 /// Information about a specific microcontroller.
8617 const char *DefineName;
8620 // This list should be kept up-to-date with AVRDevices.td in LLVM.
8621 static ArrayRef<MCUInfo> AVRMcus = {
8622 { "at90s1200", "__AVR_AT90S1200__" },
8623 { "attiny11", "__AVR_ATtiny11__" },
8624 { "attiny12", "__AVR_ATtiny12__" },
8625 { "attiny15", "__AVR_ATtiny15__" },
8626 { "attiny28", "__AVR_ATtiny28__" },
8627 { "at90s2313", "__AVR_AT90S2313__" },
8628 { "at90s2323", "__AVR_AT90S2323__" },
8629 { "at90s2333", "__AVR_AT90S2333__" },
8630 { "at90s2343", "__AVR_AT90S2343__" },
8631 { "attiny22", "__AVR_ATtiny22__" },
8632 { "attiny26", "__AVR_ATtiny26__" },
8633 { "at86rf401", "__AVR_AT86RF401__" },
8634 { "at90s4414", "__AVR_AT90S4414__" },
8635 { "at90s4433", "__AVR_AT90S4433__" },
8636 { "at90s4434", "__AVR_AT90S4434__" },
8637 { "at90s8515", "__AVR_AT90S8515__" },
8638 { "at90c8534", "__AVR_AT90c8534__" },
8639 { "at90s8535", "__AVR_AT90S8535__" },
8640 { "ata5272", "__AVR_ATA5272__" },
8641 { "attiny13", "__AVR_ATtiny13__" },
8642 { "attiny13a", "__AVR_ATtiny13A__" },
8643 { "attiny2313", "__AVR_ATtiny2313__" },
8644 { "attiny2313a", "__AVR_ATtiny2313A__" },
8645 { "attiny24", "__AVR_ATtiny24__" },
8646 { "attiny24a", "__AVR_ATtiny24A__" },
8647 { "attiny4313", "__AVR_ATtiny4313__" },
8648 { "attiny44", "__AVR_ATtiny44__" },
8649 { "attiny44a", "__AVR_ATtiny44A__" },
8650 { "attiny84", "__AVR_ATtiny84__" },
8651 { "attiny84a", "__AVR_ATtiny84A__" },
8652 { "attiny25", "__AVR_ATtiny25__" },
8653 { "attiny45", "__AVR_ATtiny45__" },
8654 { "attiny85", "__AVR_ATtiny85__" },
8655 { "attiny261", "__AVR_ATtiny261__" },
8656 { "attiny261a", "__AVR_ATtiny261A__" },
8657 { "attiny461", "__AVR_ATtiny461__" },
8658 { "attiny461a", "__AVR_ATtiny461A__" },
8659 { "attiny861", "__AVR_ATtiny861__" },
8660 { "attiny861a", "__AVR_ATtiny861A__" },
8661 { "attiny87", "__AVR_ATtiny87__" },
8662 { "attiny43u", "__AVR_ATtiny43U__" },
8663 { "attiny48", "__AVR_ATtiny48__" },
8664 { "attiny88", "__AVR_ATtiny88__" },
8665 { "attiny828", "__AVR_ATtiny828__" },
8666 { "at43usb355", "__AVR_AT43USB355__" },
8667 { "at76c711", "__AVR_AT76C711__" },
8668 { "atmega103", "__AVR_ATmega103__" },
8669 { "at43usb320", "__AVR_AT43USB320__" },
8670 { "attiny167", "__AVR_ATtiny167__" },
8671 { "at90usb82", "__AVR_AT90USB82__" },
8672 { "at90usb162", "__AVR_AT90USB162__" },
8673 { "ata5505", "__AVR_ATA5505__" },
8674 { "atmega8u2", "__AVR_ATmega8U2__" },
8675 { "atmega16u2", "__AVR_ATmega16U2__" },
8676 { "atmega32u2", "__AVR_ATmega32U2__" },
8677 { "attiny1634", "__AVR_ATtiny1634__" },
8678 { "atmega8", "__AVR_ATmega8__" },
8679 { "ata6289", "__AVR_ATA6289__" },
8680 { "atmega8a", "__AVR_ATmega8A__" },
8681 { "ata6285", "__AVR_ATA6285__" },
8682 { "ata6286", "__AVR_ATA6286__" },
8683 { "atmega48", "__AVR_ATmega48__" },
8684 { "atmega48a", "__AVR_ATmega48A__" },
8685 { "atmega48pa", "__AVR_ATmega48PA__" },
8686 { "atmega48p", "__AVR_ATmega48P__" },
8687 { "atmega88", "__AVR_ATmega88__" },
8688 { "atmega88a", "__AVR_ATmega88A__" },
8689 { "atmega88p", "__AVR_ATmega88P__" },
8690 { "atmega88pa", "__AVR_ATmega88PA__" },
8691 { "atmega8515", "__AVR_ATmega8515__" },
8692 { "atmega8535", "__AVR_ATmega8535__" },
8693 { "atmega8hva", "__AVR_ATmega8HVA__" },
8694 { "at90pwm1", "__AVR_AT90PWM1__" },
8695 { "at90pwm2", "__AVR_AT90PWM2__" },
8696 { "at90pwm2b", "__AVR_AT90PWM2B__" },
8697 { "at90pwm3", "__AVR_AT90PWM3__" },
8698 { "at90pwm3b", "__AVR_AT90PWM3B__" },
8699 { "at90pwm81", "__AVR_AT90PWM81__" },
8700 { "ata5790", "__AVR_ATA5790__" },
8701 { "ata5795", "__AVR_ATA5795__" },
8702 { "atmega16", "__AVR_ATmega16__" },
8703 { "atmega16a", "__AVR_ATmega16A__" },
8704 { "atmega161", "__AVR_ATmega161__" },
8705 { "atmega162", "__AVR_ATmega162__" },
8706 { "atmega163", "__AVR_ATmega163__" },
8707 { "atmega164a", "__AVR_ATmega164A__" },
8708 { "atmega164p", "__AVR_ATmega164P__" },
8709 { "atmega164pa", "__AVR_ATmega164PA__" },
8710 { "atmega165", "__AVR_ATmega165__" },
8711 { "atmega165a", "__AVR_ATmega165A__" },
8712 { "atmega165p", "__AVR_ATmega165P__" },
8713 { "atmega165pa", "__AVR_ATmega165PA__" },
8714 { "atmega168", "__AVR_ATmega168__" },
8715 { "atmega168a", "__AVR_ATmega168A__" },
8716 { "atmega168p", "__AVR_ATmega168P__" },
8717 { "atmega168pa", "__AVR_ATmega168PA__" },
8718 { "atmega169", "__AVR_ATmega169__" },
8719 { "atmega169a", "__AVR_ATmega169A__" },
8720 { "atmega169p", "__AVR_ATmega169P__" },
8721 { "atmega169pa", "__AVR_ATmega169PA__" },
8722 { "atmega32", "__AVR_ATmega32__" },
8723 { "atmega32a", "__AVR_ATmega32A__" },
8724 { "atmega323", "__AVR_ATmega323__" },
8725 { "atmega324a", "__AVR_ATmega324A__" },
8726 { "atmega324p", "__AVR_ATmega324P__" },
8727 { "atmega324pa", "__AVR_ATmega324PA__" },
8728 { "atmega325", "__AVR_ATmega325__" },
8729 { "atmega325a", "__AVR_ATmega325A__" },
8730 { "atmega325p", "__AVR_ATmega325P__" },
8731 { "atmega325pa", "__AVR_ATmega325PA__" },
8732 { "atmega3250", "__AVR_ATmega3250__" },
8733 { "atmega3250a", "__AVR_ATmega3250A__" },
8734 { "atmega3250p", "__AVR_ATmega3250P__" },
8735 { "atmega3250pa", "__AVR_ATmega3250PA__" },
8736 { "atmega328", "__AVR_ATmega328__" },
8737 { "atmega328p", "__AVR_ATmega328P__" },
8738 { "atmega329", "__AVR_ATmega329__" },
8739 { "atmega329a", "__AVR_ATmega329A__" },
8740 { "atmega329p", "__AVR_ATmega329P__" },
8741 { "atmega329pa", "__AVR_ATmega329PA__" },
8742 { "atmega3290", "__AVR_ATmega3290__" },
8743 { "atmega3290a", "__AVR_ATmega3290A__" },
8744 { "atmega3290p", "__AVR_ATmega3290P__" },
8745 { "atmega3290pa", "__AVR_ATmega3290PA__" },
8746 { "atmega406", "__AVR_ATmega406__" },
8747 { "atmega64", "__AVR_ATmega64__" },
8748 { "atmega64a", "__AVR_ATmega64A__" },
8749 { "atmega640", "__AVR_ATmega640__" },
8750 { "atmega644", "__AVR_ATmega644__" },
8751 { "atmega644a", "__AVR_ATmega644A__" },
8752 { "atmega644p", "__AVR_ATmega644P__" },
8753 { "atmega644pa", "__AVR_ATmega644PA__" },
8754 { "atmega645", "__AVR_ATmega645__" },
8755 { "atmega645a", "__AVR_ATmega645A__" },
8756 { "atmega645p", "__AVR_ATmega645P__" },
8757 { "atmega649", "__AVR_ATmega649__" },
8758 { "atmega649a", "__AVR_ATmega649A__" },
8759 { "atmega649p", "__AVR_ATmega649P__" },
8760 { "atmega6450", "__AVR_ATmega6450__" },
8761 { "atmega6450a", "__AVR_ATmega6450A__" },
8762 { "atmega6450p", "__AVR_ATmega6450P__" },
8763 { "atmega6490", "__AVR_ATmega6490__" },
8764 { "atmega6490a", "__AVR_ATmega6490A__" },
8765 { "atmega6490p", "__AVR_ATmega6490P__" },
8766 { "atmega64rfr2", "__AVR_ATmega64RFR2__" },
8767 { "atmega644rfr2", "__AVR_ATmega644RFR2__" },
8768 { "atmega16hva", "__AVR_ATmega16HVA__" },
8769 { "atmega16hva2", "__AVR_ATmega16HVA2__" },
8770 { "atmega16hvb", "__AVR_ATmega16HVB__" },
8771 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" },
8772 { "atmega32hvb", "__AVR_ATmega32HVB__" },
8773 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" },
8774 { "atmega64hve", "__AVR_ATmega64HVE__" },
8775 { "at90can32", "__AVR_AT90CAN32__" },
8776 { "at90can64", "__AVR_AT90CAN64__" },
8777 { "at90pwm161", "__AVR_AT90PWM161__" },
8778 { "at90pwm216", "__AVR_AT90PWM216__" },
8779 { "at90pwm316", "__AVR_AT90PWM316__" },
8780 { "atmega32c1", "__AVR_ATmega32C1__" },
8781 { "atmega64c1", "__AVR_ATmega64C1__" },
8782 { "atmega16m1", "__AVR_ATmega16M1__" },
8783 { "atmega32m1", "__AVR_ATmega32M1__" },
8784 { "atmega64m1", "__AVR_ATmega64M1__" },
8785 { "atmega16u4", "__AVR_ATmega16U4__" },
8786 { "atmega32u4", "__AVR_ATmega32U4__" },
8787 { "atmega32u6", "__AVR_ATmega32U6__" },
8788 { "at90usb646", "__AVR_AT90USB646__" },
8789 { "at90usb647", "__AVR_AT90USB647__" },
8790 { "at90scr100", "__AVR_AT90SCR100__" },
8791 { "at94k", "__AVR_AT94K__" },
8792 { "m3000", "__AVR_AT000__" },
8793 { "atmega128", "__AVR_ATmega128__" },
8794 { "atmega128a", "__AVR_ATmega128A__" },
8795 { "atmega1280", "__AVR_ATmega1280__" },
8796 { "atmega1281", "__AVR_ATmega1281__" },
8797 { "atmega1284", "__AVR_ATmega1284__" },
8798 { "atmega1284p", "__AVR_ATmega1284P__" },
8799 { "atmega128rfa1", "__AVR_ATmega128RFA1__" },
8800 { "atmega128rfr2", "__AVR_ATmega128RFR2__" },
8801 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" },
8802 { "at90can128", "__AVR_AT90CAN128__" },
8803 { "at90usb1286", "__AVR_AT90USB1286__" },
8804 { "at90usb1287", "__AVR_AT90USB1287__" },
8805 { "atmega2560", "__AVR_ATmega2560__" },
8806 { "atmega2561", "__AVR_ATmega2561__" },
8807 { "atmega256rfr2", "__AVR_ATmega256RFR2__" },
8808 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" },
8809 { "atxmega16a4", "__AVR_ATxmega16A4__" },
8810 { "atxmega16a4u", "__AVR_ATxmega16a4U__" },
8811 { "atxmega16c4", "__AVR_ATxmega16C4__" },
8812 { "atxmega16d4", "__AVR_ATxmega16D4__" },
8813 { "atxmega32a4", "__AVR_ATxmega32A4__" },
8814 { "atxmega32a4u", "__AVR_ATxmega32A4U__" },
8815 { "atxmega32c4", "__AVR_ATxmega32C4__" },
8816 { "atxmega32d4", "__AVR_ATxmega32D4__" },
8817 { "atxmega32e5", "__AVR_ATxmega32E5__" },
8818 { "atxmega16e5", "__AVR_ATxmega16E5__" },
8819 { "atxmega8e5", "__AVR_ATxmega8E5__" },
8820 { "atxmega32x1", "__AVR_ATxmega32X1__" },
8821 { "atxmega64a3", "__AVR_ATxmega64A3__" },
8822 { "atxmega64a3u", "__AVR_ATxmega64A3U__" },
8823 { "atxmega64a4u", "__AVR_ATxmega64A4U__" },
8824 { "atxmega64b1", "__AVR_ATxmega64B1__" },
8825 { "atxmega64b3", "__AVR_ATxmega64B3__" },
8826 { "atxmega64c3", "__AVR_ATxmega64C3__" },
8827 { "atxmega64d3", "__AVR_ATxmega64D3__" },
8828 { "atxmega64d4", "__AVR_ATxmega64D4__" },
8829 { "atxmega64a1", "__AVR_ATxmega64A1__" },
8830 { "atxmega64a1u", "__AVR_ATxmega64A1U__" },
8831 { "atxmega128a3", "__AVR_ATxmega128A3__" },
8832 { "atxmega128a3u", "__AVR_ATxmega128A3U__" },
8833 { "atxmega128b1", "__AVR_ATxmega128B1__" },
8834 { "atxmega128b3", "__AVR_ATxmega128B3__" },
8835 { "atxmega128c3", "__AVR_ATxmega128C3__" },
8836 { "atxmega128d3", "__AVR_ATxmega128D3__" },
8837 { "atxmega128d4", "__AVR_ATxmega128D4__" },
8838 { "atxmega192a3", "__AVR_ATxmega192A3__" },
8839 { "atxmega192a3u", "__AVR_ATxmega192A3U__" },
8840 { "atxmega192c3", "__AVR_ATxmega192C3__" },
8841 { "atxmega192d3", "__AVR_ATxmega192D3__" },
8842 { "atxmega256a3", "__AVR_ATxmega256A3__" },
8843 { "atxmega256a3u", "__AVR_ATxmega256A3U__" },
8844 { "atxmega256a3b", "__AVR_ATxmega256A3B__" },
8845 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" },
8846 { "atxmega256c3", "__AVR_ATxmega256C3__" },
8847 { "atxmega256d3", "__AVR_ATxmega256D3__" },
8848 { "atxmega384c3", "__AVR_ATxmega384C3__" },
8849 { "atxmega384d3", "__AVR_ATxmega384D3__" },
8850 { "atxmega128a1", "__AVR_ATxmega128A1__" },
8851 { "atxmega128a1u", "__AVR_ATxmega128A1U__" },
8852 { "atxmega128a4u", "__AVR_ATxmega128a4U__" },
8853 { "attiny4", "__AVR_ATtiny4__" },
8854 { "attiny5", "__AVR_ATtiny5__" },
8855 { "attiny9", "__AVR_ATtiny9__" },
8856 { "attiny10", "__AVR_ATtiny10__" },
8857 { "attiny20", "__AVR_ATtiny20__" },
8858 { "attiny40", "__AVR_ATtiny40__" },
8859 { "attiny102", "__AVR_ATtiny102__" },
8860 { "attiny104", "__AVR_ATtiny104__" },
8864 class AVRTargetInfo : public TargetInfo {
8866 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8867 : TargetInfo(Triple) {
8868 TLSSupported = false;
8878 DefaultAlignForAttributeAligned = 8;
8885 DoubleFormat = &llvm::APFloat::IEEEsingle();
8886 LongDoubleWidth = 32;
8887 LongDoubleAlign = 8;
8888 LongDoubleFormat = &llvm::APFloat::IEEEsingle();
8889 SizeType = UnsignedInt;
8890 PtrDiffType = SignedInt;
8891 IntPtrType = SignedInt;
8892 Char16Type = UnsignedInt;
8893 WCharType = SignedInt;
8894 WIntType = SignedInt;
8895 Char32Type = UnsignedLong;
8896 SigAtomicType = SignedChar;
8897 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64"
8898 "-f32:32:32-f64:64:64-n8");
8901 void getTargetDefines(const LangOptions &Opts,
8902 MacroBuilder &Builder) const override {
8903 Builder.defineMacro("AVR");
8904 Builder.defineMacro("__AVR");
8905 Builder.defineMacro("__AVR__");
8907 if (!this->CPU.empty()) {
8908 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(),
8909 [&](const MCUInfo &Info) { return Info.Name == this->CPU; });
8911 if (It != AVRMcus.end())
8912 Builder.defineMacro(It->DefineName);
8916 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8920 BuiltinVaListKind getBuiltinVaListKind() const override {
8921 return TargetInfo::VoidPtrBuiltinVaList;
8924 const char *getClobbers() const override {
8928 ArrayRef<const char *> getGCCRegNames() const override {
8929 static const char * const GCCRegNames[] = {
8930 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8931 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8932 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8933 "r24", "r25", "X", "Y", "Z", "SP"
8935 return llvm::makeArrayRef(GCCRegNames);
8938 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8942 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
8943 static const TargetInfo::AddlRegName AddlRegNames[] = {
8944 { { "r26", "r27"}, 26 },
8945 { { "r28", "r29"}, 27 },
8946 { { "r30", "r31"}, 28 },
8947 { { "SPL", "SPH"}, 29 },
8949 return llvm::makeArrayRef(AddlRegNames);
8952 bool validateAsmConstraint(const char *&Name,
8953 TargetInfo::ConstraintInfo &Info) const override {
8954 // There aren't any multi-character AVR specific constraints.
8955 if (StringRef(Name).size() > 1) return false;
8958 default: return false;
8959 case 'a': // Simple upper registers
8960 case 'b': // Base pointer registers pairs
8961 case 'd': // Upper register
8962 case 'l': // Lower registers
8963 case 'e': // Pointer register pairs
8964 case 'q': // Stack pointer register
8965 case 'r': // Any register
8966 case 'w': // Special upper register pairs
8967 case 't': // Temporary register
8968 case 'x': case 'X': // Pointer register pair X
8969 case 'y': case 'Y': // Pointer register pair Y
8970 case 'z': case 'Z': // Pointer register pair Z
8971 Info.setAllowsRegister();
8973 case 'I': // 6-bit positive integer constant
8974 Info.setRequiresImmediate(0, 63);
8976 case 'J': // 6-bit negative integer constant
8977 Info.setRequiresImmediate(-63, 0);
8979 case 'K': // Integer constant (Range: 2)
8980 Info.setRequiresImmediate(2);
8982 case 'L': // Integer constant (Range: 0)
8983 Info.setRequiresImmediate(0);
8985 case 'M': // 8-bit integer constant
8986 Info.setRequiresImmediate(0, 0xff);
8988 case 'N': // Integer constant (Range: -1)
8989 Info.setRequiresImmediate(-1);
8991 case 'O': // Integer constant (Range: 8, 16, 24)
8992 Info.setRequiresImmediate({8, 16, 24});
8994 case 'P': // Integer constant (Range: 1)
8995 Info.setRequiresImmediate(1);
8997 case 'R': // Integer constant (Range: -6 to 5)
8998 Info.setRequiresImmediate(-6, 5);
9000 case 'G': // Floating point constant
9001 case 'Q': // A memory address based on Y or Z pointer with displacement.
9008 IntType getIntTypeByWidth(unsigned BitWidth,
9009 bool IsSigned) const final {
9010 // AVR prefers int for 16-bit integers.
9011 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt)
9012 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
9015 IntType getLeastIntTypeByWidth(unsigned BitWidth,
9016 bool IsSigned) const final {
9017 // AVR uses int for int_least16_t and int_fast16_t.
9018 return BitWidth == 16
9019 ? (IsSigned ? SignedInt : UnsignedInt)
9020 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
9023 bool setCPU(const std::string &Name) override {
9024 bool IsFamily = llvm::StringSwitch<bool>(Name)
9027 .Case("avr25", true)
9029 .Case("avr31", true)
9030 .Case("avr35", true)
9033 .Case("avr51", true)
9035 .Case("avrxmega1", true)
9036 .Case("avrxmega2", true)
9037 .Case("avrxmega3", true)
9038 .Case("avrxmega4", true)
9039 .Case("avrxmega5", true)
9040 .Case("avrxmega6", true)
9041 .Case("avrxmega7", true)
9042 .Case("avrtiny", true)
9045 if (IsFamily) this->CPU = Name;
9047 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(),
9048 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end();
9050 if (IsMCU) this->CPU = Name;
9052 return IsFamily || IsMCU;
9059 } // end anonymous namespace
9061 //===----------------------------------------------------------------------===//
9063 //===----------------------------------------------------------------------===//
9065 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
9066 const TargetOptions &Opts) {
9067 llvm::Triple::OSType os = Triple.getOS();
9069 switch (Triple.getArch()) {
9073 case llvm::Triple::xcore:
9074 return new XCoreTargetInfo(Triple, Opts);
9076 case llvm::Triple::hexagon:
9077 return new HexagonTargetInfo(Triple, Opts);
9079 case llvm::Triple::lanai:
9080 return new LanaiTargetInfo(Triple, Opts);
9082 case llvm::Triple::aarch64:
9083 if (Triple.isOSDarwin())
9084 return new DarwinAArch64TargetInfo(Triple, Opts);
9087 case llvm::Triple::CloudABI:
9088 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts);
9089 case llvm::Triple::FreeBSD:
9090 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9091 case llvm::Triple::Fuchsia:
9092 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9093 case llvm::Triple::Linux:
9094 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9095 case llvm::Triple::NetBSD:
9096 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9097 case llvm::Triple::OpenBSD:
9098 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9100 return new AArch64leTargetInfo(Triple, Opts);
9103 case llvm::Triple::aarch64_be:
9105 case llvm::Triple::FreeBSD:
9106 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9107 case llvm::Triple::Fuchsia:
9108 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9109 case llvm::Triple::Linux:
9110 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9111 case llvm::Triple::NetBSD:
9112 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9114 return new AArch64beTargetInfo(Triple, Opts);
9117 case llvm::Triple::arm:
9118 case llvm::Triple::thumb:
9119 if (Triple.isOSBinFormatMachO())
9120 return new DarwinARMTargetInfo(Triple, Opts);
9123 case llvm::Triple::CloudABI:
9124 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts);
9125 case llvm::Triple::Linux:
9126 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts);
9127 case llvm::Triple::FreeBSD:
9128 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
9129 case llvm::Triple::NetBSD:
9130 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
9131 case llvm::Triple::OpenBSD:
9132 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
9133 case llvm::Triple::Bitrig:
9134 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts);
9135 case llvm::Triple::RTEMS:
9136 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts);
9137 case llvm::Triple::NaCl:
9138 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts);
9139 case llvm::Triple::Win32:
9140 switch (Triple.getEnvironment()) {
9141 case llvm::Triple::Cygnus:
9142 return new CygwinARMTargetInfo(Triple, Opts);
9143 case llvm::Triple::GNU:
9144 return new MinGWARMTargetInfo(Triple, Opts);
9145 case llvm::Triple::Itanium:
9146 return new ItaniumWindowsARMleTargetInfo(Triple, Opts);
9147 case llvm::Triple::MSVC:
9148 default: // Assume MSVC for unknown environments
9149 return new MicrosoftARMleTargetInfo(Triple, Opts);
9152 return new ARMleTargetInfo(Triple, Opts);
9155 case llvm::Triple::armeb:
9156 case llvm::Triple::thumbeb:
9157 if (Triple.isOSDarwin())
9158 return new DarwinARMTargetInfo(Triple, Opts);
9161 case llvm::Triple::Linux:
9162 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9163 case llvm::Triple::FreeBSD:
9164 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9165 case llvm::Triple::NetBSD:
9166 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9167 case llvm::Triple::OpenBSD:
9168 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9169 case llvm::Triple::Bitrig:
9170 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9171 case llvm::Triple::RTEMS:
9172 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9173 case llvm::Triple::NaCl:
9174 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9176 return new ARMbeTargetInfo(Triple, Opts);
9179 case llvm::Triple::avr:
9180 return new AVRTargetInfo(Triple, Opts);
9181 case llvm::Triple::bpfeb:
9182 case llvm::Triple::bpfel:
9183 return new BPFTargetInfo(Triple, Opts);
9185 case llvm::Triple::msp430:
9186 return new MSP430TargetInfo(Triple, Opts);
9188 case llvm::Triple::mips:
9190 case llvm::Triple::Linux:
9191 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9192 case llvm::Triple::RTEMS:
9193 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9194 case llvm::Triple::FreeBSD:
9195 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9196 case llvm::Triple::NetBSD:
9197 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9199 return new MipsTargetInfo(Triple, Opts);
9202 case llvm::Triple::mipsel:
9204 case llvm::Triple::Linux:
9205 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9206 case llvm::Triple::RTEMS:
9207 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9208 case llvm::Triple::FreeBSD:
9209 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9210 case llvm::Triple::NetBSD:
9211 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9212 case llvm::Triple::NaCl:
9213 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts);
9215 return new MipsTargetInfo(Triple, Opts);
9218 case llvm::Triple::mips64:
9220 case llvm::Triple::Linux:
9221 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9222 case llvm::Triple::RTEMS:
9223 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9224 case llvm::Triple::FreeBSD:
9225 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9226 case llvm::Triple::NetBSD:
9227 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9228 case llvm::Triple::OpenBSD:
9229 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9231 return new MipsTargetInfo(Triple, Opts);
9234 case llvm::Triple::mips64el:
9236 case llvm::Triple::Linux:
9237 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9238 case llvm::Triple::RTEMS:
9239 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9240 case llvm::Triple::FreeBSD:
9241 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9242 case llvm::Triple::NetBSD:
9243 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9244 case llvm::Triple::OpenBSD:
9245 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9247 return new MipsTargetInfo(Triple, Opts);
9250 case llvm::Triple::le32:
9252 case llvm::Triple::NaCl:
9253 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts);
9258 case llvm::Triple::le64:
9259 return new Le64TargetInfo(Triple, Opts);
9261 case llvm::Triple::ppc:
9262 if (Triple.isOSDarwin())
9263 return new DarwinPPC32TargetInfo(Triple, Opts);
9265 case llvm::Triple::Linux:
9266 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts);
9267 case llvm::Triple::FreeBSD:
9268 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
9269 case llvm::Triple::NetBSD:
9270 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
9271 case llvm::Triple::OpenBSD:
9272 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
9273 case llvm::Triple::RTEMS:
9274 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts);
9276 return new PPC32TargetInfo(Triple, Opts);
9279 case llvm::Triple::ppc64:
9280 if (Triple.isOSDarwin())
9281 return new DarwinPPC64TargetInfo(Triple, Opts);
9283 case llvm::Triple::Linux:
9284 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
9285 case llvm::Triple::Lv2:
9286 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts);
9287 case llvm::Triple::FreeBSD:
9288 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
9289 case llvm::Triple::NetBSD:
9290 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
9292 return new PPC64TargetInfo(Triple, Opts);
9295 case llvm::Triple::ppc64le:
9297 case llvm::Triple::Linux:
9298 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
9299 case llvm::Triple::NetBSD:
9300 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
9302 return new PPC64TargetInfo(Triple, Opts);
9305 case llvm::Triple::nvptx:
9306 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32);
9307 case llvm::Triple::nvptx64:
9308 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64);
9310 case llvm::Triple::amdgcn:
9311 case llvm::Triple::r600:
9312 return new AMDGPUTargetInfo(Triple, Opts);
9314 case llvm::Triple::sparc:
9316 case llvm::Triple::Linux:
9317 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9318 case llvm::Triple::Solaris:
9319 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9320 case llvm::Triple::NetBSD:
9321 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9322 case llvm::Triple::OpenBSD:
9323 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9324 case llvm::Triple::RTEMS:
9325 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9327 return new SparcV8TargetInfo(Triple, Opts);
9330 // The 'sparcel' architecture copies all the above cases except for Solaris.
9331 case llvm::Triple::sparcel:
9333 case llvm::Triple::Linux:
9334 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9335 case llvm::Triple::NetBSD:
9336 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9337 case llvm::Triple::OpenBSD:
9338 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9339 case llvm::Triple::RTEMS:
9340 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9342 return new SparcV8elTargetInfo(Triple, Opts);
9345 case llvm::Triple::sparcv9:
9347 case llvm::Triple::Linux:
9348 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9349 case llvm::Triple::Solaris:
9350 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9351 case llvm::Triple::NetBSD:
9352 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9353 case llvm::Triple::OpenBSD:
9354 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9355 case llvm::Triple::FreeBSD:
9356 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9358 return new SparcV9TargetInfo(Triple, Opts);
9361 case llvm::Triple::systemz:
9363 case llvm::Triple::Linux:
9364 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts);
9366 return new SystemZTargetInfo(Triple, Opts);
9369 case llvm::Triple::tce:
9370 return new TCETargetInfo(Triple, Opts);
9372 case llvm::Triple::tcele:
9373 return new TCELETargetInfo(Triple, Opts);
9375 case llvm::Triple::x86:
9376 if (Triple.isOSDarwin())
9377 return new DarwinI386TargetInfo(Triple, Opts);
9380 case llvm::Triple::CloudABI:
9381 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts);
9382 case llvm::Triple::Linux: {
9383 switch (Triple.getEnvironment()) {
9385 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts);
9386 case llvm::Triple::Android:
9387 return new AndroidX86_32TargetInfo(Triple, Opts);
9390 case llvm::Triple::DragonFly:
9391 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
9392 case llvm::Triple::NetBSD:
9393 return new NetBSDI386TargetInfo(Triple, Opts);
9394 case llvm::Triple::OpenBSD:
9395 return new OpenBSDI386TargetInfo(Triple, Opts);
9396 case llvm::Triple::Bitrig:
9397 return new BitrigI386TargetInfo(Triple, Opts);
9398 case llvm::Triple::FreeBSD:
9399 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
9400 case llvm::Triple::KFreeBSD:
9401 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
9402 case llvm::Triple::Minix:
9403 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts);
9404 case llvm::Triple::Solaris:
9405 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts);
9406 case llvm::Triple::Win32: {
9407 switch (Triple.getEnvironment()) {
9408 case llvm::Triple::Cygnus:
9409 return new CygwinX86_32TargetInfo(Triple, Opts);
9410 case llvm::Triple::GNU:
9411 return new MinGWX86_32TargetInfo(Triple, Opts);
9412 case llvm::Triple::Itanium:
9413 case llvm::Triple::MSVC:
9414 default: // Assume MSVC for unknown environments
9415 return new MicrosoftX86_32TargetInfo(Triple, Opts);
9418 case llvm::Triple::Haiku:
9419 return new HaikuX86_32TargetInfo(Triple, Opts);
9420 case llvm::Triple::RTEMS:
9421 return new RTEMSX86_32TargetInfo(Triple, Opts);
9422 case llvm::Triple::NaCl:
9423 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts);
9424 case llvm::Triple::ELFIAMCU:
9425 return new MCUX86_32TargetInfo(Triple, Opts);
9427 return new X86_32TargetInfo(Triple, Opts);
9430 case llvm::Triple::x86_64:
9431 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
9432 return new DarwinX86_64TargetInfo(Triple, Opts);
9435 case llvm::Triple::CloudABI:
9436 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts);
9437 case llvm::Triple::Linux: {
9438 switch (Triple.getEnvironment()) {
9440 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts);
9441 case llvm::Triple::Android:
9442 return new AndroidX86_64TargetInfo(Triple, Opts);
9445 case llvm::Triple::DragonFly:
9446 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9447 case llvm::Triple::NetBSD:
9448 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9449 case llvm::Triple::OpenBSD:
9450 return new OpenBSDX86_64TargetInfo(Triple, Opts);
9451 case llvm::Triple::Bitrig:
9452 return new BitrigX86_64TargetInfo(Triple, Opts);
9453 case llvm::Triple::FreeBSD:
9454 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9455 case llvm::Triple::Fuchsia:
9456 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts);
9457 case llvm::Triple::KFreeBSD:
9458 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9459 case llvm::Triple::Solaris:
9460 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts);
9461 case llvm::Triple::Win32: {
9462 switch (Triple.getEnvironment()) {
9463 case llvm::Triple::Cygnus:
9464 return new CygwinX86_64TargetInfo(Triple, Opts);
9465 case llvm::Triple::GNU:
9466 return new MinGWX86_64TargetInfo(Triple, Opts);
9467 case llvm::Triple::MSVC:
9468 default: // Assume MSVC for unknown environments
9469 return new MicrosoftX86_64TargetInfo(Triple, Opts);
9472 case llvm::Triple::Haiku:
9473 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts);
9474 case llvm::Triple::NaCl:
9475 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts);
9476 case llvm::Triple::PS4:
9477 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts);
9479 return new X86_64TargetInfo(Triple, Opts);
9482 case llvm::Triple::spir: {
9483 if (Triple.getOS() != llvm::Triple::UnknownOS ||
9484 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
9486 return new SPIR32TargetInfo(Triple, Opts);
9488 case llvm::Triple::spir64: {
9489 if (Triple.getOS() != llvm::Triple::UnknownOS ||
9490 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
9492 return new SPIR64TargetInfo(Triple, Opts);
9494 case llvm::Triple::wasm32:
9495 if (Triple.getSubArch() != llvm::Triple::NoSubArch ||
9496 Triple.getVendor() != llvm::Triple::UnknownVendor ||
9497 Triple.getOS() != llvm::Triple::UnknownOS ||
9498 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment ||
9499 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm()))
9501 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts);
9502 case llvm::Triple::wasm64:
9503 if (Triple.getSubArch() != llvm::Triple::NoSubArch ||
9504 Triple.getVendor() != llvm::Triple::UnknownVendor ||
9505 Triple.getOS() != llvm::Triple::UnknownOS ||
9506 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment ||
9507 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm()))
9509 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts);
9511 case llvm::Triple::renderscript32:
9512 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts);
9513 case llvm::Triple::renderscript64:
9514 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts);
9518 /// CreateTargetInfo - Return the target info object for the specified target
9521 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
9522 const std::shared_ptr<TargetOptions> &Opts) {
9523 llvm::Triple Triple(Opts->Triple);
9525 // Construct the target
9526 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts));
9528 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
9531 Target->TargetOpts = Opts;
9533 // Set the target CPU if specified.
9534 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
9535 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
9539 // Set the target ABI if specified.
9540 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
9541 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
9545 // Set the fp math unit.
9546 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
9547 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
9551 // Compute the default target features, we need the target to handle this
9552 // because features may have dependencies on one another.
9553 llvm::StringMap<bool> Features;
9554 if (!Target->initFeatureMap(Features, Diags, Opts->CPU,
9555 Opts->FeaturesAsWritten))
9558 // Add the features to the compile options.
9559 Opts->Features.clear();
9560 for (const auto &F : Features)
9561 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str());
9563 if (!Target->handleTargetFeatures(Opts->Features, Diags))
9566 Target->setSupportedOpenCLOpts();
9567 Target->setOpenCLExtensionOpts();
9569 if (!Target->validateTarget(Diags))
9572 return Target.release();