1 //===--- Targets.cpp - Implement target feature support -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/Builtins.h"
16 #include "clang/Basic/Cuda.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetInfo.h"
22 #include "clang/Basic/TargetOptions.h"
23 #include "clang/Basic/Version.h"
24 #include "clang/Frontend/CodeGenOptions.h"
25 #include "llvm/ADT/APFloat.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/StringSwitch.h"
30 #include "llvm/ADT/Triple.h"
31 #include "llvm/MC/MCSectionMachO.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/TargetParser.h"
37 using namespace clang;
39 //===----------------------------------------------------------------------===//
40 // Common code shared among targets.
41 //===----------------------------------------------------------------------===//
43 /// DefineStd - Define a macro name and standard variants. For example if
44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
47 const LangOptions &Opts) {
48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
51 // in the user's namespace.
53 Builder.defineMacro(MacroName);
56 Builder.defineMacro("__" + MacroName);
59 Builder.defineMacro("__" + MacroName + "__");
62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
64 Builder.defineMacro("__" + CPUName);
65 Builder.defineMacro("__" + CPUName + "__");
67 Builder.defineMacro("__tune_" + CPUName + "__");
70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
71 const TargetOptions &Opts);
73 //===----------------------------------------------------------------------===//
74 // Defines specific to certain operating systems.
75 //===----------------------------------------------------------------------===//
78 template<typename TgtInfo>
79 class OSTargetInfo : public TgtInfo {
81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
82 MacroBuilder &Builder) const=0;
84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
85 : TgtInfo(Triple, Opts) {}
86 void getTargetDefines(const LangOptions &Opts,
87 MacroBuilder &Builder) const override {
88 TgtInfo::getTargetDefines(Opts, Builder);
89 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
95 template <typename Target>
96 class CloudABITargetInfo : public OSTargetInfo<Target> {
98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
99 MacroBuilder &Builder) const override {
100 Builder.defineMacro("__CloudABI__");
101 Builder.defineMacro("__ELF__");
103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
104 Builder.defineMacro("__STDC_ISO_10646__", "201206L");
105 Builder.defineMacro("__STDC_UTF_16__");
106 Builder.defineMacro("__STDC_UTF_32__");
110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
111 : OSTargetInfo<Target>(Triple, Opts) {}
114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
115 const llvm::Triple &Triple,
116 StringRef &PlatformName,
117 VersionTuple &PlatformMinVersion) {
118 Builder.defineMacro("__APPLE_CC__", "6000");
119 Builder.defineMacro("__APPLE__");
120 Builder.defineMacro("OBJC_NEW_PROPERTIES");
121 // AddressSanitizer doesn't play well with source fortification, which is on
122 // by default on Darwin.
123 if (Opts.Sanitize.has(SanitizerKind::Address))
124 Builder.defineMacro("_FORTIFY_SOURCE", "0");
126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode.
128 // __weak is always defined, for use in blocks and with objc pointers.
129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
130 Builder.defineMacro("__strong", "");
131 Builder.defineMacro("__unsafe_unretained", "");
135 Builder.defineMacro("__STATIC__");
137 Builder.defineMacro("__DYNAMIC__");
139 if (Opts.POSIXThreads)
140 Builder.defineMacro("_REENTRANT");
142 // Get the platform type and version number from the triple.
143 unsigned Maj, Min, Rev;
144 if (Triple.isMacOSX()) {
145 Triple.getMacOSXVersion(Maj, Min, Rev);
146 PlatformName = "macos";
148 Triple.getOSVersion(Maj, Min, Rev);
149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
152 // If -target arch-pc-win32-macho option specified, we're
153 // generating code for Win32 ABI. No need to emit
154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
155 if (PlatformName == "win32") {
156 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
160 // Set the appropriate OS version define.
161 if (Triple.isiOS()) {
162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
166 Str[1] = '0' + (Min / 10);
167 Str[2] = '0' + (Min % 10);
168 Str[3] = '0' + (Rev / 10);
169 Str[4] = '0' + (Rev % 10);
172 // Handle versions >= 10.
173 Str[0] = '0' + (Maj / 10);
174 Str[1] = '0' + (Maj % 10);
175 Str[2] = '0' + (Min / 10);
176 Str[3] = '0' + (Min % 10);
177 Str[4] = '0' + (Rev / 10);
178 Str[5] = '0' + (Rev % 10);
182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str);
184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
187 } else if (Triple.isWatchOS()) {
188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
191 Str[1] = '0' + (Min / 10);
192 Str[2] = '0' + (Min % 10);
193 Str[3] = '0' + (Rev / 10);
194 Str[4] = '0' + (Rev % 10);
196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str);
197 } else if (Triple.isMacOSX()) {
198 // Note that the Driver allows versions which aren't representable in the
199 // define (because we only get a single digit for the minor and micro
200 // revision numbers). So, we limit them to the maximum representable
202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
204 if (Maj < 10 || (Maj == 10 && Min < 10)) {
205 Str[0] = '0' + (Maj / 10);
206 Str[1] = '0' + (Maj % 10);
207 Str[2] = '0' + std::min(Min, 9U);
208 Str[3] = '0' + std::min(Rev, 9U);
211 // Handle versions > 10.9.
212 Str[0] = '0' + (Maj / 10);
213 Str[1] = '0' + (Maj % 10);
214 Str[2] = '0' + (Min / 10);
215 Str[3] = '0' + (Min % 10);
216 Str[4] = '0' + (Rev / 10);
217 Str[5] = '0' + (Rev % 10);
220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
223 // Tell users about the kernel if there is one.
224 if (Triple.isOSDarwin())
225 Builder.defineMacro("__MACH__");
227 // The Watch ABI uses Dwarf EH.
228 if(Triple.isWatchABI())
229 Builder.defineMacro("__ARM_DWARF_EH__");
231 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
234 template<typename Target>
235 class DarwinTargetInfo : public OSTargetInfo<Target> {
237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
238 MacroBuilder &Builder) const override {
239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
240 this->PlatformMinVersion);
244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
245 : OSTargetInfo<Target>(Triple, Opts) {
246 // By default, no TLS, and we whitelist permitted architecture/OS
248 this->TLSSupported = false;
250 if (Triple.isMacOSX())
251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7);
252 else if (Triple.isiOS()) {
253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards.
254 if (Triple.getArch() == llvm::Triple::x86_64 ||
255 Triple.getArch() == llvm::Triple::aarch64)
256 this->TLSSupported = !Triple.isOSVersionLT(8);
257 else if (Triple.getArch() == llvm::Triple::x86 ||
258 Triple.getArch() == llvm::Triple::arm ||
259 Triple.getArch() == llvm::Triple::thumb)
260 this->TLSSupported = !Triple.isOSVersionLT(9);
261 } else if (Triple.isWatchOS())
262 this->TLSSupported = !Triple.isOSVersionLT(2);
264 this->MCountName = "\01mcount";
267 std::string isValidSectionSpecifier(StringRef SR) const override {
268 // Let MCSectionMachO validate this.
269 StringRef Segment, Section;
270 unsigned TAA, StubSize;
272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
273 TAA, HasTAA, StubSize);
276 const char *getStaticInitSectionSpecifier() const override {
277 // FIXME: We should return 0 when building kexts.
278 return "__TEXT,__StaticInit,regular,pure_instructions";
281 /// Darwin does not support protected visibility. Darwin's "default"
282 /// is very similar to ELF's "protected"; Darwin requires a "weak"
283 /// attribute on declarations that can be dynamically replaced.
284 bool hasProtectedVisibility() const override {
288 unsigned getExnObjectAlignment() const override {
289 // The alignment of an exception object is 8-bytes for darwin since
290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned))
291 // and therefore doesn't guarantee 16-byte alignment.
297 // DragonFlyBSD Target
298 template<typename Target>
299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
302 MacroBuilder &Builder) const override {
303 // DragonFly defines; list based off of gcc output
304 Builder.defineMacro("__DragonFly__");
305 Builder.defineMacro("__DragonFly_cc_version", "100001");
306 Builder.defineMacro("__ELF__");
307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
308 Builder.defineMacro("__tune_i386__");
309 DefineStd(Builder, "unix", Opts);
312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
313 : OSTargetInfo<Target>(Triple, Opts) {
314 switch (Triple.getArch()) {
316 case llvm::Triple::x86:
317 case llvm::Triple::x86_64:
318 this->MCountName = ".mcount";
324 #ifndef FREEBSD_CC_VERSION
325 #define FREEBSD_CC_VERSION 0U
329 template<typename Target>
330 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
333 MacroBuilder &Builder) const override {
334 // FreeBSD defines; list based off of gcc output
336 unsigned Release = Triple.getOSMajorVersion();
339 unsigned CCVersion = FREEBSD_CC_VERSION;
341 CCVersion = Release * 100000U + 1U;
343 Builder.defineMacro("__FreeBSD__", Twine(Release));
344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion));
345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
346 DefineStd(Builder, "unix", Opts);
347 Builder.defineMacro("__ELF__");
349 // On FreeBSD, wchar_t contains the number of the code point as
350 // used by the character set of the locale. These character sets are
351 // not necessarily a superset of ASCII.
353 // FIXME: This is wrong; the macro refers to the numerical values
354 // of wchar_t *literals*, which are not locale-dependent. However,
355 // FreeBSD systems apparently depend on us getting this wrong, and
356 // setting this to 1 is conforming even if all the basic source
357 // character literals have the same encoding as char and wchar_t.
358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
362 : OSTargetInfo<Target>(Triple, Opts) {
363 switch (Triple.getArch()) {
365 case llvm::Triple::x86:
366 case llvm::Triple::x86_64:
367 this->MCountName = ".mcount";
369 case llvm::Triple::mips:
370 case llvm::Triple::mipsel:
371 case llvm::Triple::ppc:
372 case llvm::Triple::ppc64:
373 case llvm::Triple::ppc64le:
374 this->MCountName = "_mcount";
376 case llvm::Triple::arm:
377 this->MCountName = "__mcount";
383 // GNU/kFreeBSD Target
384 template<typename Target>
385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
388 MacroBuilder &Builder) const override {
389 // GNU/kFreeBSD defines; list based off of gcc output
391 DefineStd(Builder, "unix", Opts);
392 Builder.defineMacro("__FreeBSD_kernel__");
393 Builder.defineMacro("__GLIBC__");
394 Builder.defineMacro("__ELF__");
395 if (Opts.POSIXThreads)
396 Builder.defineMacro("_REENTRANT");
398 Builder.defineMacro("_GNU_SOURCE");
401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
402 : OSTargetInfo<Target>(Triple, Opts) {}
406 template<typename Target>
407 class HaikuTargetInfo : public OSTargetInfo<Target> {
409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
410 MacroBuilder &Builder) const override {
411 // Haiku defines; list based off of gcc output
412 Builder.defineMacro("__HAIKU__");
413 Builder.defineMacro("__ELF__");
414 DefineStd(Builder, "unix", Opts);
417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
418 : OSTargetInfo<Target>(Triple, Opts) {
419 this->SizeType = TargetInfo::UnsignedLong;
420 this->IntPtrType = TargetInfo::SignedLong;
421 this->PtrDiffType = TargetInfo::SignedLong;
422 this->ProcessIDType = TargetInfo::SignedLong;
423 this->TLSSupported = false;
429 template<typename Target>
430 class MinixTargetInfo : public OSTargetInfo<Target> {
432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
433 MacroBuilder &Builder) const override {
436 Builder.defineMacro("__minix", "3");
437 Builder.defineMacro("_EM_WSIZE", "4");
438 Builder.defineMacro("_EM_PSIZE", "4");
439 Builder.defineMacro("_EM_SSIZE", "2");
440 Builder.defineMacro("_EM_LSIZE", "4");
441 Builder.defineMacro("_EM_FSIZE", "4");
442 Builder.defineMacro("_EM_DSIZE", "8");
443 Builder.defineMacro("__ELF__");
444 DefineStd(Builder, "unix", Opts);
447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
448 : OSTargetInfo<Target>(Triple, Opts) {}
452 template<typename Target>
453 class LinuxTargetInfo : public OSTargetInfo<Target> {
455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
456 MacroBuilder &Builder) const override {
457 // Linux defines; list based off of gcc output
458 DefineStd(Builder, "unix", Opts);
459 DefineStd(Builder, "linux", Opts);
460 Builder.defineMacro("__gnu_linux__");
461 Builder.defineMacro("__ELF__");
462 if (Triple.isAndroid()) {
463 Builder.defineMacro("__ANDROID__", "1");
464 unsigned Maj, Min, Rev;
465 Triple.getEnvironmentVersion(Maj, Min, Rev);
466 this->PlatformName = "android";
467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
469 Builder.defineMacro("__ANDROID_API__", Twine(Maj));
471 if (Opts.POSIXThreads)
472 Builder.defineMacro("_REENTRANT");
474 Builder.defineMacro("_GNU_SOURCE");
475 if (this->HasFloat128)
476 Builder.defineMacro("__FLOAT128__");
479 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
480 : OSTargetInfo<Target>(Triple, Opts) {
481 this->WIntType = TargetInfo::UnsignedInt;
483 switch (Triple.getArch()) {
486 case llvm::Triple::ppc:
487 case llvm::Triple::ppc64:
488 case llvm::Triple::ppc64le:
489 this->MCountName = "_mcount";
491 case llvm::Triple::x86:
492 case llvm::Triple::x86_64:
493 case llvm::Triple::systemz:
494 this->HasFloat128 = true;
499 const char *getStaticInitSectionSpecifier() const override {
500 return ".text.startup";
505 template<typename Target>
506 class NetBSDTargetInfo : public OSTargetInfo<Target> {
508 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
509 MacroBuilder &Builder) const override {
510 // NetBSD defines; list based off of gcc output
511 Builder.defineMacro("__NetBSD__");
512 Builder.defineMacro("__unix__");
513 Builder.defineMacro("__ELF__");
514 if (Opts.POSIXThreads)
515 Builder.defineMacro("_REENTRANT");
517 switch (Triple.getArch()) {
520 case llvm::Triple::arm:
521 case llvm::Triple::armeb:
522 case llvm::Triple::thumb:
523 case llvm::Triple::thumbeb:
524 Builder.defineMacro("__ARM_DWARF_EH__");
529 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
530 : OSTargetInfo<Target>(Triple, Opts) {
531 this->MCountName = "_mcount";
536 template<typename Target>
537 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
539 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
540 MacroBuilder &Builder) const override {
541 // OpenBSD defines; list based off of gcc output
543 Builder.defineMacro("__OpenBSD__");
544 DefineStd(Builder, "unix", Opts);
545 Builder.defineMacro("__ELF__");
546 if (Opts.POSIXThreads)
547 Builder.defineMacro("_REENTRANT");
550 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
551 : OSTargetInfo<Target>(Triple, Opts) {
552 this->TLSSupported = false;
554 switch (Triple.getArch()) {
556 case llvm::Triple::x86:
557 case llvm::Triple::x86_64:
558 case llvm::Triple::arm:
559 case llvm::Triple::sparc:
560 this->MCountName = "__mcount";
562 case llvm::Triple::mips64:
563 case llvm::Triple::mips64el:
564 case llvm::Triple::ppc:
565 case llvm::Triple::sparcv9:
566 this->MCountName = "_mcount";
573 template<typename Target>
574 class BitrigTargetInfo : public OSTargetInfo<Target> {
576 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
577 MacroBuilder &Builder) const override {
578 // Bitrig defines; list based off of gcc output
580 Builder.defineMacro("__Bitrig__");
581 DefineStd(Builder, "unix", Opts);
582 Builder.defineMacro("__ELF__");
583 if (Opts.POSIXThreads)
584 Builder.defineMacro("_REENTRANT");
586 switch (Triple.getArch()) {
589 case llvm::Triple::arm:
590 case llvm::Triple::armeb:
591 case llvm::Triple::thumb:
592 case llvm::Triple::thumbeb:
593 Builder.defineMacro("__ARM_DWARF_EH__");
598 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
599 : OSTargetInfo<Target>(Triple, Opts) {
600 this->MCountName = "__mcount";
605 template<typename Target>
606 class PSPTargetInfo : public OSTargetInfo<Target> {
608 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
609 MacroBuilder &Builder) const override {
610 // PSP defines; list based on the output of the pspdev gcc toolchain.
611 Builder.defineMacro("PSP");
612 Builder.defineMacro("_PSP");
613 Builder.defineMacro("__psp__");
614 Builder.defineMacro("__ELF__");
617 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {}
621 template<typename Target>
622 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
624 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
625 MacroBuilder &Builder) const override {
627 Builder.defineMacro("__PPC__");
628 Builder.defineMacro("__PPU__");
629 Builder.defineMacro("__CELLOS_LV2__");
630 Builder.defineMacro("__ELF__");
631 Builder.defineMacro("__LP32__");
632 Builder.defineMacro("_ARCH_PPC64");
633 Builder.defineMacro("__powerpc64__");
636 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
637 : OSTargetInfo<Target>(Triple, Opts) {
638 this->LongWidth = this->LongAlign = 32;
639 this->PointerWidth = this->PointerAlign = 32;
640 this->IntMaxType = TargetInfo::SignedLongLong;
641 this->Int64Type = TargetInfo::SignedLongLong;
642 this->SizeType = TargetInfo::UnsignedInt;
643 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64");
647 template <typename Target>
648 class PS4OSTargetInfo : public OSTargetInfo<Target> {
650 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
651 MacroBuilder &Builder) const override {
652 Builder.defineMacro("__FreeBSD__", "9");
653 Builder.defineMacro("__FreeBSD_cc_version", "900001");
654 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
655 DefineStd(Builder, "unix", Opts);
656 Builder.defineMacro("__ELF__");
657 Builder.defineMacro("__ORBIS__");
660 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
661 : OSTargetInfo<Target>(Triple, Opts) {
662 this->WCharType = this->UnsignedShort;
664 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits).
665 this->MaxTLSAlign = 256;
667 // On PS4, do not honor explicit bit field alignment,
668 // as in "__attribute__((aligned(2))) int b : 1;".
669 this->UseExplicitBitFieldAlignment = false;
671 switch (Triple.getArch()) {
673 case llvm::Triple::x86_64:
674 this->MCountName = ".mcount";
681 template<typename Target>
682 class SolarisTargetInfo : public OSTargetInfo<Target> {
684 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
685 MacroBuilder &Builder) const override {
686 DefineStd(Builder, "sun", Opts);
687 DefineStd(Builder, "unix", Opts);
688 Builder.defineMacro("__ELF__");
689 Builder.defineMacro("__svr4__");
690 Builder.defineMacro("__SVR4");
691 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
692 // newer, but to 500 for everything else. feature_test.h has a check to
693 // ensure that you are not using C99 with an old version of X/Open or C89
694 // with a new version.
696 Builder.defineMacro("_XOPEN_SOURCE", "600");
698 Builder.defineMacro("_XOPEN_SOURCE", "500");
700 Builder.defineMacro("__C99FEATURES__");
701 Builder.defineMacro("_LARGEFILE_SOURCE");
702 Builder.defineMacro("_LARGEFILE64_SOURCE");
703 Builder.defineMacro("__EXTENSIONS__");
704 Builder.defineMacro("_REENTRANT");
707 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
708 : OSTargetInfo<Target>(Triple, Opts) {
709 this->WCharType = this->SignedInt;
710 // FIXME: WIntType should be SignedLong
715 template<typename Target>
716 class WindowsTargetInfo : public OSTargetInfo<Target> {
718 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
719 MacroBuilder &Builder) const override {
720 Builder.defineMacro("_WIN32");
722 void getVisualStudioDefines(const LangOptions &Opts,
723 MacroBuilder &Builder) const {
724 if (Opts.CPlusPlus) {
726 Builder.defineMacro("_CPPRTTI");
728 if (Opts.CXXExceptions)
729 Builder.defineMacro("_CPPUNWIND");
733 Builder.defineMacro("__BOOL_DEFINED");
735 if (!Opts.CharIsSigned)
736 Builder.defineMacro("_CHAR_UNSIGNED");
738 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
739 // but it works for now.
740 if (Opts.POSIXThreads)
741 Builder.defineMacro("_MT");
743 if (Opts.MSCompatibilityVersion) {
744 Builder.defineMacro("_MSC_VER",
745 Twine(Opts.MSCompatibilityVersion / 100000));
746 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
747 // FIXME We cannot encode the revision information into 32-bits
748 Builder.defineMacro("_MSC_BUILD", Twine(1));
750 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
751 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
753 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) {
754 if (Opts.CPlusPlus1z)
755 Builder.defineMacro("_MSVC_LANG", "201403L");
756 else if (Opts.CPlusPlus14)
757 Builder.defineMacro("_MSVC_LANG", "201402L");
761 if (Opts.MicrosoftExt) {
762 Builder.defineMacro("_MSC_EXTENSIONS");
764 if (Opts.CPlusPlus11) {
765 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
766 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
767 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
771 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
775 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
776 : OSTargetInfo<Target>(Triple, Opts) {}
779 template <typename Target>
780 class NaClTargetInfo : public OSTargetInfo<Target> {
782 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
783 MacroBuilder &Builder) const override {
784 if (Opts.POSIXThreads)
785 Builder.defineMacro("_REENTRANT");
787 Builder.defineMacro("_GNU_SOURCE");
789 DefineStd(Builder, "unix", Opts);
790 Builder.defineMacro("__ELF__");
791 Builder.defineMacro("__native_client__");
795 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
796 : OSTargetInfo<Target>(Triple, Opts) {
797 this->LongAlign = 32;
798 this->LongWidth = 32;
799 this->PointerAlign = 32;
800 this->PointerWidth = 32;
801 this->IntMaxType = TargetInfo::SignedLongLong;
802 this->Int64Type = TargetInfo::SignedLongLong;
803 this->DoubleAlign = 64;
804 this->LongDoubleWidth = 64;
805 this->LongDoubleAlign = 64;
806 this->LongLongWidth = 64;
807 this->LongLongAlign = 64;
808 this->SizeType = TargetInfo::UnsignedInt;
809 this->PtrDiffType = TargetInfo::SignedInt;
810 this->IntPtrType = TargetInfo::SignedInt;
811 // RegParmMax is inherited from the underlying architecture.
812 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble();
813 if (Triple.getArch() == llvm::Triple::arm) {
814 // Handled in ARM's setABI().
815 } else if (Triple.getArch() == llvm::Triple::x86) {
816 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128");
817 } else if (Triple.getArch() == llvm::Triple::x86_64) {
818 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128");
819 } else if (Triple.getArch() == llvm::Triple::mipsel) {
820 // Handled on mips' setDataLayout.
822 assert(Triple.getArch() == llvm::Triple::le32);
823 this->resetDataLayout("e-p:32:32-i64:64");
829 template<typename Target>
830 class FuchsiaTargetInfo : public OSTargetInfo<Target> {
832 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
833 MacroBuilder &Builder) const override {
834 Builder.defineMacro("__Fuchsia__");
835 Builder.defineMacro("__ELF__");
836 if (Opts.POSIXThreads)
837 Builder.defineMacro("_REENTRANT");
838 // Required by the libc++ locale support.
840 Builder.defineMacro("_GNU_SOURCE");
843 FuchsiaTargetInfo(const llvm::Triple &Triple,
844 const TargetOptions &Opts)
845 : OSTargetInfo<Target>(Triple, Opts) {
846 this->MCountName = "__mcount";
850 // WebAssembly target
851 template <typename Target>
852 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> {
853 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
854 MacroBuilder &Builder) const final {
855 // A common platform macro.
856 if (Opts.POSIXThreads)
857 Builder.defineMacro("_REENTRANT");
858 // Follow g++ convention and predefine _GNU_SOURCE for C++.
860 Builder.defineMacro("_GNU_SOURCE");
863 // As an optimization, group static init code together in a section.
864 const char *getStaticInitSectionSpecifier() const final {
865 return ".text.__startup";
869 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple,
870 const TargetOptions &Opts)
871 : OSTargetInfo<Target>(Triple, Opts) {
872 this->MCountName = "__mcount";
873 this->TheCXXABI.set(TargetCXXABI::WebAssembly);
877 //===----------------------------------------------------------------------===//
878 // Specific target implementations.
879 //===----------------------------------------------------------------------===//
881 // PPC abstract base class
882 class PPCTargetInfo : public TargetInfo {
883 static const Builtin::Info BuiltinInfo[];
884 static const char * const GCCRegNames[];
885 static const TargetInfo::GCCRegAlias GCCRegAliases[];
888 // Target cpu features.
903 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
904 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
905 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
906 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) {
907 SimdDefaultAlign = 128;
908 LongDoubleWidth = LongDoubleAlign = 128;
909 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
912 /// \brief Flags for architecture specific defines.
915 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
916 ArchDefinePpcgr = 1 << 1,
917 ArchDefinePpcsq = 1 << 2,
918 ArchDefine440 = 1 << 3,
919 ArchDefine603 = 1 << 4,
920 ArchDefine604 = 1 << 5,
921 ArchDefinePwr4 = 1 << 6,
922 ArchDefinePwr5 = 1 << 7,
923 ArchDefinePwr5x = 1 << 8,
924 ArchDefinePwr6 = 1 << 9,
925 ArchDefinePwr6x = 1 << 10,
926 ArchDefinePwr7 = 1 << 11,
927 ArchDefinePwr8 = 1 << 12,
928 ArchDefinePwr9 = 1 << 13,
929 ArchDefineA2 = 1 << 14,
930 ArchDefineA2q = 1 << 15
933 // Note: GCC recognizes the following additional cpus:
934 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
935 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
937 bool setCPU(const std::string &Name) override {
938 bool CPUKnown = llvm::StringSwitch<bool>(Name)
939 .Case("generic", true)
961 .Case("e500mc", true)
963 .Case("power3", true)
965 .Case("power4", true)
967 .Case("power5", true)
969 .Case("power5x", true)
971 .Case("power6", true)
973 .Case("power6x", true)
975 .Case("power7", true)
977 .Case("power8", true)
979 .Case("power9", true)
981 .Case("powerpc", true)
983 .Case("powerpc64", true)
985 .Case("powerpc64le", true)
986 .Case("ppc64le", true)
996 StringRef getABI() const override { return ABI; }
998 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
999 return llvm::makeArrayRef(BuiltinInfo,
1000 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin);
1003 bool isCLZForZeroUndef() const override { return false; }
1005 void getTargetDefines(const LangOptions &Opts,
1006 MacroBuilder &Builder) const override;
1009 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
1011 const std::vector<std::string> &FeaturesVec) const override;
1013 bool handleTargetFeatures(std::vector<std::string> &Features,
1014 DiagnosticsEngine &Diags) override;
1015 bool hasFeature(StringRef Feature) const override;
1016 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
1017 bool Enabled) const override;
1019 ArrayRef<const char *> getGCCRegNames() const override;
1020 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
1021 bool validateAsmConstraint(const char *&Name,
1022 TargetInfo::ConstraintInfo &Info) const override {
1024 default: return false;
1027 case 'b': // Base register
1028 case 'f': // Floating point register
1029 Info.setAllowsRegister();
1031 // FIXME: The following are added to allow parsing.
1032 // I just took a guess at what the actions should be.
1033 // Also, is more specific checking needed? I.e. specific registers?
1034 case 'd': // Floating point register (containing 64-bit value)
1035 case 'v': // Altivec vector register
1036 Info.setAllowsRegister();
1040 case 'd':// VSX vector register to hold vector double data
1041 case 'f':// VSX vector register to hold vector float data
1042 case 's':// VSX vector register to hold scalar float data
1043 case 'a':// Any VSX register
1044 case 'c':// An individual CR bit
1049 Info.setAllowsRegister();
1050 Name++; // Skip over 'w'.
1052 case 'h': // `MQ', `CTR', or `LINK' register
1053 case 'q': // `MQ' register
1054 case 'c': // `CTR' register
1055 case 'l': // `LINK' register
1056 case 'x': // `CR' register (condition register) number 0
1057 case 'y': // `CR' register (condition register)
1058 case 'z': // `XER[CA]' carry bit (part of the XER register)
1059 Info.setAllowsRegister();
1061 case 'I': // Signed 16-bit constant
1062 case 'J': // Unsigned 16-bit constant shifted left 16 bits
1063 // (use `L' instead for SImode constants)
1064 case 'K': // Unsigned 16-bit constant
1065 case 'L': // Signed 16-bit constant shifted left 16 bits
1066 case 'M': // Constant larger than 31
1067 case 'N': // Exact power of 2
1068 case 'P': // Constant whose negation is a signed 16-bit constant
1069 case 'G': // Floating point constant that can be loaded into a
1070 // register with one instruction per word
1071 case 'H': // Integer/Floating point constant that can be loaded
1072 // into a register using three instructions
1074 case 'm': // Memory operand. Note that on PowerPC targets, m can
1075 // include addresses that update the base register. It
1076 // is therefore only safe to use `m' in an asm statement
1077 // if that asm statement accesses the operand exactly once.
1078 // The asm statement must also use `%U<opno>' as a
1079 // placeholder for the "update" flag in the corresponding
1080 // load or store instruction. For example:
1081 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
1083 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
1084 // is not. Use es rather than m if you don't want the base
1085 // register to be updated.
1089 // es: A "stable" memory operand; that is, one which does not
1090 // include any automodification of the base register. Unlike
1091 // `m', this constraint can be used in asm statements that
1092 // might access the operand several times, or that might not
1093 // access it at all.
1094 Info.setAllowsMemory();
1095 Name++; // Skip over 'e'.
1097 case 'Q': // Memory operand that is an offset from a register (it is
1098 // usually better to use `m' or `es' in asm statements)
1099 case 'Z': // Memory operand that is an indexed or indirect from a
1100 // register (it is usually better to use `m' or `es' in
1102 Info.setAllowsMemory();
1103 Info.setAllowsRegister();
1105 case 'R': // AIX TOC entry
1106 case 'a': // Address operand that is an indexed or indirect from a
1107 // register (`p' is preferable for asm statements)
1108 case 'S': // Constant suitable as a 64-bit mask operand
1109 case 'T': // Constant suitable as a 32-bit mask operand
1110 case 'U': // System V Release 4 small data area reference
1111 case 't': // AND masks that can be performed by two rldic{l, r}
1113 case 'W': // Vector constant that does not require memory
1114 case 'j': // Vector constant that is all zeros.
1120 std::string convertConstraint(const char *&Constraint) const override {
1122 switch (*Constraint) {
1125 // Two-character constraint; add "^" hint for later parsing.
1126 R = std::string("^") + std::string(Constraint, 2);
1130 return TargetInfo::convertConstraint(Constraint);
1134 const char *getClobbers() const override {
1137 int getEHDataRegisterNumber(unsigned RegNo) const override {
1138 if (RegNo == 0) return 3;
1139 if (RegNo == 1) return 4;
1143 bool hasSjLjLowering() const override {
1147 bool useFloat128ManglingForLongDouble() const override {
1148 return LongDoubleWidth == 128 &&
1149 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() &&
1150 getTriple().isOSBinFormatELF();
1154 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
1155 #define BUILTIN(ID, TYPE, ATTRS) \
1156 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1157 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1158 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1159 #include "clang/Basic/BuiltinsPPC.def"
1162 /// handleTargetFeatures - Perform initialization based on the user
1163 /// configured set of features.
1164 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1165 DiagnosticsEngine &Diags) {
1166 for (const auto &Feature : Features) {
1167 if (Feature == "+vsx") {
1169 } else if (Feature == "+bpermd") {
1171 } else if (Feature == "+extdiv") {
1173 } else if (Feature == "+power8-vector") {
1175 } else if (Feature == "+crypto") {
1177 } else if (Feature == "+direct-move") {
1178 HasDirectMove = true;
1179 } else if (Feature == "+qpx") {
1181 } else if (Feature == "+htm") {
1183 } else if (Feature == "+float128") {
1185 } else if (Feature == "+power9-vector") {
1188 // TODO: Finish this list and add an assert that we've handled them
1195 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1196 /// #defines that are not tied to a specific subtarget.
1197 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1198 MacroBuilder &Builder) const {
1199 // Target identification.
1200 Builder.defineMacro("__ppc__");
1201 Builder.defineMacro("__PPC__");
1202 Builder.defineMacro("_ARCH_PPC");
1203 Builder.defineMacro("__powerpc__");
1204 Builder.defineMacro("__POWERPC__");
1205 if (PointerWidth == 64) {
1206 Builder.defineMacro("_ARCH_PPC64");
1207 Builder.defineMacro("__powerpc64__");
1208 Builder.defineMacro("__ppc64__");
1209 Builder.defineMacro("__PPC64__");
1212 // Target properties.
1213 if (getTriple().getArch() == llvm::Triple::ppc64le) {
1214 Builder.defineMacro("_LITTLE_ENDIAN");
1216 if (getTriple().getOS() != llvm::Triple::NetBSD &&
1217 getTriple().getOS() != llvm::Triple::OpenBSD)
1218 Builder.defineMacro("_BIG_ENDIAN");
1222 if (ABI == "elfv1" || ABI == "elfv1-qpx")
1223 Builder.defineMacro("_CALL_ELF", "1");
1225 Builder.defineMacro("_CALL_ELF", "2");
1227 // Subtarget options.
1228 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1229 Builder.defineMacro("__REGISTER_PREFIX__", "");
1231 // FIXME: Should be controlled by command line option.
1232 if (LongDoubleWidth == 128)
1233 Builder.defineMacro("__LONG_DOUBLE_128__");
1236 Builder.defineMacro("__VEC__", "10206");
1237 Builder.defineMacro("__ALTIVEC__");
1240 // CPU identification.
1241 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1242 .Case("440", ArchDefineName)
1243 .Case("450", ArchDefineName | ArchDefine440)
1244 .Case("601", ArchDefineName)
1245 .Case("602", ArchDefineName | ArchDefinePpcgr)
1246 .Case("603", ArchDefineName | ArchDefinePpcgr)
1247 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1248 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1249 .Case("604", ArchDefineName | ArchDefinePpcgr)
1250 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1251 .Case("620", ArchDefineName | ArchDefinePpcgr)
1252 .Case("630", ArchDefineName | ArchDefinePpcgr)
1253 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1254 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1255 .Case("750", ArchDefineName | ArchDefinePpcgr)
1256 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1258 .Case("a2", ArchDefineA2)
1259 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1260 .Case("pwr3", ArchDefinePpcgr)
1261 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1262 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1264 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1265 | ArchDefinePpcgr | ArchDefinePpcsq)
1266 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1267 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1268 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1269 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1271 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1272 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1273 | ArchDefinePpcgr | ArchDefinePpcsq)
1274 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1275 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1276 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1277 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7
1278 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1279 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1281 .Case("power3", ArchDefinePpcgr)
1282 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1283 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1285 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1286 | ArchDefinePpcgr | ArchDefinePpcsq)
1287 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1288 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1289 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1290 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1292 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1293 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1294 | ArchDefinePpcgr | ArchDefinePpcsq)
1295 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1296 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1297 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1298 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7
1299 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1300 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1302 .Default(ArchDefineNone);
1304 if (defs & ArchDefineName)
1305 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1306 if (defs & ArchDefinePpcgr)
1307 Builder.defineMacro("_ARCH_PPCGR");
1308 if (defs & ArchDefinePpcsq)
1309 Builder.defineMacro("_ARCH_PPCSQ");
1310 if (defs & ArchDefine440)
1311 Builder.defineMacro("_ARCH_440");
1312 if (defs & ArchDefine603)
1313 Builder.defineMacro("_ARCH_603");
1314 if (defs & ArchDefine604)
1315 Builder.defineMacro("_ARCH_604");
1316 if (defs & ArchDefinePwr4)
1317 Builder.defineMacro("_ARCH_PWR4");
1318 if (defs & ArchDefinePwr5)
1319 Builder.defineMacro("_ARCH_PWR5");
1320 if (defs & ArchDefinePwr5x)
1321 Builder.defineMacro("_ARCH_PWR5X");
1322 if (defs & ArchDefinePwr6)
1323 Builder.defineMacro("_ARCH_PWR6");
1324 if (defs & ArchDefinePwr6x)
1325 Builder.defineMacro("_ARCH_PWR6X");
1326 if (defs & ArchDefinePwr7)
1327 Builder.defineMacro("_ARCH_PWR7");
1328 if (defs & ArchDefinePwr8)
1329 Builder.defineMacro("_ARCH_PWR8");
1330 if (defs & ArchDefinePwr9)
1331 Builder.defineMacro("_ARCH_PWR9");
1332 if (defs & ArchDefineA2)
1333 Builder.defineMacro("_ARCH_A2");
1334 if (defs & ArchDefineA2q) {
1335 Builder.defineMacro("_ARCH_A2Q");
1336 Builder.defineMacro("_ARCH_QP");
1339 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1340 Builder.defineMacro("__bg__");
1341 Builder.defineMacro("__THW_BLUEGENE__");
1342 Builder.defineMacro("__bgq__");
1343 Builder.defineMacro("__TOS_BGQ__");
1347 Builder.defineMacro("__VSX__");
1349 Builder.defineMacro("__POWER8_VECTOR__");
1351 Builder.defineMacro("__CRYPTO__");
1353 Builder.defineMacro("__HTM__");
1355 Builder.defineMacro("__FLOAT128__");
1357 Builder.defineMacro("__POWER9_VECTOR__");
1359 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1360 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1361 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1362 if (PointerWidth == 64)
1363 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1365 // FIXME: The following are not yet generated here by Clang, but are
1366 // generated by GCC:
1369 // __RECIP_PRECISION__
1370 // __APPLE_ALTIVEC__
1379 // __CMODEL_MEDIUM__
1386 // Handle explicit options being passed to the compiler here: if we've
1387 // explicitly turned off vsx and turned on any of:
1392 // then go ahead and error since the customer has expressed an incompatible
1394 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
1395 const std::vector<std::string> &FeaturesVec) {
1397 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") !=
1398 FeaturesVec.end()) {
1399 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") !=
1400 FeaturesVec.end()) {
1401 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
1406 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") !=
1407 FeaturesVec.end()) {
1408 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
1413 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") !=
1414 FeaturesVec.end()) {
1415 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
1420 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") !=
1421 FeaturesVec.end()) {
1422 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector"
1431 bool PPCTargetInfo::initFeatureMap(
1432 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
1433 const std::vector<std::string> &FeaturesVec) const {
1434 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1445 .Case("ppc64", true)
1446 .Case("ppc64le", true)
1449 Features["qpx"] = (CPU == "a2q");
1450 Features["power9-vector"] = (CPU == "pwr9");
1451 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1452 .Case("ppc64le", true)
1456 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1457 .Case("ppc64le", true)
1461 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1462 .Case("ppc64le", true)
1467 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1468 .Case("ppc64le", true)
1473 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1474 .Case("ppc64le", true)
1478 Features["vsx"] = llvm::StringSwitch<bool>(CPU)
1479 .Case("ppc64le", true)
1485 if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
1488 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1491 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1492 return llvm::StringSwitch<bool>(Feature)
1493 .Case("powerpc", true)
1494 .Case("vsx", HasVSX)
1495 .Case("power8-vector", HasP8Vector)
1496 .Case("crypto", HasP8Crypto)
1497 .Case("direct-move", HasDirectMove)
1498 .Case("qpx", HasQPX)
1499 .Case("htm", HasHTM)
1500 .Case("bpermd", HasBPERMD)
1501 .Case("extdiv", HasExtDiv)
1502 .Case("float128", HasFloat128)
1503 .Case("power9-vector", HasP9Vector)
1507 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1508 StringRef Name, bool Enabled) const {
1509 // If we're enabling direct-move or power8-vector go ahead and enable vsx
1510 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user
1511 // incompatible options.
1513 if (Name == "direct-move" ||
1514 Name == "power8-vector" ||
1515 Name == "float128" ||
1516 Name == "power9-vector") {
1517 // power9-vector is really a superset of power8-vector so encode that.
1518 Features[Name] = Features["vsx"] = true;
1519 if (Name == "power9-vector")
1520 Features["power8-vector"] = true;
1522 Features[Name] = true;
1525 if (Name == "vsx") {
1526 Features[Name] = Features["direct-move"] = Features["power8-vector"] =
1527 Features["float128"] = Features["power9-vector"] = false;
1529 Features[Name] = false;
1534 const char * const PPCTargetInfo::GCCRegNames[] = {
1535 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1536 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1537 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1538 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1539 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1540 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1541 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1542 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1543 "mq", "lr", "ctr", "ap",
1544 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1546 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1547 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1548 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1549 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1551 "spe_acc", "spefscr",
1555 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const {
1556 return llvm::makeArrayRef(GCCRegNames);
1559 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1560 // While some of these aliases do map to different registers
1561 // they still share the same register name.
1572 { { "10" }, "r10" },
1573 { { "11" }, "r11" },
1574 { { "12" }, "r12" },
1575 { { "13" }, "r13" },
1576 { { "14" }, "r14" },
1577 { { "15" }, "r15" },
1578 { { "16" }, "r16" },
1579 { { "17" }, "r17" },
1580 { { "18" }, "r18" },
1581 { { "19" }, "r19" },
1582 { { "20" }, "r20" },
1583 { { "21" }, "r21" },
1584 { { "22" }, "r22" },
1585 { { "23" }, "r23" },
1586 { { "24" }, "r24" },
1587 { { "25" }, "r25" },
1588 { { "26" }, "r26" },
1589 { { "27" }, "r27" },
1590 { { "28" }, "r28" },
1591 { { "29" }, "r29" },
1592 { { "30" }, "r30" },
1593 { { "31" }, "r31" },
1594 { { "fr0" }, "f0" },
1595 { { "fr1" }, "f1" },
1596 { { "fr2" }, "f2" },
1597 { { "fr3" }, "f3" },
1598 { { "fr4" }, "f4" },
1599 { { "fr5" }, "f5" },
1600 { { "fr6" }, "f6" },
1601 { { "fr7" }, "f7" },
1602 { { "fr8" }, "f8" },
1603 { { "fr9" }, "f9" },
1604 { { "fr10" }, "f10" },
1605 { { "fr11" }, "f11" },
1606 { { "fr12" }, "f12" },
1607 { { "fr13" }, "f13" },
1608 { { "fr14" }, "f14" },
1609 { { "fr15" }, "f15" },
1610 { { "fr16" }, "f16" },
1611 { { "fr17" }, "f17" },
1612 { { "fr18" }, "f18" },
1613 { { "fr19" }, "f19" },
1614 { { "fr20" }, "f20" },
1615 { { "fr21" }, "f21" },
1616 { { "fr22" }, "f22" },
1617 { { "fr23" }, "f23" },
1618 { { "fr24" }, "f24" },
1619 { { "fr25" }, "f25" },
1620 { { "fr26" }, "f26" },
1621 { { "fr27" }, "f27" },
1622 { { "fr28" }, "f28" },
1623 { { "fr29" }, "f29" },
1624 { { "fr30" }, "f30" },
1625 { { "fr31" }, "f31" },
1626 { { "cc" }, "cr0" },
1629 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
1630 return llvm::makeArrayRef(GCCRegAliases);
1633 class PPC32TargetInfo : public PPCTargetInfo {
1635 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1636 : PPCTargetInfo(Triple, Opts) {
1637 resetDataLayout("E-m:e-p:32:32-i64:64-n32");
1639 switch (getTriple().getOS()) {
1640 case llvm::Triple::Linux:
1641 case llvm::Triple::FreeBSD:
1642 case llvm::Triple::NetBSD:
1643 SizeType = UnsignedInt;
1644 PtrDiffType = SignedInt;
1645 IntPtrType = SignedInt;
1651 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1652 LongDoubleWidth = LongDoubleAlign = 64;
1653 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1656 // PPC32 supports atomics up to 4 bytes.
1657 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1660 BuiltinVaListKind getBuiltinVaListKind() const override {
1661 // This is the ELF definition, and is overridden by the Darwin sub-target
1662 return TargetInfo::PowerABIBuiltinVaList;
1666 // Note: ABI differences may eventually require us to have a separate
1667 // TargetInfo for little endian.
1668 class PPC64TargetInfo : public PPCTargetInfo {
1670 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1671 : PPCTargetInfo(Triple, Opts) {
1672 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1673 IntMaxType = SignedLong;
1674 Int64Type = SignedLong;
1676 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1677 resetDataLayout("e-m:e-i64:64-n32:64");
1680 resetDataLayout("E-m:e-i64:64-n32:64");
1684 switch (getTriple().getOS()) {
1685 case llvm::Triple::FreeBSD:
1686 LongDoubleWidth = LongDoubleAlign = 64;
1687 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1689 case llvm::Triple::NetBSD:
1690 IntMaxType = SignedLongLong;
1691 Int64Type = SignedLongLong;
1697 // PPC64 supports atomics up to 8 bytes.
1698 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1700 BuiltinVaListKind getBuiltinVaListKind() const override {
1701 return TargetInfo::CharPtrBuiltinVaList;
1703 // PPC64 Linux-specific ABI options.
1704 bool setABI(const std::string &Name) override {
1705 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1713 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> {
1715 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1716 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
1717 HasAlignMac68kSupport = true;
1718 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1719 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1721 SuitableAlign = 128;
1722 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
1724 BuiltinVaListKind getBuiltinVaListKind() const override {
1725 return TargetInfo::CharPtrBuiltinVaList;
1729 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> {
1731 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1732 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
1733 HasAlignMac68kSupport = true;
1734 SuitableAlign = 128;
1735 resetDataLayout("E-m:o-i64:64-n32:64");
1739 static const unsigned NVPTXAddrSpaceMap[] = {
1742 4, // opencl_constant
1743 // FIXME: generic has to be added to the target
1744 0, // opencl_generic
1750 class NVPTXTargetInfo : public TargetInfo {
1751 static const char *const GCCRegNames[];
1752 static const Builtin::Info BuiltinInfo[];
1754 std::unique_ptr<TargetInfo> HostTarget;
1757 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts,
1758 unsigned TargetPointerWidth)
1759 : TargetInfo(Triple) {
1760 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) &&
1761 "NVPTX only supports 32- and 64-bit modes.");
1763 TLSSupported = false;
1764 AddrSpaceMap = &NVPTXAddrSpaceMap;
1765 UseAddrSpaceMapMangling = true;
1767 // Define available target features
1768 // These must be defined in sorted order!
1769 NoAsmVariants = true;
1770 GPU = CudaArch::SM_20;
1772 if (TargetPointerWidth == 32)
1773 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64");
1775 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64");
1777 // If possible, get a TargetInfo for our host triple, so we can match its
1779 llvm::Triple HostTriple(Opts.HostTriple);
1780 if (!HostTriple.isNVPTX())
1781 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts));
1783 // If no host target, make some guesses about the data layout and return.
1785 LongWidth = LongAlign = TargetPointerWidth;
1786 PointerWidth = PointerAlign = TargetPointerWidth;
1787 switch (TargetPointerWidth) {
1789 SizeType = TargetInfo::UnsignedInt;
1790 PtrDiffType = TargetInfo::SignedInt;
1791 IntPtrType = TargetInfo::SignedInt;
1794 SizeType = TargetInfo::UnsignedLong;
1795 PtrDiffType = TargetInfo::SignedLong;
1796 IntPtrType = TargetInfo::SignedLong;
1799 llvm_unreachable("TargetPointerWidth must be 32 or 64");
1804 // Copy properties from host target.
1805 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0);
1806 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0);
1807 BoolWidth = HostTarget->getBoolWidth();
1808 BoolAlign = HostTarget->getBoolAlign();
1809 IntWidth = HostTarget->getIntWidth();
1810 IntAlign = HostTarget->getIntAlign();
1811 HalfWidth = HostTarget->getHalfWidth();
1812 HalfAlign = HostTarget->getHalfAlign();
1813 FloatWidth = HostTarget->getFloatWidth();
1814 FloatAlign = HostTarget->getFloatAlign();
1815 DoubleWidth = HostTarget->getDoubleWidth();
1816 DoubleAlign = HostTarget->getDoubleAlign();
1817 LongWidth = HostTarget->getLongWidth();
1818 LongAlign = HostTarget->getLongAlign();
1819 LongLongWidth = HostTarget->getLongLongWidth();
1820 LongLongAlign = HostTarget->getLongLongAlign();
1821 MinGlobalAlign = HostTarget->getMinGlobalAlign();
1822 NewAlign = HostTarget->getNewAlign();
1823 DefaultAlignForAttributeAligned =
1824 HostTarget->getDefaultAlignForAttributeAligned();
1825 SizeType = HostTarget->getSizeType();
1826 IntMaxType = HostTarget->getIntMaxType();
1827 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0);
1828 IntPtrType = HostTarget->getIntPtrType();
1829 WCharType = HostTarget->getWCharType();
1830 WIntType = HostTarget->getWIntType();
1831 Char16Type = HostTarget->getChar16Type();
1832 Char32Type = HostTarget->getChar32Type();
1833 Int64Type = HostTarget->getInt64Type();
1834 SigAtomicType = HostTarget->getSigAtomicType();
1835 ProcessIDType = HostTarget->getProcessIDType();
1837 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
1838 UseZeroLengthBitfieldAlignment =
1839 HostTarget->useZeroLengthBitfieldAlignment();
1840 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
1841 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
1843 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
1844 // we need those macros to be identical on host and device, because (among
1845 // other things) they affect which standard library classes are defined, and
1846 // we need all classes to be defined on both the host and device.
1847 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
1849 // Properties intentionally not copied from host:
1850 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the
1851 // host/device boundary.
1852 // - SuitableAlign: Not visible across the host/device boundary, and may
1853 // correctly be different on host/device, e.g. if host has wider vector
1854 // types than device.
1855 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same
1856 // as its double type, but that's not necessarily true on the host.
1857 // TODO: nvcc emits a warning when using long double on device; we should
1860 void getTargetDefines(const LangOptions &Opts,
1861 MacroBuilder &Builder) const override {
1862 Builder.defineMacro("__PTX__");
1863 Builder.defineMacro("__NVPTX__");
1864 if (Opts.CUDAIsDevice) {
1865 // Set __CUDA_ARCH__ for the GPU specified.
1866 std::string CUDAArchCode = [this] {
1868 case CudaArch::UNKNOWN:
1869 assert(false && "No GPU arch when compiling CUDA device code.");
1871 case CudaArch::SM_20:
1873 case CudaArch::SM_21:
1875 case CudaArch::SM_30:
1877 case CudaArch::SM_32:
1879 case CudaArch::SM_35:
1881 case CudaArch::SM_37:
1883 case CudaArch::SM_50:
1885 case CudaArch::SM_52:
1887 case CudaArch::SM_53:
1889 case CudaArch::SM_60:
1891 case CudaArch::SM_61:
1893 case CudaArch::SM_62:
1896 llvm_unreachable("unhandled CudaArch");
1898 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1901 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1902 return llvm::makeArrayRef(BuiltinInfo,
1903 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin);
1906 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
1908 const std::vector<std::string> &FeaturesVec) const override {
1909 Features["satom"] = GPU >= CudaArch::SM_60;
1910 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1913 bool hasFeature(StringRef Feature) const override {
1914 return llvm::StringSwitch<bool>(Feature)
1915 .Cases("ptx", "nvptx", true)
1916 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope.
1920 ArrayRef<const char *> getGCCRegNames() const override;
1921 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1925 bool validateAsmConstraint(const char *&Name,
1926 TargetInfo::ConstraintInfo &Info) const override {
1936 Info.setAllowsRegister();
1940 const char *getClobbers() const override {
1941 // FIXME: Is this really right?
1944 BuiltinVaListKind getBuiltinVaListKind() const override {
1946 return TargetInfo::CharPtrBuiltinVaList;
1948 bool setCPU(const std::string &Name) override {
1949 GPU = StringToCudaArch(Name);
1950 return GPU != CudaArch::UNKNOWN;
1952 void setSupportedOpenCLOpts() override {
1953 auto &Opts = getSupportedOpenCLOpts();
1954 Opts.support("cl_clang_storage_class_specifiers");
1955 Opts.support("cl_khr_gl_sharing");
1956 Opts.support("cl_khr_icd");
1958 Opts.support("cl_khr_fp64");
1959 Opts.support("cl_khr_byte_addressable_store");
1960 Opts.support("cl_khr_global_int32_base_atomics");
1961 Opts.support("cl_khr_global_int32_extended_atomics");
1962 Opts.support("cl_khr_local_int32_base_atomics");
1963 Opts.support("cl_khr_local_int32_extended_atomics");
1966 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
1967 // CUDA compilations support all of the host's calling conventions.
1969 // TODO: We should warn if you apply a non-default CC to anything other than
1972 return HostTarget->checkCallingConvention(CC);
1973 return CCCR_Warning;
1977 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1978 #define BUILTIN(ID, TYPE, ATTRS) \
1979 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1980 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1981 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1982 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
1983 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
1984 #include "clang/Basic/BuiltinsNVPTX.def"
1987 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
1989 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
1990 return llvm::makeArrayRef(GCCRegNames);
1993 static const unsigned AMDGPUAddrSpaceMap[] = {
1996 2, // opencl_constant
1997 4, // opencl_generic
2003 // If you edit the description strings, make sure you update
2004 // getPointerWidthV().
2006 static const char *const DataLayoutStringR600 =
2007 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2008 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
2010 static const char *const DataLayoutStringSI =
2011 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
2012 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2013 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
2015 class AMDGPUTargetInfo final : public TargetInfo {
2016 static const Builtin::Info BuiltinInfo[];
2017 static const char * const GCCRegNames[];
2019 /// \brief The GPU profiles supported by the AMDGPU target.
2027 GK_EVERGREEN_DOUBLE_OPS,
2028 GK_NORTHERN_ISLANDS,
2038 bool hasFullSpeedFP32Denorms:1;
2040 static bool isAMDGCN(const llvm::Triple &TT) {
2041 return TT.getArch() == llvm::Triple::amdgcn;
2045 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
2046 : TargetInfo(Triple) ,
2047 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600),
2051 hasFullSpeedFP32Denorms(false){
2052 if (getTriple().getArch() == llvm::Triple::amdgcn) {
2058 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ?
2059 DataLayoutStringSI : DataLayoutStringR600);
2061 AddrSpaceMap = &AMDGPUAddrSpaceMap;
2062 UseAddrSpaceMapMangling = true;
2065 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
2066 if (GPU <= GK_CAYMAN)
2079 uint64_t getMaxPointerWidth() const override {
2080 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32;
2083 const char * getClobbers() const override {
2087 ArrayRef<const char *> getGCCRegNames() const override;
2089 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2093 bool validateAsmConstraint(const char *&Name,
2094 TargetInfo::ConstraintInfo &Info) const override {
2099 Info.setAllowsRegister();
2105 bool initFeatureMap(llvm::StringMap<bool> &Features,
2106 DiagnosticsEngine &Diags, StringRef CPU,
2107 const std::vector<std::string> &FeatureVec) const override;
2109 void adjustTargetOptions(const CodeGenOptions &CGOpts,
2110 TargetOptions &TargetOpts) const override {
2111 bool hasFP32Denormals = false;
2112 bool hasFP64Denormals = false;
2113 for (auto &I : TargetOpts.FeaturesAsWritten) {
2114 if (I == "+fp32-denormals" || I == "-fp32-denormals")
2115 hasFP32Denormals = true;
2116 if (I == "+fp64-denormals" || I == "-fp64-denormals")
2117 hasFP64Denormals = true;
2119 if (!hasFP32Denormals)
2120 TargetOpts.Features.push_back((Twine(hasFullSpeedFP32Denorms &&
2121 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str());
2122 // Always do not flush fp64 denorms.
2123 if (!hasFP64Denormals && hasFP64)
2124 TargetOpts.Features.push_back("+fp64-denormals");
2127 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
2128 return llvm::makeArrayRef(BuiltinInfo,
2129 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin);
2132 void getTargetDefines(const LangOptions &Opts,
2133 MacroBuilder &Builder) const override {
2134 if (getTriple().getArch() == llvm::Triple::amdgcn)
2135 Builder.defineMacro("__AMDGCN__");
2137 Builder.defineMacro("__R600__");
2140 Builder.defineMacro("__HAS_FMAF__");
2142 Builder.defineMacro("__HAS_LDEXPF__");
2144 Builder.defineMacro("__HAS_FP64__");
2147 BuiltinVaListKind getBuiltinVaListKind() const override {
2148 return TargetInfo::CharPtrBuiltinVaList;
2151 static GPUKind parseR600Name(StringRef Name) {
2152 return llvm::StringSwitch<GPUKind>(Name)
2153 .Case("r600" , GK_R600)
2154 .Case("rv610", GK_R600)
2155 .Case("rv620", GK_R600)
2156 .Case("rv630", GK_R600)
2157 .Case("rv635", GK_R600)
2158 .Case("rs780", GK_R600)
2159 .Case("rs880", GK_R600)
2160 .Case("rv670", GK_R600_DOUBLE_OPS)
2161 .Case("rv710", GK_R700)
2162 .Case("rv730", GK_R700)
2163 .Case("rv740", GK_R700_DOUBLE_OPS)
2164 .Case("rv770", GK_R700_DOUBLE_OPS)
2165 .Case("palm", GK_EVERGREEN)
2166 .Case("cedar", GK_EVERGREEN)
2167 .Case("sumo", GK_EVERGREEN)
2168 .Case("sumo2", GK_EVERGREEN)
2169 .Case("redwood", GK_EVERGREEN)
2170 .Case("juniper", GK_EVERGREEN)
2171 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
2172 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
2173 .Case("barts", GK_NORTHERN_ISLANDS)
2174 .Case("turks", GK_NORTHERN_ISLANDS)
2175 .Case("caicos", GK_NORTHERN_ISLANDS)
2176 .Case("cayman", GK_CAYMAN)
2177 .Case("aruba", GK_CAYMAN)
2181 static GPUKind parseAMDGCNName(StringRef Name) {
2182 return llvm::StringSwitch<GPUKind>(Name)
2183 .Case("tahiti", GK_GFX6)
2184 .Case("pitcairn", GK_GFX6)
2185 .Case("verde", GK_GFX6)
2186 .Case("oland", GK_GFX6)
2187 .Case("hainan", GK_GFX6)
2188 .Case("bonaire", GK_GFX7)
2189 .Case("kabini", GK_GFX7)
2190 .Case("kaveri", GK_GFX7)
2191 .Case("hawaii", GK_GFX7)
2192 .Case("mullins", GK_GFX7)
2193 .Case("gfx700", GK_GFX7)
2194 .Case("gfx701", GK_GFX7)
2195 .Case("gfx702", GK_GFX7)
2196 .Case("tonga", GK_GFX8)
2197 .Case("iceland", GK_GFX8)
2198 .Case("carrizo", GK_GFX8)
2199 .Case("fiji", GK_GFX8)
2200 .Case("stoney", GK_GFX8)
2201 .Case("polaris10", GK_GFX8)
2202 .Case("polaris11", GK_GFX8)
2203 .Case("gfx800", GK_GFX8)
2204 .Case("gfx801", GK_GFX8)
2205 .Case("gfx802", GK_GFX8)
2206 .Case("gfx803", GK_GFX8)
2207 .Case("gfx804", GK_GFX8)
2208 .Case("gfx810", GK_GFX8)
2212 bool setCPU(const std::string &Name) override {
2213 if (getTriple().getArch() == llvm::Triple::amdgcn)
2214 GPU = parseAMDGCNName(Name);
2216 GPU = parseR600Name(Name);
2218 return GPU != GK_NONE;
2221 void setSupportedOpenCLOpts() override {
2222 auto &Opts = getSupportedOpenCLOpts();
2223 Opts.support("cl_clang_storage_class_specifiers");
2224 Opts.support("cl_khr_icd");
2227 Opts.support("cl_khr_fp64");
2228 if (GPU >= GK_EVERGREEN) {
2229 Opts.support("cl_khr_byte_addressable_store");
2230 Opts.support("cl_khr_global_int32_base_atomics");
2231 Opts.support("cl_khr_global_int32_extended_atomics");
2232 Opts.support("cl_khr_local_int32_base_atomics");
2233 Opts.support("cl_khr_local_int32_extended_atomics");
2235 if (GPU >= GK_GFX6) {
2236 Opts.support("cl_khr_fp16");
2237 Opts.support("cl_khr_int64_base_atomics");
2238 Opts.support("cl_khr_int64_extended_atomics");
2239 Opts.support("cl_khr_mipmap_image");
2240 Opts.support("cl_khr_subgroups");
2241 Opts.support("cl_khr_3d_image_writes");
2242 Opts.support("cl_amd_media_ops");
2243 Opts.support("cl_amd_media_ops2");
2247 LangAS::ID getOpenCLImageAddrSpace() const override {
2248 return LangAS::opencl_constant;
2251 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2254 return CCCR_Warning;
2256 case CC_OpenCLKernel:
2261 // In amdgcn target the null pointer in global, constant, and generic
2262 // address space has value 0 but in private and local address space has
2264 uint64_t getNullPointerValue(unsigned AS) const override {
2265 return AS != LangAS::opencl_local && AS != 0 ? 0 : ~0;
2269 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
2270 #define BUILTIN(ID, TYPE, ATTRS) \
2271 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2272 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2273 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2274 #include "clang/Basic/BuiltinsAMDGPU.def"
2276 const char * const AMDGPUTargetInfo::GCCRegNames[] = {
2277 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2278 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2279 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2280 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
2281 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
2282 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
2283 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
2284 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
2285 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
2286 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
2287 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
2288 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
2289 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
2290 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
2291 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
2292 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
2293 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
2294 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
2295 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
2296 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
2297 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
2298 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
2299 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
2300 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
2301 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
2302 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
2303 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
2304 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
2305 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
2306 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
2307 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
2308 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
2309 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2310 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
2311 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
2312 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
2313 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
2314 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
2315 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
2316 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
2317 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
2318 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
2319 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
2320 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
2321 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
2322 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
2323 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
2324 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127",
2325 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi",
2326 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi"
2329 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const {
2330 return llvm::makeArrayRef(GCCRegNames);
2333 bool AMDGPUTargetInfo::initFeatureMap(
2334 llvm::StringMap<bool> &Features,
2335 DiagnosticsEngine &Diags, StringRef CPU,
2336 const std::vector<std::string> &FeatureVec) const {
2338 // XXX - What does the member GPU mean if device name string passed here?
2339 if (getTriple().getArch() == llvm::Triple::amdgcn) {
2343 switch (parseAMDGCNName(CPU)) {
2349 Features["s-memrealtime"] = true;
2350 Features["16-bit-insts"] = true;
2356 llvm_unreachable("unhandled subtarget");
2362 switch (parseR600Name(CPU)) {
2366 case GK_NORTHERN_ISLANDS:
2368 case GK_R600_DOUBLE_OPS:
2369 case GK_R700_DOUBLE_OPS:
2370 case GK_EVERGREEN_DOUBLE_OPS:
2372 Features["fp64"] = true;
2377 llvm_unreachable("unhandled subtarget");
2381 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec);
2384 const Builtin::Info BuiltinInfoX86[] = {
2385 #define BUILTIN(ID, TYPE, ATTRS) \
2386 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2387 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2388 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2389 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
2390 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
2391 #include "clang/Basic/BuiltinsX86.def"
2393 #define BUILTIN(ID, TYPE, ATTRS) \
2394 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2395 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2396 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2397 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
2398 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
2399 #include "clang/Basic/BuiltinsX86_64.def"
2403 static const char* const GCCRegNames[] = {
2404 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
2405 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
2406 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
2407 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
2408 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
2409 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2410 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
2411 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
2412 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
2413 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23",
2414 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31",
2415 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23",
2416 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31",
2417 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7",
2418 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15",
2419 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23",
2420 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31",
2421 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7",
2424 const TargetInfo::AddlRegName AddlRegNames[] = {
2425 { { "al", "ah", "eax", "rax" }, 0 },
2426 { { "bl", "bh", "ebx", "rbx" }, 3 },
2427 { { "cl", "ch", "ecx", "rcx" }, 2 },
2428 { { "dl", "dh", "edx", "rdx" }, 1 },
2429 { { "esi", "rsi" }, 4 },
2430 { { "edi", "rdi" }, 5 },
2431 { { "esp", "rsp" }, 7 },
2432 { { "ebp", "rbp" }, 6 },
2433 { { "r8d", "r8w", "r8b" }, 38 },
2434 { { "r9d", "r9w", "r9b" }, 39 },
2435 { { "r10d", "r10w", "r10b" }, 40 },
2436 { { "r11d", "r11w", "r11b" }, 41 },
2437 { { "r12d", "r12w", "r12b" }, 42 },
2438 { { "r13d", "r13w", "r13b" }, 43 },
2439 { { "r14d", "r14w", "r14b" }, 44 },
2440 { { "r15d", "r15w", "r15b" }, 45 },
2443 // X86 target abstract base class; x86-32 and x86-64 are very close, so
2444 // most of the implementation can be shared.
2445 class X86TargetInfo : public TargetInfo {
2447 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
2450 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
2451 } MMX3DNowLevel = NoMMX3DNow;
2459 bool HasAES = false;
2460 bool HasPCLMUL = false;
2461 bool HasLZCNT = false;
2462 bool HasRDRND = false;
2463 bool HasFSGSBASE = false;
2464 bool HasBMI = false;
2465 bool HasBMI2 = false;
2466 bool HasPOPCNT = false;
2467 bool HasRTM = false;
2468 bool HasPRFCHW = false;
2469 bool HasRDSEED = false;
2470 bool HasADX = false;
2471 bool HasTBM = false;
2472 bool HasFMA = false;
2473 bool HasF16C = false;
2474 bool HasAVX512CD = false;
2475 bool HasAVX512ER = false;
2476 bool HasAVX512PF = false;
2477 bool HasAVX512DQ = false;
2478 bool HasAVX512BW = false;
2479 bool HasAVX512VL = false;
2480 bool HasAVX512VBMI = false;
2481 bool HasAVX512IFMA = false;
2482 bool HasSHA = false;
2483 bool HasMPX = false;
2484 bool HasSGX = false;
2485 bool HasCX16 = false;
2486 bool HasFXSR = false;
2487 bool HasXSAVE = false;
2488 bool HasXSAVEOPT = false;
2489 bool HasXSAVEC = false;
2490 bool HasXSAVES = false;
2491 bool HasMWAITX = false;
2492 bool HasPKU = false;
2493 bool HasCLFLUSHOPT = false;
2494 bool HasPCOMMIT = false;
2495 bool HasCLWB = false;
2496 bool HasUMIP = false;
2497 bool HasMOVBE = false;
2498 bool HasPREFETCHWT1 = false;
2500 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2502 /// Each enumeration represents a particular CPU supported by Clang. These
2503 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2508 /// i386-generation processors.
2514 /// i486-generation processors.
2523 /// i586-generation processors, P5 microarchitecture based.
2531 /// i686-generation processors, P6 / Pentium M microarchitecture based.
2541 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2542 /// Clang however has some logic to suport this.
2543 // FIXME: Warn, deprecate, and potentially remove this.
2548 /// Netburst microarchitecture based processors.
2557 /// Core microarchitecture based processors.
2561 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2562 /// codename which GCC no longer accepts as an option to -march, but Clang
2563 /// has some logic for recognizing it.
2564 // FIXME: Warn, deprecate, and potentially remove this.
2576 /// Nehalem microarchitecture based processors.
2580 /// Westmere microarchitecture based processors.
2583 /// \name Sandy Bridge
2584 /// Sandy Bridge microarchitecture based processors.
2587 /// \name Ivy Bridge
2588 /// Ivy Bridge microarchitecture based processors.
2592 /// Haswell microarchitecture based processors.
2596 /// Broadwell microarchitecture based processors.
2599 /// \name Skylake Client
2600 /// Skylake client microarchitecture based processors.
2603 /// \name Skylake Server
2604 /// Skylake server microarchitecture based processors.
2607 /// \name Cannonlake Client
2608 /// Cannonlake client microarchitecture based processors.
2611 /// \name Knights Landing
2612 /// Knights Landing processor.
2616 /// Lakemont microarchitecture based processors.
2620 /// K6 architecture processors.
2628 /// K7 architecture processors.
2631 CK_AthlonThunderbird,
2638 /// K8 architecture processors.
2651 /// Bobcat architecture processors.
2658 /// Bulldozer architecture processors.
2667 /// Zen architecture processors.
2672 /// This specification is deprecated and will be removed in the future.
2673 /// Users should prefer \see CK_K8.
2674 // FIXME: Warn on this when the CPU is set to it.
2680 /// Geode processors.
2686 CPUKind getCPUKind(StringRef CPU) const {
2687 return llvm::StringSwitch<CPUKind>(CPU)
2688 .Case("i386", CK_i386)
2689 .Case("i486", CK_i486)
2690 .Case("winchip-c6", CK_WinChipC6)
2691 .Case("winchip2", CK_WinChip2)
2693 .Case("i586", CK_i586)
2694 .Case("pentium", CK_Pentium)
2695 .Case("pentium-mmx", CK_PentiumMMX)
2696 .Case("i686", CK_i686)
2697 .Case("pentiumpro", CK_PentiumPro)
2698 .Case("pentium2", CK_Pentium2)
2699 .Case("pentium3", CK_Pentium3)
2700 .Case("pentium3m", CK_Pentium3M)
2701 .Case("pentium-m", CK_PentiumM)
2702 .Case("c3-2", CK_C3_2)
2703 .Case("yonah", CK_Yonah)
2704 .Case("pentium4", CK_Pentium4)
2705 .Case("pentium4m", CK_Pentium4M)
2706 .Case("prescott", CK_Prescott)
2707 .Case("nocona", CK_Nocona)
2708 .Case("core2", CK_Core2)
2709 .Case("penryn", CK_Penryn)
2710 .Case("bonnell", CK_Bonnell)
2711 .Case("atom", CK_Bonnell) // Legacy name.
2712 .Case("silvermont", CK_Silvermont)
2713 .Case("slm", CK_Silvermont) // Legacy name.
2714 .Case("nehalem", CK_Nehalem)
2715 .Case("corei7", CK_Nehalem) // Legacy name.
2716 .Case("westmere", CK_Westmere)
2717 .Case("sandybridge", CK_SandyBridge)
2718 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2719 .Case("ivybridge", CK_IvyBridge)
2720 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2721 .Case("haswell", CK_Haswell)
2722 .Case("core-avx2", CK_Haswell) // Legacy name.
2723 .Case("broadwell", CK_Broadwell)
2724 .Case("skylake", CK_SkylakeClient)
2725 .Case("skylake-avx512", CK_SkylakeServer)
2726 .Case("skx", CK_SkylakeServer) // Legacy name.
2727 .Case("cannonlake", CK_Cannonlake)
2728 .Case("knl", CK_KNL)
2729 .Case("lakemont", CK_Lakemont)
2731 .Case("k6-2", CK_K6_2)
2732 .Case("k6-3", CK_K6_3)
2733 .Case("athlon", CK_Athlon)
2734 .Case("athlon-tbird", CK_AthlonThunderbird)
2735 .Case("athlon-4", CK_Athlon4)
2736 .Case("athlon-xp", CK_AthlonXP)
2737 .Case("athlon-mp", CK_AthlonMP)
2738 .Case("athlon64", CK_Athlon64)
2739 .Case("athlon64-sse3", CK_Athlon64SSE3)
2740 .Case("athlon-fx", CK_AthlonFX)
2742 .Case("k8-sse3", CK_K8SSE3)
2743 .Case("opteron", CK_Opteron)
2744 .Case("opteron-sse3", CK_OpteronSSE3)
2745 .Case("barcelona", CK_AMDFAM10)
2746 .Case("amdfam10", CK_AMDFAM10)
2747 .Case("btver1", CK_BTVER1)
2748 .Case("btver2", CK_BTVER2)
2749 .Case("bdver1", CK_BDVER1)
2750 .Case("bdver2", CK_BDVER2)
2751 .Case("bdver3", CK_BDVER3)
2752 .Case("bdver4", CK_BDVER4)
2753 .Case("znver1", CK_ZNVER1)
2754 .Case("x86-64", CK_x86_64)
2755 .Case("geode", CK_Geode)
2756 .Default(CK_Generic);
2763 } FPMath = FP_Default;
2766 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
2767 : TargetInfo(Triple) {
2768 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
2770 unsigned getFloatEvalMethod() const override {
2771 // X87 evaluates with 80 bits "long double" precision.
2772 return SSELevel == NoSSE ? 2 : 0;
2774 ArrayRef<const char *> getGCCRegNames() const override {
2775 return llvm::makeArrayRef(GCCRegNames);
2777 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2780 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
2781 return llvm::makeArrayRef(AddlRegNames);
2783 bool validateCpuSupports(StringRef Name) const override;
2784 bool validateAsmConstraint(const char *&Name,
2785 TargetInfo::ConstraintInfo &info) const override;
2787 bool validateGlobalRegisterVariable(StringRef RegName,
2789 bool &HasSizeMismatch) const override {
2790 // esp and ebp are the only 32-bit registers the x86 backend can currently
2792 if (RegName.equals("esp") || RegName.equals("ebp")) {
2793 // Check that the register size is 32-bit.
2794 HasSizeMismatch = RegSize != 32;
2801 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2803 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2805 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2807 std::string convertConstraint(const char *&Constraint) const override;
2808 const char *getClobbers() const override {
2809 return "~{dirflag},~{fpsr},~{flags}";
2812 StringRef getConstraintRegister(const StringRef &Constraint,
2813 const StringRef &Expression) const override {
2814 StringRef::iterator I, E;
2815 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) {
2822 // For the register constraints, return the matching register name
2835 // In case the constraint is 'r' we need to return Expression
2839 // Default value if there is no constraint for the register
2845 void getTargetDefines(const LangOptions &Opts,
2846 MacroBuilder &Builder) const override;
2847 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2849 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2851 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2853 void setFeatureEnabled(llvm::StringMap<bool> &Features,
2854 StringRef Name, bool Enabled) const override {
2855 setFeatureEnabledImpl(Features, Name, Enabled);
2857 // This exists purely to cut down on the number of virtual calls in
2858 // initFeatureMap which calls this repeatedly.
2859 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2860 StringRef Name, bool Enabled);
2862 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
2864 const std::vector<std::string> &FeaturesVec) const override;
2865 bool hasFeature(StringRef Feature) const override;
2866 bool handleTargetFeatures(std::vector<std::string> &Features,
2867 DiagnosticsEngine &Diags) override;
2868 StringRef getABI() const override {
2869 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
2871 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2873 if (getTriple().getArch() == llvm::Triple::x86 &&
2874 MMX3DNowLevel == NoMMX3DNow)
2878 bool setCPU(const std::string &Name) override {
2879 CPU = getCPUKind(Name);
2881 // Perform any per-CPU checks necessary to determine if this CPU is
2883 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2884 // invalid without explaining *why*.
2887 // No processor selected!
2914 case CK_AthlonThunderbird:
2919 // Only accept certain architectures when compiling in 32-bit mode.
2920 if (getTriple().getArch() != llvm::Triple::x86)
2931 case CK_SandyBridge:
2935 case CK_SkylakeClient:
2936 case CK_SkylakeServer:
2940 case CK_Athlon64SSE3:
2945 case CK_OpteronSSE3:
2957 llvm_unreachable("Unhandled CPU kind");
2960 bool setFPMath(StringRef Name) override;
2962 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2963 // Most of the non-ARM calling conventions are i386 conventions.
2965 case CC_X86ThisCall:
2966 case CC_X86FastCall:
2968 case CC_X86VectorCall:
2973 case CC_IntelOclBicc:
2976 return CCCR_Warning;
2980 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2981 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2984 bool hasSjLjLowering() const override {
2988 void setSupportedOpenCLOpts() override {
2989 getSupportedOpenCLOpts().supportAll();
2993 bool X86TargetInfo::setFPMath(StringRef Name) {
2994 if (Name == "387") {
2998 if (Name == "sse") {
3005 bool X86TargetInfo::initFeatureMap(
3006 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
3007 const std::vector<std::string> &FeaturesVec) const {
3008 // FIXME: This *really* should not be here.
3009 // X86_64 always has SSE2.
3010 if (getTriple().getArch() == llvm::Triple::x86_64)
3011 setFeatureEnabledImpl(Features, "sse2", true);
3013 const CPUKind Kind = getCPUKind(CPU);
3015 // Enable X87 for all X86 processors but Lakemont.
3016 if (Kind != CK_Lakemont)
3017 setFeatureEnabledImpl(Features, "x87", true);
3033 setFeatureEnabledImpl(Features, "mmx", true);
3038 setFeatureEnabledImpl(Features, "sse", true);
3039 setFeatureEnabledImpl(Features, "fxsr", true);
3045 setFeatureEnabledImpl(Features, "sse2", true);
3046 setFeatureEnabledImpl(Features, "fxsr", true);
3051 setFeatureEnabledImpl(Features, "sse3", true);
3052 setFeatureEnabledImpl(Features, "fxsr", true);
3053 setFeatureEnabledImpl(Features, "cx16", true);
3057 setFeatureEnabledImpl(Features, "ssse3", true);
3058 setFeatureEnabledImpl(Features, "fxsr", true);
3059 setFeatureEnabledImpl(Features, "cx16", true);
3062 setFeatureEnabledImpl(Features, "sse4.1", true);
3063 setFeatureEnabledImpl(Features, "fxsr", true);
3064 setFeatureEnabledImpl(Features, "cx16", true);
3067 setFeatureEnabledImpl(Features, "avx512ifma", true);
3068 setFeatureEnabledImpl(Features, "avx512vbmi", true);
3069 setFeatureEnabledImpl(Features, "sha", true);
3070 setFeatureEnabledImpl(Features, "umip", true);
3072 case CK_SkylakeServer:
3073 setFeatureEnabledImpl(Features, "avx512f", true);
3074 setFeatureEnabledImpl(Features, "avx512cd", true);
3075 setFeatureEnabledImpl(Features, "avx512dq", true);
3076 setFeatureEnabledImpl(Features, "avx512bw", true);
3077 setFeatureEnabledImpl(Features, "avx512vl", true);
3078 setFeatureEnabledImpl(Features, "pku", true);
3079 setFeatureEnabledImpl(Features, "pcommit", true);
3080 setFeatureEnabledImpl(Features, "clwb", true);
3082 case CK_SkylakeClient:
3083 setFeatureEnabledImpl(Features, "xsavec", true);
3084 setFeatureEnabledImpl(Features, "xsaves", true);
3085 setFeatureEnabledImpl(Features, "mpx", true);
3086 setFeatureEnabledImpl(Features, "sgx", true);
3087 setFeatureEnabledImpl(Features, "clflushopt", true);
3090 setFeatureEnabledImpl(Features, "rdseed", true);
3091 setFeatureEnabledImpl(Features, "adx", true);
3094 setFeatureEnabledImpl(Features, "avx2", true);
3095 setFeatureEnabledImpl(Features, "lzcnt", true);
3096 setFeatureEnabledImpl(Features, "bmi", true);
3097 setFeatureEnabledImpl(Features, "bmi2", true);
3098 setFeatureEnabledImpl(Features, "rtm", true);
3099 setFeatureEnabledImpl(Features, "fma", true);
3100 setFeatureEnabledImpl(Features, "movbe", true);
3103 setFeatureEnabledImpl(Features, "rdrnd", true);
3104 setFeatureEnabledImpl(Features, "f16c", true);
3105 setFeatureEnabledImpl(Features, "fsgsbase", true);
3107 case CK_SandyBridge:
3108 setFeatureEnabledImpl(Features, "avx", true);
3109 setFeatureEnabledImpl(Features, "xsave", true);
3110 setFeatureEnabledImpl(Features, "xsaveopt", true);
3114 setFeatureEnabledImpl(Features, "aes", true);
3115 setFeatureEnabledImpl(Features, "pclmul", true);
3118 setFeatureEnabledImpl(Features, "sse4.2", true);
3119 setFeatureEnabledImpl(Features, "fxsr", true);
3120 setFeatureEnabledImpl(Features, "cx16", true);
3123 setFeatureEnabledImpl(Features, "avx512f", true);
3124 setFeatureEnabledImpl(Features, "avx512cd", true);
3125 setFeatureEnabledImpl(Features, "avx512er", true);
3126 setFeatureEnabledImpl(Features, "avx512pf", true);
3127 setFeatureEnabledImpl(Features, "prefetchwt1", true);
3128 setFeatureEnabledImpl(Features, "fxsr", true);
3129 setFeatureEnabledImpl(Features, "rdseed", true);
3130 setFeatureEnabledImpl(Features, "adx", true);
3131 setFeatureEnabledImpl(Features, "lzcnt", true);
3132 setFeatureEnabledImpl(Features, "bmi", true);
3133 setFeatureEnabledImpl(Features, "bmi2", true);
3134 setFeatureEnabledImpl(Features, "rtm", true);
3135 setFeatureEnabledImpl(Features, "fma", true);
3136 setFeatureEnabledImpl(Features, "rdrnd", true);
3137 setFeatureEnabledImpl(Features, "f16c", true);
3138 setFeatureEnabledImpl(Features, "fsgsbase", true);
3139 setFeatureEnabledImpl(Features, "aes", true);
3140 setFeatureEnabledImpl(Features, "pclmul", true);
3141 setFeatureEnabledImpl(Features, "cx16", true);
3142 setFeatureEnabledImpl(Features, "xsaveopt", true);
3143 setFeatureEnabledImpl(Features, "xsave", true);
3144 setFeatureEnabledImpl(Features, "movbe", true);
3150 setFeatureEnabledImpl(Features, "3dnow", true);
3153 case CK_AthlonThunderbird:
3155 setFeatureEnabledImpl(Features, "3dnowa", true);
3160 setFeatureEnabledImpl(Features, "sse", true);
3161 setFeatureEnabledImpl(Features, "3dnowa", true);
3162 setFeatureEnabledImpl(Features, "fxsr", true);
3168 setFeatureEnabledImpl(Features, "sse2", true);
3169 setFeatureEnabledImpl(Features, "3dnowa", true);
3170 setFeatureEnabledImpl(Features, "fxsr", true);
3173 setFeatureEnabledImpl(Features, "sse4a", true);
3174 setFeatureEnabledImpl(Features, "lzcnt", true);
3175 setFeatureEnabledImpl(Features, "popcnt", true);
3178 case CK_OpteronSSE3:
3179 case CK_Athlon64SSE3:
3180 setFeatureEnabledImpl(Features, "sse3", true);
3181 setFeatureEnabledImpl(Features, "3dnowa", true);
3182 setFeatureEnabledImpl(Features, "fxsr", true);
3185 setFeatureEnabledImpl(Features, "avx", true);
3186 setFeatureEnabledImpl(Features, "aes", true);
3187 setFeatureEnabledImpl(Features, "pclmul", true);
3188 setFeatureEnabledImpl(Features, "bmi", true);
3189 setFeatureEnabledImpl(Features, "f16c", true);
3190 setFeatureEnabledImpl(Features, "xsaveopt", true);
3193 setFeatureEnabledImpl(Features, "ssse3", true);
3194 setFeatureEnabledImpl(Features, "sse4a", true);
3195 setFeatureEnabledImpl(Features, "lzcnt", true);
3196 setFeatureEnabledImpl(Features, "popcnt", true);
3197 setFeatureEnabledImpl(Features, "prfchw", true);
3198 setFeatureEnabledImpl(Features, "cx16", true);
3199 setFeatureEnabledImpl(Features, "fxsr", true);
3202 setFeatureEnabledImpl(Features, "adx", true);
3203 setFeatureEnabledImpl(Features, "aes", true);
3204 setFeatureEnabledImpl(Features, "avx2", true);
3205 setFeatureEnabledImpl(Features, "bmi", true);
3206 setFeatureEnabledImpl(Features, "bmi2", true);
3207 setFeatureEnabledImpl(Features, "clflushopt", true);
3208 setFeatureEnabledImpl(Features, "cx16", true);
3209 setFeatureEnabledImpl(Features, "f16c", true);
3210 setFeatureEnabledImpl(Features, "fma", true);
3211 setFeatureEnabledImpl(Features, "fsgsbase", true);
3212 setFeatureEnabledImpl(Features, "fxsr", true);
3213 setFeatureEnabledImpl(Features, "lzcnt", true);
3214 setFeatureEnabledImpl(Features, "mwaitx", true);
3215 setFeatureEnabledImpl(Features, "movbe", true);
3216 setFeatureEnabledImpl(Features, "pclmul", true);
3217 setFeatureEnabledImpl(Features, "popcnt", true);
3218 setFeatureEnabledImpl(Features, "prfchw", true);
3219 setFeatureEnabledImpl(Features, "rdrnd", true);
3220 setFeatureEnabledImpl(Features, "rdseed", true);
3221 setFeatureEnabledImpl(Features, "sha", true);
3222 setFeatureEnabledImpl(Features, "sse4a", true);
3223 setFeatureEnabledImpl(Features, "xsave", true);
3224 setFeatureEnabledImpl(Features, "xsavec", true);
3225 setFeatureEnabledImpl(Features, "xsaveopt", true);
3226 setFeatureEnabledImpl(Features, "xsaves", true);
3229 setFeatureEnabledImpl(Features, "avx2", true);
3230 setFeatureEnabledImpl(Features, "bmi2", true);
3231 setFeatureEnabledImpl(Features, "mwaitx", true);
3234 setFeatureEnabledImpl(Features, "fsgsbase", true);
3235 setFeatureEnabledImpl(Features, "xsaveopt", true);
3238 setFeatureEnabledImpl(Features, "bmi", true);
3239 setFeatureEnabledImpl(Features, "fma", true);
3240 setFeatureEnabledImpl(Features, "f16c", true);
3241 setFeatureEnabledImpl(Features, "tbm", true);
3244 // xop implies avx, sse4a and fma4.
3245 setFeatureEnabledImpl(Features, "xop", true);
3246 setFeatureEnabledImpl(Features, "lzcnt", true);
3247 setFeatureEnabledImpl(Features, "aes", true);
3248 setFeatureEnabledImpl(Features, "pclmul", true);
3249 setFeatureEnabledImpl(Features, "prfchw", true);
3250 setFeatureEnabledImpl(Features, "cx16", true);
3251 setFeatureEnabledImpl(Features, "fxsr", true);
3252 setFeatureEnabledImpl(Features, "xsave", true);
3255 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
3258 // Can't do this earlier because we need to be able to explicitly enable
3259 // or disable these features and the things that they depend upon.
3261 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
3262 auto I = Features.find("sse4.2");
3263 if (I != Features.end() && I->getValue() &&
3264 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
3266 Features["popcnt"] = true;
3268 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
3269 I = Features.find("3dnow");
3270 if (I != Features.end() && I->getValue() &&
3271 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
3273 Features["prfchw"] = true;
3275 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
3277 I = Features.find("sse");
3278 if (I != Features.end() && I->getValue() &&
3279 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
3281 Features["mmx"] = true;
3286 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
3287 X86SSEEnum Level, bool Enabled) {
3291 Features["avx512f"] = true;
3293 Features["avx2"] = true;
3295 Features["avx"] = true;
3296 Features["xsave"] = true;
3298 Features["sse4.2"] = true;
3300 Features["sse4.1"] = true;
3302 Features["ssse3"] = true;
3304 Features["sse3"] = true;
3306 Features["sse2"] = true;
3308 Features["sse"] = true;
3318 Features["sse"] = false;
3320 Features["sse2"] = Features["pclmul"] = Features["aes"] =
3321 Features["sha"] = false;
3323 Features["sse3"] = false;
3324 setXOPLevel(Features, NoXOP, false);
3326 Features["ssse3"] = false;
3328 Features["sse4.1"] = false;
3330 Features["sse4.2"] = false;
3332 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
3333 Features["xsaveopt"] = false;
3334 setXOPLevel(Features, FMA4, false);
3336 Features["avx2"] = false;
3338 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
3339 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
3340 Features["avx512vl"] = Features["avx512vbmi"] =
3341 Features["avx512ifma"] = false;
3345 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
3346 MMX3DNowEnum Level, bool Enabled) {
3349 case AMD3DNowAthlon:
3350 Features["3dnowa"] = true;
3352 Features["3dnow"] = true;
3354 Features["mmx"] = true;
3364 Features["mmx"] = false;
3366 Features["3dnow"] = false;
3367 case AMD3DNowAthlon:
3368 Features["3dnowa"] = false;
3372 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
3377 Features["xop"] = true;
3379 Features["fma4"] = true;
3380 setSSELevel(Features, AVX, true);
3382 Features["sse4a"] = true;
3383 setSSELevel(Features, SSE3, true);
3393 Features["sse4a"] = false;
3395 Features["fma4"] = false;
3397 Features["xop"] = false;
3401 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
3402 StringRef Name, bool Enabled) {
3403 // This is a bit of a hack to deal with the sse4 target feature when used
3404 // as part of the target attribute. We handle sse4 correctly everywhere
3405 // else. See below for more information on how we handle the sse4 options.
3407 Features[Name] = Enabled;
3409 if (Name == "mmx") {
3410 setMMXLevel(Features, MMX, Enabled);
3411 } else if (Name == "sse") {
3412 setSSELevel(Features, SSE1, Enabled);
3413 } else if (Name == "sse2") {
3414 setSSELevel(Features, SSE2, Enabled);
3415 } else if (Name == "sse3") {
3416 setSSELevel(Features, SSE3, Enabled);
3417 } else if (Name == "ssse3") {
3418 setSSELevel(Features, SSSE3, Enabled);
3419 } else if (Name == "sse4.2") {
3420 setSSELevel(Features, SSE42, Enabled);
3421 } else if (Name == "sse4.1") {
3422 setSSELevel(Features, SSE41, Enabled);
3423 } else if (Name == "3dnow") {
3424 setMMXLevel(Features, AMD3DNow, Enabled);
3425 } else if (Name == "3dnowa") {
3426 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
3427 } else if (Name == "aes") {
3429 setSSELevel(Features, SSE2, Enabled);
3430 } else if (Name == "pclmul") {
3432 setSSELevel(Features, SSE2, Enabled);
3433 } else if (Name == "avx") {
3434 setSSELevel(Features, AVX, Enabled);
3435 } else if (Name == "avx2") {
3436 setSSELevel(Features, AVX2, Enabled);
3437 } else if (Name == "avx512f") {
3438 setSSELevel(Features, AVX512F, Enabled);
3439 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
3440 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
3441 Name == "avx512vbmi" || Name == "avx512ifma") {
3443 setSSELevel(Features, AVX512F, Enabled);
3444 // Enable BWI instruction if VBMI is being enabled.
3445 if (Name == "avx512vbmi" && Enabled)
3446 Features["avx512bw"] = true;
3447 // Also disable VBMI if BWI is being disabled.
3448 if (Name == "avx512bw" && !Enabled)
3449 Features["avx512vbmi"] = false;
3450 } else if (Name == "fma") {
3452 setSSELevel(Features, AVX, Enabled);
3453 } else if (Name == "fma4") {
3454 setXOPLevel(Features, FMA4, Enabled);
3455 } else if (Name == "xop") {
3456 setXOPLevel(Features, XOP, Enabled);
3457 } else if (Name == "sse4a") {
3458 setXOPLevel(Features, SSE4A, Enabled);
3459 } else if (Name == "f16c") {
3461 setSSELevel(Features, AVX, Enabled);
3462 } else if (Name == "sha") {
3464 setSSELevel(Features, SSE2, Enabled);
3465 } else if (Name == "sse4") {
3466 // We can get here via the __target__ attribute since that's not controlled
3467 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
3468 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
3471 setSSELevel(Features, SSE42, Enabled);
3473 setSSELevel(Features, SSE41, Enabled);
3474 } else if (Name == "xsave") {
3476 Features["xsaveopt"] = false;
3477 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
3479 Features["xsave"] = true;
3483 /// handleTargetFeatures - Perform initialization based on the user
3484 /// configured set of features.
3485 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
3486 DiagnosticsEngine &Diags) {
3487 for (const auto &Feature : Features) {
3488 if (Feature[0] != '+')
3491 if (Feature == "+aes") {
3493 } else if (Feature == "+pclmul") {
3495 } else if (Feature == "+lzcnt") {
3497 } else if (Feature == "+rdrnd") {
3499 } else if (Feature == "+fsgsbase") {
3501 } else if (Feature == "+bmi") {
3503 } else if (Feature == "+bmi2") {
3505 } else if (Feature == "+popcnt") {
3507 } else if (Feature == "+rtm") {
3509 } else if (Feature == "+prfchw") {
3511 } else if (Feature == "+rdseed") {
3513 } else if (Feature == "+adx") {
3515 } else if (Feature == "+tbm") {
3517 } else if (Feature == "+fma") {
3519 } else if (Feature == "+f16c") {
3521 } else if (Feature == "+avx512cd") {
3523 } else if (Feature == "+avx512er") {
3525 } else if (Feature == "+avx512pf") {
3527 } else if (Feature == "+avx512dq") {
3529 } else if (Feature == "+avx512bw") {
3531 } else if (Feature == "+avx512vl") {
3533 } else if (Feature == "+avx512vbmi") {
3534 HasAVX512VBMI = true;
3535 } else if (Feature == "+avx512ifma") {
3536 HasAVX512IFMA = true;
3537 } else if (Feature == "+sha") {
3539 } else if (Feature == "+mpx") {
3541 } else if (Feature == "+movbe") {
3543 } else if (Feature == "+sgx") {
3545 } else if (Feature == "+cx16") {
3547 } else if (Feature == "+fxsr") {
3549 } else if (Feature == "+xsave") {
3551 } else if (Feature == "+xsaveopt") {
3553 } else if (Feature == "+xsavec") {
3555 } else if (Feature == "+xsaves") {
3557 } else if (Feature == "+mwaitx") {
3559 } else if (Feature == "+pku") {
3561 } else if (Feature == "+clflushopt") {
3562 HasCLFLUSHOPT = true;
3563 } else if (Feature == "+pcommit") {
3565 } else if (Feature == "+clwb") {
3567 } else if (Feature == "+umip") {
3569 } else if (Feature == "+prefetchwt1") {
3570 HasPREFETCHWT1 = true;
3573 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
3574 .Case("+avx512f", AVX512F)
3575 .Case("+avx2", AVX2)
3577 .Case("+sse4.2", SSE42)
3578 .Case("+sse4.1", SSE41)
3579 .Case("+ssse3", SSSE3)
3580 .Case("+sse3", SSE3)
3581 .Case("+sse2", SSE2)
3584 SSELevel = std::max(SSELevel, Level);
3586 MMX3DNowEnum ThreeDNowLevel =
3587 llvm::StringSwitch<MMX3DNowEnum>(Feature)
3588 .Case("+3dnowa", AMD3DNowAthlon)
3589 .Case("+3dnow", AMD3DNow)
3591 .Default(NoMMX3DNow);
3592 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
3594 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
3596 .Case("+fma4", FMA4)
3597 .Case("+sse4a", SSE4A)
3599 XOPLevel = std::max(XOPLevel, XLevel);
3602 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
3603 // matches the selected sse level.
3604 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
3605 (FPMath == FP_387 && SSELevel >= SSE1)) {
3606 Diags.Report(diag::err_target_unsupported_fpmath) <<
3607 (FPMath == FP_SSE ? "sse" : "387");
3612 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3616 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
3617 /// definitions for this particular subtarget.
3618 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
3619 MacroBuilder &Builder) const {
3620 // Target identification.
3621 if (getTriple().getArch() == llvm::Triple::x86_64) {
3622 Builder.defineMacro("__amd64__");
3623 Builder.defineMacro("__amd64");
3624 Builder.defineMacro("__x86_64");
3625 Builder.defineMacro("__x86_64__");
3626 if (getTriple().getArchName() == "x86_64h") {
3627 Builder.defineMacro("__x86_64h");
3628 Builder.defineMacro("__x86_64h__");
3631 DefineStd(Builder, "i386", Opts);
3634 // Subtarget options.
3635 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
3636 // truly should be based on -mtune options.
3641 // The rest are coming from the i386 define above.
3642 Builder.defineMacro("__tune_i386__");
3648 defineCPUMacros(Builder, "i486");
3651 Builder.defineMacro("__pentium_mmx__");
3652 Builder.defineMacro("__tune_pentium_mmx__");
3656 defineCPUMacros(Builder, "i586");
3657 defineCPUMacros(Builder, "pentium");
3662 Builder.defineMacro("__tune_pentium3__");
3666 Builder.defineMacro("__tune_pentium2__");
3669 Builder.defineMacro("__tune_i686__");
3670 Builder.defineMacro("__tune_pentiumpro__");
3673 Builder.defineMacro("__i686");
3674 Builder.defineMacro("__i686__");
3675 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3676 Builder.defineMacro("__pentiumpro");
3677 Builder.defineMacro("__pentiumpro__");
3681 defineCPUMacros(Builder, "pentium4");
3686 defineCPUMacros(Builder, "nocona");
3690 defineCPUMacros(Builder, "core2");
3693 defineCPUMacros(Builder, "atom");
3696 defineCPUMacros(Builder, "slm");
3700 case CK_SandyBridge:
3704 case CK_SkylakeClient:
3705 // FIXME: Historically, we defined this legacy name, it would be nice to
3706 // remove it at some point. We've never exposed fine-grained names for
3707 // recent primary x86 CPUs, and we should keep it that way.
3708 defineCPUMacros(Builder, "corei7");
3710 case CK_SkylakeServer:
3711 defineCPUMacros(Builder, "skx");
3716 defineCPUMacros(Builder, "knl");
3719 Builder.defineMacro("__tune_lakemont__");
3722 Builder.defineMacro("__k6_2__");
3723 Builder.defineMacro("__tune_k6_2__");
3726 if (CPU != CK_K6_2) { // In case of fallthrough
3727 // FIXME: GCC may be enabling these in cases where some other k6
3728 // architecture is specified but -m3dnow is explicitly provided. The
3729 // exact semantics need to be determined and emulated here.
3730 Builder.defineMacro("__k6_3__");
3731 Builder.defineMacro("__tune_k6_3__");
3735 defineCPUMacros(Builder, "k6");
3738 case CK_AthlonThunderbird:
3742 defineCPUMacros(Builder, "athlon");
3743 if (SSELevel != NoSSE) {
3744 Builder.defineMacro("__athlon_sse__");
3745 Builder.defineMacro("__tune_athlon_sse__");
3752 case CK_OpteronSSE3:
3754 case CK_Athlon64SSE3:
3756 defineCPUMacros(Builder, "k8");
3759 defineCPUMacros(Builder, "amdfam10");
3762 defineCPUMacros(Builder, "btver1");
3765 defineCPUMacros(Builder, "btver2");
3768 defineCPUMacros(Builder, "bdver1");
3771 defineCPUMacros(Builder, "bdver2");
3774 defineCPUMacros(Builder, "bdver3");
3777 defineCPUMacros(Builder, "bdver4");
3780 defineCPUMacros(Builder, "znver1");
3783 defineCPUMacros(Builder, "geode");
3787 // Target properties.
3788 Builder.defineMacro("__REGISTER_PREFIX__", "");
3790 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3791 // functions in glibc header files that use FP Stack inline asm which the
3792 // backend can't deal with (PR879).
3793 Builder.defineMacro("__NO_MATH_INLINES");
3796 Builder.defineMacro("__AES__");
3799 Builder.defineMacro("__PCLMUL__");
3802 Builder.defineMacro("__LZCNT__");
3805 Builder.defineMacro("__RDRND__");
3808 Builder.defineMacro("__FSGSBASE__");
3811 Builder.defineMacro("__BMI__");
3814 Builder.defineMacro("__BMI2__");
3817 Builder.defineMacro("__POPCNT__");
3820 Builder.defineMacro("__RTM__");
3823 Builder.defineMacro("__PRFCHW__");
3826 Builder.defineMacro("__RDSEED__");
3829 Builder.defineMacro("__ADX__");
3832 Builder.defineMacro("__TBM__");
3835 Builder.defineMacro("__MWAITX__");
3839 Builder.defineMacro("__XOP__");
3841 Builder.defineMacro("__FMA4__");
3843 Builder.defineMacro("__SSE4A__");
3849 Builder.defineMacro("__FMA__");
3852 Builder.defineMacro("__F16C__");
3855 Builder.defineMacro("__AVX512CD__");
3857 Builder.defineMacro("__AVX512ER__");
3859 Builder.defineMacro("__AVX512PF__");
3861 Builder.defineMacro("__AVX512DQ__");
3863 Builder.defineMacro("__AVX512BW__");
3865 Builder.defineMacro("__AVX512VL__");
3867 Builder.defineMacro("__AVX512VBMI__");
3869 Builder.defineMacro("__AVX512IFMA__");
3872 Builder.defineMacro("__SHA__");
3875 Builder.defineMacro("__FXSR__");
3877 Builder.defineMacro("__XSAVE__");
3879 Builder.defineMacro("__XSAVEOPT__");
3881 Builder.defineMacro("__XSAVEC__");
3883 Builder.defineMacro("__XSAVES__");
3885 Builder.defineMacro("__PKU__");
3887 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3889 // Each case falls through to the previous one here.
3892 Builder.defineMacro("__AVX512F__");
3894 Builder.defineMacro("__AVX2__");
3896 Builder.defineMacro("__AVX__");
3898 Builder.defineMacro("__SSE4_2__");
3900 Builder.defineMacro("__SSE4_1__");
3902 Builder.defineMacro("__SSSE3__");
3904 Builder.defineMacro("__SSE3__");
3906 Builder.defineMacro("__SSE2__");
3907 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
3909 Builder.defineMacro("__SSE__");
3910 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
3915 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3925 Builder.defineMacro("_M_IX86_FP", Twine(2));
3928 Builder.defineMacro("_M_IX86_FP", Twine(1));
3931 Builder.defineMacro("_M_IX86_FP", Twine(0));
3935 // Each case falls through to the previous one here.
3936 switch (MMX3DNowLevel) {
3937 case AMD3DNowAthlon:
3938 Builder.defineMacro("__3dNOW_A__");
3940 Builder.defineMacro("__3dNOW__");
3942 Builder.defineMacro("__MMX__");
3947 if (CPU >= CK_i486) {
3948 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3949 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3950 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3953 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3956 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3957 return llvm::StringSwitch<bool>(Feature)
3958 .Case("aes", HasAES)
3959 .Case("avx", SSELevel >= AVX)
3960 .Case("avx2", SSELevel >= AVX2)
3961 .Case("avx512f", SSELevel >= AVX512F)
3962 .Case("avx512cd", HasAVX512CD)
3963 .Case("avx512er", HasAVX512ER)
3964 .Case("avx512pf", HasAVX512PF)
3965 .Case("avx512dq", HasAVX512DQ)
3966 .Case("avx512bw", HasAVX512BW)
3967 .Case("avx512vl", HasAVX512VL)
3968 .Case("avx512vbmi", HasAVX512VBMI)
3969 .Case("avx512ifma", HasAVX512IFMA)
3970 .Case("bmi", HasBMI)
3971 .Case("bmi2", HasBMI2)
3972 .Case("clflushopt", HasCLFLUSHOPT)
3973 .Case("clwb", HasCLWB)
3974 .Case("cx16", HasCX16)
3975 .Case("f16c", HasF16C)
3976 .Case("fma", HasFMA)
3977 .Case("fma4", XOPLevel >= FMA4)
3978 .Case("fsgsbase", HasFSGSBASE)
3979 .Case("fxsr", HasFXSR)
3980 .Case("lzcnt", HasLZCNT)
3981 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3982 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3983 .Case("mmx", MMX3DNowLevel >= MMX)
3984 .Case("movbe", HasMOVBE)
3985 .Case("mpx", HasMPX)
3986 .Case("pclmul", HasPCLMUL)
3987 .Case("pcommit", HasPCOMMIT)
3988 .Case("pku", HasPKU)
3989 .Case("popcnt", HasPOPCNT)
3990 .Case("prefetchwt1", HasPREFETCHWT1)
3991 .Case("prfchw", HasPRFCHW)
3992 .Case("rdrnd", HasRDRND)
3993 .Case("rdseed", HasRDSEED)
3994 .Case("rtm", HasRTM)
3995 .Case("sgx", HasSGX)
3996 .Case("sha", HasSHA)
3997 .Case("sse", SSELevel >= SSE1)
3998 .Case("sse2", SSELevel >= SSE2)
3999 .Case("sse3", SSELevel >= SSE3)
4000 .Case("ssse3", SSELevel >= SSSE3)
4001 .Case("sse4.1", SSELevel >= SSE41)
4002 .Case("sse4.2", SSELevel >= SSE42)
4003 .Case("sse4a", XOPLevel >= SSE4A)
4004 .Case("tbm", HasTBM)
4005 .Case("umip", HasUMIP)
4007 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
4008 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
4009 .Case("xop", XOPLevel >= XOP)
4010 .Case("xsave", HasXSAVE)
4011 .Case("xsavec", HasXSAVEC)
4012 .Case("xsaves", HasXSAVES)
4013 .Case("xsaveopt", HasXSAVEOPT)
4017 // We can't use a generic validation scheme for the features accepted here
4018 // versus subtarget features accepted in the target attribute because the
4019 // bitfield structure that's initialized in the runtime only supports the
4020 // below currently rather than the full range of subtarget features. (See
4021 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
4022 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
4023 return llvm::StringSwitch<bool>(FeatureStr)
4026 .Case("popcnt", true)
4030 .Case("ssse3", true)
4031 .Case("sse4.1", true)
4032 .Case("sse4.2", true)
4035 .Case("sse4a", true)
4039 .Case("avx512f", true)
4043 .Case("pclmul", true)
4044 .Case("avx512vl", true)
4045 .Case("avx512bw", true)
4046 .Case("avx512dq", true)
4047 .Case("avx512cd", true)
4048 .Case("avx512er", true)
4049 .Case("avx512pf", true)
4050 .Case("avx512vbmi", true)
4051 .Case("avx512ifma", true)
4056 X86TargetInfo::validateAsmConstraint(const char *&Name,
4057 TargetInfo::ConstraintInfo &Info) const {
4059 default: return false;
4060 // Constant constraints.
4061 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
4063 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
4064 // x86_64 instructions.
4066 Info.setRequiresImmediate();
4069 Info.setRequiresImmediate(0, 31);
4072 Info.setRequiresImmediate(0, 63);
4075 Info.setRequiresImmediate(-128, 127);
4078 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) });
4081 Info.setRequiresImmediate(0, 3);
4084 Info.setRequiresImmediate(0, 255);
4087 Info.setRequiresImmediate(0, 127);
4089 // Register constraints.
4090 case 'Y': // 'Y' is the first character for several 2-character constraints.
4091 // Shift the pointer to the second character of the constraint.
4096 case '0': // First SSE register.
4097 case 't': // Any SSE register, when SSE2 is enabled.
4098 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
4099 case 'm': // Any MMX register, when inter-unit moves enabled.
4100 case 'k': // AVX512 arch mask registers: k1-k7.
4101 Info.setAllowsRegister();
4104 case 'f': // Any x87 floating point stack register.
4105 // Constraint 'f' cannot be used for output operands.
4106 if (Info.ConstraintStr[0] == '=')
4108 Info.setAllowsRegister();
4116 case 'A': // edx:eax.
4117 case 't': // Top of floating point stack.
4118 case 'u': // Second from top of floating point stack.
4119 case 'q': // Any register accessible as [r]l: a, b, c, and d.
4120 case 'y': // Any MMX register.
4121 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
4122 case 'x': // Any SSE register.
4123 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0
4124 // for intermideate k reg operations).
4125 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
4126 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
4127 case 'l': // "Index" registers: any general register that can be used as an
4128 // index in a base+index memory access.
4129 Info.setAllowsRegister();
4131 // Floating point constant constraints.
4132 case 'C': // SSE floating point constant.
4133 case 'G': // x87 floating point constant.
4138 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
4139 unsigned Size) const {
4140 // Strip off constraint modifiers.
4141 while (Constraint[0] == '=' ||
4142 Constraint[0] == '+' ||
4143 Constraint[0] == '&')
4144 Constraint = Constraint.substr(1);
4146 return validateOperandSize(Constraint, Size);
4149 bool X86TargetInfo::validateInputSize(StringRef Constraint,
4150 unsigned Size) const {
4151 return validateOperandSize(Constraint, Size);
4154 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
4155 unsigned Size) const {
4156 switch (Constraint[0]) {
4159 // Registers k0-k7 (AVX512) size limit is 64 bit.
4168 if (SSELevel >= AVX512F)
4169 // 512-bit zmm registers can be used if target supports AVX512F.
4170 return Size <= 512U;
4171 else if (SSELevel >= AVX)
4172 // 256-bit ymm registers can be used if target supports AVX.
4173 return Size <= 256U;
4174 return Size <= 128U;
4176 // 'Y' is the first character for several 2-character constraints.
4177 switch (Constraint[1]) {
4180 // 'Ym' is synonymous with 'y'.
4185 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
4186 if (SSELevel >= AVX512F)
4187 return Size <= 512U;
4188 else if (SSELevel >= AVX)
4189 return Size <= 256U;
4190 return SSELevel >= SSE2 && Size <= 128U;
4199 X86TargetInfo::convertConstraint(const char *&Constraint) const {
4200 switch (*Constraint) {
4201 case 'a': return std::string("{ax}");
4202 case 'b': return std::string("{bx}");
4203 case 'c': return std::string("{cx}");
4204 case 'd': return std::string("{dx}");
4205 case 'S': return std::string("{si}");
4206 case 'D': return std::string("{di}");
4207 case 'p': // address
4208 return std::string("im");
4209 case 't': // top of floating point stack.
4210 return std::string("{st}");
4211 case 'u': // second from top of floating point stack.
4212 return std::string("{st(1)}"); // second from top of floating point stack.
4214 switch (Constraint[1]) {
4216 // Break from inner switch and fall through (copy single char),
4217 // continue parsing after copying the current constraint into
4218 // the return string.
4221 // "^" hints llvm that this is a 2 letter constraint.
4222 // "Constraint++" is used to promote the string iterator
4223 // to the next constraint.
4224 return std::string("^") + std::string(Constraint++, 2);
4228 return std::string(1, *Constraint);
4232 // X86-32 generic target
4233 class X86_32TargetInfo : public X86TargetInfo {
4235 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4236 : X86TargetInfo(Triple, Opts) {
4237 DoubleAlign = LongLongAlign = 32;
4238 LongDoubleWidth = 96;
4239 LongDoubleAlign = 32;
4240 SuitableAlign = 128;
4241 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128");
4242 SizeType = UnsignedInt;
4243 PtrDiffType = SignedInt;
4244 IntPtrType = SignedInt;
4247 // Use fpret for all types.
4248 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
4249 (1 << TargetInfo::Double) |
4250 (1 << TargetInfo::LongDouble));
4252 // x86-32 has atomics up to 8 bytes
4253 // FIXME: Check that we actually have cmpxchg8b before setting
4254 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
4255 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4257 BuiltinVaListKind getBuiltinVaListKind() const override {
4258 return TargetInfo::CharPtrBuiltinVaList;
4261 int getEHDataRegisterNumber(unsigned RegNo) const override {
4262 if (RegNo == 0) return 0;
4263 if (RegNo == 1) return 2;
4266 bool validateOperandSize(StringRef Constraint,
4267 unsigned Size) const override {
4268 switch (Constraint[0]) {
4284 return X86TargetInfo::validateOperandSize(Constraint, Size);
4286 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4287 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
4288 Builtin::FirstTSBuiltin + 1);
4292 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
4294 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4295 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {}
4297 unsigned getFloatEvalMethod() const override {
4298 unsigned Major, Minor, Micro;
4299 getTriple().getOSVersion(Major, Minor, Micro);
4300 // New NetBSD uses the default rounding mode.
4301 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
4302 return X86_32TargetInfo::getFloatEvalMethod();
4303 // NetBSD before 6.99.26 defaults to "double" rounding.
4308 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
4310 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4311 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4312 SizeType = UnsignedLong;
4313 IntPtrType = SignedLong;
4314 PtrDiffType = SignedLong;
4318 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
4320 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4321 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4322 SizeType = UnsignedLong;
4323 IntPtrType = SignedLong;
4324 PtrDiffType = SignedLong;
4328 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
4330 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4331 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4332 LongDoubleWidth = 128;
4333 LongDoubleAlign = 128;
4334 SuitableAlign = 128;
4335 MaxVectorAlign = 256;
4336 // The watchOS simulator uses the builtin bool type for Objective-C.
4337 llvm::Triple T = llvm::Triple(Triple);
4339 UseSignedCharForObjCBool = false;
4340 SizeType = UnsignedLong;
4341 IntPtrType = SignedLong;
4342 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128");
4343 HasAlignMac68kSupport = true;
4346 bool handleTargetFeatures(std::vector<std::string> &Features,
4347 DiagnosticsEngine &Diags) override {
4348 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features,
4351 // We now know the features we have: we can decide how to align vectors.
4353 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4358 // x86-32 Windows target
4359 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
4361 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4362 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4363 WCharType = UnsignedShort;
4364 DoubleAlign = LongLongAlign = 64;
4366 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4367 resetDataLayout(IsWinCOFF
4368 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
4369 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4371 void getTargetDefines(const LangOptions &Opts,
4372 MacroBuilder &Builder) const override {
4373 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4377 // x86-32 Windows Visual Studio target
4378 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
4380 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple,
4381 const TargetOptions &Opts)
4382 : WindowsX86_32TargetInfo(Triple, Opts) {
4383 LongDoubleWidth = LongDoubleAlign = 64;
4384 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4386 void getTargetDefines(const LangOptions &Opts,
4387 MacroBuilder &Builder) const override {
4388 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4389 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
4390 // The value of the following reflects processor type.
4391 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
4392 // We lost the original triple, so we use the default.
4393 Builder.defineMacro("_M_IX86", "600");
4397 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4398 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang
4399 // supports __declspec natively under -fms-extensions, but we define a no-op
4400 // __declspec macro anyway for pre-processor compatibility.
4401 if (Opts.MicrosoftExt)
4402 Builder.defineMacro("__declspec", "__declspec");
4404 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
4406 if (!Opts.MicrosoftExt) {
4407 // Provide macros for all the calling convention keywords. Provide both
4408 // single and double underscore prefixed variants. These are available on
4409 // x64 as well as x86, even though they have no effect.
4410 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
4411 for (const char *CC : CCs) {
4412 std::string GCCSpelling = "__attribute__((__";
4414 GCCSpelling += "__))";
4415 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
4416 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
4421 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4422 Builder.defineMacro("__MSVCRT__");
4423 Builder.defineMacro("__MINGW32__");
4424 addCygMingDefines(Opts, Builder);
4427 // x86-32 MinGW target
4428 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
4430 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4431 : WindowsX86_32TargetInfo(Triple, Opts) {}
4432 void getTargetDefines(const LangOptions &Opts,
4433 MacroBuilder &Builder) const override {
4434 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4435 DefineStd(Builder, "WIN32", Opts);
4436 DefineStd(Builder, "WINNT", Opts);
4437 Builder.defineMacro("_X86_");
4438 addMinGWDefines(Opts, Builder);
4442 // x86-32 Cygwin target
4443 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
4445 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4446 : X86_32TargetInfo(Triple, Opts) {
4447 WCharType = UnsignedShort;
4448 DoubleAlign = LongLongAlign = 64;
4449 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4451 void getTargetDefines(const LangOptions &Opts,
4452 MacroBuilder &Builder) const override {
4453 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4454 Builder.defineMacro("_X86_");
4455 Builder.defineMacro("__CYGWIN__");
4456 Builder.defineMacro("__CYGWIN32__");
4457 addCygMingDefines(Opts, Builder);
4458 DefineStd(Builder, "unix", Opts);
4460 Builder.defineMacro("_GNU_SOURCE");
4464 // x86-32 Haiku target
4465 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> {
4467 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4468 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4470 void getTargetDefines(const LangOptions &Opts,
4471 MacroBuilder &Builder) const override {
4472 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4473 Builder.defineMacro("__INTEL__");
4477 // X86-32 MCU target
4478 class MCUX86_32TargetInfo : public X86_32TargetInfo {
4480 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4481 : X86_32TargetInfo(Triple, Opts) {
4482 LongDoubleWidth = 64;
4483 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4484 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32");
4485 WIntType = UnsignedInt;
4488 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4489 // On MCU we support only C calling convention.
4490 return CC == CC_C ? CCCR_OK : CCCR_Warning;
4493 void getTargetDefines(const LangOptions &Opts,
4494 MacroBuilder &Builder) const override {
4495 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4496 Builder.defineMacro("__iamcu");
4497 Builder.defineMacro("__iamcu__");
4500 bool allowsLargerPreferedTypeAlignment() const override {
4506 template<typename Target>
4507 class RTEMSTargetInfo : public OSTargetInfo<Target> {
4509 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4510 MacroBuilder &Builder) const override {
4511 // RTEMS defines; list based off of gcc output
4513 Builder.defineMacro("__rtems__");
4514 Builder.defineMacro("__ELF__");
4518 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4519 : OSTargetInfo<Target>(Triple, Opts) {
4520 switch (Triple.getArch()) {
4522 case llvm::Triple::x86:
4523 // this->MCountName = ".mcount";
4525 case llvm::Triple::mips:
4526 case llvm::Triple::mipsel:
4527 case llvm::Triple::ppc:
4528 case llvm::Triple::ppc64:
4529 case llvm::Triple::ppc64le:
4530 // this->MCountName = "_mcount";
4532 case llvm::Triple::arm:
4533 // this->MCountName = "__mcount";
4539 // x86-32 RTEMS target
4540 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
4542 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4543 : X86_32TargetInfo(Triple, Opts) {
4544 SizeType = UnsignedLong;
4545 IntPtrType = SignedLong;
4546 PtrDiffType = SignedLong;
4548 void getTargetDefines(const LangOptions &Opts,
4549 MacroBuilder &Builder) const override {
4550 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4551 Builder.defineMacro("__INTEL__");
4552 Builder.defineMacro("__rtems__");
4556 // x86-64 generic target
4557 class X86_64TargetInfo : public X86TargetInfo {
4559 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4560 : X86TargetInfo(Triple, Opts) {
4561 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
4563 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4564 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
4565 LongDoubleWidth = 128;
4566 LongDoubleAlign = 128;
4567 LargeArrayMinWidth = 128;
4568 LargeArrayAlign = 128;
4569 SuitableAlign = 128;
4570 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
4571 PtrDiffType = IsX32 ? SignedInt : SignedLong;
4572 IntPtrType = IsX32 ? SignedInt : SignedLong;
4573 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
4574 Int64Type = IsX32 ? SignedLongLong : SignedLong;
4577 // Pointers are 32-bit in x32.
4578 resetDataLayout(IsX32
4579 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
4580 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
4581 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128");
4583 // Use fpret only for long double.
4584 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
4586 // Use fp2ret for _Complex long double.
4587 ComplexLongDoubleUsesFP2Ret = true;
4589 // Make __builtin_ms_va_list available.
4590 HasBuiltinMSVaList = true;
4592 // x86-64 has atomics up to 16 bytes.
4593 MaxAtomicPromoteWidth = 128;
4594 MaxAtomicInlineWidth = 128;
4596 BuiltinVaListKind getBuiltinVaListKind() const override {
4597 return TargetInfo::X86_64ABIBuiltinVaList;
4600 int getEHDataRegisterNumber(unsigned RegNo) const override {
4601 if (RegNo == 0) return 0;
4602 if (RegNo == 1) return 1;
4606 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4610 case CC_X86VectorCall:
4611 case CC_IntelOclBicc:
4612 case CC_X86_64Win64:
4613 case CC_PreserveMost:
4614 case CC_PreserveAll:
4618 return CCCR_Warning;
4622 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
4626 // for x32 we need it here explicitly
4627 bool hasInt128Type() const override { return true; }
4628 unsigned getUnwindWordWidth() const override { return 64; }
4629 unsigned getRegisterWidth() const override { return 64; }
4631 bool validateGlobalRegisterVariable(StringRef RegName,
4633 bool &HasSizeMismatch) const override {
4634 // rsp and rbp are the only 64-bit registers the x86 backend can currently
4636 if (RegName.equals("rsp") || RegName.equals("rbp")) {
4637 // Check that the register size is 64-bit.
4638 HasSizeMismatch = RegSize != 64;
4642 // Check if the register is a 32-bit register the backend can handle.
4643 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize,
4646 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4647 return llvm::makeArrayRef(BuiltinInfoX86,
4648 X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
4652 // x86-64 Windows target
4653 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
4655 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4656 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4657 WCharType = UnsignedShort;
4658 LongWidth = LongAlign = 32;
4659 DoubleAlign = LongLongAlign = 64;
4660 IntMaxType = SignedLongLong;
4661 Int64Type = SignedLongLong;
4662 SizeType = UnsignedLongLong;
4663 PtrDiffType = SignedLongLong;
4664 IntPtrType = SignedLongLong;
4667 void getTargetDefines(const LangOptions &Opts,
4668 MacroBuilder &Builder) const override {
4669 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
4670 Builder.defineMacro("_WIN64");
4673 BuiltinVaListKind getBuiltinVaListKind() const override {
4674 return TargetInfo::CharPtrBuiltinVaList;
4677 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4680 case CC_X86ThisCall:
4681 case CC_X86FastCall:
4684 case CC_X86VectorCall:
4685 case CC_IntelOclBicc:
4691 return CCCR_Warning;
4696 // x86-64 Windows Visual Studio target
4697 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
4699 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple,
4700 const TargetOptions &Opts)
4701 : WindowsX86_64TargetInfo(Triple, Opts) {
4702 LongDoubleWidth = LongDoubleAlign = 64;
4703 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4705 void getTargetDefines(const LangOptions &Opts,
4706 MacroBuilder &Builder) const override {
4707 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4708 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
4709 Builder.defineMacro("_M_X64", "100");
4710 Builder.defineMacro("_M_AMD64", "100");
4714 // x86-64 MinGW target
4715 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
4717 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4718 : WindowsX86_64TargetInfo(Triple, Opts) {
4719 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
4720 // with x86 FP ops. Weird.
4721 LongDoubleWidth = LongDoubleAlign = 128;
4722 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
4725 void getTargetDefines(const LangOptions &Opts,
4726 MacroBuilder &Builder) const override {
4727 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4728 DefineStd(Builder, "WIN64", Opts);
4729 Builder.defineMacro("__MINGW64__");
4730 addMinGWDefines(Opts, Builder);
4732 // GCC defines this macro when it is using __gxx_personality_seh0.
4733 if (!Opts.SjLjExceptions)
4734 Builder.defineMacro("__SEH__");
4738 // x86-64 Cygwin target
4739 class CygwinX86_64TargetInfo : public X86_64TargetInfo {
4741 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4742 : X86_64TargetInfo(Triple, Opts) {
4743 TLSSupported = false;
4744 WCharType = UnsignedShort;
4746 void getTargetDefines(const LangOptions &Opts,
4747 MacroBuilder &Builder) const override {
4748 X86_64TargetInfo::getTargetDefines(Opts, Builder);
4749 Builder.defineMacro("__x86_64__");
4750 Builder.defineMacro("__CYGWIN__");
4751 Builder.defineMacro("__CYGWIN64__");
4752 addCygMingDefines(Opts, Builder);
4753 DefineStd(Builder, "unix", Opts);
4755 Builder.defineMacro("_GNU_SOURCE");
4757 // GCC defines this macro when it is using __gxx_personality_seh0.
4758 if (!Opts.SjLjExceptions)
4759 Builder.defineMacro("__SEH__");
4763 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
4765 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4766 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4767 Int64Type = SignedLongLong;
4768 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
4769 llvm::Triple T = llvm::Triple(Triple);
4771 UseSignedCharForObjCBool = false;
4772 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128");
4775 bool handleTargetFeatures(std::vector<std::string> &Features,
4776 DiagnosticsEngine &Diags) override {
4777 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features,
4780 // We now know the features we have: we can decide how to align vectors.
4782 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4787 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
4789 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4790 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4791 IntMaxType = SignedLongLong;
4792 Int64Type = SignedLongLong;
4796 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
4798 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4799 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4800 IntMaxType = SignedLongLong;
4801 Int64Type = SignedLongLong;
4805 class ARMTargetInfo : public TargetInfo {
4806 // Possible FPU choices.
4815 // Possible HWDiv features.
4817 HWDivThumb = (1 << 0),
4821 static bool FPUModeIsVFP(FPUMode Mode) {
4822 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
4825 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4826 static const char * const GCCRegNames[];
4828 std::string ABI, CPU;
4830 StringRef CPUProfile;
4840 unsigned ArchKind = llvm::ARM::AK_ARMV4T;
4841 unsigned ArchProfile;
4842 unsigned ArchVersion;
4846 unsigned IsAAPCS : 1;
4849 // Initialized via features.
4850 unsigned SoftFloat : 1;
4851 unsigned SoftFloatABI : 1;
4854 unsigned Crypto : 1;
4856 unsigned Unaligned : 1;
4859 LDREX_B = (1 << 0), /// byte (8-bit)
4860 LDREX_H = (1 << 1), /// half (16-bit)
4861 LDREX_W = (1 << 2), /// word (32-bit)
4862 LDREX_D = (1 << 3), /// double (64-bit)
4867 // ACLE 6.5.1 Hardware floating point
4869 HW_FP_HP = (1 << 1), /// half (16-bit)
4870 HW_FP_SP = (1 << 2), /// single (32-bit)
4871 HW_FP_DP = (1 << 3), /// double (64-bit)
4875 static const Builtin::Info BuiltinInfo[];
4877 void setABIAAPCS() {
4880 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4881 const llvm::Triple &T = getTriple();
4883 // size_t is unsigned long on MachO-derived environments, NetBSD,
4884 // OpenBSD and Bitrig.
4885 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
4886 T.getOS() == llvm::Triple::OpenBSD ||
4887 T.getOS() == llvm::Triple::Bitrig)
4888 SizeType = UnsignedLong;
4890 SizeType = UnsignedInt;
4892 switch (T.getOS()) {
4893 case llvm::Triple::NetBSD:
4894 case llvm::Triple::OpenBSD:
4895 WCharType = SignedInt;
4897 case llvm::Triple::Win32:
4898 WCharType = UnsignedShort;
4900 case llvm::Triple::Linux:
4902 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
4903 WCharType = UnsignedInt;
4907 UseBitFieldTypeAlignment = true;
4909 ZeroLengthBitfieldBoundary = 0;
4911 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
4912 // so set preferred for small types to 32.
4913 if (T.isOSBinFormatMachO()) {
4914 resetDataLayout(BigEndian
4915 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4916 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
4917 } else if (T.isOSWindows()) {
4918 assert(!BigEndian && "Windows on ARM does not support big endian");
4927 } else if (T.isOSNaCl()) {
4928 assert(!BigEndian && "NaCl on ARM does not support big endian");
4929 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128");
4931 resetDataLayout(BigEndian
4932 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4933 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
4936 // FIXME: Enumerated types are variable width in straight AAPCS.
4939 void setABIAPCS(bool IsAAPCS16) {
4940 const llvm::Triple &T = getTriple();
4945 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4947 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
4949 // size_t is unsigned int on FreeBSD.
4950 if (T.getOS() == llvm::Triple::FreeBSD)
4951 SizeType = UnsignedInt;
4953 SizeType = UnsignedLong;
4955 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
4956 WCharType = SignedInt;
4958 // Do not respect the alignment of bit-field types when laying out
4959 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
4960 UseBitFieldTypeAlignment = false;
4962 /// gcc forces the alignment to 4 bytes, regardless of the type of the
4963 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
4965 ZeroLengthBitfieldBoundary = 32;
4967 if (T.isOSBinFormatMachO() && IsAAPCS16) {
4968 assert(!BigEndian && "AAPCS16 does not support big-endian");
4969 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128");
4970 } else if (T.isOSBinFormatMachO())
4973 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4974 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
4978 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4979 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
4981 // FIXME: Override "preferred align" for double and long long.
4984 void setArchInfo() {
4985 StringRef ArchName = getTriple().getArchName();
4987 ArchISA = llvm::ARM::parseArchISA(ArchName);
4988 CPU = llvm::ARM::getDefaultCPU(ArchName);
4989 unsigned AK = llvm::ARM::parseArch(ArchName);
4990 if (AK != llvm::ARM::AK_INVALID)
4992 setArchInfo(ArchKind);
4995 void setArchInfo(unsigned Kind) {
4998 // cache TargetParser info
5000 SubArch = llvm::ARM::getSubArch(ArchKind);
5001 ArchProfile = llvm::ARM::parseArchProfile(SubArch);
5002 ArchVersion = llvm::ARM::parseArchVersion(SubArch);
5004 // cache CPU related strings
5005 CPUAttr = getCPUAttr();
5006 CPUProfile = getCPUProfile();
5010 // when triple does not specify a sub arch,
5011 // then we are not using inline atomics
5012 bool ShouldUseInlineAtomic =
5013 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) ||
5014 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
5015 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
5016 if (ArchProfile == llvm::ARM::PK_M) {
5017 MaxAtomicPromoteWidth = 32;
5018 if (ShouldUseInlineAtomic)
5019 MaxAtomicInlineWidth = 32;
5022 MaxAtomicPromoteWidth = 64;
5023 if (ShouldUseInlineAtomic)
5024 MaxAtomicInlineWidth = 64;
5028 bool isThumb() const {
5029 return (ArchISA == llvm::ARM::IK_THUMB);
5032 bool supportsThumb() const {
5033 return CPUAttr.count('T') || ArchVersion >= 6;
5036 bool supportsThumb2() const {
5037 return CPUAttr.equals("6T2") ||
5038 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE"));
5041 StringRef getCPUAttr() const {
5042 // For most sub-arches, the build attribute CPU name is enough.
5043 // For Cortex variants, it's slightly different.
5046 return llvm::ARM::getCPUAttr(ArchKind);
5047 case llvm::ARM::AK_ARMV6M:
5049 case llvm::ARM::AK_ARMV7S:
5051 case llvm::ARM::AK_ARMV7A:
5053 case llvm::ARM::AK_ARMV7R:
5055 case llvm::ARM::AK_ARMV7M:
5057 case llvm::ARM::AK_ARMV7EM:
5059 case llvm::ARM::AK_ARMV8A:
5061 case llvm::ARM::AK_ARMV8_1A:
5063 case llvm::ARM::AK_ARMV8_2A:
5065 case llvm::ARM::AK_ARMV8MBaseline:
5067 case llvm::ARM::AK_ARMV8MMainline:
5069 case llvm::ARM::AK_ARMV8R:
5074 StringRef getCPUProfile() const {
5075 switch(ArchProfile) {
5076 case llvm::ARM::PK_A:
5078 case llvm::ARM::PK_R:
5080 case llvm::ARM::PK_M:
5088 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5089 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0),
5092 switch (getTriple().getOS()) {
5093 case llvm::Triple::NetBSD:
5094 case llvm::Triple::OpenBSD:
5095 PtrDiffType = SignedLong;
5098 PtrDiffType = SignedInt;
5102 // Cache arch related info.
5105 // {} in inline assembly are neon specifiers, not assembly variant
5107 NoAsmVariants = true;
5109 // FIXME: This duplicates code from the driver that sets the -target-abi
5110 // option - this code is used if -target-abi isn't passed and should
5111 // be unified in some way.
5112 if (Triple.isOSBinFormatMachO()) {
5113 // The backend is hardwired to assume AAPCS for M-class processors, ensure
5114 // the frontend matches that.
5115 if (Triple.getEnvironment() == llvm::Triple::EABI ||
5116 Triple.getOS() == llvm::Triple::UnknownOS ||
5117 ArchProfile == llvm::ARM::PK_M) {
5119 } else if (Triple.isWatchABI()) {
5124 } else if (Triple.isOSWindows()) {
5125 // FIXME: this is invalid for WindowsCE
5128 // Select the default based on the platform.
5129 switch (Triple.getEnvironment()) {
5130 case llvm::Triple::Android:
5131 case llvm::Triple::GNUEABI:
5132 case llvm::Triple::GNUEABIHF:
5133 case llvm::Triple::MuslEABI:
5134 case llvm::Triple::MuslEABIHF:
5135 setABI("aapcs-linux");
5137 case llvm::Triple::EABIHF:
5138 case llvm::Triple::EABI:
5141 case llvm::Triple::GNU:
5145 if (Triple.getOS() == llvm::Triple::NetBSD)
5153 // ARM targets default to using the ARM C++ ABI.
5154 TheCXXABI.set(TargetCXXABI::GenericARM);
5156 // ARM has atomics up to 8 bytes
5159 // Do force alignment of members that follow zero length bitfields. If
5160 // the alignment of the zero-length bitfield is greater than the member
5161 // that follows it, `bar', `bar' will be aligned as the type of the
5162 // zero length bitfield.
5163 UseZeroLengthBitfieldAlignment = true;
5165 if (Triple.getOS() == llvm::Triple::Linux ||
5166 Triple.getOS() == llvm::Triple::UnknownOS)
5168 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount";
5171 StringRef getABI() const override { return ABI; }
5173 bool setABI(const std::string &Name) override {
5176 // The defaults (above) are for AAPCS, check if we need to change them.
5178 // FIXME: We need support for -meabi... we could just mangle it into the
5180 if (Name == "apcs-gnu" || Name == "aapcs16") {
5181 setABIAPCS(Name == "aapcs16");
5184 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
5191 // FIXME: This should be based on Arch attributes, not CPU names.
5193 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
5195 const std::vector<std::string> &FeaturesVec) const override {
5197 std::vector<StringRef> TargetFeatures;
5198 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName());
5200 // get default FPU features
5201 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
5202 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
5204 // get default Extension features
5205 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
5206 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
5208 for (auto Feature : TargetFeatures)
5209 if (Feature[0] == '+')
5210 Features[Feature.drop_front(1)] = true;
5212 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
5215 bool handleTargetFeatures(std::vector<std::string> &Features,
5216 DiagnosticsEngine &Diags) override {
5222 SoftFloat = SoftFloatABI = false;
5225 // This does not diagnose illegal cases like having both
5226 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
5227 uint32_t HW_FP_remove = 0;
5228 for (const auto &Feature : Features) {
5229 if (Feature == "+soft-float") {
5231 } else if (Feature == "+soft-float-abi") {
5232 SoftFloatABI = true;
5233 } else if (Feature == "+vfp2") {
5235 HW_FP |= HW_FP_SP | HW_FP_DP;
5236 } else if (Feature == "+vfp3") {
5238 HW_FP |= HW_FP_SP | HW_FP_DP;
5239 } else if (Feature == "+vfp4") {
5241 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
5242 } else if (Feature == "+fp-armv8") {
5244 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
5245 } else if (Feature == "+neon") {
5247 HW_FP |= HW_FP_SP | HW_FP_DP;
5248 } else if (Feature == "+hwdiv") {
5249 HWDiv |= HWDivThumb;
5250 } else if (Feature == "+hwdiv-arm") {
5252 } else if (Feature == "+crc") {
5254 } else if (Feature == "+crypto") {
5256 } else if (Feature == "+dsp") {
5258 } else if (Feature == "+fp-only-sp") {
5259 HW_FP_remove |= HW_FP_DP;
5260 } else if (Feature == "+strict-align") {
5262 } else if (Feature == "+fp16") {
5266 HW_FP &= ~HW_FP_remove;
5268 switch (ArchVersion) {
5270 if (ArchProfile == llvm::ARM::PK_M)
5272 else if (ArchKind == llvm::ARM::AK_ARMV6K)
5273 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5278 if (ArchProfile == llvm::ARM::PK_M)
5279 LDREX = LDREX_W | LDREX_H | LDREX_B ;
5281 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5284 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5287 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
5288 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
5292 if (FPMath == FP_Neon)
5293 Features.push_back("+neonfp");
5294 else if (FPMath == FP_VFP)
5295 Features.push_back("-neonfp");
5297 // Remove front-end specific options which the backend handles differently.
5299 std::find(Features.begin(), Features.end(), "+soft-float-abi");
5300 if (Feature != Features.end())
5301 Features.erase(Feature);
5306 bool hasFeature(StringRef Feature) const override {
5307 return llvm::StringSwitch<bool>(Feature)
5309 .Case("aarch32", true)
5310 .Case("softfloat", SoftFloat)
5311 .Case("thumb", isThumb())
5312 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
5313 .Case("hwdiv", HWDiv & HWDivThumb)
5314 .Case("hwdiv-arm", HWDiv & HWDivARM)
5318 bool setCPU(const std::string &Name) override {
5319 if (Name != "generic")
5320 setArchInfo(llvm::ARM::parseCPUArch(Name));
5322 if (ArchKind == llvm::ARM::AK_INVALID)
5329 bool setFPMath(StringRef Name) override;
5331 void getTargetDefines(const LangOptions &Opts,
5332 MacroBuilder &Builder) const override {
5333 // Target identification.
5334 Builder.defineMacro("__arm");
5335 Builder.defineMacro("__arm__");
5336 // For bare-metal none-eabi.
5337 if (getTriple().getOS() == llvm::Triple::UnknownOS &&
5338 getTriple().getEnvironment() == llvm::Triple::EABI)
5339 Builder.defineMacro("__ELF__");
5341 // Target properties.
5342 Builder.defineMacro("__REGISTER_PREFIX__", "");
5344 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
5345 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
5346 if (getTriple().isWatchABI())
5347 Builder.defineMacro("__ARM_ARCH_7K__", "2");
5349 if (!CPUAttr.empty())
5350 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
5352 // ACLE 6.4.1 ARM/Thumb instruction set architecture
5353 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
5354 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
5356 if (ArchVersion >= 8) {
5357 // ACLE 6.5.7 Crypto Extension
5359 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
5360 // ACLE 6.5.8 CRC32 Extension
5362 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
5363 // ACLE 6.5.10 Numeric Maximum and Minimum
5364 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
5365 // ACLE 6.5.9 Directed Rounding
5366 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
5369 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
5370 // is not defined for the M-profile.
5371 // NOTE that the default profile is assumed to be 'A'
5372 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M)
5373 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
5375 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original
5376 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the
5377 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all
5378 // v7 and v8 architectures excluding v8-M Baseline.
5379 if (supportsThumb2())
5380 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
5381 else if (supportsThumb())
5382 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
5384 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
5385 // instruction set such as ARM or Thumb.
5386 Builder.defineMacro("__ARM_32BIT_STATE", "1");
5388 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
5390 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
5391 if (!CPUProfile.empty())
5392 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
5394 // ACLE 6.4.3 Unaligned access supported in hardware
5396 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
5398 // ACLE 6.4.4 LDREX/STREX
5400 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX));
5403 if (ArchVersion == 5 ||
5404 (ArchVersion == 6 && CPUProfile != "M") ||
5406 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
5408 // ACLE 6.5.1 Hardware Floating Point
5410 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
5413 Builder.defineMacro("__ARM_ACLE", "200");
5415 // FP16 support (we currently only support IEEE format).
5416 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
5417 Builder.defineMacro("__ARM_FP16_ARGS", "1");
5419 // ACLE 6.5.3 Fused multiply-accumulate (FMA)
5420 if (ArchVersion >= 7 && (FPU & VFP4FPU))
5421 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
5423 // Subtarget options.
5425 // FIXME: It's more complicated than this and we don't really support
5427 // Windows on ARM does not "support" interworking
5428 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows())
5429 Builder.defineMacro("__THUMB_INTERWORK__");
5431 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
5432 // Embedded targets on Darwin follow AAPCS, but not EABI.
5433 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
5434 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows())
5435 Builder.defineMacro("__ARM_EABI__");
5436 Builder.defineMacro("__ARM_PCS", "1");
5439 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" ||
5441 Builder.defineMacro("__ARM_PCS_VFP", "1");
5444 Builder.defineMacro("__SOFTFP__");
5446 if (ArchKind == llvm::ARM::AK_XSCALE)
5447 Builder.defineMacro("__XSCALE__");
5450 Builder.defineMacro("__THUMBEL__");
5451 Builder.defineMacro("__thumb__");
5452 if (supportsThumb2())
5453 Builder.defineMacro("__thumb2__");
5456 // ACLE 6.4.9 32-bit SIMD instructions
5457 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
5458 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
5460 // ACLE 6.4.10 Hardware Integer Divide
5461 if (((HWDiv & HWDivThumb) && isThumb()) ||
5462 ((HWDiv & HWDivARM) && !isThumb())) {
5463 Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
5464 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
5467 // Note, this is always on in gcc, even though it doesn't make sense.
5468 Builder.defineMacro("__APCS_32__");
5470 if (FPUModeIsVFP((FPUMode) FPU)) {
5471 Builder.defineMacro("__VFP_FP__");
5473 Builder.defineMacro("__ARM_VFPV2__");
5475 Builder.defineMacro("__ARM_VFPV3__");
5477 Builder.defineMacro("__ARM_VFPV4__");
5479 Builder.defineMacro("__ARM_FPV5__");
5482 // This only gets set when Neon instructions are actually available, unlike
5483 // the VFP define, hence the soft float and arch check. This is subtly
5484 // different from gcc, we follow the intent which was that it should be set
5485 // when Neon instructions are actually available.
5486 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
5487 Builder.defineMacro("__ARM_NEON", "1");
5488 Builder.defineMacro("__ARM_NEON__");
5489 // current AArch32 NEON implementations do not support double-precision
5490 // floating-point even when it is present in VFP.
5491 Builder.defineMacro("__ARM_NEON_FP",
5492 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP));
5495 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
5496 Opts.ShortWChar ? "2" : "4");
5498 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5499 Opts.ShortEnums ? "1" : "4");
5501 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") {
5502 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
5503 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
5504 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
5505 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
5508 // ACLE 6.4.7 DSP instructions
5510 Builder.defineMacro("__ARM_FEATURE_DSP", "1");
5513 // ACLE 6.4.8 Saturation instructions
5515 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) {
5516 Builder.defineMacro("__ARM_FEATURE_SAT", "1");
5520 // ACLE 6.4.6 Q (saturation) flag
5522 Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
5524 if (Opts.UnsafeFPMath)
5525 Builder.defineMacro("__ARM_FP_FAST", "1");
5527 if (ArchKind == llvm::ARM::AK_ARMV8_1A)
5528 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
5531 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5532 return llvm::makeArrayRef(BuiltinInfo,
5533 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin);
5535 bool isCLZForZeroUndef() const override { return false; }
5536 BuiltinVaListKind getBuiltinVaListKind() const override {
5538 ? AAPCSABIBuiltinVaList
5539 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList
5540 : TargetInfo::VoidPtrBuiltinVaList);
5542 ArrayRef<const char *> getGCCRegNames() const override;
5543 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5544 bool validateAsmConstraint(const char *&Name,
5545 TargetInfo::ConstraintInfo &Info) const override {
5550 case 't': // VFP Floating point register single precision
5551 case 'w': // VFP Floating point register double precision
5552 Info.setAllowsRegister();
5561 case 'Q': // A memory address that is a single base register.
5562 Info.setAllowsMemory();
5564 case 'U': // a memory reference...
5566 case 'q': // ...ARMV4 ldrsb
5567 case 'v': // ...VFP load/store (reg+constant offset)
5568 case 'y': // ...iWMMXt load/store
5569 case 't': // address valid for load/store opaque types wider
5571 case 'n': // valid address for Neon doubleword vector load/store
5572 case 'm': // valid address for Neon element and structure load/store
5573 case 's': // valid address for non-offset loads/stores of quad-word
5574 // values in four ARM registers
5575 Info.setAllowsMemory();
5582 std::string convertConstraint(const char *&Constraint) const override {
5584 switch (*Constraint) {
5585 case 'U': // Two-character constraint; add "^" hint for later parsing.
5586 R = std::string("^") + std::string(Constraint, 2);
5589 case 'p': // 'p' should be translated to 'r' by default.
5590 R = std::string("r");
5593 return std::string(1, *Constraint);
5598 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5599 std::string &SuggestedModifier) const override {
5600 bool isOutput = (Constraint[0] == '=');
5601 bool isInOut = (Constraint[0] == '+');
5603 // Strip off constraint modifiers.
5604 while (Constraint[0] == '=' ||
5605 Constraint[0] == '+' ||
5606 Constraint[0] == '&')
5607 Constraint = Constraint.substr(1);
5609 switch (Constraint[0]) {
5614 return (isInOut || isOutput || Size <= 64);
5616 // A register of size 32 cannot fit a vector type.
5624 const char *getClobbers() const override {
5625 // FIXME: Is this really right?
5629 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5636 return CCCR_Warning;
5640 int getEHDataRegisterNumber(unsigned RegNo) const override {
5641 if (RegNo == 0) return 0;
5642 if (RegNo == 1) return 1;
5646 bool hasSjLjLowering() const override {
5651 bool ARMTargetInfo::setFPMath(StringRef Name) {
5652 if (Name == "neon") {
5655 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
5663 const char * const ARMTargetInfo::GCCRegNames[] = {
5664 // Integer registers
5665 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5666 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
5669 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
5670 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
5671 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
5672 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5675 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
5676 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
5677 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
5678 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5681 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
5682 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
5685 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
5686 return llvm::makeArrayRef(GCCRegNames);
5689 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
5699 { { "v6", "rfp" }, "r9" },
5700 { { "sl" }, "r10" },
5701 { { "fp" }, "r11" },
5702 { { "ip" }, "r12" },
5703 { { "r13" }, "sp" },
5704 { { "r14" }, "lr" },
5705 { { "r15" }, "pc" },
5706 // The S, D and Q registers overlap, but aren't really aliases; we
5707 // don't want to substitute one of these for a different-sized one.
5710 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
5711 return llvm::makeArrayRef(GCCRegAliases);
5714 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
5715 #define BUILTIN(ID, TYPE, ATTRS) \
5716 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5717 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5718 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5719 #include "clang/Basic/BuiltinsNEON.def"
5721 #define BUILTIN(ID, TYPE, ATTRS) \
5722 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5723 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \
5724 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr },
5725 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5726 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5727 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
5728 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
5729 #include "clang/Basic/BuiltinsARM.def"
5732 class ARMleTargetInfo : public ARMTargetInfo {
5734 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5735 : ARMTargetInfo(Triple, Opts) {}
5736 void getTargetDefines(const LangOptions &Opts,
5737 MacroBuilder &Builder) const override {
5738 Builder.defineMacro("__ARMEL__");
5739 ARMTargetInfo::getTargetDefines(Opts, Builder);
5743 class ARMbeTargetInfo : public ARMTargetInfo {
5745 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5746 : ARMTargetInfo(Triple, Opts) {}
5747 void getTargetDefines(const LangOptions &Opts,
5748 MacroBuilder &Builder) const override {
5749 Builder.defineMacro("__ARMEB__");
5750 Builder.defineMacro("__ARM_BIG_ENDIAN");
5751 ARMTargetInfo::getTargetDefines(Opts, Builder);
5755 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
5756 const llvm::Triple Triple;
5758 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5759 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
5760 WCharType = UnsignedShort;
5761 SizeType = UnsignedInt;
5763 void getVisualStudioDefines(const LangOptions &Opts,
5764 MacroBuilder &Builder) const {
5765 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
5767 // FIXME: this is invalid for WindowsCE
5768 Builder.defineMacro("_M_ARM_NT", "1");
5769 Builder.defineMacro("_M_ARMT", "_M_ARM");
5770 Builder.defineMacro("_M_THUMB", "_M_ARM");
5772 assert((Triple.getArch() == llvm::Triple::arm ||
5773 Triple.getArch() == llvm::Triple::thumb) &&
5774 "invalid architecture for Windows ARM target info");
5775 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
5776 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
5778 // TODO map the complete set of values
5779 // 31: VFPv3 40: VFPv4
5780 Builder.defineMacro("_M_ARM_FP", "31");
5782 BuiltinVaListKind getBuiltinVaListKind() const override {
5783 return TargetInfo::CharPtrBuiltinVaList;
5785 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5788 case CC_X86ThisCall:
5789 case CC_X86FastCall:
5790 case CC_X86VectorCall:
5795 return CCCR_Warning;
5800 // Windows ARM + Itanium C++ ABI Target
5801 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
5803 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple,
5804 const TargetOptions &Opts)
5805 : WindowsARMTargetInfo(Triple, Opts) {
5806 TheCXXABI.set(TargetCXXABI::GenericARM);
5809 void getTargetDefines(const LangOptions &Opts,
5810 MacroBuilder &Builder) const override {
5811 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5813 if (Opts.MSVCCompat)
5814 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5818 // Windows ARM, MS (C++) ABI
5819 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
5821 MicrosoftARMleTargetInfo(const llvm::Triple &Triple,
5822 const TargetOptions &Opts)
5823 : WindowsARMTargetInfo(Triple, Opts) {
5824 TheCXXABI.set(TargetCXXABI::Microsoft);
5827 void getTargetDefines(const LangOptions &Opts,
5828 MacroBuilder &Builder) const override {
5829 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5830 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5835 class MinGWARMTargetInfo : public WindowsARMTargetInfo {
5837 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5838 : WindowsARMTargetInfo(Triple, Opts) {
5839 TheCXXABI.set(TargetCXXABI::GenericARM);
5842 void getTargetDefines(const LangOptions &Opts,
5843 MacroBuilder &Builder) const override {
5844 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5845 DefineStd(Builder, "WIN32", Opts);
5846 DefineStd(Builder, "WINNT", Opts);
5847 Builder.defineMacro("_ARM_");
5848 addMinGWDefines(Opts, Builder);
5852 // ARM Cygwin target
5853 class CygwinARMTargetInfo : public ARMleTargetInfo {
5855 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5856 : ARMleTargetInfo(Triple, Opts) {
5857 TLSSupported = false;
5858 WCharType = UnsignedShort;
5859 DoubleAlign = LongLongAlign = 64;
5860 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
5862 void getTargetDefines(const LangOptions &Opts,
5863 MacroBuilder &Builder) const override {
5864 ARMleTargetInfo::getTargetDefines(Opts, Builder);
5865 Builder.defineMacro("_ARM_");
5866 Builder.defineMacro("__CYGWIN__");
5867 Builder.defineMacro("__CYGWIN32__");
5868 DefineStd(Builder, "unix", Opts);
5870 Builder.defineMacro("_GNU_SOURCE");
5874 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> {
5876 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5877 MacroBuilder &Builder) const override {
5878 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5882 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5883 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
5884 HasAlignMac68kSupport = true;
5885 // iOS always has 64-bit atomic instructions.
5886 // FIXME: This should be based off of the target features in
5888 MaxAtomicInlineWidth = 64;
5890 if (Triple.isWatchABI()) {
5891 // Darwin on iOS uses a variant of the ARM C++ ABI.
5892 TheCXXABI.set(TargetCXXABI::WatchOS);
5894 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that
5895 // size_t is long, it's a bit weird for it to be int.
5896 PtrDiffType = SignedLong;
5898 // BOOL should be a real boolean on the new ABI
5899 UseSignedCharForObjCBool = false;
5901 TheCXXABI.set(TargetCXXABI::iOS);
5905 class AArch64TargetInfo : public TargetInfo {
5906 virtual void setDataLayout() = 0;
5907 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5908 static const char *const GCCRegNames[];
5921 static const Builtin::Info BuiltinInfo[];
5926 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5927 : TargetInfo(Triple), ABI("aapcs") {
5928 if (getTriple().getOS() == llvm::Triple::NetBSD) {
5929 WCharType = SignedInt;
5931 // NetBSD apparently prefers consistency across ARM targets to consistency
5932 // across 64-bit targets.
5933 Int64Type = SignedLongLong;
5934 IntMaxType = SignedLongLong;
5936 WCharType = UnsignedInt;
5937 Int64Type = SignedLong;
5938 IntMaxType = SignedLong;
5941 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5942 MaxVectorAlign = 128;
5943 MaxAtomicInlineWidth = 128;
5944 MaxAtomicPromoteWidth = 128;
5946 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
5947 LongDoubleFormat = &llvm::APFloat::IEEEquad();
5949 // {} in inline assembly are neon specifiers, not assembly variant
5951 NoAsmVariants = true;
5953 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
5954 // contributes to the alignment of the containing aggregate in the same way
5955 // a plain (non bit-field) member of that type would, without exception for
5956 // zero-sized or anonymous bit-fields."
5957 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
5958 UseZeroLengthBitfieldAlignment = true;
5960 // AArch64 targets default to using the ARM C++ ABI.
5961 TheCXXABI.set(TargetCXXABI::GenericAArch64);
5963 if (Triple.getOS() == llvm::Triple::Linux ||
5964 Triple.getOS() == llvm::Triple::UnknownOS)
5965 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount";
5968 StringRef getABI() const override { return ABI; }
5969 bool setABI(const std::string &Name) override {
5970 if (Name != "aapcs" && Name != "darwinpcs")
5977 bool setCPU(const std::string &Name) override {
5978 return Name == "generic" ||
5979 llvm::AArch64::parseCPUArch(Name) !=
5980 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID);
5983 void getTargetDefines(const LangOptions &Opts,
5984 MacroBuilder &Builder) const override {
5985 // Target identification.
5986 Builder.defineMacro("__aarch64__");
5988 // Target properties.
5989 Builder.defineMacro("_LP64");
5990 Builder.defineMacro("__LP64__");
5992 // ACLE predefines. Many can only have one possible value on v8 AArch64.
5993 Builder.defineMacro("__ARM_ACLE", "200");
5994 Builder.defineMacro("__ARM_ARCH", "8");
5995 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
5997 Builder.defineMacro("__ARM_64BIT_STATE", "1");
5998 Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
5999 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
6001 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
6002 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
6003 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
6004 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
6005 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
6006 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
6007 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
6009 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
6011 // 0xe implies support for half, single and double precision operations.
6012 Builder.defineMacro("__ARM_FP", "0xE");
6014 // PCS specifies this for SysV variants, which is all we support. Other ABIs
6015 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
6016 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
6017 Builder.defineMacro("__ARM_FP16_ARGS", "1");
6019 if (Opts.UnsafeFPMath)
6020 Builder.defineMacro("__ARM_FP_FAST", "1");
6022 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
6024 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
6025 Opts.ShortEnums ? "1" : "4");
6027 if (FPU == NeonMode) {
6028 Builder.defineMacro("__ARM_NEON", "1");
6029 // 64-bit NEON supports half, single and double precision operations.
6030 Builder.defineMacro("__ARM_NEON_FP", "0xE");
6034 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
6037 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
6040 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
6043 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
6045 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
6046 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
6047 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
6048 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
6049 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
6052 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6053 return llvm::makeArrayRef(BuiltinInfo,
6054 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin);
6057 bool hasFeature(StringRef Feature) const override {
6058 return Feature == "aarch64" ||
6059 Feature == "arm64" ||
6061 (Feature == "neon" && FPU == NeonMode);
6064 bool handleTargetFeatures(std::vector<std::string> &Features,
6065 DiagnosticsEngine &Diags) override {
6072 for (const auto &Feature : Features) {
6073 if (Feature == "+neon")
6075 if (Feature == "+crc")
6077 if (Feature == "+crypto")
6079 if (Feature == "+strict-align")
6081 if (Feature == "+v8.1a")
6090 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6094 case CC_PreserveMost:
6095 case CC_PreserveAll:
6098 return CCCR_Warning;
6102 bool isCLZForZeroUndef() const override { return false; }
6104 BuiltinVaListKind getBuiltinVaListKind() const override {
6105 return TargetInfo::AArch64ABIBuiltinVaList;
6108 ArrayRef<const char *> getGCCRegNames() const override;
6109 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6111 bool validateAsmConstraint(const char *&Name,
6112 TargetInfo::ConstraintInfo &Info) const override {
6116 case 'w': // Floating point and SIMD registers (V0-V31)
6117 Info.setAllowsRegister();
6119 case 'I': // Constant that can be used with an ADD instruction
6120 case 'J': // Constant that can be used with a SUB instruction
6121 case 'K': // Constant that can be used with a 32-bit logical instruction
6122 case 'L': // Constant that can be used with a 64-bit logical instruction
6123 case 'M': // Constant that can be used as a 32-bit MOV immediate
6124 case 'N': // Constant that can be used as a 64-bit MOV immediate
6125 case 'Y': // Floating point constant zero
6126 case 'Z': // Integer constant zero
6128 case 'Q': // A memory reference with base register and no offset
6129 Info.setAllowsMemory();
6131 case 'S': // A symbolic address
6132 Info.setAllowsRegister();
6135 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
6136 // Utf: A memory address suitable for ldp/stp in TF mode.
6137 // Usa: An absolute symbolic address.
6138 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
6139 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
6140 case 'z': // Zero register, wzr or xzr
6141 Info.setAllowsRegister();
6143 case 'x': // Floating point and SIMD registers (V0-V15)
6144 Info.setAllowsRegister();
6151 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
6152 std::string &SuggestedModifier) const override {
6153 // Strip off constraint modifiers.
6154 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
6155 Constraint = Constraint.substr(1);
6157 switch (Constraint[0]) {
6165 // For now assume that the person knows what they're
6166 // doing with the modifier.
6169 // By default an 'r' constraint will be in the 'x'
6174 SuggestedModifier = "w";
6181 const char *getClobbers() const override { return ""; }
6183 int getEHDataRegisterNumber(unsigned RegNo) const override {
6192 const char *const AArch64TargetInfo::GCCRegNames[] = {
6193 // 32-bit Integer registers
6194 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
6195 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
6196 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
6198 // 64-bit Integer registers
6199 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
6200 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
6201 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
6203 // 32-bit floating point regsisters
6204 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
6205 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
6206 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
6208 // 64-bit floating point regsisters
6209 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
6210 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
6211 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
6214 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
6215 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
6216 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
6219 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
6220 return llvm::makeArrayRef(GCCRegNames);
6223 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
6224 { { "w31" }, "wsp" },
6225 { { "x29" }, "fp" },
6226 { { "x30" }, "lr" },
6227 { { "x31" }, "sp" },
6228 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
6229 // don't want to substitute one of these for a different-sized one.
6232 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
6233 return llvm::makeArrayRef(GCCRegAliases);
6236 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
6237 #define BUILTIN(ID, TYPE, ATTRS) \
6238 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6239 #include "clang/Basic/BuiltinsNEON.def"
6241 #define BUILTIN(ID, TYPE, ATTRS) \
6242 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6243 #include "clang/Basic/BuiltinsAArch64.def"
6246 class AArch64leTargetInfo : public AArch64TargetInfo {
6247 void setDataLayout() override {
6248 if (getTriple().isOSBinFormatMachO())
6249 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128");
6251 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6255 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6256 : AArch64TargetInfo(Triple, Opts) {
6258 void getTargetDefines(const LangOptions &Opts,
6259 MacroBuilder &Builder) const override {
6260 Builder.defineMacro("__AARCH64EL__");
6261 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6265 class AArch64beTargetInfo : public AArch64TargetInfo {
6266 void setDataLayout() override {
6267 assert(!getTriple().isOSBinFormatMachO());
6268 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6272 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6273 : AArch64TargetInfo(Triple, Opts) {}
6274 void getTargetDefines(const LangOptions &Opts,
6275 MacroBuilder &Builder) const override {
6276 Builder.defineMacro("__AARCH64EB__");
6277 Builder.defineMacro("__AARCH_BIG_ENDIAN");
6278 Builder.defineMacro("__ARM_BIG_ENDIAN");
6279 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6283 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
6285 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
6286 MacroBuilder &Builder) const override {
6287 Builder.defineMacro("__AARCH64_SIMD__");
6288 Builder.defineMacro("__ARM64_ARCH_8__");
6289 Builder.defineMacro("__ARM_NEON__");
6290 Builder.defineMacro("__LITTLE_ENDIAN__");
6291 Builder.defineMacro("__REGISTER_PREFIX__", "");
6292 Builder.defineMacro("__arm64", "1");
6293 Builder.defineMacro("__arm64__", "1");
6295 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
6299 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6300 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
6301 Int64Type = SignedLongLong;
6302 WCharType = SignedInt;
6303 UseSignedCharForObjCBool = false;
6305 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
6306 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
6308 TheCXXABI.set(TargetCXXABI::iOS64);
6311 BuiltinVaListKind getBuiltinVaListKind() const override {
6312 return TargetInfo::CharPtrBuiltinVaList;
6316 // Hexagon abstract base class
6317 class HexagonTargetInfo : public TargetInfo {
6318 static const Builtin::Info BuiltinInfo[];
6319 static const char * const GCCRegNames[];
6320 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6322 bool HasHVX, HasHVXDouble;
6326 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6327 : TargetInfo(Triple) {
6328 // Specify the vector alignment explicitly. For v512x1, the calculated
6329 // alignment would be 512*alignment(i1), which is 512 bytes, instead of
6330 // the required minimum of 64 bytes.
6331 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-"
6332 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
6333 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048");
6334 SizeType = UnsignedInt;
6335 PtrDiffType = SignedInt;
6336 IntPtrType = SignedInt;
6338 // {} in inline assembly are packet specifiers, not assembly variant
6340 NoAsmVariants = true;
6342 LargeArrayMinWidth = 64;
6343 LargeArrayAlign = 64;
6344 UseBitFieldTypeAlignment = true;
6345 ZeroLengthBitfieldBoundary = 32;
6346 HasHVX = HasHVXDouble = false;
6347 UseLongCalls = false;
6350 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6351 return llvm::makeArrayRef(BuiltinInfo,
6352 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin);
6355 bool validateAsmConstraint(const char *&Name,
6356 TargetInfo::ConstraintInfo &Info) const override {
6361 Info.setAllowsRegister();
6366 // Relocatable constant.
6372 void getTargetDefines(const LangOptions &Opts,
6373 MacroBuilder &Builder) const override;
6375 bool isCLZForZeroUndef() const override { return false; }
6377 bool hasFeature(StringRef Feature) const override {
6378 return llvm::StringSwitch<bool>(Feature)
6379 .Case("hexagon", true)
6380 .Case("hvx", HasHVX)
6381 .Case("hvx-double", HasHVXDouble)
6382 .Case("long-calls", UseLongCalls)
6386 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6387 StringRef CPU, const std::vector<std::string> &FeaturesVec)
6390 bool handleTargetFeatures(std::vector<std::string> &Features,
6391 DiagnosticsEngine &Diags) override;
6393 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
6394 bool Enabled) const override;
6396 BuiltinVaListKind getBuiltinVaListKind() const override {
6397 return TargetInfo::CharPtrBuiltinVaList;
6399 ArrayRef<const char *> getGCCRegNames() const override;
6400 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6401 const char *getClobbers() const override {
6405 static const char *getHexagonCPUSuffix(StringRef Name) {
6406 return llvm::StringSwitch<const char*>(Name)
6407 .Case("hexagonv4", "4")
6408 .Case("hexagonv5", "5")
6409 .Case("hexagonv55", "55")
6410 .Case("hexagonv60", "60")
6414 bool setCPU(const std::string &Name) override {
6415 if (!getHexagonCPUSuffix(Name))
6421 int getEHDataRegisterNumber(unsigned RegNo) const override {
6422 return RegNo < 2 ? RegNo : -1;
6426 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
6427 MacroBuilder &Builder) const {
6428 Builder.defineMacro("__qdsp6__", "1");
6429 Builder.defineMacro("__hexagon__", "1");
6431 if (CPU == "hexagonv4") {
6432 Builder.defineMacro("__HEXAGON_V4__");
6433 Builder.defineMacro("__HEXAGON_ARCH__", "4");
6434 if (Opts.HexagonQdsp6Compat) {
6435 Builder.defineMacro("__QDSP6_V4__");
6436 Builder.defineMacro("__QDSP6_ARCH__", "4");
6438 } else if (CPU == "hexagonv5") {
6439 Builder.defineMacro("__HEXAGON_V5__");
6440 Builder.defineMacro("__HEXAGON_ARCH__", "5");
6441 if(Opts.HexagonQdsp6Compat) {
6442 Builder.defineMacro("__QDSP6_V5__");
6443 Builder.defineMacro("__QDSP6_ARCH__", "5");
6445 } else if (CPU == "hexagonv55") {
6446 Builder.defineMacro("__HEXAGON_V55__");
6447 Builder.defineMacro("__HEXAGON_ARCH__", "55");
6448 Builder.defineMacro("__QDSP6_V55__");
6449 Builder.defineMacro("__QDSP6_ARCH__", "55");
6450 } else if (CPU == "hexagonv60") {
6451 Builder.defineMacro("__HEXAGON_V60__");
6452 Builder.defineMacro("__HEXAGON_ARCH__", "60");
6453 Builder.defineMacro("__QDSP6_V60__");
6454 Builder.defineMacro("__QDSP6_ARCH__", "60");
6457 if (hasFeature("hvx")) {
6458 Builder.defineMacro("__HVX__");
6459 if (hasFeature("hvx-double"))
6460 Builder.defineMacro("__HVXDBL__");
6464 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features,
6465 DiagnosticsEngine &Diags, StringRef CPU,
6466 const std::vector<std::string> &FeaturesVec) const {
6467 // Default for v60: -hvx, -hvx-double.
6468 Features["hvx"] = false;
6469 Features["hvx-double"] = false;
6470 Features["long-calls"] = false;
6472 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6475 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
6476 DiagnosticsEngine &Diags) {
6477 for (auto &F : Features) {
6480 else if (F == "-hvx")
6481 HasHVX = HasHVXDouble = false;
6482 else if (F == "+hvx-double")
6483 HasHVX = HasHVXDouble = true;
6484 else if (F == "-hvx-double")
6485 HasHVXDouble = false;
6487 if (F == "+long-calls")
6488 UseLongCalls = true;
6489 else if (F == "-long-calls")
6490 UseLongCalls = false;
6495 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
6496 StringRef Name, bool Enabled) const {
6498 if (Name == "hvx-double")
6499 Features["hvx"] = true;
6502 Features["hvx-double"] = false;
6504 Features[Name] = Enabled;
6507 const char *const HexagonTargetInfo::GCCRegNames[] = {
6508 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6509 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6510 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6511 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
6512 "p0", "p1", "p2", "p3",
6513 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
6516 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const {
6517 return llvm::makeArrayRef(GCCRegNames);
6520 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
6521 { { "sp" }, "r29" },
6522 { { "fp" }, "r30" },
6523 { { "lr" }, "r31" },
6526 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const {
6527 return llvm::makeArrayRef(GCCRegAliases);
6531 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
6532 #define BUILTIN(ID, TYPE, ATTRS) \
6533 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6534 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6535 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6536 #include "clang/Basic/BuiltinsHexagon.def"
6539 class LanaiTargetInfo : public TargetInfo {
6540 // Class for Lanai (32-bit).
6541 // The CPU profiles supported by the Lanai backend
6547 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6548 static const char *const GCCRegNames[];
6551 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6552 : TargetInfo(Triple) {
6553 // Description string has to be kept in sync with backend.
6554 resetDataLayout("E" // Big endian
6555 "-m:e" // ELF name manging
6556 "-p:32:32" // 32 bit pointers, 32 bit aligned
6557 "-i64:64" // 64 bit integers, 64 bit aligned
6558 "-a:0:32" // 32 bit alignment of objects of aggregate type
6559 "-n32" // 32 bit native integer width
6560 "-S64" // 64 bit natural stack alignment
6563 // Setting RegParmMax equal to what mregparm was set to in the old
6567 // Set the default CPU to V11
6570 // Temporary approach to make everything at least word-aligned and allow for
6571 // safely casting between pointers with different alignment requirements.
6572 // TODO: Remove this when there are no more cast align warnings on the
6574 MinGlobalAlign = 32;
6577 void getTargetDefines(const LangOptions &Opts,
6578 MacroBuilder &Builder) const override {
6579 // Define __lanai__ when building for target lanai.
6580 Builder.defineMacro("__lanai__");
6582 // Set define for the CPU specified.
6585 Builder.defineMacro("__LANAI_V11__");
6588 llvm_unreachable("Unhandled target CPU");
6592 bool setCPU(const std::string &Name) override {
6593 CPU = llvm::StringSwitch<CPUKind>(Name)
6594 .Case("v11", CK_V11)
6597 return CPU != CK_NONE;
6600 bool hasFeature(StringRef Feature) const override {
6601 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false);
6604 ArrayRef<const char *> getGCCRegNames() const override;
6606 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6608 BuiltinVaListKind getBuiltinVaListKind() const override {
6609 return TargetInfo::VoidPtrBuiltinVaList;
6612 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
6614 bool validateAsmConstraint(const char *&Name,
6615 TargetInfo::ConstraintInfo &info) const override {
6619 const char *getClobbers() const override { return ""; }
6622 const char *const LanaiTargetInfo::GCCRegNames[] = {
6623 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
6624 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
6625 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
6627 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const {
6628 return llvm::makeArrayRef(GCCRegNames);
6631 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = {
6641 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const {
6642 return llvm::makeArrayRef(GCCRegAliases);
6645 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
6646 class SparcTargetInfo : public TargetInfo {
6647 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6648 static const char * const GCCRegNames[];
6651 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6652 : TargetInfo(Triple), SoftFloat(false) {}
6654 int getEHDataRegisterNumber(unsigned RegNo) const override {
6655 if (RegNo == 0) return 24;
6656 if (RegNo == 1) return 25;
6660 bool handleTargetFeatures(std::vector<std::string> &Features,
6661 DiagnosticsEngine &Diags) override {
6662 // Check if software floating point is enabled
6663 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
6664 if (Feature != Features.end()) {
6669 void getTargetDefines(const LangOptions &Opts,
6670 MacroBuilder &Builder) const override {
6671 DefineStd(Builder, "sparc", Opts);
6672 Builder.defineMacro("__REGISTER_PREFIX__", "");
6675 Builder.defineMacro("SOFT_FLOAT", "1");
6678 bool hasFeature(StringRef Feature) const override {
6679 return llvm::StringSwitch<bool>(Feature)
6680 .Case("softfloat", SoftFloat)
6681 .Case("sparc", true)
6685 bool hasSjLjLowering() const override {
6689 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6690 // FIXME: Implement!
6693 BuiltinVaListKind getBuiltinVaListKind() const override {
6694 return TargetInfo::VoidPtrBuiltinVaList;
6696 ArrayRef<const char *> getGCCRegNames() const override;
6697 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6698 bool validateAsmConstraint(const char *&Name,
6699 TargetInfo::ConstraintInfo &info) const override {
6700 // FIXME: Implement!
6702 case 'I': // Signed 13-bit constant
6704 case 'K': // 32-bit constant with the low 12 bits clear
6705 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
6706 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
6707 case 'N': // Same as 'K' but zext (required for SIMode)
6708 case 'O': // The constant 4096
6713 const char *getClobbers() const override {
6714 // FIXME: Implement!
6718 // No Sparc V7 for now, the backend doesn't support it anyway.
6749 enum CPUGeneration {
6754 CPUGeneration getCPUGeneration(CPUKind Kind) const {
6762 case CK_SPARCLITE86X:
6769 case CK_LEON2_AT697E:
6770 case CK_LEON2_AT697F:
6772 case CK_LEON3_UT699:
6773 case CK_LEON3_GR712RC:
6775 case CK_LEON4_GR740:
6779 case CK_ULTRASPARC3:
6786 llvm_unreachable("Unexpected CPU kind");
6789 CPUKind getCPUKind(StringRef Name) const {
6790 return llvm::StringSwitch<CPUKind>(Name)
6792 .Case("supersparc", CK_SUPERSPARC)
6793 .Case("sparclite", CK_SPARCLITE)
6794 .Case("f934", CK_F934)
6795 .Case("hypersparc", CK_HYPERSPARC)
6796 .Case("sparclite86x", CK_SPARCLITE86X)
6797 .Case("sparclet", CK_SPARCLET)
6798 .Case("tsc701", CK_TSC701)
6800 .Case("ultrasparc", CK_ULTRASPARC)
6801 .Case("ultrasparc3", CK_ULTRASPARC3)
6802 .Case("niagara", CK_NIAGARA)
6803 .Case("niagara2", CK_NIAGARA2)
6804 .Case("niagara3", CK_NIAGARA3)
6805 .Case("niagara4", CK_NIAGARA4)
6806 .Case("ma2100", CK_MYRIAD2100)
6807 .Case("ma2150", CK_MYRIAD2150)
6808 .Case("ma2450", CK_MYRIAD2450)
6809 // FIXME: the myriad2[.n] spellings are obsolete,
6810 // but a grace period is needed to allow updating dependent builds.
6811 .Case("myriad2", CK_MYRIAD2100)
6812 .Case("myriad2.1", CK_MYRIAD2100)
6813 .Case("myriad2.2", CK_MYRIAD2150)
6814 .Case("leon2", CK_LEON2)
6815 .Case("at697e", CK_LEON2_AT697E)
6816 .Case("at697f", CK_LEON2_AT697F)
6817 .Case("leon3", CK_LEON3)
6818 .Case("ut699", CK_LEON3_UT699)
6819 .Case("gr712rc", CK_LEON3_GR712RC)
6820 .Case("leon4", CK_LEON4)
6821 .Case("gr740", CK_LEON4_GR740)
6822 .Default(CK_GENERIC);
6825 bool setCPU(const std::string &Name) override {
6826 CPU = getCPUKind(Name);
6827 return CPU != CK_GENERIC;
6831 const char * const SparcTargetInfo::GCCRegNames[] = {
6832 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6833 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6834 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6835 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6838 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
6839 return llvm::makeArrayRef(GCCRegNames);
6842 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
6853 { { "o2" }, "r10" },
6854 { { "o3" }, "r11" },
6855 { { "o4" }, "r12" },
6856 { { "o5" }, "r13" },
6857 { { "o6", "sp" }, "r14" },
6858 { { "o7" }, "r15" },
6859 { { "l0" }, "r16" },
6860 { { "l1" }, "r17" },
6861 { { "l2" }, "r18" },
6862 { { "l3" }, "r19" },
6863 { { "l4" }, "r20" },
6864 { { "l5" }, "r21" },
6865 { { "l6" }, "r22" },
6866 { { "l7" }, "r23" },
6867 { { "i0" }, "r24" },
6868 { { "i1" }, "r25" },
6869 { { "i2" }, "r26" },
6870 { { "i3" }, "r27" },
6871 { { "i4" }, "r28" },
6872 { { "i5" }, "r29" },
6873 { { "i6", "fp" }, "r30" },
6874 { { "i7" }, "r31" },
6877 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
6878 return llvm::makeArrayRef(GCCRegAliases);
6881 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
6882 class SparcV8TargetInfo : public SparcTargetInfo {
6884 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6885 : SparcTargetInfo(Triple, Opts) {
6886 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64");
6887 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
6888 switch (getTriple().getOS()) {
6890 SizeType = UnsignedInt;
6891 IntPtrType = SignedInt;
6892 PtrDiffType = SignedInt;
6894 case llvm::Triple::NetBSD:
6895 case llvm::Triple::OpenBSD:
6896 SizeType = UnsignedLong;
6897 IntPtrType = SignedLong;
6898 PtrDiffType = SignedLong;
6901 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops
6902 // on up to 64 bits.
6903 MaxAtomicPromoteWidth = 64;
6904 MaxAtomicInlineWidth = 32;
6907 void getTargetDefines(const LangOptions &Opts,
6908 MacroBuilder &Builder) const override {
6909 SparcTargetInfo::getTargetDefines(Opts, Builder);
6910 switch (getCPUGeneration(CPU)) {
6912 Builder.defineMacro("__sparcv8");
6913 if (getTriple().getOS() != llvm::Triple::Solaris)
6914 Builder.defineMacro("__sparcv8__");
6917 Builder.defineMacro("__sparcv9");
6918 if (getTriple().getOS() != llvm::Triple::Solaris) {
6919 Builder.defineMacro("__sparcv9__");
6920 Builder.defineMacro("__sparc_v9__");
6924 if (getTriple().getVendor() == llvm::Triple::Myriad) {
6925 std::string MyriadArchValue, Myriad2Value;
6926 Builder.defineMacro("__sparc_v8__");
6927 Builder.defineMacro("__leon__");
6930 MyriadArchValue = "__ma2150";
6934 MyriadArchValue = "__ma2450";
6938 MyriadArchValue = "__ma2100";
6942 Builder.defineMacro(MyriadArchValue, "1");
6943 Builder.defineMacro(MyriadArchValue+"__", "1");
6944 Builder.defineMacro("__myriad2__", Myriad2Value);
6945 Builder.defineMacro("__myriad2", Myriad2Value);
6949 bool hasSjLjLowering() const override {
6954 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
6955 class SparcV8elTargetInfo : public SparcV8TargetInfo {
6957 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6958 : SparcV8TargetInfo(Triple, Opts) {
6959 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64");
6963 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
6964 class SparcV9TargetInfo : public SparcTargetInfo {
6966 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6967 : SparcTargetInfo(Triple, Opts) {
6968 // FIXME: Support Sparc quad-precision long double?
6969 resetDataLayout("E-m:e-i64:64-n32:64-S128");
6970 // This is an LP64 platform.
6971 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6973 // OpenBSD uses long long for int64_t and intmax_t.
6974 if (getTriple().getOS() == llvm::Triple::OpenBSD)
6975 IntMaxType = SignedLongLong;
6977 IntMaxType = SignedLong;
6978 Int64Type = IntMaxType;
6980 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
6981 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
6982 LongDoubleWidth = 128;
6983 LongDoubleAlign = 128;
6984 LongDoubleFormat = &llvm::APFloat::IEEEquad();
6985 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6988 void getTargetDefines(const LangOptions &Opts,
6989 MacroBuilder &Builder) const override {
6990 SparcTargetInfo::getTargetDefines(Opts, Builder);
6991 Builder.defineMacro("__sparcv9");
6992 Builder.defineMacro("__arch64__");
6993 // Solaris doesn't need these variants, but the BSDs do.
6994 if (getTriple().getOS() != llvm::Triple::Solaris) {
6995 Builder.defineMacro("__sparc64__");
6996 Builder.defineMacro("__sparc_v9__");
6997 Builder.defineMacro("__sparcv9__");
7001 bool setCPU(const std::string &Name) override {
7002 if (!SparcTargetInfo::setCPU(Name))
7004 return getCPUGeneration(CPU) == CG_V9;
7008 class SystemZTargetInfo : public TargetInfo {
7009 static const Builtin::Info BuiltinInfo[];
7010 static const char *const GCCRegNames[];
7012 bool HasTransactionalExecution;
7016 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7017 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false),
7019 IntMaxType = SignedLong;
7020 Int64Type = SignedLong;
7021 TLSSupported = true;
7022 IntWidth = IntAlign = 32;
7023 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
7024 PointerWidth = PointerAlign = 64;
7025 LongDoubleWidth = 128;
7026 LongDoubleAlign = 64;
7027 LongDoubleFormat = &llvm::APFloat::IEEEquad();
7028 DefaultAlignForAttributeAligned = 64;
7029 MinGlobalAlign = 16;
7030 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64");
7031 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7033 void getTargetDefines(const LangOptions &Opts,
7034 MacroBuilder &Builder) const override {
7035 Builder.defineMacro("__s390__");
7036 Builder.defineMacro("__s390x__");
7037 Builder.defineMacro("__zarch__");
7038 Builder.defineMacro("__LONG_DOUBLE_128__");
7040 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
7041 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
7042 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
7043 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
7045 if (HasTransactionalExecution)
7046 Builder.defineMacro("__HTM__");
7048 Builder.defineMacro("__VEC__", "10301");
7050 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7051 return llvm::makeArrayRef(BuiltinInfo,
7052 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin);
7055 ArrayRef<const char *> getGCCRegNames() const override;
7056 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7060 bool validateAsmConstraint(const char *&Name,
7061 TargetInfo::ConstraintInfo &info) const override;
7062 const char *getClobbers() const override {
7063 // FIXME: Is this really right?
7066 BuiltinVaListKind getBuiltinVaListKind() const override {
7067 return TargetInfo::SystemZBuiltinVaList;
7069 bool setCPU(const std::string &Name) override {
7071 bool CPUKnown = llvm::StringSwitch<bool>(Name)
7073 .Case("arch8", true)
7075 .Case("arch9", true)
7076 .Case("zEC12", true)
7077 .Case("arch10", true)
7079 .Case("arch11", true)
7085 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7087 const std::vector<std::string> &FeaturesVec) const override {
7088 if (CPU == "zEC12" || CPU == "arch10")
7089 Features["transactional-execution"] = true;
7090 if (CPU == "z13" || CPU == "arch11") {
7091 Features["transactional-execution"] = true;
7092 Features["vector"] = true;
7094 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7097 bool handleTargetFeatures(std::vector<std::string> &Features,
7098 DiagnosticsEngine &Diags) override {
7099 HasTransactionalExecution = false;
7100 for (const auto &Feature : Features) {
7101 if (Feature == "+transactional-execution")
7102 HasTransactionalExecution = true;
7103 else if (Feature == "+vector")
7106 // If we use the vector ABI, vector types are 64-bit aligned.
7108 MaxVectorAlign = 64;
7109 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
7110 "-v128:64-a:8:16-n32:64");
7115 bool hasFeature(StringRef Feature) const override {
7116 return llvm::StringSwitch<bool>(Feature)
7117 .Case("systemz", true)
7118 .Case("htm", HasTransactionalExecution)
7119 .Case("vx", HasVector)
7123 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
7129 return CCCR_Warning;
7133 StringRef getABI() const override {
7139 bool useFloat128ManglingForLongDouble() const override {
7144 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
7145 #define BUILTIN(ID, TYPE, ATTRS) \
7146 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7147 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
7148 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
7149 #include "clang/Basic/BuiltinsSystemZ.def"
7152 const char *const SystemZTargetInfo::GCCRegNames[] = {
7153 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7154 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7155 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
7156 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
7159 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
7160 return llvm::makeArrayRef(GCCRegNames);
7163 bool SystemZTargetInfo::
7164 validateAsmConstraint(const char *&Name,
7165 TargetInfo::ConstraintInfo &Info) const {
7170 case 'a': // Address register
7171 case 'd': // Data register (equivalent to 'r')
7172 case 'f': // Floating-point register
7173 Info.setAllowsRegister();
7176 case 'I': // Unsigned 8-bit constant
7177 case 'J': // Unsigned 12-bit constant
7178 case 'K': // Signed 16-bit constant
7179 case 'L': // Signed 20-bit displacement (on all targets we support)
7180 case 'M': // 0x7fffffff
7183 case 'Q': // Memory with base and unsigned 12-bit displacement
7184 case 'R': // Likewise, plus an index
7185 case 'S': // Memory with base and signed 20-bit displacement
7186 case 'T': // Likewise, plus an index
7187 Info.setAllowsMemory();
7192 class MSP430TargetInfo : public TargetInfo {
7193 static const char *const GCCRegNames[];
7196 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7197 : TargetInfo(Triple) {
7198 TLSSupported = false;
7203 LongAlign = LongLongAlign = 16;
7207 SizeType = UnsignedInt;
7208 IntMaxType = SignedLongLong;
7209 IntPtrType = SignedInt;
7210 PtrDiffType = SignedInt;
7211 SigAtomicType = SignedLong;
7212 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16");
7214 void getTargetDefines(const LangOptions &Opts,
7215 MacroBuilder &Builder) const override {
7216 Builder.defineMacro("MSP430");
7217 Builder.defineMacro("__MSP430__");
7218 // FIXME: defines for different 'flavours' of MCU
7220 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7221 // FIXME: Implement.
7224 bool hasFeature(StringRef Feature) const override {
7225 return Feature == "msp430";
7227 ArrayRef<const char *> getGCCRegNames() const override;
7228 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7232 bool validateAsmConstraint(const char *&Name,
7233 TargetInfo::ConstraintInfo &info) const override {
7236 case 'K': // the constant 1
7237 case 'L': // constant -1^20 .. 1^19
7238 case 'M': // constant 1-4:
7241 // No target constraints for now.
7244 const char *getClobbers() const override {
7245 // FIXME: Is this really right?
7248 BuiltinVaListKind getBuiltinVaListKind() const override {
7250 return TargetInfo::CharPtrBuiltinVaList;
7254 const char *const MSP430TargetInfo::GCCRegNames[] = {
7255 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7256 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
7258 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const {
7259 return llvm::makeArrayRef(GCCRegNames);
7262 // LLVM and Clang cannot be used directly to output native binaries for
7263 // target, but is used to compile C code to llvm bitcode with correct
7264 // type and alignment information.
7266 // TCE uses the llvm bitcode as input and uses it for generating customized
7267 // target processor and program binary. TCE co-design environment is
7268 // publicly available in http://tce.cs.tut.fi
7270 static const unsigned TCEOpenCLAddrSpaceMap[] = {
7273 5, // opencl_constant
7274 // FIXME: generic has to be added to the target
7275 0, // opencl_generic
7281 class TCETargetInfo : public TargetInfo {
7283 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7284 : TargetInfo(Triple) {
7285 TLSSupported = false;
7287 LongWidth = LongLongWidth = 32;
7290 LongAlign = LongLongAlign = 32;
7293 SizeType = UnsignedInt;
7294 IntMaxType = SignedLong;
7295 IntPtrType = SignedInt;
7296 PtrDiffType = SignedInt;
7301 LongDoubleWidth = 32;
7302 LongDoubleAlign = 32;
7303 FloatFormat = &llvm::APFloat::IEEEsingle();
7304 DoubleFormat = &llvm::APFloat::IEEEsingle();
7305 LongDoubleFormat = &llvm::APFloat::IEEEsingle();
7306 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-"
7307 "i16:16:32-i32:32:32-i64:32:32-"
7308 "f32:32:32-f64:32:32-v64:32:32-"
7309 "v128:32:32-v256:32:32-v512:32:32-"
7310 "v1024:32:32-a0:0:32-n32");
7311 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
7312 UseAddrSpaceMapMangling = true;
7315 void getTargetDefines(const LangOptions &Opts,
7316 MacroBuilder &Builder) const override {
7317 DefineStd(Builder, "tce", Opts);
7318 Builder.defineMacro("__TCE__");
7319 Builder.defineMacro("__TCE_V1__");
7321 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; }
7323 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7324 const char *getClobbers() const override { return ""; }
7325 BuiltinVaListKind getBuiltinVaListKind() const override {
7326 return TargetInfo::VoidPtrBuiltinVaList;
7328 ArrayRef<const char *> getGCCRegNames() const override { return None; }
7329 bool validateAsmConstraint(const char *&Name,
7330 TargetInfo::ConstraintInfo &info) const override {
7333 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7338 class TCELETargetInfo : public TCETargetInfo {
7340 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7341 : TCETargetInfo(Triple, Opts) {
7344 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-"
7345 "i16:16:32-i32:32:32-i64:32:32-"
7346 "f32:32:32-f64:32:32-v64:32:32-"
7347 "v128:32:32-v256:32:32-v512:32:32-"
7348 "v1024:32:32-a0:0:32-n32");
7352 virtual void getTargetDefines(const LangOptions &Opts,
7353 MacroBuilder &Builder) const {
7354 DefineStd(Builder, "tcele", Opts);
7355 Builder.defineMacro("__TCE__");
7356 Builder.defineMacro("__TCE_V1__");
7357 Builder.defineMacro("__TCELE__");
7358 Builder.defineMacro("__TCELE_V1__");
7363 class BPFTargetInfo : public TargetInfo {
7365 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7366 : TargetInfo(Triple) {
7367 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7368 SizeType = UnsignedLong;
7369 PtrDiffType = SignedLong;
7370 IntPtrType = SignedLong;
7371 IntMaxType = SignedLong;
7372 Int64Type = SignedLong;
7374 if (Triple.getArch() == llvm::Triple::bpfeb) {
7375 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128");
7377 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
7379 MaxAtomicPromoteWidth = 64;
7380 MaxAtomicInlineWidth = 64;
7381 TLSSupported = false;
7383 void getTargetDefines(const LangOptions &Opts,
7384 MacroBuilder &Builder) const override {
7385 DefineStd(Builder, "bpf", Opts);
7386 Builder.defineMacro("__BPF__");
7388 bool hasFeature(StringRef Feature) const override {
7389 return Feature == "bpf";
7392 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7393 const char *getClobbers() const override {
7396 BuiltinVaListKind getBuiltinVaListKind() const override {
7397 return TargetInfo::VoidPtrBuiltinVaList;
7399 ArrayRef<const char *> getGCCRegNames() const override {
7402 bool validateAsmConstraint(const char *&Name,
7403 TargetInfo::ConstraintInfo &info) const override {
7406 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7411 class MipsTargetInfo : public TargetInfo {
7412 void setDataLayout() {
7416 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
7417 else if (ABI == "n32")
7418 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7419 else if (ABI == "n64")
7420 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7422 llvm_unreachable("Invalid ABI");
7425 resetDataLayout(("E-" + Layout).str());
7427 resetDataLayout(("e-" + Layout).str());
7431 static const Builtin::Info BuiltinInfo[];
7438 HardFloat, SoftFloat
7450 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7451 : TargetInfo(Triple), IsMips16(false), IsMicromips(false),
7452 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
7453 DspRev(NoDSP), HasMSA(false), HasFP64(false) {
7454 TheCXXABI.set(TargetCXXABI::GenericMIPS);
7456 setABI((getTriple().getArch() == llvm::Triple::mips ||
7457 getTriple().getArch() == llvm::Triple::mipsel)
7461 CPU = ABI == "o32" ? "mips32r2" : "mips64r2";
7464 bool isNaN2008Default() const {
7465 return CPU == "mips32r6" || CPU == "mips64r6";
7468 bool isFP64Default() const {
7469 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
7472 bool isNan2008() const override {
7476 bool processorSupportsGPR64() const {
7477 return llvm::StringSwitch<bool>(CPU)
7478 .Case("mips3", true)
7479 .Case("mips4", true)
7480 .Case("mips5", true)
7481 .Case("mips64", true)
7482 .Case("mips64r2", true)
7483 .Case("mips64r3", true)
7484 .Case("mips64r5", true)
7485 .Case("mips64r6", true)
7486 .Case("octeon", true)
7491 StringRef getABI() const override { return ABI; }
7492 bool setABI(const std::string &Name) override {
7493 if (Name == "o32") {
7499 if (Name == "n32") {
7504 if (Name == "n64") {
7512 void setO32ABITypes() {
7513 Int64Type = SignedLongLong;
7514 IntMaxType = Int64Type;
7515 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
7516 LongDoubleWidth = LongDoubleAlign = 64;
7517 LongWidth = LongAlign = 32;
7518 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
7519 PointerWidth = PointerAlign = 32;
7520 PtrDiffType = SignedInt;
7521 SizeType = UnsignedInt;
7525 void setN32N64ABITypes() {
7526 LongDoubleWidth = LongDoubleAlign = 128;
7527 LongDoubleFormat = &llvm::APFloat::IEEEquad();
7528 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
7529 LongDoubleWidth = LongDoubleAlign = 64;
7530 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
7532 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7533 SuitableAlign = 128;
7536 void setN64ABITypes() {
7537 setN32N64ABITypes();
7538 Int64Type = SignedLong;
7539 IntMaxType = Int64Type;
7540 LongWidth = LongAlign = 64;
7541 PointerWidth = PointerAlign = 64;
7542 PtrDiffType = SignedLong;
7543 SizeType = UnsignedLong;
7546 void setN32ABITypes() {
7547 setN32N64ABITypes();
7548 Int64Type = SignedLongLong;
7549 IntMaxType = Int64Type;
7550 LongWidth = LongAlign = 32;
7551 PointerWidth = PointerAlign = 32;
7552 PtrDiffType = SignedInt;
7553 SizeType = UnsignedInt;
7556 bool setCPU(const std::string &Name) override {
7558 return llvm::StringSwitch<bool>(Name)
7559 .Case("mips1", true)
7560 .Case("mips2", true)
7561 .Case("mips3", true)
7562 .Case("mips4", true)
7563 .Case("mips5", true)
7564 .Case("mips32", true)
7565 .Case("mips32r2", true)
7566 .Case("mips32r3", true)
7567 .Case("mips32r5", true)
7568 .Case("mips32r6", true)
7569 .Case("mips64", true)
7570 .Case("mips64r2", true)
7571 .Case("mips64r3", true)
7572 .Case("mips64r5", true)
7573 .Case("mips64r6", true)
7574 .Case("octeon", true)
7575 .Case("p5600", true)
7578 const std::string& getCPU() const { return CPU; }
7580 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7582 const std::vector<std::string> &FeaturesVec) const override {
7585 if (CPU == "octeon")
7586 Features["mips64r2"] = Features["cnmips"] = true;
7588 Features[CPU] = true;
7589 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7592 void getTargetDefines(const LangOptions &Opts,
7593 MacroBuilder &Builder) const override {
7595 DefineStd(Builder, "MIPSEB", Opts);
7596 Builder.defineMacro("_MIPSEB");
7598 DefineStd(Builder, "MIPSEL", Opts);
7599 Builder.defineMacro("_MIPSEL");
7602 Builder.defineMacro("__mips__");
7603 Builder.defineMacro("_mips");
7605 Builder.defineMacro("mips");
7608 Builder.defineMacro("__mips", "32");
7609 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
7611 Builder.defineMacro("__mips", "64");
7612 Builder.defineMacro("__mips64");
7613 Builder.defineMacro("__mips64__");
7614 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
7617 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU())
7618 .Cases("mips32", "mips64", "1")
7619 .Cases("mips32r2", "mips64r2", "2")
7620 .Cases("mips32r3", "mips64r3", "3")
7621 .Cases("mips32r5", "mips64r5", "5")
7622 .Cases("mips32r6", "mips64r6", "6")
7624 if (!ISARev.empty())
7625 Builder.defineMacro("__mips_isa_rev", ISARev);
7628 Builder.defineMacro("__mips_o32");
7629 Builder.defineMacro("_ABIO32", "1");
7630 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
7631 } else if (ABI == "n32") {
7632 Builder.defineMacro("__mips_n32");
7633 Builder.defineMacro("_ABIN32", "2");
7634 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
7635 } else if (ABI == "n64") {
7636 Builder.defineMacro("__mips_n64");
7637 Builder.defineMacro("_ABI64", "3");
7638 Builder.defineMacro("_MIPS_SIM", "_ABI64");
7640 llvm_unreachable("Invalid ABI.");
7642 Builder.defineMacro("__REGISTER_PREFIX__", "");
7646 Builder.defineMacro("__mips_hard_float", Twine(1));
7649 Builder.defineMacro("__mips_soft_float", Twine(1));
7654 Builder.defineMacro("__mips_single_float", Twine(1));
7656 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
7657 Builder.defineMacro("_MIPS_FPSET",
7658 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
7661 Builder.defineMacro("__mips16", Twine(1));
7664 Builder.defineMacro("__mips_micromips", Twine(1));
7667 Builder.defineMacro("__mips_nan2008", Twine(1));
7673 Builder.defineMacro("__mips_dsp_rev", Twine(1));
7674 Builder.defineMacro("__mips_dsp", Twine(1));
7677 Builder.defineMacro("__mips_dsp_rev", Twine(2));
7678 Builder.defineMacro("__mips_dspr2", Twine(1));
7679 Builder.defineMacro("__mips_dsp", Twine(1));
7684 Builder.defineMacro("__mips_msa", Twine(1));
7686 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
7687 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
7688 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
7690 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
7691 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
7693 // These shouldn't be defined for MIPS-I but there's no need to check
7694 // for that since MIPS-I isn't supported.
7695 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
7696 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
7697 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
7699 // 32-bit MIPS processors don't have the necessary lld/scd instructions
7700 // found in 64-bit processors. In the case of O32 on a 64-bit processor,
7701 // the instructions exist but using them violates the ABI since they
7702 // require 64-bit GPRs and O32 only supports 32-bit GPRs.
7703 if (ABI == "n32" || ABI == "n64")
7704 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
7707 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7708 return llvm::makeArrayRef(BuiltinInfo,
7709 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin);
7711 bool hasFeature(StringRef Feature) const override {
7712 return llvm::StringSwitch<bool>(Feature)
7714 .Case("fp64", HasFP64)
7717 BuiltinVaListKind getBuiltinVaListKind() const override {
7718 return TargetInfo::VoidPtrBuiltinVaList;
7720 ArrayRef<const char *> getGCCRegNames() const override {
7721 static const char *const GCCRegNames[] = {
7722 // CPU register names
7723 // Must match second column of GCCRegAliases
7724 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
7725 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
7726 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
7727 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
7728 // Floating point register names
7729 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
7730 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
7731 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
7732 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
7733 // Hi/lo and condition register names
7734 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
7735 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo",
7737 // MSA register names
7738 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
7739 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
7740 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
7741 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
7742 // MSA control register names
7743 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
7744 "$msarequest", "$msamap", "$msaunmap"
7746 return llvm::makeArrayRef(GCCRegNames);
7748 bool validateAsmConstraint(const char *&Name,
7749 TargetInfo::ConstraintInfo &Info) const override {
7753 case 'r': // CPU registers.
7754 case 'd': // Equivalent to "r" unless generating MIPS16 code.
7755 case 'y': // Equivalent to "r", backward compatibility only.
7756 case 'f': // floating-point registers.
7757 case 'c': // $25 for indirect jumps
7758 case 'l': // lo register
7759 case 'x': // hilo register pair
7760 Info.setAllowsRegister();
7762 case 'I': // Signed 16-bit constant
7763 case 'J': // Integer 0
7764 case 'K': // Unsigned 16-bit constant
7765 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
7766 case 'M': // Constants not loadable via lui, addiu, or ori
7767 case 'N': // Constant -1 to -65535
7768 case 'O': // A signed 15-bit constant
7769 case 'P': // A constant between 1 go 65535
7771 case 'R': // An address that can be used in a non-macro load or store
7772 Info.setAllowsMemory();
7775 if (Name[1] == 'C') { // An address usable by ll, and sc.
7776 Info.setAllowsMemory();
7777 Name++; // Skip over 'Z'.
7784 std::string convertConstraint(const char *&Constraint) const override {
7786 switch (*Constraint) {
7787 case 'Z': // Two-character constraint; add "^" hint for later parsing.
7788 if (Constraint[1] == 'C') {
7789 R = std::string("^") + std::string(Constraint, 2);
7795 return TargetInfo::convertConstraint(Constraint);
7798 const char *getClobbers() const override {
7799 // In GCC, $1 is not widely used in generated code (it's used only in a few
7800 // specific situations), so there is no real need for users to add it to
7801 // the clobbers list if they want to use it in their inline assembly code.
7803 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
7804 // code generation, so using it in inline assembly without adding it to the
7805 // clobbers list can cause conflicts between the inline assembly code and
7806 // the surrounding generated code.
7808 // Another problem is that LLVM is allowed to choose $1 for inline assembly
7809 // operands, which will conflict with the ".set at" assembler option (which
7810 // we use only for inline assembly, in order to maintain compatibility with
7811 // GCC) and will also conflict with the user's usage of $1.
7813 // The easiest way to avoid these conflicts and keep $1 as an allocatable
7814 // register for generated code is to automatically clobber $1 for all inline
7817 // FIXME: We should automatically clobber $1 only for inline assembly code
7818 // which actually uses it. This would allow LLVM to use $1 for inline
7819 // assembly operands if the user's assembly code doesn't use it.
7823 bool handleTargetFeatures(std::vector<std::string> &Features,
7824 DiagnosticsEngine &Diags) override {
7826 IsMicromips = false;
7827 IsNan2008 = isNaN2008Default();
7828 IsSingleFloat = false;
7829 FloatABI = HardFloat;
7831 HasFP64 = isFP64Default();
7833 for (const auto &Feature : Features) {
7834 if (Feature == "+single-float")
7835 IsSingleFloat = true;
7836 else if (Feature == "+soft-float")
7837 FloatABI = SoftFloat;
7838 else if (Feature == "+mips16")
7840 else if (Feature == "+micromips")
7842 else if (Feature == "+dsp")
7843 DspRev = std::max(DspRev, DSP1);
7844 else if (Feature == "+dspr2")
7845 DspRev = std::max(DspRev, DSP2);
7846 else if (Feature == "+msa")
7848 else if (Feature == "+fp64")
7850 else if (Feature == "-fp64")
7852 else if (Feature == "+nan2008")
7854 else if (Feature == "-nan2008")
7863 int getEHDataRegisterNumber(unsigned RegNo) const override {
7864 if (RegNo == 0) return 4;
7865 if (RegNo == 1) return 5;
7869 bool isCLZForZeroUndef() const override { return false; }
7871 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7872 static const TargetInfo::GCCRegAlias O32RegAliases[] = {
7873 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
7874 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
7875 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"},
7876 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"},
7877 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"},
7878 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
7879 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
7880 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
7881 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
7882 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
7884 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = {
7885 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
7886 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
7887 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"},
7888 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"},
7889 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"},
7890 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
7891 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
7892 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
7893 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
7894 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
7897 return llvm::makeArrayRef(O32RegAliases);
7898 return llvm::makeArrayRef(NewABIRegAliases);
7901 bool hasInt128Type() const override {
7902 return ABI == "n32" || ABI == "n64";
7905 bool validateTarget(DiagnosticsEngine &Diags) const override {
7906 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle
7907 // this yet. It's better to fail here than on the backend assertion.
7908 if (processorSupportsGPR64() && ABI == "o32") {
7909 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
7913 // 64-bit ABI's require 64-bit CPU's.
7914 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) {
7915 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
7919 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend
7920 // can't handle this yet. It's better to fail here than on the
7921 // backend assertion.
7922 if ((getTriple().getArch() == llvm::Triple::mips64 ||
7923 getTriple().getArch() == llvm::Triple::mips64el) &&
7925 Diags.Report(diag::err_target_unsupported_abi_for_triple)
7926 << ABI << getTriple().str();
7930 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend
7931 // can't handle this yet. It's better to fail here than on the
7932 // backend assertion.
7933 if ((getTriple().getArch() == llvm::Triple::mips ||
7934 getTriple().getArch() == llvm::Triple::mipsel) &&
7935 (ABI == "n32" || ABI == "n64")) {
7936 Diags.Report(diag::err_target_unsupported_abi_for_triple)
7937 << ABI << getTriple().str();
7945 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = {
7946 #define BUILTIN(ID, TYPE, ATTRS) \
7947 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7948 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
7949 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
7950 #include "clang/Basic/BuiltinsMips.def"
7953 class PNaClTargetInfo : public TargetInfo {
7955 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7956 : TargetInfo(Triple) {
7957 this->LongAlign = 32;
7958 this->LongWidth = 32;
7959 this->PointerAlign = 32;
7960 this->PointerWidth = 32;
7961 this->IntMaxType = TargetInfo::SignedLongLong;
7962 this->Int64Type = TargetInfo::SignedLongLong;
7963 this->DoubleAlign = 64;
7964 this->LongDoubleWidth = 64;
7965 this->LongDoubleAlign = 64;
7966 this->SizeType = TargetInfo::UnsignedInt;
7967 this->PtrDiffType = TargetInfo::SignedInt;
7968 this->IntPtrType = TargetInfo::SignedInt;
7969 this->RegParmMax = 0; // Disallow regparm
7972 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
7973 Builder.defineMacro("__le32__");
7974 Builder.defineMacro("__pnacl__");
7976 void getTargetDefines(const LangOptions &Opts,
7977 MacroBuilder &Builder) const override {
7978 getArchDefines(Opts, Builder);
7980 bool hasFeature(StringRef Feature) const override {
7981 return Feature == "pnacl";
7983 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7984 BuiltinVaListKind getBuiltinVaListKind() const override {
7985 return TargetInfo::PNaClABIBuiltinVaList;
7987 ArrayRef<const char *> getGCCRegNames() const override;
7988 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
7989 bool validateAsmConstraint(const char *&Name,
7990 TargetInfo::ConstraintInfo &Info) const override {
7994 const char *getClobbers() const override {
7999 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const {
8003 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const {
8007 // We attempt to use PNaCl (le32) frontend and Mips32EL backend.
8008 class NaClMips32TargetInfo : public MipsTargetInfo {
8010 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8011 : MipsTargetInfo(Triple, Opts) {}
8013 BuiltinVaListKind getBuiltinVaListKind() const override {
8014 return TargetInfo::PNaClABIBuiltinVaList;
8018 class Le64TargetInfo : public TargetInfo {
8019 static const Builtin::Info BuiltinInfo[];
8022 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8023 : TargetInfo(Triple) {
8024 NoAsmVariants = true;
8025 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
8026 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8027 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128");
8030 void getTargetDefines(const LangOptions &Opts,
8031 MacroBuilder &Builder) const override {
8032 DefineStd(Builder, "unix", Opts);
8033 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
8034 Builder.defineMacro("__ELF__");
8036 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8037 return llvm::makeArrayRef(BuiltinInfo,
8038 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin);
8040 BuiltinVaListKind getBuiltinVaListKind() const override {
8041 return TargetInfo::PNaClABIBuiltinVaList;
8043 const char *getClobbers() const override { return ""; }
8044 ArrayRef<const char *> getGCCRegNames() const override {
8047 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8050 bool validateAsmConstraint(const char *&Name,
8051 TargetInfo::ConstraintInfo &Info) const override {
8055 bool hasProtectedVisibility() const override { return false; }
8058 class WebAssemblyTargetInfo : public TargetInfo {
8059 static const Builtin::Info BuiltinInfo[];
8067 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &)
8068 : TargetInfo(T), SIMDLevel(NoSIMD) {
8069 NoAsmVariants = true;
8070 SuitableAlign = 128;
8071 LargeArrayMinWidth = 128;
8072 LargeArrayAlign = 128;
8073 SimdDefaultAlign = 128;
8074 SigAtomicType = SignedLong;
8075 LongDoubleWidth = LongDoubleAlign = 128;
8076 LongDoubleFormat = &llvm::APFloat::IEEEquad();
8077 SizeType = UnsignedInt;
8078 PtrDiffType = SignedInt;
8079 IntPtrType = SignedInt;
8083 void getTargetDefines(const LangOptions &Opts,
8084 MacroBuilder &Builder) const override {
8085 defineCPUMacros(Builder, "wasm", /*Tuning=*/false);
8086 if (SIMDLevel >= SIMD128)
8087 Builder.defineMacro("__wasm_simd128__");
8092 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
8094 const std::vector<std::string> &FeaturesVec) const override {
8095 if (CPU == "bleeding-edge")
8096 Features["simd128"] = true;
8097 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
8099 bool hasFeature(StringRef Feature) const final {
8100 return llvm::StringSwitch<bool>(Feature)
8101 .Case("simd128", SIMDLevel >= SIMD128)
8104 bool handleTargetFeatures(std::vector<std::string> &Features,
8105 DiagnosticsEngine &Diags) final {
8106 for (const auto &Feature : Features) {
8107 if (Feature == "+simd128") {
8108 SIMDLevel = std::max(SIMDLevel, SIMD128);
8111 if (Feature == "-simd128") {
8112 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1));
8116 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature
8117 << "-target-feature";
8122 bool setCPU(const std::string &Name) final {
8123 return llvm::StringSwitch<bool>(Name)
8125 .Case("bleeding-edge", true)
8126 .Case("generic", true)
8129 ArrayRef<Builtin::Info> getTargetBuiltins() const final {
8130 return llvm::makeArrayRef(BuiltinInfo,
8131 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin);
8133 BuiltinVaListKind getBuiltinVaListKind() const final {
8134 return VoidPtrBuiltinVaList;
8136 ArrayRef<const char *> getGCCRegNames() const final {
8139 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final {
8143 validateAsmConstraint(const char *&Name,
8144 TargetInfo::ConstraintInfo &Info) const final {
8147 const char *getClobbers() const final { return ""; }
8148 bool isCLZForZeroUndef() const final { return false; }
8149 bool hasInt128Type() const final { return true; }
8150 IntType getIntTypeByWidth(unsigned BitWidth,
8151 bool IsSigned) const final {
8152 // WebAssembly prefers long long for explicitly 64-bit integers.
8153 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
8154 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
8156 IntType getLeastIntTypeByWidth(unsigned BitWidth,
8157 bool IsSigned) const final {
8158 // WebAssembly uses long long for int_least64_t and int_fast64_t.
8159 return BitWidth == 64
8160 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
8161 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
8165 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = {
8166 #define BUILTIN(ID, TYPE, ATTRS) \
8167 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8168 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8169 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8170 #include "clang/Basic/BuiltinsWebAssembly.def"
8173 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo {
8175 explicit WebAssembly32TargetInfo(const llvm::Triple &T,
8176 const TargetOptions &Opts)
8177 : WebAssemblyTargetInfo(T, Opts) {
8178 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
8179 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128");
8183 void getTargetDefines(const LangOptions &Opts,
8184 MacroBuilder &Builder) const override {
8185 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
8186 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false);
8190 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo {
8192 explicit WebAssembly64TargetInfo(const llvm::Triple &T,
8193 const TargetOptions &Opts)
8194 : WebAssemblyTargetInfo(T, Opts) {
8195 LongAlign = LongWidth = 64;
8196 PointerAlign = PointerWidth = 64;
8197 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8198 SizeType = UnsignedLong;
8199 PtrDiffType = SignedLong;
8200 IntPtrType = SignedLong;
8201 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
8205 void getTargetDefines(const LangOptions &Opts,
8206 MacroBuilder &Builder) const override {
8207 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
8208 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false);
8212 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
8213 #define BUILTIN(ID, TYPE, ATTRS) \
8214 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8215 #include "clang/Basic/BuiltinsLe64.def"
8218 static const unsigned SPIRAddrSpaceMap[] = {
8221 2, // opencl_constant
8222 4, // opencl_generic
8227 class SPIRTargetInfo : public TargetInfo {
8229 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8230 : TargetInfo(Triple) {
8231 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
8232 "SPIR target must use unknown OS");
8233 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
8234 "SPIR target must use unknown environment type");
8235 TLSSupported = false;
8236 LongWidth = LongAlign = 64;
8237 AddrSpaceMap = &SPIRAddrSpaceMap;
8238 UseAddrSpaceMapMangling = true;
8239 // Define available target features
8240 // These must be defined in sorted order!
8241 NoAsmVariants = true;
8243 void getTargetDefines(const LangOptions &Opts,
8244 MacroBuilder &Builder) const override {
8245 DefineStd(Builder, "SPIR", Opts);
8247 bool hasFeature(StringRef Feature) const override {
8248 return Feature == "spir";
8251 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
8252 const char *getClobbers() const override { return ""; }
8253 ArrayRef<const char *> getGCCRegNames() const override { return None; }
8254 bool validateAsmConstraint(const char *&Name,
8255 TargetInfo::ConstraintInfo &info) const override {
8258 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8261 BuiltinVaListKind getBuiltinVaListKind() const override {
8262 return TargetInfo::VoidPtrBuiltinVaList;
8265 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
8266 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK
8270 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
8271 return CC_SpirFunction;
8274 void setSupportedOpenCLOpts() override {
8275 // Assume all OpenCL extensions and optional core features are supported
8276 // for SPIR since it is a generic target.
8277 getSupportedOpenCLOpts().supportAll();
8281 class SPIR32TargetInfo : public SPIRTargetInfo {
8283 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8284 : SPIRTargetInfo(Triple, Opts) {
8285 PointerWidth = PointerAlign = 32;
8286 SizeType = TargetInfo::UnsignedInt;
8287 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
8288 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
8289 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
8291 void getTargetDefines(const LangOptions &Opts,
8292 MacroBuilder &Builder) const override {
8293 DefineStd(Builder, "SPIR32", Opts);
8297 class SPIR64TargetInfo : public SPIRTargetInfo {
8299 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8300 : SPIRTargetInfo(Triple, Opts) {
8301 PointerWidth = PointerAlign = 64;
8302 SizeType = TargetInfo::UnsignedLong;
8303 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
8304 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
8305 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
8307 void getTargetDefines(const LangOptions &Opts,
8308 MacroBuilder &Builder) const override {
8309 DefineStd(Builder, "SPIR64", Opts);
8313 class XCoreTargetInfo : public TargetInfo {
8314 static const Builtin::Info BuiltinInfo[];
8316 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8317 : TargetInfo(Triple) {
8318 NoAsmVariants = true;
8321 DoubleAlign = LongDoubleAlign = 32;
8322 SizeType = UnsignedInt;
8323 PtrDiffType = SignedInt;
8324 IntPtrType = SignedInt;
8325 WCharType = UnsignedChar;
8326 WIntType = UnsignedInt;
8327 UseZeroLengthBitfieldAlignment = true;
8328 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
8329 "-f64:32-a:0:32-n32");
8331 void getTargetDefines(const LangOptions &Opts,
8332 MacroBuilder &Builder) const override {
8333 Builder.defineMacro("__XS1B__");
8335 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8336 return llvm::makeArrayRef(BuiltinInfo,
8337 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin);
8339 BuiltinVaListKind getBuiltinVaListKind() const override {
8340 return TargetInfo::VoidPtrBuiltinVaList;
8342 const char *getClobbers() const override {
8345 ArrayRef<const char *> getGCCRegNames() const override {
8346 static const char * const GCCRegNames[] = {
8347 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8348 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
8350 return llvm::makeArrayRef(GCCRegNames);
8352 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8355 bool validateAsmConstraint(const char *&Name,
8356 TargetInfo::ConstraintInfo &Info) const override {
8359 int getEHDataRegisterNumber(unsigned RegNo) const override {
8360 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
8361 return (RegNo < 2)? RegNo : -1;
8363 bool allowsLargerPreferedTypeAlignment() const override {
8368 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
8369 #define BUILTIN(ID, TYPE, ATTRS) \
8370 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8371 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8372 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8373 #include "clang/Basic/BuiltinsXCore.def"
8376 // x86_32 Android target
8377 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
8379 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8380 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) {
8382 LongDoubleWidth = 64;
8383 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
8387 // x86_64 Android target
8388 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
8390 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8391 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) {
8392 LongDoubleFormat = &llvm::APFloat::IEEEquad();
8395 bool useFloat128ManglingForLongDouble() const override {
8400 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes
8401 class RenderScript32TargetInfo : public ARMleTargetInfo {
8403 RenderScript32TargetInfo(const llvm::Triple &Triple,
8404 const TargetOptions &Opts)
8405 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(),
8407 Triple.getEnvironmentName()),
8409 IsRenderScriptTarget = true;
8410 LongWidth = LongAlign = 64;
8412 void getTargetDefines(const LangOptions &Opts,
8413 MacroBuilder &Builder) const override {
8414 Builder.defineMacro("__RENDERSCRIPT__");
8415 ARMleTargetInfo::getTargetDefines(Opts, Builder);
8419 // 64-bit RenderScript is aarch64
8420 class RenderScript64TargetInfo : public AArch64leTargetInfo {
8422 RenderScript64TargetInfo(const llvm::Triple &Triple,
8423 const TargetOptions &Opts)
8424 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(),
8426 Triple.getEnvironmentName()),
8428 IsRenderScriptTarget = true;
8431 void getTargetDefines(const LangOptions &Opts,
8432 MacroBuilder &Builder) const override {
8433 Builder.defineMacro("__RENDERSCRIPT__");
8434 AArch64leTargetInfo::getTargetDefines(Opts, Builder);
8440 class AVRTargetInfo : public TargetInfo {
8442 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8443 : TargetInfo(Triple) {
8444 TLSSupported = false;
8454 DefaultAlignForAttributeAligned = 8;
8461 DoubleFormat = &llvm::APFloat::IEEEsingle();
8462 LongDoubleWidth = 32;
8463 LongDoubleAlign = 8;
8464 LongDoubleFormat = &llvm::APFloat::IEEEsingle();
8465 SizeType = UnsignedInt;
8466 PtrDiffType = SignedInt;
8467 IntPtrType = SignedInt;
8468 Char16Type = UnsignedInt;
8469 WCharType = SignedInt;
8470 WIntType = SignedInt;
8471 Char32Type = UnsignedLong;
8472 SigAtomicType = SignedChar;
8473 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64"
8474 "-f32:32:32-f64:64:64-n8");
8477 void getTargetDefines(const LangOptions &Opts,
8478 MacroBuilder &Builder) const override {
8479 Builder.defineMacro("__AVR__");
8482 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8486 BuiltinVaListKind getBuiltinVaListKind() const override {
8487 return TargetInfo::VoidPtrBuiltinVaList;
8490 const char *getClobbers() const override {
8494 ArrayRef<const char *> getGCCRegNames() const override {
8495 static const char * const GCCRegNames[] = {
8496 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8497 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8498 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8499 "r24", "r25", "X", "Y", "Z", "SP"
8501 return llvm::makeArrayRef(GCCRegNames);
8504 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8508 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
8509 static const TargetInfo::AddlRegName AddlRegNames[] = {
8510 { { "r26", "r27"}, 26 },
8511 { { "r28", "r29"}, 27 },
8512 { { "r30", "r31"}, 28 },
8513 { { "SPL", "SPH"}, 29 },
8515 return llvm::makeArrayRef(AddlRegNames);
8518 bool validateAsmConstraint(const char *&Name,
8519 TargetInfo::ConstraintInfo &Info) const override {
8523 IntType getIntTypeByWidth(unsigned BitWidth,
8524 bool IsSigned) const final {
8525 // AVR prefers int for 16-bit integers.
8526 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt)
8527 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
8530 IntType getLeastIntTypeByWidth(unsigned BitWidth,
8531 bool IsSigned) const final {
8532 // AVR uses int for int_least16_t and int_fast16_t.
8533 return BitWidth == 16
8534 ? (IsSigned ? SignedInt : UnsignedInt)
8535 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
8539 } // end anonymous namespace
8541 //===----------------------------------------------------------------------===//
8543 //===----------------------------------------------------------------------===//
8545 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
8546 const TargetOptions &Opts) {
8547 llvm::Triple::OSType os = Triple.getOS();
8549 switch (Triple.getArch()) {
8553 case llvm::Triple::xcore:
8554 return new XCoreTargetInfo(Triple, Opts);
8556 case llvm::Triple::hexagon:
8557 return new HexagonTargetInfo(Triple, Opts);
8559 case llvm::Triple::lanai:
8560 return new LanaiTargetInfo(Triple, Opts);
8562 case llvm::Triple::aarch64:
8563 if (Triple.isOSDarwin())
8564 return new DarwinAArch64TargetInfo(Triple, Opts);
8567 case llvm::Triple::CloudABI:
8568 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts);
8569 case llvm::Triple::FreeBSD:
8570 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
8571 case llvm::Triple::Fuchsia:
8572 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts);
8573 case llvm::Triple::Linux:
8574 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts);
8575 case llvm::Triple::NetBSD:
8576 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
8578 return new AArch64leTargetInfo(Triple, Opts);
8581 case llvm::Triple::aarch64_be:
8583 case llvm::Triple::FreeBSD:
8584 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
8585 case llvm::Triple::Fuchsia:
8586 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts);
8587 case llvm::Triple::Linux:
8588 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts);
8589 case llvm::Triple::NetBSD:
8590 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
8592 return new AArch64beTargetInfo(Triple, Opts);
8595 case llvm::Triple::arm:
8596 case llvm::Triple::thumb:
8597 if (Triple.isOSBinFormatMachO())
8598 return new DarwinARMTargetInfo(Triple, Opts);
8601 case llvm::Triple::CloudABI:
8602 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts);
8603 case llvm::Triple::Linux:
8604 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts);
8605 case llvm::Triple::FreeBSD:
8606 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
8607 case llvm::Triple::Fuchsia:
8608 return new FuchsiaTargetInfo<ARMleTargetInfo>(Triple, Opts);
8609 case llvm::Triple::NetBSD:
8610 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
8611 case llvm::Triple::OpenBSD:
8612 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
8613 case llvm::Triple::Bitrig:
8614 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts);
8615 case llvm::Triple::RTEMS:
8616 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts);
8617 case llvm::Triple::NaCl:
8618 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts);
8619 case llvm::Triple::Win32:
8620 switch (Triple.getEnvironment()) {
8621 case llvm::Triple::Cygnus:
8622 return new CygwinARMTargetInfo(Triple, Opts);
8623 case llvm::Triple::GNU:
8624 return new MinGWARMTargetInfo(Triple, Opts);
8625 case llvm::Triple::Itanium:
8626 return new ItaniumWindowsARMleTargetInfo(Triple, Opts);
8627 case llvm::Triple::MSVC:
8628 default: // Assume MSVC for unknown environments
8629 return new MicrosoftARMleTargetInfo(Triple, Opts);
8632 return new ARMleTargetInfo(Triple, Opts);
8635 case llvm::Triple::armeb:
8636 case llvm::Triple::thumbeb:
8637 if (Triple.isOSDarwin())
8638 return new DarwinARMTargetInfo(Triple, Opts);
8641 case llvm::Triple::Linux:
8642 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8643 case llvm::Triple::FreeBSD:
8644 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8645 case llvm::Triple::Fuchsia:
8646 return new FuchsiaTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8647 case llvm::Triple::NetBSD:
8648 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8649 case llvm::Triple::OpenBSD:
8650 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8651 case llvm::Triple::Bitrig:
8652 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8653 case llvm::Triple::RTEMS:
8654 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8655 case llvm::Triple::NaCl:
8656 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8658 return new ARMbeTargetInfo(Triple, Opts);
8661 case llvm::Triple::avr:
8662 return new AVRTargetInfo(Triple, Opts);
8663 case llvm::Triple::bpfeb:
8664 case llvm::Triple::bpfel:
8665 return new BPFTargetInfo(Triple, Opts);
8667 case llvm::Triple::msp430:
8668 return new MSP430TargetInfo(Triple, Opts);
8670 case llvm::Triple::mips:
8672 case llvm::Triple::Linux:
8673 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
8674 case llvm::Triple::RTEMS:
8675 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
8676 case llvm::Triple::FreeBSD:
8677 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8678 case llvm::Triple::NetBSD:
8679 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8681 return new MipsTargetInfo(Triple, Opts);
8684 case llvm::Triple::mipsel:
8686 case llvm::Triple::Linux:
8687 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
8688 case llvm::Triple::RTEMS:
8689 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
8690 case llvm::Triple::FreeBSD:
8691 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8692 case llvm::Triple::NetBSD:
8693 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8694 case llvm::Triple::NaCl:
8695 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts);
8697 return new MipsTargetInfo(Triple, Opts);
8700 case llvm::Triple::mips64:
8702 case llvm::Triple::Linux:
8703 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
8704 case llvm::Triple::RTEMS:
8705 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
8706 case llvm::Triple::FreeBSD:
8707 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8708 case llvm::Triple::NetBSD:
8709 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8710 case llvm::Triple::OpenBSD:
8711 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8713 return new MipsTargetInfo(Triple, Opts);
8716 case llvm::Triple::mips64el:
8718 case llvm::Triple::Linux:
8719 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
8720 case llvm::Triple::RTEMS:
8721 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
8722 case llvm::Triple::FreeBSD:
8723 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8724 case llvm::Triple::NetBSD:
8725 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8726 case llvm::Triple::OpenBSD:
8727 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8729 return new MipsTargetInfo(Triple, Opts);
8732 case llvm::Triple::le32:
8734 case llvm::Triple::NaCl:
8735 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts);
8740 case llvm::Triple::le64:
8741 return new Le64TargetInfo(Triple, Opts);
8743 case llvm::Triple::ppc:
8744 if (Triple.isOSDarwin())
8745 return new DarwinPPC32TargetInfo(Triple, Opts);
8747 case llvm::Triple::Linux:
8748 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts);
8749 case llvm::Triple::FreeBSD:
8750 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
8751 case llvm::Triple::NetBSD:
8752 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
8753 case llvm::Triple::OpenBSD:
8754 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
8755 case llvm::Triple::RTEMS:
8756 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts);
8758 return new PPC32TargetInfo(Triple, Opts);
8761 case llvm::Triple::ppc64:
8762 if (Triple.isOSDarwin())
8763 return new DarwinPPC64TargetInfo(Triple, Opts);
8765 case llvm::Triple::Linux:
8766 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
8767 case llvm::Triple::Lv2:
8768 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts);
8769 case llvm::Triple::FreeBSD:
8770 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
8771 case llvm::Triple::NetBSD:
8772 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
8774 return new PPC64TargetInfo(Triple, Opts);
8777 case llvm::Triple::ppc64le:
8779 case llvm::Triple::Linux:
8780 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
8781 case llvm::Triple::NetBSD:
8782 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
8784 return new PPC64TargetInfo(Triple, Opts);
8787 case llvm::Triple::nvptx:
8788 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32);
8789 case llvm::Triple::nvptx64:
8790 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64);
8792 case llvm::Triple::amdgcn:
8793 case llvm::Triple::r600:
8794 return new AMDGPUTargetInfo(Triple, Opts);
8796 case llvm::Triple::sparc:
8798 case llvm::Triple::Linux:
8799 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8800 case llvm::Triple::Solaris:
8801 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8802 case llvm::Triple::NetBSD:
8803 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8804 case llvm::Triple::OpenBSD:
8805 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8806 case llvm::Triple::RTEMS:
8807 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8809 return new SparcV8TargetInfo(Triple, Opts);
8812 // The 'sparcel' architecture copies all the above cases except for Solaris.
8813 case llvm::Triple::sparcel:
8815 case llvm::Triple::Linux:
8816 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
8817 case llvm::Triple::NetBSD:
8818 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
8819 case llvm::Triple::OpenBSD:
8820 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
8821 case llvm::Triple::RTEMS:
8822 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
8824 return new SparcV8elTargetInfo(Triple, Opts);
8827 case llvm::Triple::sparcv9:
8829 case llvm::Triple::Linux:
8830 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8831 case llvm::Triple::Solaris:
8832 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8833 case llvm::Triple::NetBSD:
8834 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8835 case llvm::Triple::OpenBSD:
8836 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8837 case llvm::Triple::FreeBSD:
8838 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8840 return new SparcV9TargetInfo(Triple, Opts);
8843 case llvm::Triple::systemz:
8845 case llvm::Triple::Linux:
8846 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts);
8848 return new SystemZTargetInfo(Triple, Opts);
8851 case llvm::Triple::tce:
8852 return new TCETargetInfo(Triple, Opts);
8854 case llvm::Triple::tcele:
8855 return new TCELETargetInfo(Triple, Opts);
8857 case llvm::Triple::x86:
8858 if (Triple.isOSDarwin())
8859 return new DarwinI386TargetInfo(Triple, Opts);
8862 case llvm::Triple::CloudABI:
8863 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts);
8864 case llvm::Triple::Linux: {
8865 switch (Triple.getEnvironment()) {
8867 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts);
8868 case llvm::Triple::Android:
8869 return new AndroidX86_32TargetInfo(Triple, Opts);
8872 case llvm::Triple::DragonFly:
8873 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
8874 case llvm::Triple::NetBSD:
8875 return new NetBSDI386TargetInfo(Triple, Opts);
8876 case llvm::Triple::OpenBSD:
8877 return new OpenBSDI386TargetInfo(Triple, Opts);
8878 case llvm::Triple::Bitrig:
8879 return new BitrigI386TargetInfo(Triple, Opts);
8880 case llvm::Triple::FreeBSD:
8881 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
8882 case llvm::Triple::Fuchsia:
8883 return new FuchsiaTargetInfo<X86_32TargetInfo>(Triple, Opts);
8884 case llvm::Triple::KFreeBSD:
8885 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
8886 case llvm::Triple::Minix:
8887 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts);
8888 case llvm::Triple::Solaris:
8889 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts);
8890 case llvm::Triple::Win32: {
8891 switch (Triple.getEnvironment()) {
8892 case llvm::Triple::Cygnus:
8893 return new CygwinX86_32TargetInfo(Triple, Opts);
8894 case llvm::Triple::GNU:
8895 return new MinGWX86_32TargetInfo(Triple, Opts);
8896 case llvm::Triple::Itanium:
8897 case llvm::Triple::MSVC:
8898 default: // Assume MSVC for unknown environments
8899 return new MicrosoftX86_32TargetInfo(Triple, Opts);
8902 case llvm::Triple::Haiku:
8903 return new HaikuX86_32TargetInfo(Triple, Opts);
8904 case llvm::Triple::RTEMS:
8905 return new RTEMSX86_32TargetInfo(Triple, Opts);
8906 case llvm::Triple::NaCl:
8907 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts);
8908 case llvm::Triple::ELFIAMCU:
8909 return new MCUX86_32TargetInfo(Triple, Opts);
8911 return new X86_32TargetInfo(Triple, Opts);
8914 case llvm::Triple::x86_64:
8915 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
8916 return new DarwinX86_64TargetInfo(Triple, Opts);
8919 case llvm::Triple::CloudABI:
8920 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts);
8921 case llvm::Triple::Linux: {
8922 switch (Triple.getEnvironment()) {
8924 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts);
8925 case llvm::Triple::Android:
8926 return new AndroidX86_64TargetInfo(Triple, Opts);
8929 case llvm::Triple::DragonFly:
8930 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
8931 case llvm::Triple::NetBSD:
8932 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
8933 case llvm::Triple::OpenBSD:
8934 return new OpenBSDX86_64TargetInfo(Triple, Opts);
8935 case llvm::Triple::Bitrig:
8936 return new BitrigX86_64TargetInfo(Triple, Opts);
8937 case llvm::Triple::FreeBSD:
8938 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
8939 case llvm::Triple::Fuchsia:
8940 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts);
8941 case llvm::Triple::KFreeBSD:
8942 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
8943 case llvm::Triple::Solaris:
8944 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts);
8945 case llvm::Triple::Win32: {
8946 switch (Triple.getEnvironment()) {
8947 case llvm::Triple::Cygnus:
8948 return new CygwinX86_64TargetInfo(Triple, Opts);
8949 case llvm::Triple::GNU:
8950 return new MinGWX86_64TargetInfo(Triple, Opts);
8951 case llvm::Triple::MSVC:
8952 default: // Assume MSVC for unknown environments
8953 return new MicrosoftX86_64TargetInfo(Triple, Opts);
8956 case llvm::Triple::Haiku:
8957 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts);
8958 case llvm::Triple::NaCl:
8959 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts);
8960 case llvm::Triple::PS4:
8961 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts);
8963 return new X86_64TargetInfo(Triple, Opts);
8966 case llvm::Triple::spir: {
8967 if (Triple.getOS() != llvm::Triple::UnknownOS ||
8968 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
8970 return new SPIR32TargetInfo(Triple, Opts);
8972 case llvm::Triple::spir64: {
8973 if (Triple.getOS() != llvm::Triple::UnknownOS ||
8974 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
8976 return new SPIR64TargetInfo(Triple, Opts);
8978 case llvm::Triple::wasm32:
8979 if (!(Triple == llvm::Triple("wasm32-unknown-unknown")))
8981 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts);
8982 case llvm::Triple::wasm64:
8983 if (!(Triple == llvm::Triple("wasm64-unknown-unknown")))
8985 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts);
8987 case llvm::Triple::renderscript32:
8988 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts);
8989 case llvm::Triple::renderscript64:
8990 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts);
8994 /// CreateTargetInfo - Return the target info object for the specified target
8997 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
8998 const std::shared_ptr<TargetOptions> &Opts) {
8999 llvm::Triple Triple(Opts->Triple);
9001 // Construct the target
9002 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts));
9004 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
9007 Target->TargetOpts = Opts;
9009 // Set the target CPU if specified.
9010 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
9011 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
9015 // Set the target ABI if specified.
9016 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
9017 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
9021 // Set the fp math unit.
9022 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
9023 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
9027 // Compute the default target features, we need the target to handle this
9028 // because features may have dependencies on one another.
9029 llvm::StringMap<bool> Features;
9030 if (!Target->initFeatureMap(Features, Diags, Opts->CPU,
9031 Opts->FeaturesAsWritten))
9034 // Add the features to the compile options.
9035 Opts->Features.clear();
9036 for (const auto &F : Features)
9037 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str());
9039 if (!Target->handleTargetFeatures(Opts->Features, Diags))
9042 Target->setSupportedOpenCLOpts();
9043 Target->setOpenCLExtensionOpts();
9045 if (!Target->validateTarget(Diags))
9048 return Target.release();