1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/OwningPtr.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
32 using namespace clang;
34 //===----------------------------------------------------------------------===//
35 // Common code shared among targets.
36 //===----------------------------------------------------------------------===//
38 /// DefineStd - Define a macro name and standard variants. For example if
39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42 const LangOptions &Opts) {
43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46 // in the user's namespace.
48 Builder.defineMacro(MacroName);
51 Builder.defineMacro("__" + MacroName);
54 Builder.defineMacro("__" + MacroName + "__");
57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
59 Builder.defineMacro("__" + CPUName);
60 Builder.defineMacro("__" + CPUName + "__");
62 Builder.defineMacro("__tune_" + CPUName + "__");
65 //===----------------------------------------------------------------------===//
66 // Defines specific to certain operating systems.
67 //===----------------------------------------------------------------------===//
70 template<typename TgtInfo>
71 class OSTargetInfo : public TgtInfo {
73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74 MacroBuilder &Builder) const=0;
76 OSTargetInfo(const std::string& triple) : TgtInfo(triple) {}
77 virtual void getTargetDefines(const LangOptions &Opts,
78 MacroBuilder &Builder) const {
79 TgtInfo::getTargetDefines(Opts, Builder);
80 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
84 } // end anonymous namespace
87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88 const llvm::Triple &Triple,
89 StringRef &PlatformName,
90 VersionTuple &PlatformMinVersion) {
91 Builder.defineMacro("__APPLE_CC__", "5621");
92 Builder.defineMacro("__APPLE__");
93 Builder.defineMacro("__MACH__");
94 Builder.defineMacro("OBJC_NEW_PROPERTIES");
95 // AddressSanitizer doesn't play well with source fortification, which is on
96 // by default on Darwin.
97 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
99 if (!Opts.ObjCAutoRefCount) {
100 // __weak is always defined, for use in blocks and with objc pointers.
101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
103 // Darwin defines __strong even in C mode (just to nothing).
104 if (Opts.getGC() != LangOptions::NonGC)
105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
107 Builder.defineMacro("__strong", "");
109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110 // allow this in C, since one might have block pointers in structs that
111 // are used in pure C code and in Objective-C ARC.
112 Builder.defineMacro("__unsafe_unretained", "");
116 Builder.defineMacro("__STATIC__");
118 Builder.defineMacro("__DYNAMIC__");
120 if (Opts.POSIXThreads)
121 Builder.defineMacro("_REENTRANT");
123 // Get the platform type and version number from the triple.
124 unsigned Maj, Min, Rev;
125 if (Triple.isMacOSX()) {
126 Triple.getMacOSXVersion(Maj, Min, Rev);
127 PlatformName = "macosx";
129 Triple.getOSVersion(Maj, Min, Rev);
130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
133 // If -target arch-pc-win32-macho option specified, we're
134 // generating code for Win32 ABI. No need to emit
135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136 if (PlatformName == "win32") {
137 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
141 // Set the appropriate OS version define.
142 if (Triple.getOS() == llvm::Triple::IOS) {
143 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
146 Str[1] = '0' + (Min / 10);
147 Str[2] = '0' + (Min % 10);
148 Str[3] = '0' + (Rev / 10);
149 Str[4] = '0' + (Rev % 10);
151 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str);
153 // Note that the Driver allows versions which aren't representable in the
154 // define (because we only get a single digit for the minor and micro
155 // revision numbers). So, we limit them to the maximum representable
157 assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
158 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
160 Str[0] = '0' + (Maj / 10);
161 Str[1] = '0' + (Maj % 10);
162 Str[2] = '0' + std::min(Min, 9U);
163 Str[3] = '0' + std::min(Rev, 9U);
165 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
168 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
172 template<typename Target>
173 class DarwinTargetInfo : public OSTargetInfo<Target> {
175 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
176 MacroBuilder &Builder) const {
177 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
178 this->PlatformMinVersion);
182 DarwinTargetInfo(const std::string& triple) :
183 OSTargetInfo<Target>(triple) {
184 llvm::Triple T = llvm::Triple(triple);
185 this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7);
186 this->MCountName = "\01mcount";
189 virtual std::string isValidSectionSpecifier(StringRef SR) const {
190 // Let MCSectionMachO validate this.
191 StringRef Segment, Section;
192 unsigned TAA, StubSize;
194 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
195 TAA, HasTAA, StubSize);
198 virtual const char *getStaticInitSectionSpecifier() const {
199 // FIXME: We should return 0 when building kexts.
200 return "__TEXT,__StaticInit,regular,pure_instructions";
203 /// Darwin does not support protected visibility. Darwin's "default"
204 /// is very similar to ELF's "protected"; Darwin requires a "weak"
205 /// attribute on declarations that can be dynamically replaced.
206 virtual bool hasProtectedVisibility() const {
212 // DragonFlyBSD Target
213 template<typename Target>
214 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
216 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
217 MacroBuilder &Builder) const {
218 // DragonFly defines; list based off of gcc output
219 Builder.defineMacro("__DragonFly__");
220 Builder.defineMacro("__DragonFly_cc_version", "100001");
221 Builder.defineMacro("__ELF__");
222 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
223 Builder.defineMacro("__tune_i386__");
224 DefineStd(Builder, "unix", Opts);
227 DragonFlyBSDTargetInfo(const std::string &triple)
228 : OSTargetInfo<Target>(triple) {
229 this->UserLabelPrefix = "";
231 llvm::Triple Triple(triple);
232 switch (Triple.getArch()) {
234 case llvm::Triple::x86:
235 case llvm::Triple::x86_64:
236 this->MCountName = ".mcount";
243 template<typename Target>
244 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
246 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
247 MacroBuilder &Builder) const {
248 // FreeBSD defines; list based off of gcc output
250 unsigned Release = Triple.getOSMajorVersion();
254 Builder.defineMacro("__FreeBSD__", Twine(Release));
255 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
256 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
257 DefineStd(Builder, "unix", Opts);
258 Builder.defineMacro("__ELF__");
261 FreeBSDTargetInfo(const std::string &triple)
262 : OSTargetInfo<Target>(triple) {
263 this->UserLabelPrefix = "";
265 llvm::Triple Triple(triple);
266 switch (Triple.getArch()) {
268 case llvm::Triple::x86:
269 case llvm::Triple::x86_64:
270 this->MCountName = ".mcount";
272 case llvm::Triple::mips:
273 case llvm::Triple::mipsel:
274 case llvm::Triple::ppc:
275 case llvm::Triple::ppc64:
276 this->MCountName = "_mcount";
278 case llvm::Triple::arm:
279 this->MCountName = "__mcount";
287 template<typename Target>
288 class MinixTargetInfo : public OSTargetInfo<Target> {
290 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
291 MacroBuilder &Builder) const {
294 Builder.defineMacro("__minix", "3");
295 Builder.defineMacro("_EM_WSIZE", "4");
296 Builder.defineMacro("_EM_PSIZE", "4");
297 Builder.defineMacro("_EM_SSIZE", "2");
298 Builder.defineMacro("_EM_LSIZE", "4");
299 Builder.defineMacro("_EM_FSIZE", "4");
300 Builder.defineMacro("_EM_DSIZE", "8");
301 Builder.defineMacro("__ELF__");
302 DefineStd(Builder, "unix", Opts);
305 MinixTargetInfo(const std::string &triple)
306 : OSTargetInfo<Target>(triple) {
307 this->UserLabelPrefix = "";
312 template<typename Target>
313 class LinuxTargetInfo : public OSTargetInfo<Target> {
315 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
316 MacroBuilder &Builder) const {
317 // Linux defines; list based off of gcc output
318 DefineStd(Builder, "unix", Opts);
319 DefineStd(Builder, "linux", Opts);
320 Builder.defineMacro("__gnu_linux__");
321 Builder.defineMacro("__ELF__");
322 if (Triple.getEnvironment() == llvm::Triple::Android)
323 Builder.defineMacro("__ANDROID__", "1");
324 if (Opts.POSIXThreads)
325 Builder.defineMacro("_REENTRANT");
327 Builder.defineMacro("_GNU_SOURCE");
330 LinuxTargetInfo(const std::string& triple)
331 : OSTargetInfo<Target>(triple) {
332 this->UserLabelPrefix = "";
333 this->WIntType = TargetInfo::UnsignedInt;
336 virtual const char *getStaticInitSectionSpecifier() const {
337 return ".text.startup";
342 template<typename Target>
343 class NetBSDTargetInfo : public OSTargetInfo<Target> {
345 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
346 MacroBuilder &Builder) const {
347 // NetBSD defines; list based off of gcc output
348 Builder.defineMacro("__NetBSD__");
349 Builder.defineMacro("__unix__");
350 Builder.defineMacro("__ELF__");
351 if (Opts.POSIXThreads)
352 Builder.defineMacro("_POSIX_THREADS");
355 NetBSDTargetInfo(const std::string &triple)
356 : OSTargetInfo<Target>(triple) {
357 this->UserLabelPrefix = "";
362 template<typename Target>
363 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
365 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
366 MacroBuilder &Builder) const {
367 // OpenBSD defines; list based off of gcc output
369 Builder.defineMacro("__OpenBSD__");
370 DefineStd(Builder, "unix", Opts);
371 Builder.defineMacro("__ELF__");
372 if (Opts.POSIXThreads)
373 Builder.defineMacro("_REENTRANT");
376 OpenBSDTargetInfo(const std::string &triple)
377 : OSTargetInfo<Target>(triple) {
378 this->UserLabelPrefix = "";
379 this->TLSSupported = false;
381 llvm::Triple Triple(triple);
382 switch (Triple.getArch()) {
384 case llvm::Triple::x86:
385 case llvm::Triple::x86_64:
386 case llvm::Triple::arm:
387 case llvm::Triple::sparc:
388 this->MCountName = "__mcount";
390 case llvm::Triple::mips64:
391 case llvm::Triple::mips64el:
392 case llvm::Triple::ppc:
393 case llvm::Triple::sparcv9:
394 this->MCountName = "_mcount";
401 template<typename Target>
402 class BitrigTargetInfo : public OSTargetInfo<Target> {
404 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
405 MacroBuilder &Builder) const {
406 // Bitrig defines; list based off of gcc output
408 Builder.defineMacro("__Bitrig__");
409 DefineStd(Builder, "unix", Opts);
410 Builder.defineMacro("__ELF__");
411 if (Opts.POSIXThreads)
412 Builder.defineMacro("_REENTRANT");
415 BitrigTargetInfo(const std::string &triple)
416 : OSTargetInfo<Target>(triple) {
417 this->UserLabelPrefix = "";
418 this->TLSSupported = false;
419 this->MCountName = "__mcount";
424 template<typename Target>
425 class PSPTargetInfo : public OSTargetInfo<Target> {
427 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
428 MacroBuilder &Builder) const {
429 // PSP defines; list based on the output of the pspdev gcc toolchain.
430 Builder.defineMacro("PSP");
431 Builder.defineMacro("_PSP");
432 Builder.defineMacro("__psp__");
433 Builder.defineMacro("__ELF__");
436 PSPTargetInfo(const std::string& triple)
437 : OSTargetInfo<Target>(triple) {
438 this->UserLabelPrefix = "";
443 template<typename Target>
444 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
446 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
447 MacroBuilder &Builder) const {
449 Builder.defineMacro("__PPC__");
450 Builder.defineMacro("__PPU__");
451 Builder.defineMacro("__CELLOS_LV2__");
452 Builder.defineMacro("__ELF__");
453 Builder.defineMacro("__LP32__");
454 Builder.defineMacro("_ARCH_PPC64");
455 Builder.defineMacro("__powerpc64__");
458 PS3PPUTargetInfo(const std::string& triple)
459 : OSTargetInfo<Target>(triple) {
460 this->UserLabelPrefix = "";
461 this->LongWidth = this->LongAlign = 32;
462 this->PointerWidth = this->PointerAlign = 32;
463 this->IntMaxType = TargetInfo::SignedLongLong;
464 this->UIntMaxType = TargetInfo::UnsignedLongLong;
465 this->Int64Type = TargetInfo::SignedLongLong;
466 this->SizeType = TargetInfo::UnsignedInt;
467 this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
468 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
472 // FIXME: Need a real SPU target.
474 template<typename Target>
475 class PS3SPUTargetInfo : public OSTargetInfo<Target> {
477 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
478 MacroBuilder &Builder) const {
480 Builder.defineMacro("__SPU__");
481 Builder.defineMacro("__ELF__");
484 PS3SPUTargetInfo(const std::string& triple)
485 : OSTargetInfo<Target>(triple) {
486 this->UserLabelPrefix = "";
491 template<typename Target>
492 class AuroraUXTargetInfo : public OSTargetInfo<Target> {
494 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495 MacroBuilder &Builder) const {
496 DefineStd(Builder, "sun", Opts);
497 DefineStd(Builder, "unix", Opts);
498 Builder.defineMacro("__ELF__");
499 Builder.defineMacro("__svr4__");
500 Builder.defineMacro("__SVR4");
503 AuroraUXTargetInfo(const std::string& triple)
504 : OSTargetInfo<Target>(triple) {
505 this->UserLabelPrefix = "";
506 this->WCharType = this->SignedLong;
507 // FIXME: WIntType should be SignedLong
512 template<typename Target>
513 class SolarisTargetInfo : public OSTargetInfo<Target> {
515 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
516 MacroBuilder &Builder) const {
517 DefineStd(Builder, "sun", Opts);
518 DefineStd(Builder, "unix", Opts);
519 Builder.defineMacro("__ELF__");
520 Builder.defineMacro("__svr4__");
521 Builder.defineMacro("__SVR4");
522 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
523 // newer, but to 500 for everything else. feature_test.h has a check to
524 // ensure that you are not using C99 with an old version of X/Open or C89
525 // with a new version.
526 if (Opts.C99 || Opts.C11)
527 Builder.defineMacro("_XOPEN_SOURCE", "600");
529 Builder.defineMacro("_XOPEN_SOURCE", "500");
531 Builder.defineMacro("__C99FEATURES__");
532 Builder.defineMacro("_LARGEFILE_SOURCE");
533 Builder.defineMacro("_LARGEFILE64_SOURCE");
534 Builder.defineMacro("__EXTENSIONS__");
535 Builder.defineMacro("_REENTRANT");
538 SolarisTargetInfo(const std::string& triple)
539 : OSTargetInfo<Target>(triple) {
540 this->UserLabelPrefix = "";
541 this->WCharType = this->SignedInt;
542 // FIXME: WIntType should be SignedLong
547 template<typename Target>
548 class WindowsTargetInfo : public OSTargetInfo<Target> {
550 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
551 MacroBuilder &Builder) const {
552 Builder.defineMacro("_WIN32");
554 void getVisualStudioDefines(const LangOptions &Opts,
555 MacroBuilder &Builder) const {
556 if (Opts.CPlusPlus) {
558 Builder.defineMacro("_CPPRTTI");
561 Builder.defineMacro("_CPPUNWIND");
564 if (!Opts.CharIsSigned)
565 Builder.defineMacro("_CHAR_UNSIGNED");
567 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
568 // but it works for now.
569 if (Opts.POSIXThreads)
570 Builder.defineMacro("_MT");
572 if (Opts.MSCVersion != 0)
573 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
575 if (Opts.MicrosoftExt) {
576 Builder.defineMacro("_MSC_EXTENSIONS");
578 if (Opts.CPlusPlus11) {
579 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
580 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
581 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
585 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
589 WindowsTargetInfo(const std::string &triple)
590 : OSTargetInfo<Target>(triple) {}
593 template <typename Target>
594 class NaClTargetInfo : public OSTargetInfo<Target> {
596 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
597 MacroBuilder &Builder) const {
598 if (Opts.POSIXThreads)
599 Builder.defineMacro("_REENTRANT");
601 Builder.defineMacro("_GNU_SOURCE");
603 DefineStd(Builder, "unix", Opts);
604 Builder.defineMacro("__ELF__");
605 Builder.defineMacro("__native_client__");
608 NaClTargetInfo(const std::string &triple)
609 : OSTargetInfo<Target>(triple) {
610 this->UserLabelPrefix = "";
611 this->LongAlign = 32;
612 this->LongWidth = 32;
613 this->PointerAlign = 32;
614 this->PointerWidth = 32;
615 this->IntMaxType = TargetInfo::SignedLongLong;
616 this->UIntMaxType = TargetInfo::UnsignedLongLong;
617 this->Int64Type = TargetInfo::SignedLongLong;
618 this->DoubleAlign = 64;
619 this->LongDoubleWidth = 64;
620 this->LongDoubleAlign = 64;
621 this->SizeType = TargetInfo::UnsignedInt;
622 this->PtrDiffType = TargetInfo::SignedInt;
623 this->IntPtrType = TargetInfo::SignedInt;
624 this->RegParmMax = 2;
625 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
626 this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
627 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
629 virtual typename Target::CallingConvCheckResult checkCallingConvention(
630 CallingConv CC) const {
631 return CC == CC_PnaclCall ? Target::CCCR_OK :
632 Target::checkCallingConvention(CC);
635 } // end anonymous namespace.
637 //===----------------------------------------------------------------------===//
638 // Specific target implementations.
639 //===----------------------------------------------------------------------===//
642 // PPC abstract base class
643 class PPCTargetInfo : public TargetInfo {
644 static const Builtin::Info BuiltinInfo[];
645 static const char * const GCCRegNames[];
646 static const TargetInfo::GCCRegAlias GCCRegAliases[];
649 PPCTargetInfo(const std::string& triple) : TargetInfo(triple) {
650 LongDoubleWidth = LongDoubleAlign = 128;
651 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
654 /// \brief Flags for architecture specific defines.
657 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
658 ArchDefinePpcgr = 1 << 1,
659 ArchDefinePpcsq = 1 << 2,
660 ArchDefine440 = 1 << 3,
661 ArchDefine603 = 1 << 4,
662 ArchDefine604 = 1 << 5,
663 ArchDefinePwr4 = 1 << 6,
664 ArchDefinePwr5 = 1 << 7,
665 ArchDefinePwr5x = 1 << 8,
666 ArchDefinePwr6 = 1 << 9,
667 ArchDefinePwr6x = 1 << 10,
668 ArchDefinePwr7 = 1 << 11,
669 ArchDefineA2 = 1 << 12,
670 ArchDefineA2q = 1 << 13
673 // Note: GCC recognizes the following additional cpus:
674 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
675 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
677 virtual bool setCPU(const std::string &Name) {
678 bool CPUKnown = llvm::StringSwitch<bool>(Name)
679 .Case("generic", true)
701 .Case("e500mc", true)
703 .Case("power3", true)
705 .Case("power4", true)
707 .Case("power5", true)
709 .Case("power5x", true)
711 .Case("power6", true)
713 .Case("power6x", true)
715 .Case("power7", true)
717 .Case("powerpc", true)
719 .Case("powerpc64", true)
729 virtual void getTargetBuiltins(const Builtin::Info *&Records,
730 unsigned &NumRecords) const {
731 Records = BuiltinInfo;
732 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
735 virtual bool isCLZForZeroUndef() const { return false; }
737 virtual void getTargetDefines(const LangOptions &Opts,
738 MacroBuilder &Builder) const;
740 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
742 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
746 virtual bool hasFeature(StringRef Feature) const;
748 virtual void getGCCRegNames(const char * const *&Names,
749 unsigned &NumNames) const;
750 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
751 unsigned &NumAliases) const;
752 virtual bool validateAsmConstraint(const char *&Name,
753 TargetInfo::ConstraintInfo &Info) const {
755 default: return false;
758 case 'b': // Base register
759 case 'f': // Floating point register
760 Info.setAllowsRegister();
762 // FIXME: The following are added to allow parsing.
763 // I just took a guess at what the actions should be.
764 // Also, is more specific checking needed? I.e. specific registers?
765 case 'd': // Floating point register (containing 64-bit value)
766 case 'v': // Altivec vector register
767 Info.setAllowsRegister();
771 case 'd':// VSX vector register to hold vector double data
772 case 'f':// VSX vector register to hold vector float data
773 case 's':// VSX vector register to hold scalar float data
774 case 'a':// Any VSX register
779 Info.setAllowsRegister();
780 Name++; // Skip over 'w'.
782 case 'h': // `MQ', `CTR', or `LINK' register
783 case 'q': // `MQ' register
784 case 'c': // `CTR' register
785 case 'l': // `LINK' register
786 case 'x': // `CR' register (condition register) number 0
787 case 'y': // `CR' register (condition register)
788 case 'z': // `XER[CA]' carry bit (part of the XER register)
789 Info.setAllowsRegister();
791 case 'I': // Signed 16-bit constant
792 case 'J': // Unsigned 16-bit constant shifted left 16 bits
793 // (use `L' instead for SImode constants)
794 case 'K': // Unsigned 16-bit constant
795 case 'L': // Signed 16-bit constant shifted left 16 bits
796 case 'M': // Constant larger than 31
797 case 'N': // Exact power of 2
798 case 'P': // Constant whose negation is a signed 16-bit constant
799 case 'G': // Floating point constant that can be loaded into a
800 // register with one instruction per word
801 case 'H': // Integer/Floating point constant that can be loaded
802 // into a register using three instructions
804 case 'm': // Memory operand. Note that on PowerPC targets, m can
805 // include addresses that update the base register. It
806 // is therefore only safe to use `m' in an asm statement
807 // if that asm statement accesses the operand exactly once.
808 // The asm statement must also use `%U<opno>' as a
809 // placeholder for the "update" flag in the corresponding
810 // load or store instruction. For example:
811 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
813 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
814 // is not. Use es rather than m if you don't want the base
815 // register to be updated.
819 // es: A "stable" memory operand; that is, one which does not
820 // include any automodification of the base register. Unlike
821 // `m', this constraint can be used in asm statements that
822 // might access the operand several times, or that might not
824 Info.setAllowsMemory();
825 Name++; // Skip over 'e'.
827 case 'Q': // Memory operand that is an offset from a register (it is
828 // usually better to use `m' or `es' in asm statements)
829 case 'Z': // Memory operand that is an indexed or indirect from a
830 // register (it is usually better to use `m' or `es' in
832 Info.setAllowsMemory();
833 Info.setAllowsRegister();
835 case 'R': // AIX TOC entry
836 case 'a': // Address operand that is an indexed or indirect from a
837 // register (`p' is preferable for asm statements)
838 case 'S': // Constant suitable as a 64-bit mask operand
839 case 'T': // Constant suitable as a 32-bit mask operand
840 case 'U': // System V Release 4 small data area reference
841 case 't': // AND masks that can be performed by two rldic{l, r}
843 case 'W': // Vector constant that does not require memory
844 case 'j': // Vector constant that is all zeros.
850 virtual const char *getClobbers() const {
853 int getEHDataRegisterNumber(unsigned RegNo) const {
854 if (RegNo == 0) return 3;
855 if (RegNo == 1) return 4;
860 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
861 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
862 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
864 #include "clang/Basic/BuiltinsPPC.def"
868 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
869 /// #defines that are not tied to a specific subtarget.
870 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
871 MacroBuilder &Builder) const {
872 // Target identification.
873 Builder.defineMacro("__ppc__");
874 Builder.defineMacro("_ARCH_PPC");
875 Builder.defineMacro("__powerpc__");
876 Builder.defineMacro("__POWERPC__");
877 if (PointerWidth == 64) {
878 Builder.defineMacro("_ARCH_PPC64");
879 Builder.defineMacro("__powerpc64__");
880 Builder.defineMacro("__ppc64__");
882 Builder.defineMacro("__ppc__");
885 // Target properties.
886 if (getTriple().getOS() != llvm::Triple::NetBSD &&
887 getTriple().getOS() != llvm::Triple::OpenBSD)
888 Builder.defineMacro("_BIG_ENDIAN");
889 Builder.defineMacro("__BIG_ENDIAN__");
891 // Subtarget options.
892 Builder.defineMacro("__NATURAL_ALIGNMENT__");
893 Builder.defineMacro("__REGISTER_PREFIX__", "");
895 // FIXME: Should be controlled by command line option.
896 Builder.defineMacro("__LONG_DOUBLE_128__");
899 Builder.defineMacro("__VEC__", "10206");
900 Builder.defineMacro("__ALTIVEC__");
903 // CPU identification.
904 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
905 .Case("440", ArchDefineName)
906 .Case("450", ArchDefineName | ArchDefine440)
907 .Case("601", ArchDefineName)
908 .Case("602", ArchDefineName | ArchDefinePpcgr)
909 .Case("603", ArchDefineName | ArchDefinePpcgr)
910 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
911 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
912 .Case("604", ArchDefineName | ArchDefinePpcgr)
913 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
914 .Case("620", ArchDefineName | ArchDefinePpcgr)
915 .Case("630", ArchDefineName | ArchDefinePpcgr)
916 .Case("7400", ArchDefineName | ArchDefinePpcgr)
917 .Case("7450", ArchDefineName | ArchDefinePpcgr)
918 .Case("750", ArchDefineName | ArchDefinePpcgr)
919 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
921 .Case("a2", ArchDefineA2)
922 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
923 .Case("pwr3", ArchDefinePpcgr)
924 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
925 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
927 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
928 | ArchDefinePpcgr | ArchDefinePpcsq)
929 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
930 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
931 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
932 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
934 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
935 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
936 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
937 .Case("power3", ArchDefinePpcgr)
938 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
939 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
941 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
942 | ArchDefinePpcgr | ArchDefinePpcsq)
943 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
944 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
945 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
946 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
948 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
949 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
950 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
951 .Default(ArchDefineNone);
953 if (defs & ArchDefineName)
954 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
955 if (defs & ArchDefinePpcgr)
956 Builder.defineMacro("_ARCH_PPCGR");
957 if (defs & ArchDefinePpcsq)
958 Builder.defineMacro("_ARCH_PPCSQ");
959 if (defs & ArchDefine440)
960 Builder.defineMacro("_ARCH_440");
961 if (defs & ArchDefine603)
962 Builder.defineMacro("_ARCH_603");
963 if (defs & ArchDefine604)
964 Builder.defineMacro("_ARCH_604");
965 if (defs & ArchDefinePwr4)
966 Builder.defineMacro("_ARCH_PWR4");
967 if (defs & ArchDefinePwr5)
968 Builder.defineMacro("_ARCH_PWR5");
969 if (defs & ArchDefinePwr5x)
970 Builder.defineMacro("_ARCH_PWR5X");
971 if (defs & ArchDefinePwr6)
972 Builder.defineMacro("_ARCH_PWR6");
973 if (defs & ArchDefinePwr6x)
974 Builder.defineMacro("_ARCH_PWR6X");
975 if (defs & ArchDefinePwr7)
976 Builder.defineMacro("_ARCH_PWR7");
977 if (defs & ArchDefineA2)
978 Builder.defineMacro("_ARCH_A2");
979 if (defs & ArchDefineA2q) {
980 Builder.defineMacro("_ARCH_A2Q");
981 Builder.defineMacro("_ARCH_QP");
984 if (getTriple().getVendor() == llvm::Triple::BGQ) {
985 Builder.defineMacro("__bg__");
986 Builder.defineMacro("__THW_BLUEGENE__");
987 Builder.defineMacro("__bgq__");
988 Builder.defineMacro("__TOS_BGQ__");
991 // FIXME: The following are not yet generated here by Clang, but are
995 // __RECIP_PRECISION__
1006 // __CMODEL_MEDIUM__
1013 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1014 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1023 .Case("ppc64", true)
1026 Features["qpx"] = (CPU == "a2q");
1029 bool PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1031 bool Enabled) const {
1032 if (Name == "altivec" || Name == "fprnd" || Name == "mfocrf" ||
1033 Name == "popcntd" || Name == "qpx") {
1034 Features[Name] = Enabled;
1041 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1042 return Feature == "powerpc";
1046 const char * const PPCTargetInfo::GCCRegNames[] = {
1047 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1048 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1049 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1050 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1051 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1052 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1053 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1054 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1055 "mq", "lr", "ctr", "ap",
1056 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1058 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1059 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1060 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1061 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1063 "spe_acc", "spefscr",
1067 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1068 unsigned &NumNames) const {
1069 Names = GCCRegNames;
1070 NumNames = llvm::array_lengthof(GCCRegNames);
1073 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1074 // While some of these aliases do map to different registers
1075 // they still share the same register name.
1086 { { "10" }, "r10" },
1087 { { "11" }, "r11" },
1088 { { "12" }, "r12" },
1089 { { "13" }, "r13" },
1090 { { "14" }, "r14" },
1091 { { "15" }, "r15" },
1092 { { "16" }, "r16" },
1093 { { "17" }, "r17" },
1094 { { "18" }, "r18" },
1095 { { "19" }, "r19" },
1096 { { "20" }, "r20" },
1097 { { "21" }, "r21" },
1098 { { "22" }, "r22" },
1099 { { "23" }, "r23" },
1100 { { "24" }, "r24" },
1101 { { "25" }, "r25" },
1102 { { "26" }, "r26" },
1103 { { "27" }, "r27" },
1104 { { "28" }, "r28" },
1105 { { "29" }, "r29" },
1106 { { "30" }, "r30" },
1107 { { "31" }, "r31" },
1108 { { "fr0" }, "f0" },
1109 { { "fr1" }, "f1" },
1110 { { "fr2" }, "f2" },
1111 { { "fr3" }, "f3" },
1112 { { "fr4" }, "f4" },
1113 { { "fr5" }, "f5" },
1114 { { "fr6" }, "f6" },
1115 { { "fr7" }, "f7" },
1116 { { "fr8" }, "f8" },
1117 { { "fr9" }, "f9" },
1118 { { "fr10" }, "f10" },
1119 { { "fr11" }, "f11" },
1120 { { "fr12" }, "f12" },
1121 { { "fr13" }, "f13" },
1122 { { "fr14" }, "f14" },
1123 { { "fr15" }, "f15" },
1124 { { "fr16" }, "f16" },
1125 { { "fr17" }, "f17" },
1126 { { "fr18" }, "f18" },
1127 { { "fr19" }, "f19" },
1128 { { "fr20" }, "f20" },
1129 { { "fr21" }, "f21" },
1130 { { "fr22" }, "f22" },
1131 { { "fr23" }, "f23" },
1132 { { "fr24" }, "f24" },
1133 { { "fr25" }, "f25" },
1134 { { "fr26" }, "f26" },
1135 { { "fr27" }, "f27" },
1136 { { "fr28" }, "f28" },
1137 { { "fr29" }, "f29" },
1138 { { "fr30" }, "f30" },
1139 { { "fr31" }, "f31" },
1140 { { "cc" }, "cr0" },
1143 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1144 unsigned &NumAliases) const {
1145 Aliases = GCCRegAliases;
1146 NumAliases = llvm::array_lengthof(GCCRegAliases);
1148 } // end anonymous namespace.
1151 class PPC32TargetInfo : public PPCTargetInfo {
1153 PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) {
1154 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1155 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
1157 switch (getTriple().getOS()) {
1158 case llvm::Triple::Linux:
1159 case llvm::Triple::FreeBSD:
1160 case llvm::Triple::NetBSD:
1161 SizeType = UnsignedInt;
1162 PtrDiffType = SignedInt;
1163 IntPtrType = SignedInt;
1169 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1170 LongDoubleWidth = LongDoubleAlign = 64;
1171 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1174 // PPC32 supports atomics up to 4 bytes.
1175 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1178 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1179 // This is the ELF definition, and is overridden by the Darwin sub-target
1180 return TargetInfo::PowerABIBuiltinVaList;
1183 } // end anonymous namespace.
1186 class PPC64TargetInfo : public PPCTargetInfo {
1188 PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) {
1189 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1190 IntMaxType = SignedLong;
1191 UIntMaxType = UnsignedLong;
1192 Int64Type = SignedLong;
1194 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1195 LongDoubleWidth = LongDoubleAlign = 64;
1196 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1197 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1198 "i64:64:64-f32:32:32-f64:64:64-f128:64:64-"
1199 "v128:128:128-n32:64";
1201 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1202 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
1203 "v128:128:128-n32:64";
1205 // PPC64 supports atomics up to 8 bytes.
1206 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1208 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1209 return TargetInfo::CharPtrBuiltinVaList;
1212 } // end anonymous namespace.
1216 class DarwinPPC32TargetInfo :
1217 public DarwinTargetInfo<PPC32TargetInfo> {
1219 DarwinPPC32TargetInfo(const std::string& triple)
1220 : DarwinTargetInfo<PPC32TargetInfo>(triple) {
1221 HasAlignMac68kSupport = true;
1222 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1224 SuitableAlign = 128;
1225 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1226 "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1228 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1229 return TargetInfo::CharPtrBuiltinVaList;
1233 class DarwinPPC64TargetInfo :
1234 public DarwinTargetInfo<PPC64TargetInfo> {
1236 DarwinPPC64TargetInfo(const std::string& triple)
1237 : DarwinTargetInfo<PPC64TargetInfo>(triple) {
1238 HasAlignMac68kSupport = true;
1239 SuitableAlign = 128;
1240 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1241 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1244 } // end anonymous namespace.
1247 static const unsigned NVPTXAddrSpaceMap[] = {
1250 4, // opencl_constant
1255 class NVPTXTargetInfo : public TargetInfo {
1256 static const char * const GCCRegNames[];
1257 static const Builtin::Info BuiltinInfo[];
1258 std::vector<StringRef> AvailableFeatures;
1260 NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) {
1262 TLSSupported = false;
1263 LongWidth = LongAlign = 64;
1264 AddrSpaceMap = &NVPTXAddrSpaceMap;
1265 // Define available target features
1266 // These must be defined in sorted order!
1267 NoAsmVariants = true;
1269 virtual void getTargetDefines(const LangOptions &Opts,
1270 MacroBuilder &Builder) const {
1271 Builder.defineMacro("__PTX__");
1272 Builder.defineMacro("__NVPTX__");
1274 virtual void getTargetBuiltins(const Builtin::Info *&Records,
1275 unsigned &NumRecords) const {
1276 Records = BuiltinInfo;
1277 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1279 virtual bool hasFeature(StringRef Feature) const {
1280 return Feature == "ptx" || Feature == "nvptx";
1283 virtual void getGCCRegNames(const char * const *&Names,
1284 unsigned &NumNames) const;
1285 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1286 unsigned &NumAliases) const {
1291 virtual bool validateAsmConstraint(const char *&Name,
1292 TargetInfo::ConstraintInfo &info) const {
1296 virtual const char *getClobbers() const {
1297 // FIXME: Is this really right?
1300 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1302 return TargetInfo::CharPtrBuiltinVaList;
1304 virtual bool setCPU(const std::string &Name) {
1305 bool Valid = llvm::StringSwitch<bool>(Name)
1306 .Case("sm_20", true)
1307 .Case("sm_21", true)
1308 .Case("sm_30", true)
1309 .Case("sm_35", true)
1314 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1316 bool Enabled) const;
1319 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1320 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1321 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1323 #include "clang/Basic/BuiltinsNVPTX.def"
1326 const char * const NVPTXTargetInfo::GCCRegNames[] = {
1330 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1331 unsigned &NumNames) const {
1332 Names = GCCRegNames;
1333 NumNames = llvm::array_lengthof(GCCRegNames);
1336 bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1338 bool Enabled) const {
1339 if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(),
1341 Features[Name] = Enabled;
1348 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1350 NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1351 PointerWidth = PointerAlign = 32;
1352 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1354 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1355 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1360 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1362 NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1363 PointerWidth = PointerAlign = 64;
1364 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1366 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1367 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1375 static const unsigned R600AddrSpaceMap[] = {
1378 2, // opencl_constant
1384 static const char *DescriptionStringR600 =
1387 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
1388 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1389 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1392 static const char *DescriptionStringR600DoubleOps =
1395 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1396 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1397 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1400 static const char *DescriptionStringSI =
1403 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1404 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1405 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1408 class R600TargetInfo : public TargetInfo {
1409 /// \brief The GPU profiles supported by the R600 target.
1417 GK_EVERGREEN_DOUBLE_OPS,
1418 GK_NORTHERN_ISLANDS,
1424 R600TargetInfo(const std::string& triple)
1425 : TargetInfo(triple),
1427 DescriptionString = DescriptionStringR600;
1428 AddrSpaceMap = &R600AddrSpaceMap;
1431 virtual const char * getClobbers() const {
1435 virtual void getGCCRegNames(const char * const *&Names,
1436 unsigned &numNames) const {
1441 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1442 unsigned &NumAliases) const {
1447 virtual bool validateAsmConstraint(const char *&Name,
1448 TargetInfo::ConstraintInfo &info) const {
1452 virtual void getTargetBuiltins(const Builtin::Info *&Records,
1453 unsigned &NumRecords) const {
1459 virtual void getTargetDefines(const LangOptions &Opts,
1460 MacroBuilder &Builder) const {
1461 Builder.defineMacro("__R600__");
1464 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1465 return TargetInfo::CharPtrBuiltinVaList;
1468 virtual bool setCPU(const std::string &Name) {
1469 GPU = llvm::StringSwitch<GPUKind>(Name)
1470 .Case("r600" , GK_R600)
1471 .Case("rv610", GK_R600)
1472 .Case("rv620", GK_R600)
1473 .Case("rv630", GK_R600)
1474 .Case("rv635", GK_R600)
1475 .Case("rs780", GK_R600)
1476 .Case("rs880", GK_R600)
1477 .Case("rv670", GK_R600_DOUBLE_OPS)
1478 .Case("rv710", GK_R700)
1479 .Case("rv730", GK_R700)
1480 .Case("rv740", GK_R700_DOUBLE_OPS)
1481 .Case("rv770", GK_R700_DOUBLE_OPS)
1482 .Case("palm", GK_EVERGREEN)
1483 .Case("cedar", GK_EVERGREEN)
1484 .Case("sumo", GK_EVERGREEN)
1485 .Case("sumo2", GK_EVERGREEN)
1486 .Case("redwood", GK_EVERGREEN)
1487 .Case("juniper", GK_EVERGREEN)
1488 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
1489 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
1490 .Case("barts", GK_NORTHERN_ISLANDS)
1491 .Case("turks", GK_NORTHERN_ISLANDS)
1492 .Case("caicos", GK_NORTHERN_ISLANDS)
1493 .Case("cayman", GK_CAYMAN)
1494 .Case("aruba", GK_CAYMAN)
1495 .Case("tahiti", GK_SOUTHERN_ISLANDS)
1496 .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1497 .Case("verde", GK_SOUTHERN_ISLANDS)
1498 .Case("oland", GK_SOUTHERN_ISLANDS)
1501 if (GPU == GK_NONE) {
1505 // Set the correct data layout
1511 case GK_NORTHERN_ISLANDS:
1512 DescriptionString = DescriptionStringR600;
1514 case GK_R600_DOUBLE_OPS:
1515 case GK_R700_DOUBLE_OPS:
1516 case GK_EVERGREEN_DOUBLE_OPS:
1518 DescriptionString = DescriptionStringR600DoubleOps;
1520 case GK_SOUTHERN_ISLANDS:
1521 DescriptionString = DescriptionStringSI;
1529 } // end anonymous namespace
1532 // MBlaze abstract base class
1533 class MBlazeTargetInfo : public TargetInfo {
1534 static const char * const GCCRegNames[];
1535 static const TargetInfo::GCCRegAlias GCCRegAliases[];
1538 MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) {
1539 DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16";
1542 virtual void getTargetBuiltins(const Builtin::Info *&Records,
1543 unsigned &NumRecords) const {
1544 // FIXME: Implement.
1549 virtual void getTargetDefines(const LangOptions &Opts,
1550 MacroBuilder &Builder) const;
1552 virtual bool hasFeature(StringRef Feature) const {
1553 return Feature == "mblaze";
1556 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1557 return TargetInfo::CharPtrBuiltinVaList;
1559 virtual const char *getTargetPrefix() const {
1562 virtual void getGCCRegNames(const char * const *&Names,
1563 unsigned &NumNames) const;
1564 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1565 unsigned &NumAliases) const;
1566 virtual bool validateAsmConstraint(const char *&Name,
1567 TargetInfo::ConstraintInfo &Info) const {
1569 default: return false;
1572 case 'b': // Base register
1573 case 'f': // Floating point register
1574 Info.setAllowsRegister();
1578 virtual const char *getClobbers() const {
1583 /// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific
1584 /// #defines that are not tied to a specific subtarget.
1585 void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts,
1586 MacroBuilder &Builder) const {
1587 // Target identification.
1588 Builder.defineMacro("__microblaze__");
1589 Builder.defineMacro("_ARCH_MICROBLAZE");
1590 Builder.defineMacro("__MICROBLAZE__");
1592 // Target properties.
1593 Builder.defineMacro("_BIG_ENDIAN");
1594 Builder.defineMacro("__BIG_ENDIAN__");
1596 // Subtarget options.
1597 Builder.defineMacro("__REGISTER_PREFIX__", "");
1601 const char * const MBlazeTargetInfo::GCCRegNames[] = {
1602 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1603 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1604 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1605 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1606 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
1607 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1608 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1609 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
1610 "hi", "lo", "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4",
1611 "$fcc5","$fcc6","$fcc7","$ap", "$rap", "$frp"
1614 void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names,
1615 unsigned &NumNames) const {
1616 Names = GCCRegNames;
1617 NumNames = llvm::array_lengthof(GCCRegNames);
1620 const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = {
1655 void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1656 unsigned &NumAliases) const {
1657 Aliases = GCCRegAliases;
1658 NumAliases = llvm::array_lengthof(GCCRegAliases);
1660 } // end anonymous namespace.
1663 // Namespace for x86 abstract base class
1664 const Builtin::Info BuiltinInfo[] = {
1665 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1666 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1668 #include "clang/Basic/BuiltinsX86.def"
1671 static const char* const GCCRegNames[] = {
1672 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1673 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1674 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1675 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1676 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1677 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1678 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1679 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1680 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1683 const TargetInfo::AddlRegName AddlRegNames[] = {
1684 { { "al", "ah", "eax", "rax" }, 0 },
1685 { { "bl", "bh", "ebx", "rbx" }, 3 },
1686 { { "cl", "ch", "ecx", "rcx" }, 2 },
1687 { { "dl", "dh", "edx", "rdx" }, 1 },
1688 { { "esi", "rsi" }, 4 },
1689 { { "edi", "rdi" }, 5 },
1690 { { "esp", "rsp" }, 7 },
1691 { { "ebp", "rbp" }, 6 },
1694 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1695 // most of the implementation can be shared.
1696 class X86TargetInfo : public TargetInfo {
1698 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
1701 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1720 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1722 /// Each enumeration represents a particular CPU supported by Clang. These
1723 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1728 /// i386-generation processors.
1734 /// i486-generation processors.
1743 /// i586-generation processors, P5 microarchitecture based.
1751 /// i686-generation processors, P6 / Pentium M microarchitecture based.
1761 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1762 /// Clang however has some logic to suport this.
1763 // FIXME: Warn, deprecate, and potentially remove this.
1768 /// Netburst microarchitecture based processors.
1777 /// Core microarchitecture based processors.
1781 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1782 /// codename which GCC no longer accepts as an option to -march, but Clang
1783 /// has some logic for recognizing it.
1784 // FIXME: Warn, deprecate, and potentially remove this.
1795 /// Nehalem microarchitecture based processors.
1804 /// K6 architecture processors.
1812 /// K7 architecture processors.
1815 CK_AthlonThunderbird,
1822 /// K8 architecture processors.
1835 /// Bobcat architecture processors.
1841 /// Bulldozer architecture processors.
1847 /// This specification is deprecated and will be removed in the future.
1848 /// Users should prefer \see CK_K8.
1849 // FIXME: Warn on this when the CPU is set to it.
1854 /// Geode processors.
1861 X86TargetInfo(const std::string& triple)
1862 : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1863 HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false),
1864 HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasRTM(false),
1865 HasPRFCHW(false), HasRDSEED(false), HasSSE4a(false), HasFMA4(false),
1866 HasFMA(false), HasXOP(false), HasF16C(false), CPU(CK_Generic) {
1868 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1870 virtual unsigned getFloatEvalMethod() const {
1871 // X87 evaluates with 80 bits "long double" precision.
1872 return SSELevel == NoSSE ? 2 : 0;
1874 virtual void getTargetBuiltins(const Builtin::Info *&Records,
1875 unsigned &NumRecords) const {
1876 Records = BuiltinInfo;
1877 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1879 virtual void getGCCRegNames(const char * const *&Names,
1880 unsigned &NumNames) const {
1881 Names = GCCRegNames;
1882 NumNames = llvm::array_lengthof(GCCRegNames);
1884 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1885 unsigned &NumAliases) const {
1889 virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1890 unsigned &NumNames) const {
1891 Names = AddlRegNames;
1892 NumNames = llvm::array_lengthof(AddlRegNames);
1894 virtual bool validateAsmConstraint(const char *&Name,
1895 TargetInfo::ConstraintInfo &info) const;
1896 virtual std::string convertConstraint(const char *&Constraint) const;
1897 virtual const char *getClobbers() const {
1898 return "~{dirflag},~{fpsr},~{flags}";
1900 virtual void getTargetDefines(const LangOptions &Opts,
1901 MacroBuilder &Builder) const;
1902 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1904 bool Enabled) const;
1905 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1906 virtual bool hasFeature(StringRef Feature) const;
1907 virtual void HandleTargetFeatures(std::vector<std::string> &Features);
1908 virtual const char* getABI() const {
1909 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1911 else if (getTriple().getArch() == llvm::Triple::x86 &&
1912 MMX3DNowLevel == NoMMX3DNow)
1916 virtual bool setCPU(const std::string &Name) {
1917 CPU = llvm::StringSwitch<CPUKind>(Name)
1918 .Case("i386", CK_i386)
1919 .Case("i486", CK_i486)
1920 .Case("winchip-c6", CK_WinChipC6)
1921 .Case("winchip2", CK_WinChip2)
1923 .Case("i586", CK_i586)
1924 .Case("pentium", CK_Pentium)
1925 .Case("pentium-mmx", CK_PentiumMMX)
1926 .Case("i686", CK_i686)
1927 .Case("pentiumpro", CK_PentiumPro)
1928 .Case("pentium2", CK_Pentium2)
1929 .Case("pentium3", CK_Pentium3)
1930 .Case("pentium3m", CK_Pentium3M)
1931 .Case("pentium-m", CK_PentiumM)
1932 .Case("c3-2", CK_C3_2)
1933 .Case("yonah", CK_Yonah)
1934 .Case("pentium4", CK_Pentium4)
1935 .Case("pentium4m", CK_Pentium4M)
1936 .Case("prescott", CK_Prescott)
1937 .Case("nocona", CK_Nocona)
1938 .Case("core2", CK_Core2)
1939 .Case("penryn", CK_Penryn)
1940 .Case("atom", CK_Atom)
1941 .Case("corei7", CK_Corei7)
1942 .Case("corei7-avx", CK_Corei7AVX)
1943 .Case("core-avx-i", CK_CoreAVXi)
1944 .Case("core-avx2", CK_CoreAVX2)
1946 .Case("k6-2", CK_K6_2)
1947 .Case("k6-3", CK_K6_3)
1948 .Case("athlon", CK_Athlon)
1949 .Case("athlon-tbird", CK_AthlonThunderbird)
1950 .Case("athlon-4", CK_Athlon4)
1951 .Case("athlon-xp", CK_AthlonXP)
1952 .Case("athlon-mp", CK_AthlonMP)
1953 .Case("athlon64", CK_Athlon64)
1954 .Case("athlon64-sse3", CK_Athlon64SSE3)
1955 .Case("athlon-fx", CK_AthlonFX)
1957 .Case("k8-sse3", CK_K8SSE3)
1958 .Case("opteron", CK_Opteron)
1959 .Case("opteron-sse3", CK_OpteronSSE3)
1960 .Case("amdfam10", CK_AMDFAM10)
1961 .Case("btver1", CK_BTVER1)
1962 .Case("bdver1", CK_BDVER1)
1963 .Case("bdver2", CK_BDVER2)
1964 .Case("x86-64", CK_x86_64)
1965 .Case("geode", CK_Geode)
1966 .Default(CK_Generic);
1968 // Perform any per-CPU checks necessary to determine if this CPU is
1970 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1971 // invalid without explaining *why*.
1974 // No processor selected!
2000 case CK_AthlonThunderbird:
2005 // Only accept certain architectures when compiling in 32-bit mode.
2006 if (getTriple().getArch() != llvm::Triple::x86)
2019 case CK_Athlon64SSE3:
2024 case CK_OpteronSSE3:
2032 llvm_unreachable("Unhandled CPU kind");
2035 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
2036 // We accept all non-ARM calling conventions
2037 return (CC == CC_X86ThisCall ||
2038 CC == CC_X86FastCall ||
2039 CC == CC_X86StdCall ||
2041 CC == CC_X86Pascal ||
2042 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2045 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
2046 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2050 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2051 // FIXME: This should not be here.
2052 Features["3dnow"] = false;
2053 Features["3dnowa"] = false;
2054 Features["mmx"] = false;
2055 Features["sse"] = false;
2056 Features["sse2"] = false;
2057 Features["sse3"] = false;
2058 Features["ssse3"] = false;
2059 Features["sse41"] = false;
2060 Features["sse42"] = false;
2061 Features["sse4a"] = false;
2062 Features["aes"] = false;
2063 Features["pclmul"] = false;
2064 Features["avx"] = false;
2065 Features["avx2"] = false;
2066 Features["lzcnt"] = false;
2067 Features["rdrand"] = false;
2068 Features["bmi"] = false;
2069 Features["bmi2"] = false;
2070 Features["popcnt"] = false;
2071 Features["rtm"] = false;
2072 Features["prfchw"] = false;
2073 Features["rdseed"] = false;
2074 Features["fma4"] = false;
2075 Features["fma"] = false;
2076 Features["xop"] = false;
2077 Features["f16c"] = false;
2079 // FIXME: This *really* should not be here.
2081 // X86_64 always has SSE2.
2082 if (getTriple().getArch() == llvm::Triple::x86_64)
2083 setFeatureEnabled(Features, "sse2", true);
2096 setFeatureEnabled(Features, "mmx", true);
2100 setFeatureEnabled(Features, "sse", true);
2106 setFeatureEnabled(Features, "sse2", true);
2111 setFeatureEnabled(Features, "sse3", true);
2114 setFeatureEnabled(Features, "ssse3", true);
2117 setFeatureEnabled(Features, "sse4.1", true);
2120 setFeatureEnabled(Features, "ssse3", true);
2123 setFeatureEnabled(Features, "sse4", true);
2126 setFeatureEnabled(Features, "avx", true);
2127 setFeatureEnabled(Features, "aes", true);
2128 setFeatureEnabled(Features, "pclmul", true);
2131 setFeatureEnabled(Features, "avx", true);
2132 setFeatureEnabled(Features, "aes", true);
2133 setFeatureEnabled(Features, "pclmul", true);
2134 setFeatureEnabled(Features, "rdrnd", true);
2135 setFeatureEnabled(Features, "f16c", true);
2138 setFeatureEnabled(Features, "avx2", true);
2139 setFeatureEnabled(Features, "aes", true);
2140 setFeatureEnabled(Features, "pclmul", true);
2141 setFeatureEnabled(Features, "lzcnt", true);
2142 setFeatureEnabled(Features, "rdrnd", true);
2143 setFeatureEnabled(Features, "f16c", true);
2144 setFeatureEnabled(Features, "bmi", true);
2145 setFeatureEnabled(Features, "bmi2", true);
2146 setFeatureEnabled(Features, "rtm", true);
2147 setFeatureEnabled(Features, "fma", true);
2151 setFeatureEnabled(Features, "mmx", true);
2157 setFeatureEnabled(Features, "3dnow", true);
2160 case CK_AthlonThunderbird:
2162 setFeatureEnabled(Features, "3dnowa", true);
2167 setFeatureEnabled(Features, "sse", true);
2168 setFeatureEnabled(Features, "3dnowa", true);
2174 setFeatureEnabled(Features, "sse2", true);
2175 setFeatureEnabled(Features, "3dnowa", true);
2178 case CK_OpteronSSE3:
2179 case CK_Athlon64SSE3:
2180 setFeatureEnabled(Features, "sse3", true);
2181 setFeatureEnabled(Features, "3dnowa", true);
2184 setFeatureEnabled(Features, "sse3", true);
2185 setFeatureEnabled(Features, "sse4a", true);
2186 setFeatureEnabled(Features, "3dnowa", true);
2187 setFeatureEnabled(Features, "lzcnt", true);
2188 setFeatureEnabled(Features, "popcnt", true);
2191 setFeatureEnabled(Features, "ssse3", true);
2192 setFeatureEnabled(Features, "sse4a", true);
2193 setFeatureEnabled(Features, "lzcnt", true);
2194 setFeatureEnabled(Features, "popcnt", true);
2197 setFeatureEnabled(Features, "xop", true);
2198 setFeatureEnabled(Features, "lzcnt", true);
2199 setFeatureEnabled(Features, "aes", true);
2200 setFeatureEnabled(Features, "pclmul", true);
2203 setFeatureEnabled(Features, "xop", true);
2204 setFeatureEnabled(Features, "lzcnt", true);
2205 setFeatureEnabled(Features, "aes", true);
2206 setFeatureEnabled(Features, "pclmul", true);
2207 setFeatureEnabled(Features, "bmi", true);
2208 setFeatureEnabled(Features, "fma", true);
2209 setFeatureEnabled(Features, "f16c", true);
2212 setFeatureEnabled(Features, "sse", true);
2217 bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
2219 bool Enabled) const {
2220 // FIXME: This *really* should not be here. We need some way of translating
2221 // options into llvm subtarget features.
2222 if (!Features.count(Name) &&
2223 (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" &&
2227 // FIXME: this should probably use a switch with fall through.
2231 Features["mmx"] = true;
2232 else if (Name == "sse")
2233 Features["mmx"] = Features["sse"] = true;
2234 else if (Name == "sse2")
2235 Features["mmx"] = Features["sse"] = Features["sse2"] = true;
2236 else if (Name == "sse3")
2237 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2239 else if (Name == "ssse3")
2240 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2241 Features["ssse3"] = true;
2242 else if (Name == "sse4" || Name == "sse4.2")
2243 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2244 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2245 Features["popcnt"] = true;
2246 else if (Name == "sse4.1")
2247 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2248 Features["ssse3"] = Features["sse41"] = true;
2249 else if (Name == "3dnow")
2250 Features["mmx"] = Features["3dnow"] = true;
2251 else if (Name == "3dnowa")
2252 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true;
2253 else if (Name == "aes")
2254 Features["sse"] = Features["sse2"] = Features["aes"] = true;
2255 else if (Name == "pclmul")
2256 Features["sse"] = Features["sse2"] = Features["pclmul"] = true;
2257 else if (Name == "avx")
2258 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2259 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2260 Features["popcnt"] = Features["avx"] = true;
2261 else if (Name == "avx2")
2262 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2263 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2264 Features["popcnt"] = Features["avx"] = Features["avx2"] = true;
2265 else if (Name == "fma")
2266 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2267 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2268 Features["popcnt"] = Features["avx"] = Features["fma"] = true;
2269 else if (Name == "fma4")
2270 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2271 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2272 Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2273 Features["fma4"] = true;
2274 else if (Name == "xop")
2275 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2276 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2277 Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2278 Features["fma4"] = Features["xop"] = true;
2279 else if (Name == "sse4a")
2280 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2281 Features["sse4a"] = true;
2282 else if (Name == "lzcnt")
2283 Features["lzcnt"] = true;
2284 else if (Name == "rdrnd")
2285 Features["rdrand"] = true;
2286 else if (Name == "bmi")
2287 Features["bmi"] = true;
2288 else if (Name == "bmi2")
2289 Features["bmi2"] = true;
2290 else if (Name == "popcnt")
2291 Features["popcnt"] = true;
2292 else if (Name == "f16c")
2293 Features["f16c"] = true;
2294 else if (Name == "rtm")
2295 Features["rtm"] = true;
2296 else if (Name == "prfchw")
2297 Features["prfchw"] = true;
2298 else if (Name == "rdseed")
2299 Features["rdseed"] = true;
2302 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false;
2303 else if (Name == "sse")
2304 Features["sse"] = Features["sse2"] = Features["sse3"] =
2305 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2306 Features["sse4a"] = Features["avx"] = Features["avx2"] =
2307 Features["fma"] = Features["fma4"] = Features["aes"] =
2308 Features["pclmul"] = Features["xop"] = false;
2309 else if (Name == "sse2")
2310 Features["sse2"] = Features["sse3"] = Features["ssse3"] =
2311 Features["sse41"] = Features["sse42"] = Features["sse4a"] =
2312 Features["avx"] = Features["avx2"] = Features["fma"] =
2313 Features["fma4"] = Features["aes"] = Features["pclmul"] =
2314 Features["xop"] = false;
2315 else if (Name == "sse3")
2316 Features["sse3"] = Features["ssse3"] = Features["sse41"] =
2317 Features["sse42"] = Features["sse4a"] = Features["avx"] =
2318 Features["avx2"] = Features["fma"] = Features["fma4"] =
2319 Features["xop"] = false;
2320 else if (Name == "ssse3")
2321 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2322 Features["avx"] = Features["avx2"] = Features["fma"] = false;
2323 else if (Name == "sse4" || Name == "sse4.1")
2324 Features["sse41"] = Features["sse42"] = Features["avx"] =
2325 Features["avx2"] = Features["fma"] = false;
2326 else if (Name == "sse4.2")
2327 Features["sse42"] = Features["avx"] = Features["avx2"] =
2328 Features["fma"] = false;
2329 else if (Name == "3dnow")
2330 Features["3dnow"] = Features["3dnowa"] = false;
2331 else if (Name == "3dnowa")
2332 Features["3dnowa"] = false;
2333 else if (Name == "aes")
2334 Features["aes"] = false;
2335 else if (Name == "pclmul")
2336 Features["pclmul"] = false;
2337 else if (Name == "avx")
2338 Features["avx"] = Features["avx2"] = Features["fma"] =
2339 Features["fma4"] = Features["xop"] = false;
2340 else if (Name == "avx2")
2341 Features["avx2"] = false;
2342 else if (Name == "fma")
2343 Features["fma"] = false;
2344 else if (Name == "sse4a")
2345 Features["sse4a"] = Features["fma4"] = Features["xop"] = false;
2346 else if (Name == "lzcnt")
2347 Features["lzcnt"] = false;
2348 else if (Name == "rdrnd")
2349 Features["rdrand"] = false;
2350 else if (Name == "bmi")
2351 Features["bmi"] = false;
2352 else if (Name == "bmi2")
2353 Features["bmi2"] = false;
2354 else if (Name == "popcnt")
2355 Features["popcnt"] = false;
2356 else if (Name == "fma4")
2357 Features["fma4"] = Features["xop"] = false;
2358 else if (Name == "xop")
2359 Features["xop"] = false;
2360 else if (Name == "f16c")
2361 Features["f16c"] = false;
2362 else if (Name == "rtm")
2363 Features["rtm"] = false;
2364 else if (Name == "prfchw")
2365 Features["prfchw"] = false;
2366 else if (Name == "rdseed")
2367 Features["rdseed"] = false;
2373 /// HandleTargetOptions - Perform initialization based on the user
2374 /// configured set of features.
2375 void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) {
2376 // Remember the maximum enabled sselevel.
2377 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2378 // Ignore disabled features.
2379 if (Features[i][0] == '-')
2382 StringRef Feature = StringRef(Features[i]).substr(1);
2384 if (Feature == "aes") {
2389 if (Feature == "pclmul") {
2394 if (Feature == "lzcnt") {
2399 if (Feature == "rdrand") {
2404 if (Feature == "bmi") {
2409 if (Feature == "bmi2") {
2414 if (Feature == "popcnt") {
2419 if (Feature == "rtm") {
2424 if (Feature == "prfchw") {
2429 if (Feature == "rdseed") {
2434 if (Feature == "sse4a") {
2439 if (Feature == "fma4") {
2444 if (Feature == "fma") {
2449 if (Feature == "xop") {
2454 if (Feature == "f16c") {
2459 assert(Features[i][0] == '+' && "Invalid target feature!");
2460 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2463 .Case("sse42", SSE42)
2464 .Case("sse41", SSE41)
2465 .Case("ssse3", SSSE3)
2470 SSELevel = std::max(SSELevel, Level);
2472 MMX3DNowEnum ThreeDNowLevel =
2473 llvm::StringSwitch<MMX3DNowEnum>(Feature)
2474 .Case("3dnowa", AMD3DNowAthlon)
2475 .Case("3dnow", AMD3DNow)
2477 .Default(NoMMX3DNow);
2479 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2482 // Don't tell the backend if we're turning off mmx; it will end up disabling
2483 // SSE, which we don't want.
2484 std::vector<std::string>::iterator it;
2485 it = std::find(Features.begin(), Features.end(), "-mmx");
2486 if (it != Features.end())
2490 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2491 /// definitions for this particular subtarget.
2492 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2493 MacroBuilder &Builder) const {
2494 // Target identification.
2495 if (getTriple().getArch() == llvm::Triple::x86_64) {
2496 Builder.defineMacro("__amd64__");
2497 Builder.defineMacro("__amd64");
2498 Builder.defineMacro("__x86_64");
2499 Builder.defineMacro("__x86_64__");
2501 DefineStd(Builder, "i386", Opts);
2504 // Subtarget options.
2505 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2506 // truly should be based on -mtune options.
2511 // The rest are coming from the i386 define above.
2512 Builder.defineMacro("__tune_i386__");
2518 defineCPUMacros(Builder, "i486");
2521 Builder.defineMacro("__pentium_mmx__");
2522 Builder.defineMacro("__tune_pentium_mmx__");
2526 defineCPUMacros(Builder, "i586");
2527 defineCPUMacros(Builder, "pentium");
2532 Builder.defineMacro("__tune_pentium3__");
2536 Builder.defineMacro("__tune_pentium2__");
2539 Builder.defineMacro("__tune_i686__");
2540 Builder.defineMacro("__tune_pentiumpro__");
2543 Builder.defineMacro("__i686");
2544 Builder.defineMacro("__i686__");
2545 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2546 Builder.defineMacro("__pentiumpro");
2547 Builder.defineMacro("__pentiumpro__");
2551 defineCPUMacros(Builder, "pentium4");
2556 defineCPUMacros(Builder, "nocona");
2560 defineCPUMacros(Builder, "core2");
2563 defineCPUMacros(Builder, "atom");
2569 defineCPUMacros(Builder, "corei7");
2572 Builder.defineMacro("__k6_2__");
2573 Builder.defineMacro("__tune_k6_2__");
2576 if (CPU != CK_K6_2) { // In case of fallthrough
2577 // FIXME: GCC may be enabling these in cases where some other k6
2578 // architecture is specified but -m3dnow is explicitly provided. The
2579 // exact semantics need to be determined and emulated here.
2580 Builder.defineMacro("__k6_3__");
2581 Builder.defineMacro("__tune_k6_3__");
2585 defineCPUMacros(Builder, "k6");
2588 case CK_AthlonThunderbird:
2592 defineCPUMacros(Builder, "athlon");
2593 if (SSELevel != NoSSE) {
2594 Builder.defineMacro("__athlon_sse__");
2595 Builder.defineMacro("__tune_athlon_sse__");
2602 case CK_OpteronSSE3:
2604 case CK_Athlon64SSE3:
2606 defineCPUMacros(Builder, "k8");
2609 defineCPUMacros(Builder, "amdfam10");
2612 defineCPUMacros(Builder, "btver1");
2615 defineCPUMacros(Builder, "bdver1");
2618 defineCPUMacros(Builder, "bdver2");
2621 defineCPUMacros(Builder, "geode");
2625 // Target properties.
2626 Builder.defineMacro("__LITTLE_ENDIAN__");
2627 Builder.defineMacro("__REGISTER_PREFIX__", "");
2629 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2630 // functions in glibc header files that use FP Stack inline asm which the
2631 // backend can't deal with (PR879).
2632 Builder.defineMacro("__NO_MATH_INLINES");
2635 Builder.defineMacro("__AES__");
2638 Builder.defineMacro("__PCLMUL__");
2641 Builder.defineMacro("__LZCNT__");
2644 Builder.defineMacro("__RDRND__");
2647 Builder.defineMacro("__BMI__");
2650 Builder.defineMacro("__BMI2__");
2653 Builder.defineMacro("__POPCNT__");
2656 Builder.defineMacro("__RTM__");
2659 Builder.defineMacro("__PRFCHW__");
2662 Builder.defineMacro("__RDSEED__");
2665 Builder.defineMacro("__SSE4A__");
2668 Builder.defineMacro("__FMA4__");
2671 Builder.defineMacro("__FMA__");
2674 Builder.defineMacro("__XOP__");
2677 Builder.defineMacro("__F16C__");
2679 // Each case falls through to the previous one here.
2682 Builder.defineMacro("__AVX2__");
2684 Builder.defineMacro("__AVX__");
2686 Builder.defineMacro("__SSE4_2__");
2688 Builder.defineMacro("__SSE4_1__");
2690 Builder.defineMacro("__SSSE3__");
2692 Builder.defineMacro("__SSE3__");
2694 Builder.defineMacro("__SSE2__");
2695 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
2697 Builder.defineMacro("__SSE__");
2698 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
2703 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2712 Builder.defineMacro("_M_IX86_FP", Twine(2));
2715 Builder.defineMacro("_M_IX86_FP", Twine(1));
2718 Builder.defineMacro("_M_IX86_FP", Twine(0));
2722 // Each case falls through to the previous one here.
2723 switch (MMX3DNowLevel) {
2724 case AMD3DNowAthlon:
2725 Builder.defineMacro("__3dNOW_A__");
2727 Builder.defineMacro("__3dNOW__");
2729 Builder.defineMacro("__MMX__");
2734 if (CPU >= CK_i486) {
2735 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
2736 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
2737 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
2740 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
2743 bool X86TargetInfo::hasFeature(StringRef Feature) const {
2744 return llvm::StringSwitch<bool>(Feature)
2745 .Case("aes", HasAES)
2746 .Case("avx", SSELevel >= AVX)
2747 .Case("avx2", SSELevel >= AVX2)
2748 .Case("bmi", HasBMI)
2749 .Case("bmi2", HasBMI2)
2750 .Case("fma", HasFMA)
2751 .Case("fma4", HasFMA4)
2752 .Case("lzcnt", HasLZCNT)
2753 .Case("rdrnd", HasRDRND)
2754 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2755 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2756 .Case("mmx", MMX3DNowLevel >= MMX)
2757 .Case("pclmul", HasPCLMUL)
2758 .Case("popcnt", HasPOPCNT)
2759 .Case("rtm", HasRTM)
2760 .Case("prfchw", HasPRFCHW)
2761 .Case("rdseed", HasRDSEED)
2762 .Case("sse", SSELevel >= SSE1)
2763 .Case("sse2", SSELevel >= SSE2)
2764 .Case("sse3", SSELevel >= SSE3)
2765 .Case("ssse3", SSELevel >= SSSE3)
2766 .Case("sse41", SSELevel >= SSE41)
2767 .Case("sse42", SSELevel >= SSE42)
2768 .Case("sse4a", HasSSE4a)
2770 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2771 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2772 .Case("xop", HasXOP)
2773 .Case("f16c", HasF16C)
2778 X86TargetInfo::validateAsmConstraint(const char *&Name,
2779 TargetInfo::ConstraintInfo &Info) const {
2781 default: return false;
2782 case 'Y': // first letter of a pair:
2783 switch (*(Name+1)) {
2784 default: return false;
2785 case '0': // First SSE register.
2786 case 't': // Any SSE register, when SSE2 is enabled.
2787 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
2788 case 'm': // any MMX register, when inter-unit moves enabled.
2789 break; // falls through to setAllowsRegister.
2797 case 'A': // edx:eax.
2798 case 'f': // any x87 floating point stack register.
2799 case 't': // top of floating point stack.
2800 case 'u': // second from top of floating point stack.
2801 case 'q': // Any register accessible as [r]l: a, b, c, and d.
2802 case 'y': // Any MMX register.
2803 case 'x': // Any SSE register.
2804 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2805 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2806 case 'l': // "Index" registers: any general register that can be used as an
2807 // index in a base+index memory access.
2808 Info.setAllowsRegister();
2810 case 'C': // SSE floating point constant.
2811 case 'G': // x87 floating point constant.
2812 case 'e': // 32-bit signed integer constant for use with zero-extending
2813 // x86_64 instructions.
2814 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2815 // x86_64 instructions.
2822 X86TargetInfo::convertConstraint(const char *&Constraint) const {
2823 switch (*Constraint) {
2824 case 'a': return std::string("{ax}");
2825 case 'b': return std::string("{bx}");
2826 case 'c': return std::string("{cx}");
2827 case 'd': return std::string("{dx}");
2828 case 'S': return std::string("{si}");
2829 case 'D': return std::string("{di}");
2830 case 'p': // address
2831 return std::string("im");
2832 case 't': // top of floating point stack.
2833 return std::string("{st}");
2834 case 'u': // second from top of floating point stack.
2835 return std::string("{st(1)}"); // second from top of floating point stack.
2837 return std::string(1, *Constraint);
2840 } // end anonymous namespace
2843 // X86-32 generic target
2844 class X86_32TargetInfo : public X86TargetInfo {
2846 X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) {
2847 DoubleAlign = LongLongAlign = 32;
2848 LongDoubleWidth = 96;
2849 LongDoubleAlign = 32;
2850 SuitableAlign = 128;
2851 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2852 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2853 "a0:0:64-f80:32:32-n8:16:32-S128";
2854 SizeType = UnsignedInt;
2855 PtrDiffType = SignedInt;
2856 IntPtrType = SignedInt;
2859 // Use fpret for all types.
2860 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2861 (1 << TargetInfo::Double) |
2862 (1 << TargetInfo::LongDouble));
2864 // x86-32 has atomics up to 8 bytes
2865 // FIXME: Check that we actually have cmpxchg8b before setting
2866 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2867 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2869 virtual BuiltinVaListKind getBuiltinVaListKind() const {
2870 return TargetInfo::CharPtrBuiltinVaList;
2873 int getEHDataRegisterNumber(unsigned RegNo) const {
2874 if (RegNo == 0) return 0;
2875 if (RegNo == 1) return 2;
2878 virtual bool validateInputSize(StringRef Constraint,
2879 unsigned Size) const {
2880 switch (Constraint[0]) {
2892 } // end anonymous namespace
2895 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2897 NetBSDI386TargetInfo(const std::string &triple) :
2898 NetBSDTargetInfo<X86_32TargetInfo>(triple) {
2901 virtual unsigned getFloatEvalMethod() const {
2902 // NetBSD defaults to "double" rounding
2906 } // end anonymous namespace
2909 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
2911 OpenBSDI386TargetInfo(const std::string& triple) :
2912 OpenBSDTargetInfo<X86_32TargetInfo>(triple) {
2913 SizeType = UnsignedLong;
2914 IntPtrType = SignedLong;
2915 PtrDiffType = SignedLong;
2918 } // end anonymous namespace
2921 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
2923 BitrigI386TargetInfo(const std::string& triple) :
2924 BitrigTargetInfo<X86_32TargetInfo>(triple) {
2925 SizeType = UnsignedLong;
2926 IntPtrType = SignedLong;
2927 PtrDiffType = SignedLong;
2930 } // end anonymous namespace
2933 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
2935 DarwinI386TargetInfo(const std::string& triple) :
2936 DarwinTargetInfo<X86_32TargetInfo>(triple) {
2937 LongDoubleWidth = 128;
2938 LongDoubleAlign = 128;
2939 SuitableAlign = 128;
2940 MaxVectorAlign = 256;
2941 SizeType = UnsignedLong;
2942 IntPtrType = SignedLong;
2943 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2944 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2945 "a0:0:64-f80:128:128-n8:16:32-S128";
2946 HasAlignMac68kSupport = true;
2950 } // end anonymous namespace
2953 // x86-32 Windows target
2954 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
2956 WindowsX86_32TargetInfo(const std::string& triple)
2957 : WindowsTargetInfo<X86_32TargetInfo>(triple) {
2958 TLSSupported = false;
2959 WCharType = UnsignedShort;
2960 DoubleAlign = LongLongAlign = 64;
2961 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2962 "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
2963 "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
2965 virtual void getTargetDefines(const LangOptions &Opts,
2966 MacroBuilder &Builder) const {
2967 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
2970 } // end anonymous namespace
2974 // x86-32 Windows Visual Studio target
2975 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
2977 VisualStudioWindowsX86_32TargetInfo(const std::string& triple)
2978 : WindowsX86_32TargetInfo(triple) {
2979 LongDoubleWidth = LongDoubleAlign = 64;
2980 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
2982 virtual void getTargetDefines(const LangOptions &Opts,
2983 MacroBuilder &Builder) const {
2984 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
2985 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
2986 // The value of the following reflects processor type.
2987 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
2988 // We lost the original triple, so we use the default.
2989 Builder.defineMacro("_M_IX86", "600");
2992 } // end anonymous namespace
2995 // x86-32 MinGW target
2996 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
2998 MinGWX86_32TargetInfo(const std::string& triple)
2999 : WindowsX86_32TargetInfo(triple) {
3001 virtual void getTargetDefines(const LangOptions &Opts,
3002 MacroBuilder &Builder) const {
3003 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3004 DefineStd(Builder, "WIN32", Opts);
3005 DefineStd(Builder, "WINNT", Opts);
3006 Builder.defineMacro("_X86_");
3007 Builder.defineMacro("__MSVCRT__");
3008 Builder.defineMacro("__MINGW32__");
3010 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3011 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3012 if (Opts.MicrosoftExt)
3013 // Provide "as-is" __declspec.
3014 Builder.defineMacro("__declspec", "__declspec");
3016 // Provide alias of __attribute__ like mingw32-gcc.
3017 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3020 } // end anonymous namespace
3023 // x86-32 Cygwin target
3024 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3026 CygwinX86_32TargetInfo(const std::string& triple)
3027 : X86_32TargetInfo(triple) {
3028 TLSSupported = false;
3029 WCharType = UnsignedShort;
3030 DoubleAlign = LongLongAlign = 64;
3031 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3032 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3033 "a0:0:64-f80:32:32-n8:16:32-S32";
3035 virtual void getTargetDefines(const LangOptions &Opts,
3036 MacroBuilder &Builder) const {
3037 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3038 Builder.defineMacro("_X86_");
3039 Builder.defineMacro("__CYGWIN__");
3040 Builder.defineMacro("__CYGWIN32__");
3041 DefineStd(Builder, "unix", Opts);
3043 Builder.defineMacro("_GNU_SOURCE");
3046 } // end anonymous namespace
3049 // x86-32 Haiku target
3050 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3052 HaikuX86_32TargetInfo(const std::string& triple)
3053 : X86_32TargetInfo(triple) {
3054 SizeType = UnsignedLong;
3055 IntPtrType = SignedLong;
3056 PtrDiffType = SignedLong;
3057 ProcessIDType = SignedLong;
3058 this->UserLabelPrefix = "";
3059 this->TLSSupported = false;
3061 virtual void getTargetDefines(const LangOptions &Opts,
3062 MacroBuilder &Builder) const {
3063 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3064 Builder.defineMacro("__INTEL__");
3065 Builder.defineMacro("__HAIKU__");
3068 } // end anonymous namespace
3071 template<typename Target>
3072 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3074 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3075 MacroBuilder &Builder) const {
3076 // RTEMS defines; list based off of gcc output
3078 Builder.defineMacro("__rtems__");
3079 Builder.defineMacro("__ELF__");
3082 RTEMSTargetInfo(const std::string &triple)
3083 : OSTargetInfo<Target>(triple) {
3084 this->UserLabelPrefix = "";
3086 llvm::Triple Triple(triple);
3087 switch (Triple.getArch()) {
3089 case llvm::Triple::x86:
3090 // this->MCountName = ".mcount";
3092 case llvm::Triple::mips:
3093 case llvm::Triple::mipsel:
3094 case llvm::Triple::ppc:
3095 case llvm::Triple::ppc64:
3096 // this->MCountName = "_mcount";
3098 case llvm::Triple::arm:
3099 // this->MCountName = "__mcount";
3107 // x86-32 RTEMS target
3108 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3110 RTEMSX86_32TargetInfo(const std::string& triple)
3111 : X86_32TargetInfo(triple) {
3112 SizeType = UnsignedLong;
3113 IntPtrType = SignedLong;
3114 PtrDiffType = SignedLong;
3115 this->UserLabelPrefix = "";
3117 virtual void getTargetDefines(const LangOptions &Opts,
3118 MacroBuilder &Builder) const {
3119 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3120 Builder.defineMacro("__INTEL__");
3121 Builder.defineMacro("__rtems__");
3124 } // end anonymous namespace
3127 // x86-64 generic target
3128 class X86_64TargetInfo : public X86TargetInfo {
3130 X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) {
3131 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
3132 LongDoubleWidth = 128;
3133 LongDoubleAlign = 128;
3134 LargeArrayMinWidth = 128;
3135 LargeArrayAlign = 128;
3136 SuitableAlign = 128;
3137 IntMaxType = SignedLong;
3138 UIntMaxType = UnsignedLong;
3139 Int64Type = SignedLong;
3142 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3143 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3144 "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
3146 // Use fpret only for long double.
3147 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3149 // Use fp2ret for _Complex long double.
3150 ComplexLongDoubleUsesFP2Ret = true;
3152 // x86-64 has atomics up to 16 bytes.
3153 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
3154 // on CPUs with cmpxchg16b
3155 MaxAtomicPromoteWidth = 128;
3156 MaxAtomicInlineWidth = 64;
3158 virtual BuiltinVaListKind getBuiltinVaListKind() const {
3159 return TargetInfo::X86_64ABIBuiltinVaList;
3162 int getEHDataRegisterNumber(unsigned RegNo) const {
3163 if (RegNo == 0) return 0;
3164 if (RegNo == 1) return 1;
3168 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3169 return (CC == CC_Default ||
3171 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
3174 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
3179 } // end anonymous namespace
3182 // x86-64 Windows target
3183 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3185 WindowsX86_64TargetInfo(const std::string& triple)
3186 : WindowsTargetInfo<X86_64TargetInfo>(triple) {
3187 TLSSupported = false;
3188 WCharType = UnsignedShort;
3189 LongWidth = LongAlign = 32;
3190 DoubleAlign = LongLongAlign = 64;
3191 IntMaxType = SignedLongLong;
3192 UIntMaxType = UnsignedLongLong;
3193 Int64Type = SignedLongLong;
3194 SizeType = UnsignedLongLong;
3195 PtrDiffType = SignedLongLong;
3196 IntPtrType = SignedLongLong;
3197 this->UserLabelPrefix = "";
3199 virtual void getTargetDefines(const LangOptions &Opts,
3200 MacroBuilder &Builder) const {
3201 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3202 Builder.defineMacro("_WIN64");
3204 virtual BuiltinVaListKind getBuiltinVaListKind() const {
3205 return TargetInfo::CharPtrBuiltinVaList;
3208 } // end anonymous namespace
3211 // x86-64 Windows Visual Studio target
3212 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
3214 VisualStudioWindowsX86_64TargetInfo(const std::string& triple)
3215 : WindowsX86_64TargetInfo(triple) {
3216 LongDoubleWidth = LongDoubleAlign = 64;
3217 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3219 virtual void getTargetDefines(const LangOptions &Opts,
3220 MacroBuilder &Builder) const {
3221 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3222 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3223 Builder.defineMacro("_M_X64");
3224 Builder.defineMacro("_M_AMD64");
3227 } // end anonymous namespace
3230 // x86-64 MinGW target
3231 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3233 MinGWX86_64TargetInfo(const std::string& triple)
3234 : WindowsX86_64TargetInfo(triple) {
3236 virtual void getTargetDefines(const LangOptions &Opts,
3237 MacroBuilder &Builder) const {
3238 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3239 DefineStd(Builder, "WIN64", Opts);
3240 Builder.defineMacro("__MSVCRT__");
3241 Builder.defineMacro("__MINGW32__");
3242 Builder.defineMacro("__MINGW64__");
3244 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3245 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3246 if (Opts.MicrosoftExt)
3247 // Provide "as-is" __declspec.
3248 Builder.defineMacro("__declspec", "__declspec");
3250 // Provide alias of __attribute__ like mingw32-gcc.
3251 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3254 } // end anonymous namespace
3257 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3259 DarwinX86_64TargetInfo(const std::string& triple)
3260 : DarwinTargetInfo<X86_64TargetInfo>(triple) {
3261 Int64Type = SignedLongLong;
3262 MaxVectorAlign = 256;
3265 } // end anonymous namespace
3268 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3270 OpenBSDX86_64TargetInfo(const std::string& triple)
3271 : OpenBSDTargetInfo<X86_64TargetInfo>(triple) {
3272 IntMaxType = SignedLongLong;
3273 UIntMaxType = UnsignedLongLong;
3274 Int64Type = SignedLongLong;
3277 } // end anonymous namespace
3280 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3282 BitrigX86_64TargetInfo(const std::string& triple)
3283 : BitrigTargetInfo<X86_64TargetInfo>(triple) {
3284 IntMaxType = SignedLongLong;
3285 UIntMaxType = UnsignedLongLong;
3286 Int64Type = SignedLongLong;
3292 class AArch64TargetInfo : public TargetInfo {
3293 static const char * const GCCRegNames[];
3294 static const TargetInfo::GCCRegAlias GCCRegAliases[];
3296 AArch64TargetInfo(const std::string& triple) : TargetInfo(triple) {
3298 LongWidth = LongAlign = 64;
3299 LongDoubleWidth = LongDoubleAlign = 128;
3300 PointerWidth = PointerAlign = 64;
3301 SuitableAlign = 128;
3302 DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3303 "i64:64:64-i128:128:128-f32:32:32-f64:64:64-"
3304 "f128:128:128-n32:64-S128";
3306 WCharType = UnsignedInt;
3307 LongDoubleFormat = &llvm::APFloat::IEEEquad;
3309 // AArch64 backend supports 64-bit operations at the moment. In principle
3310 // 128-bit is possible if register-pairs are used.
3311 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3313 TheCXXABI.set(TargetCXXABI::GenericAArch64);
3315 virtual void getTargetDefines(const LangOptions &Opts,
3316 MacroBuilder &Builder) const {
3317 // GCC defines theses currently
3318 Builder.defineMacro("__aarch64__");
3319 Builder.defineMacro("__AARCH64EL__");
3321 // ACLE predefines. Many can only have one possible value on v8 AArch64.
3323 // FIXME: these were written based on an unreleased version of a 32-bit ACLE
3324 // which was intended to be compatible with a 64-bit implementation. They
3325 // will need updating when a real 64-bit ACLE exists. Particularly pressing
3326 // instances are: __AARCH_ISA_A32, __AARCH_ISA_T32, __ARCH_PCS.
3327 Builder.defineMacro("__AARCH_ACLE", "101");
3328 Builder.defineMacro("__AARCH", "8");
3329 Builder.defineMacro("__AARCH_PROFILE", "'A'");
3331 Builder.defineMacro("__AARCH_FEATURE_UNALIGNED");
3332 Builder.defineMacro("__AARCH_FEATURE_CLZ");
3333 Builder.defineMacro("__AARCH_FEATURE_FMA");
3335 // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean
3336 // 128-bit LDXP present, at which point this becomes 0x1f.
3337 Builder.defineMacro("__AARCH_FEATURE_LDREX", "0xf");
3339 // 0xe implies support for half, single and double precision operations.
3340 Builder.defineMacro("__AARCH_FP", "0xe");
3342 // PCS specifies this for SysV variants, which is all we support. Other ABIs
3343 // may choose __AARCH_FP16_FORMAT_ALTERNATIVE.
3344 Builder.defineMacro("__AARCH_FP16_FORMAT_IEEE");
3346 if (Opts.FastMath || Opts.FiniteMathOnly)
3347 Builder.defineMacro("__AARCH_FP_FAST");
3349 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
3350 Builder.defineMacro("__AARCH_FP_FENV_ROUNDING");
3352 Builder.defineMacro("__AARCH_SIZEOF_WCHAR_T",
3353 Opts.ShortWChar ? "2" : "4");
3355 Builder.defineMacro("__AARCH_SIZEOF_MINIMAL_ENUM",
3356 Opts.ShortEnums ? "1" : "4");
3359 Builder.defineMacro("__AARCH_BIG_ENDIAN");
3361 virtual void getTargetBuiltins(const Builtin::Info *&Records,
3362 unsigned &NumRecords) const {
3366 virtual bool hasFeature(StringRef Feature) const {
3367 return Feature == "aarch64";
3369 virtual void getGCCRegNames(const char * const *&Names,
3370 unsigned &NumNames) const;
3371 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3372 unsigned &NumAliases) const;
3374 virtual bool isCLZForZeroUndef() const { return false; }
3376 virtual bool validateAsmConstraint(const char *&Name,
3377 TargetInfo::ConstraintInfo &Info) const {
3379 default: return false;
3380 case 'w': // An FP/SIMD vector register
3381 Info.setAllowsRegister();
3383 case 'I': // Constant that can be used with an ADD instruction
3384 case 'J': // Constant that can be used with a SUB instruction
3385 case 'K': // Constant that can be used with a 32-bit logical instruction
3386 case 'L': // Constant that can be used with a 64-bit logical instruction
3387 case 'M': // Constant that can be used as a 32-bit MOV immediate
3388 case 'N': // Constant that can be used as a 64-bit MOV immediate
3389 case 'Y': // Floating point constant zero
3390 case 'Z': // Integer constant zero
3392 case 'Q': // A memory reference with base register and no offset
3393 Info.setAllowsMemory();
3395 case 'S': // A symbolic address
3396 Info.setAllowsRegister();
3399 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
3400 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
3401 // Usa: An absolute symbolic address
3402 // Ush: The high part (bits 32:12) of a pc-relative symbolic address
3403 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
3407 virtual const char *getClobbers() const {
3408 // There are no AArch64 clobbers shared by all asm statements.
3412 virtual BuiltinVaListKind getBuiltinVaListKind() const {
3413 return TargetInfo::AArch64ABIBuiltinVaList;
3417 const char * const AArch64TargetInfo::GCCRegNames[] = {
3418 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
3419 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
3420 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3421 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
3423 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
3424 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
3425 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
3426 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
3428 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
3429 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
3430 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
3431 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
3433 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
3434 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
3435 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
3436 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
3438 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3439 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3440 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3441 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3443 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3444 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3445 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3446 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3448 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3449 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
3450 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
3451 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
3454 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
3455 unsigned &NumNames) const {
3456 Names = GCCRegNames;
3457 NumNames = llvm::array_lengthof(GCCRegNames);
3460 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
3461 { { "x16" }, "ip0"},
3462 { { "x17" }, "ip1"},
3463 { { "x29" }, "fp" },
3467 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3468 unsigned &NumAliases) const {
3469 Aliases = GCCRegAliases;
3470 NumAliases = llvm::array_lengthof(GCCRegAliases);
3473 } // end anonymous namespace
3476 class ARMTargetInfo : public TargetInfo {
3477 // Possible FPU choices.
3485 static bool FPUModeIsVFP(FPUMode Mode) {
3486 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU);
3489 static const TargetInfo::GCCRegAlias GCCRegAliases[];
3490 static const char * const GCCRegNames[];
3492 std::string ABI, CPU;
3496 unsigned IsAAPCS : 1;
3497 unsigned IsThumb : 1;
3499 // Initialized via features.
3500 unsigned SoftFloat : 1;
3501 unsigned SoftFloatABI : 1;
3503 static const Builtin::Info BuiltinInfo[];
3506 ARMTargetInfo(const std::string &TripleStr)
3507 : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s"), IsAAPCS(true)
3510 SizeType = UnsignedInt;
3511 PtrDiffType = SignedInt;
3512 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3513 WCharType = UnsignedInt;
3515 // {} in inline assembly are neon specifiers, not assembly variant
3517 NoAsmVariants = true;
3519 // FIXME: Should we just treat this as a feature?
3520 IsThumb = getTriple().getArchName().startswith("thumb");
3522 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3523 // so set preferred for small types to 32.
3524 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3525 "i64:64:64-f32:32:32-f64:64:64-"
3526 "v64:64:64-v128:64:128-a0:0:32-n32-S64");
3528 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3529 "i64:64:64-f32:32:32-f64:64:64-"
3530 "v64:64:64-v128:64:128-a0:0:64-n32-S64");
3533 // ARM targets default to using the ARM C++ ABI.
3534 TheCXXABI.set(TargetCXXABI::GenericARM);
3536 // ARM has atomics up to 8 bytes
3537 // FIXME: Set MaxAtomicInlineWidth if we have the feature v6e
3538 MaxAtomicPromoteWidth = 64;
3540 // Do force alignment of members that follow zero length bitfields. If
3541 // the alignment of the zero-length bitfield is greater than the member
3542 // that follows it, `bar', `bar' will be aligned as the type of the
3543 // zero length bitfield.
3544 UseZeroLengthBitfieldAlignment = true;
3546 virtual const char *getABI() const { return ABI.c_str(); }
3547 virtual bool setABI(const std::string &Name) {
3550 // The defaults (above) are for AAPCS, check if we need to change them.
3552 // FIXME: We need support for -meabi... we could just mangle it into the
3554 if (Name == "apcs-gnu") {
3555 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3556 // size_t is unsigned int on FreeBSD.
3557 if (getTriple().getOS() != llvm::Triple::FreeBSD)
3558 SizeType = UnsignedLong;
3560 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3561 WCharType = SignedInt;
3563 // Do not respect the alignment of bit-field types when laying out
3564 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3565 UseBitFieldTypeAlignment = false;
3567 /// gcc forces the alignment to 4 bytes, regardless of the type of the
3568 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
3570 ZeroLengthBitfieldBoundary = 32;
3575 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3576 // so set preferred for small types to 32.
3577 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3578 "i64:32:64-f32:32:32-f64:32:64-"
3579 "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3581 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3582 "i64:32:64-f32:32:32-f64:32:64-"
3583 "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3586 // FIXME: Override "preferred align" for double and long long.
3587 } else if (Name == "aapcs" || Name == "aapcs-vfp") {
3589 // FIXME: Enumerated types are variable width in straight AAPCS.
3590 } else if (Name == "aapcs-linux") {
3598 void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3599 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3600 Features["vfp2"] = true;
3601 else if (CPU == "cortex-a8" || CPU == "cortex-a15" ||
3602 CPU == "cortex-a9" || CPU == "cortex-a9-mp")
3603 Features["neon"] = true;
3604 else if (CPU == "swift" || CPU == "cortex-a7") {
3605 Features["vfp4"] = true;
3606 Features["neon"] = true;
3610 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3612 bool Enabled) const {
3613 if (Name == "soft-float" || Name == "soft-float-abi" ||
3614 Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" ||
3615 Name == "d16" || Name == "neonfp") {
3616 Features[Name] = Enabled;
3623 virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3625 SoftFloat = SoftFloatABI = false;
3626 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3627 if (Features[i] == "+soft-float")
3629 else if (Features[i] == "+soft-float-abi")
3630 SoftFloatABI = true;
3631 else if (Features[i] == "+vfp2")
3633 else if (Features[i] == "+vfp3")
3635 else if (Features[i] == "+vfp4")
3637 else if (Features[i] == "+neon")
3641 // Remove front-end specific options which the backend handles differently.
3642 std::vector<std::string>::iterator it;
3643 it = std::find(Features.begin(), Features.end(), "+soft-float");
3644 if (it != Features.end())
3646 it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3647 if (it != Features.end())
3651 virtual bool hasFeature(StringRef Feature) const {
3652 return llvm::StringSwitch<bool>(Feature)
3654 .Case("softfloat", SoftFloat)
3655 .Case("thumb", IsThumb)
3656 .Case("neon", FPU == NeonFPU && !SoftFloat &&
3657 StringRef(getCPUDefineSuffix(CPU)).startswith("7"))
3660 // FIXME: Should we actually have some table instead of these switches?
3661 static const char *getCPUDefineSuffix(StringRef Name) {
3662 return llvm::StringSwitch<const char*>(Name)
3663 .Cases("arm8", "arm810", "4")
3664 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3665 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3666 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3667 .Case("ep9312", "4T")
3668 .Cases("arm10tdmi", "arm1020t", "5T")
3669 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3670 .Case("arm926ej-s", "5TEJ")
3671 .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3672 .Cases("xscale", "iwmmxt", "5TE")
3673 .Case("arm1136j-s", "6J")
3674 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3675 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3676 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3677 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
3678 .Cases("cortex-a9", "cortex-a15", "7A")
3679 .Case("cortex-r5", "7R")
3680 .Case("cortex-a9-mp", "7F")
3681 .Case("swift", "7S")
3682 .Cases("cortex-m3", "cortex-m4", "7M")
3683 .Case("cortex-m0", "6M")
3686 static const char *getCPUProfile(StringRef Name) {
3687 return llvm::StringSwitch<const char*>(Name)
3688 .Cases("cortex-a8", "cortex-a9", "A")
3689 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3690 .Case("cortex-r5", "R")
3693 virtual bool setCPU(const std::string &Name) {
3694 if (!getCPUDefineSuffix(Name))
3700 virtual void getTargetDefines(const LangOptions &Opts,
3701 MacroBuilder &Builder) const {
3702 // Target identification.
3703 Builder.defineMacro("__arm");
3704 Builder.defineMacro("__arm__");
3706 // Target properties.
3707 Builder.defineMacro("__ARMEL__");
3708 Builder.defineMacro("__LITTLE_ENDIAN__");
3709 Builder.defineMacro("__REGISTER_PREFIX__", "");
3711 StringRef CPUArch = getCPUDefineSuffix(CPU);
3712 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3713 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3714 StringRef CPUProfile = getCPUProfile(CPU);
3715 if (!CPUProfile.empty())
3716 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3718 // Subtarget options.
3720 // FIXME: It's more complicated than this and we don't really support
3722 if ('5' <= CPUArch[0] && CPUArch[0] <= '7')
3723 Builder.defineMacro("__THUMB_INTERWORK__");
3725 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3726 // M-class CPUs on Darwin follow AAPCS, but not EABI.
3727 if (!(getTriple().isOSDarwin() && CPUProfile == "M"))
3728 Builder.defineMacro("__ARM_EABI__");
3729 Builder.defineMacro("__ARM_PCS", "1");
3731 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3732 Builder.defineMacro("__ARM_PCS_VFP", "1");
3736 Builder.defineMacro("__SOFTFP__");
3738 if (CPU == "xscale")
3739 Builder.defineMacro("__XSCALE__");
3741 bool IsARMv7 = CPUArch.startswith("7");
3743 Builder.defineMacro("__THUMBEL__");
3744 Builder.defineMacro("__thumb__");
3745 if (CPUArch == "6T2" || IsARMv7)
3746 Builder.defineMacro("__thumb2__");
3749 // Note, this is always on in gcc, even though it doesn't make sense.
3750 Builder.defineMacro("__APCS_32__");
3752 if (FPUModeIsVFP((FPUMode) FPU)) {
3753 Builder.defineMacro("__VFP_FP__");
3755 Builder.defineMacro("__ARM_VFPV2__");
3757 Builder.defineMacro("__ARM_VFPV3__");
3759 Builder.defineMacro("__ARM_VFPV4__");
3762 // This only gets set when Neon instructions are actually available, unlike
3763 // the VFP define, hence the soft float and arch check. This is subtly
3764 // different from gcc, we follow the intent which was that it should be set
3765 // when Neon instructions are actually available.
3766 if ((FPU & NeonFPU) && !SoftFloat && IsARMv7)
3767 Builder.defineMacro("__ARM_NEON__");
3769 virtual void getTargetBuiltins(const Builtin::Info *&Records,
3770 unsigned &NumRecords) const {
3771 Records = BuiltinInfo;
3772 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
3774 virtual bool isCLZForZeroUndef() const { return false; }
3775 virtual BuiltinVaListKind getBuiltinVaListKind() const {
3776 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
3778 virtual void getGCCRegNames(const char * const *&Names,
3779 unsigned &NumNames) const;
3780 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3781 unsigned &NumAliases) const;
3782 virtual bool validateAsmConstraint(const char *&Name,
3783 TargetInfo::ConstraintInfo &Info) const {
3788 case 'w': // VFP Floating point register single precision
3789 case 'P': // VFP Floating point register double precision
3790 Info.setAllowsRegister();
3792 case 'Q': // A memory address that is a single base register.
3793 Info.setAllowsMemory();
3795 case 'U': // a memory reference...
3797 case 'q': // ...ARMV4 ldrsb
3798 case 'v': // ...VFP load/store (reg+constant offset)
3799 case 'y': // ...iWMMXt load/store
3800 case 't': // address valid for load/store opaque types wider
3802 case 'n': // valid address for Neon doubleword vector load/store
3803 case 'm': // valid address for Neon element and structure load/store
3804 case 's': // valid address for non-offset loads/stores of quad-word
3805 // values in four ARM registers
3806 Info.setAllowsMemory();
3813 virtual std::string convertConstraint(const char *&Constraint) const {
3815 switch (*Constraint) {
3816 case 'U': // Two-character constraint; add "^" hint for later parsing.
3817 R = std::string("^") + std::string(Constraint, 2);
3820 case 'p': // 'p' should be translated to 'r' by default.
3821 R = std::string("r");
3824 return std::string(1, *Constraint);
3828 virtual bool validateConstraintModifier(StringRef Constraint,
3829 const char Modifier,
3830 unsigned Size) const {
3831 bool isOutput = (Constraint[0] == '=');
3832 bool isInOut = (Constraint[0] == '+');
3834 // Strip off constraint modifiers.
3835 while (Constraint[0] == '=' ||
3836 Constraint[0] == '+' ||
3837 Constraint[0] == '&')
3838 Constraint = Constraint.substr(1);
3840 switch (Constraint[0]) {
3845 return isInOut || (isOutput && Size >= 32) ||
3846 (!isOutput && !isInOut && Size <= 32);
3848 // A register of size 32 cannot fit a vector type.
3856 virtual const char *getClobbers() const {
3857 // FIXME: Is this really right?
3861 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3862 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
3865 virtual int getEHDataRegisterNumber(unsigned RegNo) const {
3866 if (RegNo == 0) return 0;
3867 if (RegNo == 1) return 1;
3872 const char * const ARMTargetInfo::GCCRegNames[] = {
3873 // Integer registers
3874 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3875 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
3878 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3879 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3880 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3881 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3884 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3885 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3886 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3887 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3890 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3891 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
3894 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
3895 unsigned &NumNames) const {
3896 Names = GCCRegNames;
3897 NumNames = llvm::array_lengthof(GCCRegNames);
3900 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
3910 { { "v6", "rfp" }, "r9" },
3911 { { "sl" }, "r10" },
3912 { { "fp" }, "r11" },
3913 { { "ip" }, "r12" },
3914 { { "r13" }, "sp" },
3915 { { "r14" }, "lr" },
3916 { { "r15" }, "pc" },
3917 // The S, D and Q registers overlap, but aren't really aliases; we
3918 // don't want to substitute one of these for a different-sized one.
3921 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3922 unsigned &NumAliases) const {
3923 Aliases = GCCRegAliases;
3924 NumAliases = llvm::array_lengthof(GCCRegAliases);
3927 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
3928 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3929 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3931 #include "clang/Basic/BuiltinsARM.def"
3933 } // end anonymous namespace.
3936 class DarwinARMTargetInfo :
3937 public DarwinTargetInfo<ARMTargetInfo> {
3939 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3940 MacroBuilder &Builder) const {
3941 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
3945 DarwinARMTargetInfo(const std::string& triple)
3946 : DarwinTargetInfo<ARMTargetInfo>(triple) {
3947 HasAlignMac68kSupport = true;
3948 // iOS always has 64-bit atomic instructions.
3949 // FIXME: This should be based off of the target features in ARMTargetInfo.
3950 MaxAtomicInlineWidth = 64;
3952 // Darwin on iOS uses a variant of the ARM C++ ABI.
3953 TheCXXABI.set(TargetCXXABI::iOS);
3956 } // end anonymous namespace.
3960 // Hexagon abstract base class
3961 class HexagonTargetInfo : public TargetInfo {
3962 static const Builtin::Info BuiltinInfo[];
3963 static const char * const GCCRegNames[];
3964 static const TargetInfo::GCCRegAlias GCCRegAliases[];
3967 HexagonTargetInfo(const std::string& triple) : TargetInfo(triple) {
3969 DescriptionString = ("e-p:32:32:32-"
3970 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
3971 "f64:64:64-f32:32:32-a0:0-n32");
3973 // {} in inline assembly are packet specifiers, not assembly variant
3975 NoAsmVariants = true;
3978 virtual void getTargetBuiltins(const Builtin::Info *&Records,
3979 unsigned &NumRecords) const {
3980 Records = BuiltinInfo;
3981 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
3984 virtual bool validateAsmConstraint(const char *&Name,
3985 TargetInfo::ConstraintInfo &Info) const {
3989 virtual void getTargetDefines(const LangOptions &Opts,
3990 MacroBuilder &Builder) const;
3992 virtual bool hasFeature(StringRef Feature) const {
3993 return Feature == "hexagon";
3996 virtual BuiltinVaListKind getBuiltinVaListKind() const {
3997 return TargetInfo::CharPtrBuiltinVaList;
3999 virtual void getGCCRegNames(const char * const *&Names,
4000 unsigned &NumNames) const;
4001 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4002 unsigned &NumAliases) const;
4003 virtual const char *getClobbers() const {
4007 static const char *getHexagonCPUSuffix(StringRef Name) {
4008 return llvm::StringSwitch<const char*>(Name)
4009 .Case("hexagonv4", "4")
4010 .Case("hexagonv5", "5")
4014 virtual bool setCPU(const std::string &Name) {
4015 if (!getHexagonCPUSuffix(Name))
4023 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4024 MacroBuilder &Builder) const {
4025 Builder.defineMacro("qdsp6");
4026 Builder.defineMacro("__qdsp6", "1");
4027 Builder.defineMacro("__qdsp6__", "1");
4029 Builder.defineMacro("hexagon");
4030 Builder.defineMacro("__hexagon", "1");
4031 Builder.defineMacro("__hexagon__", "1");
4033 if(CPU == "hexagonv1") {
4034 Builder.defineMacro("__HEXAGON_V1__");
4035 Builder.defineMacro("__HEXAGON_ARCH__", "1");
4036 if(Opts.HexagonQdsp6Compat) {
4037 Builder.defineMacro("__QDSP6_V1__");
4038 Builder.defineMacro("__QDSP6_ARCH__", "1");
4041 else if(CPU == "hexagonv2") {
4042 Builder.defineMacro("__HEXAGON_V2__");
4043 Builder.defineMacro("__HEXAGON_ARCH__", "2");
4044 if(Opts.HexagonQdsp6Compat) {
4045 Builder.defineMacro("__QDSP6_V2__");
4046 Builder.defineMacro("__QDSP6_ARCH__", "2");
4049 else if(CPU == "hexagonv3") {
4050 Builder.defineMacro("__HEXAGON_V3__");
4051 Builder.defineMacro("__HEXAGON_ARCH__", "3");
4052 if(Opts.HexagonQdsp6Compat) {
4053 Builder.defineMacro("__QDSP6_V3__");
4054 Builder.defineMacro("__QDSP6_ARCH__", "3");
4057 else if(CPU == "hexagonv4") {
4058 Builder.defineMacro("__HEXAGON_V4__");
4059 Builder.defineMacro("__HEXAGON_ARCH__", "4");
4060 if(Opts.HexagonQdsp6Compat) {
4061 Builder.defineMacro("__QDSP6_V4__");
4062 Builder.defineMacro("__QDSP6_ARCH__", "4");
4065 else if(CPU == "hexagonv5") {
4066 Builder.defineMacro("__HEXAGON_V5__");
4067 Builder.defineMacro("__HEXAGON_ARCH__", "5");
4068 if(Opts.HexagonQdsp6Compat) {
4069 Builder.defineMacro("__QDSP6_V5__");
4070 Builder.defineMacro("__QDSP6_ARCH__", "5");
4075 const char * const HexagonTargetInfo::GCCRegNames[] = {
4076 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4077 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4078 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4079 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
4080 "p0", "p1", "p2", "p3",
4081 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
4084 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
4085 unsigned &NumNames) const {
4086 Names = GCCRegNames;
4087 NumNames = llvm::array_lengthof(GCCRegNames);
4091 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
4092 { { "sp" }, "r29" },
4093 { { "fp" }, "r30" },
4094 { { "lr" }, "r31" },
4097 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4098 unsigned &NumAliases) const {
4099 Aliases = GCCRegAliases;
4100 NumAliases = llvm::array_lengthof(GCCRegAliases);
4104 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
4105 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4106 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4108 #include "clang/Basic/BuiltinsHexagon.def"
4114 class SparcV8TargetInfo : public TargetInfo {
4115 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4116 static const char * const GCCRegNames[];
4119 SparcV8TargetInfo(const std::string& triple) : TargetInfo(triple) {
4120 // FIXME: Support Sparc quad-precision long double?
4121 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4122 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32";
4124 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4126 bool Enabled) const {
4127 if (Name == "soft-float")
4128 Features[Name] = Enabled;
4134 virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4136 for (unsigned i = 0, e = Features.size(); i != e; ++i)
4137 if (Features[i] == "+soft-float")
4140 virtual void getTargetDefines(const LangOptions &Opts,
4141 MacroBuilder &Builder) const {
4142 DefineStd(Builder, "sparc", Opts);
4143 Builder.defineMacro("__sparcv8");
4144 Builder.defineMacro("__REGISTER_PREFIX__", "");
4147 Builder.defineMacro("SOFT_FLOAT", "1");
4150 virtual bool hasFeature(StringRef Feature) const {
4151 return llvm::StringSwitch<bool>(Feature)
4152 .Case("softfloat", SoftFloat)
4153 .Case("sparc", true)
4157 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4158 unsigned &NumRecords) const {
4159 // FIXME: Implement!
4161 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4162 return TargetInfo::VoidPtrBuiltinVaList;
4164 virtual void getGCCRegNames(const char * const *&Names,
4165 unsigned &NumNames) const;
4166 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4167 unsigned &NumAliases) const;
4168 virtual bool validateAsmConstraint(const char *&Name,
4169 TargetInfo::ConstraintInfo &info) const {
4170 // FIXME: Implement!
4173 virtual const char *getClobbers() const {
4174 // FIXME: Implement!
4179 const char * const SparcV8TargetInfo::GCCRegNames[] = {
4180 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4181 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4182 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4183 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4186 void SparcV8TargetInfo::getGCCRegNames(const char * const *&Names,
4187 unsigned &NumNames) const {
4188 Names = GCCRegNames;
4189 NumNames = llvm::array_lengthof(GCCRegNames);
4192 const TargetInfo::GCCRegAlias SparcV8TargetInfo::GCCRegAliases[] = {
4203 { { "o2" }, "r10" },
4204 { { "o3" }, "r11" },
4205 { { "o4" }, "r12" },
4206 { { "o5" }, "r13" },
4207 { { "o6", "sp" }, "r14" },
4208 { { "o7" }, "r15" },
4209 { { "l0" }, "r16" },
4210 { { "l1" }, "r17" },
4211 { { "l2" }, "r18" },
4212 { { "l3" }, "r19" },
4213 { { "l4" }, "r20" },
4214 { { "l5" }, "r21" },
4215 { { "l6" }, "r22" },
4216 { { "l7" }, "r23" },
4217 { { "i0" }, "r24" },
4218 { { "i1" }, "r25" },
4219 { { "i2" }, "r26" },
4220 { { "i3" }, "r27" },
4221 { { "i4" }, "r28" },
4222 { { "i5" }, "r29" },
4223 { { "i6", "fp" }, "r30" },
4224 { { "i7" }, "r31" },
4227 void SparcV8TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4228 unsigned &NumAliases) const {
4229 Aliases = GCCRegAliases;
4230 NumAliases = llvm::array_lengthof(GCCRegAliases);
4232 } // end anonymous namespace.
4235 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
4237 AuroraUXSparcV8TargetInfo(const std::string& triple) :
4238 AuroraUXTargetInfo<SparcV8TargetInfo>(triple) {
4239 SizeType = UnsignedInt;
4240 PtrDiffType = SignedInt;
4243 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
4245 SolarisSparcV8TargetInfo(const std::string& triple) :
4246 SolarisTargetInfo<SparcV8TargetInfo>(triple) {
4247 SizeType = UnsignedInt;
4248 PtrDiffType = SignedInt;
4251 } // end anonymous namespace.
4254 class MSP430TargetInfo : public TargetInfo {
4255 static const char * const GCCRegNames[];
4257 MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) {
4259 TLSSupported = false;
4260 IntWidth = 16; IntAlign = 16;
4261 LongWidth = 32; LongLongWidth = 64;
4262 LongAlign = LongLongAlign = 16;
4263 PointerWidth = 16; PointerAlign = 16;
4265 SizeType = UnsignedInt;
4266 IntMaxType = SignedLong;
4267 UIntMaxType = UnsignedLong;
4268 IntPtrType = SignedShort;
4269 PtrDiffType = SignedInt;
4270 SigAtomicType = SignedLong;
4271 DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
4273 virtual void getTargetDefines(const LangOptions &Opts,
4274 MacroBuilder &Builder) const {
4275 Builder.defineMacro("MSP430");
4276 Builder.defineMacro("__MSP430__");
4277 // FIXME: defines for different 'flavours' of MCU
4279 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4280 unsigned &NumRecords) const {
4281 // FIXME: Implement.
4285 virtual bool hasFeature(StringRef Feature) const {
4286 return Feature == "msp430";
4288 virtual void getGCCRegNames(const char * const *&Names,
4289 unsigned &NumNames) const;
4290 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4291 unsigned &NumAliases) const {
4296 virtual bool validateAsmConstraint(const char *&Name,
4297 TargetInfo::ConstraintInfo &info) const {
4298 // No target constraints for now.
4301 virtual const char *getClobbers() const {
4302 // FIXME: Is this really right?
4305 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4307 return TargetInfo::CharPtrBuiltinVaList;
4311 const char * const MSP430TargetInfo::GCCRegNames[] = {
4312 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4313 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4316 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
4317 unsigned &NumNames) const {
4318 Names = GCCRegNames;
4319 NumNames = llvm::array_lengthof(GCCRegNames);
4325 // LLVM and Clang cannot be used directly to output native binaries for
4326 // target, but is used to compile C code to llvm bitcode with correct
4327 // type and alignment information.
4329 // TCE uses the llvm bitcode as input and uses it for generating customized
4330 // target processor and program binary. TCE co-design environment is
4331 // publicly available in http://tce.cs.tut.fi
4333 static const unsigned TCEOpenCLAddrSpaceMap[] = {
4336 5, // opencl_constant
4342 class TCETargetInfo : public TargetInfo{
4344 TCETargetInfo(const std::string& triple) : TargetInfo(triple) {
4345 TLSSupported = false;
4347 LongWidth = LongLongWidth = 32;
4350 LongAlign = LongLongAlign = 32;
4353 SizeType = UnsignedInt;
4354 IntMaxType = SignedLong;
4355 UIntMaxType = UnsignedLong;
4356 IntPtrType = SignedInt;
4357 PtrDiffType = SignedInt;
4362 LongDoubleWidth = 32;
4363 LongDoubleAlign = 32;
4364 FloatFormat = &llvm::APFloat::IEEEsingle;
4365 DoubleFormat = &llvm::APFloat::IEEEsingle;
4366 LongDoubleFormat = &llvm::APFloat::IEEEsingle;
4367 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
4368 "i16:16:32-i32:32:32-i64:32:32-"
4369 "f32:32:32-f64:32:32-v64:32:32-"
4370 "v128:32:32-a0:0:32-n32";
4371 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
4374 virtual void getTargetDefines(const LangOptions &Opts,
4375 MacroBuilder &Builder) const {
4376 DefineStd(Builder, "tce", Opts);
4377 Builder.defineMacro("__TCE__");
4378 Builder.defineMacro("__TCE_V1__");
4380 virtual bool hasFeature(StringRef Feature) const {
4381 return Feature == "tce";
4384 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4385 unsigned &NumRecords) const {}
4386 virtual const char *getClobbers() const {
4389 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4390 return TargetInfo::VoidPtrBuiltinVaList;
4392 virtual void getGCCRegNames(const char * const *&Names,
4393 unsigned &NumNames) const {}
4394 virtual bool validateAsmConstraint(const char *&Name,
4395 TargetInfo::ConstraintInfo &info) const {
4398 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4399 unsigned &NumAliases) const {}
4404 class MipsTargetInfoBase : public TargetInfo {
4405 static const Builtin::Info BuiltinInfo[];
4409 HardFloat, SingleFloat, SoftFloat
4419 MipsTargetInfoBase(const std::string& triple,
4420 const std::string& ABIStr,
4421 const std::string& CPUStr)
4422 : TargetInfo(triple),
4425 FloatABI(HardFloat),
4430 virtual const char *getABI() const { return ABI.c_str(); }
4431 virtual bool setABI(const std::string &Name) = 0;
4432 virtual bool setCPU(const std::string &Name) {
4436 void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4437 Features[ABI] = true;
4438 Features[CPU] = true;
4441 virtual void getTargetDefines(const LangOptions &Opts,
4442 MacroBuilder &Builder) const {
4443 DefineStd(Builder, "mips", Opts);
4444 Builder.defineMacro("_mips");
4445 Builder.defineMacro("__REGISTER_PREFIX__", "");
4449 Builder.defineMacro("__mips_hard_float", Twine(1));
4452 Builder.defineMacro("__mips_hard_float", Twine(1));
4453 Builder.defineMacro("__mips_single_float", Twine(1));
4456 Builder.defineMacro("__mips_soft_float", Twine(1));
4461 Builder.defineMacro("__mips16", Twine(1));
4467 Builder.defineMacro("__mips_dsp_rev", Twine(1));
4468 Builder.defineMacro("__mips_dsp", Twine(1));
4471 Builder.defineMacro("__mips_dsp_rev", Twine(2));
4472 Builder.defineMacro("__mips_dspr2", Twine(1));
4473 Builder.defineMacro("__mips_dsp", Twine(1));
4477 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
4478 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
4479 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
4481 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
4482 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
4485 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4486 unsigned &NumRecords) const {
4487 Records = BuiltinInfo;
4488 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
4490 virtual bool hasFeature(StringRef Feature) const {
4491 return Feature == "mips";
4493 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4494 return TargetInfo::VoidPtrBuiltinVaList;
4496 virtual void getGCCRegNames(const char * const *&Names,
4497 unsigned &NumNames) const {
4498 static const char * const GCCRegNames[] = {
4499 // CPU register names
4500 // Must match second column of GCCRegAliases
4501 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
4502 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
4503 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
4504 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
4505 // Floating point register names
4506 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
4507 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
4508 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
4509 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
4510 // Hi/lo and condition register names
4511 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
4512 "$fcc5","$fcc6","$fcc7"
4514 Names = GCCRegNames;
4515 NumNames = llvm::array_lengthof(GCCRegNames);
4517 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4518 unsigned &NumAliases) const = 0;
4519 virtual bool validateAsmConstraint(const char *&Name,
4520 TargetInfo::ConstraintInfo &Info) const {
4525 case 'r': // CPU registers.
4526 case 'd': // Equivalent to "r" unless generating MIPS16 code.
4527 case 'y': // Equivalent to "r", backwards compatibility only.
4528 case 'f': // floating-point registers.
4529 case 'c': // $25 for indirect jumps
4530 case 'l': // lo register
4531 case 'x': // hilo register pair
4532 Info.setAllowsRegister();
4534 case 'R': // An address that can be used in a non-macro load or store
4535 Info.setAllowsMemory();
4540 virtual const char *getClobbers() const {
4541 // FIXME: Implement!
4545 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4547 bool Enabled) const {
4548 if (Name == "soft-float" || Name == "single-float" ||
4549 Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" ||
4550 Name == "mips32" || Name == "mips32r2" ||
4551 Name == "mips64" || Name == "mips64r2" ||
4552 Name == "mips16" || Name == "dsp" || Name == "dspr2") {
4553 Features[Name] = Enabled;
4555 } else if (Name == "32") {
4556 Features["o32"] = Enabled;
4558 } else if (Name == "64") {
4559 Features["n64"] = Enabled;
4565 virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4567 FloatABI = HardFloat;
4570 for (std::vector<std::string>::iterator it = Features.begin(),
4571 ie = Features.end(); it != ie; ++it) {
4572 if (*it == "+single-float")
4573 FloatABI = SingleFloat;
4574 else if (*it == "+soft-float")
4575 FloatABI = SoftFloat;
4576 else if (*it == "+mips16")
4578 else if (*it == "+dsp")
4579 DspRev = std::max(DspRev, DSP1);
4580 else if (*it == "+dspr2")
4581 DspRev = std::max(DspRev, DSP2);
4584 // Remove front-end specific option.
4585 std::vector<std::string>::iterator it =
4586 std::find(Features.begin(), Features.end(), "+soft-float");
4587 if (it != Features.end())
4591 virtual int getEHDataRegisterNumber(unsigned RegNo) const {
4592 if (RegNo == 0) return 4;
4593 if (RegNo == 1) return 5;
4598 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
4599 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4600 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4602 #include "clang/Basic/BuiltinsMips.def"
4605 class Mips32TargetInfoBase : public MipsTargetInfoBase {
4607 Mips32TargetInfoBase(const std::string& triple) :
4608 MipsTargetInfoBase(triple, "o32", "mips32") {
4609 SizeType = UnsignedInt;
4610 PtrDiffType = SignedInt;
4611 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
4613 virtual bool setABI(const std::string &Name) {
4614 if ((Name == "o32") || (Name == "eabi")) {
4617 } else if (Name == "32") {
4623 virtual void getTargetDefines(const LangOptions &Opts,
4624 MacroBuilder &Builder) const {
4625 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4628 Builder.defineMacro("__mips_o32");
4629 Builder.defineMacro("_ABIO32", "1");
4630 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
4632 else if (ABI == "eabi")
4633 Builder.defineMacro("__mips_eabi");
4635 llvm_unreachable("Invalid ABI for Mips32.");
4637 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4638 unsigned &NumAliases) const {
4639 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4649 { { "t2" }, "$10" },
4650 { { "t3" }, "$11" },
4651 { { "t4" }, "$12" },
4652 { { "t5" }, "$13" },
4653 { { "t6" }, "$14" },
4654 { { "t7" }, "$15" },
4655 { { "s0" }, "$16" },
4656 { { "s1" }, "$17" },
4657 { { "s2" }, "$18" },
4658 { { "s3" }, "$19" },
4659 { { "s4" }, "$20" },
4660 { { "s5" }, "$21" },
4661 { { "s6" }, "$22" },
4662 { { "s7" }, "$23" },
4663 { { "t8" }, "$24" },
4664 { { "t9" }, "$25" },
4665 { { "k0" }, "$26" },
4666 { { "k1" }, "$27" },
4667 { { "gp" }, "$28" },
4668 { { "sp","$sp" }, "$29" },
4669 { { "fp","$fp" }, "$30" },
4672 Aliases = GCCRegAliases;
4673 NumAliases = llvm::array_lengthof(GCCRegAliases);
4677 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
4679 Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4680 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4681 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4683 virtual void getTargetDefines(const LangOptions &Opts,
4684 MacroBuilder &Builder) const {
4685 DefineStd(Builder, "MIPSEB", Opts);
4686 Builder.defineMacro("_MIPSEB");
4687 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4691 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
4693 Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4695 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4696 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4698 virtual void getTargetDefines(const LangOptions &Opts,
4699 MacroBuilder &Builder) const {
4700 DefineStd(Builder, "MIPSEL", Opts);
4701 Builder.defineMacro("_MIPSEL");
4702 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4706 class Mips64TargetInfoBase : public MipsTargetInfoBase {
4707 virtual void SetDescriptionString(const std::string &Name) = 0;
4709 Mips64TargetInfoBase(const std::string& triple) :
4710 MipsTargetInfoBase(triple, "n64", "mips64") {
4711 LongWidth = LongAlign = 64;
4712 PointerWidth = PointerAlign = 64;
4713 LongDoubleWidth = LongDoubleAlign = 128;
4714 LongDoubleFormat = &llvm::APFloat::IEEEquad;
4715 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
4716 LongDoubleWidth = LongDoubleAlign = 64;
4717 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4719 SuitableAlign = 128;
4720 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4722 virtual bool setABI(const std::string &Name) {
4723 SetDescriptionString(Name);
4724 if (Name == "n32") {
4725 LongWidth = LongAlign = 32;
4726 PointerWidth = PointerAlign = 32;
4729 } else if (Name == "n64") {
4732 } else if (Name == "64") {
4738 virtual void getTargetDefines(const LangOptions &Opts,
4739 MacroBuilder &Builder) const {
4740 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4742 Builder.defineMacro("__mips64");
4743 Builder.defineMacro("__mips64__");
4746 Builder.defineMacro("__mips_n32");
4747 Builder.defineMacro("_ABIN32", "2");
4748 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
4750 else if (ABI == "n64") {
4751 Builder.defineMacro("__mips_n64");
4752 Builder.defineMacro("_ABI64", "3");
4753 Builder.defineMacro("_MIPS_SIM", "_ABI64");
4756 llvm_unreachable("Invalid ABI for Mips64.");
4758 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4759 unsigned &NumAliases) const {
4760 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4770 { { "a6" }, "$10" },
4771 { { "a7" }, "$11" },
4772 { { "t0" }, "$12" },
4773 { { "t1" }, "$13" },
4774 { { "t2" }, "$14" },
4775 { { "t3" }, "$15" },
4776 { { "s0" }, "$16" },
4777 { { "s1" }, "$17" },
4778 { { "s2" }, "$18" },
4779 { { "s3" }, "$19" },
4780 { { "s4" }, "$20" },
4781 { { "s5" }, "$21" },
4782 { { "s6" }, "$22" },
4783 { { "s7" }, "$23" },
4784 { { "t8" }, "$24" },
4785 { { "t9" }, "$25" },
4786 { { "k0" }, "$26" },
4787 { { "k1" }, "$27" },
4788 { { "gp" }, "$28" },
4789 { { "sp","$sp" }, "$29" },
4790 { { "fp","$fp" }, "$30" },
4793 Aliases = GCCRegAliases;
4794 NumAliases = llvm::array_lengthof(GCCRegAliases);
4798 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
4799 virtual void SetDescriptionString(const std::string &Name) {
4800 // Change DescriptionString only if ABI is n32.
4802 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4803 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4804 "v64:64:64-n32:64-S128";
4807 Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
4808 // Default ABI is n64.
4809 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4810 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4811 "v64:64:64-n32:64-S128";
4813 virtual void getTargetDefines(const LangOptions &Opts,
4814 MacroBuilder &Builder) const {
4815 DefineStd(Builder, "MIPSEB", Opts);
4816 Builder.defineMacro("_MIPSEB");
4817 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
4821 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
4822 virtual void SetDescriptionString(const std::string &Name) {
4823 // Change DescriptionString only if ABI is n32.
4825 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4826 "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
4827 "-v64:64:64-n32:64-S128";
4830 Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
4831 // Default ABI is n64.
4833 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4834 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4835 "v64:64:64-n32:64-S128";
4837 virtual void getTargetDefines(const LangOptions &Opts,
4838 MacroBuilder &Builder) const {
4839 DefineStd(Builder, "MIPSEL", Opts);
4840 Builder.defineMacro("_MIPSEL");
4841 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
4844 } // end anonymous namespace.
4847 class PNaClTargetInfo : public TargetInfo {
4849 PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) {
4851 this->UserLabelPrefix = "";
4852 this->LongAlign = 32;
4853 this->LongWidth = 32;
4854 this->PointerAlign = 32;
4855 this->PointerWidth = 32;
4856 this->IntMaxType = TargetInfo::SignedLongLong;
4857 this->UIntMaxType = TargetInfo::UnsignedLongLong;
4858 this->Int64Type = TargetInfo::SignedLongLong;
4859 this->DoubleAlign = 64;
4860 this->LongDoubleWidth = 64;
4861 this->LongDoubleAlign = 64;
4862 this->SizeType = TargetInfo::UnsignedInt;
4863 this->PtrDiffType = TargetInfo::SignedInt;
4864 this->IntPtrType = TargetInfo::SignedInt;
4865 this->RegParmMax = 2;
4866 DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
4867 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
4870 void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4872 virtual void getArchDefines(const LangOptions &Opts,
4873 MacroBuilder &Builder) const {
4874 Builder.defineMacro("__le32__");
4875 Builder.defineMacro("__pnacl__");
4877 virtual void getTargetDefines(const LangOptions &Opts,
4878 MacroBuilder &Builder) const {
4879 Builder.defineMacro("__LITTLE_ENDIAN__");
4880 getArchDefines(Opts, Builder);
4882 virtual bool hasFeature(StringRef Feature) const {
4883 return Feature == "pnacl";
4885 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4886 unsigned &NumRecords) const {
4888 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4889 return TargetInfo::PNaClABIBuiltinVaList;
4891 virtual void getGCCRegNames(const char * const *&Names,
4892 unsigned &NumNames) const;
4893 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4894 unsigned &NumAliases) const;
4895 virtual bool validateAsmConstraint(const char *&Name,
4896 TargetInfo::ConstraintInfo &Info) const {
4900 virtual const char *getClobbers() const {
4905 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
4906 unsigned &NumNames) const {
4911 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4912 unsigned &NumAliases) const {
4916 } // end anonymous namespace.
4919 static const unsigned SPIRAddrSpaceMap[] = {
4922 2, // opencl_constant
4927 class SPIRTargetInfo : public TargetInfo {
4928 static const char * const GCCRegNames[];
4929 static const Builtin::Info BuiltinInfo[];
4930 std::vector<StringRef> AvailableFeatures;
4932 SPIRTargetInfo(const std::string& triple) : TargetInfo(triple) {
4933 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
4934 "SPIR target must use unknown OS");
4935 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
4936 "SPIR target must use unknown environment type");
4938 TLSSupported = false;
4939 LongWidth = LongAlign = 64;
4940 AddrSpaceMap = &SPIRAddrSpaceMap;
4941 // Define available target features
4942 // These must be defined in sorted order!
4943 NoAsmVariants = true;
4945 virtual void getTargetDefines(const LangOptions &Opts,
4946 MacroBuilder &Builder) const {
4947 DefineStd(Builder, "SPIR", Opts);
4949 virtual bool hasFeature(StringRef Feature) const {
4950 return Feature == "spir";
4953 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4954 unsigned &NumRecords) const {}
4955 virtual const char *getClobbers() const {
4958 virtual void getGCCRegNames(const char * const *&Names,
4959 unsigned &NumNames) const {}
4960 virtual bool validateAsmConstraint(const char *&Name,
4961 TargetInfo::ConstraintInfo &info) const {
4964 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4965 unsigned &NumAliases) const {}
4966 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4967 return TargetInfo::VoidPtrBuiltinVaList;
4972 class SPIR32TargetInfo : public SPIRTargetInfo {
4974 SPIR32TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
4975 PointerWidth = PointerAlign = 32;
4976 SizeType = TargetInfo::UnsignedInt;
4977 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
4979 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
4980 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
4981 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
4982 "v512:512:512-v1024:1024:1024";
4984 virtual void getTargetDefines(const LangOptions &Opts,
4985 MacroBuilder &Builder) const {
4986 DefineStd(Builder, "SPIR32", Opts);
4990 class SPIR64TargetInfo : public SPIRTargetInfo {
4992 SPIR64TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
4993 PointerWidth = PointerAlign = 64;
4994 SizeType = TargetInfo::UnsignedLong;
4995 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
4997 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
4998 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
4999 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5000 "v512:512:512-v1024:1024:1024";
5002 virtual void getTargetDefines(const LangOptions &Opts,
5003 MacroBuilder &Builder) const {
5004 DefineStd(Builder, "SPIR64", Opts);
5010 //===----------------------------------------------------------------------===//
5012 //===----------------------------------------------------------------------===//
5014 static TargetInfo *AllocateTarget(const std::string &T) {
5015 llvm::Triple Triple(T);
5016 llvm::Triple::OSType os = Triple.getOS();
5018 switch (Triple.getArch()) {
5022 case llvm::Triple::hexagon:
5023 return new HexagonTargetInfo(T);
5025 case llvm::Triple::aarch64:
5027 case llvm::Triple::Linux:
5028 return new LinuxTargetInfo<AArch64TargetInfo>(T);
5030 return new AArch64TargetInfo(T);
5033 case llvm::Triple::arm:
5034 case llvm::Triple::thumb:
5035 if (Triple.isOSDarwin())
5036 return new DarwinARMTargetInfo(T);
5039 case llvm::Triple::Linux:
5040 return new LinuxTargetInfo<ARMTargetInfo>(T);
5041 case llvm::Triple::FreeBSD:
5042 return new FreeBSDTargetInfo<ARMTargetInfo>(T);
5043 case llvm::Triple::NetBSD:
5044 return new NetBSDTargetInfo<ARMTargetInfo>(T);
5045 case llvm::Triple::OpenBSD:
5046 return new OpenBSDTargetInfo<ARMTargetInfo>(T);
5047 case llvm::Triple::Bitrig:
5048 return new BitrigTargetInfo<ARMTargetInfo>(T);
5049 case llvm::Triple::RTEMS:
5050 return new RTEMSTargetInfo<ARMTargetInfo>(T);
5051 case llvm::Triple::NaCl:
5052 return new NaClTargetInfo<ARMTargetInfo>(T);
5054 return new ARMTargetInfo(T);
5057 case llvm::Triple::msp430:
5058 return new MSP430TargetInfo(T);
5060 case llvm::Triple::mips:
5062 case llvm::Triple::Linux:
5063 return new LinuxTargetInfo<Mips32EBTargetInfo>(T);
5064 case llvm::Triple::RTEMS:
5065 return new RTEMSTargetInfo<Mips32EBTargetInfo>(T);
5066 case llvm::Triple::FreeBSD:
5067 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T);
5068 case llvm::Triple::NetBSD:
5069 return new NetBSDTargetInfo<Mips32EBTargetInfo>(T);
5071 return new Mips32EBTargetInfo(T);
5074 case llvm::Triple::mipsel:
5076 case llvm::Triple::Linux:
5077 return new LinuxTargetInfo<Mips32ELTargetInfo>(T);
5078 case llvm::Triple::RTEMS:
5079 return new RTEMSTargetInfo<Mips32ELTargetInfo>(T);
5080 case llvm::Triple::FreeBSD:
5081 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T);
5082 case llvm::Triple::NetBSD:
5083 return new NetBSDTargetInfo<Mips32ELTargetInfo>(T);
5085 return new Mips32ELTargetInfo(T);
5088 case llvm::Triple::mips64:
5090 case llvm::Triple::Linux:
5091 return new LinuxTargetInfo<Mips64EBTargetInfo>(T);
5092 case llvm::Triple::RTEMS:
5093 return new RTEMSTargetInfo<Mips64EBTargetInfo>(T);
5094 case llvm::Triple::FreeBSD:
5095 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T);
5096 case llvm::Triple::NetBSD:
5097 return new NetBSDTargetInfo<Mips64EBTargetInfo>(T);
5098 case llvm::Triple::OpenBSD:
5099 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(T);
5101 return new Mips64EBTargetInfo(T);
5104 case llvm::Triple::mips64el:
5106 case llvm::Triple::Linux:
5107 return new LinuxTargetInfo<Mips64ELTargetInfo>(T);
5108 case llvm::Triple::RTEMS:
5109 return new RTEMSTargetInfo<Mips64ELTargetInfo>(T);
5110 case llvm::Triple::FreeBSD:
5111 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T);
5112 case llvm::Triple::NetBSD:
5113 return new NetBSDTargetInfo<Mips64ELTargetInfo>(T);
5114 case llvm::Triple::OpenBSD:
5115 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(T);
5117 return new Mips64ELTargetInfo(T);
5120 case llvm::Triple::le32:
5122 case llvm::Triple::NaCl:
5123 return new NaClTargetInfo<PNaClTargetInfo>(T);
5128 case llvm::Triple::ppc:
5129 if (Triple.isOSDarwin())
5130 return new DarwinPPC32TargetInfo(T);
5132 case llvm::Triple::Linux:
5133 return new LinuxTargetInfo<PPC32TargetInfo>(T);
5134 case llvm::Triple::FreeBSD:
5135 return new FreeBSDTargetInfo<PPC32TargetInfo>(T);
5136 case llvm::Triple::NetBSD:
5137 return new NetBSDTargetInfo<PPC32TargetInfo>(T);
5138 case llvm::Triple::OpenBSD:
5139 return new OpenBSDTargetInfo<PPC32TargetInfo>(T);
5140 case llvm::Triple::RTEMS:
5141 return new RTEMSTargetInfo<PPC32TargetInfo>(T);
5143 return new PPC32TargetInfo(T);
5146 case llvm::Triple::ppc64:
5147 if (Triple.isOSDarwin())
5148 return new DarwinPPC64TargetInfo(T);
5150 case llvm::Triple::Linux:
5151 return new LinuxTargetInfo<PPC64TargetInfo>(T);
5152 case llvm::Triple::Lv2:
5153 return new PS3PPUTargetInfo<PPC64TargetInfo>(T);
5154 case llvm::Triple::FreeBSD:
5155 return new FreeBSDTargetInfo<PPC64TargetInfo>(T);
5156 case llvm::Triple::NetBSD:
5157 return new NetBSDTargetInfo<PPC64TargetInfo>(T);
5159 return new PPC64TargetInfo(T);
5162 case llvm::Triple::nvptx:
5163 return new NVPTX32TargetInfo(T);
5164 case llvm::Triple::nvptx64:
5165 return new NVPTX64TargetInfo(T);
5167 case llvm::Triple::mblaze:
5168 return new MBlazeTargetInfo(T);
5170 case llvm::Triple::r600:
5171 return new R600TargetInfo(T);
5173 case llvm::Triple::sparc:
5175 case llvm::Triple::Linux:
5176 return new LinuxTargetInfo<SparcV8TargetInfo>(T);
5177 case llvm::Triple::AuroraUX:
5178 return new AuroraUXSparcV8TargetInfo(T);
5179 case llvm::Triple::Solaris:
5180 return new SolarisSparcV8TargetInfo(T);
5181 case llvm::Triple::NetBSD:
5182 return new NetBSDTargetInfo<SparcV8TargetInfo>(T);
5183 case llvm::Triple::OpenBSD:
5184 return new OpenBSDTargetInfo<SparcV8TargetInfo>(T);
5185 case llvm::Triple::RTEMS:
5186 return new RTEMSTargetInfo<SparcV8TargetInfo>(T);
5188 return new SparcV8TargetInfo(T);
5191 case llvm::Triple::tce:
5192 return new TCETargetInfo(T);
5194 case llvm::Triple::x86:
5195 if (Triple.isOSDarwin())
5196 return new DarwinI386TargetInfo(T);
5199 case llvm::Triple::AuroraUX:
5200 return new AuroraUXTargetInfo<X86_32TargetInfo>(T);
5201 case llvm::Triple::Linux:
5202 return new LinuxTargetInfo<X86_32TargetInfo>(T);
5203 case llvm::Triple::DragonFly:
5204 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T);
5205 case llvm::Triple::NetBSD:
5206 return new NetBSDI386TargetInfo(T);
5207 case llvm::Triple::OpenBSD:
5208 return new OpenBSDI386TargetInfo(T);
5209 case llvm::Triple::Bitrig:
5210 return new BitrigI386TargetInfo(T);
5211 case llvm::Triple::FreeBSD:
5212 return new FreeBSDTargetInfo<X86_32TargetInfo>(T);
5213 case llvm::Triple::Minix:
5214 return new MinixTargetInfo<X86_32TargetInfo>(T);
5215 case llvm::Triple::Solaris:
5216 return new SolarisTargetInfo<X86_32TargetInfo>(T);
5217 case llvm::Triple::Cygwin:
5218 return new CygwinX86_32TargetInfo(T);
5219 case llvm::Triple::MinGW32:
5220 return new MinGWX86_32TargetInfo(T);
5221 case llvm::Triple::Win32:
5222 return new VisualStudioWindowsX86_32TargetInfo(T);
5223 case llvm::Triple::Haiku:
5224 return new HaikuX86_32TargetInfo(T);
5225 case llvm::Triple::RTEMS:
5226 return new RTEMSX86_32TargetInfo(T);
5227 case llvm::Triple::NaCl:
5228 return new NaClTargetInfo<X86_32TargetInfo>(T);
5230 return new X86_32TargetInfo(T);
5233 case llvm::Triple::x86_64:
5234 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
5235 return new DarwinX86_64TargetInfo(T);
5238 case llvm::Triple::AuroraUX:
5239 return new AuroraUXTargetInfo<X86_64TargetInfo>(T);
5240 case llvm::Triple::Linux:
5241 return new LinuxTargetInfo<X86_64TargetInfo>(T);
5242 case llvm::Triple::DragonFly:
5243 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T);
5244 case llvm::Triple::NetBSD:
5245 return new NetBSDTargetInfo<X86_64TargetInfo>(T);
5246 case llvm::Triple::OpenBSD:
5247 return new OpenBSDX86_64TargetInfo(T);
5248 case llvm::Triple::Bitrig:
5249 return new BitrigX86_64TargetInfo(T);
5250 case llvm::Triple::FreeBSD:
5251 return new FreeBSDTargetInfo<X86_64TargetInfo>(T);
5252 case llvm::Triple::Solaris:
5253 return new SolarisTargetInfo<X86_64TargetInfo>(T);
5254 case llvm::Triple::MinGW32:
5255 return new MinGWX86_64TargetInfo(T);
5256 case llvm::Triple::Win32: // This is what Triple.h supports now.
5257 return new VisualStudioWindowsX86_64TargetInfo(T);
5258 case llvm::Triple::NaCl:
5259 return new NaClTargetInfo<X86_64TargetInfo>(T);
5261 return new X86_64TargetInfo(T);
5264 case llvm::Triple::spir: {
5265 llvm::Triple Triple(T);
5266 if (Triple.getOS() != llvm::Triple::UnknownOS ||
5267 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5269 return new SPIR32TargetInfo(T);
5271 case llvm::Triple::spir64: {
5272 llvm::Triple Triple(T);
5273 if (Triple.getOS() != llvm::Triple::UnknownOS ||
5274 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5276 return new SPIR64TargetInfo(T);
5281 /// CreateTargetInfo - Return the target info object for the specified target
5283 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
5284 TargetOptions *Opts) {
5285 llvm::Triple Triple(Opts->Triple);
5287 // Construct the target
5288 OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str()));
5290 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
5293 Target->setTargetOpts(Opts);
5295 // Set the target CPU if specified.
5296 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
5297 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
5301 // Set the target ABI if specified.
5302 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
5303 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
5307 // Set the target C++ ABI.
5308 if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) {
5309 Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI;
5313 // Compute the default target features, we need the target to handle this
5314 // because features may have dependencies on one another.
5315 llvm::StringMap<bool> Features;
5316 Target->getDefaultFeatures(Features);
5318 // Apply the user specified deltas.
5319 // First the enables.
5320 for (std::vector<std::string>::const_iterator
5321 it = Opts->FeaturesAsWritten.begin(),
5322 ie = Opts->FeaturesAsWritten.end();
5324 const char *Name = it->c_str();
5329 // Apply the feature via the target.
5330 if (!Target->setFeatureEnabled(Features, Name + 1, true)) {
5331 Diags.Report(diag::err_target_invalid_feature) << Name;
5336 // Then the disables.
5337 for (std::vector<std::string>::const_iterator
5338 it = Opts->FeaturesAsWritten.begin(),
5339 ie = Opts->FeaturesAsWritten.end();
5341 const char *Name = it->c_str();
5346 // Apply the feature via the target.
5347 if (Name[0] != '-' ||
5348 !Target->setFeatureEnabled(Features, Name + 1, false)) {
5349 Diags.Report(diag::err_target_invalid_feature) << Name;
5354 // Add the features to the compile options.
5356 // FIXME: If we are completely confident that we have the right set, we only
5357 // need to pass the minuses.
5358 Opts->Features.clear();
5359 for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
5360 ie = Features.end(); it != ie; ++it)
5361 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
5362 Target->HandleTargetFeatures(Opts->Features);
5364 return Target.take();