1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/MC/MCSectionMachO.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/TargetParser.h"
33 using namespace clang;
35 //===----------------------------------------------------------------------===//
36 // Common code shared among targets.
37 //===----------------------------------------------------------------------===//
39 /// DefineStd - Define a macro name and standard variants. For example if
40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
43 const LangOptions &Opts) {
44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
47 // in the user's namespace.
49 Builder.defineMacro(MacroName);
52 Builder.defineMacro("__" + MacroName);
55 Builder.defineMacro("__" + MacroName + "__");
58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
60 Builder.defineMacro("__" + CPUName);
61 Builder.defineMacro("__" + CPUName + "__");
63 Builder.defineMacro("__tune_" + CPUName + "__");
66 //===----------------------------------------------------------------------===//
67 // Defines specific to certain operating systems.
68 //===----------------------------------------------------------------------===//
71 template<typename TgtInfo>
72 class OSTargetInfo : public TgtInfo {
74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
75 MacroBuilder &Builder) const=0;
77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
78 void getTargetDefines(const LangOptions &Opts,
79 MacroBuilder &Builder) const override {
80 TgtInfo::getTargetDefines(Opts, Builder);
81 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
85 } // end anonymous namespace
88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
89 const llvm::Triple &Triple,
90 StringRef &PlatformName,
91 VersionTuple &PlatformMinVersion) {
92 Builder.defineMacro("__APPLE_CC__", "6000");
93 Builder.defineMacro("__APPLE__");
94 Builder.defineMacro("OBJC_NEW_PROPERTIES");
95 // AddressSanitizer doesn't play well with source fortification, which is on
96 // by default on Darwin.
97 if (Opts.Sanitize.has(SanitizerKind::Address))
98 Builder.defineMacro("_FORTIFY_SOURCE", "0");
100 if (!Opts.ObjCAutoRefCount) {
101 // __weak is always defined, for use in blocks and with objc pointers.
102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
104 // Darwin defines __strong even in C mode (just to nothing).
105 if (Opts.getGC() != LangOptions::NonGC)
106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
108 Builder.defineMacro("__strong", "");
110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even
111 // allow this in C, since one might have block pointers in structs that
112 // are used in pure C code and in Objective-C ARC.
113 Builder.defineMacro("__unsafe_unretained", "");
117 Builder.defineMacro("__STATIC__");
119 Builder.defineMacro("__DYNAMIC__");
121 if (Opts.POSIXThreads)
122 Builder.defineMacro("_REENTRANT");
124 // Get the platform type and version number from the triple.
125 unsigned Maj, Min, Rev;
126 if (Triple.isMacOSX()) {
127 Triple.getMacOSXVersion(Maj, Min, Rev);
128 PlatformName = "macosx";
130 Triple.getOSVersion(Maj, Min, Rev);
131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
134 // If -target arch-pc-win32-macho option specified, we're
135 // generating code for Win32 ABI. No need to emit
136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
137 if (PlatformName == "win32") {
138 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
142 // Set the appropriate OS version define.
143 if (Triple.isiOS()) {
144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
147 Str[1] = '0' + (Min / 10);
148 Str[2] = '0' + (Min % 10);
149 Str[3] = '0' + (Rev / 10);
150 Str[4] = '0' + (Rev % 10);
152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
154 } else if (Triple.isMacOSX()) {
155 // Note that the Driver allows versions which aren't representable in the
156 // define (because we only get a single digit for the minor and micro
157 // revision numbers). So, we limit them to the maximum representable
159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
161 if (Maj < 10 || (Maj == 10 && Min < 10)) {
162 Str[0] = '0' + (Maj / 10);
163 Str[1] = '0' + (Maj % 10);
164 Str[2] = '0' + std::min(Min, 9U);
165 Str[3] = '0' + std::min(Rev, 9U);
168 // Handle versions > 10.9.
169 Str[0] = '0' + (Maj / 10);
170 Str[1] = '0' + (Maj % 10);
171 Str[2] = '0' + (Min / 10);
172 Str[3] = '0' + (Min % 10);
173 Str[4] = '0' + (Rev / 10);
174 Str[5] = '0' + (Rev % 10);
177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
180 // Tell users about the kernel if there is one.
181 if (Triple.isOSDarwin())
182 Builder.defineMacro("__MACH__");
184 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
189 template <typename Target>
190 class CloudABITargetInfo : public OSTargetInfo<Target> {
192 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
193 MacroBuilder &Builder) const override {
194 Builder.defineMacro("__CloudABI__");
195 Builder.defineMacro("__ELF__");
197 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
198 Builder.defineMacro("__STDC_ISO_10646__", "201206L");
199 Builder.defineMacro("__STDC_UTF_16__");
200 Builder.defineMacro("__STDC_UTF_32__");
204 CloudABITargetInfo(const llvm::Triple &Triple)
205 : OSTargetInfo<Target>(Triple) {
206 this->UserLabelPrefix = "";
210 template<typename Target>
211 class DarwinTargetInfo : public OSTargetInfo<Target> {
213 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
214 MacroBuilder &Builder) const override {
215 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
216 this->PlatformMinVersion);
220 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
221 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
222 this->MCountName = "\01mcount";
225 std::string isValidSectionSpecifier(StringRef SR) const override {
226 // Let MCSectionMachO validate this.
227 StringRef Segment, Section;
228 unsigned TAA, StubSize;
230 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
231 TAA, HasTAA, StubSize);
234 const char *getStaticInitSectionSpecifier() const override {
235 // FIXME: We should return 0 when building kexts.
236 return "__TEXT,__StaticInit,regular,pure_instructions";
239 /// Darwin does not support protected visibility. Darwin's "default"
240 /// is very similar to ELF's "protected"; Darwin requires a "weak"
241 /// attribute on declarations that can be dynamically replaced.
242 bool hasProtectedVisibility() const override {
248 // DragonFlyBSD Target
249 template<typename Target>
250 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
252 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
253 MacroBuilder &Builder) const override {
254 // DragonFly defines; list based off of gcc output
255 Builder.defineMacro("__DragonFly__");
256 Builder.defineMacro("__DragonFly_cc_version", "100001");
257 Builder.defineMacro("__ELF__");
258 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
259 Builder.defineMacro("__tune_i386__");
260 DefineStd(Builder, "unix", Opts);
263 DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
264 : OSTargetInfo<Target>(Triple) {
265 this->UserLabelPrefix = "";
267 switch (Triple.getArch()) {
269 case llvm::Triple::x86:
270 case llvm::Triple::x86_64:
271 this->MCountName = ".mcount";
278 template<typename Target>
279 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
281 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
282 MacroBuilder &Builder) const override {
283 // FreeBSD defines; list based off of gcc output
285 unsigned Release = Triple.getOSMajorVersion();
289 Builder.defineMacro("__FreeBSD__", Twine(Release));
290 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
291 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
292 DefineStd(Builder, "unix", Opts);
293 Builder.defineMacro("__ELF__");
295 // On FreeBSD, wchar_t contains the number of the code point as
296 // used by the character set of the locale. These character sets are
297 // not necessarily a superset of ASCII.
299 // FIXME: This is wrong; the macro refers to the numerical values
300 // of wchar_t *literals*, which are not locale-dependent. However,
301 // FreeBSD systems apparently depend on us getting this wrong, and
302 // setting this to 1 is conforming even if all the basic source
303 // character literals have the same encoding as char and wchar_t.
304 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
307 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
308 this->UserLabelPrefix = "";
310 switch (Triple.getArch()) {
312 case llvm::Triple::x86:
313 case llvm::Triple::x86_64:
314 this->MCountName = ".mcount";
316 case llvm::Triple::mips:
317 case llvm::Triple::mipsel:
318 case llvm::Triple::ppc:
319 case llvm::Triple::ppc64:
320 case llvm::Triple::ppc64le:
321 this->MCountName = "_mcount";
323 case llvm::Triple::arm:
324 this->MCountName = "__mcount";
330 // GNU/kFreeBSD Target
331 template<typename Target>
332 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
334 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
335 MacroBuilder &Builder) const override {
336 // GNU/kFreeBSD defines; list based off of gcc output
338 DefineStd(Builder, "unix", Opts);
339 Builder.defineMacro("__FreeBSD_kernel__");
340 Builder.defineMacro("__GLIBC__");
341 Builder.defineMacro("__ELF__");
342 if (Opts.POSIXThreads)
343 Builder.defineMacro("_REENTRANT");
345 Builder.defineMacro("_GNU_SOURCE");
348 KFreeBSDTargetInfo(const llvm::Triple &Triple)
349 : OSTargetInfo<Target>(Triple) {
350 this->UserLabelPrefix = "";
355 template<typename Target>
356 class MinixTargetInfo : public OSTargetInfo<Target> {
358 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
359 MacroBuilder &Builder) const override {
362 Builder.defineMacro("__minix", "3");
363 Builder.defineMacro("_EM_WSIZE", "4");
364 Builder.defineMacro("_EM_PSIZE", "4");
365 Builder.defineMacro("_EM_SSIZE", "2");
366 Builder.defineMacro("_EM_LSIZE", "4");
367 Builder.defineMacro("_EM_FSIZE", "4");
368 Builder.defineMacro("_EM_DSIZE", "8");
369 Builder.defineMacro("__ELF__");
370 DefineStd(Builder, "unix", Opts);
373 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
374 this->UserLabelPrefix = "";
379 template<typename Target>
380 class LinuxTargetInfo : public OSTargetInfo<Target> {
382 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
383 MacroBuilder &Builder) const override {
384 // Linux defines; list based off of gcc output
385 DefineStd(Builder, "unix", Opts);
386 DefineStd(Builder, "linux", Opts);
387 Builder.defineMacro("__gnu_linux__");
388 Builder.defineMacro("__ELF__");
389 if (Triple.getEnvironment() == llvm::Triple::Android) {
390 Builder.defineMacro("__ANDROID__", "1");
391 unsigned Maj, Min, Rev;
392 Triple.getOSVersion(Maj, Min, Rev);
393 this->PlatformName = "android";
394 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
396 if (Opts.POSIXThreads)
397 Builder.defineMacro("_REENTRANT");
399 Builder.defineMacro("_GNU_SOURCE");
402 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
403 this->UserLabelPrefix = "";
404 this->WIntType = TargetInfo::UnsignedInt;
406 switch (Triple.getArch()) {
409 case llvm::Triple::ppc:
410 case llvm::Triple::ppc64:
411 case llvm::Triple::ppc64le:
412 this->MCountName = "_mcount";
417 const char *getStaticInitSectionSpecifier() const override {
418 return ".text.startup";
423 template<typename Target>
424 class NetBSDTargetInfo : public OSTargetInfo<Target> {
426 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
427 MacroBuilder &Builder) const override {
428 // NetBSD defines; list based off of gcc output
429 Builder.defineMacro("__NetBSD__");
430 Builder.defineMacro("__unix__");
431 Builder.defineMacro("__ELF__");
432 if (Opts.POSIXThreads)
433 Builder.defineMacro("_POSIX_THREADS");
435 switch (Triple.getArch()) {
438 case llvm::Triple::arm:
439 case llvm::Triple::armeb:
440 case llvm::Triple::thumb:
441 case llvm::Triple::thumbeb:
442 Builder.defineMacro("__ARM_DWARF_EH__");
447 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
448 this->UserLabelPrefix = "";
449 this->MCountName = "_mcount";
454 template<typename Target>
455 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
457 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
458 MacroBuilder &Builder) const override {
459 // OpenBSD defines; list based off of gcc output
461 Builder.defineMacro("__OpenBSD__");
462 DefineStd(Builder, "unix", Opts);
463 Builder.defineMacro("__ELF__");
464 if (Opts.POSIXThreads)
465 Builder.defineMacro("_REENTRANT");
468 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
469 this->UserLabelPrefix = "";
470 this->TLSSupported = false;
472 switch (Triple.getArch()) {
474 case llvm::Triple::x86:
475 case llvm::Triple::x86_64:
476 case llvm::Triple::arm:
477 case llvm::Triple::sparc:
478 this->MCountName = "__mcount";
480 case llvm::Triple::mips64:
481 case llvm::Triple::mips64el:
482 case llvm::Triple::ppc:
483 case llvm::Triple::sparcv9:
484 this->MCountName = "_mcount";
491 template<typename Target>
492 class BitrigTargetInfo : public OSTargetInfo<Target> {
494 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495 MacroBuilder &Builder) const override {
496 // Bitrig defines; list based off of gcc output
498 Builder.defineMacro("__Bitrig__");
499 DefineStd(Builder, "unix", Opts);
500 Builder.defineMacro("__ELF__");
501 if (Opts.POSIXThreads)
502 Builder.defineMacro("_REENTRANT");
504 switch (Triple.getArch()) {
507 case llvm::Triple::arm:
508 case llvm::Triple::armeb:
509 case llvm::Triple::thumb:
510 case llvm::Triple::thumbeb:
511 Builder.defineMacro("__ARM_DWARF_EH__");
516 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
517 this->UserLabelPrefix = "";
518 this->MCountName = "__mcount";
523 template<typename Target>
524 class PSPTargetInfo : public OSTargetInfo<Target> {
526 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
527 MacroBuilder &Builder) const override {
528 // PSP defines; list based on the output of the pspdev gcc toolchain.
529 Builder.defineMacro("PSP");
530 Builder.defineMacro("_PSP");
531 Builder.defineMacro("__psp__");
532 Builder.defineMacro("__ELF__");
535 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
536 this->UserLabelPrefix = "";
541 template<typename Target>
542 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
544 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
545 MacroBuilder &Builder) const override {
547 Builder.defineMacro("__PPC__");
548 Builder.defineMacro("__PPU__");
549 Builder.defineMacro("__CELLOS_LV2__");
550 Builder.defineMacro("__ELF__");
551 Builder.defineMacro("__LP32__");
552 Builder.defineMacro("_ARCH_PPC64");
553 Builder.defineMacro("__powerpc64__");
556 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
557 this->UserLabelPrefix = "";
558 this->LongWidth = this->LongAlign = 32;
559 this->PointerWidth = this->PointerAlign = 32;
560 this->IntMaxType = TargetInfo::SignedLongLong;
561 this->Int64Type = TargetInfo::SignedLongLong;
562 this->SizeType = TargetInfo::UnsignedInt;
563 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
567 template <typename Target>
568 class PS4OSTargetInfo : public OSTargetInfo<Target> {
570 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
571 MacroBuilder &Builder) const override {
572 Builder.defineMacro("__FreeBSD__", "9");
573 Builder.defineMacro("__FreeBSD_cc_version", "900001");
574 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
575 DefineStd(Builder, "unix", Opts);
576 Builder.defineMacro("__ELF__");
577 Builder.defineMacro("__PS4__");
580 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
581 this->WCharType = this->UnsignedShort;
583 this->UserLabelPrefix = "";
585 switch (Triple.getArch()) {
587 case llvm::Triple::x86_64:
588 this->MCountName = ".mcount";
595 template<typename Target>
596 class SolarisTargetInfo : public OSTargetInfo<Target> {
598 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
599 MacroBuilder &Builder) const override {
600 DefineStd(Builder, "sun", Opts);
601 DefineStd(Builder, "unix", Opts);
602 Builder.defineMacro("__ELF__");
603 Builder.defineMacro("__svr4__");
604 Builder.defineMacro("__SVR4");
605 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
606 // newer, but to 500 for everything else. feature_test.h has a check to
607 // ensure that you are not using C99 with an old version of X/Open or C89
608 // with a new version.
610 Builder.defineMacro("_XOPEN_SOURCE", "600");
612 Builder.defineMacro("_XOPEN_SOURCE", "500");
614 Builder.defineMacro("__C99FEATURES__");
615 Builder.defineMacro("_LARGEFILE_SOURCE");
616 Builder.defineMacro("_LARGEFILE64_SOURCE");
617 Builder.defineMacro("__EXTENSIONS__");
618 Builder.defineMacro("_REENTRANT");
621 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
622 this->UserLabelPrefix = "";
623 this->WCharType = this->SignedInt;
624 // FIXME: WIntType should be SignedLong
629 template<typename Target>
630 class WindowsTargetInfo : public OSTargetInfo<Target> {
632 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
633 MacroBuilder &Builder) const override {
634 Builder.defineMacro("_WIN32");
636 void getVisualStudioDefines(const LangOptions &Opts,
637 MacroBuilder &Builder) const {
638 if (Opts.CPlusPlus) {
640 Builder.defineMacro("_CPPRTTI");
642 if (Opts.CXXExceptions)
643 Builder.defineMacro("_CPPUNWIND");
646 if (!Opts.CharIsSigned)
647 Builder.defineMacro("_CHAR_UNSIGNED");
649 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
650 // but it works for now.
651 if (Opts.POSIXThreads)
652 Builder.defineMacro("_MT");
654 if (Opts.MSCompatibilityVersion) {
655 Builder.defineMacro("_MSC_VER",
656 Twine(Opts.MSCompatibilityVersion / 100000));
657 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
658 // FIXME We cannot encode the revision information into 32-bits
659 Builder.defineMacro("_MSC_BUILD", Twine(1));
661 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
662 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
665 if (Opts.MicrosoftExt) {
666 Builder.defineMacro("_MSC_EXTENSIONS");
668 if (Opts.CPlusPlus11) {
669 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
670 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
671 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
675 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
679 WindowsTargetInfo(const llvm::Triple &Triple)
680 : OSTargetInfo<Target>(Triple) {}
683 template <typename Target>
684 class NaClTargetInfo : public OSTargetInfo<Target> {
686 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
687 MacroBuilder &Builder) const override {
688 if (Opts.POSIXThreads)
689 Builder.defineMacro("_REENTRANT");
691 Builder.defineMacro("_GNU_SOURCE");
693 DefineStd(Builder, "unix", Opts);
694 Builder.defineMacro("__ELF__");
695 Builder.defineMacro("__native_client__");
699 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
700 this->UserLabelPrefix = "";
701 this->LongAlign = 32;
702 this->LongWidth = 32;
703 this->PointerAlign = 32;
704 this->PointerWidth = 32;
705 this->IntMaxType = TargetInfo::SignedLongLong;
706 this->Int64Type = TargetInfo::SignedLongLong;
707 this->DoubleAlign = 64;
708 this->LongDoubleWidth = 64;
709 this->LongDoubleAlign = 64;
710 this->LongLongWidth = 64;
711 this->LongLongAlign = 64;
712 this->SizeType = TargetInfo::UnsignedInt;
713 this->PtrDiffType = TargetInfo::SignedInt;
714 this->IntPtrType = TargetInfo::SignedInt;
715 // RegParmMax is inherited from the underlying architecture
716 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
717 if (Triple.getArch() == llvm::Triple::arm) {
718 // Handled in ARM's setABI().
719 } else if (Triple.getArch() == llvm::Triple::x86) {
720 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
721 } else if (Triple.getArch() == llvm::Triple::x86_64) {
722 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
723 } else if (Triple.getArch() == llvm::Triple::mipsel) {
724 // Handled on mips' setDescriptionString.
726 assert(Triple.getArch() == llvm::Triple::le32);
727 this->DescriptionString = "e-p:32:32-i64:64";
732 //===----------------------------------------------------------------------===//
733 // Specific target implementations.
734 //===----------------------------------------------------------------------===//
736 // PPC abstract base class
737 class PPCTargetInfo : public TargetInfo {
738 static const Builtin::Info BuiltinInfo[];
739 static const char * const GCCRegNames[];
740 static const TargetInfo::GCCRegAlias GCCRegAliases[];
743 // Target cpu features.
757 PPCTargetInfo(const llvm::Triple &Triple)
758 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
759 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
760 HasBPERMD(false), HasExtDiv(false) {
761 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
762 LongDoubleWidth = LongDoubleAlign = 128;
763 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
766 /// \brief Flags for architecture specific defines.
769 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
770 ArchDefinePpcgr = 1 << 1,
771 ArchDefinePpcsq = 1 << 2,
772 ArchDefine440 = 1 << 3,
773 ArchDefine603 = 1 << 4,
774 ArchDefine604 = 1 << 5,
775 ArchDefinePwr4 = 1 << 6,
776 ArchDefinePwr5 = 1 << 7,
777 ArchDefinePwr5x = 1 << 8,
778 ArchDefinePwr6 = 1 << 9,
779 ArchDefinePwr6x = 1 << 10,
780 ArchDefinePwr7 = 1 << 11,
781 ArchDefinePwr8 = 1 << 12,
782 ArchDefineA2 = 1 << 13,
783 ArchDefineA2q = 1 << 14
786 // Note: GCC recognizes the following additional cpus:
787 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
788 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
790 bool setCPU(const std::string &Name) override {
791 bool CPUKnown = llvm::StringSwitch<bool>(Name)
792 .Case("generic", true)
814 .Case("e500mc", true)
816 .Case("power3", true)
818 .Case("power4", true)
820 .Case("power5", true)
822 .Case("power5x", true)
824 .Case("power6", true)
826 .Case("power6x", true)
828 .Case("power7", true)
830 .Case("power8", true)
832 .Case("powerpc", true)
834 .Case("powerpc64", true)
836 .Case("powerpc64le", true)
837 .Case("ppc64le", true)
847 StringRef getABI() const override { return ABI; }
849 void getTargetBuiltins(const Builtin::Info *&Records,
850 unsigned &NumRecords) const override {
851 Records = BuiltinInfo;
852 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
855 bool isCLZForZeroUndef() const override { return false; }
857 void getTargetDefines(const LangOptions &Opts,
858 MacroBuilder &Builder) const override;
860 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
862 bool handleTargetFeatures(std::vector<std::string> &Features,
863 DiagnosticsEngine &Diags) override;
864 bool hasFeature(StringRef Feature) const override;
866 void getGCCRegNames(const char * const *&Names,
867 unsigned &NumNames) const override;
868 void getGCCRegAliases(const GCCRegAlias *&Aliases,
869 unsigned &NumAliases) const override;
870 bool validateAsmConstraint(const char *&Name,
871 TargetInfo::ConstraintInfo &Info) const override {
873 default: return false;
876 case 'b': // Base register
877 case 'f': // Floating point register
878 Info.setAllowsRegister();
880 // FIXME: The following are added to allow parsing.
881 // I just took a guess at what the actions should be.
882 // Also, is more specific checking needed? I.e. specific registers?
883 case 'd': // Floating point register (containing 64-bit value)
884 case 'v': // Altivec vector register
885 Info.setAllowsRegister();
889 case 'd':// VSX vector register to hold vector double data
890 case 'f':// VSX vector register to hold vector float data
891 case 's':// VSX vector register to hold scalar float data
892 case 'a':// Any VSX register
893 case 'c':// An individual CR bit
898 Info.setAllowsRegister();
899 Name++; // Skip over 'w'.
901 case 'h': // `MQ', `CTR', or `LINK' register
902 case 'q': // `MQ' register
903 case 'c': // `CTR' register
904 case 'l': // `LINK' register
905 case 'x': // `CR' register (condition register) number 0
906 case 'y': // `CR' register (condition register)
907 case 'z': // `XER[CA]' carry bit (part of the XER register)
908 Info.setAllowsRegister();
910 case 'I': // Signed 16-bit constant
911 case 'J': // Unsigned 16-bit constant shifted left 16 bits
912 // (use `L' instead for SImode constants)
913 case 'K': // Unsigned 16-bit constant
914 case 'L': // Signed 16-bit constant shifted left 16 bits
915 case 'M': // Constant larger than 31
916 case 'N': // Exact power of 2
917 case 'P': // Constant whose negation is a signed 16-bit constant
918 case 'G': // Floating point constant that can be loaded into a
919 // register with one instruction per word
920 case 'H': // Integer/Floating point constant that can be loaded
921 // into a register using three instructions
923 case 'm': // Memory operand. Note that on PowerPC targets, m can
924 // include addresses that update the base register. It
925 // is therefore only safe to use `m' in an asm statement
926 // if that asm statement accesses the operand exactly once.
927 // The asm statement must also use `%U<opno>' as a
928 // placeholder for the "update" flag in the corresponding
929 // load or store instruction. For example:
930 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
932 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
933 // is not. Use es rather than m if you don't want the base
934 // register to be updated.
938 // es: A "stable" memory operand; that is, one which does not
939 // include any automodification of the base register. Unlike
940 // `m', this constraint can be used in asm statements that
941 // might access the operand several times, or that might not
943 Info.setAllowsMemory();
944 Name++; // Skip over 'e'.
946 case 'Q': // Memory operand that is an offset from a register (it is
947 // usually better to use `m' or `es' in asm statements)
948 case 'Z': // Memory operand that is an indexed or indirect from a
949 // register (it is usually better to use `m' or `es' in
951 Info.setAllowsMemory();
952 Info.setAllowsRegister();
954 case 'R': // AIX TOC entry
955 case 'a': // Address operand that is an indexed or indirect from a
956 // register (`p' is preferable for asm statements)
957 case 'S': // Constant suitable as a 64-bit mask operand
958 case 'T': // Constant suitable as a 32-bit mask operand
959 case 'U': // System V Release 4 small data area reference
960 case 't': // AND masks that can be performed by two rldic{l, r}
962 case 'W': // Vector constant that does not require memory
963 case 'j': // Vector constant that is all zeros.
969 std::string convertConstraint(const char *&Constraint) const override {
971 switch (*Constraint) {
974 // Two-character constraint; add "^" hint for later parsing.
975 R = std::string("^") + std::string(Constraint, 2);
979 return TargetInfo::convertConstraint(Constraint);
983 const char *getClobbers() const override {
986 int getEHDataRegisterNumber(unsigned RegNo) const override {
987 if (RegNo == 0) return 3;
988 if (RegNo == 1) return 4;
992 bool hasSjLjLowering() const override {
997 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
998 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
999 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1001 #include "clang/Basic/BuiltinsPPC.def"
1004 /// handleTargetFeatures - Perform initialization based on the user
1005 /// configured set of features.
1006 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1007 DiagnosticsEngine &Diags) {
1008 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
1009 // Ignore disabled features.
1010 if (Features[i][0] == '-')
1013 StringRef Feature = StringRef(Features[i]).substr(1);
1015 if (Feature == "vsx") {
1020 if (Feature == "bpermd") {
1025 if (Feature == "extdiv") {
1030 if (Feature == "power8-vector") {
1036 if (Feature == "crypto") {
1041 if (Feature == "direct-move") {
1042 HasDirectMove = true;
1047 if (Feature == "qpx") {
1052 if (Feature == "htm") {
1057 // TODO: Finish this list and add an assert that we've handled them
1064 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1065 /// #defines that are not tied to a specific subtarget.
1066 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1067 MacroBuilder &Builder) const {
1068 // Target identification.
1069 Builder.defineMacro("__ppc__");
1070 Builder.defineMacro("__PPC__");
1071 Builder.defineMacro("_ARCH_PPC");
1072 Builder.defineMacro("__powerpc__");
1073 Builder.defineMacro("__POWERPC__");
1074 if (PointerWidth == 64) {
1075 Builder.defineMacro("_ARCH_PPC64");
1076 Builder.defineMacro("__powerpc64__");
1077 Builder.defineMacro("__ppc64__");
1078 Builder.defineMacro("__PPC64__");
1081 // Target properties.
1082 if (getTriple().getArch() == llvm::Triple::ppc64le) {
1083 Builder.defineMacro("_LITTLE_ENDIAN");
1085 if (getTriple().getOS() != llvm::Triple::NetBSD &&
1086 getTriple().getOS() != llvm::Triple::OpenBSD)
1087 Builder.defineMacro("_BIG_ENDIAN");
1091 if (ABI == "elfv1" || ABI == "elfv1-qpx")
1092 Builder.defineMacro("_CALL_ELF", "1");
1094 Builder.defineMacro("_CALL_ELF", "2");
1096 // Subtarget options.
1097 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1098 Builder.defineMacro("__REGISTER_PREFIX__", "");
1100 // FIXME: Should be controlled by command line option.
1101 if (LongDoubleWidth == 128)
1102 Builder.defineMacro("__LONG_DOUBLE_128__");
1105 Builder.defineMacro("__VEC__", "10206");
1106 Builder.defineMacro("__ALTIVEC__");
1109 // CPU identification.
1110 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1111 .Case("440", ArchDefineName)
1112 .Case("450", ArchDefineName | ArchDefine440)
1113 .Case("601", ArchDefineName)
1114 .Case("602", ArchDefineName | ArchDefinePpcgr)
1115 .Case("603", ArchDefineName | ArchDefinePpcgr)
1116 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1117 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1118 .Case("604", ArchDefineName | ArchDefinePpcgr)
1119 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1120 .Case("620", ArchDefineName | ArchDefinePpcgr)
1121 .Case("630", ArchDefineName | ArchDefinePpcgr)
1122 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1123 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1124 .Case("750", ArchDefineName | ArchDefinePpcgr)
1125 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1127 .Case("a2", ArchDefineA2)
1128 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1129 .Case("pwr3", ArchDefinePpcgr)
1130 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1131 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1133 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1134 | ArchDefinePpcgr | ArchDefinePpcsq)
1135 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1136 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1137 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1138 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1140 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1141 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1142 | ArchDefinePpcgr | ArchDefinePpcsq)
1143 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1144 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1145 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1146 .Case("power3", ArchDefinePpcgr)
1147 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1148 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1150 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1151 | ArchDefinePpcgr | ArchDefinePpcsq)
1152 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1153 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1154 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1155 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1157 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1158 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1159 | ArchDefinePpcgr | ArchDefinePpcsq)
1160 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1161 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1162 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1163 .Default(ArchDefineNone);
1165 if (defs & ArchDefineName)
1166 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1167 if (defs & ArchDefinePpcgr)
1168 Builder.defineMacro("_ARCH_PPCGR");
1169 if (defs & ArchDefinePpcsq)
1170 Builder.defineMacro("_ARCH_PPCSQ");
1171 if (defs & ArchDefine440)
1172 Builder.defineMacro("_ARCH_440");
1173 if (defs & ArchDefine603)
1174 Builder.defineMacro("_ARCH_603");
1175 if (defs & ArchDefine604)
1176 Builder.defineMacro("_ARCH_604");
1177 if (defs & ArchDefinePwr4)
1178 Builder.defineMacro("_ARCH_PWR4");
1179 if (defs & ArchDefinePwr5)
1180 Builder.defineMacro("_ARCH_PWR5");
1181 if (defs & ArchDefinePwr5x)
1182 Builder.defineMacro("_ARCH_PWR5X");
1183 if (defs & ArchDefinePwr6)
1184 Builder.defineMacro("_ARCH_PWR6");
1185 if (defs & ArchDefinePwr6x)
1186 Builder.defineMacro("_ARCH_PWR6X");
1187 if (defs & ArchDefinePwr7)
1188 Builder.defineMacro("_ARCH_PWR7");
1189 if (defs & ArchDefinePwr8)
1190 Builder.defineMacro("_ARCH_PWR8");
1191 if (defs & ArchDefineA2)
1192 Builder.defineMacro("_ARCH_A2");
1193 if (defs & ArchDefineA2q) {
1194 Builder.defineMacro("_ARCH_A2Q");
1195 Builder.defineMacro("_ARCH_QP");
1198 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1199 Builder.defineMacro("__bg__");
1200 Builder.defineMacro("__THW_BLUEGENE__");
1201 Builder.defineMacro("__bgq__");
1202 Builder.defineMacro("__TOS_BGQ__");
1206 Builder.defineMacro("__VSX__");
1208 Builder.defineMacro("__POWER8_VECTOR__");
1210 Builder.defineMacro("__CRYPTO__");
1212 Builder.defineMacro("__HTM__");
1213 if (getTriple().getArch() == llvm::Triple::ppc64le ||
1214 (defs & ArchDefinePwr8) || (CPU == "pwr8")) {
1215 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1216 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1217 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1218 if (PointerWidth == 64)
1219 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1222 // FIXME: The following are not yet generated here by Clang, but are
1223 // generated by GCC:
1226 // __RECIP_PRECISION__
1227 // __APPLE_ALTIVEC__
1236 // __CMODEL_MEDIUM__
1243 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1244 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1254 .Case("ppc64", true)
1255 .Case("ppc64le", true)
1258 Features["qpx"] = (CPU == "a2q");
1259 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1260 .Case("ppc64le", true)
1263 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1264 .Case("ppc64le", true)
1267 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1268 .Case("ppc64le", true)
1272 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1273 .Case("ppc64le", true)
1277 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1278 .Case("ppc64le", true)
1283 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1284 return llvm::StringSwitch<bool>(Feature)
1285 .Case("powerpc", true)
1286 .Case("vsx", HasVSX)
1287 .Case("power8-vector", HasP8Vector)
1288 .Case("crypto", HasP8Crypto)
1289 .Case("direct-move", HasDirectMove)
1290 .Case("qpx", HasQPX)
1291 .Case("htm", HasHTM)
1292 .Case("bpermd", HasBPERMD)
1293 .Case("extdiv", HasExtDiv)
1297 const char * const PPCTargetInfo::GCCRegNames[] = {
1298 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1299 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1300 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1301 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1302 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1303 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1304 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1305 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1306 "mq", "lr", "ctr", "ap",
1307 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1309 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1310 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1311 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1312 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1314 "spe_acc", "spefscr",
1318 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1319 unsigned &NumNames) const {
1320 Names = GCCRegNames;
1321 NumNames = llvm::array_lengthof(GCCRegNames);
1324 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1325 // While some of these aliases do map to different registers
1326 // they still share the same register name.
1337 { { "10" }, "r10" },
1338 { { "11" }, "r11" },
1339 { { "12" }, "r12" },
1340 { { "13" }, "r13" },
1341 { { "14" }, "r14" },
1342 { { "15" }, "r15" },
1343 { { "16" }, "r16" },
1344 { { "17" }, "r17" },
1345 { { "18" }, "r18" },
1346 { { "19" }, "r19" },
1347 { { "20" }, "r20" },
1348 { { "21" }, "r21" },
1349 { { "22" }, "r22" },
1350 { { "23" }, "r23" },
1351 { { "24" }, "r24" },
1352 { { "25" }, "r25" },
1353 { { "26" }, "r26" },
1354 { { "27" }, "r27" },
1355 { { "28" }, "r28" },
1356 { { "29" }, "r29" },
1357 { { "30" }, "r30" },
1358 { { "31" }, "r31" },
1359 { { "fr0" }, "f0" },
1360 { { "fr1" }, "f1" },
1361 { { "fr2" }, "f2" },
1362 { { "fr3" }, "f3" },
1363 { { "fr4" }, "f4" },
1364 { { "fr5" }, "f5" },
1365 { { "fr6" }, "f6" },
1366 { { "fr7" }, "f7" },
1367 { { "fr8" }, "f8" },
1368 { { "fr9" }, "f9" },
1369 { { "fr10" }, "f10" },
1370 { { "fr11" }, "f11" },
1371 { { "fr12" }, "f12" },
1372 { { "fr13" }, "f13" },
1373 { { "fr14" }, "f14" },
1374 { { "fr15" }, "f15" },
1375 { { "fr16" }, "f16" },
1376 { { "fr17" }, "f17" },
1377 { { "fr18" }, "f18" },
1378 { { "fr19" }, "f19" },
1379 { { "fr20" }, "f20" },
1380 { { "fr21" }, "f21" },
1381 { { "fr22" }, "f22" },
1382 { { "fr23" }, "f23" },
1383 { { "fr24" }, "f24" },
1384 { { "fr25" }, "f25" },
1385 { { "fr26" }, "f26" },
1386 { { "fr27" }, "f27" },
1387 { { "fr28" }, "f28" },
1388 { { "fr29" }, "f29" },
1389 { { "fr30" }, "f30" },
1390 { { "fr31" }, "f31" },
1391 { { "cc" }, "cr0" },
1394 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1395 unsigned &NumAliases) const {
1396 Aliases = GCCRegAliases;
1397 NumAliases = llvm::array_lengthof(GCCRegAliases);
1400 class PPC32TargetInfo : public PPCTargetInfo {
1402 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1403 DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1405 switch (getTriple().getOS()) {
1406 case llvm::Triple::Linux:
1407 case llvm::Triple::FreeBSD:
1408 case llvm::Triple::NetBSD:
1409 SizeType = UnsignedInt;
1410 PtrDiffType = SignedInt;
1411 IntPtrType = SignedInt;
1417 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1418 LongDoubleWidth = LongDoubleAlign = 64;
1419 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1422 // PPC32 supports atomics up to 4 bytes.
1423 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1426 BuiltinVaListKind getBuiltinVaListKind() const override {
1427 // This is the ELF definition, and is overridden by the Darwin sub-target
1428 return TargetInfo::PowerABIBuiltinVaList;
1432 // Note: ABI differences may eventually require us to have a separate
1433 // TargetInfo for little endian.
1434 class PPC64TargetInfo : public PPCTargetInfo {
1436 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1437 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1438 IntMaxType = SignedLong;
1439 Int64Type = SignedLong;
1441 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1442 DescriptionString = "e-m:e-i64:64-n32:64";
1445 DescriptionString = "E-m:e-i64:64-n32:64";
1449 switch (getTriple().getOS()) {
1450 case llvm::Triple::FreeBSD:
1451 LongDoubleWidth = LongDoubleAlign = 64;
1452 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1454 case llvm::Triple::NetBSD:
1455 IntMaxType = SignedLongLong;
1456 Int64Type = SignedLongLong;
1462 // PPC64 supports atomics up to 8 bytes.
1463 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1465 BuiltinVaListKind getBuiltinVaListKind() const override {
1466 return TargetInfo::CharPtrBuiltinVaList;
1468 // PPC64 Linux-specifc ABI options.
1469 bool setABI(const std::string &Name) override {
1470 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1478 class DarwinPPC32TargetInfo :
1479 public DarwinTargetInfo<PPC32TargetInfo> {
1481 DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1482 : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1483 HasAlignMac68kSupport = true;
1484 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1485 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1487 SuitableAlign = 128;
1488 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1490 BuiltinVaListKind getBuiltinVaListKind() const override {
1491 return TargetInfo::CharPtrBuiltinVaList;
1495 class DarwinPPC64TargetInfo :
1496 public DarwinTargetInfo<PPC64TargetInfo> {
1498 DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1499 : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1500 HasAlignMac68kSupport = true;
1501 SuitableAlign = 128;
1502 DescriptionString = "E-m:o-i64:64-n32:64";
1506 static const unsigned NVPTXAddrSpaceMap[] = {
1509 4, // opencl_constant
1510 // FIXME: generic has to be added to the target
1511 0, // opencl_generic
1516 class NVPTXTargetInfo : public TargetInfo {
1517 static const char * const GCCRegNames[];
1518 static const Builtin::Info BuiltinInfo[];
1520 // The GPU profiles supported by the NVPTX backend
1531 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1533 TLSSupported = false;
1534 LongWidth = LongAlign = 64;
1535 AddrSpaceMap = &NVPTXAddrSpaceMap;
1536 UseAddrSpaceMapMangling = true;
1537 // Define available target features
1538 // These must be defined in sorted order!
1539 NoAsmVariants = true;
1540 // Set the default GPU to sm20
1543 void getTargetDefines(const LangOptions &Opts,
1544 MacroBuilder &Builder) const override {
1545 Builder.defineMacro("__PTX__");
1546 Builder.defineMacro("__NVPTX__");
1547 if (Opts.CUDAIsDevice) {
1548 // Set __CUDA_ARCH__ for the GPU specified.
1549 std::string CUDAArchCode;
1552 CUDAArchCode = "200";
1555 CUDAArchCode = "210";
1558 CUDAArchCode = "300";
1561 CUDAArchCode = "350";
1564 CUDAArchCode = "370";
1567 llvm_unreachable("Unhandled target CPU");
1569 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1572 void getTargetBuiltins(const Builtin::Info *&Records,
1573 unsigned &NumRecords) const override {
1574 Records = BuiltinInfo;
1575 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1577 bool hasFeature(StringRef Feature) const override {
1578 return Feature == "ptx" || Feature == "nvptx";
1581 void getGCCRegNames(const char * const *&Names,
1582 unsigned &NumNames) const override;
1583 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1584 unsigned &NumAliases) const override {
1590 validateAsmConstraint(const char *&Name,
1591 TargetInfo::ConstraintInfo &Info) const override {
1593 default: return false;
1600 Info.setAllowsRegister();
1604 const char *getClobbers() const override {
1605 // FIXME: Is this really right?
1608 BuiltinVaListKind getBuiltinVaListKind() const override {
1610 return TargetInfo::CharPtrBuiltinVaList;
1612 bool setCPU(const std::string &Name) override {
1613 GPU = llvm::StringSwitch<GPUKind>(Name)
1614 .Case("sm_20", GK_SM20)
1615 .Case("sm_21", GK_SM21)
1616 .Case("sm_30", GK_SM30)
1617 .Case("sm_35", GK_SM35)
1618 .Case("sm_37", GK_SM37)
1621 return GPU != GK_NONE;
1625 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1626 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1627 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1629 #include "clang/Basic/BuiltinsNVPTX.def"
1632 const char * const NVPTXTargetInfo::GCCRegNames[] = {
1636 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1637 unsigned &NumNames) const {
1638 Names = GCCRegNames;
1639 NumNames = llvm::array_lengthof(GCCRegNames);
1642 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1644 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1645 PointerWidth = PointerAlign = 32;
1646 SizeType = TargetInfo::UnsignedInt;
1647 PtrDiffType = TargetInfo::SignedInt;
1648 IntPtrType = TargetInfo::SignedInt;
1649 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1653 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1655 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1656 PointerWidth = PointerAlign = 64;
1657 SizeType = TargetInfo::UnsignedLong;
1658 PtrDiffType = TargetInfo::SignedLong;
1659 IntPtrType = TargetInfo::SignedLong;
1660 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1664 static const unsigned R600AddrSpaceMap[] = {
1667 2, // opencl_constant
1668 4, // opencl_generic
1674 // If you edit the description strings, make sure you update
1675 // getPointerWidthV().
1677 static const char *DescriptionStringR600 =
1678 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1679 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1681 static const char *DescriptionStringR600DoubleOps =
1682 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1683 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1685 static const char *DescriptionStringSI =
1686 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1687 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1688 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1690 class R600TargetInfo : public TargetInfo {
1691 static const Builtin::Info BuiltinInfo[];
1692 static const char * const GCCRegNames[];
1694 /// \brief The GPU profiles supported by the R600 target.
1702 GK_EVERGREEN_DOUBLE_OPS,
1703 GK_NORTHERN_ISLANDS,
1705 GK_SOUTHERN_ISLANDS,
1714 R600TargetInfo(const llvm::Triple &Triple)
1715 : TargetInfo(Triple) {
1717 if (Triple.getArch() == llvm::Triple::amdgcn) {
1718 DescriptionString = DescriptionStringSI;
1719 GPU = GK_SOUTHERN_ISLANDS;
1724 DescriptionString = DescriptionStringR600;
1730 AddrSpaceMap = &R600AddrSpaceMap;
1731 UseAddrSpaceMapMangling = true;
1734 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1735 if (GPU <= GK_CAYMAN)
1748 const char * getClobbers() const override {
1752 void getGCCRegNames(const char * const *&Names,
1753 unsigned &NumNames) const override;
1755 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1756 unsigned &NumAliases) const override {
1761 bool validateAsmConstraint(const char *&Name,
1762 TargetInfo::ConstraintInfo &info) const override {
1766 void getTargetBuiltins(const Builtin::Info *&Records,
1767 unsigned &NumRecords) const override {
1768 Records = BuiltinInfo;
1769 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;
1772 void getTargetDefines(const LangOptions &Opts,
1773 MacroBuilder &Builder) const override {
1774 Builder.defineMacro("__R600__");
1776 Builder.defineMacro("__HAS_FMAF__");
1778 Builder.defineMacro("__HAS_LDEXPF__");
1779 if (hasFP64 && Opts.OpenCL) {
1780 Builder.defineMacro("cl_khr_fp64");
1784 BuiltinVaListKind getBuiltinVaListKind() const override {
1785 return TargetInfo::CharPtrBuiltinVaList;
1788 bool setCPU(const std::string &Name) override {
1789 GPU = llvm::StringSwitch<GPUKind>(Name)
1790 .Case("r600" , GK_R600)
1791 .Case("rv610", GK_R600)
1792 .Case("rv620", GK_R600)
1793 .Case("rv630", GK_R600)
1794 .Case("rv635", GK_R600)
1795 .Case("rs780", GK_R600)
1796 .Case("rs880", GK_R600)
1797 .Case("rv670", GK_R600_DOUBLE_OPS)
1798 .Case("rv710", GK_R700)
1799 .Case("rv730", GK_R700)
1800 .Case("rv740", GK_R700_DOUBLE_OPS)
1801 .Case("rv770", GK_R700_DOUBLE_OPS)
1802 .Case("palm", GK_EVERGREEN)
1803 .Case("cedar", GK_EVERGREEN)
1804 .Case("sumo", GK_EVERGREEN)
1805 .Case("sumo2", GK_EVERGREEN)
1806 .Case("redwood", GK_EVERGREEN)
1807 .Case("juniper", GK_EVERGREEN)
1808 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
1809 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
1810 .Case("barts", GK_NORTHERN_ISLANDS)
1811 .Case("turks", GK_NORTHERN_ISLANDS)
1812 .Case("caicos", GK_NORTHERN_ISLANDS)
1813 .Case("cayman", GK_CAYMAN)
1814 .Case("aruba", GK_CAYMAN)
1815 .Case("tahiti", GK_SOUTHERN_ISLANDS)
1816 .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1817 .Case("verde", GK_SOUTHERN_ISLANDS)
1818 .Case("oland", GK_SOUTHERN_ISLANDS)
1819 .Case("hainan", GK_SOUTHERN_ISLANDS)
1820 .Case("bonaire", GK_SEA_ISLANDS)
1821 .Case("kabini", GK_SEA_ISLANDS)
1822 .Case("kaveri", GK_SEA_ISLANDS)
1823 .Case("hawaii", GK_SEA_ISLANDS)
1824 .Case("mullins", GK_SEA_ISLANDS)
1827 if (GPU == GK_NONE) {
1831 // Set the correct data layout
1837 case GK_NORTHERN_ISLANDS:
1838 DescriptionString = DescriptionStringR600;
1843 case GK_R600_DOUBLE_OPS:
1844 case GK_R700_DOUBLE_OPS:
1845 case GK_EVERGREEN_DOUBLE_OPS:
1847 DescriptionString = DescriptionStringR600DoubleOps;
1852 case GK_SOUTHERN_ISLANDS:
1853 case GK_SEA_ISLANDS:
1854 DescriptionString = DescriptionStringSI;
1865 const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
1866 #define BUILTIN(ID, TYPE, ATTRS) \
1867 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1868 #include "clang/Basic/BuiltinsR600.def"
1870 const char * const R600TargetInfo::GCCRegNames[] = {
1871 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1872 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1873 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1874 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1875 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
1876 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
1877 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
1878 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
1879 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
1880 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
1881 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
1882 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
1883 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
1884 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
1885 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
1886 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
1887 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
1888 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
1889 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
1890 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
1891 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
1892 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
1893 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
1894 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
1895 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
1896 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
1897 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
1898 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
1899 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
1900 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
1901 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
1902 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
1903 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1904 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
1905 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
1906 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
1907 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
1908 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
1909 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
1910 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
1911 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
1912 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
1913 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
1914 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
1915 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
1916 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
1917 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
1918 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127"
1919 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi",
1920 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi"
1923 void R600TargetInfo::getGCCRegNames(const char * const *&Names,
1924 unsigned &NumNames) const {
1925 Names = GCCRegNames;
1926 NumNames = llvm::array_lengthof(GCCRegNames);
1929 // Namespace for x86 abstract base class
1930 const Builtin::Info BuiltinInfo[] = {
1931 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1932 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1934 #include "clang/Basic/BuiltinsX86.def"
1937 static const char* const GCCRegNames[] = {
1938 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1939 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1940 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1941 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1942 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1943 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1944 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1945 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1946 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1949 const TargetInfo::AddlRegName AddlRegNames[] = {
1950 { { "al", "ah", "eax", "rax" }, 0 },
1951 { { "bl", "bh", "ebx", "rbx" }, 3 },
1952 { { "cl", "ch", "ecx", "rcx" }, 2 },
1953 { { "dl", "dh", "edx", "rdx" }, 1 },
1954 { { "esi", "rsi" }, 4 },
1955 { { "edi", "rdi" }, 5 },
1956 { { "esp", "rsp" }, 7 },
1957 { { "ebp", "rbp" }, 6 },
1960 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1961 // most of the implementation can be shared.
1962 class X86TargetInfo : public TargetInfo {
1964 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1967 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1991 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW,
1996 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1998 /// Each enumeration represents a particular CPU supported by Clang. These
1999 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2004 /// i386-generation processors.
2010 /// i486-generation processors.
2019 /// i586-generation processors, P5 microarchitecture based.
2027 /// i686-generation processors, P6 / Pentium M microarchitecture based.
2037 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2038 /// Clang however has some logic to suport this.
2039 // FIXME: Warn, deprecate, and potentially remove this.
2044 /// Netburst microarchitecture based processors.
2053 /// Core microarchitecture based processors.
2057 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2058 /// codename which GCC no longer accepts as an option to -march, but Clang
2059 /// has some logic for recognizing it.
2060 // FIXME: Warn, deprecate, and potentially remove this.
2072 /// Nehalem microarchitecture based processors.
2076 /// Westmere microarchitecture based processors.
2079 /// \name Sandy Bridge
2080 /// Sandy Bridge microarchitecture based processors.
2083 /// \name Ivy Bridge
2084 /// Ivy Bridge microarchitecture based processors.
2088 /// Haswell microarchitecture based processors.
2092 /// Broadwell microarchitecture based processors.
2096 /// Skylake microarchitecture based processors.
2099 /// \name Knights Landing
2100 /// Knights Landing processor.
2104 /// K6 architecture processors.
2112 /// K7 architecture processors.
2115 CK_AthlonThunderbird,
2122 /// K8 architecture processors.
2135 /// Bobcat architecture processors.
2142 /// Bulldozer architecture processors.
2150 /// This specification is deprecated and will be removed in the future.
2151 /// Users should prefer \see CK_K8.
2152 // FIXME: Warn on this when the CPU is set to it.
2158 /// Geode processors.
2171 X86TargetInfo(const llvm::Triple &Triple)
2172 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
2173 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
2174 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
2175 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
2176 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
2177 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
2178 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
2179 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
2181 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
2183 unsigned getFloatEvalMethod() const override {
2184 // X87 evaluates with 80 bits "long double" precision.
2185 return SSELevel == NoSSE ? 2 : 0;
2187 void getTargetBuiltins(const Builtin::Info *&Records,
2188 unsigned &NumRecords) const override {
2189 Records = BuiltinInfo;
2190 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
2192 void getGCCRegNames(const char * const *&Names,
2193 unsigned &NumNames) const override {
2194 Names = GCCRegNames;
2195 NumNames = llvm::array_lengthof(GCCRegNames);
2197 void getGCCRegAliases(const GCCRegAlias *&Aliases,
2198 unsigned &NumAliases) const override {
2202 void getGCCAddlRegNames(const AddlRegName *&Names,
2203 unsigned &NumNames) const override {
2204 Names = AddlRegNames;
2205 NumNames = llvm::array_lengthof(AddlRegNames);
2207 bool validateAsmConstraint(const char *&Name,
2208 TargetInfo::ConstraintInfo &info) const override;
2210 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2212 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2214 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2216 std::string convertConstraint(const char *&Constraint) const override;
2217 const char *getClobbers() const override {
2218 return "~{dirflag},~{fpsr},~{flags}";
2220 void getTargetDefines(const LangOptions &Opts,
2221 MacroBuilder &Builder) const override;
2222 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2224 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2226 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2228 void setFeatureEnabled(llvm::StringMap<bool> &Features,
2229 StringRef Name, bool Enabled) const override {
2230 setFeatureEnabledImpl(Features, Name, Enabled);
2232 // This exists purely to cut down on the number of virtual calls in
2233 // getDefaultFeatures which calls this repeatedly.
2234 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2235 StringRef Name, bool Enabled);
2236 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
2237 bool hasFeature(StringRef Feature) const override;
2238 bool handleTargetFeatures(std::vector<std::string> &Features,
2239 DiagnosticsEngine &Diags) override;
2240 StringRef getABI() const override {
2241 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2243 else if (getTriple().getArch() == llvm::Triple::x86 &&
2244 MMX3DNowLevel == NoMMX3DNow)
2248 bool setCPU(const std::string &Name) override {
2249 CPU = llvm::StringSwitch<CPUKind>(Name)
2250 .Case("i386", CK_i386)
2251 .Case("i486", CK_i486)
2252 .Case("winchip-c6", CK_WinChipC6)
2253 .Case("winchip2", CK_WinChip2)
2255 .Case("i586", CK_i586)
2256 .Case("pentium", CK_Pentium)
2257 .Case("pentium-mmx", CK_PentiumMMX)
2258 .Case("i686", CK_i686)
2259 .Case("pentiumpro", CK_PentiumPro)
2260 .Case("pentium2", CK_Pentium2)
2261 .Case("pentium3", CK_Pentium3)
2262 .Case("pentium3m", CK_Pentium3M)
2263 .Case("pentium-m", CK_PentiumM)
2264 .Case("c3-2", CK_C3_2)
2265 .Case("yonah", CK_Yonah)
2266 .Case("pentium4", CK_Pentium4)
2267 .Case("pentium4m", CK_Pentium4M)
2268 .Case("prescott", CK_Prescott)
2269 .Case("nocona", CK_Nocona)
2270 .Case("core2", CK_Core2)
2271 .Case("penryn", CK_Penryn)
2272 .Case("bonnell", CK_Bonnell)
2273 .Case("atom", CK_Bonnell) // Legacy name.
2274 .Case("silvermont", CK_Silvermont)
2275 .Case("slm", CK_Silvermont) // Legacy name.
2276 .Case("nehalem", CK_Nehalem)
2277 .Case("corei7", CK_Nehalem) // Legacy name.
2278 .Case("westmere", CK_Westmere)
2279 .Case("sandybridge", CK_SandyBridge)
2280 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2281 .Case("ivybridge", CK_IvyBridge)
2282 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2283 .Case("haswell", CK_Haswell)
2284 .Case("core-avx2", CK_Haswell) // Legacy name.
2285 .Case("broadwell", CK_Broadwell)
2286 .Case("skylake", CK_Skylake)
2287 .Case("skx", CK_Skylake) // Legacy name.
2288 .Case("knl", CK_KNL)
2290 .Case("k6-2", CK_K6_2)
2291 .Case("k6-3", CK_K6_3)
2292 .Case("athlon", CK_Athlon)
2293 .Case("athlon-tbird", CK_AthlonThunderbird)
2294 .Case("athlon-4", CK_Athlon4)
2295 .Case("athlon-xp", CK_AthlonXP)
2296 .Case("athlon-mp", CK_AthlonMP)
2297 .Case("athlon64", CK_Athlon64)
2298 .Case("athlon64-sse3", CK_Athlon64SSE3)
2299 .Case("athlon-fx", CK_AthlonFX)
2301 .Case("k8-sse3", CK_K8SSE3)
2302 .Case("opteron", CK_Opteron)
2303 .Case("opteron-sse3", CK_OpteronSSE3)
2304 .Case("barcelona", CK_AMDFAM10)
2305 .Case("amdfam10", CK_AMDFAM10)
2306 .Case("btver1", CK_BTVER1)
2307 .Case("btver2", CK_BTVER2)
2308 .Case("bdver1", CK_BDVER1)
2309 .Case("bdver2", CK_BDVER2)
2310 .Case("bdver3", CK_BDVER3)
2311 .Case("bdver4", CK_BDVER4)
2312 .Case("x86-64", CK_x86_64)
2313 .Case("geode", CK_Geode)
2314 .Default(CK_Generic);
2316 // Perform any per-CPU checks necessary to determine if this CPU is
2318 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2319 // invalid without explaining *why*.
2322 // No processor selected!
2348 case CK_AthlonThunderbird:
2353 // Only accept certain architectures when compiling in 32-bit mode.
2354 if (getTriple().getArch() != llvm::Triple::x86)
2365 case CK_SandyBridge:
2372 case CK_Athlon64SSE3:
2377 case CK_OpteronSSE3:
2388 llvm_unreachable("Unhandled CPU kind");
2391 bool setFPMath(StringRef Name) override;
2393 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2394 // We accept all non-ARM calling conventions
2395 return (CC == CC_X86ThisCall ||
2396 CC == CC_X86FastCall ||
2397 CC == CC_X86StdCall ||
2398 CC == CC_X86VectorCall ||
2400 CC == CC_X86Pascal ||
2401 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2404 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2405 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2408 bool hasSjLjLowering() const override {
2413 bool X86TargetInfo::setFPMath(StringRef Name) {
2414 if (Name == "387") {
2418 if (Name == "sse") {
2425 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2426 // FIXME: This *really* should not be here.
2428 // X86_64 always has SSE2.
2429 if (getTriple().getArch() == llvm::Triple::x86_64)
2430 setFeatureEnabledImpl(Features, "sse2", true);
2445 setFeatureEnabledImpl(Features, "mmx", true);
2450 setFeatureEnabledImpl(Features, "sse", true);
2456 setFeatureEnabledImpl(Features, "sse2", true);
2461 setFeatureEnabledImpl(Features, "sse3", true);
2462 setFeatureEnabledImpl(Features, "cx16", true);
2466 setFeatureEnabledImpl(Features, "ssse3", true);
2467 setFeatureEnabledImpl(Features, "cx16", true);
2470 setFeatureEnabledImpl(Features, "sse4.1", true);
2471 setFeatureEnabledImpl(Features, "cx16", true);
2474 setFeatureEnabledImpl(Features, "avx512f", true);
2475 setFeatureEnabledImpl(Features, "avx512cd", true);
2476 setFeatureEnabledImpl(Features, "avx512dq", true);
2477 setFeatureEnabledImpl(Features, "avx512bw", true);
2478 setFeatureEnabledImpl(Features, "avx512vl", true);
2481 setFeatureEnabledImpl(Features, "rdseed", true);
2482 setFeatureEnabledImpl(Features, "adx", true);
2485 setFeatureEnabledImpl(Features, "avx2", true);
2486 setFeatureEnabledImpl(Features, "lzcnt", true);
2487 setFeatureEnabledImpl(Features, "bmi", true);
2488 setFeatureEnabledImpl(Features, "bmi2", true);
2489 setFeatureEnabledImpl(Features, "rtm", true);
2490 setFeatureEnabledImpl(Features, "fma", true);
2493 setFeatureEnabledImpl(Features, "rdrnd", true);
2494 setFeatureEnabledImpl(Features, "f16c", true);
2495 setFeatureEnabledImpl(Features, "fsgsbase", true);
2497 case CK_SandyBridge:
2498 setFeatureEnabledImpl(Features, "avx", true);
2502 setFeatureEnabledImpl(Features, "aes", true);
2503 setFeatureEnabledImpl(Features, "pclmul", true);
2506 setFeatureEnabledImpl(Features, "sse4.2", true);
2507 setFeatureEnabledImpl(Features, "cx16", true);
2510 setFeatureEnabledImpl(Features, "avx512f", true);
2511 setFeatureEnabledImpl(Features, "avx512cd", true);
2512 setFeatureEnabledImpl(Features, "avx512er", true);
2513 setFeatureEnabledImpl(Features, "avx512pf", true);
2514 setFeatureEnabledImpl(Features, "rdseed", true);
2515 setFeatureEnabledImpl(Features, "adx", true);
2516 setFeatureEnabledImpl(Features, "lzcnt", true);
2517 setFeatureEnabledImpl(Features, "bmi", true);
2518 setFeatureEnabledImpl(Features, "bmi2", true);
2519 setFeatureEnabledImpl(Features, "rtm", true);
2520 setFeatureEnabledImpl(Features, "fma", true);
2521 setFeatureEnabledImpl(Features, "rdrnd", true);
2522 setFeatureEnabledImpl(Features, "f16c", true);
2523 setFeatureEnabledImpl(Features, "fsgsbase", true);
2524 setFeatureEnabledImpl(Features, "aes", true);
2525 setFeatureEnabledImpl(Features, "pclmul", true);
2526 setFeatureEnabledImpl(Features, "cx16", true);
2532 setFeatureEnabledImpl(Features, "3dnow", true);
2535 case CK_AthlonThunderbird:
2537 setFeatureEnabledImpl(Features, "3dnowa", true);
2542 setFeatureEnabledImpl(Features, "sse", true);
2543 setFeatureEnabledImpl(Features, "3dnowa", true);
2549 setFeatureEnabledImpl(Features, "sse2", true);
2550 setFeatureEnabledImpl(Features, "3dnowa", true);
2553 setFeatureEnabledImpl(Features, "sse4a", true);
2554 setFeatureEnabledImpl(Features, "lzcnt", true);
2555 setFeatureEnabledImpl(Features, "popcnt", true);
2558 case CK_OpteronSSE3:
2559 case CK_Athlon64SSE3:
2560 setFeatureEnabledImpl(Features, "sse3", true);
2561 setFeatureEnabledImpl(Features, "3dnowa", true);
2564 setFeatureEnabledImpl(Features, "avx", true);
2565 setFeatureEnabledImpl(Features, "aes", true);
2566 setFeatureEnabledImpl(Features, "pclmul", true);
2567 setFeatureEnabledImpl(Features, "bmi", true);
2568 setFeatureEnabledImpl(Features, "f16c", true);
2571 setFeatureEnabledImpl(Features, "ssse3", true);
2572 setFeatureEnabledImpl(Features, "sse4a", true);
2573 setFeatureEnabledImpl(Features, "lzcnt", true);
2574 setFeatureEnabledImpl(Features, "popcnt", true);
2575 setFeatureEnabledImpl(Features, "prfchw", true);
2576 setFeatureEnabledImpl(Features, "cx16", true);
2579 setFeatureEnabledImpl(Features, "avx2", true);
2580 setFeatureEnabledImpl(Features, "bmi2", true);
2583 setFeatureEnabledImpl(Features, "fsgsbase", true);
2586 setFeatureEnabledImpl(Features, "bmi", true);
2587 setFeatureEnabledImpl(Features, "fma", true);
2588 setFeatureEnabledImpl(Features, "f16c", true);
2589 setFeatureEnabledImpl(Features, "tbm", true);
2592 // xop implies avx, sse4a and fma4.
2593 setFeatureEnabledImpl(Features, "xop", true);
2594 setFeatureEnabledImpl(Features, "lzcnt", true);
2595 setFeatureEnabledImpl(Features, "aes", true);
2596 setFeatureEnabledImpl(Features, "pclmul", true);
2597 setFeatureEnabledImpl(Features, "prfchw", true);
2598 setFeatureEnabledImpl(Features, "cx16", true);
2603 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2604 X86SSEEnum Level, bool Enabled) {
2608 Features["avx512f"] = true;
2610 Features["avx2"] = true;
2612 Features["avx"] = true;
2614 Features["sse4.2"] = true;
2616 Features["sse4.1"] = true;
2618 Features["ssse3"] = true;
2620 Features["sse3"] = true;
2622 Features["sse2"] = true;
2624 Features["sse"] = true;
2634 Features["sse"] = false;
2636 Features["sse2"] = Features["pclmul"] = Features["aes"] =
2637 Features["sha"] = false;
2639 Features["sse3"] = false;
2640 setXOPLevel(Features, NoXOP, false);
2642 Features["ssse3"] = false;
2644 Features["sse4.1"] = false;
2646 Features["sse4.2"] = false;
2648 Features["fma"] = Features["avx"] = Features["f16c"] = false;
2649 setXOPLevel(Features, FMA4, false);
2651 Features["avx2"] = false;
2653 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2654 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2655 Features["avx512vl"] = false;
2659 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2660 MMX3DNowEnum Level, bool Enabled) {
2663 case AMD3DNowAthlon:
2664 Features["3dnowa"] = true;
2666 Features["3dnow"] = true;
2668 Features["mmx"] = true;
2678 Features["mmx"] = false;
2680 Features["3dnow"] = false;
2681 case AMD3DNowAthlon:
2682 Features["3dnowa"] = false;
2686 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2691 Features["xop"] = true;
2693 Features["fma4"] = true;
2694 setSSELevel(Features, AVX, true);
2696 Features["sse4a"] = true;
2697 setSSELevel(Features, SSE3, true);
2707 Features["sse4a"] = false;
2709 Features["fma4"] = false;
2711 Features["xop"] = false;
2715 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2716 StringRef Name, bool Enabled) {
2717 Features[Name] = Enabled;
2719 if (Name == "mmx") {
2720 setMMXLevel(Features, MMX, Enabled);
2721 } else if (Name == "sse") {
2722 setSSELevel(Features, SSE1, Enabled);
2723 } else if (Name == "sse2") {
2724 setSSELevel(Features, SSE2, Enabled);
2725 } else if (Name == "sse3") {
2726 setSSELevel(Features, SSE3, Enabled);
2727 } else if (Name == "ssse3") {
2728 setSSELevel(Features, SSSE3, Enabled);
2729 } else if (Name == "sse4.2") {
2730 setSSELevel(Features, SSE42, Enabled);
2731 } else if (Name == "sse4.1") {
2732 setSSELevel(Features, SSE41, Enabled);
2733 } else if (Name == "3dnow") {
2734 setMMXLevel(Features, AMD3DNow, Enabled);
2735 } else if (Name == "3dnowa") {
2736 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2737 } else if (Name == "aes") {
2739 setSSELevel(Features, SSE2, Enabled);
2740 } else if (Name == "pclmul") {
2742 setSSELevel(Features, SSE2, Enabled);
2743 } else if (Name == "avx") {
2744 setSSELevel(Features, AVX, Enabled);
2745 } else if (Name == "avx2") {
2746 setSSELevel(Features, AVX2, Enabled);
2747 } else if (Name == "avx512f") {
2748 setSSELevel(Features, AVX512F, Enabled);
2749 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2750 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2752 setSSELevel(Features, AVX512F, Enabled);
2753 } else if (Name == "fma") {
2755 setSSELevel(Features, AVX, Enabled);
2756 } else if (Name == "fma4") {
2757 setXOPLevel(Features, FMA4, Enabled);
2758 } else if (Name == "xop") {
2759 setXOPLevel(Features, XOP, Enabled);
2760 } else if (Name == "sse4a") {
2761 setXOPLevel(Features, SSE4A, Enabled);
2762 } else if (Name == "f16c") {
2764 setSSELevel(Features, AVX, Enabled);
2765 } else if (Name == "sha") {
2767 setSSELevel(Features, SSE2, Enabled);
2771 /// handleTargetFeatures - Perform initialization based on the user
2772 /// configured set of features.
2773 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2774 DiagnosticsEngine &Diags) {
2775 // Remember the maximum enabled sselevel.
2776 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2777 // Ignore disabled features.
2778 if (Features[i][0] == '-')
2781 StringRef Feature = StringRef(Features[i]).substr(1);
2783 if (Feature == "aes") {
2788 if (Feature == "pclmul") {
2793 if (Feature == "lzcnt") {
2798 if (Feature == "rdrnd") {
2803 if (Feature == "fsgsbase") {
2808 if (Feature == "bmi") {
2813 if (Feature == "bmi2") {
2818 if (Feature == "popcnt") {
2823 if (Feature == "rtm") {
2828 if (Feature == "prfchw") {
2833 if (Feature == "rdseed") {
2838 if (Feature == "adx") {
2843 if (Feature == "tbm") {
2848 if (Feature == "fma") {
2853 if (Feature == "f16c") {
2858 if (Feature == "avx512cd") {
2863 if (Feature == "avx512er") {
2868 if (Feature == "avx512pf") {
2873 if (Feature == "avx512dq") {
2878 if (Feature == "avx512bw") {
2883 if (Feature == "avx512vl") {
2888 if (Feature == "sha") {
2893 if (Feature == "cx16") {
2898 assert(Features[i][0] == '+' && "Invalid target feature!");
2899 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2900 .Case("avx512f", AVX512F)
2903 .Case("sse4.2", SSE42)
2904 .Case("sse4.1", SSE41)
2905 .Case("ssse3", SSSE3)
2910 SSELevel = std::max(SSELevel, Level);
2912 MMX3DNowEnum ThreeDNowLevel =
2913 llvm::StringSwitch<MMX3DNowEnum>(Feature)
2914 .Case("3dnowa", AMD3DNowAthlon)
2915 .Case("3dnow", AMD3DNow)
2917 .Default(NoMMX3DNow);
2918 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2920 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2923 .Case("sse4a", SSE4A)
2925 XOPLevel = std::max(XOPLevel, XLevel);
2928 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2929 // Can't do this earlier because we need to be able to explicitly enable
2930 // popcnt and still disable sse4.2.
2931 if (!HasPOPCNT && SSELevel >= SSE42 &&
2932 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2934 Features.push_back("+popcnt");
2937 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2938 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2939 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2941 Features.push_back("+prfchw");
2944 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2945 // matches the selected sse level.
2946 if (FPMath == FP_SSE && SSELevel < SSE1) {
2947 Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2949 } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2950 Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2954 // Don't tell the backend if we're turning off mmx; it will end up disabling
2955 // SSE, which we don't want.
2956 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2958 std::vector<std::string>::iterator it;
2959 it = std::find(Features.begin(), Features.end(), "-mmx");
2960 if (it != Features.end())
2962 else if (SSELevel > NoSSE)
2963 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2967 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2968 /// definitions for this particular subtarget.
2969 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2970 MacroBuilder &Builder) const {
2971 // Target identification.
2972 if (getTriple().getArch() == llvm::Triple::x86_64) {
2973 Builder.defineMacro("__amd64__");
2974 Builder.defineMacro("__amd64");
2975 Builder.defineMacro("__x86_64");
2976 Builder.defineMacro("__x86_64__");
2977 if (getTriple().getArchName() == "x86_64h") {
2978 Builder.defineMacro("__x86_64h");
2979 Builder.defineMacro("__x86_64h__");
2982 DefineStd(Builder, "i386", Opts);
2985 // Subtarget options.
2986 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2987 // truly should be based on -mtune options.
2992 // The rest are coming from the i386 define above.
2993 Builder.defineMacro("__tune_i386__");
2999 defineCPUMacros(Builder, "i486");
3002 Builder.defineMacro("__pentium_mmx__");
3003 Builder.defineMacro("__tune_pentium_mmx__");
3007 defineCPUMacros(Builder, "i586");
3008 defineCPUMacros(Builder, "pentium");
3013 Builder.defineMacro("__tune_pentium3__");
3017 Builder.defineMacro("__tune_pentium2__");
3020 Builder.defineMacro("__tune_i686__");
3021 Builder.defineMacro("__tune_pentiumpro__");
3024 Builder.defineMacro("__i686");
3025 Builder.defineMacro("__i686__");
3026 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3027 Builder.defineMacro("__pentiumpro");
3028 Builder.defineMacro("__pentiumpro__");
3032 defineCPUMacros(Builder, "pentium4");
3037 defineCPUMacros(Builder, "nocona");
3041 defineCPUMacros(Builder, "core2");
3044 defineCPUMacros(Builder, "atom");
3047 defineCPUMacros(Builder, "slm");
3051 case CK_SandyBridge:
3055 // FIXME: Historically, we defined this legacy name, it would be nice to
3056 // remove it at some point. We've never exposed fine-grained names for
3057 // recent primary x86 CPUs, and we should keep it that way.
3058 defineCPUMacros(Builder, "corei7");
3061 // FIXME: Historically, we defined this legacy name, it would be nice to
3062 // remove it at some point. This is the only fine-grained CPU macro in the
3063 // main intel CPU line, and it would be better to not have these and force
3064 // people to use ISA macros.
3065 defineCPUMacros(Builder, "skx");
3068 defineCPUMacros(Builder, "knl");
3071 Builder.defineMacro("__k6_2__");
3072 Builder.defineMacro("__tune_k6_2__");
3075 if (CPU != CK_K6_2) { // In case of fallthrough
3076 // FIXME: GCC may be enabling these in cases where some other k6
3077 // architecture is specified but -m3dnow is explicitly provided. The
3078 // exact semantics need to be determined and emulated here.
3079 Builder.defineMacro("__k6_3__");
3080 Builder.defineMacro("__tune_k6_3__");
3084 defineCPUMacros(Builder, "k6");
3087 case CK_AthlonThunderbird:
3091 defineCPUMacros(Builder, "athlon");
3092 if (SSELevel != NoSSE) {
3093 Builder.defineMacro("__athlon_sse__");
3094 Builder.defineMacro("__tune_athlon_sse__");
3101 case CK_OpteronSSE3:
3103 case CK_Athlon64SSE3:
3105 defineCPUMacros(Builder, "k8");
3108 defineCPUMacros(Builder, "amdfam10");
3111 defineCPUMacros(Builder, "btver1");
3114 defineCPUMacros(Builder, "btver2");
3117 defineCPUMacros(Builder, "bdver1");
3120 defineCPUMacros(Builder, "bdver2");
3123 defineCPUMacros(Builder, "bdver3");
3126 defineCPUMacros(Builder, "bdver4");
3129 defineCPUMacros(Builder, "geode");
3133 // Target properties.
3134 Builder.defineMacro("__REGISTER_PREFIX__", "");
3136 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3137 // functions in glibc header files that use FP Stack inline asm which the
3138 // backend can't deal with (PR879).
3139 Builder.defineMacro("__NO_MATH_INLINES");
3142 Builder.defineMacro("__AES__");
3145 Builder.defineMacro("__PCLMUL__");
3148 Builder.defineMacro("__LZCNT__");
3151 Builder.defineMacro("__RDRND__");
3154 Builder.defineMacro("__FSGSBASE__");
3157 Builder.defineMacro("__BMI__");
3160 Builder.defineMacro("__BMI2__");
3163 Builder.defineMacro("__POPCNT__");
3166 Builder.defineMacro("__RTM__");
3169 Builder.defineMacro("__PRFCHW__");
3172 Builder.defineMacro("__RDSEED__");
3175 Builder.defineMacro("__ADX__");
3178 Builder.defineMacro("__TBM__");
3182 Builder.defineMacro("__XOP__");
3184 Builder.defineMacro("__FMA4__");
3186 Builder.defineMacro("__SSE4A__");
3192 Builder.defineMacro("__FMA__");
3195 Builder.defineMacro("__F16C__");
3198 Builder.defineMacro("__AVX512CD__");
3200 Builder.defineMacro("__AVX512ER__");
3202 Builder.defineMacro("__AVX512PF__");
3204 Builder.defineMacro("__AVX512DQ__");
3206 Builder.defineMacro("__AVX512BW__");
3208 Builder.defineMacro("__AVX512VL__");
3211 Builder.defineMacro("__SHA__");
3214 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3216 // Each case falls through to the previous one here.
3219 Builder.defineMacro("__AVX512F__");
3221 Builder.defineMacro("__AVX2__");
3223 Builder.defineMacro("__AVX__");
3225 Builder.defineMacro("__SSE4_2__");
3227 Builder.defineMacro("__SSE4_1__");
3229 Builder.defineMacro("__SSSE3__");
3231 Builder.defineMacro("__SSE3__");
3233 Builder.defineMacro("__SSE2__");
3234 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
3236 Builder.defineMacro("__SSE__");
3237 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
3242 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3252 Builder.defineMacro("_M_IX86_FP", Twine(2));
3255 Builder.defineMacro("_M_IX86_FP", Twine(1));
3258 Builder.defineMacro("_M_IX86_FP", Twine(0));
3262 // Each case falls through to the previous one here.
3263 switch (MMX3DNowLevel) {
3264 case AMD3DNowAthlon:
3265 Builder.defineMacro("__3dNOW_A__");
3267 Builder.defineMacro("__3dNOW__");
3269 Builder.defineMacro("__MMX__");
3274 if (CPU >= CK_i486) {
3275 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3276 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3277 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3280 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3283 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3284 return llvm::StringSwitch<bool>(Feature)
3285 .Case("aes", HasAES)
3286 .Case("avx", SSELevel >= AVX)
3287 .Case("avx2", SSELevel >= AVX2)
3288 .Case("avx512f", SSELevel >= AVX512F)
3289 .Case("avx512cd", HasAVX512CD)
3290 .Case("avx512er", HasAVX512ER)
3291 .Case("avx512pf", HasAVX512PF)
3292 .Case("avx512dq", HasAVX512DQ)
3293 .Case("avx512bw", HasAVX512BW)
3294 .Case("avx512vl", HasAVX512VL)
3295 .Case("bmi", HasBMI)
3296 .Case("bmi2", HasBMI2)
3297 .Case("cx16", HasCX16)
3298 .Case("f16c", HasF16C)
3299 .Case("fma", HasFMA)
3300 .Case("fma4", XOPLevel >= FMA4)
3301 .Case("fsgsbase", HasFSGSBASE)
3302 .Case("lzcnt", HasLZCNT)
3303 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3304 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3305 .Case("mmx", MMX3DNowLevel >= MMX)
3306 .Case("pclmul", HasPCLMUL)
3307 .Case("popcnt", HasPOPCNT)
3308 .Case("prfchw", HasPRFCHW)
3309 .Case("rdrnd", HasRDRND)
3310 .Case("rdseed", HasRDSEED)
3311 .Case("rtm", HasRTM)
3312 .Case("sha", HasSHA)
3313 .Case("sse", SSELevel >= SSE1)
3314 .Case("sse2", SSELevel >= SSE2)
3315 .Case("sse3", SSELevel >= SSE3)
3316 .Case("ssse3", SSELevel >= SSSE3)
3317 .Case("sse4.1", SSELevel >= SSE41)
3318 .Case("sse4.2", SSELevel >= SSE42)
3319 .Case("sse4a", XOPLevel >= SSE4A)
3320 .Case("tbm", HasTBM)
3322 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3323 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3324 .Case("xop", XOPLevel >= XOP)
3329 X86TargetInfo::validateAsmConstraint(const char *&Name,
3330 TargetInfo::ConstraintInfo &Info) const {
3332 default: return false;
3334 Info.setRequiresImmediate(0, 31);
3337 Info.setRequiresImmediate(0, 63);
3340 Info.setRequiresImmediate(-128, 127);
3343 // FIXME: properly analyze this constraint:
3344 // must be one of 0xff, 0xffff, or 0xffffffff
3347 Info.setRequiresImmediate(0, 3);
3350 Info.setRequiresImmediate(0, 255);
3353 Info.setRequiresImmediate(0, 127);
3355 case 'Y': // first letter of a pair:
3356 switch (*(Name+1)) {
3357 default: return false;
3358 case '0': // First SSE register.
3359 case 't': // Any SSE register, when SSE2 is enabled.
3360 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
3361 case 'm': // any MMX register, when inter-unit moves enabled.
3362 break; // falls through to setAllowsRegister.
3364 case 'f': // any x87 floating point stack register.
3365 // Constraint 'f' cannot be used for output operands.
3366 if (Info.ConstraintStr[0] == '=')
3369 Info.setAllowsRegister();
3377 case 'A': // edx:eax.
3378 case 't': // top of floating point stack.
3379 case 'u': // second from top of floating point stack.
3380 case 'q': // Any register accessible as [r]l: a, b, c, and d.
3381 case 'y': // Any MMX register.
3382 case 'x': // Any SSE register.
3383 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3384 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3385 case 'l': // "Index" registers: any general register that can be used as an
3386 // index in a base+index memory access.
3387 Info.setAllowsRegister();
3389 case 'C': // SSE floating point constant.
3390 case 'G': // x87 floating point constant.
3391 case 'e': // 32-bit signed integer constant for use with zero-extending
3392 // x86_64 instructions.
3393 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3394 // x86_64 instructions.
3399 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3400 unsigned Size) const {
3401 // Strip off constraint modifiers.
3402 while (Constraint[0] == '=' ||
3403 Constraint[0] == '+' ||
3404 Constraint[0] == '&')
3405 Constraint = Constraint.substr(1);
3407 return validateOperandSize(Constraint, Size);
3410 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3411 unsigned Size) const {
3412 return validateOperandSize(Constraint, Size);
3415 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3416 unsigned Size) const {
3417 switch (Constraint[0]) {
3426 // 256-bit ymm registers can be used if target supports AVX.
3427 return Size <= (SSELevel >= AVX ? 256U : 128U);
3434 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3435 switch (*Constraint) {
3436 case 'a': return std::string("{ax}");
3437 case 'b': return std::string("{bx}");
3438 case 'c': return std::string("{cx}");
3439 case 'd': return std::string("{dx}");
3440 case 'S': return std::string("{si}");
3441 case 'D': return std::string("{di}");
3442 case 'p': // address
3443 return std::string("im");
3444 case 't': // top of floating point stack.
3445 return std::string("{st}");
3446 case 'u': // second from top of floating point stack.
3447 return std::string("{st(1)}"); // second from top of floating point stack.
3449 return std::string(1, *Constraint);
3453 // X86-32 generic target
3454 class X86_32TargetInfo : public X86TargetInfo {
3456 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3457 DoubleAlign = LongLongAlign = 32;
3458 LongDoubleWidth = 96;
3459 LongDoubleAlign = 32;
3460 SuitableAlign = 128;
3461 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3462 SizeType = UnsignedInt;
3463 PtrDiffType = SignedInt;
3464 IntPtrType = SignedInt;
3467 // Use fpret for all types.
3468 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3469 (1 << TargetInfo::Double) |
3470 (1 << TargetInfo::LongDouble));
3472 // x86-32 has atomics up to 8 bytes
3473 // FIXME: Check that we actually have cmpxchg8b before setting
3474 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3475 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3477 BuiltinVaListKind getBuiltinVaListKind() const override {
3478 return TargetInfo::CharPtrBuiltinVaList;
3481 int getEHDataRegisterNumber(unsigned RegNo) const override {
3482 if (RegNo == 0) return 0;
3483 if (RegNo == 1) return 2;
3486 bool validateOperandSize(StringRef Constraint,
3487 unsigned Size) const override {
3488 switch (Constraint[0]) {
3504 return X86TargetInfo::validateOperandSize(Constraint, Size);
3508 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3510 NetBSDI386TargetInfo(const llvm::Triple &Triple)
3511 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3513 unsigned getFloatEvalMethod() const override {
3514 unsigned Major, Minor, Micro;
3515 getTriple().getOSVersion(Major, Minor, Micro);
3516 // New NetBSD uses the default rounding mode.
3517 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3518 return X86_32TargetInfo::getFloatEvalMethod();
3519 // NetBSD before 6.99.26 defaults to "double" rounding.
3524 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3526 OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3527 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3528 SizeType = UnsignedLong;
3529 IntPtrType = SignedLong;
3530 PtrDiffType = SignedLong;
3534 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3536 BitrigI386TargetInfo(const llvm::Triple &Triple)
3537 : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3538 SizeType = UnsignedLong;
3539 IntPtrType = SignedLong;
3540 PtrDiffType = SignedLong;
3544 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3546 DarwinI386TargetInfo(const llvm::Triple &Triple)
3547 : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3548 LongDoubleWidth = 128;
3549 LongDoubleAlign = 128;
3550 SuitableAlign = 128;
3551 MaxVectorAlign = 256;
3552 SizeType = UnsignedLong;
3553 IntPtrType = SignedLong;
3554 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3555 HasAlignMac68kSupport = true;
3560 // x86-32 Windows target
3561 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3563 WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3564 : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3565 WCharType = UnsignedShort;
3566 DoubleAlign = LongLongAlign = 64;
3568 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3569 DescriptionString = IsWinCOFF
3570 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
3571 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3573 void getTargetDefines(const LangOptions &Opts,
3574 MacroBuilder &Builder) const override {
3575 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3579 // x86-32 Windows Visual Studio target
3580 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3582 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3583 : WindowsX86_32TargetInfo(Triple) {
3584 LongDoubleWidth = LongDoubleAlign = 64;
3585 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3587 void getTargetDefines(const LangOptions &Opts,
3588 MacroBuilder &Builder) const override {
3589 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3590 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3591 // The value of the following reflects processor type.
3592 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3593 // We lost the original triple, so we use the default.
3594 Builder.defineMacro("_M_IX86", "600");
3597 } // end anonymous namespace
3599 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3600 Builder.defineMacro("__MSVCRT__");
3601 Builder.defineMacro("__MINGW32__");
3603 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports
3604 // __declspec natively under -fms-extensions, but we define a no-op __declspec
3605 // macro anyway for pre-processor compatibility.
3606 if (Opts.MicrosoftExt)
3607 Builder.defineMacro("__declspec", "__declspec");
3609 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3611 if (!Opts.MicrosoftExt) {
3612 // Provide macros for all the calling convention keywords. Provide both
3613 // single and double underscore prefixed variants. These are available on
3614 // x64 as well as x86, even though they have no effect.
3615 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3616 for (const char *CC : CCs) {
3617 std::string GCCSpelling = "__attribute__((__";
3619 GCCSpelling += "__))";
3620 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3621 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3627 // x86-32 MinGW target
3628 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3630 MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3631 : WindowsX86_32TargetInfo(Triple) {}
3632 void getTargetDefines(const LangOptions &Opts,
3633 MacroBuilder &Builder) const override {
3634 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3635 DefineStd(Builder, "WIN32", Opts);
3636 DefineStd(Builder, "WINNT", Opts);
3637 Builder.defineMacro("_X86_");
3638 addMinGWDefines(Opts, Builder);
3642 // x86-32 Cygwin target
3643 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3645 CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3646 : X86_32TargetInfo(Triple) {
3647 TLSSupported = false;
3648 WCharType = UnsignedShort;
3649 DoubleAlign = LongLongAlign = 64;
3650 DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3652 void getTargetDefines(const LangOptions &Opts,
3653 MacroBuilder &Builder) const override {
3654 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3655 Builder.defineMacro("_X86_");
3656 Builder.defineMacro("__CYGWIN__");
3657 Builder.defineMacro("__CYGWIN32__");
3658 DefineStd(Builder, "unix", Opts);
3660 Builder.defineMacro("_GNU_SOURCE");
3664 // x86-32 Haiku target
3665 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3667 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3668 SizeType = UnsignedLong;
3669 IntPtrType = SignedLong;
3670 PtrDiffType = SignedLong;
3671 ProcessIDType = SignedLong;
3672 this->UserLabelPrefix = "";
3673 this->TLSSupported = false;
3675 void getTargetDefines(const LangOptions &Opts,
3676 MacroBuilder &Builder) const override {
3677 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3678 Builder.defineMacro("__INTEL__");
3679 Builder.defineMacro("__HAIKU__");
3684 template<typename Target>
3685 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3687 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3688 MacroBuilder &Builder) const override {
3689 // RTEMS defines; list based off of gcc output
3691 Builder.defineMacro("__rtems__");
3692 Builder.defineMacro("__ELF__");
3696 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3697 this->UserLabelPrefix = "";
3699 switch (Triple.getArch()) {
3701 case llvm::Triple::x86:
3702 // this->MCountName = ".mcount";
3704 case llvm::Triple::mips:
3705 case llvm::Triple::mipsel:
3706 case llvm::Triple::ppc:
3707 case llvm::Triple::ppc64:
3708 case llvm::Triple::ppc64le:
3709 // this->MCountName = "_mcount";
3711 case llvm::Triple::arm:
3712 // this->MCountName = "__mcount";
3718 // x86-32 RTEMS target
3719 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3721 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3722 SizeType = UnsignedLong;
3723 IntPtrType = SignedLong;
3724 PtrDiffType = SignedLong;
3725 this->UserLabelPrefix = "";
3727 void getTargetDefines(const LangOptions &Opts,
3728 MacroBuilder &Builder) const override {
3729 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3730 Builder.defineMacro("__INTEL__");
3731 Builder.defineMacro("__rtems__");
3735 // x86-64 generic target
3736 class X86_64TargetInfo : public X86TargetInfo {
3738 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3739 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3741 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3742 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3743 LongDoubleWidth = 128;
3744 LongDoubleAlign = 128;
3745 LargeArrayMinWidth = 128;
3746 LargeArrayAlign = 128;
3747 SuitableAlign = 128;
3748 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
3749 PtrDiffType = IsX32 ? SignedInt : SignedLong;
3750 IntPtrType = IsX32 ? SignedInt : SignedLong;
3751 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
3752 Int64Type = IsX32 ? SignedLongLong : SignedLong;
3755 // Pointers are 32-bit in x32.
3756 DescriptionString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3758 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
3759 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3761 // Use fpret only for long double.
3762 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3764 // Use fp2ret for _Complex long double.
3765 ComplexLongDoubleUsesFP2Ret = true;
3767 // x86-64 has atomics up to 16 bytes.
3768 MaxAtomicPromoteWidth = 128;
3769 MaxAtomicInlineWidth = 128;
3771 BuiltinVaListKind getBuiltinVaListKind() const override {
3772 return TargetInfo::X86_64ABIBuiltinVaList;
3775 int getEHDataRegisterNumber(unsigned RegNo) const override {
3776 if (RegNo == 0) return 0;
3777 if (RegNo == 1) return 1;
3781 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3782 return (CC == CC_C ||
3783 CC == CC_X86VectorCall ||
3784 CC == CC_IntelOclBicc ||
3785 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3788 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3792 // for x32 we need it here explicitly
3793 bool hasInt128Type() const override { return true; }
3796 // x86-64 Windows target
3797 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3799 WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3800 : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3801 WCharType = UnsignedShort;
3802 LongWidth = LongAlign = 32;
3803 DoubleAlign = LongLongAlign = 64;
3804 IntMaxType = SignedLongLong;
3805 Int64Type = SignedLongLong;
3806 SizeType = UnsignedLongLong;
3807 PtrDiffType = SignedLongLong;
3808 IntPtrType = SignedLongLong;
3809 this->UserLabelPrefix = "";
3812 void getTargetDefines(const LangOptions &Opts,
3813 MacroBuilder &Builder) const override {
3814 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3815 Builder.defineMacro("_WIN64");
3818 BuiltinVaListKind getBuiltinVaListKind() const override {
3819 return TargetInfo::CharPtrBuiltinVaList;
3822 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3825 case CC_X86ThisCall:
3826 case CC_X86FastCall:
3829 case CC_X86VectorCall:
3830 case CC_IntelOclBicc:
3834 return CCCR_Warning;
3839 // x86-64 Windows Visual Studio target
3840 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3842 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3843 : WindowsX86_64TargetInfo(Triple) {
3844 LongDoubleWidth = LongDoubleAlign = 64;
3845 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3847 void getTargetDefines(const LangOptions &Opts,
3848 MacroBuilder &Builder) const override {
3849 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3850 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3851 Builder.defineMacro("_M_X64");
3852 Builder.defineMacro("_M_AMD64");
3856 // x86-64 MinGW target
3857 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3859 MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3860 : WindowsX86_64TargetInfo(Triple) {}
3861 void getTargetDefines(const LangOptions &Opts,
3862 MacroBuilder &Builder) const override {
3863 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3864 DefineStd(Builder, "WIN64", Opts);
3865 Builder.defineMacro("__MINGW64__");
3866 addMinGWDefines(Opts, Builder);
3868 // GCC defines this macro when it is using __gxx_personality_seh0.
3869 if (!Opts.SjLjExceptions)
3870 Builder.defineMacro("__SEH__");
3874 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3876 DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3877 : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3878 Int64Type = SignedLongLong;
3879 MaxVectorAlign = 256;
3880 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3881 llvm::Triple T = llvm::Triple(Triple);
3883 UseSignedCharForObjCBool = false;
3884 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3888 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3890 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3891 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3892 IntMaxType = SignedLongLong;
3893 Int64Type = SignedLongLong;
3897 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3899 BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3900 : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3901 IntMaxType = SignedLongLong;
3902 Int64Type = SignedLongLong;
3906 class ARMTargetInfo : public TargetInfo {
3907 // Possible FPU choices.
3916 // Possible HWDiv features.
3918 HWDivThumb = (1 << 0),
3922 static bool FPUModeIsVFP(FPUMode Mode) {
3923 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3926 static const TargetInfo::GCCRegAlias GCCRegAliases[];
3927 static const char * const GCCRegNames[];
3929 std::string ABI, CPU;
3939 unsigned IsAAPCS : 1;
3940 unsigned IsThumb : 1;
3943 // Initialized via features.
3944 unsigned SoftFloat : 1;
3945 unsigned SoftFloatABI : 1;
3948 unsigned Crypto : 1;
3950 // ACLE 6.5.1 Hardware floating point
3952 HW_FP_HP = (1 << 1), /// half (16-bit)
3953 HW_FP_SP = (1 << 2), /// single (32-bit)
3954 HW_FP_DP = (1 << 3), /// double (64-bit)
3958 static const Builtin::Info BuiltinInfo[];
3960 static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3961 StringRef ArchName = T.getArchName();
3962 if (T.getArch() == llvm::Triple::arm ||
3963 T.getArch() == llvm::Triple::armeb) {
3964 StringRef VersionStr;
3965 if (ArchName.startswith("armv"))
3966 VersionStr = ArchName.substr(4, 1);
3967 else if (ArchName.startswith("armebv"))
3968 VersionStr = ArchName.substr(6, 1);
3972 if (VersionStr.getAsInteger(10, Version))
3974 return Version >= 6;
3976 assert(T.getArch() == llvm::Triple::thumb ||
3977 T.getArch() == llvm::Triple::thumbeb);
3978 StringRef VersionStr;
3979 if (ArchName.startswith("thumbv"))
3980 VersionStr = ArchName.substr(6, 1);
3981 else if (ArchName.startswith("thumbebv"))
3982 VersionStr = ArchName.substr(8, 1);
3986 if (VersionStr.getAsInteger(10, Version))
3988 return Version >= 7;
3991 void setABIAAPCS() {
3994 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
3995 const llvm::Triple &T = getTriple();
3997 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig.
3998 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
3999 T.getOS() == llvm::Triple::Bitrig)
4000 SizeType = UnsignedLong;
4002 SizeType = UnsignedInt;
4004 switch (T.getOS()) {
4005 case llvm::Triple::NetBSD:
4006 WCharType = SignedInt;
4008 case llvm::Triple::Win32:
4009 WCharType = UnsignedShort;
4011 case llvm::Triple::Linux:
4013 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
4014 WCharType = UnsignedInt;
4018 UseBitFieldTypeAlignment = true;
4020 ZeroLengthBitfieldBoundary = 0;
4022 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
4023 // so set preferred for small types to 32.
4024 if (T.isOSBinFormatMachO()) {
4026 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4027 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4028 } else if (T.isOSWindows()) {
4029 assert(!BigEndian && "Windows on ARM does not support big endian");
4030 DescriptionString = "e"
4038 } else if (T.isOSNaCl()) {
4039 assert(!BigEndian && "NaCl on ARM does not support big endian");
4040 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
4043 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4044 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4047 // FIXME: Enumerated types are variable width in straight AAPCS.
4051 const llvm::Triple &T = getTriple();
4055 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
4057 // size_t is unsigned int on FreeBSD.
4058 if (T.getOS() == llvm::Triple::FreeBSD)
4059 SizeType = UnsignedInt;
4061 SizeType = UnsignedLong;
4063 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
4064 WCharType = SignedInt;
4066 // Do not respect the alignment of bit-field types when laying out
4067 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
4068 UseBitFieldTypeAlignment = false;
4070 /// gcc forces the alignment to 4 bytes, regardless of the type of the
4071 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
4073 ZeroLengthBitfieldBoundary = 32;
4075 if (T.isOSBinFormatMachO())
4078 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4079 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4083 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4084 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4086 // FIXME: Override "preferred align" for double and long long.
4090 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
4091 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
4092 IsAAPCS(true), HW_FP(0) {
4093 BigEndian = IsBigEndian;
4095 switch (getTriple().getOS()) {
4096 case llvm::Triple::NetBSD:
4097 PtrDiffType = SignedLong;
4100 PtrDiffType = SignedInt;
4104 // {} in inline assembly are neon specifiers, not assembly variant
4106 NoAsmVariants = true;
4108 // FIXME: Should we just treat this as a feature?
4109 IsThumb = getTriple().getArchName().startswith("thumb");
4111 // FIXME: This duplicates code from the driver that sets the -target-abi
4112 // option - this code is used if -target-abi isn't passed and should
4113 // be unified in some way.
4114 if (Triple.isOSBinFormatMachO()) {
4115 // The backend is hardwired to assume AAPCS for M-class processors, ensure
4116 // the frontend matches that.
4117 if (Triple.getEnvironment() == llvm::Triple::EABI ||
4118 Triple.getOS() == llvm::Triple::UnknownOS ||
4119 StringRef(CPU).startswith("cortex-m")) {
4124 } else if (Triple.isOSWindows()) {
4125 // FIXME: this is invalid for WindowsCE
4128 // Select the default based on the platform.
4129 switch (Triple.getEnvironment()) {
4130 case llvm::Triple::Android:
4131 case llvm::Triple::GNUEABI:
4132 case llvm::Triple::GNUEABIHF:
4133 setABI("aapcs-linux");
4135 case llvm::Triple::EABIHF:
4136 case llvm::Triple::EABI:
4139 case llvm::Triple::GNU:
4143 if (Triple.getOS() == llvm::Triple::NetBSD)
4151 // ARM targets default to using the ARM C++ ABI.
4152 TheCXXABI.set(TargetCXXABI::GenericARM);
4154 // ARM has atomics up to 8 bytes
4155 MaxAtomicPromoteWidth = 64;
4156 if (shouldUseInlineAtomic(getTriple()))
4157 MaxAtomicInlineWidth = 64;
4159 // Do force alignment of members that follow zero length bitfields. If
4160 // the alignment of the zero-length bitfield is greater than the member
4161 // that follows it, `bar', `bar' will be aligned as the type of the
4162 // zero length bitfield.
4163 UseZeroLengthBitfieldAlignment = true;
4165 StringRef getABI() const override { return ABI; }
4166 bool setABI(const std::string &Name) override {
4169 // The defaults (above) are for AAPCS, check if we need to change them.
4171 // FIXME: We need support for -meabi... we could just mangle it into the
4173 if (Name == "apcs-gnu") {
4177 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
4184 // FIXME: This should be based on Arch attributes, not CPU names.
4185 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
4186 StringRef ArchName = getTriple().getArchName();
4188 llvm::ARMTargetParser::parseArch(
4189 llvm::ARMTargetParser::getCanonicalArchName(ArchName));
4190 bool IsV8 = (ArchKind == llvm::ARM::AK_ARMV8A ||
4191 ArchKind == llvm::ARM::AK_ARMV8_1A);
4193 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
4194 Features["vfp2"] = true;
4195 else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
4196 Features["vfp3"] = true;
4197 Features["neon"] = true;
4199 else if (CPU == "cortex-a5") {
4200 Features["vfp4"] = true;
4201 Features["neon"] = true;
4202 } else if (CPU == "swift" || CPU == "cortex-a7" ||
4203 CPU == "cortex-a12" || CPU == "cortex-a15" ||
4204 CPU == "cortex-a17" || CPU == "krait") {
4205 Features["vfp4"] = true;
4206 Features["neon"] = true;
4207 Features["hwdiv"] = true;
4208 Features["hwdiv-arm"] = true;
4209 } else if (CPU == "cyclone" || CPU == "cortex-a53" || CPU == "cortex-a57" ||
4210 CPU == "cortex-a72") {
4211 Features["fp-armv8"] = true;
4212 Features["neon"] = true;
4213 Features["hwdiv"] = true;
4214 Features["hwdiv-arm"] = true;
4215 Features["crc"] = true;
4216 Features["crypto"] = true;
4217 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || IsV8) {
4218 Features["hwdiv"] = true;
4219 Features["hwdiv-arm"] = true;
4220 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" ||
4221 CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") {
4222 Features["hwdiv"] = true;
4226 bool handleTargetFeatures(std::vector<std::string> &Features,
4227 DiagnosticsEngine &Diags) override {
4231 SoftFloat = SoftFloatABI = false;
4234 for (const auto &Feature : Features) {
4235 if (Feature == "+soft-float") {
4237 } else if (Feature == "+soft-float-abi") {
4238 SoftFloatABI = true;
4239 } else if (Feature == "+vfp2") {
4241 HW_FP = HW_FP_SP | HW_FP_DP;
4242 } else if (Feature == "+vfp3") {
4244 HW_FP = HW_FP_SP | HW_FP_DP;
4245 } else if (Feature == "+vfp4") {
4247 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4248 } else if (Feature == "+fp-armv8") {
4250 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4251 } else if (Feature == "+neon") {
4253 HW_FP = HW_FP_SP | HW_FP_DP;
4254 } else if (Feature == "+hwdiv") {
4255 HWDiv |= HWDivThumb;
4256 } else if (Feature == "+hwdiv-arm") {
4258 } else if (Feature == "+crc") {
4260 } else if (Feature == "+crypto") {
4262 } else if (Feature == "+fp-only-sp") {
4267 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4268 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4272 if (FPMath == FP_Neon)
4273 Features.push_back("+neonfp");
4274 else if (FPMath == FP_VFP)
4275 Features.push_back("-neonfp");
4277 // Remove front-end specific options which the backend handles differently.
4279 std::find(Features.begin(), Features.end(), "+soft-float-abi");
4280 if (Feature != Features.end())
4281 Features.erase(Feature);
4286 bool hasFeature(StringRef Feature) const override {
4287 return llvm::StringSwitch<bool>(Feature)
4289 .Case("softfloat", SoftFloat)
4290 .Case("thumb", IsThumb)
4291 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4292 .Case("hwdiv", HWDiv & HWDivThumb)
4293 .Case("hwdiv-arm", HWDiv & HWDivARM)
4296 // FIXME: Should we actually have some table instead of these switches?
4297 const char *getCPUDefineSuffix(StringRef Name) const {
4298 // FIXME: Use ARMTargetParser
4299 if(Name == "generic") {
4300 auto subarch = getTriple().getSubArch();
4302 case llvm::Triple::SubArchType::ARMSubArch_v8_1a:
4309 return llvm::StringSwitch<const char *>(Name)
4310 .Cases("arm8", "arm810", "4")
4311 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110",
4313 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
4314 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
4315 .Case("ep9312", "4T")
4316 .Cases("arm10tdmi", "arm1020t", "5T")
4317 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
4318 .Case("arm926ej-s", "5TEJ")
4319 .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
4320 .Cases("xscale", "iwmmxt", "5TE")
4321 .Case("arm1136j-s", "6J")
4322 .Case("arm1136jf-s", "6")
4323 .Cases("mpcorenovfp", "mpcore", "6K")
4324 .Cases("arm1176jz-s", "arm1176jzf-s", "6K")
4325 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
4326 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
4327 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4329 .Cases("cortex-r4", "cortex-r4f", "cortex-r5", "cortex-r7", "7R")
4330 .Case("swift", "7S")
4331 .Case("cyclone", "8A")
4332 .Cases("sc300", "cortex-m3", "7M")
4333 .Cases("cortex-m4", "cortex-m7", "7EM")
4334 .Cases("sc000", "cortex-m0", "cortex-m0plus", "cortex-m1", "6M")
4335 .Cases("cortex-a53", "cortex-a57", "cortex-a72", "8A")
4338 const char *getCPUProfile(StringRef Name) const {
4339 if(Name == "generic") {
4340 auto subarch = getTriple().getSubArch();
4342 case llvm::Triple::SubArchType::ARMSubArch_v8_1a:
4349 unsigned CPUArch = llvm::ARMTargetParser::parseCPUArch(Name);
4350 if (CPUArch == llvm::ARM::AK_INVALID)
4353 StringRef ArchName = llvm::ARMTargetParser::getArchName(CPUArch);
4354 switch(llvm::ARMTargetParser::parseArchProfile(ArchName)) {
4355 case llvm::ARM::PK_A:
4357 case llvm::ARM::PK_R:
4359 case llvm::ARM::PK_M:
4365 bool setCPU(const std::string &Name) override {
4366 if (!getCPUDefineSuffix(Name))
4369 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4370 StringRef Profile = getCPUProfile(Name);
4371 if (Profile == "M" && MaxAtomicInlineWidth) {
4372 MaxAtomicPromoteWidth = 32;
4373 MaxAtomicInlineWidth = 32;
4379 bool setFPMath(StringRef Name) override;
4380 bool supportsThumb(StringRef ArchName, StringRef CPUArch,
4381 unsigned CPUArchVer) const {
4382 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
4383 (CPUArch.find('M') != StringRef::npos);
4385 bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
4386 unsigned CPUArchVer) const {
4387 // We check both CPUArchVer and ArchName because when only triple is
4388 // specified, the default CPU is arm1136j-s.
4389 return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
4390 ArchName.endswith("v8.1a") ||
4391 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
4393 void getTargetDefines(const LangOptions &Opts,
4394 MacroBuilder &Builder) const override {
4395 // Target identification.
4396 Builder.defineMacro("__arm");
4397 Builder.defineMacro("__arm__");
4399 // Target properties.
4400 Builder.defineMacro("__REGISTER_PREFIX__", "");
4402 StringRef CPUArch = getCPUDefineSuffix(CPU);
4403 unsigned int CPUArchVer;
4404 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
4405 llvm_unreachable("Invalid char for architecture version number");
4406 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
4408 // ACLE 6.4.1 ARM/Thumb instruction set architecture
4409 StringRef CPUProfile = getCPUProfile(CPU);
4410 StringRef ArchName = getTriple().getArchName();
4412 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4413 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
4414 if (CPUArch[0] >= '8') {
4415 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4416 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4419 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
4420 // is not defined for the M-profile.
4421 // NOTE that the deffault profile is assumed to be 'A'
4422 if (CPUProfile.empty() || CPUProfile != "M")
4423 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4425 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4426 // Thumb ISA (including v6-M). It is set to 2 if the core supports the
4427 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4428 if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4429 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4430 else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
4431 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4433 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4434 // instruction set such as ARM or Thumb.
4435 Builder.defineMacro("__ARM_32BIT_STATE", "1");
4437 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4439 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4440 if (!CPUProfile.empty())
4441 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4443 // ACLE 6.5.1 Hardware Floating Point
4445 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4448 Builder.defineMacro("__ARM_ACLE", "200");
4450 // Subtarget options.
4452 // FIXME: It's more complicated than this and we don't really support
4454 // Windows on ARM does not "support" interworking
4455 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
4456 Builder.defineMacro("__THUMB_INTERWORK__");
4458 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4459 // Embedded targets on Darwin follow AAPCS, but not EABI.
4460 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4461 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4462 Builder.defineMacro("__ARM_EABI__");
4463 Builder.defineMacro("__ARM_PCS", "1");
4465 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4466 Builder.defineMacro("__ARM_PCS_VFP", "1");
4470 Builder.defineMacro("__SOFTFP__");
4472 if (CPU == "xscale")
4473 Builder.defineMacro("__XSCALE__");
4476 Builder.defineMacro("__THUMBEL__");
4477 Builder.defineMacro("__thumb__");
4478 if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4479 Builder.defineMacro("__thumb2__");
4481 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4482 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4484 // Note, this is always on in gcc, even though it doesn't make sense.
4485 Builder.defineMacro("__APCS_32__");
4487 if (FPUModeIsVFP((FPUMode) FPU)) {
4488 Builder.defineMacro("__VFP_FP__");
4490 Builder.defineMacro("__ARM_VFPV2__");
4492 Builder.defineMacro("__ARM_VFPV3__");
4494 Builder.defineMacro("__ARM_VFPV4__");
4497 // This only gets set when Neon instructions are actually available, unlike
4498 // the VFP define, hence the soft float and arch check. This is subtly
4499 // different from gcc, we follow the intent which was that it should be set
4500 // when Neon instructions are actually available.
4501 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
4502 Builder.defineMacro("__ARM_NEON");
4503 Builder.defineMacro("__ARM_NEON__");
4506 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4507 Opts.ShortWChar ? "2" : "4");
4509 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4510 Opts.ShortEnums ? "1" : "4");
4513 Builder.defineMacro("__ARM_FEATURE_CRC32");
4516 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4518 if (CPUArchVer >= 6 && CPUArch != "6M") {
4519 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4520 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4521 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4522 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4525 bool is5EOrAbove = (CPUArchVer >= 6 ||
4527 CPUArch.find('E') != StringRef::npos));
4528 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer));
4529 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM"))
4530 Builder.defineMacro("__ARM_FEATURE_DSP");
4532 void getTargetBuiltins(const Builtin::Info *&Records,
4533 unsigned &NumRecords) const override {
4534 Records = BuiltinInfo;
4535 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4537 bool isCLZForZeroUndef() const override { return false; }
4538 BuiltinVaListKind getBuiltinVaListKind() const override {
4539 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4541 void getGCCRegNames(const char * const *&Names,
4542 unsigned &NumNames) const override;
4543 void getGCCRegAliases(const GCCRegAlias *&Aliases,
4544 unsigned &NumAliases) const override;
4545 bool validateAsmConstraint(const char *&Name,
4546 TargetInfo::ConstraintInfo &Info) const override {
4551 case 'w': // VFP Floating point register single precision
4552 case 'P': // VFP Floating point register double precision
4553 Info.setAllowsRegister();
4562 case 'Q': // A memory address that is a single base register.
4563 Info.setAllowsMemory();
4565 case 'U': // a memory reference...
4567 case 'q': // ...ARMV4 ldrsb
4568 case 'v': // ...VFP load/store (reg+constant offset)
4569 case 'y': // ...iWMMXt load/store
4570 case 't': // address valid for load/store opaque types wider
4572 case 'n': // valid address for Neon doubleword vector load/store
4573 case 'm': // valid address for Neon element and structure load/store
4574 case 's': // valid address for non-offset loads/stores of quad-word
4575 // values in four ARM registers
4576 Info.setAllowsMemory();
4583 std::string convertConstraint(const char *&Constraint) const override {
4585 switch (*Constraint) {
4586 case 'U': // Two-character constraint; add "^" hint for later parsing.
4587 R = std::string("^") + std::string(Constraint, 2);
4590 case 'p': // 'p' should be translated to 'r' by default.
4591 R = std::string("r");
4594 return std::string(1, *Constraint);
4599 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4600 std::string &SuggestedModifier) const override {
4601 bool isOutput = (Constraint[0] == '=');
4602 bool isInOut = (Constraint[0] == '+');
4604 // Strip off constraint modifiers.
4605 while (Constraint[0] == '=' ||
4606 Constraint[0] == '+' ||
4607 Constraint[0] == '&')
4608 Constraint = Constraint.substr(1);
4610 switch (Constraint[0]) {
4615 return (isInOut || isOutput || Size <= 64);
4617 // A register of size 32 cannot fit a vector type.
4625 const char *getClobbers() const override {
4626 // FIXME: Is this really right?
4630 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4631 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4634 int getEHDataRegisterNumber(unsigned RegNo) const override {
4635 if (RegNo == 0) return 0;
4636 if (RegNo == 1) return 1;
4641 bool ARMTargetInfo::setFPMath(StringRef Name) {
4642 if (Name == "neon") {
4645 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4653 const char * const ARMTargetInfo::GCCRegNames[] = {
4654 // Integer registers
4655 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4656 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4659 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4660 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4661 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4662 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4665 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4666 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4667 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4668 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4671 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4672 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4675 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4676 unsigned &NumNames) const {
4677 Names = GCCRegNames;
4678 NumNames = llvm::array_lengthof(GCCRegNames);
4681 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4691 { { "v6", "rfp" }, "r9" },
4692 { { "sl" }, "r10" },
4693 { { "fp" }, "r11" },
4694 { { "ip" }, "r12" },
4695 { { "r13" }, "sp" },
4696 { { "r14" }, "lr" },
4697 { { "r15" }, "pc" },
4698 // The S, D and Q registers overlap, but aren't really aliases; we
4699 // don't want to substitute one of these for a different-sized one.
4702 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4703 unsigned &NumAliases) const {
4704 Aliases = GCCRegAliases;
4705 NumAliases = llvm::array_lengthof(GCCRegAliases);
4708 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4709 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4710 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4712 #include "clang/Basic/BuiltinsNEON.def"
4714 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4715 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4716 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4718 #include "clang/Basic/BuiltinsARM.def"
4721 class ARMleTargetInfo : public ARMTargetInfo {
4723 ARMleTargetInfo(const llvm::Triple &Triple)
4724 : ARMTargetInfo(Triple, false) { }
4725 void getTargetDefines(const LangOptions &Opts,
4726 MacroBuilder &Builder) const override {
4727 Builder.defineMacro("__ARMEL__");
4728 ARMTargetInfo::getTargetDefines(Opts, Builder);
4732 class ARMbeTargetInfo : public ARMTargetInfo {
4734 ARMbeTargetInfo(const llvm::Triple &Triple)
4735 : ARMTargetInfo(Triple, true) { }
4736 void getTargetDefines(const LangOptions &Opts,
4737 MacroBuilder &Builder) const override {
4738 Builder.defineMacro("__ARMEB__");
4739 Builder.defineMacro("__ARM_BIG_ENDIAN");
4740 ARMTargetInfo::getTargetDefines(Opts, Builder);
4744 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4745 const llvm::Triple Triple;
4747 WindowsARMTargetInfo(const llvm::Triple &Triple)
4748 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4749 TLSSupported = false;
4750 WCharType = UnsignedShort;
4751 SizeType = UnsignedInt;
4752 UserLabelPrefix = "";
4754 void getVisualStudioDefines(const LangOptions &Opts,
4755 MacroBuilder &Builder) const {
4756 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4758 // FIXME: this is invalid for WindowsCE
4759 Builder.defineMacro("_M_ARM_NT", "1");
4760 Builder.defineMacro("_M_ARMT", "_M_ARM");
4761 Builder.defineMacro("_M_THUMB", "_M_ARM");
4763 assert((Triple.getArch() == llvm::Triple::arm ||
4764 Triple.getArch() == llvm::Triple::thumb) &&
4765 "invalid architecture for Windows ARM target info");
4766 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4767 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4769 // TODO map the complete set of values
4770 // 31: VFPv3 40: VFPv4
4771 Builder.defineMacro("_M_ARM_FP", "31");
4773 BuiltinVaListKind getBuiltinVaListKind() const override {
4774 return TargetInfo::CharPtrBuiltinVaList;
4778 // Windows ARM + Itanium C++ ABI Target
4779 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4781 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4782 : WindowsARMTargetInfo(Triple) {
4783 TheCXXABI.set(TargetCXXABI::GenericARM);
4786 void getTargetDefines(const LangOptions &Opts,
4787 MacroBuilder &Builder) const override {
4788 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4790 if (Opts.MSVCCompat)
4791 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4795 // Windows ARM, MS (C++) ABI
4796 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4798 MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4799 : WindowsARMTargetInfo(Triple) {
4800 TheCXXABI.set(TargetCXXABI::Microsoft);
4803 void getTargetDefines(const LangOptions &Opts,
4804 MacroBuilder &Builder) const override {
4805 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4806 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4810 class DarwinARMTargetInfo :
4811 public DarwinTargetInfo<ARMleTargetInfo> {
4813 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4814 MacroBuilder &Builder) const override {
4815 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4819 DarwinARMTargetInfo(const llvm::Triple &Triple)
4820 : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4821 HasAlignMac68kSupport = true;
4822 // iOS always has 64-bit atomic instructions.
4823 // FIXME: This should be based off of the target features in
4825 MaxAtomicInlineWidth = 64;
4827 // Darwin on iOS uses a variant of the ARM C++ ABI.
4828 TheCXXABI.set(TargetCXXABI::iOS);
4832 class AArch64TargetInfo : public TargetInfo {
4833 virtual void setDescriptionString() = 0;
4834 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4835 static const char *const GCCRegNames[];
4846 static const Builtin::Info BuiltinInfo[];
4851 AArch64TargetInfo(const llvm::Triple &Triple)
4852 : TargetInfo(Triple), ABI("aapcs") {
4854 if (getTriple().getOS() == llvm::Triple::NetBSD) {
4855 WCharType = SignedInt;
4857 // NetBSD apparently prefers consistency across ARM targets to consistency
4858 // across 64-bit targets.
4859 Int64Type = SignedLongLong;
4860 IntMaxType = SignedLongLong;
4862 WCharType = UnsignedInt;
4863 Int64Type = SignedLong;
4864 IntMaxType = SignedLong;
4867 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4868 MaxVectorAlign = 128;
4870 MaxAtomicInlineWidth = 128;
4871 MaxAtomicPromoteWidth = 128;
4873 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
4874 LongDoubleFormat = &llvm::APFloat::IEEEquad;
4876 // {} in inline assembly are neon specifiers, not assembly variant
4878 NoAsmVariants = true;
4880 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
4881 // contributes to the alignment of the containing aggregate in the same way
4882 // a plain (non bit-field) member of that type would, without exception for
4883 // zero-sized or anonymous bit-fields."
4884 UseBitFieldTypeAlignment = true;
4885 UseZeroLengthBitfieldAlignment = true;
4887 // AArch64 targets default to using the ARM C++ ABI.
4888 TheCXXABI.set(TargetCXXABI::GenericAArch64);
4891 StringRef getABI() const override { return ABI; }
4892 bool setABI(const std::string &Name) override {
4893 if (Name != "aapcs" && Name != "darwinpcs")
4900 bool setCPU(const std::string &Name) override {
4901 bool CPUKnown = llvm::StringSwitch<bool>(Name)
4902 .Case("generic", true)
4903 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true)
4904 .Case("cyclone", true)
4909 void getTargetDefines(const LangOptions &Opts,
4910 MacroBuilder &Builder) const override {
4911 // Target identification.
4912 Builder.defineMacro("__aarch64__");
4914 // Target properties.
4915 Builder.defineMacro("_LP64");
4916 Builder.defineMacro("__LP64__");
4918 // ACLE predefines. Many can only have one possible value on v8 AArch64.
4919 Builder.defineMacro("__ARM_ACLE", "200");
4920 Builder.defineMacro("__ARM_ARCH", "8");
4921 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4923 Builder.defineMacro("__ARM_64BIT_STATE");
4924 Builder.defineMacro("__ARM_PCS_AAPCS64");
4925 Builder.defineMacro("__ARM_ARCH_ISA_A64");
4927 Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4928 Builder.defineMacro("__ARM_FEATURE_CLZ");
4929 Builder.defineMacro("__ARM_FEATURE_FMA");
4930 Builder.defineMacro("__ARM_FEATURE_DIV");
4931 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
4932 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
4933 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4934 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4936 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4938 // 0xe implies support for half, single and double precision operations.
4939 Builder.defineMacro("__ARM_FP", "0xe");
4941 // PCS specifies this for SysV variants, which is all we support. Other ABIs
4942 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4943 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4945 if (Opts.FastMath || Opts.FiniteMathOnly)
4946 Builder.defineMacro("__ARM_FP_FAST");
4948 if (Opts.C99 && !Opts.Freestanding)
4949 Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4951 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4953 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4954 Opts.ShortEnums ? "1" : "4");
4956 if (FPU == NeonMode) {
4957 Builder.defineMacro("__ARM_NEON");
4958 // 64-bit NEON supports half, single and double precision operations.
4959 Builder.defineMacro("__ARM_NEON_FP", "0xe");
4963 Builder.defineMacro("__ARM_FEATURE_CRC32");
4966 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4968 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
4969 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4970 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4971 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4972 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4975 void getTargetBuiltins(const Builtin::Info *&Records,
4976 unsigned &NumRecords) const override {
4977 Records = BuiltinInfo;
4978 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
4981 bool hasFeature(StringRef Feature) const override {
4982 return Feature == "aarch64" ||
4983 Feature == "arm64" ||
4984 (Feature == "neon" && FPU == NeonMode);
4987 bool handleTargetFeatures(std::vector<std::string> &Features,
4988 DiagnosticsEngine &Diags) override {
4992 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
4993 if (Features[i] == "+neon")
4995 if (Features[i] == "+crc")
4997 if (Features[i] == "+crypto")
5001 setDescriptionString();
5006 bool isCLZForZeroUndef() const override { return false; }
5008 BuiltinVaListKind getBuiltinVaListKind() const override {
5009 return TargetInfo::AArch64ABIBuiltinVaList;
5012 void getGCCRegNames(const char *const *&Names,
5013 unsigned &NumNames) const override;
5014 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5015 unsigned &NumAliases) const override;
5017 bool validateAsmConstraint(const char *&Name,
5018 TargetInfo::ConstraintInfo &Info) const override {
5022 case 'w': // Floating point and SIMD registers (V0-V31)
5023 Info.setAllowsRegister();
5025 case 'I': // Constant that can be used with an ADD instruction
5026 case 'J': // Constant that can be used with a SUB instruction
5027 case 'K': // Constant that can be used with a 32-bit logical instruction
5028 case 'L': // Constant that can be used with a 64-bit logical instruction
5029 case 'M': // Constant that can be used as a 32-bit MOV immediate
5030 case 'N': // Constant that can be used as a 64-bit MOV immediate
5031 case 'Y': // Floating point constant zero
5032 case 'Z': // Integer constant zero
5034 case 'Q': // A memory reference with base register and no offset
5035 Info.setAllowsMemory();
5037 case 'S': // A symbolic address
5038 Info.setAllowsRegister();
5041 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
5042 // Utf: A memory address suitable for ldp/stp in TF mode.
5043 // Usa: An absolute symbolic address.
5044 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
5045 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
5046 case 'z': // Zero register, wzr or xzr
5047 Info.setAllowsRegister();
5049 case 'x': // Floating point and SIMD registers (V0-V15)
5050 Info.setAllowsRegister();
5057 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5058 std::string &SuggestedModifier) const override {
5059 // Strip off constraint modifiers.
5060 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
5061 Constraint = Constraint.substr(1);
5063 switch (Constraint[0]) {
5071 // For now assume that the person knows what they're
5072 // doing with the modifier.
5075 // By default an 'r' constraint will be in the 'x'
5080 SuggestedModifier = "w";
5087 const char *getClobbers() const override { return ""; }
5089 int getEHDataRegisterNumber(unsigned RegNo) const override {
5098 const char *const AArch64TargetInfo::GCCRegNames[] = {
5099 // 32-bit Integer registers
5100 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
5101 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
5102 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
5104 // 64-bit Integer registers
5105 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
5106 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
5107 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
5109 // 32-bit floating point regsisters
5110 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
5111 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
5112 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5114 // 64-bit floating point regsisters
5115 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
5116 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
5117 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5120 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
5121 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
5122 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
5125 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
5126 unsigned &NumNames) const {
5127 Names = GCCRegNames;
5128 NumNames = llvm::array_lengthof(GCCRegNames);
5131 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
5132 { { "w31" }, "wsp" },
5133 { { "x29" }, "fp" },
5134 { { "x30" }, "lr" },
5135 { { "x31" }, "sp" },
5136 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
5137 // don't want to substitute one of these for a different-sized one.
5140 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5141 unsigned &NumAliases) const {
5142 Aliases = GCCRegAliases;
5143 NumAliases = llvm::array_lengthof(GCCRegAliases);
5146 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
5147 #define BUILTIN(ID, TYPE, ATTRS) \
5148 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5149 #include "clang/Basic/BuiltinsNEON.def"
5151 #define BUILTIN(ID, TYPE, ATTRS) \
5152 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5153 #include "clang/Basic/BuiltinsAArch64.def"
5156 class AArch64leTargetInfo : public AArch64TargetInfo {
5157 void setDescriptionString() override {
5158 if (getTriple().isOSBinFormatMachO())
5159 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
5161 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
5165 AArch64leTargetInfo(const llvm::Triple &Triple)
5166 : AArch64TargetInfo(Triple) {
5169 void getTargetDefines(const LangOptions &Opts,
5170 MacroBuilder &Builder) const override {
5171 Builder.defineMacro("__AARCH64EL__");
5172 AArch64TargetInfo::getTargetDefines(Opts, Builder);
5176 class AArch64beTargetInfo : public AArch64TargetInfo {
5177 void setDescriptionString() override {
5178 assert(!getTriple().isOSBinFormatMachO());
5179 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
5183 AArch64beTargetInfo(const llvm::Triple &Triple)
5184 : AArch64TargetInfo(Triple) { }
5185 void getTargetDefines(const LangOptions &Opts,
5186 MacroBuilder &Builder) const override {
5187 Builder.defineMacro("__AARCH64EB__");
5188 Builder.defineMacro("__AARCH_BIG_ENDIAN");
5189 Builder.defineMacro("__ARM_BIG_ENDIAN");
5190 AArch64TargetInfo::getTargetDefines(Opts, Builder);
5194 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
5196 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5197 MacroBuilder &Builder) const override {
5198 Builder.defineMacro("__AARCH64_SIMD__");
5199 Builder.defineMacro("__ARM64_ARCH_8__");
5200 Builder.defineMacro("__ARM_NEON__");
5201 Builder.defineMacro("__LITTLE_ENDIAN__");
5202 Builder.defineMacro("__REGISTER_PREFIX__", "");
5203 Builder.defineMacro("__arm64", "1");
5204 Builder.defineMacro("__arm64__", "1");
5206 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5210 DarwinAArch64TargetInfo(const llvm::Triple &Triple)
5211 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
5212 Int64Type = SignedLongLong;
5213 WCharType = SignedInt;
5214 UseSignedCharForObjCBool = false;
5216 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
5217 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5219 TheCXXABI.set(TargetCXXABI::iOS64);
5222 BuiltinVaListKind getBuiltinVaListKind() const override {
5223 return TargetInfo::CharPtrBuiltinVaList;
5227 // Hexagon abstract base class
5228 class HexagonTargetInfo : public TargetInfo {
5229 static const Builtin::Info BuiltinInfo[];
5230 static const char * const GCCRegNames[];
5231 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5234 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5236 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
5238 // {} in inline assembly are packet specifiers, not assembly variant
5240 NoAsmVariants = true;
5243 void getTargetBuiltins(const Builtin::Info *&Records,
5244 unsigned &NumRecords) const override {
5245 Records = BuiltinInfo;
5246 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
5249 bool validateAsmConstraint(const char *&Name,
5250 TargetInfo::ConstraintInfo &Info) const override {
5254 void getTargetDefines(const LangOptions &Opts,
5255 MacroBuilder &Builder) const override;
5257 bool hasFeature(StringRef Feature) const override {
5258 return Feature == "hexagon";
5261 BuiltinVaListKind getBuiltinVaListKind() const override {
5262 return TargetInfo::CharPtrBuiltinVaList;
5264 void getGCCRegNames(const char * const *&Names,
5265 unsigned &NumNames) const override;
5266 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5267 unsigned &NumAliases) const override;
5268 const char *getClobbers() const override {
5272 static const char *getHexagonCPUSuffix(StringRef Name) {
5273 return llvm::StringSwitch<const char*>(Name)
5274 .Case("hexagonv4", "4")
5275 .Case("hexagonv5", "5")
5279 bool setCPU(const std::string &Name) override {
5280 if (!getHexagonCPUSuffix(Name))
5288 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5289 MacroBuilder &Builder) const {
5290 Builder.defineMacro("qdsp6");
5291 Builder.defineMacro("__qdsp6", "1");
5292 Builder.defineMacro("__qdsp6__", "1");
5294 Builder.defineMacro("hexagon");
5295 Builder.defineMacro("__hexagon", "1");
5296 Builder.defineMacro("__hexagon__", "1");
5298 if(CPU == "hexagonv1") {
5299 Builder.defineMacro("__HEXAGON_V1__");
5300 Builder.defineMacro("__HEXAGON_ARCH__", "1");
5301 if(Opts.HexagonQdsp6Compat) {
5302 Builder.defineMacro("__QDSP6_V1__");
5303 Builder.defineMacro("__QDSP6_ARCH__", "1");
5306 else if(CPU == "hexagonv2") {
5307 Builder.defineMacro("__HEXAGON_V2__");
5308 Builder.defineMacro("__HEXAGON_ARCH__", "2");
5309 if(Opts.HexagonQdsp6Compat) {
5310 Builder.defineMacro("__QDSP6_V2__");
5311 Builder.defineMacro("__QDSP6_ARCH__", "2");
5314 else if(CPU == "hexagonv3") {
5315 Builder.defineMacro("__HEXAGON_V3__");
5316 Builder.defineMacro("__HEXAGON_ARCH__", "3");
5317 if(Opts.HexagonQdsp6Compat) {
5318 Builder.defineMacro("__QDSP6_V3__");
5319 Builder.defineMacro("__QDSP6_ARCH__", "3");
5322 else if(CPU == "hexagonv4") {
5323 Builder.defineMacro("__HEXAGON_V4__");
5324 Builder.defineMacro("__HEXAGON_ARCH__", "4");
5325 if(Opts.HexagonQdsp6Compat) {
5326 Builder.defineMacro("__QDSP6_V4__");
5327 Builder.defineMacro("__QDSP6_ARCH__", "4");
5330 else if(CPU == "hexagonv5") {
5331 Builder.defineMacro("__HEXAGON_V5__");
5332 Builder.defineMacro("__HEXAGON_ARCH__", "5");
5333 if(Opts.HexagonQdsp6Compat) {
5334 Builder.defineMacro("__QDSP6_V5__");
5335 Builder.defineMacro("__QDSP6_ARCH__", "5");
5340 const char * const HexagonTargetInfo::GCCRegNames[] = {
5341 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5342 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5343 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5344 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5345 "p0", "p1", "p2", "p3",
5346 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5349 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
5350 unsigned &NumNames) const {
5351 Names = GCCRegNames;
5352 NumNames = llvm::array_lengthof(GCCRegNames);
5356 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5357 { { "sp" }, "r29" },
5358 { { "fp" }, "r30" },
5359 { { "lr" }, "r31" },
5362 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5363 unsigned &NumAliases) const {
5364 Aliases = GCCRegAliases;
5365 NumAliases = llvm::array_lengthof(GCCRegAliases);
5369 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5370 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5371 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5373 #include "clang/Basic/BuiltinsHexagon.def"
5376 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5377 class SparcTargetInfo : public TargetInfo {
5378 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5379 static const char * const GCCRegNames[];
5382 SparcTargetInfo(const llvm::Triple &Triple)
5383 : TargetInfo(Triple), SoftFloat(false) {}
5385 bool handleTargetFeatures(std::vector<std::string> &Features,
5386 DiagnosticsEngine &Diags) override {
5387 // The backend doesn't actually handle soft float yet, but in case someone
5388 // is using the support for the front end continue to support it.
5389 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
5390 if (Feature != Features.end()) {
5392 Features.erase(Feature);
5396 void getTargetDefines(const LangOptions &Opts,
5397 MacroBuilder &Builder) const override {
5398 DefineStd(Builder, "sparc", Opts);
5399 Builder.defineMacro("__REGISTER_PREFIX__", "");
5402 Builder.defineMacro("SOFT_FLOAT", "1");
5405 bool hasFeature(StringRef Feature) const override {
5406 return llvm::StringSwitch<bool>(Feature)
5407 .Case("softfloat", SoftFloat)
5408 .Case("sparc", true)
5412 void getTargetBuiltins(const Builtin::Info *&Records,
5413 unsigned &NumRecords) const override {
5414 // FIXME: Implement!
5416 BuiltinVaListKind getBuiltinVaListKind() const override {
5417 return TargetInfo::VoidPtrBuiltinVaList;
5419 void getGCCRegNames(const char * const *&Names,
5420 unsigned &NumNames) const override;
5421 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5422 unsigned &NumAliases) const override;
5423 bool validateAsmConstraint(const char *&Name,
5424 TargetInfo::ConstraintInfo &info) const override {
5425 // FIXME: Implement!
5427 case 'I': // Signed 13-bit constant
5429 case 'K': // 32-bit constant with the low 12 bits clear
5430 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5431 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5432 case 'N': // Same as 'K' but zext (required for SIMode)
5433 case 'O': // The constant 4096
5438 const char *getClobbers() const override {
5439 // FIXME: Implement!
5444 const char * const SparcTargetInfo::GCCRegNames[] = {
5445 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5446 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5447 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5448 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5451 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5452 unsigned &NumNames) const {
5453 Names = GCCRegNames;
5454 NumNames = llvm::array_lengthof(GCCRegNames);
5457 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5468 { { "o2" }, "r10" },
5469 { { "o3" }, "r11" },
5470 { { "o4" }, "r12" },
5471 { { "o5" }, "r13" },
5472 { { "o6", "sp" }, "r14" },
5473 { { "o7" }, "r15" },
5474 { { "l0" }, "r16" },
5475 { { "l1" }, "r17" },
5476 { { "l2" }, "r18" },
5477 { { "l3" }, "r19" },
5478 { { "l4" }, "r20" },
5479 { { "l5" }, "r21" },
5480 { { "l6" }, "r22" },
5481 { { "l7" }, "r23" },
5482 { { "i0" }, "r24" },
5483 { { "i1" }, "r25" },
5484 { { "i2" }, "r26" },
5485 { { "i3" }, "r27" },
5486 { { "i4" }, "r28" },
5487 { { "i5" }, "r29" },
5488 { { "i6", "fp" }, "r30" },
5489 { { "i7" }, "r31" },
5492 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5493 unsigned &NumAliases) const {
5494 Aliases = GCCRegAliases;
5495 NumAliases = llvm::array_lengthof(GCCRegAliases);
5498 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
5499 class SparcV8TargetInfo : public SparcTargetInfo {
5501 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5502 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5505 void getTargetDefines(const LangOptions &Opts,
5506 MacroBuilder &Builder) const override {
5507 SparcTargetInfo::getTargetDefines(Opts, Builder);
5508 Builder.defineMacro("__sparcv8");
5512 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
5513 class SparcV8elTargetInfo : public SparcV8TargetInfo {
5515 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) {
5516 DescriptionString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64";
5521 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5522 class SparcV9TargetInfo : public SparcTargetInfo {
5524 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5525 // FIXME: Support Sparc quad-precision long double?
5526 DescriptionString = "E-m:e-i64:64-n32:64-S128";
5527 // This is an LP64 platform.
5528 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5530 // OpenBSD uses long long for int64_t and intmax_t.
5531 if (getTriple().getOS() == llvm::Triple::OpenBSD)
5532 IntMaxType = SignedLongLong;
5534 IntMaxType = SignedLong;
5535 Int64Type = IntMaxType;
5537 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5538 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5539 LongDoubleWidth = 128;
5540 LongDoubleAlign = 128;
5541 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5542 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5545 void getTargetDefines(const LangOptions &Opts,
5546 MacroBuilder &Builder) const override {
5547 SparcTargetInfo::getTargetDefines(Opts, Builder);
5548 Builder.defineMacro("__sparcv9");
5549 Builder.defineMacro("__arch64__");
5550 // Solaris doesn't need these variants, but the BSDs do.
5551 if (getTriple().getOS() != llvm::Triple::Solaris) {
5552 Builder.defineMacro("__sparc64__");
5553 Builder.defineMacro("__sparc_v9__");
5554 Builder.defineMacro("__sparcv9__");
5558 bool setCPU(const std::string &Name) override {
5559 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5561 .Case("ultrasparc", true)
5562 .Case("ultrasparc3", true)
5563 .Case("niagara", true)
5564 .Case("niagara2", true)
5565 .Case("niagara3", true)
5566 .Case("niagara4", true)
5569 // No need to store the CPU yet. There aren't any CPU-specific
5570 // macros to define.
5575 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
5577 SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
5578 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
5579 SizeType = UnsignedInt;
5580 PtrDiffType = SignedInt;
5584 class SystemZTargetInfo : public TargetInfo {
5585 static const Builtin::Info BuiltinInfo[];
5586 static const char *const GCCRegNames[];
5588 bool HasTransactionalExecution;
5592 SystemZTargetInfo(const llvm::Triple &Triple)
5593 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) {
5594 IntMaxType = SignedLong;
5595 Int64Type = SignedLong;
5596 TLSSupported = true;
5597 IntWidth = IntAlign = 32;
5598 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5599 PointerWidth = PointerAlign = 64;
5600 LongDoubleWidth = 128;
5601 LongDoubleAlign = 64;
5602 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5603 DefaultAlignForAttributeAligned = 64;
5604 MinGlobalAlign = 16;
5605 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5606 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5608 void getTargetDefines(const LangOptions &Opts,
5609 MacroBuilder &Builder) const override {
5610 Builder.defineMacro("__s390__");
5611 Builder.defineMacro("__s390x__");
5612 Builder.defineMacro("__zarch__");
5613 Builder.defineMacro("__LONG_DOUBLE_128__");
5614 if (HasTransactionalExecution)
5615 Builder.defineMacro("__HTM__");
5617 void getTargetBuiltins(const Builtin::Info *&Records,
5618 unsigned &NumRecords) const override {
5619 Records = BuiltinInfo;
5620 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin;
5623 void getGCCRegNames(const char *const *&Names,
5624 unsigned &NumNames) const override;
5625 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5626 unsigned &NumAliases) const override {
5631 bool validateAsmConstraint(const char *&Name,
5632 TargetInfo::ConstraintInfo &info) const override;
5633 const char *getClobbers() const override {
5634 // FIXME: Is this really right?
5637 BuiltinVaListKind getBuiltinVaListKind() const override {
5638 return TargetInfo::SystemZBuiltinVaList;
5640 bool setCPU(const std::string &Name) override {
5642 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5645 .Case("zEC12", true)
5651 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5653 Features["transactional-execution"] = true;
5655 Features["transactional-execution"] = true;
5656 Features["vector"] = true;
5660 bool handleTargetFeatures(std::vector<std::string> &Features,
5661 DiagnosticsEngine &Diags) override {
5662 HasTransactionalExecution = false;
5663 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
5664 if (Features[i] == "+transactional-execution")
5665 HasTransactionalExecution = true;
5666 if (Features[i] == "+vector")
5669 // If we use the vector ABI, vector types are 64-bit aligned.
5671 MaxVectorAlign = 64;
5672 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
5673 "-v128:64-a:8:16-n32:64";
5678 bool hasFeature(StringRef Feature) const override {
5679 return llvm::StringSwitch<bool>(Feature)
5680 .Case("systemz", true)
5681 .Case("htm", HasTransactionalExecution)
5682 .Case("vx", HasVector)
5686 StringRef getABI() const override {
5693 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
5694 #define BUILTIN(ID, TYPE, ATTRS) \
5695 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5696 #include "clang/Basic/BuiltinsSystemZ.def"
5699 const char *const SystemZTargetInfo::GCCRegNames[] = {
5700 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5701 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5702 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
5703 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
5706 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5707 unsigned &NumNames) const {
5708 Names = GCCRegNames;
5709 NumNames = llvm::array_lengthof(GCCRegNames);
5712 bool SystemZTargetInfo::
5713 validateAsmConstraint(const char *&Name,
5714 TargetInfo::ConstraintInfo &Info) const {
5719 case 'a': // Address register
5720 case 'd': // Data register (equivalent to 'r')
5721 case 'f': // Floating-point register
5722 Info.setAllowsRegister();
5725 case 'I': // Unsigned 8-bit constant
5726 case 'J': // Unsigned 12-bit constant
5727 case 'K': // Signed 16-bit constant
5728 case 'L': // Signed 20-bit displacement (on all targets we support)
5729 case 'M': // 0x7fffffff
5732 case 'Q': // Memory with base and unsigned 12-bit displacement
5733 case 'R': // Likewise, plus an index
5734 case 'S': // Memory with base and signed 20-bit displacement
5735 case 'T': // Likewise, plus an index
5736 Info.setAllowsMemory();
5741 class MSP430TargetInfo : public TargetInfo {
5742 static const char * const GCCRegNames[];
5744 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5746 TLSSupported = false;
5747 IntWidth = 16; IntAlign = 16;
5748 LongWidth = 32; LongLongWidth = 64;
5749 LongAlign = LongLongAlign = 16;
5750 PointerWidth = 16; PointerAlign = 16;
5752 SizeType = UnsignedInt;
5753 IntMaxType = SignedLongLong;
5754 IntPtrType = SignedInt;
5755 PtrDiffType = SignedInt;
5756 SigAtomicType = SignedLong;
5757 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5759 void getTargetDefines(const LangOptions &Opts,
5760 MacroBuilder &Builder) const override {
5761 Builder.defineMacro("MSP430");
5762 Builder.defineMacro("__MSP430__");
5763 // FIXME: defines for different 'flavours' of MCU
5765 void getTargetBuiltins(const Builtin::Info *&Records,
5766 unsigned &NumRecords) const override {
5767 // FIXME: Implement.
5771 bool hasFeature(StringRef Feature) const override {
5772 return Feature == "msp430";
5774 void getGCCRegNames(const char * const *&Names,
5775 unsigned &NumNames) const override;
5776 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5777 unsigned &NumAliases) const override {
5783 validateAsmConstraint(const char *&Name,
5784 TargetInfo::ConstraintInfo &info) const override {
5787 case 'K': // the constant 1
5788 case 'L': // constant -1^20 .. 1^19
5789 case 'M': // constant 1-4:
5792 // No target constraints for now.
5795 const char *getClobbers() const override {
5796 // FIXME: Is this really right?
5799 BuiltinVaListKind getBuiltinVaListKind() const override {
5801 return TargetInfo::CharPtrBuiltinVaList;
5805 const char * const MSP430TargetInfo::GCCRegNames[] = {
5806 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5807 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5810 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5811 unsigned &NumNames) const {
5812 Names = GCCRegNames;
5813 NumNames = llvm::array_lengthof(GCCRegNames);
5816 // LLVM and Clang cannot be used directly to output native binaries for
5817 // target, but is used to compile C code to llvm bitcode with correct
5818 // type and alignment information.
5820 // TCE uses the llvm bitcode as input and uses it for generating customized
5821 // target processor and program binary. TCE co-design environment is
5822 // publicly available in http://tce.cs.tut.fi
5824 static const unsigned TCEOpenCLAddrSpaceMap[] = {
5827 5, // opencl_constant
5828 // FIXME: generic has to be added to the target
5829 0, // opencl_generic
5835 class TCETargetInfo : public TargetInfo{
5837 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5838 TLSSupported = false;
5840 LongWidth = LongLongWidth = 32;
5843 LongAlign = LongLongAlign = 32;
5846 SizeType = UnsignedInt;
5847 IntMaxType = SignedLong;
5848 IntPtrType = SignedInt;
5849 PtrDiffType = SignedInt;
5854 LongDoubleWidth = 32;
5855 LongDoubleAlign = 32;
5856 FloatFormat = &llvm::APFloat::IEEEsingle;
5857 DoubleFormat = &llvm::APFloat::IEEEsingle;
5858 LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5859 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5860 "-f64:32-v64:32-v128:32-a:0:32-n32";
5861 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5862 UseAddrSpaceMapMangling = true;
5865 void getTargetDefines(const LangOptions &Opts,
5866 MacroBuilder &Builder) const override {
5867 DefineStd(Builder, "tce", Opts);
5868 Builder.defineMacro("__TCE__");
5869 Builder.defineMacro("__TCE_V1__");
5871 bool hasFeature(StringRef Feature) const override {
5872 return Feature == "tce";
5875 void getTargetBuiltins(const Builtin::Info *&Records,
5876 unsigned &NumRecords) const override {}
5877 const char *getClobbers() const override {
5880 BuiltinVaListKind getBuiltinVaListKind() const override {
5881 return TargetInfo::VoidPtrBuiltinVaList;
5883 void getGCCRegNames(const char * const *&Names,
5884 unsigned &NumNames) const override {}
5885 bool validateAsmConstraint(const char *&Name,
5886 TargetInfo::ConstraintInfo &info) const override{
5889 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5890 unsigned &NumAliases) const override {}
5893 class MipsTargetInfoBase : public TargetInfo {
5894 virtual void setDescriptionString() = 0;
5896 static const Builtin::Info BuiltinInfo[];
5903 HardFloat, SoftFloat
5915 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5916 const std::string &CPUStr)
5917 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
5918 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
5919 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
5920 TheCXXABI.set(TargetCXXABI::GenericMIPS);
5923 bool isNaN2008Default() const {
5924 return CPU == "mips32r6" || CPU == "mips64r6";
5927 bool isFP64Default() const {
5928 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
5931 bool isNan2008() const override {
5935 StringRef getABI() const override { return ABI; }
5936 bool setCPU(const std::string &Name) override {
5937 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
5938 getTriple().getArch() == llvm::Triple::mipsel;
5940 return llvm::StringSwitch<bool>(Name)
5941 .Case("mips1", IsMips32)
5942 .Case("mips2", IsMips32)
5943 .Case("mips3", true)
5944 .Case("mips4", true)
5945 .Case("mips5", true)
5946 .Case("mips32", IsMips32)
5947 .Case("mips32r2", IsMips32)
5948 .Case("mips32r3", IsMips32)
5949 .Case("mips32r5", IsMips32)
5950 .Case("mips32r6", IsMips32)
5951 .Case("mips64", true)
5952 .Case("mips64r2", true)
5953 .Case("mips64r3", true)
5954 .Case("mips64r5", true)
5955 .Case("mips64r6", true)
5956 .Case("octeon", true)
5959 const std::string& getCPU() const { return CPU; }
5960 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5961 if (CPU == "octeon")
5962 Features["mips64r2"] = Features["cnmips"] = true;
5964 Features[CPU] = true;
5967 void getTargetDefines(const LangOptions &Opts,
5968 MacroBuilder &Builder) const override {
5969 Builder.defineMacro("__mips__");
5970 Builder.defineMacro("_mips");
5972 Builder.defineMacro("mips");
5974 Builder.defineMacro("__REGISTER_PREFIX__", "");
5978 Builder.defineMacro("__mips_hard_float", Twine(1));
5981 Builder.defineMacro("__mips_soft_float", Twine(1));
5986 Builder.defineMacro("__mips_single_float", Twine(1));
5988 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
5989 Builder.defineMacro("_MIPS_FPSET",
5990 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
5993 Builder.defineMacro("__mips16", Twine(1));
5996 Builder.defineMacro("__mips_micromips", Twine(1));
5999 Builder.defineMacro("__mips_nan2008", Twine(1));
6005 Builder.defineMacro("__mips_dsp_rev", Twine(1));
6006 Builder.defineMacro("__mips_dsp", Twine(1));
6009 Builder.defineMacro("__mips_dsp_rev", Twine(2));
6010 Builder.defineMacro("__mips_dspr2", Twine(1));
6011 Builder.defineMacro("__mips_dsp", Twine(1));
6016 Builder.defineMacro("__mips_msa", Twine(1));
6018 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
6019 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
6020 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
6022 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
6023 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
6026 void getTargetBuiltins(const Builtin::Info *&Records,
6027 unsigned &NumRecords) const override {
6028 Records = BuiltinInfo;
6029 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
6031 bool hasFeature(StringRef Feature) const override {
6032 return llvm::StringSwitch<bool>(Feature)
6034 .Case("fp64", HasFP64)
6037 BuiltinVaListKind getBuiltinVaListKind() const override {
6038 return TargetInfo::VoidPtrBuiltinVaList;
6040 void getGCCRegNames(const char * const *&Names,
6041 unsigned &NumNames) const override {
6042 static const char *const GCCRegNames[] = {
6043 // CPU register names
6044 // Must match second column of GCCRegAliases
6045 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
6046 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
6047 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
6048 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
6049 // Floating point register names
6050 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
6051 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
6052 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
6053 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
6054 // Hi/lo and condition register names
6055 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
6056 "$fcc5","$fcc6","$fcc7",
6057 // MSA register names
6058 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
6059 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
6060 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
6061 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
6062 // MSA control register names
6063 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
6064 "$msarequest", "$msamap", "$msaunmap"
6066 Names = GCCRegNames;
6067 NumNames = llvm::array_lengthof(GCCRegNames);
6069 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6070 unsigned &NumAliases) const override = 0;
6071 bool validateAsmConstraint(const char *&Name,
6072 TargetInfo::ConstraintInfo &Info) const override {
6076 case 'r': // CPU registers.
6077 case 'd': // Equivalent to "r" unless generating MIPS16 code.
6078 case 'y': // Equivalent to "r", backward compatibility only.
6079 case 'f': // floating-point registers.
6080 case 'c': // $25 for indirect jumps
6081 case 'l': // lo register
6082 case 'x': // hilo register pair
6083 Info.setAllowsRegister();
6085 case 'I': // Signed 16-bit constant
6086 case 'J': // Integer 0
6087 case 'K': // Unsigned 16-bit constant
6088 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
6089 case 'M': // Constants not loadable via lui, addiu, or ori
6090 case 'N': // Constant -1 to -65535
6091 case 'O': // A signed 15-bit constant
6092 case 'P': // A constant between 1 go 65535
6094 case 'R': // An address that can be used in a non-macro load or store
6095 Info.setAllowsMemory();
6098 if (Name[1] == 'C') { // An address usable by ll, and sc.
6099 Info.setAllowsMemory();
6100 Name++; // Skip over 'Z'.
6107 std::string convertConstraint(const char *&Constraint) const override {
6109 switch (*Constraint) {
6110 case 'Z': // Two-character constraint; add "^" hint for later parsing.
6111 if (Constraint[1] == 'C') {
6112 R = std::string("^") + std::string(Constraint, 2);
6118 return TargetInfo::convertConstraint(Constraint);
6121 const char *getClobbers() const override {
6122 // In GCC, $1 is not widely used in generated code (it's used only in a few
6123 // specific situations), so there is no real need for users to add it to
6124 // the clobbers list if they want to use it in their inline assembly code.
6126 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
6127 // code generation, so using it in inline assembly without adding it to the
6128 // clobbers list can cause conflicts between the inline assembly code and
6129 // the surrounding generated code.
6131 // Another problem is that LLVM is allowed to choose $1 for inline assembly
6132 // operands, which will conflict with the ".set at" assembler option (which
6133 // we use only for inline assembly, in order to maintain compatibility with
6134 // GCC) and will also conflict with the user's usage of $1.
6136 // The easiest way to avoid these conflicts and keep $1 as an allocatable
6137 // register for generated code is to automatically clobber $1 for all inline
6140 // FIXME: We should automatically clobber $1 only for inline assembly code
6141 // which actually uses it. This would allow LLVM to use $1 for inline
6142 // assembly operands if the user's assembly code doesn't use it.
6146 bool handleTargetFeatures(std::vector<std::string> &Features,
6147 DiagnosticsEngine &Diags) override {
6149 IsMicromips = false;
6150 IsNan2008 = isNaN2008Default();
6151 IsSingleFloat = false;
6152 FloatABI = HardFloat;
6154 HasFP64 = isFP64Default();
6156 for (std::vector<std::string>::iterator it = Features.begin(),
6157 ie = Features.end(); it != ie; ++it) {
6158 if (*it == "+single-float")
6159 IsSingleFloat = true;
6160 else if (*it == "+soft-float")
6161 FloatABI = SoftFloat;
6162 else if (*it == "+mips16")
6164 else if (*it == "+micromips")
6166 else if (*it == "+dsp")
6167 DspRev = std::max(DspRev, DSP1);
6168 else if (*it == "+dspr2")
6169 DspRev = std::max(DspRev, DSP2);
6170 else if (*it == "+msa")
6172 else if (*it == "+fp64")
6174 else if (*it == "-fp64")
6176 else if (*it == "+nan2008")
6178 else if (*it == "-nan2008")
6182 setDescriptionString();
6187 int getEHDataRegisterNumber(unsigned RegNo) const override {
6188 if (RegNo == 0) return 4;
6189 if (RegNo == 1) return 5;
6193 bool isCLZForZeroUndef() const override { return false; }
6196 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
6197 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6198 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6200 #include "clang/Basic/BuiltinsMips.def"
6203 class Mips32TargetInfoBase : public MipsTargetInfoBase {
6205 Mips32TargetInfoBase(const llvm::Triple &Triple)
6206 : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
6207 SizeType = UnsignedInt;
6208 PtrDiffType = SignedInt;
6209 Int64Type = SignedLongLong;
6210 IntMaxType = Int64Type;
6211 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
6213 bool setABI(const std::string &Name) override {
6214 if (Name == "o32" || Name == "eabi") {
6220 void getTargetDefines(const LangOptions &Opts,
6221 MacroBuilder &Builder) const override {
6222 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6224 Builder.defineMacro("__mips", "32");
6225 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
6227 const std::string& CPUStr = getCPU();
6228 if (CPUStr == "mips32")
6229 Builder.defineMacro("__mips_isa_rev", "1");
6230 else if (CPUStr == "mips32r2")
6231 Builder.defineMacro("__mips_isa_rev", "2");
6232 else if (CPUStr == "mips32r3")
6233 Builder.defineMacro("__mips_isa_rev", "3");
6234 else if (CPUStr == "mips32r5")
6235 Builder.defineMacro("__mips_isa_rev", "5");
6236 else if (CPUStr == "mips32r6")
6237 Builder.defineMacro("__mips_isa_rev", "6");
6240 Builder.defineMacro("__mips_o32");
6241 Builder.defineMacro("_ABIO32", "1");
6242 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
6244 else if (ABI == "eabi")
6245 Builder.defineMacro("__mips_eabi");
6247 llvm_unreachable("Invalid ABI for Mips32.");
6249 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6250 unsigned &NumAliases) const override {
6251 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6261 { { "t2" }, "$10" },
6262 { { "t3" }, "$11" },
6263 { { "t4" }, "$12" },
6264 { { "t5" }, "$13" },
6265 { { "t6" }, "$14" },
6266 { { "t7" }, "$15" },
6267 { { "s0" }, "$16" },
6268 { { "s1" }, "$17" },
6269 { { "s2" }, "$18" },
6270 { { "s3" }, "$19" },
6271 { { "s4" }, "$20" },
6272 { { "s5" }, "$21" },
6273 { { "s6" }, "$22" },
6274 { { "s7" }, "$23" },
6275 { { "t8" }, "$24" },
6276 { { "t9" }, "$25" },
6277 { { "k0" }, "$26" },
6278 { { "k1" }, "$27" },
6279 { { "gp" }, "$28" },
6280 { { "sp","$sp" }, "$29" },
6281 { { "fp","$fp" }, "$30" },
6284 Aliases = GCCRegAliases;
6285 NumAliases = llvm::array_lengthof(GCCRegAliases);
6289 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
6290 void setDescriptionString() override {
6291 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6295 Mips32EBTargetInfo(const llvm::Triple &Triple)
6296 : Mips32TargetInfoBase(Triple) {
6298 void getTargetDefines(const LangOptions &Opts,
6299 MacroBuilder &Builder) const override {
6300 DefineStd(Builder, "MIPSEB", Opts);
6301 Builder.defineMacro("_MIPSEB");
6302 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6306 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
6307 void setDescriptionString() override {
6308 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6312 Mips32ELTargetInfo(const llvm::Triple &Triple)
6313 : Mips32TargetInfoBase(Triple) {
6316 void getTargetDefines(const LangOptions &Opts,
6317 MacroBuilder &Builder) const override {
6318 DefineStd(Builder, "MIPSEL", Opts);
6319 Builder.defineMacro("_MIPSEL");
6320 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6324 class Mips64TargetInfoBase : public MipsTargetInfoBase {
6326 Mips64TargetInfoBase(const llvm::Triple &Triple)
6327 : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6328 LongDoubleWidth = LongDoubleAlign = 128;
6329 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6330 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6331 LongDoubleWidth = LongDoubleAlign = 64;
6332 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6335 SuitableAlign = 128;
6336 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6339 void setN64ABITypes() {
6340 LongWidth = LongAlign = 64;
6341 PointerWidth = PointerAlign = 64;
6342 SizeType = UnsignedLong;
6343 PtrDiffType = SignedLong;
6344 Int64Type = SignedLong;
6345 IntMaxType = Int64Type;
6348 void setN32ABITypes() {
6349 LongWidth = LongAlign = 32;
6350 PointerWidth = PointerAlign = 32;
6351 SizeType = UnsignedInt;
6352 PtrDiffType = SignedInt;
6353 Int64Type = SignedLongLong;
6354 IntMaxType = Int64Type;
6357 bool setABI(const std::string &Name) override {
6358 if (Name == "n32") {
6363 if (Name == "n64") {
6371 void getTargetDefines(const LangOptions &Opts,
6372 MacroBuilder &Builder) const override {
6373 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6375 Builder.defineMacro("__mips", "64");
6376 Builder.defineMacro("__mips64");
6377 Builder.defineMacro("__mips64__");
6378 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6380 const std::string& CPUStr = getCPU();
6381 if (CPUStr == "mips64")
6382 Builder.defineMacro("__mips_isa_rev", "1");
6383 else if (CPUStr == "mips64r2")
6384 Builder.defineMacro("__mips_isa_rev", "2");
6385 else if (CPUStr == "mips64r3")
6386 Builder.defineMacro("__mips_isa_rev", "3");
6387 else if (CPUStr == "mips64r5")
6388 Builder.defineMacro("__mips_isa_rev", "5");
6389 else if (CPUStr == "mips64r6")
6390 Builder.defineMacro("__mips_isa_rev", "6");
6393 Builder.defineMacro("__mips_n32");
6394 Builder.defineMacro("_ABIN32", "2");
6395 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6397 else if (ABI == "n64") {
6398 Builder.defineMacro("__mips_n64");
6399 Builder.defineMacro("_ABI64", "3");
6400 Builder.defineMacro("_MIPS_SIM", "_ABI64");
6403 llvm_unreachable("Invalid ABI for Mips64.");
6405 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6406 unsigned &NumAliases) const override {
6407 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6417 { { "a6" }, "$10" },
6418 { { "a7" }, "$11" },
6419 { { "t0" }, "$12" },
6420 { { "t1" }, "$13" },
6421 { { "t2" }, "$14" },
6422 { { "t3" }, "$15" },
6423 { { "s0" }, "$16" },
6424 { { "s1" }, "$17" },
6425 { { "s2" }, "$18" },
6426 { { "s3" }, "$19" },
6427 { { "s4" }, "$20" },
6428 { { "s5" }, "$21" },
6429 { { "s6" }, "$22" },
6430 { { "s7" }, "$23" },
6431 { { "t8" }, "$24" },
6432 { { "t9" }, "$25" },
6433 { { "k0" }, "$26" },
6434 { { "k1" }, "$27" },
6435 { { "gp" }, "$28" },
6436 { { "sp","$sp" }, "$29" },
6437 { { "fp","$fp" }, "$30" },
6440 Aliases = GCCRegAliases;
6441 NumAliases = llvm::array_lengthof(GCCRegAliases);
6444 bool hasInt128Type() const override { return true; }
6447 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
6448 void setDescriptionString() override {
6450 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6452 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6457 Mips64EBTargetInfo(const llvm::Triple &Triple)
6458 : Mips64TargetInfoBase(Triple) {}
6459 void getTargetDefines(const LangOptions &Opts,
6460 MacroBuilder &Builder) const override {
6461 DefineStd(Builder, "MIPSEB", Opts);
6462 Builder.defineMacro("_MIPSEB");
6463 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6467 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
6468 void setDescriptionString() override {
6470 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6472 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6475 Mips64ELTargetInfo(const llvm::Triple &Triple)
6476 : Mips64TargetInfoBase(Triple) {
6477 // Default ABI is n64.
6480 void getTargetDefines(const LangOptions &Opts,
6481 MacroBuilder &Builder) const override {
6482 DefineStd(Builder, "MIPSEL", Opts);
6483 Builder.defineMacro("_MIPSEL");
6484 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6488 class PNaClTargetInfo : public TargetInfo {
6490 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6492 this->UserLabelPrefix = "";
6493 this->LongAlign = 32;
6494 this->LongWidth = 32;
6495 this->PointerAlign = 32;
6496 this->PointerWidth = 32;
6497 this->IntMaxType = TargetInfo::SignedLongLong;
6498 this->Int64Type = TargetInfo::SignedLongLong;
6499 this->DoubleAlign = 64;
6500 this->LongDoubleWidth = 64;
6501 this->LongDoubleAlign = 64;
6502 this->SizeType = TargetInfo::UnsignedInt;
6503 this->PtrDiffType = TargetInfo::SignedInt;
6504 this->IntPtrType = TargetInfo::SignedInt;
6505 this->RegParmMax = 0; // Disallow regparm
6508 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6510 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6511 Builder.defineMacro("__le32__");
6512 Builder.defineMacro("__pnacl__");
6514 void getTargetDefines(const LangOptions &Opts,
6515 MacroBuilder &Builder) const override {
6516 getArchDefines(Opts, Builder);
6518 bool hasFeature(StringRef Feature) const override {
6519 return Feature == "pnacl";
6521 void getTargetBuiltins(const Builtin::Info *&Records,
6522 unsigned &NumRecords) const override {
6524 BuiltinVaListKind getBuiltinVaListKind() const override {
6525 return TargetInfo::PNaClABIBuiltinVaList;
6527 void getGCCRegNames(const char * const *&Names,
6528 unsigned &NumNames) const override;
6529 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6530 unsigned &NumAliases) const override;
6531 bool validateAsmConstraint(const char *&Name,
6532 TargetInfo::ConstraintInfo &Info) const override {
6536 const char *getClobbers() const override {
6541 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6542 unsigned &NumNames) const {
6547 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6548 unsigned &NumAliases) const {
6553 class Le64TargetInfo : public TargetInfo {
6554 static const Builtin::Info BuiltinInfo[];
6557 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6559 NoAsmVariants = true;
6560 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6561 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6563 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
6566 void getTargetDefines(const LangOptions &Opts,
6567 MacroBuilder &Builder) const override {
6568 DefineStd(Builder, "unix", Opts);
6569 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6570 Builder.defineMacro("__ELF__");
6572 void getTargetBuiltins(const Builtin::Info *&Records,
6573 unsigned &NumRecords) const override {
6574 Records = BuiltinInfo;
6575 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
6577 BuiltinVaListKind getBuiltinVaListKind() const override {
6578 return TargetInfo::PNaClABIBuiltinVaList;
6580 const char *getClobbers() const override { return ""; }
6581 void getGCCRegNames(const char *const *&Names,
6582 unsigned &NumNames) const override {
6586 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6587 unsigned &NumAliases) const override {
6591 bool validateAsmConstraint(const char *&Name,
6592 TargetInfo::ConstraintInfo &Info) const override {
6596 bool hasProtectedVisibility() const override { return false; }
6598 } // end anonymous namespace.
6600 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
6601 #define BUILTIN(ID, TYPE, ATTRS) \
6602 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6603 #include "clang/Basic/BuiltinsLe64.def"
6607 static const unsigned SPIRAddrSpaceMap[] = {
6610 2, // opencl_constant
6611 4, // opencl_generic
6616 class SPIRTargetInfo : public TargetInfo {
6618 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6619 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6620 "SPIR target must use unknown OS");
6621 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6622 "SPIR target must use unknown environment type");
6624 TLSSupported = false;
6625 LongWidth = LongAlign = 64;
6626 AddrSpaceMap = &SPIRAddrSpaceMap;
6627 UseAddrSpaceMapMangling = true;
6628 // Define available target features
6629 // These must be defined in sorted order!
6630 NoAsmVariants = true;
6632 void getTargetDefines(const LangOptions &Opts,
6633 MacroBuilder &Builder) const override {
6634 DefineStd(Builder, "SPIR", Opts);
6636 bool hasFeature(StringRef Feature) const override {
6637 return Feature == "spir";
6640 void getTargetBuiltins(const Builtin::Info *&Records,
6641 unsigned &NumRecords) const override {}
6642 const char *getClobbers() const override {
6645 void getGCCRegNames(const char * const *&Names,
6646 unsigned &NumNames) const override {}
6648 validateAsmConstraint(const char *&Name,
6649 TargetInfo::ConstraintInfo &info) const override {
6652 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6653 unsigned &NumAliases) const override {}
6654 BuiltinVaListKind getBuiltinVaListKind() const override {
6655 return TargetInfo::VoidPtrBuiltinVaList;
6658 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6659 return (CC == CC_SpirFunction ||
6660 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning;
6663 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
6664 return CC_SpirFunction;
6669 class SPIR32TargetInfo : public SPIRTargetInfo {
6671 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6672 PointerWidth = PointerAlign = 32;
6673 SizeType = TargetInfo::UnsignedInt;
6674 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6676 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6677 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6679 void getTargetDefines(const LangOptions &Opts,
6680 MacroBuilder &Builder) const override {
6681 DefineStd(Builder, "SPIR32", Opts);
6685 class SPIR64TargetInfo : public SPIRTargetInfo {
6687 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6688 PointerWidth = PointerAlign = 64;
6689 SizeType = TargetInfo::UnsignedLong;
6690 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6691 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6692 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6694 void getTargetDefines(const LangOptions &Opts,
6695 MacroBuilder &Builder) const override {
6696 DefineStd(Builder, "SPIR64", Opts);
6700 class XCoreTargetInfo : public TargetInfo {
6701 static const Builtin::Info BuiltinInfo[];
6703 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6705 NoAsmVariants = true;
6708 DoubleAlign = LongDoubleAlign = 32;
6709 SizeType = UnsignedInt;
6710 PtrDiffType = SignedInt;
6711 IntPtrType = SignedInt;
6712 WCharType = UnsignedChar;
6713 WIntType = UnsignedInt;
6714 UseZeroLengthBitfieldAlignment = true;
6715 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6716 "-f64:32-a:0:32-n32";
6718 void getTargetDefines(const LangOptions &Opts,
6719 MacroBuilder &Builder) const override {
6720 Builder.defineMacro("__XS1B__");
6722 void getTargetBuiltins(const Builtin::Info *&Records,
6723 unsigned &NumRecords) const override {
6724 Records = BuiltinInfo;
6725 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
6727 BuiltinVaListKind getBuiltinVaListKind() const override {
6728 return TargetInfo::VoidPtrBuiltinVaList;
6730 const char *getClobbers() const override {
6733 void getGCCRegNames(const char * const *&Names,
6734 unsigned &NumNames) const override {
6735 static const char * const GCCRegNames[] = {
6736 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6737 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
6739 Names = GCCRegNames;
6740 NumNames = llvm::array_lengthof(GCCRegNames);
6742 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6743 unsigned &NumAliases) const override {
6747 bool validateAsmConstraint(const char *&Name,
6748 TargetInfo::ConstraintInfo &Info) const override {
6751 int getEHDataRegisterNumber(unsigned RegNo) const override {
6752 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6753 return (RegNo < 2)? RegNo : -1;
6757 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6758 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6759 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6761 #include "clang/Basic/BuiltinsXCore.def"
6763 } // end anonymous namespace.
6766 // x86_32 Android target
6767 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
6769 AndroidX86_32TargetInfo(const llvm::Triple &Triple)
6770 : LinuxTargetInfo<X86_32TargetInfo>(Triple) {
6772 LongDoubleWidth = 64;
6773 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6776 } // end anonymous namespace
6779 // x86_64 Android target
6780 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
6782 AndroidX86_64TargetInfo(const llvm::Triple &Triple)
6783 : LinuxTargetInfo<X86_64TargetInfo>(Triple) {
6784 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6787 } // end anonymous namespace
6790 //===----------------------------------------------------------------------===//
6792 //===----------------------------------------------------------------------===//
6794 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6795 llvm::Triple::OSType os = Triple.getOS();
6797 switch (Triple.getArch()) {
6801 case llvm::Triple::xcore:
6802 return new XCoreTargetInfo(Triple);
6804 case llvm::Triple::hexagon:
6805 return new HexagonTargetInfo(Triple);
6807 case llvm::Triple::aarch64:
6808 if (Triple.isOSDarwin())
6809 return new DarwinAArch64TargetInfo(Triple);
6812 case llvm::Triple::FreeBSD:
6813 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
6814 case llvm::Triple::Linux:
6815 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6816 case llvm::Triple::NetBSD:
6817 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6819 return new AArch64leTargetInfo(Triple);
6822 case llvm::Triple::aarch64_be:
6824 case llvm::Triple::FreeBSD:
6825 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
6826 case llvm::Triple::Linux:
6827 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6828 case llvm::Triple::NetBSD:
6829 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6831 return new AArch64beTargetInfo(Triple);
6834 case llvm::Triple::arm:
6835 case llvm::Triple::thumb:
6836 if (Triple.isOSBinFormatMachO())
6837 return new DarwinARMTargetInfo(Triple);
6840 case llvm::Triple::Linux:
6841 return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6842 case llvm::Triple::FreeBSD:
6843 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6844 case llvm::Triple::NetBSD:
6845 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6846 case llvm::Triple::OpenBSD:
6847 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6848 case llvm::Triple::Bitrig:
6849 return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6850 case llvm::Triple::RTEMS:
6851 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6852 case llvm::Triple::NaCl:
6853 return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6854 case llvm::Triple::Win32:
6855 switch (Triple.getEnvironment()) {
6857 return new ARMleTargetInfo(Triple);
6858 case llvm::Triple::Itanium:
6859 return new ItaniumWindowsARMleTargetInfo(Triple);
6860 case llvm::Triple::MSVC:
6861 return new MicrosoftARMleTargetInfo(Triple);
6864 return new ARMleTargetInfo(Triple);
6867 case llvm::Triple::armeb:
6868 case llvm::Triple::thumbeb:
6869 if (Triple.isOSDarwin())
6870 return new DarwinARMTargetInfo(Triple);
6873 case llvm::Triple::Linux:
6874 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6875 case llvm::Triple::FreeBSD:
6876 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6877 case llvm::Triple::NetBSD:
6878 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6879 case llvm::Triple::OpenBSD:
6880 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6881 case llvm::Triple::Bitrig:
6882 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6883 case llvm::Triple::RTEMS:
6884 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6885 case llvm::Triple::NaCl:
6886 return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6888 return new ARMbeTargetInfo(Triple);
6891 case llvm::Triple::msp430:
6892 return new MSP430TargetInfo(Triple);
6894 case llvm::Triple::mips:
6896 case llvm::Triple::Linux:
6897 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6898 case llvm::Triple::RTEMS:
6899 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6900 case llvm::Triple::FreeBSD:
6901 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6902 case llvm::Triple::NetBSD:
6903 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6905 return new Mips32EBTargetInfo(Triple);
6908 case llvm::Triple::mipsel:
6910 case llvm::Triple::Linux:
6911 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6912 case llvm::Triple::RTEMS:
6913 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
6914 case llvm::Triple::FreeBSD:
6915 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6916 case llvm::Triple::NetBSD:
6917 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6918 case llvm::Triple::NaCl:
6919 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
6921 return new Mips32ELTargetInfo(Triple);
6924 case llvm::Triple::mips64:
6926 case llvm::Triple::Linux:
6927 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
6928 case llvm::Triple::RTEMS:
6929 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
6930 case llvm::Triple::FreeBSD:
6931 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6932 case llvm::Triple::NetBSD:
6933 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6934 case llvm::Triple::OpenBSD:
6935 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6937 return new Mips64EBTargetInfo(Triple);
6940 case llvm::Triple::mips64el:
6942 case llvm::Triple::Linux:
6943 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
6944 case llvm::Triple::RTEMS:
6945 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
6946 case llvm::Triple::FreeBSD:
6947 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6948 case llvm::Triple::NetBSD:
6949 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6950 case llvm::Triple::OpenBSD:
6951 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6953 return new Mips64ELTargetInfo(Triple);
6956 case llvm::Triple::le32:
6958 case llvm::Triple::NaCl:
6959 return new NaClTargetInfo<PNaClTargetInfo>(Triple);
6964 case llvm::Triple::le64:
6965 return new Le64TargetInfo(Triple);
6967 case llvm::Triple::ppc:
6968 if (Triple.isOSDarwin())
6969 return new DarwinPPC32TargetInfo(Triple);
6971 case llvm::Triple::Linux:
6972 return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
6973 case llvm::Triple::FreeBSD:
6974 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
6975 case llvm::Triple::NetBSD:
6976 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
6977 case llvm::Triple::OpenBSD:
6978 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
6979 case llvm::Triple::RTEMS:
6980 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
6982 return new PPC32TargetInfo(Triple);
6985 case llvm::Triple::ppc64:
6986 if (Triple.isOSDarwin())
6987 return new DarwinPPC64TargetInfo(Triple);
6989 case llvm::Triple::Linux:
6990 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6991 case llvm::Triple::Lv2:
6992 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
6993 case llvm::Triple::FreeBSD:
6994 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
6995 case llvm::Triple::NetBSD:
6996 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6998 return new PPC64TargetInfo(Triple);
7001 case llvm::Triple::ppc64le:
7003 case llvm::Triple::Linux:
7004 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7005 case llvm::Triple::NetBSD:
7006 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7008 return new PPC64TargetInfo(Triple);
7011 case llvm::Triple::nvptx:
7012 return new NVPTX32TargetInfo(Triple);
7013 case llvm::Triple::nvptx64:
7014 return new NVPTX64TargetInfo(Triple);
7016 case llvm::Triple::amdgcn:
7017 case llvm::Triple::r600:
7018 return new R600TargetInfo(Triple);
7020 case llvm::Triple::sparc:
7022 case llvm::Triple::Linux:
7023 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
7024 case llvm::Triple::Solaris:
7025 return new SolarisSparcV8TargetInfo(Triple);
7026 case llvm::Triple::NetBSD:
7027 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
7028 case llvm::Triple::OpenBSD:
7029 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
7030 case llvm::Triple::RTEMS:
7031 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
7033 return new SparcV8TargetInfo(Triple);
7036 // The 'sparcel' architecture copies all the above cases except for Solaris.
7037 case llvm::Triple::sparcel:
7039 case llvm::Triple::Linux:
7040 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple);
7041 case llvm::Triple::NetBSD:
7042 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7043 case llvm::Triple::OpenBSD:
7044 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7045 case llvm::Triple::RTEMS:
7046 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple);
7048 return new SparcV8elTargetInfo(Triple);
7051 case llvm::Triple::sparcv9:
7053 case llvm::Triple::Linux:
7054 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
7055 case llvm::Triple::Solaris:
7056 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
7057 case llvm::Triple::NetBSD:
7058 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
7059 case llvm::Triple::OpenBSD:
7060 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
7061 case llvm::Triple::FreeBSD:
7062 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
7064 return new SparcV9TargetInfo(Triple);
7067 case llvm::Triple::systemz:
7069 case llvm::Triple::Linux:
7070 return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
7072 return new SystemZTargetInfo(Triple);
7075 case llvm::Triple::tce:
7076 return new TCETargetInfo(Triple);
7078 case llvm::Triple::x86:
7079 if (Triple.isOSDarwin())
7080 return new DarwinI386TargetInfo(Triple);
7083 case llvm::Triple::Linux: {
7084 switch (Triple.getEnvironment()) {
7086 return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
7087 case llvm::Triple::Android:
7088 return new AndroidX86_32TargetInfo(Triple);
7091 case llvm::Triple::DragonFly:
7092 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
7093 case llvm::Triple::NetBSD:
7094 return new NetBSDI386TargetInfo(Triple);
7095 case llvm::Triple::OpenBSD:
7096 return new OpenBSDI386TargetInfo(Triple);
7097 case llvm::Triple::Bitrig:
7098 return new BitrigI386TargetInfo(Triple);
7099 case llvm::Triple::FreeBSD:
7100 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7101 case llvm::Triple::KFreeBSD:
7102 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7103 case llvm::Triple::Minix:
7104 return new MinixTargetInfo<X86_32TargetInfo>(Triple);
7105 case llvm::Triple::Solaris:
7106 return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
7107 case llvm::Triple::Win32: {
7108 switch (Triple.getEnvironment()) {
7110 return new X86_32TargetInfo(Triple);
7111 case llvm::Triple::Cygnus:
7112 return new CygwinX86_32TargetInfo(Triple);
7113 case llvm::Triple::GNU:
7114 return new MinGWX86_32TargetInfo(Triple);
7115 case llvm::Triple::Itanium:
7116 case llvm::Triple::MSVC:
7117 return new MicrosoftX86_32TargetInfo(Triple);
7120 case llvm::Triple::Haiku:
7121 return new HaikuX86_32TargetInfo(Triple);
7122 case llvm::Triple::RTEMS:
7123 return new RTEMSX86_32TargetInfo(Triple);
7124 case llvm::Triple::NaCl:
7125 return new NaClTargetInfo<X86_32TargetInfo>(Triple);
7127 return new X86_32TargetInfo(Triple);
7130 case llvm::Triple::x86_64:
7131 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
7132 return new DarwinX86_64TargetInfo(Triple);
7135 case llvm::Triple::CloudABI:
7136 return new CloudABITargetInfo<X86_64TargetInfo>(Triple);
7137 case llvm::Triple::Linux: {
7138 switch (Triple.getEnvironment()) {
7140 return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
7141 case llvm::Triple::Android:
7142 return new AndroidX86_64TargetInfo(Triple);
7145 case llvm::Triple::DragonFly:
7146 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
7147 case llvm::Triple::NetBSD:
7148 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
7149 case llvm::Triple::OpenBSD:
7150 return new OpenBSDX86_64TargetInfo(Triple);
7151 case llvm::Triple::Bitrig:
7152 return new BitrigX86_64TargetInfo(Triple);
7153 case llvm::Triple::FreeBSD:
7154 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7155 case llvm::Triple::KFreeBSD:
7156 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7157 case llvm::Triple::Solaris:
7158 return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
7159 case llvm::Triple::Win32: {
7160 switch (Triple.getEnvironment()) {
7162 return new X86_64TargetInfo(Triple);
7163 case llvm::Triple::GNU:
7164 return new MinGWX86_64TargetInfo(Triple);
7165 case llvm::Triple::MSVC:
7166 return new MicrosoftX86_64TargetInfo(Triple);
7169 case llvm::Triple::NaCl:
7170 return new NaClTargetInfo<X86_64TargetInfo>(Triple);
7171 case llvm::Triple::PS4:
7172 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple);
7174 return new X86_64TargetInfo(Triple);
7177 case llvm::Triple::spir: {
7178 if (Triple.getOS() != llvm::Triple::UnknownOS ||
7179 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7181 return new SPIR32TargetInfo(Triple);
7183 case llvm::Triple::spir64: {
7184 if (Triple.getOS() != llvm::Triple::UnknownOS ||
7185 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7187 return new SPIR64TargetInfo(Triple);
7192 /// CreateTargetInfo - Return the target info object for the specified target
7195 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
7196 const std::shared_ptr<TargetOptions> &Opts) {
7197 llvm::Triple Triple(Opts->Triple);
7199 // Construct the target
7200 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
7202 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
7205 Target->TargetOpts = Opts;
7207 // Set the target CPU if specified.
7208 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
7209 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
7213 // Set the target ABI if specified.
7214 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
7215 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
7219 // Set the fp math unit.
7220 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
7221 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
7225 // Compute the default target features, we need the target to handle this
7226 // because features may have dependencies on one another.
7227 llvm::StringMap<bool> Features;
7228 Target->getDefaultFeatures(Features);
7230 // Apply the user specified deltas.
7231 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
7233 const char *Name = Opts->FeaturesAsWritten[I].c_str();
7234 // Apply the feature via the target.
7235 bool Enabled = Name[0] == '+';
7236 Target->setFeatureEnabled(Features, Name + 1, Enabled);
7239 // Add the features to the compile options.
7241 // FIXME: If we are completely confident that we have the right set, we only
7242 // need to pass the minuses.
7243 Opts->Features.clear();
7244 for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
7245 ie = Features.end(); it != ie; ++it)
7246 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
7247 if (!Target->handleTargetFeatures(Opts->Features, Diags))
7250 return Target.release();