1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/MC/MCSectionMachO.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/TargetParser.h"
33 using namespace clang;
35 //===----------------------------------------------------------------------===//
36 // Common code shared among targets.
37 //===----------------------------------------------------------------------===//
39 /// DefineStd - Define a macro name and standard variants. For example if
40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
43 const LangOptions &Opts) {
44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
47 // in the user's namespace.
49 Builder.defineMacro(MacroName);
52 Builder.defineMacro("__" + MacroName);
55 Builder.defineMacro("__" + MacroName + "__");
58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
60 Builder.defineMacro("__" + CPUName);
61 Builder.defineMacro("__" + CPUName + "__");
63 Builder.defineMacro("__tune_" + CPUName + "__");
66 //===----------------------------------------------------------------------===//
67 // Defines specific to certain operating systems.
68 //===----------------------------------------------------------------------===//
71 template<typename TgtInfo>
72 class OSTargetInfo : public TgtInfo {
74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
75 MacroBuilder &Builder) const=0;
77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
78 void getTargetDefines(const LangOptions &Opts,
79 MacroBuilder &Builder) const override {
80 TgtInfo::getTargetDefines(Opts, Builder);
81 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
85 } // end anonymous namespace
88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
89 const llvm::Triple &Triple,
90 StringRef &PlatformName,
91 VersionTuple &PlatformMinVersion) {
92 Builder.defineMacro("__APPLE_CC__", "6000");
93 Builder.defineMacro("__APPLE__");
94 Builder.defineMacro("OBJC_NEW_PROPERTIES");
95 // AddressSanitizer doesn't play well with source fortification, which is on
96 // by default on Darwin.
97 if (Opts.Sanitize.has(SanitizerKind::Address))
98 Builder.defineMacro("_FORTIFY_SOURCE", "0");
100 if (!Opts.ObjCAutoRefCount) {
101 // __weak is always defined, for use in blocks and with objc pointers.
102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
104 // Darwin defines __strong even in C mode (just to nothing).
105 if (Opts.getGC() != LangOptions::NonGC)
106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
108 Builder.defineMacro("__strong", "");
110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even
111 // allow this in C, since one might have block pointers in structs that
112 // are used in pure C code and in Objective-C ARC.
113 Builder.defineMacro("__unsafe_unretained", "");
117 Builder.defineMacro("__STATIC__");
119 Builder.defineMacro("__DYNAMIC__");
121 if (Opts.POSIXThreads)
122 Builder.defineMacro("_REENTRANT");
124 // Get the platform type and version number from the triple.
125 unsigned Maj, Min, Rev;
126 if (Triple.isMacOSX()) {
127 Triple.getMacOSXVersion(Maj, Min, Rev);
128 PlatformName = "macosx";
130 Triple.getOSVersion(Maj, Min, Rev);
131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
134 // If -target arch-pc-win32-macho option specified, we're
135 // generating code for Win32 ABI. No need to emit
136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
137 if (PlatformName == "win32") {
138 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
142 // Set the appropriate OS version define.
143 if (Triple.isiOS()) {
144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
147 Str[1] = '0' + (Min / 10);
148 Str[2] = '0' + (Min % 10);
149 Str[3] = '0' + (Rev / 10);
150 Str[4] = '0' + (Rev % 10);
152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
154 } else if (Triple.isMacOSX()) {
155 // Note that the Driver allows versions which aren't representable in the
156 // define (because we only get a single digit for the minor and micro
157 // revision numbers). So, we limit them to the maximum representable
159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
161 if (Maj < 10 || (Maj == 10 && Min < 10)) {
162 Str[0] = '0' + (Maj / 10);
163 Str[1] = '0' + (Maj % 10);
164 Str[2] = '0' + std::min(Min, 9U);
165 Str[3] = '0' + std::min(Rev, 9U);
168 // Handle versions > 10.9.
169 Str[0] = '0' + (Maj / 10);
170 Str[1] = '0' + (Maj % 10);
171 Str[2] = '0' + (Min / 10);
172 Str[3] = '0' + (Min % 10);
173 Str[4] = '0' + (Rev / 10);
174 Str[5] = '0' + (Rev % 10);
177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
180 // Tell users about the kernel if there is one.
181 if (Triple.isOSDarwin())
182 Builder.defineMacro("__MACH__");
184 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
189 template <typename Target>
190 class CloudABITargetInfo : public OSTargetInfo<Target> {
192 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
193 MacroBuilder &Builder) const override {
194 Builder.defineMacro("__CloudABI__");
195 Builder.defineMacro("__ELF__");
197 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
198 Builder.defineMacro("__STDC_ISO_10646__", "201206L");
199 Builder.defineMacro("__STDC_UTF_16__");
200 Builder.defineMacro("__STDC_UTF_32__");
204 CloudABITargetInfo(const llvm::Triple &Triple)
205 : OSTargetInfo<Target>(Triple) {
206 this->UserLabelPrefix = "";
210 template<typename Target>
211 class DarwinTargetInfo : public OSTargetInfo<Target> {
213 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
214 MacroBuilder &Builder) const override {
215 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
216 this->PlatformMinVersion);
220 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
221 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
222 this->MCountName = "\01mcount";
225 std::string isValidSectionSpecifier(StringRef SR) const override {
226 // Let MCSectionMachO validate this.
227 StringRef Segment, Section;
228 unsigned TAA, StubSize;
230 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
231 TAA, HasTAA, StubSize);
234 const char *getStaticInitSectionSpecifier() const override {
235 // FIXME: We should return 0 when building kexts.
236 return "__TEXT,__StaticInit,regular,pure_instructions";
239 /// Darwin does not support protected visibility. Darwin's "default"
240 /// is very similar to ELF's "protected"; Darwin requires a "weak"
241 /// attribute on declarations that can be dynamically replaced.
242 bool hasProtectedVisibility() const override {
248 // DragonFlyBSD Target
249 template<typename Target>
250 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
252 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
253 MacroBuilder &Builder) const override {
254 // DragonFly defines; list based off of gcc output
255 Builder.defineMacro("__DragonFly__");
256 Builder.defineMacro("__DragonFly_cc_version", "100001");
257 Builder.defineMacro("__ELF__");
258 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
259 Builder.defineMacro("__tune_i386__");
260 DefineStd(Builder, "unix", Opts);
263 DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
264 : OSTargetInfo<Target>(Triple) {
265 this->UserLabelPrefix = "";
267 switch (Triple.getArch()) {
269 case llvm::Triple::x86:
270 case llvm::Triple::x86_64:
271 this->MCountName = ".mcount";
278 template<typename Target>
279 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
281 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
282 MacroBuilder &Builder) const override {
283 // FreeBSD defines; list based off of gcc output
285 unsigned Release = Triple.getOSMajorVersion();
289 Builder.defineMacro("__FreeBSD__", Twine(Release));
290 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
291 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
292 DefineStd(Builder, "unix", Opts);
293 Builder.defineMacro("__ELF__");
295 // On FreeBSD, wchar_t contains the number of the code point as
296 // used by the character set of the locale. These character sets are
297 // not necessarily a superset of ASCII.
299 // FIXME: This is wrong; the macro refers to the numerical values
300 // of wchar_t *literals*, which are not locale-dependent. However,
301 // FreeBSD systems apparently depend on us getting this wrong, and
302 // setting this to 1 is conforming even if all the basic source
303 // character literals have the same encoding as char and wchar_t.
304 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
307 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
308 this->UserLabelPrefix = "";
310 switch (Triple.getArch()) {
312 case llvm::Triple::x86:
313 case llvm::Triple::x86_64:
314 this->MCountName = ".mcount";
316 case llvm::Triple::mips:
317 case llvm::Triple::mipsel:
318 case llvm::Triple::ppc:
319 case llvm::Triple::ppc64:
320 case llvm::Triple::ppc64le:
321 this->MCountName = "_mcount";
323 case llvm::Triple::arm:
324 this->MCountName = "__mcount";
330 // GNU/kFreeBSD Target
331 template<typename Target>
332 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
334 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
335 MacroBuilder &Builder) const override {
336 // GNU/kFreeBSD defines; list based off of gcc output
338 DefineStd(Builder, "unix", Opts);
339 Builder.defineMacro("__FreeBSD_kernel__");
340 Builder.defineMacro("__GLIBC__");
341 Builder.defineMacro("__ELF__");
342 if (Opts.POSIXThreads)
343 Builder.defineMacro("_REENTRANT");
345 Builder.defineMacro("_GNU_SOURCE");
348 KFreeBSDTargetInfo(const llvm::Triple &Triple)
349 : OSTargetInfo<Target>(Triple) {
350 this->UserLabelPrefix = "";
355 template<typename Target>
356 class MinixTargetInfo : public OSTargetInfo<Target> {
358 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
359 MacroBuilder &Builder) const override {
362 Builder.defineMacro("__minix", "3");
363 Builder.defineMacro("_EM_WSIZE", "4");
364 Builder.defineMacro("_EM_PSIZE", "4");
365 Builder.defineMacro("_EM_SSIZE", "2");
366 Builder.defineMacro("_EM_LSIZE", "4");
367 Builder.defineMacro("_EM_FSIZE", "4");
368 Builder.defineMacro("_EM_DSIZE", "8");
369 Builder.defineMacro("__ELF__");
370 DefineStd(Builder, "unix", Opts);
373 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
374 this->UserLabelPrefix = "";
379 template<typename Target>
380 class LinuxTargetInfo : public OSTargetInfo<Target> {
382 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
383 MacroBuilder &Builder) const override {
384 // Linux defines; list based off of gcc output
385 DefineStd(Builder, "unix", Opts);
386 DefineStd(Builder, "linux", Opts);
387 Builder.defineMacro("__gnu_linux__");
388 Builder.defineMacro("__ELF__");
389 if (Triple.getEnvironment() == llvm::Triple::Android) {
390 Builder.defineMacro("__ANDROID__", "1");
391 unsigned Maj, Min, Rev;
392 Triple.getEnvironmentVersion(Maj, Min, Rev);
393 this->PlatformName = "android";
394 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
396 if (Opts.POSIXThreads)
397 Builder.defineMacro("_REENTRANT");
399 Builder.defineMacro("_GNU_SOURCE");
402 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
403 this->UserLabelPrefix = "";
404 this->WIntType = TargetInfo::UnsignedInt;
406 switch (Triple.getArch()) {
409 case llvm::Triple::ppc:
410 case llvm::Triple::ppc64:
411 case llvm::Triple::ppc64le:
412 this->MCountName = "_mcount";
417 const char *getStaticInitSectionSpecifier() const override {
418 return ".text.startup";
423 template<typename Target>
424 class NetBSDTargetInfo : public OSTargetInfo<Target> {
426 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
427 MacroBuilder &Builder) const override {
428 // NetBSD defines; list based off of gcc output
429 Builder.defineMacro("__NetBSD__");
430 Builder.defineMacro("__unix__");
431 Builder.defineMacro("__ELF__");
432 if (Opts.POSIXThreads)
433 Builder.defineMacro("_POSIX_THREADS");
435 switch (Triple.getArch()) {
438 case llvm::Triple::arm:
439 case llvm::Triple::armeb:
440 case llvm::Triple::thumb:
441 case llvm::Triple::thumbeb:
442 Builder.defineMacro("__ARM_DWARF_EH__");
447 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
448 this->UserLabelPrefix = "";
449 this->MCountName = "_mcount";
454 template<typename Target>
455 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
457 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
458 MacroBuilder &Builder) const override {
459 // OpenBSD defines; list based off of gcc output
461 Builder.defineMacro("__OpenBSD__");
462 DefineStd(Builder, "unix", Opts);
463 Builder.defineMacro("__ELF__");
464 if (Opts.POSIXThreads)
465 Builder.defineMacro("_REENTRANT");
468 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
469 this->UserLabelPrefix = "";
470 this->TLSSupported = false;
472 switch (Triple.getArch()) {
474 case llvm::Triple::x86:
475 case llvm::Triple::x86_64:
476 case llvm::Triple::arm:
477 case llvm::Triple::sparc:
478 this->MCountName = "__mcount";
480 case llvm::Triple::mips64:
481 case llvm::Triple::mips64el:
482 case llvm::Triple::ppc:
483 case llvm::Triple::sparcv9:
484 this->MCountName = "_mcount";
491 template<typename Target>
492 class BitrigTargetInfo : public OSTargetInfo<Target> {
494 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495 MacroBuilder &Builder) const override {
496 // Bitrig defines; list based off of gcc output
498 Builder.defineMacro("__Bitrig__");
499 DefineStd(Builder, "unix", Opts);
500 Builder.defineMacro("__ELF__");
501 if (Opts.POSIXThreads)
502 Builder.defineMacro("_REENTRANT");
504 switch (Triple.getArch()) {
507 case llvm::Triple::arm:
508 case llvm::Triple::armeb:
509 case llvm::Triple::thumb:
510 case llvm::Triple::thumbeb:
511 Builder.defineMacro("__ARM_DWARF_EH__");
516 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
517 this->UserLabelPrefix = "";
518 this->MCountName = "__mcount";
523 template<typename Target>
524 class PSPTargetInfo : public OSTargetInfo<Target> {
526 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
527 MacroBuilder &Builder) const override {
528 // PSP defines; list based on the output of the pspdev gcc toolchain.
529 Builder.defineMacro("PSP");
530 Builder.defineMacro("_PSP");
531 Builder.defineMacro("__psp__");
532 Builder.defineMacro("__ELF__");
535 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
536 this->UserLabelPrefix = "";
541 template<typename Target>
542 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
544 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
545 MacroBuilder &Builder) const override {
547 Builder.defineMacro("__PPC__");
548 Builder.defineMacro("__PPU__");
549 Builder.defineMacro("__CELLOS_LV2__");
550 Builder.defineMacro("__ELF__");
551 Builder.defineMacro("__LP32__");
552 Builder.defineMacro("_ARCH_PPC64");
553 Builder.defineMacro("__powerpc64__");
556 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
557 this->UserLabelPrefix = "";
558 this->LongWidth = this->LongAlign = 32;
559 this->PointerWidth = this->PointerAlign = 32;
560 this->IntMaxType = TargetInfo::SignedLongLong;
561 this->Int64Type = TargetInfo::SignedLongLong;
562 this->SizeType = TargetInfo::UnsignedInt;
563 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
567 template <typename Target>
568 class PS4OSTargetInfo : public OSTargetInfo<Target> {
570 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
571 MacroBuilder &Builder) const override {
572 Builder.defineMacro("__FreeBSD__", "9");
573 Builder.defineMacro("__FreeBSD_cc_version", "900001");
574 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
575 DefineStd(Builder, "unix", Opts);
576 Builder.defineMacro("__ELF__");
577 Builder.defineMacro("__PS4__");
580 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
581 this->WCharType = this->UnsignedShort;
583 this->UserLabelPrefix = "";
585 switch (Triple.getArch()) {
587 case llvm::Triple::x86_64:
588 this->MCountName = ".mcount";
595 template<typename Target>
596 class SolarisTargetInfo : public OSTargetInfo<Target> {
598 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
599 MacroBuilder &Builder) const override {
600 DefineStd(Builder, "sun", Opts);
601 DefineStd(Builder, "unix", Opts);
602 Builder.defineMacro("__ELF__");
603 Builder.defineMacro("__svr4__");
604 Builder.defineMacro("__SVR4");
605 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
606 // newer, but to 500 for everything else. feature_test.h has a check to
607 // ensure that you are not using C99 with an old version of X/Open or C89
608 // with a new version.
610 Builder.defineMacro("_XOPEN_SOURCE", "600");
612 Builder.defineMacro("_XOPEN_SOURCE", "500");
614 Builder.defineMacro("__C99FEATURES__");
615 Builder.defineMacro("_LARGEFILE_SOURCE");
616 Builder.defineMacro("_LARGEFILE64_SOURCE");
617 Builder.defineMacro("__EXTENSIONS__");
618 Builder.defineMacro("_REENTRANT");
621 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
622 this->UserLabelPrefix = "";
623 this->WCharType = this->SignedInt;
624 // FIXME: WIntType should be SignedLong
629 template<typename Target>
630 class WindowsTargetInfo : public OSTargetInfo<Target> {
632 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
633 MacroBuilder &Builder) const override {
634 Builder.defineMacro("_WIN32");
636 void getVisualStudioDefines(const LangOptions &Opts,
637 MacroBuilder &Builder) const {
638 if (Opts.CPlusPlus) {
640 Builder.defineMacro("_CPPRTTI");
642 if (Opts.CXXExceptions)
643 Builder.defineMacro("_CPPUNWIND");
646 if (!Opts.CharIsSigned)
647 Builder.defineMacro("_CHAR_UNSIGNED");
649 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
650 // but it works for now.
651 if (Opts.POSIXThreads)
652 Builder.defineMacro("_MT");
654 if (Opts.MSCompatibilityVersion) {
655 Builder.defineMacro("_MSC_VER",
656 Twine(Opts.MSCompatibilityVersion / 100000));
657 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
658 // FIXME We cannot encode the revision information into 32-bits
659 Builder.defineMacro("_MSC_BUILD", Twine(1));
661 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
662 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
665 if (Opts.MicrosoftExt) {
666 Builder.defineMacro("_MSC_EXTENSIONS");
668 if (Opts.CPlusPlus11) {
669 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
670 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
671 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
675 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
679 WindowsTargetInfo(const llvm::Triple &Triple)
680 : OSTargetInfo<Target>(Triple) {}
683 template <typename Target>
684 class NaClTargetInfo : public OSTargetInfo<Target> {
686 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
687 MacroBuilder &Builder) const override {
688 if (Opts.POSIXThreads)
689 Builder.defineMacro("_REENTRANT");
691 Builder.defineMacro("_GNU_SOURCE");
693 DefineStd(Builder, "unix", Opts);
694 Builder.defineMacro("__ELF__");
695 Builder.defineMacro("__native_client__");
699 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
700 this->UserLabelPrefix = "";
701 this->LongAlign = 32;
702 this->LongWidth = 32;
703 this->PointerAlign = 32;
704 this->PointerWidth = 32;
705 this->IntMaxType = TargetInfo::SignedLongLong;
706 this->Int64Type = TargetInfo::SignedLongLong;
707 this->DoubleAlign = 64;
708 this->LongDoubleWidth = 64;
709 this->LongDoubleAlign = 64;
710 this->LongLongWidth = 64;
711 this->LongLongAlign = 64;
712 this->SizeType = TargetInfo::UnsignedInt;
713 this->PtrDiffType = TargetInfo::SignedInt;
714 this->IntPtrType = TargetInfo::SignedInt;
715 // RegParmMax is inherited from the underlying architecture
716 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
717 if (Triple.getArch() == llvm::Triple::arm) {
718 // Handled in ARM's setABI().
719 } else if (Triple.getArch() == llvm::Triple::x86) {
720 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
721 } else if (Triple.getArch() == llvm::Triple::x86_64) {
722 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
723 } else if (Triple.getArch() == llvm::Triple::mipsel) {
724 // Handled on mips' setDescriptionString.
726 assert(Triple.getArch() == llvm::Triple::le32);
727 this->DescriptionString = "e-p:32:32-i64:64";
732 //===----------------------------------------------------------------------===//
733 // Specific target implementations.
734 //===----------------------------------------------------------------------===//
736 // PPC abstract base class
737 class PPCTargetInfo : public TargetInfo {
738 static const Builtin::Info BuiltinInfo[];
739 static const char * const GCCRegNames[];
740 static const TargetInfo::GCCRegAlias GCCRegAliases[];
743 // Target cpu features.
757 PPCTargetInfo(const llvm::Triple &Triple)
758 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
759 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
760 HasBPERMD(false), HasExtDiv(false) {
761 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
762 LongDoubleWidth = LongDoubleAlign = 128;
763 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
766 /// \brief Flags for architecture specific defines.
769 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
770 ArchDefinePpcgr = 1 << 1,
771 ArchDefinePpcsq = 1 << 2,
772 ArchDefine440 = 1 << 3,
773 ArchDefine603 = 1 << 4,
774 ArchDefine604 = 1 << 5,
775 ArchDefinePwr4 = 1 << 6,
776 ArchDefinePwr5 = 1 << 7,
777 ArchDefinePwr5x = 1 << 8,
778 ArchDefinePwr6 = 1 << 9,
779 ArchDefinePwr6x = 1 << 10,
780 ArchDefinePwr7 = 1 << 11,
781 ArchDefinePwr8 = 1 << 12,
782 ArchDefineA2 = 1 << 13,
783 ArchDefineA2q = 1 << 14
786 // Note: GCC recognizes the following additional cpus:
787 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
788 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
790 bool setCPU(const std::string &Name) override {
791 bool CPUKnown = llvm::StringSwitch<bool>(Name)
792 .Case("generic", true)
814 .Case("e500mc", true)
816 .Case("power3", true)
818 .Case("power4", true)
820 .Case("power5", true)
822 .Case("power5x", true)
824 .Case("power6", true)
826 .Case("power6x", true)
828 .Case("power7", true)
830 .Case("power8", true)
832 .Case("powerpc", true)
834 .Case("powerpc64", true)
836 .Case("powerpc64le", true)
837 .Case("ppc64le", true)
847 StringRef getABI() const override { return ABI; }
849 void getTargetBuiltins(const Builtin::Info *&Records,
850 unsigned &NumRecords) const override {
851 Records = BuiltinInfo;
852 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
855 bool isCLZForZeroUndef() const override { return false; }
857 void getTargetDefines(const LangOptions &Opts,
858 MacroBuilder &Builder) const override;
860 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
862 bool handleTargetFeatures(std::vector<std::string> &Features,
863 DiagnosticsEngine &Diags) override;
864 bool hasFeature(StringRef Feature) const override;
866 void getGCCRegNames(const char * const *&Names,
867 unsigned &NumNames) const override;
868 void getGCCRegAliases(const GCCRegAlias *&Aliases,
869 unsigned &NumAliases) const override;
870 bool validateAsmConstraint(const char *&Name,
871 TargetInfo::ConstraintInfo &Info) const override {
873 default: return false;
876 case 'b': // Base register
877 case 'f': // Floating point register
878 Info.setAllowsRegister();
880 // FIXME: The following are added to allow parsing.
881 // I just took a guess at what the actions should be.
882 // Also, is more specific checking needed? I.e. specific registers?
883 case 'd': // Floating point register (containing 64-bit value)
884 case 'v': // Altivec vector register
885 Info.setAllowsRegister();
889 case 'd':// VSX vector register to hold vector double data
890 case 'f':// VSX vector register to hold vector float data
891 case 's':// VSX vector register to hold scalar float data
892 case 'a':// Any VSX register
893 case 'c':// An individual CR bit
898 Info.setAllowsRegister();
899 Name++; // Skip over 'w'.
901 case 'h': // `MQ', `CTR', or `LINK' register
902 case 'q': // `MQ' register
903 case 'c': // `CTR' register
904 case 'l': // `LINK' register
905 case 'x': // `CR' register (condition register) number 0
906 case 'y': // `CR' register (condition register)
907 case 'z': // `XER[CA]' carry bit (part of the XER register)
908 Info.setAllowsRegister();
910 case 'I': // Signed 16-bit constant
911 case 'J': // Unsigned 16-bit constant shifted left 16 bits
912 // (use `L' instead for SImode constants)
913 case 'K': // Unsigned 16-bit constant
914 case 'L': // Signed 16-bit constant shifted left 16 bits
915 case 'M': // Constant larger than 31
916 case 'N': // Exact power of 2
917 case 'P': // Constant whose negation is a signed 16-bit constant
918 case 'G': // Floating point constant that can be loaded into a
919 // register with one instruction per word
920 case 'H': // Integer/Floating point constant that can be loaded
921 // into a register using three instructions
923 case 'm': // Memory operand. Note that on PowerPC targets, m can
924 // include addresses that update the base register. It
925 // is therefore only safe to use `m' in an asm statement
926 // if that asm statement accesses the operand exactly once.
927 // The asm statement must also use `%U<opno>' as a
928 // placeholder for the "update" flag in the corresponding
929 // load or store instruction. For example:
930 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
932 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
933 // is not. Use es rather than m if you don't want the base
934 // register to be updated.
938 // es: A "stable" memory operand; that is, one which does not
939 // include any automodification of the base register. Unlike
940 // `m', this constraint can be used in asm statements that
941 // might access the operand several times, or that might not
943 Info.setAllowsMemory();
944 Name++; // Skip over 'e'.
946 case 'Q': // Memory operand that is an offset from a register (it is
947 // usually better to use `m' or `es' in asm statements)
948 case 'Z': // Memory operand that is an indexed or indirect from a
949 // register (it is usually better to use `m' or `es' in
951 Info.setAllowsMemory();
952 Info.setAllowsRegister();
954 case 'R': // AIX TOC entry
955 case 'a': // Address operand that is an indexed or indirect from a
956 // register (`p' is preferable for asm statements)
957 case 'S': // Constant suitable as a 64-bit mask operand
958 case 'T': // Constant suitable as a 32-bit mask operand
959 case 'U': // System V Release 4 small data area reference
960 case 't': // AND masks that can be performed by two rldic{l, r}
962 case 'W': // Vector constant that does not require memory
963 case 'j': // Vector constant that is all zeros.
969 std::string convertConstraint(const char *&Constraint) const override {
971 switch (*Constraint) {
974 // Two-character constraint; add "^" hint for later parsing.
975 R = std::string("^") + std::string(Constraint, 2);
979 return TargetInfo::convertConstraint(Constraint);
983 const char *getClobbers() const override {
986 int getEHDataRegisterNumber(unsigned RegNo) const override {
987 if (RegNo == 0) return 3;
988 if (RegNo == 1) return 4;
992 bool hasSjLjLowering() const override {
996 bool useFloat128ManglingForLongDouble() const override {
997 return LongDoubleWidth == 128 &&
998 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble &&
999 getTriple().isOSBinFormatELF();
1003 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
1004 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1005 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1007 #include "clang/Basic/BuiltinsPPC.def"
1010 /// handleTargetFeatures - Perform initialization based on the user
1011 /// configured set of features.
1012 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1013 DiagnosticsEngine &Diags) {
1014 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
1015 // Ignore disabled features.
1016 if (Features[i][0] == '-')
1019 StringRef Feature = StringRef(Features[i]).substr(1);
1021 if (Feature == "vsx") {
1026 if (Feature == "bpermd") {
1031 if (Feature == "extdiv") {
1036 if (Feature == "power8-vector") {
1042 if (Feature == "crypto") {
1047 if (Feature == "direct-move") {
1048 HasDirectMove = true;
1053 if (Feature == "qpx") {
1058 if (Feature == "htm") {
1063 // TODO: Finish this list and add an assert that we've handled them
1070 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1071 /// #defines that are not tied to a specific subtarget.
1072 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1073 MacroBuilder &Builder) const {
1074 // Target identification.
1075 Builder.defineMacro("__ppc__");
1076 Builder.defineMacro("__PPC__");
1077 Builder.defineMacro("_ARCH_PPC");
1078 Builder.defineMacro("__powerpc__");
1079 Builder.defineMacro("__POWERPC__");
1080 if (PointerWidth == 64) {
1081 Builder.defineMacro("_ARCH_PPC64");
1082 Builder.defineMacro("__powerpc64__");
1083 Builder.defineMacro("__ppc64__");
1084 Builder.defineMacro("__PPC64__");
1087 // Target properties.
1088 if (getTriple().getArch() == llvm::Triple::ppc64le) {
1089 Builder.defineMacro("_LITTLE_ENDIAN");
1091 if (getTriple().getOS() != llvm::Triple::NetBSD &&
1092 getTriple().getOS() != llvm::Triple::OpenBSD)
1093 Builder.defineMacro("_BIG_ENDIAN");
1097 if (ABI == "elfv1" || ABI == "elfv1-qpx")
1098 Builder.defineMacro("_CALL_ELF", "1");
1100 Builder.defineMacro("_CALL_ELF", "2");
1102 // Subtarget options.
1103 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1104 Builder.defineMacro("__REGISTER_PREFIX__", "");
1106 // FIXME: Should be controlled by command line option.
1107 if (LongDoubleWidth == 128)
1108 Builder.defineMacro("__LONG_DOUBLE_128__");
1111 Builder.defineMacro("__VEC__", "10206");
1112 Builder.defineMacro("__ALTIVEC__");
1115 // CPU identification.
1116 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1117 .Case("440", ArchDefineName)
1118 .Case("450", ArchDefineName | ArchDefine440)
1119 .Case("601", ArchDefineName)
1120 .Case("602", ArchDefineName | ArchDefinePpcgr)
1121 .Case("603", ArchDefineName | ArchDefinePpcgr)
1122 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1123 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1124 .Case("604", ArchDefineName | ArchDefinePpcgr)
1125 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1126 .Case("620", ArchDefineName | ArchDefinePpcgr)
1127 .Case("630", ArchDefineName | ArchDefinePpcgr)
1128 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1129 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1130 .Case("750", ArchDefineName | ArchDefinePpcgr)
1131 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1133 .Case("a2", ArchDefineA2)
1134 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1135 .Case("pwr3", ArchDefinePpcgr)
1136 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1137 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1139 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1140 | ArchDefinePpcgr | ArchDefinePpcsq)
1141 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1142 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1143 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1144 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1146 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1147 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1148 | ArchDefinePpcgr | ArchDefinePpcsq)
1149 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1150 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1151 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1152 .Case("power3", ArchDefinePpcgr)
1153 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1154 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1156 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1157 | ArchDefinePpcgr | ArchDefinePpcsq)
1158 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1159 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1160 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1161 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1163 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1164 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1165 | ArchDefinePpcgr | ArchDefinePpcsq)
1166 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1167 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1168 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1169 .Default(ArchDefineNone);
1171 if (defs & ArchDefineName)
1172 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1173 if (defs & ArchDefinePpcgr)
1174 Builder.defineMacro("_ARCH_PPCGR");
1175 if (defs & ArchDefinePpcsq)
1176 Builder.defineMacro("_ARCH_PPCSQ");
1177 if (defs & ArchDefine440)
1178 Builder.defineMacro("_ARCH_440");
1179 if (defs & ArchDefine603)
1180 Builder.defineMacro("_ARCH_603");
1181 if (defs & ArchDefine604)
1182 Builder.defineMacro("_ARCH_604");
1183 if (defs & ArchDefinePwr4)
1184 Builder.defineMacro("_ARCH_PWR4");
1185 if (defs & ArchDefinePwr5)
1186 Builder.defineMacro("_ARCH_PWR5");
1187 if (defs & ArchDefinePwr5x)
1188 Builder.defineMacro("_ARCH_PWR5X");
1189 if (defs & ArchDefinePwr6)
1190 Builder.defineMacro("_ARCH_PWR6");
1191 if (defs & ArchDefinePwr6x)
1192 Builder.defineMacro("_ARCH_PWR6X");
1193 if (defs & ArchDefinePwr7)
1194 Builder.defineMacro("_ARCH_PWR7");
1195 if (defs & ArchDefinePwr8)
1196 Builder.defineMacro("_ARCH_PWR8");
1197 if (defs & ArchDefineA2)
1198 Builder.defineMacro("_ARCH_A2");
1199 if (defs & ArchDefineA2q) {
1200 Builder.defineMacro("_ARCH_A2Q");
1201 Builder.defineMacro("_ARCH_QP");
1204 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1205 Builder.defineMacro("__bg__");
1206 Builder.defineMacro("__THW_BLUEGENE__");
1207 Builder.defineMacro("__bgq__");
1208 Builder.defineMacro("__TOS_BGQ__");
1212 Builder.defineMacro("__VSX__");
1214 Builder.defineMacro("__POWER8_VECTOR__");
1216 Builder.defineMacro("__CRYPTO__");
1218 Builder.defineMacro("__HTM__");
1219 if (getTriple().getArch() == llvm::Triple::ppc64le ||
1220 (defs & ArchDefinePwr8) || (CPU == "pwr8")) {
1221 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1222 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1223 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1224 if (PointerWidth == 64)
1225 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1228 // FIXME: The following are not yet generated here by Clang, but are
1229 // generated by GCC:
1232 // __RECIP_PRECISION__
1233 // __APPLE_ALTIVEC__
1242 // __CMODEL_MEDIUM__
1249 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1250 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1260 .Case("ppc64", true)
1261 .Case("ppc64le", true)
1264 Features["qpx"] = (CPU == "a2q");
1265 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1266 .Case("ppc64le", true)
1269 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1270 .Case("ppc64le", true)
1273 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1274 .Case("ppc64le", true)
1278 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1279 .Case("ppc64le", true)
1283 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1284 .Case("ppc64le", true)
1289 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1290 return llvm::StringSwitch<bool>(Feature)
1291 .Case("powerpc", true)
1292 .Case("vsx", HasVSX)
1293 .Case("power8-vector", HasP8Vector)
1294 .Case("crypto", HasP8Crypto)
1295 .Case("direct-move", HasDirectMove)
1296 .Case("qpx", HasQPX)
1297 .Case("htm", HasHTM)
1298 .Case("bpermd", HasBPERMD)
1299 .Case("extdiv", HasExtDiv)
1303 const char * const PPCTargetInfo::GCCRegNames[] = {
1304 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1305 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1306 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1307 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1308 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1309 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1310 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1311 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1312 "mq", "lr", "ctr", "ap",
1313 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1315 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1316 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1317 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1318 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1320 "spe_acc", "spefscr",
1324 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1325 unsigned &NumNames) const {
1326 Names = GCCRegNames;
1327 NumNames = llvm::array_lengthof(GCCRegNames);
1330 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1331 // While some of these aliases do map to different registers
1332 // they still share the same register name.
1343 { { "10" }, "r10" },
1344 { { "11" }, "r11" },
1345 { { "12" }, "r12" },
1346 { { "13" }, "r13" },
1347 { { "14" }, "r14" },
1348 { { "15" }, "r15" },
1349 { { "16" }, "r16" },
1350 { { "17" }, "r17" },
1351 { { "18" }, "r18" },
1352 { { "19" }, "r19" },
1353 { { "20" }, "r20" },
1354 { { "21" }, "r21" },
1355 { { "22" }, "r22" },
1356 { { "23" }, "r23" },
1357 { { "24" }, "r24" },
1358 { { "25" }, "r25" },
1359 { { "26" }, "r26" },
1360 { { "27" }, "r27" },
1361 { { "28" }, "r28" },
1362 { { "29" }, "r29" },
1363 { { "30" }, "r30" },
1364 { { "31" }, "r31" },
1365 { { "fr0" }, "f0" },
1366 { { "fr1" }, "f1" },
1367 { { "fr2" }, "f2" },
1368 { { "fr3" }, "f3" },
1369 { { "fr4" }, "f4" },
1370 { { "fr5" }, "f5" },
1371 { { "fr6" }, "f6" },
1372 { { "fr7" }, "f7" },
1373 { { "fr8" }, "f8" },
1374 { { "fr9" }, "f9" },
1375 { { "fr10" }, "f10" },
1376 { { "fr11" }, "f11" },
1377 { { "fr12" }, "f12" },
1378 { { "fr13" }, "f13" },
1379 { { "fr14" }, "f14" },
1380 { { "fr15" }, "f15" },
1381 { { "fr16" }, "f16" },
1382 { { "fr17" }, "f17" },
1383 { { "fr18" }, "f18" },
1384 { { "fr19" }, "f19" },
1385 { { "fr20" }, "f20" },
1386 { { "fr21" }, "f21" },
1387 { { "fr22" }, "f22" },
1388 { { "fr23" }, "f23" },
1389 { { "fr24" }, "f24" },
1390 { { "fr25" }, "f25" },
1391 { { "fr26" }, "f26" },
1392 { { "fr27" }, "f27" },
1393 { { "fr28" }, "f28" },
1394 { { "fr29" }, "f29" },
1395 { { "fr30" }, "f30" },
1396 { { "fr31" }, "f31" },
1397 { { "cc" }, "cr0" },
1400 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1401 unsigned &NumAliases) const {
1402 Aliases = GCCRegAliases;
1403 NumAliases = llvm::array_lengthof(GCCRegAliases);
1406 class PPC32TargetInfo : public PPCTargetInfo {
1408 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1409 DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1411 switch (getTriple().getOS()) {
1412 case llvm::Triple::Linux:
1413 case llvm::Triple::FreeBSD:
1414 case llvm::Triple::NetBSD:
1415 SizeType = UnsignedInt;
1416 PtrDiffType = SignedInt;
1417 IntPtrType = SignedInt;
1423 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1424 LongDoubleWidth = LongDoubleAlign = 64;
1425 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1428 // PPC32 supports atomics up to 4 bytes.
1429 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1432 BuiltinVaListKind getBuiltinVaListKind() const override {
1433 // This is the ELF definition, and is overridden by the Darwin sub-target
1434 return TargetInfo::PowerABIBuiltinVaList;
1438 // Note: ABI differences may eventually require us to have a separate
1439 // TargetInfo for little endian.
1440 class PPC64TargetInfo : public PPCTargetInfo {
1442 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1443 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1444 IntMaxType = SignedLong;
1445 Int64Type = SignedLong;
1447 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1448 DescriptionString = "e-m:e-i64:64-n32:64";
1451 DescriptionString = "E-m:e-i64:64-n32:64";
1455 switch (getTriple().getOS()) {
1456 case llvm::Triple::FreeBSD:
1457 LongDoubleWidth = LongDoubleAlign = 64;
1458 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1460 case llvm::Triple::NetBSD:
1461 IntMaxType = SignedLongLong;
1462 Int64Type = SignedLongLong;
1468 // PPC64 supports atomics up to 8 bytes.
1469 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1471 BuiltinVaListKind getBuiltinVaListKind() const override {
1472 return TargetInfo::CharPtrBuiltinVaList;
1474 // PPC64 Linux-specifc ABI options.
1475 bool setABI(const std::string &Name) override {
1476 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1484 class DarwinPPC32TargetInfo :
1485 public DarwinTargetInfo<PPC32TargetInfo> {
1487 DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1488 : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1489 HasAlignMac68kSupport = true;
1490 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1491 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1493 SuitableAlign = 128;
1494 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1496 BuiltinVaListKind getBuiltinVaListKind() const override {
1497 return TargetInfo::CharPtrBuiltinVaList;
1501 class DarwinPPC64TargetInfo :
1502 public DarwinTargetInfo<PPC64TargetInfo> {
1504 DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1505 : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1506 HasAlignMac68kSupport = true;
1507 SuitableAlign = 128;
1508 DescriptionString = "E-m:o-i64:64-n32:64";
1512 static const unsigned NVPTXAddrSpaceMap[] = {
1515 4, // opencl_constant
1516 // FIXME: generic has to be added to the target
1517 0, // opencl_generic
1522 class NVPTXTargetInfo : public TargetInfo {
1523 static const char * const GCCRegNames[];
1524 static const Builtin::Info BuiltinInfo[];
1526 // The GPU profiles supported by the NVPTX backend
1537 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1539 TLSSupported = false;
1540 LongWidth = LongAlign = 64;
1541 AddrSpaceMap = &NVPTXAddrSpaceMap;
1542 UseAddrSpaceMapMangling = true;
1543 // Define available target features
1544 // These must be defined in sorted order!
1545 NoAsmVariants = true;
1546 // Set the default GPU to sm20
1549 void getTargetDefines(const LangOptions &Opts,
1550 MacroBuilder &Builder) const override {
1551 Builder.defineMacro("__PTX__");
1552 Builder.defineMacro("__NVPTX__");
1553 if (Opts.CUDAIsDevice) {
1554 // Set __CUDA_ARCH__ for the GPU specified.
1555 std::string CUDAArchCode;
1558 CUDAArchCode = "200";
1561 CUDAArchCode = "210";
1564 CUDAArchCode = "300";
1567 CUDAArchCode = "350";
1570 CUDAArchCode = "370";
1573 llvm_unreachable("Unhandled target CPU");
1575 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1578 void getTargetBuiltins(const Builtin::Info *&Records,
1579 unsigned &NumRecords) const override {
1580 Records = BuiltinInfo;
1581 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1583 bool hasFeature(StringRef Feature) const override {
1584 return Feature == "ptx" || Feature == "nvptx";
1587 void getGCCRegNames(const char * const *&Names,
1588 unsigned &NumNames) const override;
1589 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1590 unsigned &NumAliases) const override {
1596 validateAsmConstraint(const char *&Name,
1597 TargetInfo::ConstraintInfo &Info) const override {
1599 default: return false;
1606 Info.setAllowsRegister();
1610 const char *getClobbers() const override {
1611 // FIXME: Is this really right?
1614 BuiltinVaListKind getBuiltinVaListKind() const override {
1616 return TargetInfo::CharPtrBuiltinVaList;
1618 bool setCPU(const std::string &Name) override {
1619 GPU = llvm::StringSwitch<GPUKind>(Name)
1620 .Case("sm_20", GK_SM20)
1621 .Case("sm_21", GK_SM21)
1622 .Case("sm_30", GK_SM30)
1623 .Case("sm_35", GK_SM35)
1624 .Case("sm_37", GK_SM37)
1627 return GPU != GK_NONE;
1631 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1632 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1633 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1635 #include "clang/Basic/BuiltinsNVPTX.def"
1638 const char * const NVPTXTargetInfo::GCCRegNames[] = {
1642 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1643 unsigned &NumNames) const {
1644 Names = GCCRegNames;
1645 NumNames = llvm::array_lengthof(GCCRegNames);
1648 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1650 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1651 PointerWidth = PointerAlign = 32;
1652 SizeType = TargetInfo::UnsignedInt;
1653 PtrDiffType = TargetInfo::SignedInt;
1654 IntPtrType = TargetInfo::SignedInt;
1655 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1659 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1661 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1662 PointerWidth = PointerAlign = 64;
1663 SizeType = TargetInfo::UnsignedLong;
1664 PtrDiffType = TargetInfo::SignedLong;
1665 IntPtrType = TargetInfo::SignedLong;
1666 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1670 static const unsigned AMDGPUAddrSpaceMap[] = {
1673 2, // opencl_constant
1674 4, // opencl_generic
1680 // If you edit the description strings, make sure you update
1681 // getPointerWidthV().
1683 static const char *DescriptionStringR600 =
1684 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1685 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1687 static const char *DescriptionStringR600DoubleOps =
1688 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1689 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1691 static const char *DescriptionStringSI =
1692 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1693 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1694 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1696 class AMDGPUTargetInfo : public TargetInfo {
1697 static const Builtin::Info BuiltinInfo[];
1698 static const char * const GCCRegNames[];
1700 /// \brief The GPU profiles supported by the AMDGPU target.
1708 GK_EVERGREEN_DOUBLE_OPS,
1709 GK_NORTHERN_ISLANDS,
1711 GK_SOUTHERN_ISLANDS,
1721 AMDGPUTargetInfo(const llvm::Triple &Triple)
1722 : TargetInfo(Triple) {
1724 if (Triple.getArch() == llvm::Triple::amdgcn) {
1725 DescriptionString = DescriptionStringSI;
1726 GPU = GK_SOUTHERN_ISLANDS;
1731 DescriptionString = DescriptionStringR600;
1737 AddrSpaceMap = &AMDGPUAddrSpaceMap;
1738 UseAddrSpaceMapMangling = true;
1741 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1742 if (GPU <= GK_CAYMAN)
1755 const char * getClobbers() const override {
1759 void getGCCRegNames(const char * const *&Names,
1760 unsigned &NumNames) const override;
1762 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1763 unsigned &NumAliases) const override {
1768 bool validateAsmConstraint(const char *&Name,
1769 TargetInfo::ConstraintInfo &info) const override {
1773 void getTargetBuiltins(const Builtin::Info *&Records,
1774 unsigned &NumRecords) const override {
1775 Records = BuiltinInfo;
1776 NumRecords = clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin;
1779 void getTargetDefines(const LangOptions &Opts,
1780 MacroBuilder &Builder) const override {
1781 Builder.defineMacro("__R600__");
1783 Builder.defineMacro("__HAS_FMAF__");
1785 Builder.defineMacro("__HAS_LDEXPF__");
1786 if (hasFP64 && Opts.OpenCL) {
1787 Builder.defineMacro("cl_khr_fp64");
1791 BuiltinVaListKind getBuiltinVaListKind() const override {
1792 return TargetInfo::CharPtrBuiltinVaList;
1795 bool setCPU(const std::string &Name) override {
1796 GPU = llvm::StringSwitch<GPUKind>(Name)
1797 .Case("r600" , GK_R600)
1798 .Case("rv610", GK_R600)
1799 .Case("rv620", GK_R600)
1800 .Case("rv630", GK_R600)
1801 .Case("rv635", GK_R600)
1802 .Case("rs780", GK_R600)
1803 .Case("rs880", GK_R600)
1804 .Case("rv670", GK_R600_DOUBLE_OPS)
1805 .Case("rv710", GK_R700)
1806 .Case("rv730", GK_R700)
1807 .Case("rv740", GK_R700_DOUBLE_OPS)
1808 .Case("rv770", GK_R700_DOUBLE_OPS)
1809 .Case("palm", GK_EVERGREEN)
1810 .Case("cedar", GK_EVERGREEN)
1811 .Case("sumo", GK_EVERGREEN)
1812 .Case("sumo2", GK_EVERGREEN)
1813 .Case("redwood", GK_EVERGREEN)
1814 .Case("juniper", GK_EVERGREEN)
1815 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
1816 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
1817 .Case("barts", GK_NORTHERN_ISLANDS)
1818 .Case("turks", GK_NORTHERN_ISLANDS)
1819 .Case("caicos", GK_NORTHERN_ISLANDS)
1820 .Case("cayman", GK_CAYMAN)
1821 .Case("aruba", GK_CAYMAN)
1822 .Case("tahiti", GK_SOUTHERN_ISLANDS)
1823 .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1824 .Case("verde", GK_SOUTHERN_ISLANDS)
1825 .Case("oland", GK_SOUTHERN_ISLANDS)
1826 .Case("hainan", GK_SOUTHERN_ISLANDS)
1827 .Case("bonaire", GK_SEA_ISLANDS)
1828 .Case("kabini", GK_SEA_ISLANDS)
1829 .Case("kaveri", GK_SEA_ISLANDS)
1830 .Case("hawaii", GK_SEA_ISLANDS)
1831 .Case("mullins", GK_SEA_ISLANDS)
1832 .Case("tonga", GK_VOLCANIC_ISLANDS)
1833 .Case("iceland", GK_VOLCANIC_ISLANDS)
1834 .Case("carrizo", GK_VOLCANIC_ISLANDS)
1837 if (GPU == GK_NONE) {
1841 // Set the correct data layout
1847 case GK_NORTHERN_ISLANDS:
1848 DescriptionString = DescriptionStringR600;
1853 case GK_R600_DOUBLE_OPS:
1854 case GK_R700_DOUBLE_OPS:
1855 case GK_EVERGREEN_DOUBLE_OPS:
1857 DescriptionString = DescriptionStringR600DoubleOps;
1862 case GK_SOUTHERN_ISLANDS:
1863 case GK_SEA_ISLANDS:
1864 case GK_VOLCANIC_ISLANDS:
1865 DescriptionString = DescriptionStringSI;
1876 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
1877 #define BUILTIN(ID, TYPE, ATTRS) \
1878 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1879 #include "clang/Basic/BuiltinsAMDGPU.def"
1881 const char * const AMDGPUTargetInfo::GCCRegNames[] = {
1882 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1883 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1884 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1885 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1886 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
1887 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
1888 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
1889 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
1890 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
1891 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
1892 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
1893 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
1894 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
1895 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
1896 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
1897 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
1898 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
1899 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
1900 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
1901 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
1902 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
1903 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
1904 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
1905 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
1906 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
1907 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
1908 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
1909 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
1910 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
1911 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
1912 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
1913 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
1914 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1915 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
1916 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
1917 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
1918 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
1919 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
1920 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
1921 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
1922 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
1923 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
1924 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
1925 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
1926 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
1927 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
1928 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
1929 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127"
1930 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi",
1931 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi"
1934 void AMDGPUTargetInfo::getGCCRegNames(const char * const *&Names,
1935 unsigned &NumNames) const {
1936 Names = GCCRegNames;
1937 NumNames = llvm::array_lengthof(GCCRegNames);
1940 // Namespace for x86 abstract base class
1941 const Builtin::Info BuiltinInfo[] = {
1942 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1943 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1945 #include "clang/Basic/BuiltinsX86.def"
1948 static const char* const GCCRegNames[] = {
1949 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1950 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1951 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1952 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1953 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1954 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1955 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1956 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1957 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1960 const TargetInfo::AddlRegName AddlRegNames[] = {
1961 { { "al", "ah", "eax", "rax" }, 0 },
1962 { { "bl", "bh", "ebx", "rbx" }, 3 },
1963 { { "cl", "ch", "ecx", "rcx" }, 2 },
1964 { { "dl", "dh", "edx", "rdx" }, 1 },
1965 { { "esi", "rsi" }, 4 },
1966 { { "edi", "rdi" }, 5 },
1967 { { "esp", "rsp" }, 7 },
1968 { { "ebp", "rbp" }, 6 },
1971 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1972 // most of the implementation can be shared.
1973 class X86TargetInfo : public TargetInfo {
1975 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1978 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
2002 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW,
2007 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2009 /// Each enumeration represents a particular CPU supported by Clang. These
2010 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2015 /// i386-generation processors.
2021 /// i486-generation processors.
2030 /// i586-generation processors, P5 microarchitecture based.
2038 /// i686-generation processors, P6 / Pentium M microarchitecture based.
2048 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2049 /// Clang however has some logic to suport this.
2050 // FIXME: Warn, deprecate, and potentially remove this.
2055 /// Netburst microarchitecture based processors.
2064 /// Core microarchitecture based processors.
2068 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2069 /// codename which GCC no longer accepts as an option to -march, but Clang
2070 /// has some logic for recognizing it.
2071 // FIXME: Warn, deprecate, and potentially remove this.
2083 /// Nehalem microarchitecture based processors.
2087 /// Westmere microarchitecture based processors.
2090 /// \name Sandy Bridge
2091 /// Sandy Bridge microarchitecture based processors.
2094 /// \name Ivy Bridge
2095 /// Ivy Bridge microarchitecture based processors.
2099 /// Haswell microarchitecture based processors.
2103 /// Broadwell microarchitecture based processors.
2107 /// Skylake microarchitecture based processors.
2110 /// \name Knights Landing
2111 /// Knights Landing processor.
2115 /// K6 architecture processors.
2123 /// K7 architecture processors.
2126 CK_AthlonThunderbird,
2133 /// K8 architecture processors.
2146 /// Bobcat architecture processors.
2153 /// Bulldozer architecture processors.
2161 /// This specification is deprecated and will be removed in the future.
2162 /// Users should prefer \see CK_K8.
2163 // FIXME: Warn on this when the CPU is set to it.
2169 /// Geode processors.
2182 X86TargetInfo(const llvm::Triple &Triple)
2183 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
2184 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
2185 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
2186 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
2187 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
2188 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
2189 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
2190 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
2192 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
2194 unsigned getFloatEvalMethod() const override {
2195 // X87 evaluates with 80 bits "long double" precision.
2196 return SSELevel == NoSSE ? 2 : 0;
2198 void getTargetBuiltins(const Builtin::Info *&Records,
2199 unsigned &NumRecords) const override {
2200 Records = BuiltinInfo;
2201 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
2203 void getGCCRegNames(const char * const *&Names,
2204 unsigned &NumNames) const override {
2205 Names = GCCRegNames;
2206 NumNames = llvm::array_lengthof(GCCRegNames);
2208 void getGCCRegAliases(const GCCRegAlias *&Aliases,
2209 unsigned &NumAliases) const override {
2213 void getGCCAddlRegNames(const AddlRegName *&Names,
2214 unsigned &NumNames) const override {
2215 Names = AddlRegNames;
2216 NumNames = llvm::array_lengthof(AddlRegNames);
2218 bool validateAsmConstraint(const char *&Name,
2219 TargetInfo::ConstraintInfo &info) const override;
2221 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2223 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2225 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2227 std::string convertConstraint(const char *&Constraint) const override;
2228 const char *getClobbers() const override {
2229 return "~{dirflag},~{fpsr},~{flags}";
2231 void getTargetDefines(const LangOptions &Opts,
2232 MacroBuilder &Builder) const override;
2233 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2235 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2237 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2239 void setFeatureEnabled(llvm::StringMap<bool> &Features,
2240 StringRef Name, bool Enabled) const override {
2241 setFeatureEnabledImpl(Features, Name, Enabled);
2243 // This exists purely to cut down on the number of virtual calls in
2244 // getDefaultFeatures which calls this repeatedly.
2245 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2246 StringRef Name, bool Enabled);
2247 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
2248 bool hasFeature(StringRef Feature) const override;
2249 bool handleTargetFeatures(std::vector<std::string> &Features,
2250 DiagnosticsEngine &Diags) override;
2251 StringRef getABI() const override {
2252 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2254 else if (getTriple().getArch() == llvm::Triple::x86 &&
2255 MMX3DNowLevel == NoMMX3DNow)
2259 bool setCPU(const std::string &Name) override {
2260 CPU = llvm::StringSwitch<CPUKind>(Name)
2261 .Case("i386", CK_i386)
2262 .Case("i486", CK_i486)
2263 .Case("winchip-c6", CK_WinChipC6)
2264 .Case("winchip2", CK_WinChip2)
2266 .Case("i586", CK_i586)
2267 .Case("pentium", CK_Pentium)
2268 .Case("pentium-mmx", CK_PentiumMMX)
2269 .Case("i686", CK_i686)
2270 .Case("pentiumpro", CK_PentiumPro)
2271 .Case("pentium2", CK_Pentium2)
2272 .Case("pentium3", CK_Pentium3)
2273 .Case("pentium3m", CK_Pentium3M)
2274 .Case("pentium-m", CK_PentiumM)
2275 .Case("c3-2", CK_C3_2)
2276 .Case("yonah", CK_Yonah)
2277 .Case("pentium4", CK_Pentium4)
2278 .Case("pentium4m", CK_Pentium4M)
2279 .Case("prescott", CK_Prescott)
2280 .Case("nocona", CK_Nocona)
2281 .Case("core2", CK_Core2)
2282 .Case("penryn", CK_Penryn)
2283 .Case("bonnell", CK_Bonnell)
2284 .Case("atom", CK_Bonnell) // Legacy name.
2285 .Case("silvermont", CK_Silvermont)
2286 .Case("slm", CK_Silvermont) // Legacy name.
2287 .Case("nehalem", CK_Nehalem)
2288 .Case("corei7", CK_Nehalem) // Legacy name.
2289 .Case("westmere", CK_Westmere)
2290 .Case("sandybridge", CK_SandyBridge)
2291 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2292 .Case("ivybridge", CK_IvyBridge)
2293 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2294 .Case("haswell", CK_Haswell)
2295 .Case("core-avx2", CK_Haswell) // Legacy name.
2296 .Case("broadwell", CK_Broadwell)
2297 .Case("skylake", CK_Skylake)
2298 .Case("skx", CK_Skylake) // Legacy name.
2299 .Case("knl", CK_KNL)
2301 .Case("k6-2", CK_K6_2)
2302 .Case("k6-3", CK_K6_3)
2303 .Case("athlon", CK_Athlon)
2304 .Case("athlon-tbird", CK_AthlonThunderbird)
2305 .Case("athlon-4", CK_Athlon4)
2306 .Case("athlon-xp", CK_AthlonXP)
2307 .Case("athlon-mp", CK_AthlonMP)
2308 .Case("athlon64", CK_Athlon64)
2309 .Case("athlon64-sse3", CK_Athlon64SSE3)
2310 .Case("athlon-fx", CK_AthlonFX)
2312 .Case("k8-sse3", CK_K8SSE3)
2313 .Case("opteron", CK_Opteron)
2314 .Case("opteron-sse3", CK_OpteronSSE3)
2315 .Case("barcelona", CK_AMDFAM10)
2316 .Case("amdfam10", CK_AMDFAM10)
2317 .Case("btver1", CK_BTVER1)
2318 .Case("btver2", CK_BTVER2)
2319 .Case("bdver1", CK_BDVER1)
2320 .Case("bdver2", CK_BDVER2)
2321 .Case("bdver3", CK_BDVER3)
2322 .Case("bdver4", CK_BDVER4)
2323 .Case("x86-64", CK_x86_64)
2324 .Case("geode", CK_Geode)
2325 .Default(CK_Generic);
2327 // Perform any per-CPU checks necessary to determine if this CPU is
2329 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2330 // invalid without explaining *why*.
2333 // No processor selected!
2359 case CK_AthlonThunderbird:
2364 // Only accept certain architectures when compiling in 32-bit mode.
2365 if (getTriple().getArch() != llvm::Triple::x86)
2376 case CK_SandyBridge:
2383 case CK_Athlon64SSE3:
2388 case CK_OpteronSSE3:
2399 llvm_unreachable("Unhandled CPU kind");
2402 bool setFPMath(StringRef Name) override;
2404 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2405 // We accept all non-ARM calling conventions
2406 return (CC == CC_X86ThisCall ||
2407 CC == CC_X86FastCall ||
2408 CC == CC_X86StdCall ||
2409 CC == CC_X86VectorCall ||
2411 CC == CC_X86Pascal ||
2412 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2415 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2416 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2419 bool hasSjLjLowering() const override {
2424 bool X86TargetInfo::setFPMath(StringRef Name) {
2425 if (Name == "387") {
2429 if (Name == "sse") {
2436 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2437 // FIXME: This *really* should not be here.
2439 // X86_64 always has SSE2.
2440 if (getTriple().getArch() == llvm::Triple::x86_64)
2441 setFeatureEnabledImpl(Features, "sse2", true);
2456 setFeatureEnabledImpl(Features, "mmx", true);
2461 setFeatureEnabledImpl(Features, "sse", true);
2467 setFeatureEnabledImpl(Features, "sse2", true);
2472 setFeatureEnabledImpl(Features, "sse3", true);
2473 setFeatureEnabledImpl(Features, "cx16", true);
2477 setFeatureEnabledImpl(Features, "ssse3", true);
2478 setFeatureEnabledImpl(Features, "cx16", true);
2481 setFeatureEnabledImpl(Features, "sse4.1", true);
2482 setFeatureEnabledImpl(Features, "cx16", true);
2485 setFeatureEnabledImpl(Features, "avx512f", true);
2486 setFeatureEnabledImpl(Features, "avx512cd", true);
2487 setFeatureEnabledImpl(Features, "avx512dq", true);
2488 setFeatureEnabledImpl(Features, "avx512bw", true);
2489 setFeatureEnabledImpl(Features, "avx512vl", true);
2492 setFeatureEnabledImpl(Features, "rdseed", true);
2493 setFeatureEnabledImpl(Features, "adx", true);
2496 setFeatureEnabledImpl(Features, "avx2", true);
2497 setFeatureEnabledImpl(Features, "lzcnt", true);
2498 setFeatureEnabledImpl(Features, "bmi", true);
2499 setFeatureEnabledImpl(Features, "bmi2", true);
2500 setFeatureEnabledImpl(Features, "rtm", true);
2501 setFeatureEnabledImpl(Features, "fma", true);
2504 setFeatureEnabledImpl(Features, "rdrnd", true);
2505 setFeatureEnabledImpl(Features, "f16c", true);
2506 setFeatureEnabledImpl(Features, "fsgsbase", true);
2508 case CK_SandyBridge:
2509 setFeatureEnabledImpl(Features, "avx", true);
2513 setFeatureEnabledImpl(Features, "aes", true);
2514 setFeatureEnabledImpl(Features, "pclmul", true);
2517 setFeatureEnabledImpl(Features, "sse4.2", true);
2518 setFeatureEnabledImpl(Features, "cx16", true);
2521 setFeatureEnabledImpl(Features, "avx512f", true);
2522 setFeatureEnabledImpl(Features, "avx512cd", true);
2523 setFeatureEnabledImpl(Features, "avx512er", true);
2524 setFeatureEnabledImpl(Features, "avx512pf", true);
2525 setFeatureEnabledImpl(Features, "rdseed", true);
2526 setFeatureEnabledImpl(Features, "adx", true);
2527 setFeatureEnabledImpl(Features, "lzcnt", true);
2528 setFeatureEnabledImpl(Features, "bmi", true);
2529 setFeatureEnabledImpl(Features, "bmi2", true);
2530 setFeatureEnabledImpl(Features, "rtm", true);
2531 setFeatureEnabledImpl(Features, "fma", true);
2532 setFeatureEnabledImpl(Features, "rdrnd", true);
2533 setFeatureEnabledImpl(Features, "f16c", true);
2534 setFeatureEnabledImpl(Features, "fsgsbase", true);
2535 setFeatureEnabledImpl(Features, "aes", true);
2536 setFeatureEnabledImpl(Features, "pclmul", true);
2537 setFeatureEnabledImpl(Features, "cx16", true);
2543 setFeatureEnabledImpl(Features, "3dnow", true);
2546 case CK_AthlonThunderbird:
2548 setFeatureEnabledImpl(Features, "3dnowa", true);
2553 setFeatureEnabledImpl(Features, "sse", true);
2554 setFeatureEnabledImpl(Features, "3dnowa", true);
2560 setFeatureEnabledImpl(Features, "sse2", true);
2561 setFeatureEnabledImpl(Features, "3dnowa", true);
2564 setFeatureEnabledImpl(Features, "sse4a", true);
2565 setFeatureEnabledImpl(Features, "lzcnt", true);
2566 setFeatureEnabledImpl(Features, "popcnt", true);
2569 case CK_OpteronSSE3:
2570 case CK_Athlon64SSE3:
2571 setFeatureEnabledImpl(Features, "sse3", true);
2572 setFeatureEnabledImpl(Features, "3dnowa", true);
2575 setFeatureEnabledImpl(Features, "avx", true);
2576 setFeatureEnabledImpl(Features, "aes", true);
2577 setFeatureEnabledImpl(Features, "pclmul", true);
2578 setFeatureEnabledImpl(Features, "bmi", true);
2579 setFeatureEnabledImpl(Features, "f16c", true);
2582 setFeatureEnabledImpl(Features, "ssse3", true);
2583 setFeatureEnabledImpl(Features, "sse4a", true);
2584 setFeatureEnabledImpl(Features, "lzcnt", true);
2585 setFeatureEnabledImpl(Features, "popcnt", true);
2586 setFeatureEnabledImpl(Features, "prfchw", true);
2587 setFeatureEnabledImpl(Features, "cx16", true);
2590 setFeatureEnabledImpl(Features, "avx2", true);
2591 setFeatureEnabledImpl(Features, "bmi2", true);
2594 setFeatureEnabledImpl(Features, "fsgsbase", true);
2597 setFeatureEnabledImpl(Features, "bmi", true);
2598 setFeatureEnabledImpl(Features, "fma", true);
2599 setFeatureEnabledImpl(Features, "f16c", true);
2600 setFeatureEnabledImpl(Features, "tbm", true);
2603 // xop implies avx, sse4a and fma4.
2604 setFeatureEnabledImpl(Features, "xop", true);
2605 setFeatureEnabledImpl(Features, "lzcnt", true);
2606 setFeatureEnabledImpl(Features, "aes", true);
2607 setFeatureEnabledImpl(Features, "pclmul", true);
2608 setFeatureEnabledImpl(Features, "prfchw", true);
2609 setFeatureEnabledImpl(Features, "cx16", true);
2614 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2615 X86SSEEnum Level, bool Enabled) {
2619 Features["avx512f"] = true;
2621 Features["avx2"] = true;
2623 Features["avx"] = true;
2625 Features["sse4.2"] = true;
2627 Features["sse4.1"] = true;
2629 Features["ssse3"] = true;
2631 Features["sse3"] = true;
2633 Features["sse2"] = true;
2635 Features["sse"] = true;
2645 Features["sse"] = false;
2647 Features["sse2"] = Features["pclmul"] = Features["aes"] =
2648 Features["sha"] = false;
2650 Features["sse3"] = false;
2651 setXOPLevel(Features, NoXOP, false);
2653 Features["ssse3"] = false;
2655 Features["sse4.1"] = false;
2657 Features["sse4.2"] = false;
2659 Features["fma"] = Features["avx"] = Features["f16c"] = false;
2660 setXOPLevel(Features, FMA4, false);
2662 Features["avx2"] = false;
2664 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2665 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2666 Features["avx512vl"] = false;
2670 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2671 MMX3DNowEnum Level, bool Enabled) {
2674 case AMD3DNowAthlon:
2675 Features["3dnowa"] = true;
2677 Features["3dnow"] = true;
2679 Features["mmx"] = true;
2689 Features["mmx"] = false;
2691 Features["3dnow"] = false;
2692 case AMD3DNowAthlon:
2693 Features["3dnowa"] = false;
2697 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2702 Features["xop"] = true;
2704 Features["fma4"] = true;
2705 setSSELevel(Features, AVX, true);
2707 Features["sse4a"] = true;
2708 setSSELevel(Features, SSE3, true);
2718 Features["sse4a"] = false;
2720 Features["fma4"] = false;
2722 Features["xop"] = false;
2726 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2727 StringRef Name, bool Enabled) {
2728 Features[Name] = Enabled;
2730 if (Name == "mmx") {
2731 setMMXLevel(Features, MMX, Enabled);
2732 } else if (Name == "sse") {
2733 setSSELevel(Features, SSE1, Enabled);
2734 } else if (Name == "sse2") {
2735 setSSELevel(Features, SSE2, Enabled);
2736 } else if (Name == "sse3") {
2737 setSSELevel(Features, SSE3, Enabled);
2738 } else if (Name == "ssse3") {
2739 setSSELevel(Features, SSSE3, Enabled);
2740 } else if (Name == "sse4.2") {
2741 setSSELevel(Features, SSE42, Enabled);
2742 } else if (Name == "sse4.1") {
2743 setSSELevel(Features, SSE41, Enabled);
2744 } else if (Name == "3dnow") {
2745 setMMXLevel(Features, AMD3DNow, Enabled);
2746 } else if (Name == "3dnowa") {
2747 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2748 } else if (Name == "aes") {
2750 setSSELevel(Features, SSE2, Enabled);
2751 } else if (Name == "pclmul") {
2753 setSSELevel(Features, SSE2, Enabled);
2754 } else if (Name == "avx") {
2755 setSSELevel(Features, AVX, Enabled);
2756 } else if (Name == "avx2") {
2757 setSSELevel(Features, AVX2, Enabled);
2758 } else if (Name == "avx512f") {
2759 setSSELevel(Features, AVX512F, Enabled);
2760 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2761 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2763 setSSELevel(Features, AVX512F, Enabled);
2764 } else if (Name == "fma") {
2766 setSSELevel(Features, AVX, Enabled);
2767 } else if (Name == "fma4") {
2768 setXOPLevel(Features, FMA4, Enabled);
2769 } else if (Name == "xop") {
2770 setXOPLevel(Features, XOP, Enabled);
2771 } else if (Name == "sse4a") {
2772 setXOPLevel(Features, SSE4A, Enabled);
2773 } else if (Name == "f16c") {
2775 setSSELevel(Features, AVX, Enabled);
2776 } else if (Name == "sha") {
2778 setSSELevel(Features, SSE2, Enabled);
2782 /// handleTargetFeatures - Perform initialization based on the user
2783 /// configured set of features.
2784 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2785 DiagnosticsEngine &Diags) {
2786 // Remember the maximum enabled sselevel.
2787 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2788 // Ignore disabled features.
2789 if (Features[i][0] == '-')
2792 StringRef Feature = StringRef(Features[i]).substr(1);
2794 if (Feature == "aes") {
2799 if (Feature == "pclmul") {
2804 if (Feature == "lzcnt") {
2809 if (Feature == "rdrnd") {
2814 if (Feature == "fsgsbase") {
2819 if (Feature == "bmi") {
2824 if (Feature == "bmi2") {
2829 if (Feature == "popcnt") {
2834 if (Feature == "rtm") {
2839 if (Feature == "prfchw") {
2844 if (Feature == "rdseed") {
2849 if (Feature == "adx") {
2854 if (Feature == "tbm") {
2859 if (Feature == "fma") {
2864 if (Feature == "f16c") {
2869 if (Feature == "avx512cd") {
2874 if (Feature == "avx512er") {
2879 if (Feature == "avx512pf") {
2884 if (Feature == "avx512dq") {
2889 if (Feature == "avx512bw") {
2894 if (Feature == "avx512vl") {
2899 if (Feature == "sha") {
2904 if (Feature == "cx16") {
2909 assert(Features[i][0] == '+' && "Invalid target feature!");
2910 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2911 .Case("avx512f", AVX512F)
2914 .Case("sse4.2", SSE42)
2915 .Case("sse4.1", SSE41)
2916 .Case("ssse3", SSSE3)
2921 SSELevel = std::max(SSELevel, Level);
2923 MMX3DNowEnum ThreeDNowLevel =
2924 llvm::StringSwitch<MMX3DNowEnum>(Feature)
2925 .Case("3dnowa", AMD3DNowAthlon)
2926 .Case("3dnow", AMD3DNow)
2928 .Default(NoMMX3DNow);
2929 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2931 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2934 .Case("sse4a", SSE4A)
2936 XOPLevel = std::max(XOPLevel, XLevel);
2939 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2940 // Can't do this earlier because we need to be able to explicitly enable
2941 // popcnt and still disable sse4.2.
2942 if (!HasPOPCNT && SSELevel >= SSE42 &&
2943 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2945 Features.push_back("+popcnt");
2948 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2949 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2950 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2952 Features.push_back("+prfchw");
2955 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2956 // matches the selected sse level.
2957 if (FPMath == FP_SSE && SSELevel < SSE1) {
2958 Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2960 } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2961 Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2965 // Don't tell the backend if we're turning off mmx; it will end up disabling
2966 // SSE, which we don't want.
2967 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2969 std::vector<std::string>::iterator it;
2970 it = std::find(Features.begin(), Features.end(), "-mmx");
2971 if (it != Features.end())
2973 else if (SSELevel > NoSSE)
2974 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2978 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2979 /// definitions for this particular subtarget.
2980 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2981 MacroBuilder &Builder) const {
2982 // Target identification.
2983 if (getTriple().getArch() == llvm::Triple::x86_64) {
2984 Builder.defineMacro("__amd64__");
2985 Builder.defineMacro("__amd64");
2986 Builder.defineMacro("__x86_64");
2987 Builder.defineMacro("__x86_64__");
2988 if (getTriple().getArchName() == "x86_64h") {
2989 Builder.defineMacro("__x86_64h");
2990 Builder.defineMacro("__x86_64h__");
2993 DefineStd(Builder, "i386", Opts);
2996 // Subtarget options.
2997 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2998 // truly should be based on -mtune options.
3003 // The rest are coming from the i386 define above.
3004 Builder.defineMacro("__tune_i386__");
3010 defineCPUMacros(Builder, "i486");
3013 Builder.defineMacro("__pentium_mmx__");
3014 Builder.defineMacro("__tune_pentium_mmx__");
3018 defineCPUMacros(Builder, "i586");
3019 defineCPUMacros(Builder, "pentium");
3024 Builder.defineMacro("__tune_pentium3__");
3028 Builder.defineMacro("__tune_pentium2__");
3031 Builder.defineMacro("__tune_i686__");
3032 Builder.defineMacro("__tune_pentiumpro__");
3035 Builder.defineMacro("__i686");
3036 Builder.defineMacro("__i686__");
3037 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3038 Builder.defineMacro("__pentiumpro");
3039 Builder.defineMacro("__pentiumpro__");
3043 defineCPUMacros(Builder, "pentium4");
3048 defineCPUMacros(Builder, "nocona");
3052 defineCPUMacros(Builder, "core2");
3055 defineCPUMacros(Builder, "atom");
3058 defineCPUMacros(Builder, "slm");
3062 case CK_SandyBridge:
3066 // FIXME: Historically, we defined this legacy name, it would be nice to
3067 // remove it at some point. We've never exposed fine-grained names for
3068 // recent primary x86 CPUs, and we should keep it that way.
3069 defineCPUMacros(Builder, "corei7");
3072 // FIXME: Historically, we defined this legacy name, it would be nice to
3073 // remove it at some point. This is the only fine-grained CPU macro in the
3074 // main intel CPU line, and it would be better to not have these and force
3075 // people to use ISA macros.
3076 defineCPUMacros(Builder, "skx");
3079 defineCPUMacros(Builder, "knl");
3082 Builder.defineMacro("__k6_2__");
3083 Builder.defineMacro("__tune_k6_2__");
3086 if (CPU != CK_K6_2) { // In case of fallthrough
3087 // FIXME: GCC may be enabling these in cases where some other k6
3088 // architecture is specified but -m3dnow is explicitly provided. The
3089 // exact semantics need to be determined and emulated here.
3090 Builder.defineMacro("__k6_3__");
3091 Builder.defineMacro("__tune_k6_3__");
3095 defineCPUMacros(Builder, "k6");
3098 case CK_AthlonThunderbird:
3102 defineCPUMacros(Builder, "athlon");
3103 if (SSELevel != NoSSE) {
3104 Builder.defineMacro("__athlon_sse__");
3105 Builder.defineMacro("__tune_athlon_sse__");
3112 case CK_OpteronSSE3:
3114 case CK_Athlon64SSE3:
3116 defineCPUMacros(Builder, "k8");
3119 defineCPUMacros(Builder, "amdfam10");
3122 defineCPUMacros(Builder, "btver1");
3125 defineCPUMacros(Builder, "btver2");
3128 defineCPUMacros(Builder, "bdver1");
3131 defineCPUMacros(Builder, "bdver2");
3134 defineCPUMacros(Builder, "bdver3");
3137 defineCPUMacros(Builder, "bdver4");
3140 defineCPUMacros(Builder, "geode");
3144 // Target properties.
3145 Builder.defineMacro("__REGISTER_PREFIX__", "");
3147 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3148 // functions in glibc header files that use FP Stack inline asm which the
3149 // backend can't deal with (PR879).
3150 Builder.defineMacro("__NO_MATH_INLINES");
3153 Builder.defineMacro("__AES__");
3156 Builder.defineMacro("__PCLMUL__");
3159 Builder.defineMacro("__LZCNT__");
3162 Builder.defineMacro("__RDRND__");
3165 Builder.defineMacro("__FSGSBASE__");
3168 Builder.defineMacro("__BMI__");
3171 Builder.defineMacro("__BMI2__");
3174 Builder.defineMacro("__POPCNT__");
3177 Builder.defineMacro("__RTM__");
3180 Builder.defineMacro("__PRFCHW__");
3183 Builder.defineMacro("__RDSEED__");
3186 Builder.defineMacro("__ADX__");
3189 Builder.defineMacro("__TBM__");
3193 Builder.defineMacro("__XOP__");
3195 Builder.defineMacro("__FMA4__");
3197 Builder.defineMacro("__SSE4A__");
3203 Builder.defineMacro("__FMA__");
3206 Builder.defineMacro("__F16C__");
3209 Builder.defineMacro("__AVX512CD__");
3211 Builder.defineMacro("__AVX512ER__");
3213 Builder.defineMacro("__AVX512PF__");
3215 Builder.defineMacro("__AVX512DQ__");
3217 Builder.defineMacro("__AVX512BW__");
3219 Builder.defineMacro("__AVX512VL__");
3222 Builder.defineMacro("__SHA__");
3225 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3227 // Each case falls through to the previous one here.
3230 Builder.defineMacro("__AVX512F__");
3232 Builder.defineMacro("__AVX2__");
3234 Builder.defineMacro("__AVX__");
3236 Builder.defineMacro("__SSE4_2__");
3238 Builder.defineMacro("__SSE4_1__");
3240 Builder.defineMacro("__SSSE3__");
3242 Builder.defineMacro("__SSE3__");
3244 Builder.defineMacro("__SSE2__");
3245 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
3247 Builder.defineMacro("__SSE__");
3248 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
3253 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3263 Builder.defineMacro("_M_IX86_FP", Twine(2));
3266 Builder.defineMacro("_M_IX86_FP", Twine(1));
3269 Builder.defineMacro("_M_IX86_FP", Twine(0));
3273 // Each case falls through to the previous one here.
3274 switch (MMX3DNowLevel) {
3275 case AMD3DNowAthlon:
3276 Builder.defineMacro("__3dNOW_A__");
3278 Builder.defineMacro("__3dNOW__");
3280 Builder.defineMacro("__MMX__");
3285 if (CPU >= CK_i486) {
3286 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3287 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3288 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3291 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3294 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3295 return llvm::StringSwitch<bool>(Feature)
3296 .Case("aes", HasAES)
3297 .Case("avx", SSELevel >= AVX)
3298 .Case("avx2", SSELevel >= AVX2)
3299 .Case("avx512f", SSELevel >= AVX512F)
3300 .Case("avx512cd", HasAVX512CD)
3301 .Case("avx512er", HasAVX512ER)
3302 .Case("avx512pf", HasAVX512PF)
3303 .Case("avx512dq", HasAVX512DQ)
3304 .Case("avx512bw", HasAVX512BW)
3305 .Case("avx512vl", HasAVX512VL)
3306 .Case("bmi", HasBMI)
3307 .Case("bmi2", HasBMI2)
3308 .Case("cx16", HasCX16)
3309 .Case("f16c", HasF16C)
3310 .Case("fma", HasFMA)
3311 .Case("fma4", XOPLevel >= FMA4)
3312 .Case("fsgsbase", HasFSGSBASE)
3313 .Case("lzcnt", HasLZCNT)
3314 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3315 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3316 .Case("mmx", MMX3DNowLevel >= MMX)
3317 .Case("pclmul", HasPCLMUL)
3318 .Case("popcnt", HasPOPCNT)
3319 .Case("prfchw", HasPRFCHW)
3320 .Case("rdrnd", HasRDRND)
3321 .Case("rdseed", HasRDSEED)
3322 .Case("rtm", HasRTM)
3323 .Case("sha", HasSHA)
3324 .Case("sse", SSELevel >= SSE1)
3325 .Case("sse2", SSELevel >= SSE2)
3326 .Case("sse3", SSELevel >= SSE3)
3327 .Case("ssse3", SSELevel >= SSSE3)
3328 .Case("sse4.1", SSELevel >= SSE41)
3329 .Case("sse4.2", SSELevel >= SSE42)
3330 .Case("sse4a", XOPLevel >= SSE4A)
3331 .Case("tbm", HasTBM)
3333 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3334 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3335 .Case("xop", XOPLevel >= XOP)
3340 X86TargetInfo::validateAsmConstraint(const char *&Name,
3341 TargetInfo::ConstraintInfo &Info) const {
3343 default: return false;
3345 Info.setRequiresImmediate(0, 31);
3348 Info.setRequiresImmediate(0, 63);
3351 Info.setRequiresImmediate(-128, 127);
3354 // FIXME: properly analyze this constraint:
3355 // must be one of 0xff, 0xffff, or 0xffffffff
3358 Info.setRequiresImmediate(0, 3);
3361 Info.setRequiresImmediate(0, 255);
3364 Info.setRequiresImmediate(0, 127);
3366 case 'Y': // first letter of a pair:
3367 switch (*(Name+1)) {
3368 default: return false;
3369 case '0': // First SSE register.
3370 case 't': // Any SSE register, when SSE2 is enabled.
3371 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
3372 case 'm': // any MMX register, when inter-unit moves enabled.
3373 break; // falls through to setAllowsRegister.
3375 case 'f': // any x87 floating point stack register.
3376 // Constraint 'f' cannot be used for output operands.
3377 if (Info.ConstraintStr[0] == '=')
3380 Info.setAllowsRegister();
3388 case 'A': // edx:eax.
3389 case 't': // top of floating point stack.
3390 case 'u': // second from top of floating point stack.
3391 case 'q': // Any register accessible as [r]l: a, b, c, and d.
3392 case 'y': // Any MMX register.
3393 case 'x': // Any SSE register.
3394 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3395 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3396 case 'l': // "Index" registers: any general register that can be used as an
3397 // index in a base+index memory access.
3398 Info.setAllowsRegister();
3400 case 'C': // SSE floating point constant.
3401 case 'G': // x87 floating point constant.
3402 case 'e': // 32-bit signed integer constant for use with zero-extending
3403 // x86_64 instructions.
3404 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3405 // x86_64 instructions.
3410 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3411 unsigned Size) const {
3412 // Strip off constraint modifiers.
3413 while (Constraint[0] == '=' ||
3414 Constraint[0] == '+' ||
3415 Constraint[0] == '&')
3416 Constraint = Constraint.substr(1);
3418 return validateOperandSize(Constraint, Size);
3421 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3422 unsigned Size) const {
3423 return validateOperandSize(Constraint, Size);
3426 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3427 unsigned Size) const {
3428 switch (Constraint[0]) {
3437 // 256-bit ymm registers can be used if target supports AVX.
3438 return Size <= (SSELevel >= AVX ? 256U : 128U);
3445 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3446 switch (*Constraint) {
3447 case 'a': return std::string("{ax}");
3448 case 'b': return std::string("{bx}");
3449 case 'c': return std::string("{cx}");
3450 case 'd': return std::string("{dx}");
3451 case 'S': return std::string("{si}");
3452 case 'D': return std::string("{di}");
3453 case 'p': // address
3454 return std::string("im");
3455 case 't': // top of floating point stack.
3456 return std::string("{st}");
3457 case 'u': // second from top of floating point stack.
3458 return std::string("{st(1)}"); // second from top of floating point stack.
3460 return std::string(1, *Constraint);
3464 // X86-32 generic target
3465 class X86_32TargetInfo : public X86TargetInfo {
3467 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3468 DoubleAlign = LongLongAlign = 32;
3469 LongDoubleWidth = 96;
3470 LongDoubleAlign = 32;
3471 SuitableAlign = 128;
3472 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3473 SizeType = UnsignedInt;
3474 PtrDiffType = SignedInt;
3475 IntPtrType = SignedInt;
3478 // Use fpret for all types.
3479 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3480 (1 << TargetInfo::Double) |
3481 (1 << TargetInfo::LongDouble));
3483 // x86-32 has atomics up to 8 bytes
3484 // FIXME: Check that we actually have cmpxchg8b before setting
3485 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3486 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3488 BuiltinVaListKind getBuiltinVaListKind() const override {
3489 return TargetInfo::CharPtrBuiltinVaList;
3492 int getEHDataRegisterNumber(unsigned RegNo) const override {
3493 if (RegNo == 0) return 0;
3494 if (RegNo == 1) return 2;
3497 bool validateOperandSize(StringRef Constraint,
3498 unsigned Size) const override {
3499 switch (Constraint[0]) {
3515 return X86TargetInfo::validateOperandSize(Constraint, Size);
3519 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3521 NetBSDI386TargetInfo(const llvm::Triple &Triple)
3522 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3524 unsigned getFloatEvalMethod() const override {
3525 unsigned Major, Minor, Micro;
3526 getTriple().getOSVersion(Major, Minor, Micro);
3527 // New NetBSD uses the default rounding mode.
3528 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3529 return X86_32TargetInfo::getFloatEvalMethod();
3530 // NetBSD before 6.99.26 defaults to "double" rounding.
3535 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3537 OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3538 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3539 SizeType = UnsignedLong;
3540 IntPtrType = SignedLong;
3541 PtrDiffType = SignedLong;
3545 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3547 BitrigI386TargetInfo(const llvm::Triple &Triple)
3548 : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3549 SizeType = UnsignedLong;
3550 IntPtrType = SignedLong;
3551 PtrDiffType = SignedLong;
3555 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3557 DarwinI386TargetInfo(const llvm::Triple &Triple)
3558 : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3559 LongDoubleWidth = 128;
3560 LongDoubleAlign = 128;
3561 SuitableAlign = 128;
3562 MaxVectorAlign = 256;
3563 SizeType = UnsignedLong;
3564 IntPtrType = SignedLong;
3565 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3566 HasAlignMac68kSupport = true;
3571 // x86-32 Windows target
3572 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3574 WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3575 : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3576 WCharType = UnsignedShort;
3577 DoubleAlign = LongLongAlign = 64;
3579 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3580 DescriptionString = IsWinCOFF
3581 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
3582 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3584 void getTargetDefines(const LangOptions &Opts,
3585 MacroBuilder &Builder) const override {
3586 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3590 // x86-32 Windows Visual Studio target
3591 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3593 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3594 : WindowsX86_32TargetInfo(Triple) {
3595 LongDoubleWidth = LongDoubleAlign = 64;
3596 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3598 void getTargetDefines(const LangOptions &Opts,
3599 MacroBuilder &Builder) const override {
3600 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3601 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3602 // The value of the following reflects processor type.
3603 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3604 // We lost the original triple, so we use the default.
3605 Builder.defineMacro("_M_IX86", "600");
3608 } // end anonymous namespace
3610 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3611 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang supports
3612 // __declspec natively under -fms-extensions, but we define a no-op __declspec
3613 // macro anyway for pre-processor compatibility.
3614 if (Opts.MicrosoftExt)
3615 Builder.defineMacro("__declspec", "__declspec");
3617 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3619 if (!Opts.MicrosoftExt) {
3620 // Provide macros for all the calling convention keywords. Provide both
3621 // single and double underscore prefixed variants. These are available on
3622 // x64 as well as x86, even though they have no effect.
3623 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3624 for (const char *CC : CCs) {
3625 std::string GCCSpelling = "__attribute__((__";
3627 GCCSpelling += "__))";
3628 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3629 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3634 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3635 Builder.defineMacro("__MSVCRT__");
3636 Builder.defineMacro("__MINGW32__");
3637 addCygMingDefines(Opts, Builder);
3641 // x86-32 MinGW target
3642 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3644 MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3645 : WindowsX86_32TargetInfo(Triple) {}
3646 void getTargetDefines(const LangOptions &Opts,
3647 MacroBuilder &Builder) const override {
3648 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3649 DefineStd(Builder, "WIN32", Opts);
3650 DefineStd(Builder, "WINNT", Opts);
3651 Builder.defineMacro("_X86_");
3652 addMinGWDefines(Opts, Builder);
3656 // x86-32 Cygwin target
3657 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3659 CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3660 : X86_32TargetInfo(Triple) {
3661 TLSSupported = false;
3662 WCharType = UnsignedShort;
3663 DoubleAlign = LongLongAlign = 64;
3664 DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3666 void getTargetDefines(const LangOptions &Opts,
3667 MacroBuilder &Builder) const override {
3668 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3669 Builder.defineMacro("_X86_");
3670 Builder.defineMacro("__CYGWIN__");
3671 Builder.defineMacro("__CYGWIN32__");
3672 addCygMingDefines(Opts, Builder);
3673 DefineStd(Builder, "unix", Opts);
3675 Builder.defineMacro("_GNU_SOURCE");
3679 // x86-32 Haiku target
3680 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3682 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3683 SizeType = UnsignedLong;
3684 IntPtrType = SignedLong;
3685 PtrDiffType = SignedLong;
3686 ProcessIDType = SignedLong;
3687 this->UserLabelPrefix = "";
3688 this->TLSSupported = false;
3690 void getTargetDefines(const LangOptions &Opts,
3691 MacroBuilder &Builder) const override {
3692 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3693 Builder.defineMacro("__INTEL__");
3694 Builder.defineMacro("__HAIKU__");
3699 template<typename Target>
3700 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3702 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3703 MacroBuilder &Builder) const override {
3704 // RTEMS defines; list based off of gcc output
3706 Builder.defineMacro("__rtems__");
3707 Builder.defineMacro("__ELF__");
3711 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3712 this->UserLabelPrefix = "";
3714 switch (Triple.getArch()) {
3716 case llvm::Triple::x86:
3717 // this->MCountName = ".mcount";
3719 case llvm::Triple::mips:
3720 case llvm::Triple::mipsel:
3721 case llvm::Triple::ppc:
3722 case llvm::Triple::ppc64:
3723 case llvm::Triple::ppc64le:
3724 // this->MCountName = "_mcount";
3726 case llvm::Triple::arm:
3727 // this->MCountName = "__mcount";
3733 // x86-32 RTEMS target
3734 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3736 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3737 SizeType = UnsignedLong;
3738 IntPtrType = SignedLong;
3739 PtrDiffType = SignedLong;
3740 this->UserLabelPrefix = "";
3742 void getTargetDefines(const LangOptions &Opts,
3743 MacroBuilder &Builder) const override {
3744 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3745 Builder.defineMacro("__INTEL__");
3746 Builder.defineMacro("__rtems__");
3750 // x86-64 generic target
3751 class X86_64TargetInfo : public X86TargetInfo {
3753 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3754 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3756 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3757 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3758 LongDoubleWidth = 128;
3759 LongDoubleAlign = 128;
3760 LargeArrayMinWidth = 128;
3761 LargeArrayAlign = 128;
3762 SuitableAlign = 128;
3763 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
3764 PtrDiffType = IsX32 ? SignedInt : SignedLong;
3765 IntPtrType = IsX32 ? SignedInt : SignedLong;
3766 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
3767 Int64Type = IsX32 ? SignedLongLong : SignedLong;
3770 // Pointers are 32-bit in x32.
3771 DescriptionString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3773 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
3774 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3776 // Use fpret only for long double.
3777 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3779 // Use fp2ret for _Complex long double.
3780 ComplexLongDoubleUsesFP2Ret = true;
3782 // x86-64 has atomics up to 16 bytes.
3783 MaxAtomicPromoteWidth = 128;
3784 MaxAtomicInlineWidth = 128;
3786 BuiltinVaListKind getBuiltinVaListKind() const override {
3787 return TargetInfo::X86_64ABIBuiltinVaList;
3790 int getEHDataRegisterNumber(unsigned RegNo) const override {
3791 if (RegNo == 0) return 0;
3792 if (RegNo == 1) return 1;
3796 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3797 return (CC == CC_C ||
3798 CC == CC_X86VectorCall ||
3799 CC == CC_IntelOclBicc ||
3800 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3803 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3807 // for x32 we need it here explicitly
3808 bool hasInt128Type() const override { return true; }
3811 // x86-64 Windows target
3812 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3814 WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3815 : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3816 WCharType = UnsignedShort;
3817 LongWidth = LongAlign = 32;
3818 DoubleAlign = LongLongAlign = 64;
3819 IntMaxType = SignedLongLong;
3820 Int64Type = SignedLongLong;
3821 SizeType = UnsignedLongLong;
3822 PtrDiffType = SignedLongLong;
3823 IntPtrType = SignedLongLong;
3824 this->UserLabelPrefix = "";
3827 void getTargetDefines(const LangOptions &Opts,
3828 MacroBuilder &Builder) const override {
3829 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3830 Builder.defineMacro("_WIN64");
3833 BuiltinVaListKind getBuiltinVaListKind() const override {
3834 return TargetInfo::CharPtrBuiltinVaList;
3837 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3840 case CC_X86ThisCall:
3841 case CC_X86FastCall:
3844 case CC_X86VectorCall:
3845 case CC_IntelOclBicc:
3849 return CCCR_Warning;
3854 // x86-64 Windows Visual Studio target
3855 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3857 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3858 : WindowsX86_64TargetInfo(Triple) {
3859 LongDoubleWidth = LongDoubleAlign = 64;
3860 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3862 void getTargetDefines(const LangOptions &Opts,
3863 MacroBuilder &Builder) const override {
3864 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3865 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3866 Builder.defineMacro("_M_X64");
3867 Builder.defineMacro("_M_AMD64");
3871 // x86-64 MinGW target
3872 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3874 MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3875 : WindowsX86_64TargetInfo(Triple) {}
3876 void getTargetDefines(const LangOptions &Opts,
3877 MacroBuilder &Builder) const override {
3878 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3879 DefineStd(Builder, "WIN64", Opts);
3880 Builder.defineMacro("__MINGW64__");
3881 addMinGWDefines(Opts, Builder);
3883 // GCC defines this macro when it is using __gxx_personality_seh0.
3884 if (!Opts.SjLjExceptions)
3885 Builder.defineMacro("__SEH__");
3889 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3891 DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3892 : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3893 Int64Type = SignedLongLong;
3894 MaxVectorAlign = 256;
3895 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3896 llvm::Triple T = llvm::Triple(Triple);
3898 UseSignedCharForObjCBool = false;
3899 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3903 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3905 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3906 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3907 IntMaxType = SignedLongLong;
3908 Int64Type = SignedLongLong;
3912 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3914 BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3915 : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3916 IntMaxType = SignedLongLong;
3917 Int64Type = SignedLongLong;
3921 class ARMTargetInfo : public TargetInfo {
3922 // Possible FPU choices.
3931 // Possible HWDiv features.
3933 HWDivThumb = (1 << 0),
3937 static bool FPUModeIsVFP(FPUMode Mode) {
3938 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3941 static const TargetInfo::GCCRegAlias GCCRegAliases[];
3942 static const char * const GCCRegNames[];
3944 std::string ABI, CPU;
3954 unsigned IsAAPCS : 1;
3955 unsigned IsThumb : 1;
3958 // Initialized via features.
3959 unsigned SoftFloat : 1;
3960 unsigned SoftFloatABI : 1;
3963 unsigned Crypto : 1;
3965 // ACLE 6.5.1 Hardware floating point
3967 HW_FP_HP = (1 << 1), /// half (16-bit)
3968 HW_FP_SP = (1 << 2), /// single (32-bit)
3969 HW_FP_DP = (1 << 3), /// double (64-bit)
3973 static const Builtin::Info BuiltinInfo[];
3975 static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3976 StringRef ArchName = T.getArchName();
3977 if (T.getArch() == llvm::Triple::arm ||
3978 T.getArch() == llvm::Triple::armeb) {
3979 StringRef VersionStr;
3980 if (ArchName.startswith("armv"))
3981 VersionStr = ArchName.substr(4, 1);
3982 else if (ArchName.startswith("armebv"))
3983 VersionStr = ArchName.substr(6, 1);
3987 if (VersionStr.getAsInteger(10, Version))
3989 return Version >= 6;
3991 assert(T.getArch() == llvm::Triple::thumb ||
3992 T.getArch() == llvm::Triple::thumbeb);
3993 StringRef VersionStr;
3994 if (ArchName.startswith("thumbv"))
3995 VersionStr = ArchName.substr(6, 1);
3996 else if (ArchName.startswith("thumbebv"))
3997 VersionStr = ArchName.substr(8, 1);
4001 if (VersionStr.getAsInteger(10, Version))
4003 return Version >= 7;
4006 void setABIAAPCS() {
4009 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4010 const llvm::Triple &T = getTriple();
4012 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig.
4013 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
4014 T.getOS() == llvm::Triple::Bitrig)
4015 SizeType = UnsignedLong;
4017 SizeType = UnsignedInt;
4019 switch (T.getOS()) {
4020 case llvm::Triple::NetBSD:
4021 WCharType = SignedInt;
4023 case llvm::Triple::Win32:
4024 WCharType = UnsignedShort;
4026 case llvm::Triple::Linux:
4028 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
4029 WCharType = UnsignedInt;
4033 UseBitFieldTypeAlignment = true;
4035 ZeroLengthBitfieldBoundary = 0;
4037 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
4038 // so set preferred for small types to 32.
4039 if (T.isOSBinFormatMachO()) {
4041 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4042 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4043 } else if (T.isOSWindows()) {
4044 assert(!BigEndian && "Windows on ARM does not support big endian");
4045 DescriptionString = "e"
4053 } else if (T.isOSNaCl()) {
4054 assert(!BigEndian && "NaCl on ARM does not support big endian");
4055 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
4058 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4059 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4062 // FIXME: Enumerated types are variable width in straight AAPCS.
4066 const llvm::Triple &T = getTriple();
4070 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
4072 // size_t is unsigned int on FreeBSD.
4073 if (T.getOS() == llvm::Triple::FreeBSD)
4074 SizeType = UnsignedInt;
4076 SizeType = UnsignedLong;
4078 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
4079 WCharType = SignedInt;
4081 // Do not respect the alignment of bit-field types when laying out
4082 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
4083 UseBitFieldTypeAlignment = false;
4085 /// gcc forces the alignment to 4 bytes, regardless of the type of the
4086 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
4088 ZeroLengthBitfieldBoundary = 32;
4090 if (T.isOSBinFormatMachO())
4093 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4094 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4098 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4099 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4101 // FIXME: Override "preferred align" for double and long long.
4105 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
4106 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
4107 IsAAPCS(true), HW_FP(0) {
4108 BigEndian = IsBigEndian;
4110 switch (getTriple().getOS()) {
4111 case llvm::Triple::NetBSD:
4112 PtrDiffType = SignedLong;
4115 PtrDiffType = SignedInt;
4119 // {} in inline assembly are neon specifiers, not assembly variant
4121 NoAsmVariants = true;
4123 // FIXME: Should we just treat this as a feature?
4124 IsThumb = getTriple().getArchName().startswith("thumb");
4126 // FIXME: This duplicates code from the driver that sets the -target-abi
4127 // option - this code is used if -target-abi isn't passed and should
4128 // be unified in some way.
4129 if (Triple.isOSBinFormatMachO()) {
4130 // The backend is hardwired to assume AAPCS for M-class processors, ensure
4131 // the frontend matches that.
4132 if (Triple.getEnvironment() == llvm::Triple::EABI ||
4133 Triple.getOS() == llvm::Triple::UnknownOS ||
4134 StringRef(CPU).startswith("cortex-m")) {
4139 } else if (Triple.isOSWindows()) {
4140 // FIXME: this is invalid for WindowsCE
4143 // Select the default based on the platform.
4144 switch (Triple.getEnvironment()) {
4145 case llvm::Triple::Android:
4146 case llvm::Triple::GNUEABI:
4147 case llvm::Triple::GNUEABIHF:
4148 setABI("aapcs-linux");
4150 case llvm::Triple::EABIHF:
4151 case llvm::Triple::EABI:
4154 case llvm::Triple::GNU:
4158 if (Triple.getOS() == llvm::Triple::NetBSD)
4166 // ARM targets default to using the ARM C++ ABI.
4167 TheCXXABI.set(TargetCXXABI::GenericARM);
4169 // ARM has atomics up to 8 bytes
4170 MaxAtomicPromoteWidth = 64;
4171 if (shouldUseInlineAtomic(getTriple()))
4172 MaxAtomicInlineWidth = 64;
4174 // Do force alignment of members that follow zero length bitfields. If
4175 // the alignment of the zero-length bitfield is greater than the member
4176 // that follows it, `bar', `bar' will be aligned as the type of the
4177 // zero length bitfield.
4178 UseZeroLengthBitfieldAlignment = true;
4180 StringRef getABI() const override { return ABI; }
4181 bool setABI(const std::string &Name) override {
4184 // The defaults (above) are for AAPCS, check if we need to change them.
4186 // FIXME: We need support for -meabi... we could just mangle it into the
4188 if (Name == "apcs-gnu") {
4192 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
4199 // FIXME: This should be based on Arch attributes, not CPU names.
4200 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
4201 StringRef ArchName = getTriple().getArchName();
4202 unsigned ArchKind = llvm::ARMTargetParser::parseArch(ArchName);
4203 bool IsV8 = (ArchKind == llvm::ARM::AK_ARMV8A ||
4204 ArchKind == llvm::ARM::AK_ARMV8_1A);
4206 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
4207 Features["vfp2"] = true;
4208 else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
4209 Features["vfp3"] = true;
4210 Features["neon"] = true;
4212 else if (CPU == "cortex-a5") {
4213 Features["vfp4"] = true;
4214 Features["neon"] = true;
4215 } else if (CPU == "swift" || CPU == "cortex-a7" ||
4216 CPU == "cortex-a12" || CPU == "cortex-a15" ||
4217 CPU == "cortex-a17" || CPU == "krait") {
4218 Features["vfp4"] = true;
4219 Features["neon"] = true;
4220 Features["hwdiv"] = true;
4221 Features["hwdiv-arm"] = true;
4222 } else if (CPU == "cyclone" || CPU == "cortex-a53" || CPU == "cortex-a57" ||
4223 CPU == "cortex-a72") {
4224 Features["fp-armv8"] = true;
4225 Features["neon"] = true;
4226 Features["hwdiv"] = true;
4227 Features["hwdiv-arm"] = true;
4228 Features["crc"] = true;
4229 Features["crypto"] = true;
4230 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || IsV8) {
4231 Features["hwdiv"] = true;
4232 Features["hwdiv-arm"] = true;
4233 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" ||
4234 CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") {
4235 Features["hwdiv"] = true;
4239 bool handleTargetFeatures(std::vector<std::string> &Features,
4240 DiagnosticsEngine &Diags) override {
4244 SoftFloat = SoftFloatABI = false;
4247 for (const auto &Feature : Features) {
4248 if (Feature == "+soft-float") {
4250 } else if (Feature == "+soft-float-abi") {
4251 SoftFloatABI = true;
4252 } else if (Feature == "+vfp2") {
4254 HW_FP = HW_FP_SP | HW_FP_DP;
4255 } else if (Feature == "+vfp3") {
4257 HW_FP = HW_FP_SP | HW_FP_DP;
4258 } else if (Feature == "+vfp4") {
4260 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4261 } else if (Feature == "+fp-armv8") {
4263 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4264 } else if (Feature == "+neon") {
4266 HW_FP = HW_FP_SP | HW_FP_DP;
4267 } else if (Feature == "+hwdiv") {
4268 HWDiv |= HWDivThumb;
4269 } else if (Feature == "+hwdiv-arm") {
4271 } else if (Feature == "+crc") {
4273 } else if (Feature == "+crypto") {
4275 } else if (Feature == "+fp-only-sp") {
4280 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4281 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4285 if (FPMath == FP_Neon)
4286 Features.push_back("+neonfp");
4287 else if (FPMath == FP_VFP)
4288 Features.push_back("-neonfp");
4290 // Remove front-end specific options which the backend handles differently.
4292 std::find(Features.begin(), Features.end(), "+soft-float-abi");
4293 if (Feature != Features.end())
4294 Features.erase(Feature);
4299 bool hasFeature(StringRef Feature) const override {
4300 return llvm::StringSwitch<bool>(Feature)
4302 .Case("softfloat", SoftFloat)
4303 .Case("thumb", IsThumb)
4304 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4305 .Case("hwdiv", HWDiv & HWDivThumb)
4306 .Case("hwdiv-arm", HWDiv & HWDivARM)
4309 const char *getCPUDefineSuffix(StringRef Name) const {
4310 if(Name == "generic") {
4311 auto subarch = getTriple().getSubArch();
4313 case llvm::Triple::SubArchType::ARMSubArch_v8_1a:
4320 unsigned ArchKind = llvm::ARMTargetParser::parseCPUArch(Name);
4321 if (ArchKind == llvm::ARM::AK_INVALID)
4324 // For most sub-arches, the build attribute CPU name is enough.
4325 // For Cortex variants, it's slightly different.
4328 return llvm::ARMTargetParser::getCPUAttr(ArchKind);
4329 case llvm::ARM::AK_ARMV6M:
4330 case llvm::ARM::AK_ARMV6SM:
4332 case llvm::ARM::AK_ARMV7:
4333 case llvm::ARM::AK_ARMV7A:
4334 case llvm::ARM::AK_ARMV7S:
4336 case llvm::ARM::AK_ARMV7R:
4338 case llvm::ARM::AK_ARMV7M:
4340 case llvm::ARM::AK_ARMV7EM:
4342 case llvm::ARM::AK_ARMV8A:
4344 case llvm::ARM::AK_ARMV8_1A:
4348 const char *getCPUProfile(StringRef Name) const {
4349 if(Name == "generic") {
4350 auto subarch = getTriple().getSubArch();
4352 case llvm::Triple::SubArchType::ARMSubArch_v8_1a:
4359 unsigned CPUArch = llvm::ARMTargetParser::parseCPUArch(Name);
4360 if (CPUArch == llvm::ARM::AK_INVALID)
4363 StringRef ArchName = llvm::ARMTargetParser::getArchName(CPUArch);
4364 switch(llvm::ARMTargetParser::parseArchProfile(ArchName)) {
4365 case llvm::ARM::PK_A:
4367 case llvm::ARM::PK_R:
4369 case llvm::ARM::PK_M:
4375 bool setCPU(const std::string &Name) override {
4376 if (!getCPUDefineSuffix(Name))
4379 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4380 StringRef Profile = getCPUProfile(Name);
4381 if (Profile == "M" && MaxAtomicInlineWidth) {
4382 MaxAtomicPromoteWidth = 32;
4383 MaxAtomicInlineWidth = 32;
4389 bool setFPMath(StringRef Name) override;
4390 bool supportsThumb(StringRef ArchName, StringRef CPUArch,
4391 unsigned CPUArchVer) const {
4392 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
4393 (CPUArch.find('M') != StringRef::npos);
4395 bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
4396 unsigned CPUArchVer) const {
4397 // We check both CPUArchVer and ArchName because when only triple is
4398 // specified, the default CPU is arm1136j-s.
4399 return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
4400 ArchName.endswith("v8.1a") ||
4401 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
4403 void getTargetDefines(const LangOptions &Opts,
4404 MacroBuilder &Builder) const override {
4405 // Target identification.
4406 Builder.defineMacro("__arm");
4407 Builder.defineMacro("__arm__");
4409 // Target properties.
4410 Builder.defineMacro("__REGISTER_PREFIX__", "");
4412 StringRef CPUArch = getCPUDefineSuffix(CPU);
4413 unsigned int CPUArchVer;
4414 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
4415 llvm_unreachable("Invalid char for architecture version number");
4416 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
4418 // ACLE 6.4.1 ARM/Thumb instruction set architecture
4419 StringRef CPUProfile = getCPUProfile(CPU);
4420 StringRef ArchName = getTriple().getArchName();
4422 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4423 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
4424 if (CPUArch[0] >= '8') {
4425 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4426 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4429 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
4430 // is not defined for the M-profile.
4431 // NOTE that the deffault profile is assumed to be 'A'
4432 if (CPUProfile.empty() || CPUProfile != "M")
4433 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4435 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4436 // Thumb ISA (including v6-M). It is set to 2 if the core supports the
4437 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4438 if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4439 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4440 else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
4441 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4443 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4444 // instruction set such as ARM or Thumb.
4445 Builder.defineMacro("__ARM_32BIT_STATE", "1");
4447 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4449 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4450 if (!CPUProfile.empty())
4451 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4453 // ACLE 6.5.1 Hardware Floating Point
4455 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4458 Builder.defineMacro("__ARM_ACLE", "200");
4460 // Subtarget options.
4462 // FIXME: It's more complicated than this and we don't really support
4464 // Windows on ARM does not "support" interworking
4465 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
4466 Builder.defineMacro("__THUMB_INTERWORK__");
4468 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4469 // Embedded targets on Darwin follow AAPCS, but not EABI.
4470 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4471 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4472 Builder.defineMacro("__ARM_EABI__");
4473 Builder.defineMacro("__ARM_PCS", "1");
4475 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4476 Builder.defineMacro("__ARM_PCS_VFP", "1");
4480 Builder.defineMacro("__SOFTFP__");
4482 if (CPU == "xscale")
4483 Builder.defineMacro("__XSCALE__");
4486 Builder.defineMacro("__THUMBEL__");
4487 Builder.defineMacro("__thumb__");
4488 if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4489 Builder.defineMacro("__thumb2__");
4491 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4492 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4494 // Note, this is always on in gcc, even though it doesn't make sense.
4495 Builder.defineMacro("__APCS_32__");
4497 if (FPUModeIsVFP((FPUMode) FPU)) {
4498 Builder.defineMacro("__VFP_FP__");
4500 Builder.defineMacro("__ARM_VFPV2__");
4502 Builder.defineMacro("__ARM_VFPV3__");
4504 Builder.defineMacro("__ARM_VFPV4__");
4507 // This only gets set when Neon instructions are actually available, unlike
4508 // the VFP define, hence the soft float and arch check. This is subtly
4509 // different from gcc, we follow the intent which was that it should be set
4510 // when Neon instructions are actually available.
4511 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
4512 Builder.defineMacro("__ARM_NEON");
4513 Builder.defineMacro("__ARM_NEON__");
4516 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4517 Opts.ShortWChar ? "2" : "4");
4519 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4520 Opts.ShortEnums ? "1" : "4");
4523 Builder.defineMacro("__ARM_FEATURE_CRC32");
4526 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4528 if (CPUArchVer >= 6 && CPUArch != "6M") {
4529 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4530 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4531 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4532 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4535 bool is5EOrAbove = (CPUArchVer >= 6 ||
4537 CPUArch.find('E') != StringRef::npos));
4538 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer));
4539 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM"))
4540 Builder.defineMacro("__ARM_FEATURE_DSP");
4542 void getTargetBuiltins(const Builtin::Info *&Records,
4543 unsigned &NumRecords) const override {
4544 Records = BuiltinInfo;
4545 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4547 bool isCLZForZeroUndef() const override { return false; }
4548 BuiltinVaListKind getBuiltinVaListKind() const override {
4549 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4551 void getGCCRegNames(const char * const *&Names,
4552 unsigned &NumNames) const override;
4553 void getGCCRegAliases(const GCCRegAlias *&Aliases,
4554 unsigned &NumAliases) const override;
4555 bool validateAsmConstraint(const char *&Name,
4556 TargetInfo::ConstraintInfo &Info) const override {
4561 case 'w': // VFP Floating point register single precision
4562 case 'P': // VFP Floating point register double precision
4563 Info.setAllowsRegister();
4572 case 'Q': // A memory address that is a single base register.
4573 Info.setAllowsMemory();
4575 case 'U': // a memory reference...
4577 case 'q': // ...ARMV4 ldrsb
4578 case 'v': // ...VFP load/store (reg+constant offset)
4579 case 'y': // ...iWMMXt load/store
4580 case 't': // address valid for load/store opaque types wider
4582 case 'n': // valid address for Neon doubleword vector load/store
4583 case 'm': // valid address for Neon element and structure load/store
4584 case 's': // valid address for non-offset loads/stores of quad-word
4585 // values in four ARM registers
4586 Info.setAllowsMemory();
4593 std::string convertConstraint(const char *&Constraint) const override {
4595 switch (*Constraint) {
4596 case 'U': // Two-character constraint; add "^" hint for later parsing.
4597 R = std::string("^") + std::string(Constraint, 2);
4600 case 'p': // 'p' should be translated to 'r' by default.
4601 R = std::string("r");
4604 return std::string(1, *Constraint);
4609 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4610 std::string &SuggestedModifier) const override {
4611 bool isOutput = (Constraint[0] == '=');
4612 bool isInOut = (Constraint[0] == '+');
4614 // Strip off constraint modifiers.
4615 while (Constraint[0] == '=' ||
4616 Constraint[0] == '+' ||
4617 Constraint[0] == '&')
4618 Constraint = Constraint.substr(1);
4620 switch (Constraint[0]) {
4625 return (isInOut || isOutput || Size <= 64);
4627 // A register of size 32 cannot fit a vector type.
4635 const char *getClobbers() const override {
4636 // FIXME: Is this really right?
4640 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4641 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4644 int getEHDataRegisterNumber(unsigned RegNo) const override {
4645 if (RegNo == 0) return 0;
4646 if (RegNo == 1) return 1;
4651 bool ARMTargetInfo::setFPMath(StringRef Name) {
4652 if (Name == "neon") {
4655 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4663 const char * const ARMTargetInfo::GCCRegNames[] = {
4664 // Integer registers
4665 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4666 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4669 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4670 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4671 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4672 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4675 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4676 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4677 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4678 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4681 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4682 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4685 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4686 unsigned &NumNames) const {
4687 Names = GCCRegNames;
4688 NumNames = llvm::array_lengthof(GCCRegNames);
4691 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4701 { { "v6", "rfp" }, "r9" },
4702 { { "sl" }, "r10" },
4703 { { "fp" }, "r11" },
4704 { { "ip" }, "r12" },
4705 { { "r13" }, "sp" },
4706 { { "r14" }, "lr" },
4707 { { "r15" }, "pc" },
4708 // The S, D and Q registers overlap, but aren't really aliases; we
4709 // don't want to substitute one of these for a different-sized one.
4712 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4713 unsigned &NumAliases) const {
4714 Aliases = GCCRegAliases;
4715 NumAliases = llvm::array_lengthof(GCCRegAliases);
4718 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4719 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4720 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4722 #include "clang/Basic/BuiltinsNEON.def"
4724 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4725 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4726 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4728 #include "clang/Basic/BuiltinsARM.def"
4731 class ARMleTargetInfo : public ARMTargetInfo {
4733 ARMleTargetInfo(const llvm::Triple &Triple)
4734 : ARMTargetInfo(Triple, false) { }
4735 void getTargetDefines(const LangOptions &Opts,
4736 MacroBuilder &Builder) const override {
4737 Builder.defineMacro("__ARMEL__");
4738 ARMTargetInfo::getTargetDefines(Opts, Builder);
4742 class ARMbeTargetInfo : public ARMTargetInfo {
4744 ARMbeTargetInfo(const llvm::Triple &Triple)
4745 : ARMTargetInfo(Triple, true) { }
4746 void getTargetDefines(const LangOptions &Opts,
4747 MacroBuilder &Builder) const override {
4748 Builder.defineMacro("__ARMEB__");
4749 Builder.defineMacro("__ARM_BIG_ENDIAN");
4750 ARMTargetInfo::getTargetDefines(Opts, Builder);
4754 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4755 const llvm::Triple Triple;
4757 WindowsARMTargetInfo(const llvm::Triple &Triple)
4758 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4759 TLSSupported = false;
4760 WCharType = UnsignedShort;
4761 SizeType = UnsignedInt;
4762 UserLabelPrefix = "";
4764 void getVisualStudioDefines(const LangOptions &Opts,
4765 MacroBuilder &Builder) const {
4766 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4768 // FIXME: this is invalid for WindowsCE
4769 Builder.defineMacro("_M_ARM_NT", "1");
4770 Builder.defineMacro("_M_ARMT", "_M_ARM");
4771 Builder.defineMacro("_M_THUMB", "_M_ARM");
4773 assert((Triple.getArch() == llvm::Triple::arm ||
4774 Triple.getArch() == llvm::Triple::thumb) &&
4775 "invalid architecture for Windows ARM target info");
4776 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4777 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4779 // TODO map the complete set of values
4780 // 31: VFPv3 40: VFPv4
4781 Builder.defineMacro("_M_ARM_FP", "31");
4783 BuiltinVaListKind getBuiltinVaListKind() const override {
4784 return TargetInfo::CharPtrBuiltinVaList;
4788 // Windows ARM + Itanium C++ ABI Target
4789 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4791 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4792 : WindowsARMTargetInfo(Triple) {
4793 TheCXXABI.set(TargetCXXABI::GenericARM);
4796 void getTargetDefines(const LangOptions &Opts,
4797 MacroBuilder &Builder) const override {
4798 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4800 if (Opts.MSVCCompat)
4801 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4805 // Windows ARM, MS (C++) ABI
4806 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4808 MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4809 : WindowsARMTargetInfo(Triple) {
4810 TheCXXABI.set(TargetCXXABI::Microsoft);
4813 void getTargetDefines(const LangOptions &Opts,
4814 MacroBuilder &Builder) const override {
4815 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4816 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4820 class DarwinARMTargetInfo :
4821 public DarwinTargetInfo<ARMleTargetInfo> {
4823 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4824 MacroBuilder &Builder) const override {
4825 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4829 DarwinARMTargetInfo(const llvm::Triple &Triple)
4830 : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4831 HasAlignMac68kSupport = true;
4832 // iOS always has 64-bit atomic instructions.
4833 // FIXME: This should be based off of the target features in
4835 MaxAtomicInlineWidth = 64;
4837 // Darwin on iOS uses a variant of the ARM C++ ABI.
4838 TheCXXABI.set(TargetCXXABI::iOS);
4842 class AArch64TargetInfo : public TargetInfo {
4843 virtual void setDescriptionString() = 0;
4844 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4845 static const char *const GCCRegNames[];
4856 static const Builtin::Info BuiltinInfo[];
4861 AArch64TargetInfo(const llvm::Triple &Triple)
4862 : TargetInfo(Triple), ABI("aapcs") {
4864 if (getTriple().getOS() == llvm::Triple::NetBSD) {
4865 WCharType = SignedInt;
4867 // NetBSD apparently prefers consistency across ARM targets to consistency
4868 // across 64-bit targets.
4869 Int64Type = SignedLongLong;
4870 IntMaxType = SignedLongLong;
4872 WCharType = UnsignedInt;
4873 Int64Type = SignedLong;
4874 IntMaxType = SignedLong;
4877 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4878 MaxVectorAlign = 128;
4880 MaxAtomicInlineWidth = 128;
4881 MaxAtomicPromoteWidth = 128;
4883 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
4884 LongDoubleFormat = &llvm::APFloat::IEEEquad;
4886 // {} in inline assembly are neon specifiers, not assembly variant
4888 NoAsmVariants = true;
4890 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
4891 // contributes to the alignment of the containing aggregate in the same way
4892 // a plain (non bit-field) member of that type would, without exception for
4893 // zero-sized or anonymous bit-fields."
4894 UseBitFieldTypeAlignment = true;
4895 UseZeroLengthBitfieldAlignment = true;
4897 // AArch64 targets default to using the ARM C++ ABI.
4898 TheCXXABI.set(TargetCXXABI::GenericAArch64);
4901 StringRef getABI() const override { return ABI; }
4902 bool setABI(const std::string &Name) override {
4903 if (Name != "aapcs" && Name != "darwinpcs")
4910 bool setCPU(const std::string &Name) override {
4911 bool CPUKnown = llvm::StringSwitch<bool>(Name)
4912 .Case("generic", true)
4913 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true)
4914 .Case("cyclone", true)
4919 void getTargetDefines(const LangOptions &Opts,
4920 MacroBuilder &Builder) const override {
4921 // Target identification.
4922 Builder.defineMacro("__aarch64__");
4924 // Target properties.
4925 Builder.defineMacro("_LP64");
4926 Builder.defineMacro("__LP64__");
4928 // ACLE predefines. Many can only have one possible value on v8 AArch64.
4929 Builder.defineMacro("__ARM_ACLE", "200");
4930 Builder.defineMacro("__ARM_ARCH", "8");
4931 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4933 Builder.defineMacro("__ARM_64BIT_STATE");
4934 Builder.defineMacro("__ARM_PCS_AAPCS64");
4935 Builder.defineMacro("__ARM_ARCH_ISA_A64");
4937 Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4938 Builder.defineMacro("__ARM_FEATURE_CLZ");
4939 Builder.defineMacro("__ARM_FEATURE_FMA");
4940 Builder.defineMacro("__ARM_FEATURE_DIV");
4941 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
4942 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
4943 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4944 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4946 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4948 // 0xe implies support for half, single and double precision operations.
4949 Builder.defineMacro("__ARM_FP", "0xe");
4951 // PCS specifies this for SysV variants, which is all we support. Other ABIs
4952 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4953 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4955 if (Opts.FastMath || Opts.FiniteMathOnly)
4956 Builder.defineMacro("__ARM_FP_FAST");
4958 if (Opts.C99 && !Opts.Freestanding)
4959 Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4961 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4963 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4964 Opts.ShortEnums ? "1" : "4");
4966 if (FPU == NeonMode) {
4967 Builder.defineMacro("__ARM_NEON");
4968 // 64-bit NEON supports half, single and double precision operations.
4969 Builder.defineMacro("__ARM_NEON_FP", "0xe");
4973 Builder.defineMacro("__ARM_FEATURE_CRC32");
4976 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4978 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
4979 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4980 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4981 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4982 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4985 void getTargetBuiltins(const Builtin::Info *&Records,
4986 unsigned &NumRecords) const override {
4987 Records = BuiltinInfo;
4988 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
4991 bool hasFeature(StringRef Feature) const override {
4992 return Feature == "aarch64" ||
4993 Feature == "arm64" ||
4994 (Feature == "neon" && FPU == NeonMode);
4997 bool handleTargetFeatures(std::vector<std::string> &Features,
4998 DiagnosticsEngine &Diags) override {
5002 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
5003 if (Features[i] == "+neon")
5005 if (Features[i] == "+crc")
5007 if (Features[i] == "+crypto")
5011 setDescriptionString();
5016 bool isCLZForZeroUndef() const override { return false; }
5018 BuiltinVaListKind getBuiltinVaListKind() const override {
5019 return TargetInfo::AArch64ABIBuiltinVaList;
5022 void getGCCRegNames(const char *const *&Names,
5023 unsigned &NumNames) const override;
5024 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5025 unsigned &NumAliases) const override;
5027 bool validateAsmConstraint(const char *&Name,
5028 TargetInfo::ConstraintInfo &Info) const override {
5032 case 'w': // Floating point and SIMD registers (V0-V31)
5033 Info.setAllowsRegister();
5035 case 'I': // Constant that can be used with an ADD instruction
5036 case 'J': // Constant that can be used with a SUB instruction
5037 case 'K': // Constant that can be used with a 32-bit logical instruction
5038 case 'L': // Constant that can be used with a 64-bit logical instruction
5039 case 'M': // Constant that can be used as a 32-bit MOV immediate
5040 case 'N': // Constant that can be used as a 64-bit MOV immediate
5041 case 'Y': // Floating point constant zero
5042 case 'Z': // Integer constant zero
5044 case 'Q': // A memory reference with base register and no offset
5045 Info.setAllowsMemory();
5047 case 'S': // A symbolic address
5048 Info.setAllowsRegister();
5051 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
5052 // Utf: A memory address suitable for ldp/stp in TF mode.
5053 // Usa: An absolute symbolic address.
5054 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
5055 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
5056 case 'z': // Zero register, wzr or xzr
5057 Info.setAllowsRegister();
5059 case 'x': // Floating point and SIMD registers (V0-V15)
5060 Info.setAllowsRegister();
5067 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5068 std::string &SuggestedModifier) const override {
5069 // Strip off constraint modifiers.
5070 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
5071 Constraint = Constraint.substr(1);
5073 switch (Constraint[0]) {
5081 // For now assume that the person knows what they're
5082 // doing with the modifier.
5085 // By default an 'r' constraint will be in the 'x'
5090 SuggestedModifier = "w";
5097 const char *getClobbers() const override { return ""; }
5099 int getEHDataRegisterNumber(unsigned RegNo) const override {
5108 const char *const AArch64TargetInfo::GCCRegNames[] = {
5109 // 32-bit Integer registers
5110 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
5111 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
5112 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
5114 // 64-bit Integer registers
5115 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
5116 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
5117 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
5119 // 32-bit floating point regsisters
5120 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
5121 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
5122 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5124 // 64-bit floating point regsisters
5125 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
5126 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
5127 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5130 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
5131 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
5132 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
5135 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
5136 unsigned &NumNames) const {
5137 Names = GCCRegNames;
5138 NumNames = llvm::array_lengthof(GCCRegNames);
5141 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
5142 { { "w31" }, "wsp" },
5143 { { "x29" }, "fp" },
5144 { { "x30" }, "lr" },
5145 { { "x31" }, "sp" },
5146 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
5147 // don't want to substitute one of these for a different-sized one.
5150 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5151 unsigned &NumAliases) const {
5152 Aliases = GCCRegAliases;
5153 NumAliases = llvm::array_lengthof(GCCRegAliases);
5156 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
5157 #define BUILTIN(ID, TYPE, ATTRS) \
5158 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5159 #include "clang/Basic/BuiltinsNEON.def"
5161 #define BUILTIN(ID, TYPE, ATTRS) \
5162 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5163 #include "clang/Basic/BuiltinsAArch64.def"
5166 class AArch64leTargetInfo : public AArch64TargetInfo {
5167 void setDescriptionString() override {
5168 if (getTriple().isOSBinFormatMachO())
5169 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
5171 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
5175 AArch64leTargetInfo(const llvm::Triple &Triple)
5176 : AArch64TargetInfo(Triple) {
5179 void getTargetDefines(const LangOptions &Opts,
5180 MacroBuilder &Builder) const override {
5181 Builder.defineMacro("__AARCH64EL__");
5182 AArch64TargetInfo::getTargetDefines(Opts, Builder);
5186 class AArch64beTargetInfo : public AArch64TargetInfo {
5187 void setDescriptionString() override {
5188 assert(!getTriple().isOSBinFormatMachO());
5189 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
5193 AArch64beTargetInfo(const llvm::Triple &Triple)
5194 : AArch64TargetInfo(Triple) { }
5195 void getTargetDefines(const LangOptions &Opts,
5196 MacroBuilder &Builder) const override {
5197 Builder.defineMacro("__AARCH64EB__");
5198 Builder.defineMacro("__AARCH_BIG_ENDIAN");
5199 Builder.defineMacro("__ARM_BIG_ENDIAN");
5200 AArch64TargetInfo::getTargetDefines(Opts, Builder);
5204 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
5206 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5207 MacroBuilder &Builder) const override {
5208 Builder.defineMacro("__AARCH64_SIMD__");
5209 Builder.defineMacro("__ARM64_ARCH_8__");
5210 Builder.defineMacro("__ARM_NEON__");
5211 Builder.defineMacro("__LITTLE_ENDIAN__");
5212 Builder.defineMacro("__REGISTER_PREFIX__", "");
5213 Builder.defineMacro("__arm64", "1");
5214 Builder.defineMacro("__arm64__", "1");
5216 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5220 DarwinAArch64TargetInfo(const llvm::Triple &Triple)
5221 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
5222 Int64Type = SignedLongLong;
5223 WCharType = SignedInt;
5224 UseSignedCharForObjCBool = false;
5226 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
5227 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5229 TheCXXABI.set(TargetCXXABI::iOS64);
5232 BuiltinVaListKind getBuiltinVaListKind() const override {
5233 return TargetInfo::CharPtrBuiltinVaList;
5237 // Hexagon abstract base class
5238 class HexagonTargetInfo : public TargetInfo {
5239 static const Builtin::Info BuiltinInfo[];
5240 static const char * const GCCRegNames[];
5241 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5244 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5246 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
5248 // {} in inline assembly are packet specifiers, not assembly variant
5250 NoAsmVariants = true;
5253 void getTargetBuiltins(const Builtin::Info *&Records,
5254 unsigned &NumRecords) const override {
5255 Records = BuiltinInfo;
5256 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
5259 bool validateAsmConstraint(const char *&Name,
5260 TargetInfo::ConstraintInfo &Info) const override {
5264 void getTargetDefines(const LangOptions &Opts,
5265 MacroBuilder &Builder) const override;
5267 bool hasFeature(StringRef Feature) const override {
5268 return Feature == "hexagon";
5271 BuiltinVaListKind getBuiltinVaListKind() const override {
5272 return TargetInfo::CharPtrBuiltinVaList;
5274 void getGCCRegNames(const char * const *&Names,
5275 unsigned &NumNames) const override;
5276 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5277 unsigned &NumAliases) const override;
5278 const char *getClobbers() const override {
5282 static const char *getHexagonCPUSuffix(StringRef Name) {
5283 return llvm::StringSwitch<const char*>(Name)
5284 .Case("hexagonv4", "4")
5285 .Case("hexagonv5", "5")
5289 bool setCPU(const std::string &Name) override {
5290 if (!getHexagonCPUSuffix(Name))
5298 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5299 MacroBuilder &Builder) const {
5300 Builder.defineMacro("qdsp6");
5301 Builder.defineMacro("__qdsp6", "1");
5302 Builder.defineMacro("__qdsp6__", "1");
5304 Builder.defineMacro("hexagon");
5305 Builder.defineMacro("__hexagon", "1");
5306 Builder.defineMacro("__hexagon__", "1");
5308 if(CPU == "hexagonv1") {
5309 Builder.defineMacro("__HEXAGON_V1__");
5310 Builder.defineMacro("__HEXAGON_ARCH__", "1");
5311 if(Opts.HexagonQdsp6Compat) {
5312 Builder.defineMacro("__QDSP6_V1__");
5313 Builder.defineMacro("__QDSP6_ARCH__", "1");
5316 else if(CPU == "hexagonv2") {
5317 Builder.defineMacro("__HEXAGON_V2__");
5318 Builder.defineMacro("__HEXAGON_ARCH__", "2");
5319 if(Opts.HexagonQdsp6Compat) {
5320 Builder.defineMacro("__QDSP6_V2__");
5321 Builder.defineMacro("__QDSP6_ARCH__", "2");
5324 else if(CPU == "hexagonv3") {
5325 Builder.defineMacro("__HEXAGON_V3__");
5326 Builder.defineMacro("__HEXAGON_ARCH__", "3");
5327 if(Opts.HexagonQdsp6Compat) {
5328 Builder.defineMacro("__QDSP6_V3__");
5329 Builder.defineMacro("__QDSP6_ARCH__", "3");
5332 else if(CPU == "hexagonv4") {
5333 Builder.defineMacro("__HEXAGON_V4__");
5334 Builder.defineMacro("__HEXAGON_ARCH__", "4");
5335 if(Opts.HexagonQdsp6Compat) {
5336 Builder.defineMacro("__QDSP6_V4__");
5337 Builder.defineMacro("__QDSP6_ARCH__", "4");
5340 else if(CPU == "hexagonv5") {
5341 Builder.defineMacro("__HEXAGON_V5__");
5342 Builder.defineMacro("__HEXAGON_ARCH__", "5");
5343 if(Opts.HexagonQdsp6Compat) {
5344 Builder.defineMacro("__QDSP6_V5__");
5345 Builder.defineMacro("__QDSP6_ARCH__", "5");
5350 const char * const HexagonTargetInfo::GCCRegNames[] = {
5351 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5352 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5353 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5354 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5355 "p0", "p1", "p2", "p3",
5356 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5359 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
5360 unsigned &NumNames) const {
5361 Names = GCCRegNames;
5362 NumNames = llvm::array_lengthof(GCCRegNames);
5366 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5367 { { "sp" }, "r29" },
5368 { { "fp" }, "r30" },
5369 { { "lr" }, "r31" },
5372 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5373 unsigned &NumAliases) const {
5374 Aliases = GCCRegAliases;
5375 NumAliases = llvm::array_lengthof(GCCRegAliases);
5379 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5380 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5381 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5383 #include "clang/Basic/BuiltinsHexagon.def"
5386 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5387 class SparcTargetInfo : public TargetInfo {
5388 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5389 static const char * const GCCRegNames[];
5392 SparcTargetInfo(const llvm::Triple &Triple)
5393 : TargetInfo(Triple), SoftFloat(false) {}
5395 bool handleTargetFeatures(std::vector<std::string> &Features,
5396 DiagnosticsEngine &Diags) override {
5397 // The backend doesn't actually handle soft float yet, but in case someone
5398 // is using the support for the front end continue to support it.
5399 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
5400 if (Feature != Features.end()) {
5402 Features.erase(Feature);
5406 void getTargetDefines(const LangOptions &Opts,
5407 MacroBuilder &Builder) const override {
5408 DefineStd(Builder, "sparc", Opts);
5409 Builder.defineMacro("__REGISTER_PREFIX__", "");
5412 Builder.defineMacro("SOFT_FLOAT", "1");
5415 bool hasFeature(StringRef Feature) const override {
5416 return llvm::StringSwitch<bool>(Feature)
5417 .Case("softfloat", SoftFloat)
5418 .Case("sparc", true)
5422 void getTargetBuiltins(const Builtin::Info *&Records,
5423 unsigned &NumRecords) const override {
5424 // FIXME: Implement!
5426 BuiltinVaListKind getBuiltinVaListKind() const override {
5427 return TargetInfo::VoidPtrBuiltinVaList;
5429 void getGCCRegNames(const char * const *&Names,
5430 unsigned &NumNames) const override;
5431 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5432 unsigned &NumAliases) const override;
5433 bool validateAsmConstraint(const char *&Name,
5434 TargetInfo::ConstraintInfo &info) const override {
5435 // FIXME: Implement!
5437 case 'I': // Signed 13-bit constant
5439 case 'K': // 32-bit constant with the low 12 bits clear
5440 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5441 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5442 case 'N': // Same as 'K' but zext (required for SIMode)
5443 case 'O': // The constant 4096
5448 const char *getClobbers() const override {
5449 // FIXME: Implement!
5454 const char * const SparcTargetInfo::GCCRegNames[] = {
5455 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5456 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5457 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5458 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5461 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5462 unsigned &NumNames) const {
5463 Names = GCCRegNames;
5464 NumNames = llvm::array_lengthof(GCCRegNames);
5467 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5478 { { "o2" }, "r10" },
5479 { { "o3" }, "r11" },
5480 { { "o4" }, "r12" },
5481 { { "o5" }, "r13" },
5482 { { "o6", "sp" }, "r14" },
5483 { { "o7" }, "r15" },
5484 { { "l0" }, "r16" },
5485 { { "l1" }, "r17" },
5486 { { "l2" }, "r18" },
5487 { { "l3" }, "r19" },
5488 { { "l4" }, "r20" },
5489 { { "l5" }, "r21" },
5490 { { "l6" }, "r22" },
5491 { { "l7" }, "r23" },
5492 { { "i0" }, "r24" },
5493 { { "i1" }, "r25" },
5494 { { "i2" }, "r26" },
5495 { { "i3" }, "r27" },
5496 { { "i4" }, "r28" },
5497 { { "i5" }, "r29" },
5498 { { "i6", "fp" }, "r30" },
5499 { { "i7" }, "r31" },
5502 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5503 unsigned &NumAliases) const {
5504 Aliases = GCCRegAliases;
5505 NumAliases = llvm::array_lengthof(GCCRegAliases);
5508 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
5509 class SparcV8TargetInfo : public SparcTargetInfo {
5511 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5512 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5513 // NetBSD uses long (same as llvm default); everyone else uses int.
5514 if (getTriple().getOS() == llvm::Triple::NetBSD) {
5515 SizeType = UnsignedLong;
5516 IntPtrType = SignedLong;
5517 PtrDiffType = SignedLong;
5519 SizeType = UnsignedInt;
5520 IntPtrType = SignedInt;
5521 PtrDiffType = SignedInt;
5525 void getTargetDefines(const LangOptions &Opts,
5526 MacroBuilder &Builder) const override {
5527 SparcTargetInfo::getTargetDefines(Opts, Builder);
5528 Builder.defineMacro("__sparcv8");
5532 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
5533 class SparcV8elTargetInfo : public SparcV8TargetInfo {
5535 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) {
5536 DescriptionString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64";
5541 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5542 class SparcV9TargetInfo : public SparcTargetInfo {
5544 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5545 // FIXME: Support Sparc quad-precision long double?
5546 DescriptionString = "E-m:e-i64:64-n32:64-S128";
5547 // This is an LP64 platform.
5548 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5550 // OpenBSD uses long long for int64_t and intmax_t.
5551 if (getTriple().getOS() == llvm::Triple::OpenBSD)
5552 IntMaxType = SignedLongLong;
5554 IntMaxType = SignedLong;
5555 Int64Type = IntMaxType;
5557 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5558 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5559 LongDoubleWidth = 128;
5560 LongDoubleAlign = 128;
5561 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5562 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5565 void getTargetDefines(const LangOptions &Opts,
5566 MacroBuilder &Builder) const override {
5567 SparcTargetInfo::getTargetDefines(Opts, Builder);
5568 Builder.defineMacro("__sparcv9");
5569 Builder.defineMacro("__arch64__");
5570 // Solaris doesn't need these variants, but the BSDs do.
5571 if (getTriple().getOS() != llvm::Triple::Solaris) {
5572 Builder.defineMacro("__sparc64__");
5573 Builder.defineMacro("__sparc_v9__");
5574 Builder.defineMacro("__sparcv9__");
5578 bool setCPU(const std::string &Name) override {
5579 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5581 .Case("ultrasparc", true)
5582 .Case("ultrasparc3", true)
5583 .Case("niagara", true)
5584 .Case("niagara2", true)
5585 .Case("niagara3", true)
5586 .Case("niagara4", true)
5589 // No need to store the CPU yet. There aren't any CPU-specific
5590 // macros to define.
5595 class SystemZTargetInfo : public TargetInfo {
5596 static const Builtin::Info BuiltinInfo[];
5597 static const char *const GCCRegNames[];
5599 bool HasTransactionalExecution;
5603 SystemZTargetInfo(const llvm::Triple &Triple)
5604 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) {
5605 IntMaxType = SignedLong;
5606 Int64Type = SignedLong;
5607 TLSSupported = true;
5608 IntWidth = IntAlign = 32;
5609 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5610 PointerWidth = PointerAlign = 64;
5611 LongDoubleWidth = 128;
5612 LongDoubleAlign = 64;
5613 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5614 DefaultAlignForAttributeAligned = 64;
5615 MinGlobalAlign = 16;
5616 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5617 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5619 void getTargetDefines(const LangOptions &Opts,
5620 MacroBuilder &Builder) const override {
5621 Builder.defineMacro("__s390__");
5622 Builder.defineMacro("__s390x__");
5623 Builder.defineMacro("__zarch__");
5624 Builder.defineMacro("__LONG_DOUBLE_128__");
5625 if (HasTransactionalExecution)
5626 Builder.defineMacro("__HTM__");
5628 void getTargetBuiltins(const Builtin::Info *&Records,
5629 unsigned &NumRecords) const override {
5630 Records = BuiltinInfo;
5631 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin;
5634 void getGCCRegNames(const char *const *&Names,
5635 unsigned &NumNames) const override;
5636 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5637 unsigned &NumAliases) const override {
5642 bool validateAsmConstraint(const char *&Name,
5643 TargetInfo::ConstraintInfo &info) const override;
5644 const char *getClobbers() const override {
5645 // FIXME: Is this really right?
5648 BuiltinVaListKind getBuiltinVaListKind() const override {
5649 return TargetInfo::SystemZBuiltinVaList;
5651 bool setCPU(const std::string &Name) override {
5653 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5656 .Case("zEC12", true)
5662 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5664 Features["transactional-execution"] = true;
5666 Features["transactional-execution"] = true;
5667 Features["vector"] = true;
5671 bool handleTargetFeatures(std::vector<std::string> &Features,
5672 DiagnosticsEngine &Diags) override {
5673 HasTransactionalExecution = false;
5674 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
5675 if (Features[i] == "+transactional-execution")
5676 HasTransactionalExecution = true;
5677 if (Features[i] == "+vector")
5680 // If we use the vector ABI, vector types are 64-bit aligned.
5682 MaxVectorAlign = 64;
5683 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
5684 "-v128:64-a:8:16-n32:64";
5689 bool hasFeature(StringRef Feature) const override {
5690 return llvm::StringSwitch<bool>(Feature)
5691 .Case("systemz", true)
5692 .Case("htm", HasTransactionalExecution)
5693 .Case("vx", HasVector)
5697 StringRef getABI() const override {
5703 bool useFloat128ManglingForLongDouble() const override {
5708 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
5709 #define BUILTIN(ID, TYPE, ATTRS) \
5710 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5711 #include "clang/Basic/BuiltinsSystemZ.def"
5714 const char *const SystemZTargetInfo::GCCRegNames[] = {
5715 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5716 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5717 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
5718 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
5721 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5722 unsigned &NumNames) const {
5723 Names = GCCRegNames;
5724 NumNames = llvm::array_lengthof(GCCRegNames);
5727 bool SystemZTargetInfo::
5728 validateAsmConstraint(const char *&Name,
5729 TargetInfo::ConstraintInfo &Info) const {
5734 case 'a': // Address register
5735 case 'd': // Data register (equivalent to 'r')
5736 case 'f': // Floating-point register
5737 Info.setAllowsRegister();
5740 case 'I': // Unsigned 8-bit constant
5741 case 'J': // Unsigned 12-bit constant
5742 case 'K': // Signed 16-bit constant
5743 case 'L': // Signed 20-bit displacement (on all targets we support)
5744 case 'M': // 0x7fffffff
5747 case 'Q': // Memory with base and unsigned 12-bit displacement
5748 case 'R': // Likewise, plus an index
5749 case 'S': // Memory with base and signed 20-bit displacement
5750 case 'T': // Likewise, plus an index
5751 Info.setAllowsMemory();
5756 class MSP430TargetInfo : public TargetInfo {
5757 static const char * const GCCRegNames[];
5759 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5761 TLSSupported = false;
5762 IntWidth = 16; IntAlign = 16;
5763 LongWidth = 32; LongLongWidth = 64;
5764 LongAlign = LongLongAlign = 16;
5765 PointerWidth = 16; PointerAlign = 16;
5767 SizeType = UnsignedInt;
5768 IntMaxType = SignedLongLong;
5769 IntPtrType = SignedInt;
5770 PtrDiffType = SignedInt;
5771 SigAtomicType = SignedLong;
5772 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5774 void getTargetDefines(const LangOptions &Opts,
5775 MacroBuilder &Builder) const override {
5776 Builder.defineMacro("MSP430");
5777 Builder.defineMacro("__MSP430__");
5778 // FIXME: defines for different 'flavours' of MCU
5780 void getTargetBuiltins(const Builtin::Info *&Records,
5781 unsigned &NumRecords) const override {
5782 // FIXME: Implement.
5786 bool hasFeature(StringRef Feature) const override {
5787 return Feature == "msp430";
5789 void getGCCRegNames(const char * const *&Names,
5790 unsigned &NumNames) const override;
5791 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5792 unsigned &NumAliases) const override {
5798 validateAsmConstraint(const char *&Name,
5799 TargetInfo::ConstraintInfo &info) const override {
5802 case 'K': // the constant 1
5803 case 'L': // constant -1^20 .. 1^19
5804 case 'M': // constant 1-4:
5807 // No target constraints for now.
5810 const char *getClobbers() const override {
5811 // FIXME: Is this really right?
5814 BuiltinVaListKind getBuiltinVaListKind() const override {
5816 return TargetInfo::CharPtrBuiltinVaList;
5820 const char * const MSP430TargetInfo::GCCRegNames[] = {
5821 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5822 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5825 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5826 unsigned &NumNames) const {
5827 Names = GCCRegNames;
5828 NumNames = llvm::array_lengthof(GCCRegNames);
5831 // LLVM and Clang cannot be used directly to output native binaries for
5832 // target, but is used to compile C code to llvm bitcode with correct
5833 // type and alignment information.
5835 // TCE uses the llvm bitcode as input and uses it for generating customized
5836 // target processor and program binary. TCE co-design environment is
5837 // publicly available in http://tce.cs.tut.fi
5839 static const unsigned TCEOpenCLAddrSpaceMap[] = {
5842 5, // opencl_constant
5843 // FIXME: generic has to be added to the target
5844 0, // opencl_generic
5850 class TCETargetInfo : public TargetInfo{
5852 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5853 TLSSupported = false;
5855 LongWidth = LongLongWidth = 32;
5858 LongAlign = LongLongAlign = 32;
5861 SizeType = UnsignedInt;
5862 IntMaxType = SignedLong;
5863 IntPtrType = SignedInt;
5864 PtrDiffType = SignedInt;
5869 LongDoubleWidth = 32;
5870 LongDoubleAlign = 32;
5871 FloatFormat = &llvm::APFloat::IEEEsingle;
5872 DoubleFormat = &llvm::APFloat::IEEEsingle;
5873 LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5874 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5875 "-f64:32-v64:32-v128:32-a:0:32-n32";
5876 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5877 UseAddrSpaceMapMangling = true;
5880 void getTargetDefines(const LangOptions &Opts,
5881 MacroBuilder &Builder) const override {
5882 DefineStd(Builder, "tce", Opts);
5883 Builder.defineMacro("__TCE__");
5884 Builder.defineMacro("__TCE_V1__");
5886 bool hasFeature(StringRef Feature) const override {
5887 return Feature == "tce";
5890 void getTargetBuiltins(const Builtin::Info *&Records,
5891 unsigned &NumRecords) const override {}
5892 const char *getClobbers() const override {
5895 BuiltinVaListKind getBuiltinVaListKind() const override {
5896 return TargetInfo::VoidPtrBuiltinVaList;
5898 void getGCCRegNames(const char * const *&Names,
5899 unsigned &NumNames) const override {}
5900 bool validateAsmConstraint(const char *&Name,
5901 TargetInfo::ConstraintInfo &info) const override{
5904 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5905 unsigned &NumAliases) const override {}
5908 class BPFTargetInfo : public TargetInfo {
5910 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5911 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5912 SizeType = UnsignedLong;
5913 PtrDiffType = SignedLong;
5914 IntPtrType = SignedLong;
5915 IntMaxType = SignedLong;
5916 Int64Type = SignedLong;
5918 if (Triple.getArch() == llvm::Triple::bpfeb) {
5920 DescriptionString = "E-m:e-p:64:64-i64:64-n32:64-S128";
5923 DescriptionString = "e-m:e-p:64:64-i64:64-n32:64-S128";
5925 MaxAtomicPromoteWidth = 64;
5926 MaxAtomicInlineWidth = 64;
5927 TLSSupported = false;
5929 void getTargetDefines(const LangOptions &Opts,
5930 MacroBuilder &Builder) const override {
5931 DefineStd(Builder, "bpf", Opts);
5932 Builder.defineMacro("__BPF__");
5934 bool hasFeature(StringRef Feature) const override {
5935 return Feature == "bpf";
5938 void getTargetBuiltins(const Builtin::Info *&Records,
5939 unsigned &NumRecords) const override {}
5940 const char *getClobbers() const override {
5943 BuiltinVaListKind getBuiltinVaListKind() const override {
5944 return TargetInfo::VoidPtrBuiltinVaList;
5946 void getGCCRegNames(const char * const *&Names,
5947 unsigned &NumNames) const override {
5951 bool validateAsmConstraint(const char *&Name,
5952 TargetInfo::ConstraintInfo &info) const override {
5955 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5956 unsigned &NumAliases) const override {
5962 class MipsTargetInfoBase : public TargetInfo {
5963 virtual void setDescriptionString() = 0;
5965 static const Builtin::Info BuiltinInfo[];
5972 HardFloat, SoftFloat
5984 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5985 const std::string &CPUStr)
5986 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
5987 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
5988 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
5989 TheCXXABI.set(TargetCXXABI::GenericMIPS);
5992 bool isNaN2008Default() const {
5993 return CPU == "mips32r6" || CPU == "mips64r6";
5996 bool isFP64Default() const {
5997 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
6000 bool isNan2008() const override {
6004 StringRef getABI() const override { return ABI; }
6005 bool setCPU(const std::string &Name) override {
6006 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
6007 getTriple().getArch() == llvm::Triple::mipsel;
6009 return llvm::StringSwitch<bool>(Name)
6010 .Case("mips1", IsMips32)
6011 .Case("mips2", IsMips32)
6012 .Case("mips3", true)
6013 .Case("mips4", true)
6014 .Case("mips5", true)
6015 .Case("mips32", IsMips32)
6016 .Case("mips32r2", IsMips32)
6017 .Case("mips32r3", IsMips32)
6018 .Case("mips32r5", IsMips32)
6019 .Case("mips32r6", IsMips32)
6020 .Case("mips64", true)
6021 .Case("mips64r2", true)
6022 .Case("mips64r3", true)
6023 .Case("mips64r5", true)
6024 .Case("mips64r6", true)
6025 .Case("octeon", true)
6028 const std::string& getCPU() const { return CPU; }
6029 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6030 if (CPU == "octeon")
6031 Features["mips64r2"] = Features["cnmips"] = true;
6033 Features[CPU] = true;
6036 void getTargetDefines(const LangOptions &Opts,
6037 MacroBuilder &Builder) const override {
6038 Builder.defineMacro("__mips__");
6039 Builder.defineMacro("_mips");
6041 Builder.defineMacro("mips");
6043 Builder.defineMacro("__REGISTER_PREFIX__", "");
6047 Builder.defineMacro("__mips_hard_float", Twine(1));
6050 Builder.defineMacro("__mips_soft_float", Twine(1));
6055 Builder.defineMacro("__mips_single_float", Twine(1));
6057 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
6058 Builder.defineMacro("_MIPS_FPSET",
6059 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
6062 Builder.defineMacro("__mips16", Twine(1));
6065 Builder.defineMacro("__mips_micromips", Twine(1));
6068 Builder.defineMacro("__mips_nan2008", Twine(1));
6074 Builder.defineMacro("__mips_dsp_rev", Twine(1));
6075 Builder.defineMacro("__mips_dsp", Twine(1));
6078 Builder.defineMacro("__mips_dsp_rev", Twine(2));
6079 Builder.defineMacro("__mips_dspr2", Twine(1));
6080 Builder.defineMacro("__mips_dsp", Twine(1));
6085 Builder.defineMacro("__mips_msa", Twine(1));
6087 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
6088 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
6089 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
6091 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
6092 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
6095 void getTargetBuiltins(const Builtin::Info *&Records,
6096 unsigned &NumRecords) const override {
6097 Records = BuiltinInfo;
6098 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
6100 bool hasFeature(StringRef Feature) const override {
6101 return llvm::StringSwitch<bool>(Feature)
6103 .Case("fp64", HasFP64)
6106 BuiltinVaListKind getBuiltinVaListKind() const override {
6107 return TargetInfo::VoidPtrBuiltinVaList;
6109 void getGCCRegNames(const char * const *&Names,
6110 unsigned &NumNames) const override {
6111 static const char *const GCCRegNames[] = {
6112 // CPU register names
6113 // Must match second column of GCCRegAliases
6114 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
6115 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
6116 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
6117 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
6118 // Floating point register names
6119 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
6120 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
6121 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
6122 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
6123 // Hi/lo and condition register names
6124 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
6125 "$fcc5","$fcc6","$fcc7",
6126 // MSA register names
6127 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
6128 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
6129 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
6130 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
6131 // MSA control register names
6132 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
6133 "$msarequest", "$msamap", "$msaunmap"
6135 Names = GCCRegNames;
6136 NumNames = llvm::array_lengthof(GCCRegNames);
6138 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6139 unsigned &NumAliases) const override = 0;
6140 bool validateAsmConstraint(const char *&Name,
6141 TargetInfo::ConstraintInfo &Info) const override {
6145 case 'r': // CPU registers.
6146 case 'd': // Equivalent to "r" unless generating MIPS16 code.
6147 case 'y': // Equivalent to "r", backward compatibility only.
6148 case 'f': // floating-point registers.
6149 case 'c': // $25 for indirect jumps
6150 case 'l': // lo register
6151 case 'x': // hilo register pair
6152 Info.setAllowsRegister();
6154 case 'I': // Signed 16-bit constant
6155 case 'J': // Integer 0
6156 case 'K': // Unsigned 16-bit constant
6157 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
6158 case 'M': // Constants not loadable via lui, addiu, or ori
6159 case 'N': // Constant -1 to -65535
6160 case 'O': // A signed 15-bit constant
6161 case 'P': // A constant between 1 go 65535
6163 case 'R': // An address that can be used in a non-macro load or store
6164 Info.setAllowsMemory();
6167 if (Name[1] == 'C') { // An address usable by ll, and sc.
6168 Info.setAllowsMemory();
6169 Name++; // Skip over 'Z'.
6176 std::string convertConstraint(const char *&Constraint) const override {
6178 switch (*Constraint) {
6179 case 'Z': // Two-character constraint; add "^" hint for later parsing.
6180 if (Constraint[1] == 'C') {
6181 R = std::string("^") + std::string(Constraint, 2);
6187 return TargetInfo::convertConstraint(Constraint);
6190 const char *getClobbers() const override {
6191 // In GCC, $1 is not widely used in generated code (it's used only in a few
6192 // specific situations), so there is no real need for users to add it to
6193 // the clobbers list if they want to use it in their inline assembly code.
6195 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
6196 // code generation, so using it in inline assembly without adding it to the
6197 // clobbers list can cause conflicts between the inline assembly code and
6198 // the surrounding generated code.
6200 // Another problem is that LLVM is allowed to choose $1 for inline assembly
6201 // operands, which will conflict with the ".set at" assembler option (which
6202 // we use only for inline assembly, in order to maintain compatibility with
6203 // GCC) and will also conflict with the user's usage of $1.
6205 // The easiest way to avoid these conflicts and keep $1 as an allocatable
6206 // register for generated code is to automatically clobber $1 for all inline
6209 // FIXME: We should automatically clobber $1 only for inline assembly code
6210 // which actually uses it. This would allow LLVM to use $1 for inline
6211 // assembly operands if the user's assembly code doesn't use it.
6215 bool handleTargetFeatures(std::vector<std::string> &Features,
6216 DiagnosticsEngine &Diags) override {
6218 IsMicromips = false;
6219 IsNan2008 = isNaN2008Default();
6220 IsSingleFloat = false;
6221 FloatABI = HardFloat;
6223 HasFP64 = isFP64Default();
6225 for (std::vector<std::string>::iterator it = Features.begin(),
6226 ie = Features.end(); it != ie; ++it) {
6227 if (*it == "+single-float")
6228 IsSingleFloat = true;
6229 else if (*it == "+soft-float")
6230 FloatABI = SoftFloat;
6231 else if (*it == "+mips16")
6233 else if (*it == "+micromips")
6235 else if (*it == "+dsp")
6236 DspRev = std::max(DspRev, DSP1);
6237 else if (*it == "+dspr2")
6238 DspRev = std::max(DspRev, DSP2);
6239 else if (*it == "+msa")
6241 else if (*it == "+fp64")
6243 else if (*it == "-fp64")
6245 else if (*it == "+nan2008")
6247 else if (*it == "-nan2008")
6251 setDescriptionString();
6256 int getEHDataRegisterNumber(unsigned RegNo) const override {
6257 if (RegNo == 0) return 4;
6258 if (RegNo == 1) return 5;
6262 bool isCLZForZeroUndef() const override { return false; }
6265 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
6266 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6267 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6269 #include "clang/Basic/BuiltinsMips.def"
6272 class Mips32TargetInfoBase : public MipsTargetInfoBase {
6274 Mips32TargetInfoBase(const llvm::Triple &Triple)
6275 : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
6276 SizeType = UnsignedInt;
6277 PtrDiffType = SignedInt;
6278 Int64Type = SignedLongLong;
6279 IntMaxType = Int64Type;
6280 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
6282 bool setABI(const std::string &Name) override {
6283 if (Name == "o32" || Name == "eabi") {
6289 void getTargetDefines(const LangOptions &Opts,
6290 MacroBuilder &Builder) const override {
6291 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6293 Builder.defineMacro("__mips", "32");
6294 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
6296 const std::string& CPUStr = getCPU();
6297 if (CPUStr == "mips32")
6298 Builder.defineMacro("__mips_isa_rev", "1");
6299 else if (CPUStr == "mips32r2")
6300 Builder.defineMacro("__mips_isa_rev", "2");
6301 else if (CPUStr == "mips32r3")
6302 Builder.defineMacro("__mips_isa_rev", "3");
6303 else if (CPUStr == "mips32r5")
6304 Builder.defineMacro("__mips_isa_rev", "5");
6305 else if (CPUStr == "mips32r6")
6306 Builder.defineMacro("__mips_isa_rev", "6");
6309 Builder.defineMacro("__mips_o32");
6310 Builder.defineMacro("_ABIO32", "1");
6311 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
6313 else if (ABI == "eabi")
6314 Builder.defineMacro("__mips_eabi");
6316 llvm_unreachable("Invalid ABI for Mips32.");
6318 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6319 unsigned &NumAliases) const override {
6320 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6330 { { "t2" }, "$10" },
6331 { { "t3" }, "$11" },
6332 { { "t4" }, "$12" },
6333 { { "t5" }, "$13" },
6334 { { "t6" }, "$14" },
6335 { { "t7" }, "$15" },
6336 { { "s0" }, "$16" },
6337 { { "s1" }, "$17" },
6338 { { "s2" }, "$18" },
6339 { { "s3" }, "$19" },
6340 { { "s4" }, "$20" },
6341 { { "s5" }, "$21" },
6342 { { "s6" }, "$22" },
6343 { { "s7" }, "$23" },
6344 { { "t8" }, "$24" },
6345 { { "t9" }, "$25" },
6346 { { "k0" }, "$26" },
6347 { { "k1" }, "$27" },
6348 { { "gp" }, "$28" },
6349 { { "sp","$sp" }, "$29" },
6350 { { "fp","$fp" }, "$30" },
6353 Aliases = GCCRegAliases;
6354 NumAliases = llvm::array_lengthof(GCCRegAliases);
6358 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
6359 void setDescriptionString() override {
6360 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6364 Mips32EBTargetInfo(const llvm::Triple &Triple)
6365 : Mips32TargetInfoBase(Triple) {
6367 void getTargetDefines(const LangOptions &Opts,
6368 MacroBuilder &Builder) const override {
6369 DefineStd(Builder, "MIPSEB", Opts);
6370 Builder.defineMacro("_MIPSEB");
6371 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6375 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
6376 void setDescriptionString() override {
6377 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6381 Mips32ELTargetInfo(const llvm::Triple &Triple)
6382 : Mips32TargetInfoBase(Triple) {
6385 void getTargetDefines(const LangOptions &Opts,
6386 MacroBuilder &Builder) const override {
6387 DefineStd(Builder, "MIPSEL", Opts);
6388 Builder.defineMacro("_MIPSEL");
6389 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6393 class Mips64TargetInfoBase : public MipsTargetInfoBase {
6395 Mips64TargetInfoBase(const llvm::Triple &Triple)
6396 : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6397 LongDoubleWidth = LongDoubleAlign = 128;
6398 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6399 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6400 LongDoubleWidth = LongDoubleAlign = 64;
6401 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6404 SuitableAlign = 128;
6405 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6408 void setN64ABITypes() {
6409 LongWidth = LongAlign = 64;
6410 PointerWidth = PointerAlign = 64;
6411 SizeType = UnsignedLong;
6412 PtrDiffType = SignedLong;
6413 Int64Type = SignedLong;
6414 IntMaxType = Int64Type;
6417 void setN32ABITypes() {
6418 LongWidth = LongAlign = 32;
6419 PointerWidth = PointerAlign = 32;
6420 SizeType = UnsignedInt;
6421 PtrDiffType = SignedInt;
6422 Int64Type = SignedLongLong;
6423 IntMaxType = Int64Type;
6426 bool setABI(const std::string &Name) override {
6427 if (Name == "n32") {
6432 if (Name == "n64") {
6440 void getTargetDefines(const LangOptions &Opts,
6441 MacroBuilder &Builder) const override {
6442 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6444 Builder.defineMacro("__mips", "64");
6445 Builder.defineMacro("__mips64");
6446 Builder.defineMacro("__mips64__");
6447 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6449 const std::string& CPUStr = getCPU();
6450 if (CPUStr == "mips64")
6451 Builder.defineMacro("__mips_isa_rev", "1");
6452 else if (CPUStr == "mips64r2")
6453 Builder.defineMacro("__mips_isa_rev", "2");
6454 else if (CPUStr == "mips64r3")
6455 Builder.defineMacro("__mips_isa_rev", "3");
6456 else if (CPUStr == "mips64r5")
6457 Builder.defineMacro("__mips_isa_rev", "5");
6458 else if (CPUStr == "mips64r6")
6459 Builder.defineMacro("__mips_isa_rev", "6");
6462 Builder.defineMacro("__mips_n32");
6463 Builder.defineMacro("_ABIN32", "2");
6464 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6466 else if (ABI == "n64") {
6467 Builder.defineMacro("__mips_n64");
6468 Builder.defineMacro("_ABI64", "3");
6469 Builder.defineMacro("_MIPS_SIM", "_ABI64");
6472 llvm_unreachable("Invalid ABI for Mips64.");
6474 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6475 unsigned &NumAliases) const override {
6476 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6486 { { "a6" }, "$10" },
6487 { { "a7" }, "$11" },
6488 { { "t0" }, "$12" },
6489 { { "t1" }, "$13" },
6490 { { "t2" }, "$14" },
6491 { { "t3" }, "$15" },
6492 { { "s0" }, "$16" },
6493 { { "s1" }, "$17" },
6494 { { "s2" }, "$18" },
6495 { { "s3" }, "$19" },
6496 { { "s4" }, "$20" },
6497 { { "s5" }, "$21" },
6498 { { "s6" }, "$22" },
6499 { { "s7" }, "$23" },
6500 { { "t8" }, "$24" },
6501 { { "t9" }, "$25" },
6502 { { "k0" }, "$26" },
6503 { { "k1" }, "$27" },
6504 { { "gp" }, "$28" },
6505 { { "sp","$sp" }, "$29" },
6506 { { "fp","$fp" }, "$30" },
6509 Aliases = GCCRegAliases;
6510 NumAliases = llvm::array_lengthof(GCCRegAliases);
6513 bool hasInt128Type() const override { return true; }
6516 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
6517 void setDescriptionString() override {
6519 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6521 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6526 Mips64EBTargetInfo(const llvm::Triple &Triple)
6527 : Mips64TargetInfoBase(Triple) {}
6528 void getTargetDefines(const LangOptions &Opts,
6529 MacroBuilder &Builder) const override {
6530 DefineStd(Builder, "MIPSEB", Opts);
6531 Builder.defineMacro("_MIPSEB");
6532 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6536 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
6537 void setDescriptionString() override {
6539 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6541 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6544 Mips64ELTargetInfo(const llvm::Triple &Triple)
6545 : Mips64TargetInfoBase(Triple) {
6546 // Default ABI is n64.
6549 void getTargetDefines(const LangOptions &Opts,
6550 MacroBuilder &Builder) const override {
6551 DefineStd(Builder, "MIPSEL", Opts);
6552 Builder.defineMacro("_MIPSEL");
6553 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6557 class PNaClTargetInfo : public TargetInfo {
6559 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6561 this->UserLabelPrefix = "";
6562 this->LongAlign = 32;
6563 this->LongWidth = 32;
6564 this->PointerAlign = 32;
6565 this->PointerWidth = 32;
6566 this->IntMaxType = TargetInfo::SignedLongLong;
6567 this->Int64Type = TargetInfo::SignedLongLong;
6568 this->DoubleAlign = 64;
6569 this->LongDoubleWidth = 64;
6570 this->LongDoubleAlign = 64;
6571 this->SizeType = TargetInfo::UnsignedInt;
6572 this->PtrDiffType = TargetInfo::SignedInt;
6573 this->IntPtrType = TargetInfo::SignedInt;
6574 this->RegParmMax = 0; // Disallow regparm
6577 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6579 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6580 Builder.defineMacro("__le32__");
6581 Builder.defineMacro("__pnacl__");
6583 void getTargetDefines(const LangOptions &Opts,
6584 MacroBuilder &Builder) const override {
6585 getArchDefines(Opts, Builder);
6587 bool hasFeature(StringRef Feature) const override {
6588 return Feature == "pnacl";
6590 void getTargetBuiltins(const Builtin::Info *&Records,
6591 unsigned &NumRecords) const override {
6593 BuiltinVaListKind getBuiltinVaListKind() const override {
6594 return TargetInfo::PNaClABIBuiltinVaList;
6596 void getGCCRegNames(const char * const *&Names,
6597 unsigned &NumNames) const override;
6598 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6599 unsigned &NumAliases) const override;
6600 bool validateAsmConstraint(const char *&Name,
6601 TargetInfo::ConstraintInfo &Info) const override {
6605 const char *getClobbers() const override {
6610 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6611 unsigned &NumNames) const {
6616 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6617 unsigned &NumAliases) const {
6622 class Le64TargetInfo : public TargetInfo {
6623 static const Builtin::Info BuiltinInfo[];
6626 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6628 NoAsmVariants = true;
6629 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6630 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6632 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
6635 void getTargetDefines(const LangOptions &Opts,
6636 MacroBuilder &Builder) const override {
6637 DefineStd(Builder, "unix", Opts);
6638 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6639 Builder.defineMacro("__ELF__");
6641 void getTargetBuiltins(const Builtin::Info *&Records,
6642 unsigned &NumRecords) const override {
6643 Records = BuiltinInfo;
6644 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
6646 BuiltinVaListKind getBuiltinVaListKind() const override {
6647 return TargetInfo::PNaClABIBuiltinVaList;
6649 const char *getClobbers() const override { return ""; }
6650 void getGCCRegNames(const char *const *&Names,
6651 unsigned &NumNames) const override {
6655 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6656 unsigned &NumAliases) const override {
6660 bool validateAsmConstraint(const char *&Name,
6661 TargetInfo::ConstraintInfo &Info) const override {
6665 bool hasProtectedVisibility() const override { return false; }
6667 } // end anonymous namespace.
6669 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
6670 #define BUILTIN(ID, TYPE, ATTRS) \
6671 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6672 #include "clang/Basic/BuiltinsLe64.def"
6676 static const unsigned SPIRAddrSpaceMap[] = {
6679 2, // opencl_constant
6680 4, // opencl_generic
6685 class SPIRTargetInfo : public TargetInfo {
6687 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6688 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6689 "SPIR target must use unknown OS");
6690 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6691 "SPIR target must use unknown environment type");
6693 TLSSupported = false;
6694 LongWidth = LongAlign = 64;
6695 AddrSpaceMap = &SPIRAddrSpaceMap;
6696 UseAddrSpaceMapMangling = true;
6697 // Define available target features
6698 // These must be defined in sorted order!
6699 NoAsmVariants = true;
6701 void getTargetDefines(const LangOptions &Opts,
6702 MacroBuilder &Builder) const override {
6703 DefineStd(Builder, "SPIR", Opts);
6705 bool hasFeature(StringRef Feature) const override {
6706 return Feature == "spir";
6709 void getTargetBuiltins(const Builtin::Info *&Records,
6710 unsigned &NumRecords) const override {}
6711 const char *getClobbers() const override {
6714 void getGCCRegNames(const char * const *&Names,
6715 unsigned &NumNames) const override {}
6717 validateAsmConstraint(const char *&Name,
6718 TargetInfo::ConstraintInfo &info) const override {
6721 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6722 unsigned &NumAliases) const override {}
6723 BuiltinVaListKind getBuiltinVaListKind() const override {
6724 return TargetInfo::VoidPtrBuiltinVaList;
6727 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6728 return (CC == CC_SpirFunction ||
6729 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning;
6732 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
6733 return CC_SpirFunction;
6738 class SPIR32TargetInfo : public SPIRTargetInfo {
6740 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6741 PointerWidth = PointerAlign = 32;
6742 SizeType = TargetInfo::UnsignedInt;
6743 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6745 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6746 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6748 void getTargetDefines(const LangOptions &Opts,
6749 MacroBuilder &Builder) const override {
6750 DefineStd(Builder, "SPIR32", Opts);
6754 class SPIR64TargetInfo : public SPIRTargetInfo {
6756 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6757 PointerWidth = PointerAlign = 64;
6758 SizeType = TargetInfo::UnsignedLong;
6759 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6760 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6761 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6763 void getTargetDefines(const LangOptions &Opts,
6764 MacroBuilder &Builder) const override {
6765 DefineStd(Builder, "SPIR64", Opts);
6769 class XCoreTargetInfo : public TargetInfo {
6770 static const Builtin::Info BuiltinInfo[];
6772 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6774 NoAsmVariants = true;
6777 DoubleAlign = LongDoubleAlign = 32;
6778 SizeType = UnsignedInt;
6779 PtrDiffType = SignedInt;
6780 IntPtrType = SignedInt;
6781 WCharType = UnsignedChar;
6782 WIntType = UnsignedInt;
6783 UseZeroLengthBitfieldAlignment = true;
6784 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6785 "-f64:32-a:0:32-n32";
6787 void getTargetDefines(const LangOptions &Opts,
6788 MacroBuilder &Builder) const override {
6789 Builder.defineMacro("__XS1B__");
6791 void getTargetBuiltins(const Builtin::Info *&Records,
6792 unsigned &NumRecords) const override {
6793 Records = BuiltinInfo;
6794 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
6796 BuiltinVaListKind getBuiltinVaListKind() const override {
6797 return TargetInfo::VoidPtrBuiltinVaList;
6799 const char *getClobbers() const override {
6802 void getGCCRegNames(const char * const *&Names,
6803 unsigned &NumNames) const override {
6804 static const char * const GCCRegNames[] = {
6805 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6806 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
6808 Names = GCCRegNames;
6809 NumNames = llvm::array_lengthof(GCCRegNames);
6811 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6812 unsigned &NumAliases) const override {
6816 bool validateAsmConstraint(const char *&Name,
6817 TargetInfo::ConstraintInfo &Info) const override {
6820 int getEHDataRegisterNumber(unsigned RegNo) const override {
6821 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6822 return (RegNo < 2)? RegNo : -1;
6826 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6827 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6828 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6830 #include "clang/Basic/BuiltinsXCore.def"
6832 } // end anonymous namespace.
6835 // x86_32 Android target
6836 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
6838 AndroidX86_32TargetInfo(const llvm::Triple &Triple)
6839 : LinuxTargetInfo<X86_32TargetInfo>(Triple) {
6841 LongDoubleWidth = 64;
6842 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6845 } // end anonymous namespace
6848 // x86_64 Android target
6849 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
6851 AndroidX86_64TargetInfo(const llvm::Triple &Triple)
6852 : LinuxTargetInfo<X86_64TargetInfo>(Triple) {
6853 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6856 } // end anonymous namespace
6859 //===----------------------------------------------------------------------===//
6861 //===----------------------------------------------------------------------===//
6863 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6864 llvm::Triple::OSType os = Triple.getOS();
6866 switch (Triple.getArch()) {
6870 case llvm::Triple::xcore:
6871 return new XCoreTargetInfo(Triple);
6873 case llvm::Triple::hexagon:
6874 return new HexagonTargetInfo(Triple);
6876 case llvm::Triple::aarch64:
6877 if (Triple.isOSDarwin())
6878 return new DarwinAArch64TargetInfo(Triple);
6881 case llvm::Triple::FreeBSD:
6882 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
6883 case llvm::Triple::Linux:
6884 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6885 case llvm::Triple::NetBSD:
6886 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6888 return new AArch64leTargetInfo(Triple);
6891 case llvm::Triple::aarch64_be:
6893 case llvm::Triple::FreeBSD:
6894 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
6895 case llvm::Triple::Linux:
6896 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6897 case llvm::Triple::NetBSD:
6898 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6900 return new AArch64beTargetInfo(Triple);
6903 case llvm::Triple::arm:
6904 case llvm::Triple::thumb:
6905 if (Triple.isOSBinFormatMachO())
6906 return new DarwinARMTargetInfo(Triple);
6909 case llvm::Triple::Linux:
6910 return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6911 case llvm::Triple::FreeBSD:
6912 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6913 case llvm::Triple::NetBSD:
6914 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6915 case llvm::Triple::OpenBSD:
6916 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6917 case llvm::Triple::Bitrig:
6918 return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6919 case llvm::Triple::RTEMS:
6920 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6921 case llvm::Triple::NaCl:
6922 return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6923 case llvm::Triple::Win32:
6924 switch (Triple.getEnvironment()) {
6926 return new ARMleTargetInfo(Triple);
6927 case llvm::Triple::Itanium:
6928 return new ItaniumWindowsARMleTargetInfo(Triple);
6929 case llvm::Triple::MSVC:
6930 return new MicrosoftARMleTargetInfo(Triple);
6933 return new ARMleTargetInfo(Triple);
6936 case llvm::Triple::armeb:
6937 case llvm::Triple::thumbeb:
6938 if (Triple.isOSDarwin())
6939 return new DarwinARMTargetInfo(Triple);
6942 case llvm::Triple::Linux:
6943 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6944 case llvm::Triple::FreeBSD:
6945 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6946 case llvm::Triple::NetBSD:
6947 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6948 case llvm::Triple::OpenBSD:
6949 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6950 case llvm::Triple::Bitrig:
6951 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6952 case llvm::Triple::RTEMS:
6953 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6954 case llvm::Triple::NaCl:
6955 return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6957 return new ARMbeTargetInfo(Triple);
6960 case llvm::Triple::bpfeb:
6961 case llvm::Triple::bpfel:
6962 return new BPFTargetInfo(Triple);
6964 case llvm::Triple::msp430:
6965 return new MSP430TargetInfo(Triple);
6967 case llvm::Triple::mips:
6969 case llvm::Triple::Linux:
6970 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6971 case llvm::Triple::RTEMS:
6972 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6973 case llvm::Triple::FreeBSD:
6974 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6975 case llvm::Triple::NetBSD:
6976 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6978 return new Mips32EBTargetInfo(Triple);
6981 case llvm::Triple::mipsel:
6983 case llvm::Triple::Linux:
6984 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6985 case llvm::Triple::RTEMS:
6986 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
6987 case llvm::Triple::FreeBSD:
6988 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6989 case llvm::Triple::NetBSD:
6990 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6991 case llvm::Triple::NaCl:
6992 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
6994 return new Mips32ELTargetInfo(Triple);
6997 case llvm::Triple::mips64:
6999 case llvm::Triple::Linux:
7000 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
7001 case llvm::Triple::RTEMS:
7002 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
7003 case llvm::Triple::FreeBSD:
7004 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7005 case llvm::Triple::NetBSD:
7006 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7007 case llvm::Triple::OpenBSD:
7008 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7010 return new Mips64EBTargetInfo(Triple);
7013 case llvm::Triple::mips64el:
7015 case llvm::Triple::Linux:
7016 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
7017 case llvm::Triple::RTEMS:
7018 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
7019 case llvm::Triple::FreeBSD:
7020 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7021 case llvm::Triple::NetBSD:
7022 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7023 case llvm::Triple::OpenBSD:
7024 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7026 return new Mips64ELTargetInfo(Triple);
7029 case llvm::Triple::le32:
7031 case llvm::Triple::NaCl:
7032 return new NaClTargetInfo<PNaClTargetInfo>(Triple);
7037 case llvm::Triple::le64:
7038 return new Le64TargetInfo(Triple);
7040 case llvm::Triple::ppc:
7041 if (Triple.isOSDarwin())
7042 return new DarwinPPC32TargetInfo(Triple);
7044 case llvm::Triple::Linux:
7045 return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
7046 case llvm::Triple::FreeBSD:
7047 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
7048 case llvm::Triple::NetBSD:
7049 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
7050 case llvm::Triple::OpenBSD:
7051 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
7052 case llvm::Triple::RTEMS:
7053 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
7055 return new PPC32TargetInfo(Triple);
7058 case llvm::Triple::ppc64:
7059 if (Triple.isOSDarwin())
7060 return new DarwinPPC64TargetInfo(Triple);
7062 case llvm::Triple::Linux:
7063 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7064 case llvm::Triple::Lv2:
7065 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
7066 case llvm::Triple::FreeBSD:
7067 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
7068 case llvm::Triple::NetBSD:
7069 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7071 return new PPC64TargetInfo(Triple);
7074 case llvm::Triple::ppc64le:
7076 case llvm::Triple::Linux:
7077 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7078 case llvm::Triple::NetBSD:
7079 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7081 return new PPC64TargetInfo(Triple);
7084 case llvm::Triple::nvptx:
7085 return new NVPTX32TargetInfo(Triple);
7086 case llvm::Triple::nvptx64:
7087 return new NVPTX64TargetInfo(Triple);
7089 case llvm::Triple::amdgcn:
7090 case llvm::Triple::r600:
7091 return new AMDGPUTargetInfo(Triple);
7093 case llvm::Triple::sparc:
7095 case llvm::Triple::Linux:
7096 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
7097 case llvm::Triple::Solaris:
7098 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple);
7099 case llvm::Triple::NetBSD:
7100 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
7101 case llvm::Triple::OpenBSD:
7102 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
7103 case llvm::Triple::RTEMS:
7104 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
7106 return new SparcV8TargetInfo(Triple);
7109 // The 'sparcel' architecture copies all the above cases except for Solaris.
7110 case llvm::Triple::sparcel:
7112 case llvm::Triple::Linux:
7113 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple);
7114 case llvm::Triple::NetBSD:
7115 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7116 case llvm::Triple::OpenBSD:
7117 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7118 case llvm::Triple::RTEMS:
7119 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple);
7121 return new SparcV8elTargetInfo(Triple);
7124 case llvm::Triple::sparcv9:
7126 case llvm::Triple::Linux:
7127 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
7128 case llvm::Triple::Solaris:
7129 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
7130 case llvm::Triple::NetBSD:
7131 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
7132 case llvm::Triple::OpenBSD:
7133 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
7134 case llvm::Triple::FreeBSD:
7135 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
7137 return new SparcV9TargetInfo(Triple);
7140 case llvm::Triple::systemz:
7142 case llvm::Triple::Linux:
7143 return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
7145 return new SystemZTargetInfo(Triple);
7148 case llvm::Triple::tce:
7149 return new TCETargetInfo(Triple);
7151 case llvm::Triple::x86:
7152 if (Triple.isOSDarwin())
7153 return new DarwinI386TargetInfo(Triple);
7156 case llvm::Triple::CloudABI:
7157 return new CloudABITargetInfo<X86_32TargetInfo>(Triple);
7158 case llvm::Triple::Linux: {
7159 switch (Triple.getEnvironment()) {
7161 return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
7162 case llvm::Triple::Android:
7163 return new AndroidX86_32TargetInfo(Triple);
7166 case llvm::Triple::DragonFly:
7167 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
7168 case llvm::Triple::NetBSD:
7169 return new NetBSDI386TargetInfo(Triple);
7170 case llvm::Triple::OpenBSD:
7171 return new OpenBSDI386TargetInfo(Triple);
7172 case llvm::Triple::Bitrig:
7173 return new BitrigI386TargetInfo(Triple);
7174 case llvm::Triple::FreeBSD:
7175 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7176 case llvm::Triple::KFreeBSD:
7177 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7178 case llvm::Triple::Minix:
7179 return new MinixTargetInfo<X86_32TargetInfo>(Triple);
7180 case llvm::Triple::Solaris:
7181 return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
7182 case llvm::Triple::Win32: {
7183 switch (Triple.getEnvironment()) {
7185 return new X86_32TargetInfo(Triple);
7186 case llvm::Triple::Cygnus:
7187 return new CygwinX86_32TargetInfo(Triple);
7188 case llvm::Triple::GNU:
7189 return new MinGWX86_32TargetInfo(Triple);
7190 case llvm::Triple::Itanium:
7191 case llvm::Triple::MSVC:
7192 return new MicrosoftX86_32TargetInfo(Triple);
7195 case llvm::Triple::Haiku:
7196 return new HaikuX86_32TargetInfo(Triple);
7197 case llvm::Triple::RTEMS:
7198 return new RTEMSX86_32TargetInfo(Triple);
7199 case llvm::Triple::NaCl:
7200 return new NaClTargetInfo<X86_32TargetInfo>(Triple);
7202 return new X86_32TargetInfo(Triple);
7205 case llvm::Triple::x86_64:
7206 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
7207 return new DarwinX86_64TargetInfo(Triple);
7210 case llvm::Triple::CloudABI:
7211 return new CloudABITargetInfo<X86_64TargetInfo>(Triple);
7212 case llvm::Triple::Linux: {
7213 switch (Triple.getEnvironment()) {
7215 return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
7216 case llvm::Triple::Android:
7217 return new AndroidX86_64TargetInfo(Triple);
7220 case llvm::Triple::DragonFly:
7221 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
7222 case llvm::Triple::NetBSD:
7223 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
7224 case llvm::Triple::OpenBSD:
7225 return new OpenBSDX86_64TargetInfo(Triple);
7226 case llvm::Triple::Bitrig:
7227 return new BitrigX86_64TargetInfo(Triple);
7228 case llvm::Triple::FreeBSD:
7229 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7230 case llvm::Triple::KFreeBSD:
7231 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7232 case llvm::Triple::Solaris:
7233 return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
7234 case llvm::Triple::Win32: {
7235 switch (Triple.getEnvironment()) {
7237 return new X86_64TargetInfo(Triple);
7238 case llvm::Triple::GNU:
7239 return new MinGWX86_64TargetInfo(Triple);
7240 case llvm::Triple::MSVC:
7241 return new MicrosoftX86_64TargetInfo(Triple);
7244 case llvm::Triple::NaCl:
7245 return new NaClTargetInfo<X86_64TargetInfo>(Triple);
7246 case llvm::Triple::PS4:
7247 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple);
7249 return new X86_64TargetInfo(Triple);
7252 case llvm::Triple::spir: {
7253 if (Triple.getOS() != llvm::Triple::UnknownOS ||
7254 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7256 return new SPIR32TargetInfo(Triple);
7258 case llvm::Triple::spir64: {
7259 if (Triple.getOS() != llvm::Triple::UnknownOS ||
7260 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7262 return new SPIR64TargetInfo(Triple);
7267 /// CreateTargetInfo - Return the target info object for the specified target
7270 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
7271 const std::shared_ptr<TargetOptions> &Opts) {
7272 llvm::Triple Triple(Opts->Triple);
7274 // Construct the target
7275 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
7277 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
7280 Target->TargetOpts = Opts;
7282 // Set the target CPU if specified.
7283 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
7284 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
7288 // Set the target ABI if specified.
7289 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
7290 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
7294 // Set the fp math unit.
7295 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
7296 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
7300 // Compute the default target features, we need the target to handle this
7301 // because features may have dependencies on one another.
7302 llvm::StringMap<bool> Features;
7303 Target->getDefaultFeatures(Features);
7305 // Apply the user specified deltas.
7306 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
7308 const char *Name = Opts->FeaturesAsWritten[I].c_str();
7309 // Apply the feature via the target.
7310 bool Enabled = Name[0] == '+';
7311 Target->setFeatureEnabled(Features, Name + 1, Enabled);
7314 // Add the features to the compile options.
7316 // FIXME: If we are completely confident that we have the right set, we only
7317 // need to pass the minuses.
7318 Opts->Features.clear();
7319 for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
7320 ie = Features.end(); it != ie; ++it)
7321 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
7322 if (!Target->handleTargetFeatures(Opts->Features, Diags))
7325 return Target.release();