1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/MC/MCSectionMachO.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/TargetParser.h"
33 using namespace clang;
35 //===----------------------------------------------------------------------===//
36 // Common code shared among targets.
37 //===----------------------------------------------------------------------===//
39 /// DefineStd - Define a macro name and standard variants. For example if
40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
43 const LangOptions &Opts) {
44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
47 // in the user's namespace.
49 Builder.defineMacro(MacroName);
52 Builder.defineMacro("__" + MacroName);
55 Builder.defineMacro("__" + MacroName + "__");
58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
60 Builder.defineMacro("__" + CPUName);
61 Builder.defineMacro("__" + CPUName + "__");
63 Builder.defineMacro("__tune_" + CPUName + "__");
66 //===----------------------------------------------------------------------===//
67 // Defines specific to certain operating systems.
68 //===----------------------------------------------------------------------===//
71 template<typename TgtInfo>
72 class OSTargetInfo : public TgtInfo {
74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
75 MacroBuilder &Builder) const=0;
77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
78 void getTargetDefines(const LangOptions &Opts,
79 MacroBuilder &Builder) const override {
80 TgtInfo::getTargetDefines(Opts, Builder);
81 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
85 } // end anonymous namespace
88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
89 const llvm::Triple &Triple,
90 StringRef &PlatformName,
91 VersionTuple &PlatformMinVersion) {
92 Builder.defineMacro("__APPLE_CC__", "6000");
93 Builder.defineMacro("__APPLE__");
94 Builder.defineMacro("OBJC_NEW_PROPERTIES");
95 // AddressSanitizer doesn't play well with source fortification, which is on
96 // by default on Darwin.
97 if (Opts.Sanitize.has(SanitizerKind::Address))
98 Builder.defineMacro("_FORTIFY_SOURCE", "0");
100 if (!Opts.ObjCAutoRefCount) {
101 // __weak is always defined, for use in blocks and with objc pointers.
102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
104 // Darwin defines __strong even in C mode (just to nothing).
105 if (Opts.getGC() != LangOptions::NonGC)
106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
108 Builder.defineMacro("__strong", "");
110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even
111 // allow this in C, since one might have block pointers in structs that
112 // are used in pure C code and in Objective-C ARC.
113 Builder.defineMacro("__unsafe_unretained", "");
117 Builder.defineMacro("__STATIC__");
119 Builder.defineMacro("__DYNAMIC__");
121 if (Opts.POSIXThreads)
122 Builder.defineMacro("_REENTRANT");
124 // Get the platform type and version number from the triple.
125 unsigned Maj, Min, Rev;
126 if (Triple.isMacOSX()) {
127 Triple.getMacOSXVersion(Maj, Min, Rev);
128 PlatformName = "macosx";
130 Triple.getOSVersion(Maj, Min, Rev);
131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
134 // If -target arch-pc-win32-macho option specified, we're
135 // generating code for Win32 ABI. No need to emit
136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
137 if (PlatformName == "win32") {
138 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
142 // Set the appropriate OS version define.
143 if (Triple.isiOS()) {
144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
147 Str[1] = '0' + (Min / 10);
148 Str[2] = '0' + (Min % 10);
149 Str[3] = '0' + (Rev / 10);
150 Str[4] = '0' + (Rev % 10);
152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
154 } else if (Triple.isMacOSX()) {
155 // Note that the Driver allows versions which aren't representable in the
156 // define (because we only get a single digit for the minor and micro
157 // revision numbers). So, we limit them to the maximum representable
159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
161 if (Maj < 10 || (Maj == 10 && Min < 10)) {
162 Str[0] = '0' + (Maj / 10);
163 Str[1] = '0' + (Maj % 10);
164 Str[2] = '0' + std::min(Min, 9U);
165 Str[3] = '0' + std::min(Rev, 9U);
168 // Handle versions > 10.9.
169 Str[0] = '0' + (Maj / 10);
170 Str[1] = '0' + (Maj % 10);
171 Str[2] = '0' + (Min / 10);
172 Str[3] = '0' + (Min % 10);
173 Str[4] = '0' + (Rev / 10);
174 Str[5] = '0' + (Rev % 10);
177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
180 // Tell users about the kernel if there is one.
181 if (Triple.isOSDarwin())
182 Builder.defineMacro("__MACH__");
184 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
189 template <typename Target>
190 class CloudABITargetInfo : public OSTargetInfo<Target> {
192 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
193 MacroBuilder &Builder) const override {
194 Builder.defineMacro("__CloudABI__");
195 Builder.defineMacro("__ELF__");
197 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
198 Builder.defineMacro("__STDC_ISO_10646__", "201206L");
199 Builder.defineMacro("__STDC_UTF_16__");
200 Builder.defineMacro("__STDC_UTF_32__");
204 CloudABITargetInfo(const llvm::Triple &Triple)
205 : OSTargetInfo<Target>(Triple) {
206 this->UserLabelPrefix = "";
210 template<typename Target>
211 class DarwinTargetInfo : public OSTargetInfo<Target> {
213 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
214 MacroBuilder &Builder) const override {
215 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
216 this->PlatformMinVersion);
220 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
221 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
222 this->MCountName = "\01mcount";
225 std::string isValidSectionSpecifier(StringRef SR) const override {
226 // Let MCSectionMachO validate this.
227 StringRef Segment, Section;
228 unsigned TAA, StubSize;
230 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
231 TAA, HasTAA, StubSize);
234 const char *getStaticInitSectionSpecifier() const override {
235 // FIXME: We should return 0 when building kexts.
236 return "__TEXT,__StaticInit,regular,pure_instructions";
239 /// Darwin does not support protected visibility. Darwin's "default"
240 /// is very similar to ELF's "protected"; Darwin requires a "weak"
241 /// attribute on declarations that can be dynamically replaced.
242 bool hasProtectedVisibility() const override {
248 // DragonFlyBSD Target
249 template<typename Target>
250 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
252 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
253 MacroBuilder &Builder) const override {
254 // DragonFly defines; list based off of gcc output
255 Builder.defineMacro("__DragonFly__");
256 Builder.defineMacro("__DragonFly_cc_version", "100001");
257 Builder.defineMacro("__ELF__");
258 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
259 Builder.defineMacro("__tune_i386__");
260 DefineStd(Builder, "unix", Opts);
263 DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
264 : OSTargetInfo<Target>(Triple) {
265 this->UserLabelPrefix = "";
267 switch (Triple.getArch()) {
269 case llvm::Triple::x86:
270 case llvm::Triple::x86_64:
271 this->MCountName = ".mcount";
278 template<typename Target>
279 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
281 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
282 MacroBuilder &Builder) const override {
283 // FreeBSD defines; list based off of gcc output
285 unsigned Release = Triple.getOSMajorVersion();
289 Builder.defineMacro("__FreeBSD__", Twine(Release));
290 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
291 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
292 DefineStd(Builder, "unix", Opts);
293 Builder.defineMacro("__ELF__");
295 // On FreeBSD, wchar_t contains the number of the code point as
296 // used by the character set of the locale. These character sets are
297 // not necessarily a superset of ASCII.
299 // FIXME: This is wrong; the macro refers to the numerical values
300 // of wchar_t *literals*, which are not locale-dependent. However,
301 // FreeBSD systems apparently depend on us getting this wrong, and
302 // setting this to 1 is conforming even if all the basic source
303 // character literals have the same encoding as char and wchar_t.
304 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
307 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
308 this->UserLabelPrefix = "";
310 switch (Triple.getArch()) {
312 case llvm::Triple::x86:
313 case llvm::Triple::x86_64:
314 this->MCountName = ".mcount";
316 case llvm::Triple::mips:
317 case llvm::Triple::mipsel:
318 case llvm::Triple::ppc:
319 case llvm::Triple::ppc64:
320 case llvm::Triple::ppc64le:
321 this->MCountName = "_mcount";
323 case llvm::Triple::arm:
324 this->MCountName = "__mcount";
330 // GNU/kFreeBSD Target
331 template<typename Target>
332 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
334 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
335 MacroBuilder &Builder) const override {
336 // GNU/kFreeBSD defines; list based off of gcc output
338 DefineStd(Builder, "unix", Opts);
339 Builder.defineMacro("__FreeBSD_kernel__");
340 Builder.defineMacro("__GLIBC__");
341 Builder.defineMacro("__ELF__");
342 if (Opts.POSIXThreads)
343 Builder.defineMacro("_REENTRANT");
345 Builder.defineMacro("_GNU_SOURCE");
348 KFreeBSDTargetInfo(const llvm::Triple &Triple)
349 : OSTargetInfo<Target>(Triple) {
350 this->UserLabelPrefix = "";
355 template<typename Target>
356 class MinixTargetInfo : public OSTargetInfo<Target> {
358 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
359 MacroBuilder &Builder) const override {
362 Builder.defineMacro("__minix", "3");
363 Builder.defineMacro("_EM_WSIZE", "4");
364 Builder.defineMacro("_EM_PSIZE", "4");
365 Builder.defineMacro("_EM_SSIZE", "2");
366 Builder.defineMacro("_EM_LSIZE", "4");
367 Builder.defineMacro("_EM_FSIZE", "4");
368 Builder.defineMacro("_EM_DSIZE", "8");
369 Builder.defineMacro("__ELF__");
370 DefineStd(Builder, "unix", Opts);
373 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
374 this->UserLabelPrefix = "";
379 template<typename Target>
380 class LinuxTargetInfo : public OSTargetInfo<Target> {
382 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
383 MacroBuilder &Builder) const override {
384 // Linux defines; list based off of gcc output
385 DefineStd(Builder, "unix", Opts);
386 DefineStd(Builder, "linux", Opts);
387 Builder.defineMacro("__gnu_linux__");
388 Builder.defineMacro("__ELF__");
389 if (Triple.getEnvironment() == llvm::Triple::Android) {
390 Builder.defineMacro("__ANDROID__", "1");
391 unsigned Maj, Min, Rev;
392 Triple.getEnvironmentVersion(Maj, Min, Rev);
393 this->PlatformName = "android";
394 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
396 if (Opts.POSIXThreads)
397 Builder.defineMacro("_REENTRANT");
399 Builder.defineMacro("_GNU_SOURCE");
402 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
403 this->UserLabelPrefix = "";
404 this->WIntType = TargetInfo::UnsignedInt;
406 switch (Triple.getArch()) {
409 case llvm::Triple::ppc:
410 case llvm::Triple::ppc64:
411 case llvm::Triple::ppc64le:
412 this->MCountName = "_mcount";
417 const char *getStaticInitSectionSpecifier() const override {
418 return ".text.startup";
423 template<typename Target>
424 class NetBSDTargetInfo : public OSTargetInfo<Target> {
426 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
427 MacroBuilder &Builder) const override {
428 // NetBSD defines; list based off of gcc output
429 Builder.defineMacro("__NetBSD__");
430 Builder.defineMacro("__unix__");
431 Builder.defineMacro("__ELF__");
432 if (Opts.POSIXThreads)
433 Builder.defineMacro("_POSIX_THREADS");
435 switch (Triple.getArch()) {
438 case llvm::Triple::arm:
439 case llvm::Triple::armeb:
440 case llvm::Triple::thumb:
441 case llvm::Triple::thumbeb:
442 Builder.defineMacro("__ARM_DWARF_EH__");
447 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
448 this->UserLabelPrefix = "";
449 this->MCountName = "_mcount";
454 template<typename Target>
455 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
457 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
458 MacroBuilder &Builder) const override {
459 // OpenBSD defines; list based off of gcc output
461 Builder.defineMacro("__OpenBSD__");
462 DefineStd(Builder, "unix", Opts);
463 Builder.defineMacro("__ELF__");
464 if (Opts.POSIXThreads)
465 Builder.defineMacro("_REENTRANT");
468 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
469 this->UserLabelPrefix = "";
470 this->TLSSupported = false;
472 switch (Triple.getArch()) {
474 case llvm::Triple::x86:
475 case llvm::Triple::x86_64:
476 case llvm::Triple::arm:
477 case llvm::Triple::sparc:
478 this->MCountName = "__mcount";
480 case llvm::Triple::mips64:
481 case llvm::Triple::mips64el:
482 case llvm::Triple::ppc:
483 case llvm::Triple::sparcv9:
484 this->MCountName = "_mcount";
491 template<typename Target>
492 class BitrigTargetInfo : public OSTargetInfo<Target> {
494 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495 MacroBuilder &Builder) const override {
496 // Bitrig defines; list based off of gcc output
498 Builder.defineMacro("__Bitrig__");
499 DefineStd(Builder, "unix", Opts);
500 Builder.defineMacro("__ELF__");
501 if (Opts.POSIXThreads)
502 Builder.defineMacro("_REENTRANT");
504 switch (Triple.getArch()) {
507 case llvm::Triple::arm:
508 case llvm::Triple::armeb:
509 case llvm::Triple::thumb:
510 case llvm::Triple::thumbeb:
511 Builder.defineMacro("__ARM_DWARF_EH__");
516 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
517 this->UserLabelPrefix = "";
518 this->MCountName = "__mcount";
523 template<typename Target>
524 class PSPTargetInfo : public OSTargetInfo<Target> {
526 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
527 MacroBuilder &Builder) const override {
528 // PSP defines; list based on the output of the pspdev gcc toolchain.
529 Builder.defineMacro("PSP");
530 Builder.defineMacro("_PSP");
531 Builder.defineMacro("__psp__");
532 Builder.defineMacro("__ELF__");
535 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
536 this->UserLabelPrefix = "";
541 template<typename Target>
542 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
544 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
545 MacroBuilder &Builder) const override {
547 Builder.defineMacro("__PPC__");
548 Builder.defineMacro("__PPU__");
549 Builder.defineMacro("__CELLOS_LV2__");
550 Builder.defineMacro("__ELF__");
551 Builder.defineMacro("__LP32__");
552 Builder.defineMacro("_ARCH_PPC64");
553 Builder.defineMacro("__powerpc64__");
556 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
557 this->UserLabelPrefix = "";
558 this->LongWidth = this->LongAlign = 32;
559 this->PointerWidth = this->PointerAlign = 32;
560 this->IntMaxType = TargetInfo::SignedLongLong;
561 this->Int64Type = TargetInfo::SignedLongLong;
562 this->SizeType = TargetInfo::UnsignedInt;
563 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
567 template <typename Target>
568 class PS4OSTargetInfo : public OSTargetInfo<Target> {
570 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
571 MacroBuilder &Builder) const override {
572 Builder.defineMacro("__FreeBSD__", "9");
573 Builder.defineMacro("__FreeBSD_cc_version", "900001");
574 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
575 DefineStd(Builder, "unix", Opts);
576 Builder.defineMacro("__ELF__");
577 Builder.defineMacro("__PS4__");
580 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
581 this->WCharType = this->UnsignedShort;
583 this->UserLabelPrefix = "";
585 switch (Triple.getArch()) {
587 case llvm::Triple::x86_64:
588 this->MCountName = ".mcount";
595 template<typename Target>
596 class SolarisTargetInfo : public OSTargetInfo<Target> {
598 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
599 MacroBuilder &Builder) const override {
600 DefineStd(Builder, "sun", Opts);
601 DefineStd(Builder, "unix", Opts);
602 Builder.defineMacro("__ELF__");
603 Builder.defineMacro("__svr4__");
604 Builder.defineMacro("__SVR4");
605 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
606 // newer, but to 500 for everything else. feature_test.h has a check to
607 // ensure that you are not using C99 with an old version of X/Open or C89
608 // with a new version.
610 Builder.defineMacro("_XOPEN_SOURCE", "600");
612 Builder.defineMacro("_XOPEN_SOURCE", "500");
614 Builder.defineMacro("__C99FEATURES__");
615 Builder.defineMacro("_LARGEFILE_SOURCE");
616 Builder.defineMacro("_LARGEFILE64_SOURCE");
617 Builder.defineMacro("__EXTENSIONS__");
618 Builder.defineMacro("_REENTRANT");
621 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
622 this->UserLabelPrefix = "";
623 this->WCharType = this->SignedInt;
624 // FIXME: WIntType should be SignedLong
629 template<typename Target>
630 class WindowsTargetInfo : public OSTargetInfo<Target> {
632 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
633 MacroBuilder &Builder) const override {
634 Builder.defineMacro("_WIN32");
636 void getVisualStudioDefines(const LangOptions &Opts,
637 MacroBuilder &Builder) const {
638 if (Opts.CPlusPlus) {
640 Builder.defineMacro("_CPPRTTI");
642 if (Opts.CXXExceptions)
643 Builder.defineMacro("_CPPUNWIND");
646 if (!Opts.CharIsSigned)
647 Builder.defineMacro("_CHAR_UNSIGNED");
649 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
650 // but it works for now.
651 if (Opts.POSIXThreads)
652 Builder.defineMacro("_MT");
654 if (Opts.MSCompatibilityVersion) {
655 Builder.defineMacro("_MSC_VER",
656 Twine(Opts.MSCompatibilityVersion / 100000));
657 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
658 // FIXME We cannot encode the revision information into 32-bits
659 Builder.defineMacro("_MSC_BUILD", Twine(1));
661 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
662 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
665 if (Opts.MicrosoftExt) {
666 Builder.defineMacro("_MSC_EXTENSIONS");
668 if (Opts.CPlusPlus11) {
669 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
670 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
671 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
675 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
679 WindowsTargetInfo(const llvm::Triple &Triple)
680 : OSTargetInfo<Target>(Triple) {}
683 template <typename Target>
684 class NaClTargetInfo : public OSTargetInfo<Target> {
686 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
687 MacroBuilder &Builder) const override {
688 if (Opts.POSIXThreads)
689 Builder.defineMacro("_REENTRANT");
691 Builder.defineMacro("_GNU_SOURCE");
693 DefineStd(Builder, "unix", Opts);
694 Builder.defineMacro("__ELF__");
695 Builder.defineMacro("__native_client__");
699 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
700 this->UserLabelPrefix = "";
701 this->LongAlign = 32;
702 this->LongWidth = 32;
703 this->PointerAlign = 32;
704 this->PointerWidth = 32;
705 this->IntMaxType = TargetInfo::SignedLongLong;
706 this->Int64Type = TargetInfo::SignedLongLong;
707 this->DoubleAlign = 64;
708 this->LongDoubleWidth = 64;
709 this->LongDoubleAlign = 64;
710 this->LongLongWidth = 64;
711 this->LongLongAlign = 64;
712 this->SizeType = TargetInfo::UnsignedInt;
713 this->PtrDiffType = TargetInfo::SignedInt;
714 this->IntPtrType = TargetInfo::SignedInt;
715 // RegParmMax is inherited from the underlying architecture
716 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
717 if (Triple.getArch() == llvm::Triple::arm) {
718 // Handled in ARM's setABI().
719 } else if (Triple.getArch() == llvm::Triple::x86) {
720 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
721 } else if (Triple.getArch() == llvm::Triple::x86_64) {
722 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
723 } else if (Triple.getArch() == llvm::Triple::mipsel) {
724 // Handled on mips' setDescriptionString.
726 assert(Triple.getArch() == llvm::Triple::le32);
727 this->DescriptionString = "e-p:32:32-i64:64";
732 //===----------------------------------------------------------------------===//
733 // Specific target implementations.
734 //===----------------------------------------------------------------------===//
736 // PPC abstract base class
737 class PPCTargetInfo : public TargetInfo {
738 static const Builtin::Info BuiltinInfo[];
739 static const char * const GCCRegNames[];
740 static const TargetInfo::GCCRegAlias GCCRegAliases[];
743 // Target cpu features.
757 PPCTargetInfo(const llvm::Triple &Triple)
758 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
759 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
760 HasBPERMD(false), HasExtDiv(false) {
761 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
762 SimdDefaultAlign = 128;
763 LongDoubleWidth = LongDoubleAlign = 128;
764 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
767 /// \brief Flags for architecture specific defines.
770 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
771 ArchDefinePpcgr = 1 << 1,
772 ArchDefinePpcsq = 1 << 2,
773 ArchDefine440 = 1 << 3,
774 ArchDefine603 = 1 << 4,
775 ArchDefine604 = 1 << 5,
776 ArchDefinePwr4 = 1 << 6,
777 ArchDefinePwr5 = 1 << 7,
778 ArchDefinePwr5x = 1 << 8,
779 ArchDefinePwr6 = 1 << 9,
780 ArchDefinePwr6x = 1 << 10,
781 ArchDefinePwr7 = 1 << 11,
782 ArchDefinePwr8 = 1 << 12,
783 ArchDefineA2 = 1 << 13,
784 ArchDefineA2q = 1 << 14
787 // Note: GCC recognizes the following additional cpus:
788 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
789 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
791 bool setCPU(const std::string &Name) override {
792 bool CPUKnown = llvm::StringSwitch<bool>(Name)
793 .Case("generic", true)
815 .Case("e500mc", true)
817 .Case("power3", true)
819 .Case("power4", true)
821 .Case("power5", true)
823 .Case("power5x", true)
825 .Case("power6", true)
827 .Case("power6x", true)
829 .Case("power7", true)
831 .Case("power8", true)
833 .Case("powerpc", true)
835 .Case("powerpc64", true)
837 .Case("powerpc64le", true)
838 .Case("ppc64le", true)
848 StringRef getABI() const override { return ABI; }
850 void getTargetBuiltins(const Builtin::Info *&Records,
851 unsigned &NumRecords) const override {
852 Records = BuiltinInfo;
853 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
856 bool isCLZForZeroUndef() const override { return false; }
858 void getTargetDefines(const LangOptions &Opts,
859 MacroBuilder &Builder) const override;
861 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
863 bool handleTargetFeatures(std::vector<std::string> &Features,
864 DiagnosticsEngine &Diags) override;
865 bool hasFeature(StringRef Feature) const override;
867 void getGCCRegNames(const char * const *&Names,
868 unsigned &NumNames) const override;
869 void getGCCRegAliases(const GCCRegAlias *&Aliases,
870 unsigned &NumAliases) const override;
871 bool validateAsmConstraint(const char *&Name,
872 TargetInfo::ConstraintInfo &Info) const override {
874 default: return false;
877 case 'b': // Base register
878 case 'f': // Floating point register
879 Info.setAllowsRegister();
881 // FIXME: The following are added to allow parsing.
882 // I just took a guess at what the actions should be.
883 // Also, is more specific checking needed? I.e. specific registers?
884 case 'd': // Floating point register (containing 64-bit value)
885 case 'v': // Altivec vector register
886 Info.setAllowsRegister();
890 case 'd':// VSX vector register to hold vector double data
891 case 'f':// VSX vector register to hold vector float data
892 case 's':// VSX vector register to hold scalar float data
893 case 'a':// Any VSX register
894 case 'c':// An individual CR bit
899 Info.setAllowsRegister();
900 Name++; // Skip over 'w'.
902 case 'h': // `MQ', `CTR', or `LINK' register
903 case 'q': // `MQ' register
904 case 'c': // `CTR' register
905 case 'l': // `LINK' register
906 case 'x': // `CR' register (condition register) number 0
907 case 'y': // `CR' register (condition register)
908 case 'z': // `XER[CA]' carry bit (part of the XER register)
909 Info.setAllowsRegister();
911 case 'I': // Signed 16-bit constant
912 case 'J': // Unsigned 16-bit constant shifted left 16 bits
913 // (use `L' instead for SImode constants)
914 case 'K': // Unsigned 16-bit constant
915 case 'L': // Signed 16-bit constant shifted left 16 bits
916 case 'M': // Constant larger than 31
917 case 'N': // Exact power of 2
918 case 'P': // Constant whose negation is a signed 16-bit constant
919 case 'G': // Floating point constant that can be loaded into a
920 // register with one instruction per word
921 case 'H': // Integer/Floating point constant that can be loaded
922 // into a register using three instructions
924 case 'm': // Memory operand. Note that on PowerPC targets, m can
925 // include addresses that update the base register. It
926 // is therefore only safe to use `m' in an asm statement
927 // if that asm statement accesses the operand exactly once.
928 // The asm statement must also use `%U<opno>' as a
929 // placeholder for the "update" flag in the corresponding
930 // load or store instruction. For example:
931 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
933 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
934 // is not. Use es rather than m if you don't want the base
935 // register to be updated.
939 // es: A "stable" memory operand; that is, one which does not
940 // include any automodification of the base register. Unlike
941 // `m', this constraint can be used in asm statements that
942 // might access the operand several times, or that might not
944 Info.setAllowsMemory();
945 Name++; // Skip over 'e'.
947 case 'Q': // Memory operand that is an offset from a register (it is
948 // usually better to use `m' or `es' in asm statements)
949 case 'Z': // Memory operand that is an indexed or indirect from a
950 // register (it is usually better to use `m' or `es' in
952 Info.setAllowsMemory();
953 Info.setAllowsRegister();
955 case 'R': // AIX TOC entry
956 case 'a': // Address operand that is an indexed or indirect from a
957 // register (`p' is preferable for asm statements)
958 case 'S': // Constant suitable as a 64-bit mask operand
959 case 'T': // Constant suitable as a 32-bit mask operand
960 case 'U': // System V Release 4 small data area reference
961 case 't': // AND masks that can be performed by two rldic{l, r}
963 case 'W': // Vector constant that does not require memory
964 case 'j': // Vector constant that is all zeros.
970 std::string convertConstraint(const char *&Constraint) const override {
972 switch (*Constraint) {
975 // Two-character constraint; add "^" hint for later parsing.
976 R = std::string("^") + std::string(Constraint, 2);
980 return TargetInfo::convertConstraint(Constraint);
984 const char *getClobbers() const override {
987 int getEHDataRegisterNumber(unsigned RegNo) const override {
988 if (RegNo == 0) return 3;
989 if (RegNo == 1) return 4;
993 bool hasSjLjLowering() const override {
997 bool useFloat128ManglingForLongDouble() const override {
998 return LongDoubleWidth == 128 &&
999 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble &&
1000 getTriple().isOSBinFormatELF();
1004 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
1005 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1006 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1008 #include "clang/Basic/BuiltinsPPC.def"
1011 /// handleTargetFeatures - Perform initialization based on the user
1012 /// configured set of features.
1013 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1014 DiagnosticsEngine &Diags) {
1015 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
1016 // Ignore disabled features.
1017 if (Features[i][0] == '-')
1020 StringRef Feature = StringRef(Features[i]).substr(1);
1022 if (Feature == "vsx") {
1027 if (Feature == "bpermd") {
1032 if (Feature == "extdiv") {
1037 if (Feature == "power8-vector") {
1043 if (Feature == "crypto") {
1048 if (Feature == "direct-move") {
1049 HasDirectMove = true;
1054 if (Feature == "qpx") {
1059 if (Feature == "htm") {
1064 // TODO: Finish this list and add an assert that we've handled them
1071 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1072 /// #defines that are not tied to a specific subtarget.
1073 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1074 MacroBuilder &Builder) const {
1075 // Target identification.
1076 Builder.defineMacro("__ppc__");
1077 Builder.defineMacro("__PPC__");
1078 Builder.defineMacro("_ARCH_PPC");
1079 Builder.defineMacro("__powerpc__");
1080 Builder.defineMacro("__POWERPC__");
1081 if (PointerWidth == 64) {
1082 Builder.defineMacro("_ARCH_PPC64");
1083 Builder.defineMacro("__powerpc64__");
1084 Builder.defineMacro("__ppc64__");
1085 Builder.defineMacro("__PPC64__");
1088 // Target properties.
1089 if (getTriple().getArch() == llvm::Triple::ppc64le) {
1090 Builder.defineMacro("_LITTLE_ENDIAN");
1092 if (getTriple().getOS() != llvm::Triple::NetBSD &&
1093 getTriple().getOS() != llvm::Triple::OpenBSD)
1094 Builder.defineMacro("_BIG_ENDIAN");
1098 if (ABI == "elfv1" || ABI == "elfv1-qpx")
1099 Builder.defineMacro("_CALL_ELF", "1");
1101 Builder.defineMacro("_CALL_ELF", "2");
1103 // Subtarget options.
1104 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1105 Builder.defineMacro("__REGISTER_PREFIX__", "");
1107 // FIXME: Should be controlled by command line option.
1108 if (LongDoubleWidth == 128)
1109 Builder.defineMacro("__LONG_DOUBLE_128__");
1112 Builder.defineMacro("__VEC__", "10206");
1113 Builder.defineMacro("__ALTIVEC__");
1116 // CPU identification.
1117 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1118 .Case("440", ArchDefineName)
1119 .Case("450", ArchDefineName | ArchDefine440)
1120 .Case("601", ArchDefineName)
1121 .Case("602", ArchDefineName | ArchDefinePpcgr)
1122 .Case("603", ArchDefineName | ArchDefinePpcgr)
1123 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1124 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1125 .Case("604", ArchDefineName | ArchDefinePpcgr)
1126 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1127 .Case("620", ArchDefineName | ArchDefinePpcgr)
1128 .Case("630", ArchDefineName | ArchDefinePpcgr)
1129 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1130 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1131 .Case("750", ArchDefineName | ArchDefinePpcgr)
1132 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1134 .Case("a2", ArchDefineA2)
1135 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1136 .Case("pwr3", ArchDefinePpcgr)
1137 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1138 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1140 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1141 | ArchDefinePpcgr | ArchDefinePpcsq)
1142 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1143 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1144 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1145 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1147 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1148 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1149 | ArchDefinePpcgr | ArchDefinePpcsq)
1150 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1151 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1152 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1153 .Case("power3", ArchDefinePpcgr)
1154 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1155 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1157 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1158 | ArchDefinePpcgr | ArchDefinePpcsq)
1159 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1160 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1161 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1162 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1164 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1165 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1166 | ArchDefinePpcgr | ArchDefinePpcsq)
1167 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1168 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1169 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1170 .Default(ArchDefineNone);
1172 if (defs & ArchDefineName)
1173 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1174 if (defs & ArchDefinePpcgr)
1175 Builder.defineMacro("_ARCH_PPCGR");
1176 if (defs & ArchDefinePpcsq)
1177 Builder.defineMacro("_ARCH_PPCSQ");
1178 if (defs & ArchDefine440)
1179 Builder.defineMacro("_ARCH_440");
1180 if (defs & ArchDefine603)
1181 Builder.defineMacro("_ARCH_603");
1182 if (defs & ArchDefine604)
1183 Builder.defineMacro("_ARCH_604");
1184 if (defs & ArchDefinePwr4)
1185 Builder.defineMacro("_ARCH_PWR4");
1186 if (defs & ArchDefinePwr5)
1187 Builder.defineMacro("_ARCH_PWR5");
1188 if (defs & ArchDefinePwr5x)
1189 Builder.defineMacro("_ARCH_PWR5X");
1190 if (defs & ArchDefinePwr6)
1191 Builder.defineMacro("_ARCH_PWR6");
1192 if (defs & ArchDefinePwr6x)
1193 Builder.defineMacro("_ARCH_PWR6X");
1194 if (defs & ArchDefinePwr7)
1195 Builder.defineMacro("_ARCH_PWR7");
1196 if (defs & ArchDefinePwr8)
1197 Builder.defineMacro("_ARCH_PWR8");
1198 if (defs & ArchDefineA2)
1199 Builder.defineMacro("_ARCH_A2");
1200 if (defs & ArchDefineA2q) {
1201 Builder.defineMacro("_ARCH_A2Q");
1202 Builder.defineMacro("_ARCH_QP");
1205 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1206 Builder.defineMacro("__bg__");
1207 Builder.defineMacro("__THW_BLUEGENE__");
1208 Builder.defineMacro("__bgq__");
1209 Builder.defineMacro("__TOS_BGQ__");
1213 Builder.defineMacro("__VSX__");
1215 Builder.defineMacro("__POWER8_VECTOR__");
1217 Builder.defineMacro("__CRYPTO__");
1219 Builder.defineMacro("__HTM__");
1220 if (getTriple().getArch() == llvm::Triple::ppc64le ||
1221 (defs & ArchDefinePwr8) || (CPU == "pwr8")) {
1222 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1223 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1224 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1225 if (PointerWidth == 64)
1226 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1229 // FIXME: The following are not yet generated here by Clang, but are
1230 // generated by GCC:
1233 // __RECIP_PRECISION__
1234 // __APPLE_ALTIVEC__
1243 // __CMODEL_MEDIUM__
1250 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1251 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1261 .Case("ppc64", true)
1262 .Case("ppc64le", true)
1265 Features["qpx"] = (CPU == "a2q");
1266 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1267 .Case("ppc64le", true)
1270 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1271 .Case("ppc64le", true)
1274 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1275 .Case("ppc64le", true)
1279 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1280 .Case("ppc64le", true)
1284 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1285 .Case("ppc64le", true)
1290 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1291 return llvm::StringSwitch<bool>(Feature)
1292 .Case("powerpc", true)
1293 .Case("vsx", HasVSX)
1294 .Case("power8-vector", HasP8Vector)
1295 .Case("crypto", HasP8Crypto)
1296 .Case("direct-move", HasDirectMove)
1297 .Case("qpx", HasQPX)
1298 .Case("htm", HasHTM)
1299 .Case("bpermd", HasBPERMD)
1300 .Case("extdiv", HasExtDiv)
1304 const char * const PPCTargetInfo::GCCRegNames[] = {
1305 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1306 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1307 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1308 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1309 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1310 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1311 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1312 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1313 "mq", "lr", "ctr", "ap",
1314 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1316 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1317 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1318 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1319 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1321 "spe_acc", "spefscr",
1325 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1326 unsigned &NumNames) const {
1327 Names = GCCRegNames;
1328 NumNames = llvm::array_lengthof(GCCRegNames);
1331 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1332 // While some of these aliases do map to different registers
1333 // they still share the same register name.
1344 { { "10" }, "r10" },
1345 { { "11" }, "r11" },
1346 { { "12" }, "r12" },
1347 { { "13" }, "r13" },
1348 { { "14" }, "r14" },
1349 { { "15" }, "r15" },
1350 { { "16" }, "r16" },
1351 { { "17" }, "r17" },
1352 { { "18" }, "r18" },
1353 { { "19" }, "r19" },
1354 { { "20" }, "r20" },
1355 { { "21" }, "r21" },
1356 { { "22" }, "r22" },
1357 { { "23" }, "r23" },
1358 { { "24" }, "r24" },
1359 { { "25" }, "r25" },
1360 { { "26" }, "r26" },
1361 { { "27" }, "r27" },
1362 { { "28" }, "r28" },
1363 { { "29" }, "r29" },
1364 { { "30" }, "r30" },
1365 { { "31" }, "r31" },
1366 { { "fr0" }, "f0" },
1367 { { "fr1" }, "f1" },
1368 { { "fr2" }, "f2" },
1369 { { "fr3" }, "f3" },
1370 { { "fr4" }, "f4" },
1371 { { "fr5" }, "f5" },
1372 { { "fr6" }, "f6" },
1373 { { "fr7" }, "f7" },
1374 { { "fr8" }, "f8" },
1375 { { "fr9" }, "f9" },
1376 { { "fr10" }, "f10" },
1377 { { "fr11" }, "f11" },
1378 { { "fr12" }, "f12" },
1379 { { "fr13" }, "f13" },
1380 { { "fr14" }, "f14" },
1381 { { "fr15" }, "f15" },
1382 { { "fr16" }, "f16" },
1383 { { "fr17" }, "f17" },
1384 { { "fr18" }, "f18" },
1385 { { "fr19" }, "f19" },
1386 { { "fr20" }, "f20" },
1387 { { "fr21" }, "f21" },
1388 { { "fr22" }, "f22" },
1389 { { "fr23" }, "f23" },
1390 { { "fr24" }, "f24" },
1391 { { "fr25" }, "f25" },
1392 { { "fr26" }, "f26" },
1393 { { "fr27" }, "f27" },
1394 { { "fr28" }, "f28" },
1395 { { "fr29" }, "f29" },
1396 { { "fr30" }, "f30" },
1397 { { "fr31" }, "f31" },
1398 { { "cc" }, "cr0" },
1401 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1402 unsigned &NumAliases) const {
1403 Aliases = GCCRegAliases;
1404 NumAliases = llvm::array_lengthof(GCCRegAliases);
1407 class PPC32TargetInfo : public PPCTargetInfo {
1409 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1410 DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1412 switch (getTriple().getOS()) {
1413 case llvm::Triple::Linux:
1414 case llvm::Triple::FreeBSD:
1415 case llvm::Triple::NetBSD:
1416 SizeType = UnsignedInt;
1417 PtrDiffType = SignedInt;
1418 IntPtrType = SignedInt;
1424 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1425 LongDoubleWidth = LongDoubleAlign = 64;
1426 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1429 // PPC32 supports atomics up to 4 bytes.
1430 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1433 BuiltinVaListKind getBuiltinVaListKind() const override {
1434 // This is the ELF definition, and is overridden by the Darwin sub-target
1435 return TargetInfo::PowerABIBuiltinVaList;
1439 // Note: ABI differences may eventually require us to have a separate
1440 // TargetInfo for little endian.
1441 class PPC64TargetInfo : public PPCTargetInfo {
1443 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1444 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1445 IntMaxType = SignedLong;
1446 Int64Type = SignedLong;
1448 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1449 DescriptionString = "e-m:e-i64:64-n32:64";
1452 DescriptionString = "E-m:e-i64:64-n32:64";
1456 switch (getTriple().getOS()) {
1457 case llvm::Triple::FreeBSD:
1458 LongDoubleWidth = LongDoubleAlign = 64;
1459 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1461 case llvm::Triple::NetBSD:
1462 IntMaxType = SignedLongLong;
1463 Int64Type = SignedLongLong;
1469 // PPC64 supports atomics up to 8 bytes.
1470 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1472 BuiltinVaListKind getBuiltinVaListKind() const override {
1473 return TargetInfo::CharPtrBuiltinVaList;
1475 // PPC64 Linux-specifc ABI options.
1476 bool setABI(const std::string &Name) override {
1477 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1485 class DarwinPPC32TargetInfo :
1486 public DarwinTargetInfo<PPC32TargetInfo> {
1488 DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1489 : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1490 HasAlignMac68kSupport = true;
1491 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1492 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1494 SuitableAlign = 128;
1495 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1497 BuiltinVaListKind getBuiltinVaListKind() const override {
1498 return TargetInfo::CharPtrBuiltinVaList;
1502 class DarwinPPC64TargetInfo :
1503 public DarwinTargetInfo<PPC64TargetInfo> {
1505 DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1506 : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1507 HasAlignMac68kSupport = true;
1508 SuitableAlign = 128;
1509 DescriptionString = "E-m:o-i64:64-n32:64";
1513 static const unsigned NVPTXAddrSpaceMap[] = {
1516 4, // opencl_constant
1517 // FIXME: generic has to be added to the target
1518 0, // opencl_generic
1523 class NVPTXTargetInfo : public TargetInfo {
1524 static const char * const GCCRegNames[];
1525 static const Builtin::Info BuiltinInfo[];
1527 // The GPU profiles supported by the NVPTX backend
1538 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1540 TLSSupported = false;
1541 LongWidth = LongAlign = 64;
1542 AddrSpaceMap = &NVPTXAddrSpaceMap;
1543 UseAddrSpaceMapMangling = true;
1544 // Define available target features
1545 // These must be defined in sorted order!
1546 NoAsmVariants = true;
1547 // Set the default GPU to sm20
1550 void getTargetDefines(const LangOptions &Opts,
1551 MacroBuilder &Builder) const override {
1552 Builder.defineMacro("__PTX__");
1553 Builder.defineMacro("__NVPTX__");
1554 if (Opts.CUDAIsDevice) {
1555 // Set __CUDA_ARCH__ for the GPU specified.
1556 std::string CUDAArchCode;
1559 CUDAArchCode = "200";
1562 CUDAArchCode = "210";
1565 CUDAArchCode = "300";
1568 CUDAArchCode = "350";
1571 CUDAArchCode = "370";
1574 llvm_unreachable("Unhandled target CPU");
1576 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1579 void getTargetBuiltins(const Builtin::Info *&Records,
1580 unsigned &NumRecords) const override {
1581 Records = BuiltinInfo;
1582 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1584 bool hasFeature(StringRef Feature) const override {
1585 return Feature == "ptx" || Feature == "nvptx";
1588 void getGCCRegNames(const char * const *&Names,
1589 unsigned &NumNames) const override;
1590 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1591 unsigned &NumAliases) const override {
1597 validateAsmConstraint(const char *&Name,
1598 TargetInfo::ConstraintInfo &Info) const override {
1600 default: return false;
1607 Info.setAllowsRegister();
1611 const char *getClobbers() const override {
1612 // FIXME: Is this really right?
1615 BuiltinVaListKind getBuiltinVaListKind() const override {
1617 return TargetInfo::CharPtrBuiltinVaList;
1619 bool setCPU(const std::string &Name) override {
1620 GPU = llvm::StringSwitch<GPUKind>(Name)
1621 .Case("sm_20", GK_SM20)
1622 .Case("sm_21", GK_SM21)
1623 .Case("sm_30", GK_SM30)
1624 .Case("sm_35", GK_SM35)
1625 .Case("sm_37", GK_SM37)
1628 return GPU != GK_NONE;
1632 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1633 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1634 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1636 #include "clang/Basic/BuiltinsNVPTX.def"
1639 const char * const NVPTXTargetInfo::GCCRegNames[] = {
1643 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1644 unsigned &NumNames) const {
1645 Names = GCCRegNames;
1646 NumNames = llvm::array_lengthof(GCCRegNames);
1649 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1651 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1652 PointerWidth = PointerAlign = 32;
1653 SizeType = TargetInfo::UnsignedInt;
1654 PtrDiffType = TargetInfo::SignedInt;
1655 IntPtrType = TargetInfo::SignedInt;
1656 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1660 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1662 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1663 PointerWidth = PointerAlign = 64;
1664 SizeType = TargetInfo::UnsignedLong;
1665 PtrDiffType = TargetInfo::SignedLong;
1666 IntPtrType = TargetInfo::SignedLong;
1667 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1671 static const unsigned AMDGPUAddrSpaceMap[] = {
1674 2, // opencl_constant
1675 4, // opencl_generic
1681 // If you edit the description strings, make sure you update
1682 // getPointerWidthV().
1684 static const char *DescriptionStringR600 =
1685 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1686 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1688 static const char *DescriptionStringR600DoubleOps =
1689 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1690 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1692 static const char *DescriptionStringSI =
1693 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1694 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1695 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1697 class AMDGPUTargetInfo : public TargetInfo {
1698 static const Builtin::Info BuiltinInfo[];
1699 static const char * const GCCRegNames[];
1701 /// \brief The GPU profiles supported by the AMDGPU target.
1709 GK_EVERGREEN_DOUBLE_OPS,
1710 GK_NORTHERN_ISLANDS,
1712 GK_SOUTHERN_ISLANDS,
1722 AMDGPUTargetInfo(const llvm::Triple &Triple)
1723 : TargetInfo(Triple) {
1725 if (Triple.getArch() == llvm::Triple::amdgcn) {
1726 DescriptionString = DescriptionStringSI;
1727 GPU = GK_SOUTHERN_ISLANDS;
1732 DescriptionString = DescriptionStringR600;
1738 AddrSpaceMap = &AMDGPUAddrSpaceMap;
1739 UseAddrSpaceMapMangling = true;
1742 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1743 if (GPU <= GK_CAYMAN)
1756 const char * getClobbers() const override {
1760 void getGCCRegNames(const char * const *&Names,
1761 unsigned &NumNames) const override;
1763 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1764 unsigned &NumAliases) const override {
1769 bool validateAsmConstraint(const char *&Name,
1770 TargetInfo::ConstraintInfo &info) const override {
1774 void getTargetBuiltins(const Builtin::Info *&Records,
1775 unsigned &NumRecords) const override {
1776 Records = BuiltinInfo;
1777 NumRecords = clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin;
1780 void getTargetDefines(const LangOptions &Opts,
1781 MacroBuilder &Builder) const override {
1782 Builder.defineMacro("__R600__");
1784 Builder.defineMacro("__HAS_FMAF__");
1786 Builder.defineMacro("__HAS_LDEXPF__");
1787 if (hasFP64 && Opts.OpenCL) {
1788 Builder.defineMacro("cl_khr_fp64");
1792 BuiltinVaListKind getBuiltinVaListKind() const override {
1793 return TargetInfo::CharPtrBuiltinVaList;
1796 bool setCPU(const std::string &Name) override {
1797 GPU = llvm::StringSwitch<GPUKind>(Name)
1798 .Case("r600" , GK_R600)
1799 .Case("rv610", GK_R600)
1800 .Case("rv620", GK_R600)
1801 .Case("rv630", GK_R600)
1802 .Case("rv635", GK_R600)
1803 .Case("rs780", GK_R600)
1804 .Case("rs880", GK_R600)
1805 .Case("rv670", GK_R600_DOUBLE_OPS)
1806 .Case("rv710", GK_R700)
1807 .Case("rv730", GK_R700)
1808 .Case("rv740", GK_R700_DOUBLE_OPS)
1809 .Case("rv770", GK_R700_DOUBLE_OPS)
1810 .Case("palm", GK_EVERGREEN)
1811 .Case("cedar", GK_EVERGREEN)
1812 .Case("sumo", GK_EVERGREEN)
1813 .Case("sumo2", GK_EVERGREEN)
1814 .Case("redwood", GK_EVERGREEN)
1815 .Case("juniper", GK_EVERGREEN)
1816 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
1817 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
1818 .Case("barts", GK_NORTHERN_ISLANDS)
1819 .Case("turks", GK_NORTHERN_ISLANDS)
1820 .Case("caicos", GK_NORTHERN_ISLANDS)
1821 .Case("cayman", GK_CAYMAN)
1822 .Case("aruba", GK_CAYMAN)
1823 .Case("tahiti", GK_SOUTHERN_ISLANDS)
1824 .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1825 .Case("verde", GK_SOUTHERN_ISLANDS)
1826 .Case("oland", GK_SOUTHERN_ISLANDS)
1827 .Case("hainan", GK_SOUTHERN_ISLANDS)
1828 .Case("bonaire", GK_SEA_ISLANDS)
1829 .Case("kabini", GK_SEA_ISLANDS)
1830 .Case("kaveri", GK_SEA_ISLANDS)
1831 .Case("hawaii", GK_SEA_ISLANDS)
1832 .Case("mullins", GK_SEA_ISLANDS)
1833 .Case("tonga", GK_VOLCANIC_ISLANDS)
1834 .Case("iceland", GK_VOLCANIC_ISLANDS)
1835 .Case("carrizo", GK_VOLCANIC_ISLANDS)
1838 if (GPU == GK_NONE) {
1842 // Set the correct data layout
1848 case GK_NORTHERN_ISLANDS:
1849 DescriptionString = DescriptionStringR600;
1854 case GK_R600_DOUBLE_OPS:
1855 case GK_R700_DOUBLE_OPS:
1856 case GK_EVERGREEN_DOUBLE_OPS:
1858 DescriptionString = DescriptionStringR600DoubleOps;
1863 case GK_SOUTHERN_ISLANDS:
1864 case GK_SEA_ISLANDS:
1865 case GK_VOLCANIC_ISLANDS:
1866 DescriptionString = DescriptionStringSI;
1877 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
1878 #define BUILTIN(ID, TYPE, ATTRS) \
1879 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1880 #include "clang/Basic/BuiltinsAMDGPU.def"
1882 const char * const AMDGPUTargetInfo::GCCRegNames[] = {
1883 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1884 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1885 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1886 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1887 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
1888 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
1889 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
1890 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
1891 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
1892 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
1893 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
1894 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
1895 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
1896 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
1897 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
1898 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
1899 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
1900 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
1901 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
1902 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
1903 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
1904 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
1905 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
1906 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
1907 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
1908 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
1909 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
1910 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
1911 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
1912 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
1913 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
1914 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
1915 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1916 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
1917 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
1918 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
1919 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
1920 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
1921 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
1922 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
1923 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
1924 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
1925 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
1926 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
1927 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
1928 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
1929 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
1930 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127"
1931 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi",
1932 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi"
1935 void AMDGPUTargetInfo::getGCCRegNames(const char * const *&Names,
1936 unsigned &NumNames) const {
1937 Names = GCCRegNames;
1938 NumNames = llvm::array_lengthof(GCCRegNames);
1941 // Namespace for x86 abstract base class
1942 const Builtin::Info BuiltinInfo[] = {
1943 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1944 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1946 #include "clang/Basic/BuiltinsX86.def"
1949 static const char* const GCCRegNames[] = {
1950 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1951 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1952 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1953 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1954 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1955 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1956 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1957 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1958 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1961 const TargetInfo::AddlRegName AddlRegNames[] = {
1962 { { "al", "ah", "eax", "rax" }, 0 },
1963 { { "bl", "bh", "ebx", "rbx" }, 3 },
1964 { { "cl", "ch", "ecx", "rcx" }, 2 },
1965 { { "dl", "dh", "edx", "rdx" }, 1 },
1966 { { "esi", "rsi" }, 4 },
1967 { { "edi", "rdi" }, 5 },
1968 { { "esp", "rsp" }, 7 },
1969 { { "ebp", "rbp" }, 6 },
1972 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1973 // most of the implementation can be shared.
1974 class X86TargetInfo : public TargetInfo {
1976 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1979 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
2003 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW,
2008 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2010 /// Each enumeration represents a particular CPU supported by Clang. These
2011 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2016 /// i386-generation processors.
2022 /// i486-generation processors.
2031 /// i586-generation processors, P5 microarchitecture based.
2039 /// i686-generation processors, P6 / Pentium M microarchitecture based.
2049 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2050 /// Clang however has some logic to suport this.
2051 // FIXME: Warn, deprecate, and potentially remove this.
2056 /// Netburst microarchitecture based processors.
2065 /// Core microarchitecture based processors.
2069 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2070 /// codename which GCC no longer accepts as an option to -march, but Clang
2071 /// has some logic for recognizing it.
2072 // FIXME: Warn, deprecate, and potentially remove this.
2084 /// Nehalem microarchitecture based processors.
2088 /// Westmere microarchitecture based processors.
2091 /// \name Sandy Bridge
2092 /// Sandy Bridge microarchitecture based processors.
2095 /// \name Ivy Bridge
2096 /// Ivy Bridge microarchitecture based processors.
2100 /// Haswell microarchitecture based processors.
2104 /// Broadwell microarchitecture based processors.
2108 /// Skylake microarchitecture based processors.
2111 /// \name Knights Landing
2112 /// Knights Landing processor.
2116 /// K6 architecture processors.
2124 /// K7 architecture processors.
2127 CK_AthlonThunderbird,
2134 /// K8 architecture processors.
2147 /// Bobcat architecture processors.
2154 /// Bulldozer architecture processors.
2162 /// This specification is deprecated and will be removed in the future.
2163 /// Users should prefer \see CK_K8.
2164 // FIXME: Warn on this when the CPU is set to it.
2170 /// Geode processors.
2183 X86TargetInfo(const llvm::Triple &Triple)
2184 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
2185 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
2186 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
2187 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
2188 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
2189 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
2190 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
2191 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
2193 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
2195 unsigned getFloatEvalMethod() const override {
2196 // X87 evaluates with 80 bits "long double" precision.
2197 return SSELevel == NoSSE ? 2 : 0;
2199 void getTargetBuiltins(const Builtin::Info *&Records,
2200 unsigned &NumRecords) const override {
2201 Records = BuiltinInfo;
2202 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
2204 void getGCCRegNames(const char * const *&Names,
2205 unsigned &NumNames) const override {
2206 Names = GCCRegNames;
2207 NumNames = llvm::array_lengthof(GCCRegNames);
2209 void getGCCRegAliases(const GCCRegAlias *&Aliases,
2210 unsigned &NumAliases) const override {
2214 void getGCCAddlRegNames(const AddlRegName *&Names,
2215 unsigned &NumNames) const override {
2216 Names = AddlRegNames;
2217 NumNames = llvm::array_lengthof(AddlRegNames);
2219 bool validateCpuSupports(StringRef Name) const override;
2220 bool validateAsmConstraint(const char *&Name,
2221 TargetInfo::ConstraintInfo &info) const override;
2223 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2225 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2227 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2229 std::string convertConstraint(const char *&Constraint) const override;
2230 const char *getClobbers() const override {
2231 return "~{dirflag},~{fpsr},~{flags}";
2233 void getTargetDefines(const LangOptions &Opts,
2234 MacroBuilder &Builder) const override;
2235 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2237 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2239 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2241 void setFeatureEnabled(llvm::StringMap<bool> &Features,
2242 StringRef Name, bool Enabled) const override {
2243 setFeatureEnabledImpl(Features, Name, Enabled);
2245 // This exists purely to cut down on the number of virtual calls in
2246 // getDefaultFeatures which calls this repeatedly.
2247 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2248 StringRef Name, bool Enabled);
2249 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
2250 bool hasFeature(StringRef Feature) const override;
2251 bool handleTargetFeatures(std::vector<std::string> &Features,
2252 DiagnosticsEngine &Diags) override;
2253 StringRef getABI() const override {
2254 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
2256 else if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2258 else if (getTriple().getArch() == llvm::Triple::x86 &&
2259 MMX3DNowLevel == NoMMX3DNow)
2263 bool setCPU(const std::string &Name) override {
2264 CPU = llvm::StringSwitch<CPUKind>(Name)
2265 .Case("i386", CK_i386)
2266 .Case("i486", CK_i486)
2267 .Case("winchip-c6", CK_WinChipC6)
2268 .Case("winchip2", CK_WinChip2)
2270 .Case("i586", CK_i586)
2271 .Case("pentium", CK_Pentium)
2272 .Case("pentium-mmx", CK_PentiumMMX)
2273 .Case("i686", CK_i686)
2274 .Case("pentiumpro", CK_PentiumPro)
2275 .Case("pentium2", CK_Pentium2)
2276 .Case("pentium3", CK_Pentium3)
2277 .Case("pentium3m", CK_Pentium3M)
2278 .Case("pentium-m", CK_PentiumM)
2279 .Case("c3-2", CK_C3_2)
2280 .Case("yonah", CK_Yonah)
2281 .Case("pentium4", CK_Pentium4)
2282 .Case("pentium4m", CK_Pentium4M)
2283 .Case("prescott", CK_Prescott)
2284 .Case("nocona", CK_Nocona)
2285 .Case("core2", CK_Core2)
2286 .Case("penryn", CK_Penryn)
2287 .Case("bonnell", CK_Bonnell)
2288 .Case("atom", CK_Bonnell) // Legacy name.
2289 .Case("silvermont", CK_Silvermont)
2290 .Case("slm", CK_Silvermont) // Legacy name.
2291 .Case("nehalem", CK_Nehalem)
2292 .Case("corei7", CK_Nehalem) // Legacy name.
2293 .Case("westmere", CK_Westmere)
2294 .Case("sandybridge", CK_SandyBridge)
2295 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2296 .Case("ivybridge", CK_IvyBridge)
2297 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2298 .Case("haswell", CK_Haswell)
2299 .Case("core-avx2", CK_Haswell) // Legacy name.
2300 .Case("broadwell", CK_Broadwell)
2301 .Case("skylake", CK_Skylake)
2302 .Case("skx", CK_Skylake) // Legacy name.
2303 .Case("knl", CK_KNL)
2305 .Case("k6-2", CK_K6_2)
2306 .Case("k6-3", CK_K6_3)
2307 .Case("athlon", CK_Athlon)
2308 .Case("athlon-tbird", CK_AthlonThunderbird)
2309 .Case("athlon-4", CK_Athlon4)
2310 .Case("athlon-xp", CK_AthlonXP)
2311 .Case("athlon-mp", CK_AthlonMP)
2312 .Case("athlon64", CK_Athlon64)
2313 .Case("athlon64-sse3", CK_Athlon64SSE3)
2314 .Case("athlon-fx", CK_AthlonFX)
2316 .Case("k8-sse3", CK_K8SSE3)
2317 .Case("opteron", CK_Opteron)
2318 .Case("opteron-sse3", CK_OpteronSSE3)
2319 .Case("barcelona", CK_AMDFAM10)
2320 .Case("amdfam10", CK_AMDFAM10)
2321 .Case("btver1", CK_BTVER1)
2322 .Case("btver2", CK_BTVER2)
2323 .Case("bdver1", CK_BDVER1)
2324 .Case("bdver2", CK_BDVER2)
2325 .Case("bdver3", CK_BDVER3)
2326 .Case("bdver4", CK_BDVER4)
2327 .Case("x86-64", CK_x86_64)
2328 .Case("geode", CK_Geode)
2329 .Default(CK_Generic);
2331 // Perform any per-CPU checks necessary to determine if this CPU is
2333 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2334 // invalid without explaining *why*.
2337 // No processor selected!
2363 case CK_AthlonThunderbird:
2368 // Only accept certain architectures when compiling in 32-bit mode.
2369 if (getTriple().getArch() != llvm::Triple::x86)
2380 case CK_SandyBridge:
2387 case CK_Athlon64SSE3:
2392 case CK_OpteronSSE3:
2403 llvm_unreachable("Unhandled CPU kind");
2406 bool setFPMath(StringRef Name) override;
2408 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2409 // We accept all non-ARM calling conventions
2410 return (CC == CC_X86ThisCall ||
2411 CC == CC_X86FastCall ||
2412 CC == CC_X86StdCall ||
2413 CC == CC_X86VectorCall ||
2415 CC == CC_X86Pascal ||
2416 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2419 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2420 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2423 bool hasSjLjLowering() const override {
2428 bool X86TargetInfo::setFPMath(StringRef Name) {
2429 if (Name == "387") {
2433 if (Name == "sse") {
2440 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2441 // FIXME: This *really* should not be here.
2443 // X86_64 always has SSE2.
2444 if (getTriple().getArch() == llvm::Triple::x86_64)
2445 setFeatureEnabledImpl(Features, "sse2", true);
2460 setFeatureEnabledImpl(Features, "mmx", true);
2465 setFeatureEnabledImpl(Features, "sse", true);
2471 setFeatureEnabledImpl(Features, "sse2", true);
2476 setFeatureEnabledImpl(Features, "sse3", true);
2477 setFeatureEnabledImpl(Features, "cx16", true);
2481 setFeatureEnabledImpl(Features, "ssse3", true);
2482 setFeatureEnabledImpl(Features, "cx16", true);
2485 setFeatureEnabledImpl(Features, "sse4.1", true);
2486 setFeatureEnabledImpl(Features, "cx16", true);
2489 setFeatureEnabledImpl(Features, "avx512f", true);
2490 setFeatureEnabledImpl(Features, "avx512cd", true);
2491 setFeatureEnabledImpl(Features, "avx512dq", true);
2492 setFeatureEnabledImpl(Features, "avx512bw", true);
2493 setFeatureEnabledImpl(Features, "avx512vl", true);
2496 setFeatureEnabledImpl(Features, "rdseed", true);
2497 setFeatureEnabledImpl(Features, "adx", true);
2500 setFeatureEnabledImpl(Features, "avx2", true);
2501 setFeatureEnabledImpl(Features, "lzcnt", true);
2502 setFeatureEnabledImpl(Features, "bmi", true);
2503 setFeatureEnabledImpl(Features, "bmi2", true);
2504 setFeatureEnabledImpl(Features, "rtm", true);
2505 setFeatureEnabledImpl(Features, "fma", true);
2508 setFeatureEnabledImpl(Features, "rdrnd", true);
2509 setFeatureEnabledImpl(Features, "f16c", true);
2510 setFeatureEnabledImpl(Features, "fsgsbase", true);
2512 case CK_SandyBridge:
2513 setFeatureEnabledImpl(Features, "avx", true);
2517 setFeatureEnabledImpl(Features, "aes", true);
2518 setFeatureEnabledImpl(Features, "pclmul", true);
2521 setFeatureEnabledImpl(Features, "sse4.2", true);
2522 setFeatureEnabledImpl(Features, "cx16", true);
2525 setFeatureEnabledImpl(Features, "avx512f", true);
2526 setFeatureEnabledImpl(Features, "avx512cd", true);
2527 setFeatureEnabledImpl(Features, "avx512er", true);
2528 setFeatureEnabledImpl(Features, "avx512pf", true);
2529 setFeatureEnabledImpl(Features, "rdseed", true);
2530 setFeatureEnabledImpl(Features, "adx", true);
2531 setFeatureEnabledImpl(Features, "lzcnt", true);
2532 setFeatureEnabledImpl(Features, "bmi", true);
2533 setFeatureEnabledImpl(Features, "bmi2", true);
2534 setFeatureEnabledImpl(Features, "rtm", true);
2535 setFeatureEnabledImpl(Features, "fma", true);
2536 setFeatureEnabledImpl(Features, "rdrnd", true);
2537 setFeatureEnabledImpl(Features, "f16c", true);
2538 setFeatureEnabledImpl(Features, "fsgsbase", true);
2539 setFeatureEnabledImpl(Features, "aes", true);
2540 setFeatureEnabledImpl(Features, "pclmul", true);
2541 setFeatureEnabledImpl(Features, "cx16", true);
2547 setFeatureEnabledImpl(Features, "3dnow", true);
2550 case CK_AthlonThunderbird:
2552 setFeatureEnabledImpl(Features, "3dnowa", true);
2557 setFeatureEnabledImpl(Features, "sse", true);
2558 setFeatureEnabledImpl(Features, "3dnowa", true);
2564 setFeatureEnabledImpl(Features, "sse2", true);
2565 setFeatureEnabledImpl(Features, "3dnowa", true);
2568 setFeatureEnabledImpl(Features, "sse4a", true);
2569 setFeatureEnabledImpl(Features, "lzcnt", true);
2570 setFeatureEnabledImpl(Features, "popcnt", true);
2573 case CK_OpteronSSE3:
2574 case CK_Athlon64SSE3:
2575 setFeatureEnabledImpl(Features, "sse3", true);
2576 setFeatureEnabledImpl(Features, "3dnowa", true);
2579 setFeatureEnabledImpl(Features, "avx", true);
2580 setFeatureEnabledImpl(Features, "aes", true);
2581 setFeatureEnabledImpl(Features, "pclmul", true);
2582 setFeatureEnabledImpl(Features, "bmi", true);
2583 setFeatureEnabledImpl(Features, "f16c", true);
2586 setFeatureEnabledImpl(Features, "ssse3", true);
2587 setFeatureEnabledImpl(Features, "sse4a", true);
2588 setFeatureEnabledImpl(Features, "lzcnt", true);
2589 setFeatureEnabledImpl(Features, "popcnt", true);
2590 setFeatureEnabledImpl(Features, "prfchw", true);
2591 setFeatureEnabledImpl(Features, "cx16", true);
2594 setFeatureEnabledImpl(Features, "avx2", true);
2595 setFeatureEnabledImpl(Features, "bmi2", true);
2598 setFeatureEnabledImpl(Features, "fsgsbase", true);
2601 setFeatureEnabledImpl(Features, "bmi", true);
2602 setFeatureEnabledImpl(Features, "fma", true);
2603 setFeatureEnabledImpl(Features, "f16c", true);
2604 setFeatureEnabledImpl(Features, "tbm", true);
2607 // xop implies avx, sse4a and fma4.
2608 setFeatureEnabledImpl(Features, "xop", true);
2609 setFeatureEnabledImpl(Features, "lzcnt", true);
2610 setFeatureEnabledImpl(Features, "aes", true);
2611 setFeatureEnabledImpl(Features, "pclmul", true);
2612 setFeatureEnabledImpl(Features, "prfchw", true);
2613 setFeatureEnabledImpl(Features, "cx16", true);
2618 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2619 X86SSEEnum Level, bool Enabled) {
2623 Features["avx512f"] = true;
2625 Features["avx2"] = true;
2627 Features["avx"] = true;
2629 Features["sse4.2"] = true;
2631 Features["sse4.1"] = true;
2633 Features["ssse3"] = true;
2635 Features["sse3"] = true;
2637 Features["sse2"] = true;
2639 Features["sse"] = true;
2649 Features["sse"] = false;
2651 Features["sse2"] = Features["pclmul"] = Features["aes"] =
2652 Features["sha"] = false;
2654 Features["sse3"] = false;
2655 setXOPLevel(Features, NoXOP, false);
2657 Features["ssse3"] = false;
2659 Features["sse4.1"] = false;
2661 Features["sse4.2"] = false;
2663 Features["fma"] = Features["avx"] = Features["f16c"] = false;
2664 setXOPLevel(Features, FMA4, false);
2666 Features["avx2"] = false;
2668 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2669 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2670 Features["avx512vl"] = false;
2674 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2675 MMX3DNowEnum Level, bool Enabled) {
2678 case AMD3DNowAthlon:
2679 Features["3dnowa"] = true;
2681 Features["3dnow"] = true;
2683 Features["mmx"] = true;
2693 Features["mmx"] = false;
2695 Features["3dnow"] = false;
2696 case AMD3DNowAthlon:
2697 Features["3dnowa"] = false;
2701 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2706 Features["xop"] = true;
2708 Features["fma4"] = true;
2709 setSSELevel(Features, AVX, true);
2711 Features["sse4a"] = true;
2712 setSSELevel(Features, SSE3, true);
2722 Features["sse4a"] = false;
2724 Features["fma4"] = false;
2726 Features["xop"] = false;
2730 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2731 StringRef Name, bool Enabled) {
2732 // This is a bit of a hack to deal with the sse4 target feature when used
2733 // as part of the target attribute. We handle sse4 correctly everywhere
2734 // else. See below for more information on how we handle the sse4 options.
2736 Features[Name] = Enabled;
2738 if (Name == "mmx") {
2739 setMMXLevel(Features, MMX, Enabled);
2740 } else if (Name == "sse") {
2741 setSSELevel(Features, SSE1, Enabled);
2742 } else if (Name == "sse2") {
2743 setSSELevel(Features, SSE2, Enabled);
2744 } else if (Name == "sse3") {
2745 setSSELevel(Features, SSE3, Enabled);
2746 } else if (Name == "ssse3") {
2747 setSSELevel(Features, SSSE3, Enabled);
2748 } else if (Name == "sse4.2") {
2749 setSSELevel(Features, SSE42, Enabled);
2750 } else if (Name == "sse4.1") {
2751 setSSELevel(Features, SSE41, Enabled);
2752 } else if (Name == "3dnow") {
2753 setMMXLevel(Features, AMD3DNow, Enabled);
2754 } else if (Name == "3dnowa") {
2755 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2756 } else if (Name == "aes") {
2758 setSSELevel(Features, SSE2, Enabled);
2759 } else if (Name == "pclmul") {
2761 setSSELevel(Features, SSE2, Enabled);
2762 } else if (Name == "avx") {
2763 setSSELevel(Features, AVX, Enabled);
2764 } else if (Name == "avx2") {
2765 setSSELevel(Features, AVX2, Enabled);
2766 } else if (Name == "avx512f") {
2767 setSSELevel(Features, AVX512F, Enabled);
2768 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2769 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2771 setSSELevel(Features, AVX512F, Enabled);
2772 } else if (Name == "fma") {
2774 setSSELevel(Features, AVX, Enabled);
2775 } else if (Name == "fma4") {
2776 setXOPLevel(Features, FMA4, Enabled);
2777 } else if (Name == "xop") {
2778 setXOPLevel(Features, XOP, Enabled);
2779 } else if (Name == "sse4a") {
2780 setXOPLevel(Features, SSE4A, Enabled);
2781 } else if (Name == "f16c") {
2783 setSSELevel(Features, AVX, Enabled);
2784 } else if (Name == "sha") {
2786 setSSELevel(Features, SSE2, Enabled);
2787 } else if (Name == "sse4") {
2788 // We can get here via the __target__ attribute since that's not controlled
2789 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
2790 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
2793 setSSELevel(Features, SSE42, Enabled);
2795 setSSELevel(Features, SSE41, Enabled);
2799 /// handleTargetFeatures - Perform initialization based on the user
2800 /// configured set of features.
2801 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2802 DiagnosticsEngine &Diags) {
2803 // Remember the maximum enabled sselevel.
2804 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2805 // Ignore disabled features.
2806 if (Features[i][0] == '-')
2809 StringRef Feature = StringRef(Features[i]).substr(1);
2811 if (Feature == "aes") {
2816 if (Feature == "pclmul") {
2821 if (Feature == "lzcnt") {
2826 if (Feature == "rdrnd") {
2831 if (Feature == "fsgsbase") {
2836 if (Feature == "bmi") {
2841 if (Feature == "bmi2") {
2846 if (Feature == "popcnt") {
2851 if (Feature == "rtm") {
2856 if (Feature == "prfchw") {
2861 if (Feature == "rdseed") {
2866 if (Feature == "adx") {
2871 if (Feature == "tbm") {
2876 if (Feature == "fma") {
2881 if (Feature == "f16c") {
2886 if (Feature == "avx512cd") {
2891 if (Feature == "avx512er") {
2896 if (Feature == "avx512pf") {
2901 if (Feature == "avx512dq") {
2906 if (Feature == "avx512bw") {
2911 if (Feature == "avx512vl") {
2916 if (Feature == "sha") {
2921 if (Feature == "cx16") {
2926 assert(Features[i][0] == '+' && "Invalid target feature!");
2927 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2928 .Case("avx512f", AVX512F)
2931 .Case("sse4.2", SSE42)
2932 .Case("sse4.1", SSE41)
2933 .Case("ssse3", SSSE3)
2938 SSELevel = std::max(SSELevel, Level);
2940 MMX3DNowEnum ThreeDNowLevel =
2941 llvm::StringSwitch<MMX3DNowEnum>(Feature)
2942 .Case("3dnowa", AMD3DNowAthlon)
2943 .Case("3dnow", AMD3DNow)
2945 .Default(NoMMX3DNow);
2946 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2948 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2951 .Case("sse4a", SSE4A)
2953 XOPLevel = std::max(XOPLevel, XLevel);
2956 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2957 // Can't do this earlier because we need to be able to explicitly enable
2958 // popcnt and still disable sse4.2.
2959 if (!HasPOPCNT && SSELevel >= SSE42 &&
2960 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2962 Features.push_back("+popcnt");
2965 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2966 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2967 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2969 Features.push_back("+prfchw");
2972 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2973 // matches the selected sse level.
2974 if (FPMath == FP_SSE && SSELevel < SSE1) {
2975 Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2977 } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2978 Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2982 // Don't tell the backend if we're turning off mmx; it will end up disabling
2983 // SSE, which we don't want.
2984 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2986 std::vector<std::string>::iterator it;
2987 it = std::find(Features.begin(), Features.end(), "-mmx");
2988 if (it != Features.end())
2990 else if (SSELevel > NoSSE)
2991 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2994 (getABI() == "avx512") ? 512 : (getABI() == "avx") ? 256 : 128;
2998 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2999 /// definitions for this particular subtarget.
3000 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
3001 MacroBuilder &Builder) const {
3002 // Target identification.
3003 if (getTriple().getArch() == llvm::Triple::x86_64) {
3004 Builder.defineMacro("__amd64__");
3005 Builder.defineMacro("__amd64");
3006 Builder.defineMacro("__x86_64");
3007 Builder.defineMacro("__x86_64__");
3008 if (getTriple().getArchName() == "x86_64h") {
3009 Builder.defineMacro("__x86_64h");
3010 Builder.defineMacro("__x86_64h__");
3013 DefineStd(Builder, "i386", Opts);
3016 // Subtarget options.
3017 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
3018 // truly should be based on -mtune options.
3023 // The rest are coming from the i386 define above.
3024 Builder.defineMacro("__tune_i386__");
3030 defineCPUMacros(Builder, "i486");
3033 Builder.defineMacro("__pentium_mmx__");
3034 Builder.defineMacro("__tune_pentium_mmx__");
3038 defineCPUMacros(Builder, "i586");
3039 defineCPUMacros(Builder, "pentium");
3044 Builder.defineMacro("__tune_pentium3__");
3048 Builder.defineMacro("__tune_pentium2__");
3051 Builder.defineMacro("__tune_i686__");
3052 Builder.defineMacro("__tune_pentiumpro__");
3055 Builder.defineMacro("__i686");
3056 Builder.defineMacro("__i686__");
3057 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3058 Builder.defineMacro("__pentiumpro");
3059 Builder.defineMacro("__pentiumpro__");
3063 defineCPUMacros(Builder, "pentium4");
3068 defineCPUMacros(Builder, "nocona");
3072 defineCPUMacros(Builder, "core2");
3075 defineCPUMacros(Builder, "atom");
3078 defineCPUMacros(Builder, "slm");
3082 case CK_SandyBridge:
3086 // FIXME: Historically, we defined this legacy name, it would be nice to
3087 // remove it at some point. We've never exposed fine-grained names for
3088 // recent primary x86 CPUs, and we should keep it that way.
3089 defineCPUMacros(Builder, "corei7");
3092 // FIXME: Historically, we defined this legacy name, it would be nice to
3093 // remove it at some point. This is the only fine-grained CPU macro in the
3094 // main intel CPU line, and it would be better to not have these and force
3095 // people to use ISA macros.
3096 defineCPUMacros(Builder, "skx");
3099 defineCPUMacros(Builder, "knl");
3102 Builder.defineMacro("__k6_2__");
3103 Builder.defineMacro("__tune_k6_2__");
3106 if (CPU != CK_K6_2) { // In case of fallthrough
3107 // FIXME: GCC may be enabling these in cases where some other k6
3108 // architecture is specified but -m3dnow is explicitly provided. The
3109 // exact semantics need to be determined and emulated here.
3110 Builder.defineMacro("__k6_3__");
3111 Builder.defineMacro("__tune_k6_3__");
3115 defineCPUMacros(Builder, "k6");
3118 case CK_AthlonThunderbird:
3122 defineCPUMacros(Builder, "athlon");
3123 if (SSELevel != NoSSE) {
3124 Builder.defineMacro("__athlon_sse__");
3125 Builder.defineMacro("__tune_athlon_sse__");
3132 case CK_OpteronSSE3:
3134 case CK_Athlon64SSE3:
3136 defineCPUMacros(Builder, "k8");
3139 defineCPUMacros(Builder, "amdfam10");
3142 defineCPUMacros(Builder, "btver1");
3145 defineCPUMacros(Builder, "btver2");
3148 defineCPUMacros(Builder, "bdver1");
3151 defineCPUMacros(Builder, "bdver2");
3154 defineCPUMacros(Builder, "bdver3");
3157 defineCPUMacros(Builder, "bdver4");
3160 defineCPUMacros(Builder, "geode");
3164 // Target properties.
3165 Builder.defineMacro("__REGISTER_PREFIX__", "");
3167 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3168 // functions in glibc header files that use FP Stack inline asm which the
3169 // backend can't deal with (PR879).
3170 Builder.defineMacro("__NO_MATH_INLINES");
3173 Builder.defineMacro("__AES__");
3176 Builder.defineMacro("__PCLMUL__");
3179 Builder.defineMacro("__LZCNT__");
3182 Builder.defineMacro("__RDRND__");
3185 Builder.defineMacro("__FSGSBASE__");
3188 Builder.defineMacro("__BMI__");
3191 Builder.defineMacro("__BMI2__");
3194 Builder.defineMacro("__POPCNT__");
3197 Builder.defineMacro("__RTM__");
3200 Builder.defineMacro("__PRFCHW__");
3203 Builder.defineMacro("__RDSEED__");
3206 Builder.defineMacro("__ADX__");
3209 Builder.defineMacro("__TBM__");
3213 Builder.defineMacro("__XOP__");
3215 Builder.defineMacro("__FMA4__");
3217 Builder.defineMacro("__SSE4A__");
3223 Builder.defineMacro("__FMA__");
3226 Builder.defineMacro("__F16C__");
3229 Builder.defineMacro("__AVX512CD__");
3231 Builder.defineMacro("__AVX512ER__");
3233 Builder.defineMacro("__AVX512PF__");
3235 Builder.defineMacro("__AVX512DQ__");
3237 Builder.defineMacro("__AVX512BW__");
3239 Builder.defineMacro("__AVX512VL__");
3242 Builder.defineMacro("__SHA__");
3245 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3247 // Each case falls through to the previous one here.
3250 Builder.defineMacro("__AVX512F__");
3252 Builder.defineMacro("__AVX2__");
3254 Builder.defineMacro("__AVX__");
3256 Builder.defineMacro("__SSE4_2__");
3258 Builder.defineMacro("__SSE4_1__");
3260 Builder.defineMacro("__SSSE3__");
3262 Builder.defineMacro("__SSE3__");
3264 Builder.defineMacro("__SSE2__");
3265 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
3267 Builder.defineMacro("__SSE__");
3268 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
3273 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3283 Builder.defineMacro("_M_IX86_FP", Twine(2));
3286 Builder.defineMacro("_M_IX86_FP", Twine(1));
3289 Builder.defineMacro("_M_IX86_FP", Twine(0));
3293 // Each case falls through to the previous one here.
3294 switch (MMX3DNowLevel) {
3295 case AMD3DNowAthlon:
3296 Builder.defineMacro("__3dNOW_A__");
3298 Builder.defineMacro("__3dNOW__");
3300 Builder.defineMacro("__MMX__");
3305 if (CPU >= CK_i486) {
3306 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3307 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3308 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3311 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3314 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3315 return llvm::StringSwitch<bool>(Feature)
3316 .Case("aes", HasAES)
3317 .Case("avx", SSELevel >= AVX)
3318 .Case("avx2", SSELevel >= AVX2)
3319 .Case("avx512f", SSELevel >= AVX512F)
3320 .Case("avx512cd", HasAVX512CD)
3321 .Case("avx512er", HasAVX512ER)
3322 .Case("avx512pf", HasAVX512PF)
3323 .Case("avx512dq", HasAVX512DQ)
3324 .Case("avx512bw", HasAVX512BW)
3325 .Case("avx512vl", HasAVX512VL)
3326 .Case("bmi", HasBMI)
3327 .Case("bmi2", HasBMI2)
3328 .Case("cx16", HasCX16)
3329 .Case("f16c", HasF16C)
3330 .Case("fma", HasFMA)
3331 .Case("fma4", XOPLevel >= FMA4)
3332 .Case("fsgsbase", HasFSGSBASE)
3333 .Case("lzcnt", HasLZCNT)
3334 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3335 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3336 .Case("mmx", MMX3DNowLevel >= MMX)
3337 .Case("pclmul", HasPCLMUL)
3338 .Case("popcnt", HasPOPCNT)
3339 .Case("prfchw", HasPRFCHW)
3340 .Case("rdrnd", HasRDRND)
3341 .Case("rdseed", HasRDSEED)
3342 .Case("rtm", HasRTM)
3343 .Case("sha", HasSHA)
3344 .Case("sse", SSELevel >= SSE1)
3345 .Case("sse2", SSELevel >= SSE2)
3346 .Case("sse3", SSELevel >= SSE3)
3347 .Case("ssse3", SSELevel >= SSSE3)
3348 .Case("sse4.1", SSELevel >= SSE41)
3349 .Case("sse4.2", SSELevel >= SSE42)
3350 .Case("sse4a", XOPLevel >= SSE4A)
3351 .Case("tbm", HasTBM)
3353 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3354 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3355 .Case("xop", XOPLevel >= XOP)
3359 // We can't use a generic validation scheme for the features accepted here
3360 // versus subtarget features accepted in the target attribute because the
3361 // bitfield structure that's initialized in the runtime only supports the
3362 // below currently rather than the full range of subtarget features. (See
3363 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
3364 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
3365 return llvm::StringSwitch<bool>(FeatureStr)
3368 .Case("popcnt", true)
3372 .Case("sse4.1", true)
3373 .Case("sse4.2", true)
3376 .Case("sse4a", true)
3380 .Case("avx512f", true)
3387 X86TargetInfo::validateAsmConstraint(const char *&Name,
3388 TargetInfo::ConstraintInfo &Info) const {
3390 default: return false;
3392 Info.setRequiresImmediate(0, 31);
3395 Info.setRequiresImmediate(0, 63);
3398 Info.setRequiresImmediate(-128, 127);
3401 // FIXME: properly analyze this constraint:
3402 // must be one of 0xff, 0xffff, or 0xffffffff
3405 Info.setRequiresImmediate(0, 3);
3408 Info.setRequiresImmediate(0, 255);
3411 Info.setRequiresImmediate(0, 127);
3413 case 'Y': // first letter of a pair:
3414 switch (*(Name+1)) {
3415 default: return false;
3416 case '0': // First SSE register.
3417 case 't': // Any SSE register, when SSE2 is enabled.
3418 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
3419 case 'm': // any MMX register, when inter-unit moves enabled.
3420 break; // falls through to setAllowsRegister.
3422 case 'f': // any x87 floating point stack register.
3423 // Constraint 'f' cannot be used for output operands.
3424 if (Info.ConstraintStr[0] == '=')
3427 Info.setAllowsRegister();
3435 case 'A': // edx:eax.
3436 case 't': // top of floating point stack.
3437 case 'u': // second from top of floating point stack.
3438 case 'q': // Any register accessible as [r]l: a, b, c, and d.
3439 case 'y': // Any MMX register.
3440 case 'x': // Any SSE register.
3441 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3442 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3443 case 'l': // "Index" registers: any general register that can be used as an
3444 // index in a base+index memory access.
3445 Info.setAllowsRegister();
3447 case 'C': // SSE floating point constant.
3448 case 'G': // x87 floating point constant.
3449 case 'e': // 32-bit signed integer constant for use with zero-extending
3450 // x86_64 instructions.
3451 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3452 // x86_64 instructions.
3457 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3458 unsigned Size) const {
3459 // Strip off constraint modifiers.
3460 while (Constraint[0] == '=' ||
3461 Constraint[0] == '+' ||
3462 Constraint[0] == '&')
3463 Constraint = Constraint.substr(1);
3465 return validateOperandSize(Constraint, Size);
3468 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3469 unsigned Size) const {
3470 return validateOperandSize(Constraint, Size);
3473 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3474 unsigned Size) const {
3475 switch (Constraint[0]) {
3484 // 256-bit ymm registers can be used if target supports AVX.
3485 return Size <= (SSELevel >= AVX ? 256U : 128U);
3492 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3493 switch (*Constraint) {
3494 case 'a': return std::string("{ax}");
3495 case 'b': return std::string("{bx}");
3496 case 'c': return std::string("{cx}");
3497 case 'd': return std::string("{dx}");
3498 case 'S': return std::string("{si}");
3499 case 'D': return std::string("{di}");
3500 case 'p': // address
3501 return std::string("im");
3502 case 't': // top of floating point stack.
3503 return std::string("{st}");
3504 case 'u': // second from top of floating point stack.
3505 return std::string("{st(1)}"); // second from top of floating point stack.
3507 return std::string(1, *Constraint);
3511 // X86-32 generic target
3512 class X86_32TargetInfo : public X86TargetInfo {
3514 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3515 DoubleAlign = LongLongAlign = 32;
3516 LongDoubleWidth = 96;
3517 LongDoubleAlign = 32;
3518 SuitableAlign = 128;
3519 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3520 SizeType = UnsignedInt;
3521 PtrDiffType = SignedInt;
3522 IntPtrType = SignedInt;
3525 // Use fpret for all types.
3526 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3527 (1 << TargetInfo::Double) |
3528 (1 << TargetInfo::LongDouble));
3530 // x86-32 has atomics up to 8 bytes
3531 // FIXME: Check that we actually have cmpxchg8b before setting
3532 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3533 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3535 BuiltinVaListKind getBuiltinVaListKind() const override {
3536 return TargetInfo::CharPtrBuiltinVaList;
3539 int getEHDataRegisterNumber(unsigned RegNo) const override {
3540 if (RegNo == 0) return 0;
3541 if (RegNo == 1) return 2;
3544 bool validateOperandSize(StringRef Constraint,
3545 unsigned Size) const override {
3546 switch (Constraint[0]) {
3562 return X86TargetInfo::validateOperandSize(Constraint, Size);
3566 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3568 NetBSDI386TargetInfo(const llvm::Triple &Triple)
3569 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3571 unsigned getFloatEvalMethod() const override {
3572 unsigned Major, Minor, Micro;
3573 getTriple().getOSVersion(Major, Minor, Micro);
3574 // New NetBSD uses the default rounding mode.
3575 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3576 return X86_32TargetInfo::getFloatEvalMethod();
3577 // NetBSD before 6.99.26 defaults to "double" rounding.
3582 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3584 OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3585 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3586 SizeType = UnsignedLong;
3587 IntPtrType = SignedLong;
3588 PtrDiffType = SignedLong;
3592 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3594 BitrigI386TargetInfo(const llvm::Triple &Triple)
3595 : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3596 SizeType = UnsignedLong;
3597 IntPtrType = SignedLong;
3598 PtrDiffType = SignedLong;
3602 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3604 DarwinI386TargetInfo(const llvm::Triple &Triple)
3605 : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3606 LongDoubleWidth = 128;
3607 LongDoubleAlign = 128;
3608 SuitableAlign = 128;
3609 MaxVectorAlign = 256;
3610 SizeType = UnsignedLong;
3611 IntPtrType = SignedLong;
3612 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3613 HasAlignMac68kSupport = true;
3618 // x86-32 Windows target
3619 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3621 WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3622 : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3623 WCharType = UnsignedShort;
3624 DoubleAlign = LongLongAlign = 64;
3626 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3627 DescriptionString = IsWinCOFF
3628 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
3629 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3631 void getTargetDefines(const LangOptions &Opts,
3632 MacroBuilder &Builder) const override {
3633 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3637 // x86-32 Windows Visual Studio target
3638 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3640 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3641 : WindowsX86_32TargetInfo(Triple) {
3642 LongDoubleWidth = LongDoubleAlign = 64;
3643 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3645 void getTargetDefines(const LangOptions &Opts,
3646 MacroBuilder &Builder) const override {
3647 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3648 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3649 // The value of the following reflects processor type.
3650 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3651 // We lost the original triple, so we use the default.
3652 Builder.defineMacro("_M_IX86", "600");
3655 } // end anonymous namespace
3657 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3658 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang supports
3659 // __declspec natively under -fms-extensions, but we define a no-op __declspec
3660 // macro anyway for pre-processor compatibility.
3661 if (Opts.MicrosoftExt)
3662 Builder.defineMacro("__declspec", "__declspec");
3664 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3666 if (!Opts.MicrosoftExt) {
3667 // Provide macros for all the calling convention keywords. Provide both
3668 // single and double underscore prefixed variants. These are available on
3669 // x64 as well as x86, even though they have no effect.
3670 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3671 for (const char *CC : CCs) {
3672 std::string GCCSpelling = "__attribute__((__";
3674 GCCSpelling += "__))";
3675 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3676 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3681 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3682 Builder.defineMacro("__MSVCRT__");
3683 Builder.defineMacro("__MINGW32__");
3684 addCygMingDefines(Opts, Builder);
3688 // x86-32 MinGW target
3689 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3691 MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3692 : WindowsX86_32TargetInfo(Triple) {}
3693 void getTargetDefines(const LangOptions &Opts,
3694 MacroBuilder &Builder) const override {
3695 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3696 DefineStd(Builder, "WIN32", Opts);
3697 DefineStd(Builder, "WINNT", Opts);
3698 Builder.defineMacro("_X86_");
3699 addMinGWDefines(Opts, Builder);
3703 // x86-32 Cygwin target
3704 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3706 CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3707 : X86_32TargetInfo(Triple) {
3708 TLSSupported = false;
3709 WCharType = UnsignedShort;
3710 DoubleAlign = LongLongAlign = 64;
3711 DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3713 void getTargetDefines(const LangOptions &Opts,
3714 MacroBuilder &Builder) const override {
3715 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3716 Builder.defineMacro("_X86_");
3717 Builder.defineMacro("__CYGWIN__");
3718 Builder.defineMacro("__CYGWIN32__");
3719 addCygMingDefines(Opts, Builder);
3720 DefineStd(Builder, "unix", Opts);
3722 Builder.defineMacro("_GNU_SOURCE");
3726 // x86-32 Haiku target
3727 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3729 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3730 SizeType = UnsignedLong;
3731 IntPtrType = SignedLong;
3732 PtrDiffType = SignedLong;
3733 ProcessIDType = SignedLong;
3734 this->UserLabelPrefix = "";
3735 this->TLSSupported = false;
3737 void getTargetDefines(const LangOptions &Opts,
3738 MacroBuilder &Builder) const override {
3739 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3740 Builder.defineMacro("__INTEL__");
3741 Builder.defineMacro("__HAIKU__");
3746 template<typename Target>
3747 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3749 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3750 MacroBuilder &Builder) const override {
3751 // RTEMS defines; list based off of gcc output
3753 Builder.defineMacro("__rtems__");
3754 Builder.defineMacro("__ELF__");
3758 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3759 this->UserLabelPrefix = "";
3761 switch (Triple.getArch()) {
3763 case llvm::Triple::x86:
3764 // this->MCountName = ".mcount";
3766 case llvm::Triple::mips:
3767 case llvm::Triple::mipsel:
3768 case llvm::Triple::ppc:
3769 case llvm::Triple::ppc64:
3770 case llvm::Triple::ppc64le:
3771 // this->MCountName = "_mcount";
3773 case llvm::Triple::arm:
3774 // this->MCountName = "__mcount";
3780 // x86-32 RTEMS target
3781 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3783 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3784 SizeType = UnsignedLong;
3785 IntPtrType = SignedLong;
3786 PtrDiffType = SignedLong;
3787 this->UserLabelPrefix = "";
3789 void getTargetDefines(const LangOptions &Opts,
3790 MacroBuilder &Builder) const override {
3791 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3792 Builder.defineMacro("__INTEL__");
3793 Builder.defineMacro("__rtems__");
3797 // x86-64 generic target
3798 class X86_64TargetInfo : public X86TargetInfo {
3800 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3801 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3803 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3804 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3805 LongDoubleWidth = 128;
3806 LongDoubleAlign = 128;
3807 LargeArrayMinWidth = 128;
3808 LargeArrayAlign = 128;
3809 SuitableAlign = 128;
3810 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
3811 PtrDiffType = IsX32 ? SignedInt : SignedLong;
3812 IntPtrType = IsX32 ? SignedInt : SignedLong;
3813 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
3814 Int64Type = IsX32 ? SignedLongLong : SignedLong;
3817 // Pointers are 32-bit in x32.
3818 DescriptionString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3820 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
3821 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3823 // Use fpret only for long double.
3824 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3826 // Use fp2ret for _Complex long double.
3827 ComplexLongDoubleUsesFP2Ret = true;
3829 // x86-64 has atomics up to 16 bytes.
3830 MaxAtomicPromoteWidth = 128;
3831 MaxAtomicInlineWidth = 128;
3833 BuiltinVaListKind getBuiltinVaListKind() const override {
3834 return TargetInfo::X86_64ABIBuiltinVaList;
3837 int getEHDataRegisterNumber(unsigned RegNo) const override {
3838 if (RegNo == 0) return 0;
3839 if (RegNo == 1) return 1;
3843 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3844 return (CC == CC_C ||
3845 CC == CC_X86VectorCall ||
3846 CC == CC_IntelOclBicc ||
3847 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3850 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3854 // for x32 we need it here explicitly
3855 bool hasInt128Type() const override { return true; }
3858 // x86-64 Windows target
3859 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3861 WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3862 : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3863 WCharType = UnsignedShort;
3864 LongWidth = LongAlign = 32;
3865 DoubleAlign = LongLongAlign = 64;
3866 IntMaxType = SignedLongLong;
3867 Int64Type = SignedLongLong;
3868 SizeType = UnsignedLongLong;
3869 PtrDiffType = SignedLongLong;
3870 IntPtrType = SignedLongLong;
3871 this->UserLabelPrefix = "";
3874 void getTargetDefines(const LangOptions &Opts,
3875 MacroBuilder &Builder) const override {
3876 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3877 Builder.defineMacro("_WIN64");
3880 BuiltinVaListKind getBuiltinVaListKind() const override {
3881 return TargetInfo::CharPtrBuiltinVaList;
3884 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3887 case CC_X86ThisCall:
3888 case CC_X86FastCall:
3891 case CC_X86VectorCall:
3892 case CC_IntelOclBicc:
3896 return CCCR_Warning;
3901 // x86-64 Windows Visual Studio target
3902 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3904 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3905 : WindowsX86_64TargetInfo(Triple) {
3906 LongDoubleWidth = LongDoubleAlign = 64;
3907 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3909 void getTargetDefines(const LangOptions &Opts,
3910 MacroBuilder &Builder) const override {
3911 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3912 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3913 Builder.defineMacro("_M_X64");
3914 Builder.defineMacro("_M_AMD64");
3918 // x86-64 MinGW target
3919 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3921 MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3922 : WindowsX86_64TargetInfo(Triple) {}
3923 void getTargetDefines(const LangOptions &Opts,
3924 MacroBuilder &Builder) const override {
3925 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3926 DefineStd(Builder, "WIN64", Opts);
3927 Builder.defineMacro("__MINGW64__");
3928 addMinGWDefines(Opts, Builder);
3930 // GCC defines this macro when it is using __gxx_personality_seh0.
3931 if (!Opts.SjLjExceptions)
3932 Builder.defineMacro("__SEH__");
3936 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3938 DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3939 : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3940 Int64Type = SignedLongLong;
3941 MaxVectorAlign = 256;
3942 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3943 llvm::Triple T = llvm::Triple(Triple);
3945 UseSignedCharForObjCBool = false;
3946 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3950 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3952 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3953 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3954 IntMaxType = SignedLongLong;
3955 Int64Type = SignedLongLong;
3959 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3961 BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3962 : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3963 IntMaxType = SignedLongLong;
3964 Int64Type = SignedLongLong;
3968 class ARMTargetInfo : public TargetInfo {
3969 // Possible FPU choices.
3978 // Possible HWDiv features.
3980 HWDivThumb = (1 << 0),
3984 static bool FPUModeIsVFP(FPUMode Mode) {
3985 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3988 static const TargetInfo::GCCRegAlias GCCRegAliases[];
3989 static const char * const GCCRegNames[];
3991 std::string ABI, CPU;
4001 unsigned ArchProfile;
4002 unsigned ArchVersion;
4006 unsigned ShouldUseInlineAtomic : 1;
4007 unsigned IsAAPCS : 1;
4008 unsigned IsThumb : 1;
4011 // Initialized via features.
4012 unsigned SoftFloat : 1;
4013 unsigned SoftFloatABI : 1;
4016 unsigned Crypto : 1;
4018 // ACLE 6.5.1 Hardware floating point
4020 HW_FP_HP = (1 << 1), /// half (16-bit)
4021 HW_FP_SP = (1 << 2), /// single (32-bit)
4022 HW_FP_DP = (1 << 3), /// double (64-bit)
4026 static const Builtin::Info BuiltinInfo[];
4028 void setABIAAPCS() {
4031 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4032 const llvm::Triple &T = getTriple();
4034 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig.
4035 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
4036 T.getOS() == llvm::Triple::Bitrig)
4037 SizeType = UnsignedLong;
4039 SizeType = UnsignedInt;
4041 switch (T.getOS()) {
4042 case llvm::Triple::NetBSD:
4043 WCharType = SignedInt;
4045 case llvm::Triple::Win32:
4046 WCharType = UnsignedShort;
4048 case llvm::Triple::Linux:
4050 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
4051 WCharType = UnsignedInt;
4055 UseBitFieldTypeAlignment = true;
4057 ZeroLengthBitfieldBoundary = 0;
4059 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
4060 // so set preferred for small types to 32.
4061 if (T.isOSBinFormatMachO()) {
4063 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4064 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4065 } else if (T.isOSWindows()) {
4066 assert(!BigEndian && "Windows on ARM does not support big endian");
4067 DescriptionString = "e"
4075 } else if (T.isOSNaCl()) {
4076 assert(!BigEndian && "NaCl on ARM does not support big endian");
4077 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
4080 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4081 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4084 // FIXME: Enumerated types are variable width in straight AAPCS.
4088 const llvm::Triple &T = getTriple();
4092 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
4094 // size_t is unsigned int on FreeBSD.
4095 if (T.getOS() == llvm::Triple::FreeBSD)
4096 SizeType = UnsignedInt;
4098 SizeType = UnsignedLong;
4100 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
4101 WCharType = SignedInt;
4103 // Do not respect the alignment of bit-field types when laying out
4104 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
4105 UseBitFieldTypeAlignment = false;
4107 /// gcc forces the alignment to 4 bytes, regardless of the type of the
4108 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
4110 ZeroLengthBitfieldBoundary = 32;
4112 if (T.isOSBinFormatMachO())
4115 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4116 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4120 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4121 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4123 // FIXME: Override "preferred align" for double and long long.
4126 void setArchInfo(StringRef ArchName) {
4127 ArchISA = llvm::ARMTargetParser::parseArchISA(ArchName);
4128 ArchKind = llvm::ARMTargetParser::parseArch(ArchName);
4129 ArchProfile = llvm::ARMTargetParser::parseArchProfile(ArchName);
4130 ArchVersion = llvm::ARMTargetParser::parseArchVersion(ArchName);
4134 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4135 if (ArchProfile == llvm::ARM::PK_M) {
4136 MaxAtomicPromoteWidth = 32;
4137 if (ShouldUseInlineAtomic)
4138 MaxAtomicInlineWidth = 32;
4141 MaxAtomicPromoteWidth = 64;
4142 if (ShouldUseInlineAtomic)
4143 MaxAtomicInlineWidth = 64;
4148 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
4149 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
4150 IsAAPCS(true), HW_FP(0) {
4151 BigEndian = IsBigEndian;
4153 switch (getTriple().getOS()) {
4154 case llvm::Triple::NetBSD:
4155 PtrDiffType = SignedLong;
4158 PtrDiffType = SignedInt;
4162 // if subArch is not specified Arc Info is based on the default CPU
4163 if (Triple.getSubArch() == llvm::Triple::SubArchType::NoSubArch) {
4164 unsigned ArchKind = llvm::ARMTargetParser::parseCPUArch(CPU);
4165 setArchInfo(llvm::ARMTargetParser::getArchName(ArchKind));
4166 ShouldUseInlineAtomic = false;
4169 setArchInfo(Triple.getArchName());
4170 // FIXME: Should't this be updated also when calling setCPU() ?
4171 // Doing so currently causes regressions
4172 ShouldUseInlineAtomic = (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) ||
4173 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
4176 // {} in inline assembly are neon specifiers, not assembly variant
4178 NoAsmVariants = true;
4180 // FIXME: Should't this be updated also when calling setCPU() ?
4181 // Doing so currently causes regressions
4182 IsThumb = (ArchISA == llvm::ARM::IK_THUMB);
4184 // FIXME: This duplicates code from the driver that sets the -target-abi
4185 // option - this code is used if -target-abi isn't passed and should
4186 // be unified in some way.
4187 if (Triple.isOSBinFormatMachO()) {
4188 // The backend is hardwired to assume AAPCS for M-class processors, ensure
4189 // the frontend matches that.
4190 if (Triple.getEnvironment() == llvm::Triple::EABI ||
4191 Triple.getOS() == llvm::Triple::UnknownOS ||
4192 StringRef(CPU).startswith("cortex-m")) {
4197 } else if (Triple.isOSWindows()) {
4198 // FIXME: this is invalid for WindowsCE
4201 // Select the default based on the platform.
4202 switch (Triple.getEnvironment()) {
4203 case llvm::Triple::Android:
4204 case llvm::Triple::GNUEABI:
4205 case llvm::Triple::GNUEABIHF:
4206 setABI("aapcs-linux");
4208 case llvm::Triple::EABIHF:
4209 case llvm::Triple::EABI:
4212 case llvm::Triple::GNU:
4216 if (Triple.getOS() == llvm::Triple::NetBSD)
4224 // ARM targets default to using the ARM C++ ABI.
4225 TheCXXABI.set(TargetCXXABI::GenericARM);
4229 // Do force alignment of members that follow zero length bitfields. If
4230 // the alignment of the zero-length bitfield is greater than the member
4231 // that follows it, `bar', `bar' will be aligned as the type of the
4232 // zero length bitfield.
4233 UseZeroLengthBitfieldAlignment = true;
4236 StringRef getABI() const override { return ABI; }
4238 bool setABI(const std::string &Name) override {
4241 // The defaults (above) are for AAPCS, check if we need to change them.
4243 // FIXME: We need support for -meabi... we could just mangle it into the
4245 if (Name == "apcs-gnu") {
4249 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
4256 // FIXME: This should be based on Arch attributes, not CPU names.
4257 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
4258 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
4259 Features["vfp2"] = true;
4260 else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
4261 Features["vfp3"] = true;
4262 Features["neon"] = true;
4264 else if (CPU == "cortex-a5") {
4265 Features["vfp4"] = true;
4266 Features["neon"] = true;
4267 } else if (CPU == "swift" || CPU == "cortex-a7" ||
4268 CPU == "cortex-a12" || CPU == "cortex-a15" ||
4269 CPU == "cortex-a17" || CPU == "krait") {
4270 Features["vfp4"] = true;
4271 Features["neon"] = true;
4272 Features["hwdiv"] = true;
4273 Features["hwdiv-arm"] = true;
4274 } else if (CPU == "cyclone" || CPU == "cortex-a53" || CPU == "cortex-a57" ||
4275 CPU == "cortex-a72") {
4276 Features["fp-armv8"] = true;
4277 Features["neon"] = true;
4278 Features["hwdiv"] = true;
4279 Features["hwdiv-arm"] = true;
4280 Features["crc"] = true;
4281 Features["crypto"] = true;
4282 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || ArchVersion == 8) {
4283 Features["hwdiv"] = true;
4284 Features["hwdiv-arm"] = true;
4285 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" ||
4286 CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") {
4287 Features["hwdiv"] = true;
4291 bool handleTargetFeatures(std::vector<std::string> &Features,
4292 DiagnosticsEngine &Diags) override {
4296 SoftFloat = SoftFloatABI = false;
4299 // This does not diagnose illegal cases like having both
4300 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
4301 uint32_t HW_FP_remove = 0;
4302 for (const auto &Feature : Features) {
4303 if (Feature == "+soft-float") {
4305 } else if (Feature == "+soft-float-abi") {
4306 SoftFloatABI = true;
4307 } else if (Feature == "+vfp2") {
4309 HW_FP |= HW_FP_SP | HW_FP_DP;
4310 } else if (Feature == "+vfp3") {
4312 HW_FP |= HW_FP_SP | HW_FP_DP;
4313 } else if (Feature == "+vfp4") {
4315 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
4316 } else if (Feature == "+fp-armv8") {
4318 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
4319 } else if (Feature == "+neon") {
4321 HW_FP |= HW_FP_SP | HW_FP_DP;
4322 } else if (Feature == "+hwdiv") {
4323 HWDiv |= HWDivThumb;
4324 } else if (Feature == "+hwdiv-arm") {
4326 } else if (Feature == "+crc") {
4328 } else if (Feature == "+crypto") {
4330 } else if (Feature == "+fp-only-sp") {
4331 HW_FP_remove |= HW_FP_DP | HW_FP_HP;
4334 HW_FP &= ~HW_FP_remove;
4336 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4337 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4341 if (FPMath == FP_Neon)
4342 Features.push_back("+neonfp");
4343 else if (FPMath == FP_VFP)
4344 Features.push_back("-neonfp");
4346 // Remove front-end specific options which the backend handles differently.
4348 std::find(Features.begin(), Features.end(), "+soft-float-abi");
4349 if (Feature != Features.end())
4350 Features.erase(Feature);
4355 bool hasFeature(StringRef Feature) const override {
4356 return llvm::StringSwitch<bool>(Feature)
4358 .Case("softfloat", SoftFloat)
4359 .Case("thumb", IsThumb)
4360 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4361 .Case("hwdiv", HWDiv & HWDivThumb)
4362 .Case("hwdiv-arm", HWDiv & HWDivARM)
4365 const char *getCPUAttr() const {
4366 const char *CPUAttr;
4367 // For most sub-arches, the build attribute CPU name is enough.
4368 // For Cortex variants, it's slightly different.
4371 CPUAttr = llvm::ARMTargetParser::getCPUAttr(ArchKind);
4372 return CPUAttr ? CPUAttr : "" ;
4373 case llvm::ARM::AK_ARMV6M:
4374 case llvm::ARM::AK_ARMV6SM:
4376 case llvm::ARM::AK_ARMV7:
4377 case llvm::ARM::AK_ARMV7A:
4378 case llvm::ARM::AK_ARMV7S:
4380 case llvm::ARM::AK_ARMV7R:
4382 case llvm::ARM::AK_ARMV7M:
4384 case llvm::ARM::AK_ARMV7EM:
4386 case llvm::ARM::AK_ARMV8A:
4388 case llvm::ARM::AK_ARMV8_1A:
4392 const char *getCPUProfile() const {
4393 switch(ArchProfile) {
4394 case llvm::ARM::PK_A:
4396 case llvm::ARM::PK_R:
4398 case llvm::ARM::PK_M:
4404 bool setCPU(const std::string &Name) override {
4405 unsigned ArchKind = llvm::ARMTargetParser::parseCPUArch(Name);
4406 if (ArchKind == llvm::ARM::AK_INVALID)
4408 setArchInfo(llvm::ARMTargetParser::getArchName(ArchKind));
4413 bool setFPMath(StringRef Name) override;
4414 bool supportsThumb(StringRef CPUAttr) const {
4415 return CPUAttr.count('T') || ArchVersion >= 6;
4417 bool supportsThumb2(StringRef CPUAttr) const {
4418 return CPUAttr.equals("6T2") || ArchVersion >= 7;
4420 void getTargetDefines(const LangOptions &Opts,
4421 MacroBuilder &Builder) const override {
4422 StringRef CPUAttr = getCPUAttr();
4423 StringRef CPUProfile = getCPUProfile();
4425 // Target identification.
4426 Builder.defineMacro("__arm");
4427 Builder.defineMacro("__arm__");
4429 // Target properties.
4430 Builder.defineMacro("__REGISTER_PREFIX__", "");
4432 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
4434 // ACLE 6.4.1 ARM/Thumb instruction set architecture
4435 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4436 Builder.defineMacro("__ARM_ARCH", std::to_string(ArchVersion));
4437 if (ArchVersion >= 8) {
4438 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4439 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4442 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
4443 // is not defined for the M-profile.
4444 // NOTE that the deffault profile is assumed to be 'A'
4445 if (CPUProfile.empty() || CPUProfile != "M")
4446 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4448 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4449 // Thumb ISA (including v6-M). It is set to 2 if the core supports the
4450 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4451 if (supportsThumb2(CPUAttr))
4452 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4453 else if (supportsThumb(CPUAttr))
4454 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4456 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4457 // instruction set such as ARM or Thumb.
4458 Builder.defineMacro("__ARM_32BIT_STATE", "1");
4460 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4462 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4463 if (!CPUProfile.empty())
4464 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4466 // ACLE 6.5.1 Hardware Floating Point
4468 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4471 Builder.defineMacro("__ARM_ACLE", "200");
4473 // Subtarget options.
4475 // FIXME: It's more complicated than this and we don't really support
4477 // Windows on ARM does not "support" interworking
4478 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows())
4479 Builder.defineMacro("__THUMB_INTERWORK__");
4481 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4482 // Embedded targets on Darwin follow AAPCS, but not EABI.
4483 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4484 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4485 Builder.defineMacro("__ARM_EABI__");
4486 Builder.defineMacro("__ARM_PCS", "1");
4488 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4489 Builder.defineMacro("__ARM_PCS_VFP", "1");
4493 Builder.defineMacro("__SOFTFP__");
4495 if (CPU == "xscale")
4496 Builder.defineMacro("__XSCALE__");
4499 Builder.defineMacro("__THUMBEL__");
4500 Builder.defineMacro("__thumb__");
4501 if (supportsThumb2(CPUAttr))
4502 Builder.defineMacro("__thumb2__");
4504 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4505 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4507 // Note, this is always on in gcc, even though it doesn't make sense.
4508 Builder.defineMacro("__APCS_32__");
4510 if (FPUModeIsVFP((FPUMode) FPU)) {
4511 Builder.defineMacro("__VFP_FP__");
4513 Builder.defineMacro("__ARM_VFPV2__");
4515 Builder.defineMacro("__ARM_VFPV3__");
4517 Builder.defineMacro("__ARM_VFPV4__");
4520 // This only gets set when Neon instructions are actually available, unlike
4521 // the VFP define, hence the soft float and arch check. This is subtly
4522 // different from gcc, we follow the intent which was that it should be set
4523 // when Neon instructions are actually available.
4524 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
4525 Builder.defineMacro("__ARM_NEON");
4526 Builder.defineMacro("__ARM_NEON__");
4529 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4530 Opts.ShortWChar ? "2" : "4");
4532 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4533 Opts.ShortEnums ? "1" : "4");
4536 Builder.defineMacro("__ARM_FEATURE_CRC32");
4539 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4541 if (ArchVersion >= 6 && CPUAttr != "6M") {
4542 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4543 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4544 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4545 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4548 bool is5EOrAbove = (ArchVersion >= 6 ||
4549 (ArchVersion == 5 && CPUAttr.count('E')));
4550 // FIXME: We are not getting all 32-bit ARM architectures
4551 bool is32Bit = (!IsThumb || supportsThumb2(CPUAttr));
4552 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUAttr == "7EM"))
4553 Builder.defineMacro("__ARM_FEATURE_DSP");
4555 void getTargetBuiltins(const Builtin::Info *&Records,
4556 unsigned &NumRecords) const override {
4557 Records = BuiltinInfo;
4558 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4560 bool isCLZForZeroUndef() const override { return false; }
4561 BuiltinVaListKind getBuiltinVaListKind() const override {
4562 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4564 void getGCCRegNames(const char * const *&Names,
4565 unsigned &NumNames) const override;
4566 void getGCCRegAliases(const GCCRegAlias *&Aliases,
4567 unsigned &NumAliases) const override;
4568 bool validateAsmConstraint(const char *&Name,
4569 TargetInfo::ConstraintInfo &Info) const override {
4574 case 'w': // VFP Floating point register single precision
4575 case 'P': // VFP Floating point register double precision
4576 Info.setAllowsRegister();
4585 case 'Q': // A memory address that is a single base register.
4586 Info.setAllowsMemory();
4588 case 'U': // a memory reference...
4590 case 'q': // ...ARMV4 ldrsb
4591 case 'v': // ...VFP load/store (reg+constant offset)
4592 case 'y': // ...iWMMXt load/store
4593 case 't': // address valid for load/store opaque types wider
4595 case 'n': // valid address for Neon doubleword vector load/store
4596 case 'm': // valid address for Neon element and structure load/store
4597 case 's': // valid address for non-offset loads/stores of quad-word
4598 // values in four ARM registers
4599 Info.setAllowsMemory();
4606 std::string convertConstraint(const char *&Constraint) const override {
4608 switch (*Constraint) {
4609 case 'U': // Two-character constraint; add "^" hint for later parsing.
4610 R = std::string("^") + std::string(Constraint, 2);
4613 case 'p': // 'p' should be translated to 'r' by default.
4614 R = std::string("r");
4617 return std::string(1, *Constraint);
4622 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4623 std::string &SuggestedModifier) const override {
4624 bool isOutput = (Constraint[0] == '=');
4625 bool isInOut = (Constraint[0] == '+');
4627 // Strip off constraint modifiers.
4628 while (Constraint[0] == '=' ||
4629 Constraint[0] == '+' ||
4630 Constraint[0] == '&')
4631 Constraint = Constraint.substr(1);
4633 switch (Constraint[0]) {
4638 return (isInOut || isOutput || Size <= 64);
4640 // A register of size 32 cannot fit a vector type.
4648 const char *getClobbers() const override {
4649 // FIXME: Is this really right?
4653 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4654 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4657 int getEHDataRegisterNumber(unsigned RegNo) const override {
4658 if (RegNo == 0) return 0;
4659 if (RegNo == 1) return 1;
4664 bool ARMTargetInfo::setFPMath(StringRef Name) {
4665 if (Name == "neon") {
4668 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4676 const char * const ARMTargetInfo::GCCRegNames[] = {
4677 // Integer registers
4678 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4679 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4682 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4683 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4684 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4685 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4688 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4689 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4690 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4691 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4694 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4695 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4698 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4699 unsigned &NumNames) const {
4700 Names = GCCRegNames;
4701 NumNames = llvm::array_lengthof(GCCRegNames);
4704 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4714 { { "v6", "rfp" }, "r9" },
4715 { { "sl" }, "r10" },
4716 { { "fp" }, "r11" },
4717 { { "ip" }, "r12" },
4718 { { "r13" }, "sp" },
4719 { { "r14" }, "lr" },
4720 { { "r15" }, "pc" },
4721 // The S, D and Q registers overlap, but aren't really aliases; we
4722 // don't want to substitute one of these for a different-sized one.
4725 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4726 unsigned &NumAliases) const {
4727 Aliases = GCCRegAliases;
4728 NumAliases = llvm::array_lengthof(GCCRegAliases);
4731 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4732 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4733 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4735 #include "clang/Basic/BuiltinsNEON.def"
4737 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4738 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4739 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4741 #include "clang/Basic/BuiltinsARM.def"
4744 class ARMleTargetInfo : public ARMTargetInfo {
4746 ARMleTargetInfo(const llvm::Triple &Triple)
4747 : ARMTargetInfo(Triple, false) { }
4748 void getTargetDefines(const LangOptions &Opts,
4749 MacroBuilder &Builder) const override {
4750 Builder.defineMacro("__ARMEL__");
4751 ARMTargetInfo::getTargetDefines(Opts, Builder);
4755 class ARMbeTargetInfo : public ARMTargetInfo {
4757 ARMbeTargetInfo(const llvm::Triple &Triple)
4758 : ARMTargetInfo(Triple, true) { }
4759 void getTargetDefines(const LangOptions &Opts,
4760 MacroBuilder &Builder) const override {
4761 Builder.defineMacro("__ARMEB__");
4762 Builder.defineMacro("__ARM_BIG_ENDIAN");
4763 ARMTargetInfo::getTargetDefines(Opts, Builder);
4767 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4768 const llvm::Triple Triple;
4770 WindowsARMTargetInfo(const llvm::Triple &Triple)
4771 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4772 TLSSupported = false;
4773 WCharType = UnsignedShort;
4774 SizeType = UnsignedInt;
4775 UserLabelPrefix = "";
4777 void getVisualStudioDefines(const LangOptions &Opts,
4778 MacroBuilder &Builder) const {
4779 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4781 // FIXME: this is invalid for WindowsCE
4782 Builder.defineMacro("_M_ARM_NT", "1");
4783 Builder.defineMacro("_M_ARMT", "_M_ARM");
4784 Builder.defineMacro("_M_THUMB", "_M_ARM");
4786 assert((Triple.getArch() == llvm::Triple::arm ||
4787 Triple.getArch() == llvm::Triple::thumb) &&
4788 "invalid architecture for Windows ARM target info");
4789 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4790 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4792 // TODO map the complete set of values
4793 // 31: VFPv3 40: VFPv4
4794 Builder.defineMacro("_M_ARM_FP", "31");
4796 BuiltinVaListKind getBuiltinVaListKind() const override {
4797 return TargetInfo::CharPtrBuiltinVaList;
4801 // Windows ARM + Itanium C++ ABI Target
4802 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4804 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4805 : WindowsARMTargetInfo(Triple) {
4806 TheCXXABI.set(TargetCXXABI::GenericARM);
4809 void getTargetDefines(const LangOptions &Opts,
4810 MacroBuilder &Builder) const override {
4811 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4813 if (Opts.MSVCCompat)
4814 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4818 // Windows ARM, MS (C++) ABI
4819 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4821 MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4822 : WindowsARMTargetInfo(Triple) {
4823 TheCXXABI.set(TargetCXXABI::Microsoft);
4826 void getTargetDefines(const LangOptions &Opts,
4827 MacroBuilder &Builder) const override {
4828 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4829 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4833 class DarwinARMTargetInfo :
4834 public DarwinTargetInfo<ARMleTargetInfo> {
4836 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4837 MacroBuilder &Builder) const override {
4838 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4842 DarwinARMTargetInfo(const llvm::Triple &Triple)
4843 : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4844 HasAlignMac68kSupport = true;
4845 // iOS always has 64-bit atomic instructions.
4846 // FIXME: This should be based off of the target features in
4848 MaxAtomicInlineWidth = 64;
4850 // Darwin on iOS uses a variant of the ARM C++ ABI.
4851 TheCXXABI.set(TargetCXXABI::iOS);
4855 class AArch64TargetInfo : public TargetInfo {
4856 virtual void setDescriptionString() = 0;
4857 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4858 static const char *const GCCRegNames[];
4869 static const Builtin::Info BuiltinInfo[];
4874 AArch64TargetInfo(const llvm::Triple &Triple)
4875 : TargetInfo(Triple), ABI("aapcs") {
4877 if (getTriple().getOS() == llvm::Triple::NetBSD) {
4878 WCharType = SignedInt;
4880 // NetBSD apparently prefers consistency across ARM targets to consistency
4881 // across 64-bit targets.
4882 Int64Type = SignedLongLong;
4883 IntMaxType = SignedLongLong;
4885 WCharType = UnsignedInt;
4886 Int64Type = SignedLong;
4887 IntMaxType = SignedLong;
4890 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4891 MaxVectorAlign = 128;
4893 MaxAtomicInlineWidth = 128;
4894 MaxAtomicPromoteWidth = 128;
4896 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
4897 LongDoubleFormat = &llvm::APFloat::IEEEquad;
4899 // {} in inline assembly are neon specifiers, not assembly variant
4901 NoAsmVariants = true;
4903 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
4904 // contributes to the alignment of the containing aggregate in the same way
4905 // a plain (non bit-field) member of that type would, without exception for
4906 // zero-sized or anonymous bit-fields."
4907 UseBitFieldTypeAlignment = true;
4908 UseZeroLengthBitfieldAlignment = true;
4910 // AArch64 targets default to using the ARM C++ ABI.
4911 TheCXXABI.set(TargetCXXABI::GenericAArch64);
4914 StringRef getABI() const override { return ABI; }
4915 bool setABI(const std::string &Name) override {
4916 if (Name != "aapcs" && Name != "darwinpcs")
4923 bool setCPU(const std::string &Name) override {
4924 bool CPUKnown = llvm::StringSwitch<bool>(Name)
4925 .Case("generic", true)
4926 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true)
4927 .Case("cyclone", true)
4932 void getTargetDefines(const LangOptions &Opts,
4933 MacroBuilder &Builder) const override {
4934 // Target identification.
4935 Builder.defineMacro("__aarch64__");
4937 // Target properties.
4938 Builder.defineMacro("_LP64");
4939 Builder.defineMacro("__LP64__");
4941 // ACLE predefines. Many can only have one possible value on v8 AArch64.
4942 Builder.defineMacro("__ARM_ACLE", "200");
4943 Builder.defineMacro("__ARM_ARCH", "8");
4944 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4946 Builder.defineMacro("__ARM_64BIT_STATE");
4947 Builder.defineMacro("__ARM_PCS_AAPCS64");
4948 Builder.defineMacro("__ARM_ARCH_ISA_A64");
4950 Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4951 Builder.defineMacro("__ARM_FEATURE_CLZ");
4952 Builder.defineMacro("__ARM_FEATURE_FMA");
4953 Builder.defineMacro("__ARM_FEATURE_DIV");
4954 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
4955 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
4956 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4957 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4959 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4961 // 0xe implies support for half, single and double precision operations.
4962 Builder.defineMacro("__ARM_FP", "0xe");
4964 // PCS specifies this for SysV variants, which is all we support. Other ABIs
4965 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4966 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4968 if (Opts.FastMath || Opts.FiniteMathOnly)
4969 Builder.defineMacro("__ARM_FP_FAST");
4971 if (Opts.C99 && !Opts.Freestanding)
4972 Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4974 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4976 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4977 Opts.ShortEnums ? "1" : "4");
4979 if (FPU == NeonMode) {
4980 Builder.defineMacro("__ARM_NEON");
4981 // 64-bit NEON supports half, single and double precision operations.
4982 Builder.defineMacro("__ARM_NEON_FP", "0xe");
4986 Builder.defineMacro("__ARM_FEATURE_CRC32");
4989 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4991 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
4992 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4993 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4994 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4995 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4998 void getTargetBuiltins(const Builtin::Info *&Records,
4999 unsigned &NumRecords) const override {
5000 Records = BuiltinInfo;
5001 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
5004 bool hasFeature(StringRef Feature) const override {
5005 return Feature == "aarch64" ||
5006 Feature == "arm64" ||
5007 (Feature == "neon" && FPU == NeonMode);
5010 bool handleTargetFeatures(std::vector<std::string> &Features,
5011 DiagnosticsEngine &Diags) override {
5015 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
5016 if (Features[i] == "+neon")
5018 if (Features[i] == "+crc")
5020 if (Features[i] == "+crypto")
5024 setDescriptionString();
5029 bool isCLZForZeroUndef() const override { return false; }
5031 BuiltinVaListKind getBuiltinVaListKind() const override {
5032 return TargetInfo::AArch64ABIBuiltinVaList;
5035 void getGCCRegNames(const char *const *&Names,
5036 unsigned &NumNames) const override;
5037 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5038 unsigned &NumAliases) const override;
5040 bool validateAsmConstraint(const char *&Name,
5041 TargetInfo::ConstraintInfo &Info) const override {
5045 case 'w': // Floating point and SIMD registers (V0-V31)
5046 Info.setAllowsRegister();
5048 case 'I': // Constant that can be used with an ADD instruction
5049 case 'J': // Constant that can be used with a SUB instruction
5050 case 'K': // Constant that can be used with a 32-bit logical instruction
5051 case 'L': // Constant that can be used with a 64-bit logical instruction
5052 case 'M': // Constant that can be used as a 32-bit MOV immediate
5053 case 'N': // Constant that can be used as a 64-bit MOV immediate
5054 case 'Y': // Floating point constant zero
5055 case 'Z': // Integer constant zero
5057 case 'Q': // A memory reference with base register and no offset
5058 Info.setAllowsMemory();
5060 case 'S': // A symbolic address
5061 Info.setAllowsRegister();
5064 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
5065 // Utf: A memory address suitable for ldp/stp in TF mode.
5066 // Usa: An absolute symbolic address.
5067 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
5068 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
5069 case 'z': // Zero register, wzr or xzr
5070 Info.setAllowsRegister();
5072 case 'x': // Floating point and SIMD registers (V0-V15)
5073 Info.setAllowsRegister();
5080 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5081 std::string &SuggestedModifier) const override {
5082 // Strip off constraint modifiers.
5083 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
5084 Constraint = Constraint.substr(1);
5086 switch (Constraint[0]) {
5094 // For now assume that the person knows what they're
5095 // doing with the modifier.
5098 // By default an 'r' constraint will be in the 'x'
5103 SuggestedModifier = "w";
5110 const char *getClobbers() const override { return ""; }
5112 int getEHDataRegisterNumber(unsigned RegNo) const override {
5121 const char *const AArch64TargetInfo::GCCRegNames[] = {
5122 // 32-bit Integer registers
5123 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
5124 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
5125 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
5127 // 64-bit Integer registers
5128 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
5129 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
5130 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
5132 // 32-bit floating point regsisters
5133 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
5134 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
5135 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5137 // 64-bit floating point regsisters
5138 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
5139 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
5140 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5143 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
5144 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
5145 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
5148 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
5149 unsigned &NumNames) const {
5150 Names = GCCRegNames;
5151 NumNames = llvm::array_lengthof(GCCRegNames);
5154 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
5155 { { "w31" }, "wsp" },
5156 { { "x29" }, "fp" },
5157 { { "x30" }, "lr" },
5158 { { "x31" }, "sp" },
5159 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
5160 // don't want to substitute one of these for a different-sized one.
5163 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5164 unsigned &NumAliases) const {
5165 Aliases = GCCRegAliases;
5166 NumAliases = llvm::array_lengthof(GCCRegAliases);
5169 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
5170 #define BUILTIN(ID, TYPE, ATTRS) \
5171 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5172 #include "clang/Basic/BuiltinsNEON.def"
5174 #define BUILTIN(ID, TYPE, ATTRS) \
5175 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5176 #include "clang/Basic/BuiltinsAArch64.def"
5179 class AArch64leTargetInfo : public AArch64TargetInfo {
5180 void setDescriptionString() override {
5181 if (getTriple().isOSBinFormatMachO())
5182 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
5184 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
5188 AArch64leTargetInfo(const llvm::Triple &Triple)
5189 : AArch64TargetInfo(Triple) {
5192 void getTargetDefines(const LangOptions &Opts,
5193 MacroBuilder &Builder) const override {
5194 Builder.defineMacro("__AARCH64EL__");
5195 AArch64TargetInfo::getTargetDefines(Opts, Builder);
5199 class AArch64beTargetInfo : public AArch64TargetInfo {
5200 void setDescriptionString() override {
5201 assert(!getTriple().isOSBinFormatMachO());
5202 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
5206 AArch64beTargetInfo(const llvm::Triple &Triple)
5207 : AArch64TargetInfo(Triple) { }
5208 void getTargetDefines(const LangOptions &Opts,
5209 MacroBuilder &Builder) const override {
5210 Builder.defineMacro("__AARCH64EB__");
5211 Builder.defineMacro("__AARCH_BIG_ENDIAN");
5212 Builder.defineMacro("__ARM_BIG_ENDIAN");
5213 AArch64TargetInfo::getTargetDefines(Opts, Builder);
5217 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
5219 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5220 MacroBuilder &Builder) const override {
5221 Builder.defineMacro("__AARCH64_SIMD__");
5222 Builder.defineMacro("__ARM64_ARCH_8__");
5223 Builder.defineMacro("__ARM_NEON__");
5224 Builder.defineMacro("__LITTLE_ENDIAN__");
5225 Builder.defineMacro("__REGISTER_PREFIX__", "");
5226 Builder.defineMacro("__arm64", "1");
5227 Builder.defineMacro("__arm64__", "1");
5229 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5233 DarwinAArch64TargetInfo(const llvm::Triple &Triple)
5234 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
5235 Int64Type = SignedLongLong;
5236 WCharType = SignedInt;
5237 UseSignedCharForObjCBool = false;
5239 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
5240 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5242 TheCXXABI.set(TargetCXXABI::iOS64);
5245 BuiltinVaListKind getBuiltinVaListKind() const override {
5246 return TargetInfo::CharPtrBuiltinVaList;
5250 // Hexagon abstract base class
5251 class HexagonTargetInfo : public TargetInfo {
5252 static const Builtin::Info BuiltinInfo[];
5253 static const char * const GCCRegNames[];
5254 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5257 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5259 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
5261 // {} in inline assembly are packet specifiers, not assembly variant
5263 NoAsmVariants = true;
5266 void getTargetBuiltins(const Builtin::Info *&Records,
5267 unsigned &NumRecords) const override {
5268 Records = BuiltinInfo;
5269 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
5272 bool validateAsmConstraint(const char *&Name,
5273 TargetInfo::ConstraintInfo &Info) const override {
5277 void getTargetDefines(const LangOptions &Opts,
5278 MacroBuilder &Builder) const override;
5280 bool hasFeature(StringRef Feature) const override {
5281 return Feature == "hexagon";
5284 BuiltinVaListKind getBuiltinVaListKind() const override {
5285 return TargetInfo::CharPtrBuiltinVaList;
5287 void getGCCRegNames(const char * const *&Names,
5288 unsigned &NumNames) const override;
5289 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5290 unsigned &NumAliases) const override;
5291 const char *getClobbers() const override {
5295 static const char *getHexagonCPUSuffix(StringRef Name) {
5296 return llvm::StringSwitch<const char*>(Name)
5297 .Case("hexagonv4", "4")
5298 .Case("hexagonv5", "5")
5302 bool setCPU(const std::string &Name) override {
5303 if (!getHexagonCPUSuffix(Name))
5311 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5312 MacroBuilder &Builder) const {
5313 Builder.defineMacro("qdsp6");
5314 Builder.defineMacro("__qdsp6", "1");
5315 Builder.defineMacro("__qdsp6__", "1");
5317 Builder.defineMacro("hexagon");
5318 Builder.defineMacro("__hexagon", "1");
5319 Builder.defineMacro("__hexagon__", "1");
5321 if(CPU == "hexagonv1") {
5322 Builder.defineMacro("__HEXAGON_V1__");
5323 Builder.defineMacro("__HEXAGON_ARCH__", "1");
5324 if(Opts.HexagonQdsp6Compat) {
5325 Builder.defineMacro("__QDSP6_V1__");
5326 Builder.defineMacro("__QDSP6_ARCH__", "1");
5329 else if(CPU == "hexagonv2") {
5330 Builder.defineMacro("__HEXAGON_V2__");
5331 Builder.defineMacro("__HEXAGON_ARCH__", "2");
5332 if(Opts.HexagonQdsp6Compat) {
5333 Builder.defineMacro("__QDSP6_V2__");
5334 Builder.defineMacro("__QDSP6_ARCH__", "2");
5337 else if(CPU == "hexagonv3") {
5338 Builder.defineMacro("__HEXAGON_V3__");
5339 Builder.defineMacro("__HEXAGON_ARCH__", "3");
5340 if(Opts.HexagonQdsp6Compat) {
5341 Builder.defineMacro("__QDSP6_V3__");
5342 Builder.defineMacro("__QDSP6_ARCH__", "3");
5345 else if(CPU == "hexagonv4") {
5346 Builder.defineMacro("__HEXAGON_V4__");
5347 Builder.defineMacro("__HEXAGON_ARCH__", "4");
5348 if(Opts.HexagonQdsp6Compat) {
5349 Builder.defineMacro("__QDSP6_V4__");
5350 Builder.defineMacro("__QDSP6_ARCH__", "4");
5353 else if(CPU == "hexagonv5") {
5354 Builder.defineMacro("__HEXAGON_V5__");
5355 Builder.defineMacro("__HEXAGON_ARCH__", "5");
5356 if(Opts.HexagonQdsp6Compat) {
5357 Builder.defineMacro("__QDSP6_V5__");
5358 Builder.defineMacro("__QDSP6_ARCH__", "5");
5363 const char * const HexagonTargetInfo::GCCRegNames[] = {
5364 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5365 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5366 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5367 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5368 "p0", "p1", "p2", "p3",
5369 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5372 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
5373 unsigned &NumNames) const {
5374 Names = GCCRegNames;
5375 NumNames = llvm::array_lengthof(GCCRegNames);
5379 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5380 { { "sp" }, "r29" },
5381 { { "fp" }, "r30" },
5382 { { "lr" }, "r31" },
5385 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5386 unsigned &NumAliases) const {
5387 Aliases = GCCRegAliases;
5388 NumAliases = llvm::array_lengthof(GCCRegAliases);
5392 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5393 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5394 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5396 #include "clang/Basic/BuiltinsHexagon.def"
5399 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5400 class SparcTargetInfo : public TargetInfo {
5401 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5402 static const char * const GCCRegNames[];
5405 SparcTargetInfo(const llvm::Triple &Triple)
5406 : TargetInfo(Triple), SoftFloat(false) {}
5408 bool handleTargetFeatures(std::vector<std::string> &Features,
5409 DiagnosticsEngine &Diags) override {
5410 // The backend doesn't actually handle soft float yet, but in case someone
5411 // is using the support for the front end continue to support it.
5412 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
5413 if (Feature != Features.end()) {
5415 Features.erase(Feature);
5419 void getTargetDefines(const LangOptions &Opts,
5420 MacroBuilder &Builder) const override {
5421 DefineStd(Builder, "sparc", Opts);
5422 Builder.defineMacro("__REGISTER_PREFIX__", "");
5425 Builder.defineMacro("SOFT_FLOAT", "1");
5428 bool hasFeature(StringRef Feature) const override {
5429 return llvm::StringSwitch<bool>(Feature)
5430 .Case("softfloat", SoftFloat)
5431 .Case("sparc", true)
5435 void getTargetBuiltins(const Builtin::Info *&Records,
5436 unsigned &NumRecords) const override {
5437 // FIXME: Implement!
5439 BuiltinVaListKind getBuiltinVaListKind() const override {
5440 return TargetInfo::VoidPtrBuiltinVaList;
5442 void getGCCRegNames(const char * const *&Names,
5443 unsigned &NumNames) const override;
5444 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5445 unsigned &NumAliases) const override;
5446 bool validateAsmConstraint(const char *&Name,
5447 TargetInfo::ConstraintInfo &info) const override {
5448 // FIXME: Implement!
5450 case 'I': // Signed 13-bit constant
5452 case 'K': // 32-bit constant with the low 12 bits clear
5453 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5454 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5455 case 'N': // Same as 'K' but zext (required for SIMode)
5456 case 'O': // The constant 4096
5461 const char *getClobbers() const override {
5462 // FIXME: Implement!
5467 const char * const SparcTargetInfo::GCCRegNames[] = {
5468 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5469 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5470 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5471 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5474 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5475 unsigned &NumNames) const {
5476 Names = GCCRegNames;
5477 NumNames = llvm::array_lengthof(GCCRegNames);
5480 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5491 { { "o2" }, "r10" },
5492 { { "o3" }, "r11" },
5493 { { "o4" }, "r12" },
5494 { { "o5" }, "r13" },
5495 { { "o6", "sp" }, "r14" },
5496 { { "o7" }, "r15" },
5497 { { "l0" }, "r16" },
5498 { { "l1" }, "r17" },
5499 { { "l2" }, "r18" },
5500 { { "l3" }, "r19" },
5501 { { "l4" }, "r20" },
5502 { { "l5" }, "r21" },
5503 { { "l6" }, "r22" },
5504 { { "l7" }, "r23" },
5505 { { "i0" }, "r24" },
5506 { { "i1" }, "r25" },
5507 { { "i2" }, "r26" },
5508 { { "i3" }, "r27" },
5509 { { "i4" }, "r28" },
5510 { { "i5" }, "r29" },
5511 { { "i6", "fp" }, "r30" },
5512 { { "i7" }, "r31" },
5515 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5516 unsigned &NumAliases) const {
5517 Aliases = GCCRegAliases;
5518 NumAliases = llvm::array_lengthof(GCCRegAliases);
5521 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
5522 class SparcV8TargetInfo : public SparcTargetInfo {
5524 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5525 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5526 // NetBSD uses long (same as llvm default); everyone else uses int.
5527 if (getTriple().getOS() == llvm::Triple::NetBSD) {
5528 SizeType = UnsignedLong;
5529 IntPtrType = SignedLong;
5530 PtrDiffType = SignedLong;
5532 SizeType = UnsignedInt;
5533 IntPtrType = SignedInt;
5534 PtrDiffType = SignedInt;
5538 void getTargetDefines(const LangOptions &Opts,
5539 MacroBuilder &Builder) const override {
5540 SparcTargetInfo::getTargetDefines(Opts, Builder);
5541 Builder.defineMacro("__sparcv8");
5545 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
5546 class SparcV8elTargetInfo : public SparcV8TargetInfo {
5548 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) {
5549 DescriptionString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64";
5554 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5555 class SparcV9TargetInfo : public SparcTargetInfo {
5557 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5558 // FIXME: Support Sparc quad-precision long double?
5559 DescriptionString = "E-m:e-i64:64-n32:64-S128";
5560 // This is an LP64 platform.
5561 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5563 // OpenBSD uses long long for int64_t and intmax_t.
5564 if (getTriple().getOS() == llvm::Triple::OpenBSD)
5565 IntMaxType = SignedLongLong;
5567 IntMaxType = SignedLong;
5568 Int64Type = IntMaxType;
5570 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5571 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5572 LongDoubleWidth = 128;
5573 LongDoubleAlign = 128;
5574 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5575 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5578 void getTargetDefines(const LangOptions &Opts,
5579 MacroBuilder &Builder) const override {
5580 SparcTargetInfo::getTargetDefines(Opts, Builder);
5581 Builder.defineMacro("__sparcv9");
5582 Builder.defineMacro("__arch64__");
5583 // Solaris doesn't need these variants, but the BSDs do.
5584 if (getTriple().getOS() != llvm::Triple::Solaris) {
5585 Builder.defineMacro("__sparc64__");
5586 Builder.defineMacro("__sparc_v9__");
5587 Builder.defineMacro("__sparcv9__");
5591 bool setCPU(const std::string &Name) override {
5592 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5594 .Case("ultrasparc", true)
5595 .Case("ultrasparc3", true)
5596 .Case("niagara", true)
5597 .Case("niagara2", true)
5598 .Case("niagara3", true)
5599 .Case("niagara4", true)
5602 // No need to store the CPU yet. There aren't any CPU-specific
5603 // macros to define.
5608 class SystemZTargetInfo : public TargetInfo {
5609 static const Builtin::Info BuiltinInfo[];
5610 static const char *const GCCRegNames[];
5612 bool HasTransactionalExecution;
5616 SystemZTargetInfo(const llvm::Triple &Triple)
5617 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) {
5618 IntMaxType = SignedLong;
5619 Int64Type = SignedLong;
5620 TLSSupported = true;
5621 IntWidth = IntAlign = 32;
5622 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5623 PointerWidth = PointerAlign = 64;
5624 LongDoubleWidth = 128;
5625 LongDoubleAlign = 64;
5626 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5627 DefaultAlignForAttributeAligned = 64;
5628 MinGlobalAlign = 16;
5629 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5630 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5632 void getTargetDefines(const LangOptions &Opts,
5633 MacroBuilder &Builder) const override {
5634 Builder.defineMacro("__s390__");
5635 Builder.defineMacro("__s390x__");
5636 Builder.defineMacro("__zarch__");
5637 Builder.defineMacro("__LONG_DOUBLE_128__");
5638 if (HasTransactionalExecution)
5639 Builder.defineMacro("__HTM__");
5641 void getTargetBuiltins(const Builtin::Info *&Records,
5642 unsigned &NumRecords) const override {
5643 Records = BuiltinInfo;
5644 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin;
5647 void getGCCRegNames(const char *const *&Names,
5648 unsigned &NumNames) const override;
5649 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5650 unsigned &NumAliases) const override {
5655 bool validateAsmConstraint(const char *&Name,
5656 TargetInfo::ConstraintInfo &info) const override;
5657 const char *getClobbers() const override {
5658 // FIXME: Is this really right?
5661 BuiltinVaListKind getBuiltinVaListKind() const override {
5662 return TargetInfo::SystemZBuiltinVaList;
5664 bool setCPU(const std::string &Name) override {
5666 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5669 .Case("zEC12", true)
5675 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5677 Features["transactional-execution"] = true;
5679 Features["transactional-execution"] = true;
5680 Features["vector"] = true;
5684 bool handleTargetFeatures(std::vector<std::string> &Features,
5685 DiagnosticsEngine &Diags) override {
5686 HasTransactionalExecution = false;
5687 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
5688 if (Features[i] == "+transactional-execution")
5689 HasTransactionalExecution = true;
5690 if (Features[i] == "+vector")
5693 // If we use the vector ABI, vector types are 64-bit aligned.
5695 MaxVectorAlign = 64;
5696 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
5697 "-v128:64-a:8:16-n32:64";
5702 bool hasFeature(StringRef Feature) const override {
5703 return llvm::StringSwitch<bool>(Feature)
5704 .Case("systemz", true)
5705 .Case("htm", HasTransactionalExecution)
5706 .Case("vx", HasVector)
5710 StringRef getABI() const override {
5716 bool useFloat128ManglingForLongDouble() const override {
5721 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
5722 #define BUILTIN(ID, TYPE, ATTRS) \
5723 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5724 #include "clang/Basic/BuiltinsSystemZ.def"
5727 const char *const SystemZTargetInfo::GCCRegNames[] = {
5728 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5729 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5730 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
5731 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
5734 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5735 unsigned &NumNames) const {
5736 Names = GCCRegNames;
5737 NumNames = llvm::array_lengthof(GCCRegNames);
5740 bool SystemZTargetInfo::
5741 validateAsmConstraint(const char *&Name,
5742 TargetInfo::ConstraintInfo &Info) const {
5747 case 'a': // Address register
5748 case 'd': // Data register (equivalent to 'r')
5749 case 'f': // Floating-point register
5750 Info.setAllowsRegister();
5753 case 'I': // Unsigned 8-bit constant
5754 case 'J': // Unsigned 12-bit constant
5755 case 'K': // Signed 16-bit constant
5756 case 'L': // Signed 20-bit displacement (on all targets we support)
5757 case 'M': // 0x7fffffff
5760 case 'Q': // Memory with base and unsigned 12-bit displacement
5761 case 'R': // Likewise, plus an index
5762 case 'S': // Memory with base and signed 20-bit displacement
5763 case 'T': // Likewise, plus an index
5764 Info.setAllowsMemory();
5769 class MSP430TargetInfo : public TargetInfo {
5770 static const char * const GCCRegNames[];
5772 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5774 TLSSupported = false;
5775 IntWidth = 16; IntAlign = 16;
5776 LongWidth = 32; LongLongWidth = 64;
5777 LongAlign = LongLongAlign = 16;
5778 PointerWidth = 16; PointerAlign = 16;
5780 SizeType = UnsignedInt;
5781 IntMaxType = SignedLongLong;
5782 IntPtrType = SignedInt;
5783 PtrDiffType = SignedInt;
5784 SigAtomicType = SignedLong;
5785 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5787 void getTargetDefines(const LangOptions &Opts,
5788 MacroBuilder &Builder) const override {
5789 Builder.defineMacro("MSP430");
5790 Builder.defineMacro("__MSP430__");
5791 // FIXME: defines for different 'flavours' of MCU
5793 void getTargetBuiltins(const Builtin::Info *&Records,
5794 unsigned &NumRecords) const override {
5795 // FIXME: Implement.
5799 bool hasFeature(StringRef Feature) const override {
5800 return Feature == "msp430";
5802 void getGCCRegNames(const char * const *&Names,
5803 unsigned &NumNames) const override;
5804 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5805 unsigned &NumAliases) const override {
5811 validateAsmConstraint(const char *&Name,
5812 TargetInfo::ConstraintInfo &info) const override {
5815 case 'K': // the constant 1
5816 case 'L': // constant -1^20 .. 1^19
5817 case 'M': // constant 1-4:
5820 // No target constraints for now.
5823 const char *getClobbers() const override {
5824 // FIXME: Is this really right?
5827 BuiltinVaListKind getBuiltinVaListKind() const override {
5829 return TargetInfo::CharPtrBuiltinVaList;
5833 const char * const MSP430TargetInfo::GCCRegNames[] = {
5834 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5835 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5838 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5839 unsigned &NumNames) const {
5840 Names = GCCRegNames;
5841 NumNames = llvm::array_lengthof(GCCRegNames);
5844 // LLVM and Clang cannot be used directly to output native binaries for
5845 // target, but is used to compile C code to llvm bitcode with correct
5846 // type and alignment information.
5848 // TCE uses the llvm bitcode as input and uses it for generating customized
5849 // target processor and program binary. TCE co-design environment is
5850 // publicly available in http://tce.cs.tut.fi
5852 static const unsigned TCEOpenCLAddrSpaceMap[] = {
5855 5, // opencl_constant
5856 // FIXME: generic has to be added to the target
5857 0, // opencl_generic
5863 class TCETargetInfo : public TargetInfo{
5865 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5866 TLSSupported = false;
5868 LongWidth = LongLongWidth = 32;
5871 LongAlign = LongLongAlign = 32;
5874 SizeType = UnsignedInt;
5875 IntMaxType = SignedLong;
5876 IntPtrType = SignedInt;
5877 PtrDiffType = SignedInt;
5882 LongDoubleWidth = 32;
5883 LongDoubleAlign = 32;
5884 FloatFormat = &llvm::APFloat::IEEEsingle;
5885 DoubleFormat = &llvm::APFloat::IEEEsingle;
5886 LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5887 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5888 "-f64:32-v64:32-v128:32-a:0:32-n32";
5889 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5890 UseAddrSpaceMapMangling = true;
5893 void getTargetDefines(const LangOptions &Opts,
5894 MacroBuilder &Builder) const override {
5895 DefineStd(Builder, "tce", Opts);
5896 Builder.defineMacro("__TCE__");
5897 Builder.defineMacro("__TCE_V1__");
5899 bool hasFeature(StringRef Feature) const override {
5900 return Feature == "tce";
5903 void getTargetBuiltins(const Builtin::Info *&Records,
5904 unsigned &NumRecords) const override {}
5905 const char *getClobbers() const override {
5908 BuiltinVaListKind getBuiltinVaListKind() const override {
5909 return TargetInfo::VoidPtrBuiltinVaList;
5911 void getGCCRegNames(const char * const *&Names,
5912 unsigned &NumNames) const override {}
5913 bool validateAsmConstraint(const char *&Name,
5914 TargetInfo::ConstraintInfo &info) const override{
5917 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5918 unsigned &NumAliases) const override {}
5921 class BPFTargetInfo : public TargetInfo {
5923 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5924 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5925 SizeType = UnsignedLong;
5926 PtrDiffType = SignedLong;
5927 IntPtrType = SignedLong;
5928 IntMaxType = SignedLong;
5929 Int64Type = SignedLong;
5931 if (Triple.getArch() == llvm::Triple::bpfeb) {
5933 DescriptionString = "E-m:e-p:64:64-i64:64-n32:64-S128";
5936 DescriptionString = "e-m:e-p:64:64-i64:64-n32:64-S128";
5938 MaxAtomicPromoteWidth = 64;
5939 MaxAtomicInlineWidth = 64;
5940 TLSSupported = false;
5942 void getTargetDefines(const LangOptions &Opts,
5943 MacroBuilder &Builder) const override {
5944 DefineStd(Builder, "bpf", Opts);
5945 Builder.defineMacro("__BPF__");
5947 bool hasFeature(StringRef Feature) const override {
5948 return Feature == "bpf";
5951 void getTargetBuiltins(const Builtin::Info *&Records,
5952 unsigned &NumRecords) const override {}
5953 const char *getClobbers() const override {
5956 BuiltinVaListKind getBuiltinVaListKind() const override {
5957 return TargetInfo::VoidPtrBuiltinVaList;
5959 void getGCCRegNames(const char * const *&Names,
5960 unsigned &NumNames) const override {
5964 bool validateAsmConstraint(const char *&Name,
5965 TargetInfo::ConstraintInfo &info) const override {
5968 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5969 unsigned &NumAliases) const override {
5975 class MipsTargetInfoBase : public TargetInfo {
5976 virtual void setDescriptionString() = 0;
5978 static const Builtin::Info BuiltinInfo[];
5985 HardFloat, SoftFloat
5997 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5998 const std::string &CPUStr)
5999 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
6000 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
6001 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
6002 TheCXXABI.set(TargetCXXABI::GenericMIPS);
6005 bool isNaN2008Default() const {
6006 return CPU == "mips32r6" || CPU == "mips64r6";
6009 bool isFP64Default() const {
6010 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
6013 bool isNan2008() const override {
6017 StringRef getABI() const override { return ABI; }
6018 bool setCPU(const std::string &Name) override {
6019 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
6020 getTriple().getArch() == llvm::Triple::mipsel;
6022 return llvm::StringSwitch<bool>(Name)
6023 .Case("mips1", IsMips32)
6024 .Case("mips2", IsMips32)
6025 .Case("mips3", true)
6026 .Case("mips4", true)
6027 .Case("mips5", true)
6028 .Case("mips32", IsMips32)
6029 .Case("mips32r2", IsMips32)
6030 .Case("mips32r3", IsMips32)
6031 .Case("mips32r5", IsMips32)
6032 .Case("mips32r6", IsMips32)
6033 .Case("mips64", true)
6034 .Case("mips64r2", true)
6035 .Case("mips64r3", true)
6036 .Case("mips64r5", true)
6037 .Case("mips64r6", true)
6038 .Case("octeon", true)
6041 const std::string& getCPU() const { return CPU; }
6042 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6043 if (CPU == "octeon")
6044 Features["mips64r2"] = Features["cnmips"] = true;
6046 Features[CPU] = true;
6049 void getTargetDefines(const LangOptions &Opts,
6050 MacroBuilder &Builder) const override {
6051 Builder.defineMacro("__mips__");
6052 Builder.defineMacro("_mips");
6054 Builder.defineMacro("mips");
6056 Builder.defineMacro("__REGISTER_PREFIX__", "");
6060 Builder.defineMacro("__mips_hard_float", Twine(1));
6063 Builder.defineMacro("__mips_soft_float", Twine(1));
6068 Builder.defineMacro("__mips_single_float", Twine(1));
6070 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
6071 Builder.defineMacro("_MIPS_FPSET",
6072 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
6075 Builder.defineMacro("__mips16", Twine(1));
6078 Builder.defineMacro("__mips_micromips", Twine(1));
6081 Builder.defineMacro("__mips_nan2008", Twine(1));
6087 Builder.defineMacro("__mips_dsp_rev", Twine(1));
6088 Builder.defineMacro("__mips_dsp", Twine(1));
6091 Builder.defineMacro("__mips_dsp_rev", Twine(2));
6092 Builder.defineMacro("__mips_dspr2", Twine(1));
6093 Builder.defineMacro("__mips_dsp", Twine(1));
6098 Builder.defineMacro("__mips_msa", Twine(1));
6100 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
6101 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
6102 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
6104 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
6105 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
6108 void getTargetBuiltins(const Builtin::Info *&Records,
6109 unsigned &NumRecords) const override {
6110 Records = BuiltinInfo;
6111 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
6113 bool hasFeature(StringRef Feature) const override {
6114 return llvm::StringSwitch<bool>(Feature)
6116 .Case("fp64", HasFP64)
6119 BuiltinVaListKind getBuiltinVaListKind() const override {
6120 return TargetInfo::VoidPtrBuiltinVaList;
6122 void getGCCRegNames(const char * const *&Names,
6123 unsigned &NumNames) const override {
6124 static const char *const GCCRegNames[] = {
6125 // CPU register names
6126 // Must match second column of GCCRegAliases
6127 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
6128 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
6129 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
6130 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
6131 // Floating point register names
6132 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
6133 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
6134 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
6135 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
6136 // Hi/lo and condition register names
6137 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
6138 "$fcc5","$fcc6","$fcc7",
6139 // MSA register names
6140 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
6141 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
6142 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
6143 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
6144 // MSA control register names
6145 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
6146 "$msarequest", "$msamap", "$msaunmap"
6148 Names = GCCRegNames;
6149 NumNames = llvm::array_lengthof(GCCRegNames);
6151 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6152 unsigned &NumAliases) const override = 0;
6153 bool validateAsmConstraint(const char *&Name,
6154 TargetInfo::ConstraintInfo &Info) const override {
6158 case 'r': // CPU registers.
6159 case 'd': // Equivalent to "r" unless generating MIPS16 code.
6160 case 'y': // Equivalent to "r", backward compatibility only.
6161 case 'f': // floating-point registers.
6162 case 'c': // $25 for indirect jumps
6163 case 'l': // lo register
6164 case 'x': // hilo register pair
6165 Info.setAllowsRegister();
6167 case 'I': // Signed 16-bit constant
6168 case 'J': // Integer 0
6169 case 'K': // Unsigned 16-bit constant
6170 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
6171 case 'M': // Constants not loadable via lui, addiu, or ori
6172 case 'N': // Constant -1 to -65535
6173 case 'O': // A signed 15-bit constant
6174 case 'P': // A constant between 1 go 65535
6176 case 'R': // An address that can be used in a non-macro load or store
6177 Info.setAllowsMemory();
6180 if (Name[1] == 'C') { // An address usable by ll, and sc.
6181 Info.setAllowsMemory();
6182 Name++; // Skip over 'Z'.
6189 std::string convertConstraint(const char *&Constraint) const override {
6191 switch (*Constraint) {
6192 case 'Z': // Two-character constraint; add "^" hint for later parsing.
6193 if (Constraint[1] == 'C') {
6194 R = std::string("^") + std::string(Constraint, 2);
6200 return TargetInfo::convertConstraint(Constraint);
6203 const char *getClobbers() const override {
6204 // In GCC, $1 is not widely used in generated code (it's used only in a few
6205 // specific situations), so there is no real need for users to add it to
6206 // the clobbers list if they want to use it in their inline assembly code.
6208 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
6209 // code generation, so using it in inline assembly without adding it to the
6210 // clobbers list can cause conflicts between the inline assembly code and
6211 // the surrounding generated code.
6213 // Another problem is that LLVM is allowed to choose $1 for inline assembly
6214 // operands, which will conflict with the ".set at" assembler option (which
6215 // we use only for inline assembly, in order to maintain compatibility with
6216 // GCC) and will also conflict with the user's usage of $1.
6218 // The easiest way to avoid these conflicts and keep $1 as an allocatable
6219 // register for generated code is to automatically clobber $1 for all inline
6222 // FIXME: We should automatically clobber $1 only for inline assembly code
6223 // which actually uses it. This would allow LLVM to use $1 for inline
6224 // assembly operands if the user's assembly code doesn't use it.
6228 bool handleTargetFeatures(std::vector<std::string> &Features,
6229 DiagnosticsEngine &Diags) override {
6231 IsMicromips = false;
6232 IsNan2008 = isNaN2008Default();
6233 IsSingleFloat = false;
6234 FloatABI = HardFloat;
6236 HasFP64 = isFP64Default();
6238 for (std::vector<std::string>::iterator it = Features.begin(),
6239 ie = Features.end(); it != ie; ++it) {
6240 if (*it == "+single-float")
6241 IsSingleFloat = true;
6242 else if (*it == "+soft-float")
6243 FloatABI = SoftFloat;
6244 else if (*it == "+mips16")
6246 else if (*it == "+micromips")
6248 else if (*it == "+dsp")
6249 DspRev = std::max(DspRev, DSP1);
6250 else if (*it == "+dspr2")
6251 DspRev = std::max(DspRev, DSP2);
6252 else if (*it == "+msa")
6254 else if (*it == "+fp64")
6256 else if (*it == "-fp64")
6258 else if (*it == "+nan2008")
6260 else if (*it == "-nan2008")
6264 setDescriptionString();
6269 int getEHDataRegisterNumber(unsigned RegNo) const override {
6270 if (RegNo == 0) return 4;
6271 if (RegNo == 1) return 5;
6275 bool isCLZForZeroUndef() const override { return false; }
6278 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
6279 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6280 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6282 #include "clang/Basic/BuiltinsMips.def"
6285 class Mips32TargetInfoBase : public MipsTargetInfoBase {
6287 Mips32TargetInfoBase(const llvm::Triple &Triple)
6288 : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
6289 SizeType = UnsignedInt;
6290 PtrDiffType = SignedInt;
6291 Int64Type = SignedLongLong;
6292 IntMaxType = Int64Type;
6293 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
6295 bool setABI(const std::string &Name) override {
6296 if (Name == "o32" || Name == "eabi") {
6302 void getTargetDefines(const LangOptions &Opts,
6303 MacroBuilder &Builder) const override {
6304 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6306 Builder.defineMacro("__mips", "32");
6307 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
6309 const std::string& CPUStr = getCPU();
6310 if (CPUStr == "mips32")
6311 Builder.defineMacro("__mips_isa_rev", "1");
6312 else if (CPUStr == "mips32r2")
6313 Builder.defineMacro("__mips_isa_rev", "2");
6314 else if (CPUStr == "mips32r3")
6315 Builder.defineMacro("__mips_isa_rev", "3");
6316 else if (CPUStr == "mips32r5")
6317 Builder.defineMacro("__mips_isa_rev", "5");
6318 else if (CPUStr == "mips32r6")
6319 Builder.defineMacro("__mips_isa_rev", "6");
6322 Builder.defineMacro("__mips_o32");
6323 Builder.defineMacro("_ABIO32", "1");
6324 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
6326 else if (ABI == "eabi")
6327 Builder.defineMacro("__mips_eabi");
6329 llvm_unreachable("Invalid ABI for Mips32.");
6331 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6332 unsigned &NumAliases) const override {
6333 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6343 { { "t2" }, "$10" },
6344 { { "t3" }, "$11" },
6345 { { "t4" }, "$12" },
6346 { { "t5" }, "$13" },
6347 { { "t6" }, "$14" },
6348 { { "t7" }, "$15" },
6349 { { "s0" }, "$16" },
6350 { { "s1" }, "$17" },
6351 { { "s2" }, "$18" },
6352 { { "s3" }, "$19" },
6353 { { "s4" }, "$20" },
6354 { { "s5" }, "$21" },
6355 { { "s6" }, "$22" },
6356 { { "s7" }, "$23" },
6357 { { "t8" }, "$24" },
6358 { { "t9" }, "$25" },
6359 { { "k0" }, "$26" },
6360 { { "k1" }, "$27" },
6361 { { "gp" }, "$28" },
6362 { { "sp","$sp" }, "$29" },
6363 { { "fp","$fp" }, "$30" },
6366 Aliases = GCCRegAliases;
6367 NumAliases = llvm::array_lengthof(GCCRegAliases);
6371 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
6372 void setDescriptionString() override {
6373 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6377 Mips32EBTargetInfo(const llvm::Triple &Triple)
6378 : Mips32TargetInfoBase(Triple) {
6380 void getTargetDefines(const LangOptions &Opts,
6381 MacroBuilder &Builder) const override {
6382 DefineStd(Builder, "MIPSEB", Opts);
6383 Builder.defineMacro("_MIPSEB");
6384 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6388 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
6389 void setDescriptionString() override {
6390 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6394 Mips32ELTargetInfo(const llvm::Triple &Triple)
6395 : Mips32TargetInfoBase(Triple) {
6398 void getTargetDefines(const LangOptions &Opts,
6399 MacroBuilder &Builder) const override {
6400 DefineStd(Builder, "MIPSEL", Opts);
6401 Builder.defineMacro("_MIPSEL");
6402 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6406 class Mips64TargetInfoBase : public MipsTargetInfoBase {
6408 Mips64TargetInfoBase(const llvm::Triple &Triple)
6409 : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6410 LongDoubleWidth = LongDoubleAlign = 128;
6411 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6412 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6413 LongDoubleWidth = LongDoubleAlign = 64;
6414 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6417 SuitableAlign = 128;
6418 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6421 void setN64ABITypes() {
6422 LongWidth = LongAlign = 64;
6423 PointerWidth = PointerAlign = 64;
6424 SizeType = UnsignedLong;
6425 PtrDiffType = SignedLong;
6426 Int64Type = SignedLong;
6427 IntMaxType = Int64Type;
6430 void setN32ABITypes() {
6431 LongWidth = LongAlign = 32;
6432 PointerWidth = PointerAlign = 32;
6433 SizeType = UnsignedInt;
6434 PtrDiffType = SignedInt;
6435 Int64Type = SignedLongLong;
6436 IntMaxType = Int64Type;
6439 bool setABI(const std::string &Name) override {
6440 if (Name == "n32") {
6445 if (Name == "n64") {
6453 void getTargetDefines(const LangOptions &Opts,
6454 MacroBuilder &Builder) const override {
6455 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6457 Builder.defineMacro("__mips", "64");
6458 Builder.defineMacro("__mips64");
6459 Builder.defineMacro("__mips64__");
6460 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6462 const std::string& CPUStr = getCPU();
6463 if (CPUStr == "mips64")
6464 Builder.defineMacro("__mips_isa_rev", "1");
6465 else if (CPUStr == "mips64r2")
6466 Builder.defineMacro("__mips_isa_rev", "2");
6467 else if (CPUStr == "mips64r3")
6468 Builder.defineMacro("__mips_isa_rev", "3");
6469 else if (CPUStr == "mips64r5")
6470 Builder.defineMacro("__mips_isa_rev", "5");
6471 else if (CPUStr == "mips64r6")
6472 Builder.defineMacro("__mips_isa_rev", "6");
6475 Builder.defineMacro("__mips_n32");
6476 Builder.defineMacro("_ABIN32", "2");
6477 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6479 else if (ABI == "n64") {
6480 Builder.defineMacro("__mips_n64");
6481 Builder.defineMacro("_ABI64", "3");
6482 Builder.defineMacro("_MIPS_SIM", "_ABI64");
6485 llvm_unreachable("Invalid ABI for Mips64.");
6487 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6488 unsigned &NumAliases) const override {
6489 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6499 { { "a6" }, "$10" },
6500 { { "a7" }, "$11" },
6501 { { "t0" }, "$12" },
6502 { { "t1" }, "$13" },
6503 { { "t2" }, "$14" },
6504 { { "t3" }, "$15" },
6505 { { "s0" }, "$16" },
6506 { { "s1" }, "$17" },
6507 { { "s2" }, "$18" },
6508 { { "s3" }, "$19" },
6509 { { "s4" }, "$20" },
6510 { { "s5" }, "$21" },
6511 { { "s6" }, "$22" },
6512 { { "s7" }, "$23" },
6513 { { "t8" }, "$24" },
6514 { { "t9" }, "$25" },
6515 { { "k0" }, "$26" },
6516 { { "k1" }, "$27" },
6517 { { "gp" }, "$28" },
6518 { { "sp","$sp" }, "$29" },
6519 { { "fp","$fp" }, "$30" },
6522 Aliases = GCCRegAliases;
6523 NumAliases = llvm::array_lengthof(GCCRegAliases);
6526 bool hasInt128Type() const override { return true; }
6529 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
6530 void setDescriptionString() override {
6532 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6534 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6539 Mips64EBTargetInfo(const llvm::Triple &Triple)
6540 : Mips64TargetInfoBase(Triple) {}
6541 void getTargetDefines(const LangOptions &Opts,
6542 MacroBuilder &Builder) const override {
6543 DefineStd(Builder, "MIPSEB", Opts);
6544 Builder.defineMacro("_MIPSEB");
6545 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6549 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
6550 void setDescriptionString() override {
6552 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6554 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6557 Mips64ELTargetInfo(const llvm::Triple &Triple)
6558 : Mips64TargetInfoBase(Triple) {
6559 // Default ABI is n64.
6562 void getTargetDefines(const LangOptions &Opts,
6563 MacroBuilder &Builder) const override {
6564 DefineStd(Builder, "MIPSEL", Opts);
6565 Builder.defineMacro("_MIPSEL");
6566 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6570 class PNaClTargetInfo : public TargetInfo {
6572 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6574 this->UserLabelPrefix = "";
6575 this->LongAlign = 32;
6576 this->LongWidth = 32;
6577 this->PointerAlign = 32;
6578 this->PointerWidth = 32;
6579 this->IntMaxType = TargetInfo::SignedLongLong;
6580 this->Int64Type = TargetInfo::SignedLongLong;
6581 this->DoubleAlign = 64;
6582 this->LongDoubleWidth = 64;
6583 this->LongDoubleAlign = 64;
6584 this->SizeType = TargetInfo::UnsignedInt;
6585 this->PtrDiffType = TargetInfo::SignedInt;
6586 this->IntPtrType = TargetInfo::SignedInt;
6587 this->RegParmMax = 0; // Disallow regparm
6590 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6592 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6593 Builder.defineMacro("__le32__");
6594 Builder.defineMacro("__pnacl__");
6596 void getTargetDefines(const LangOptions &Opts,
6597 MacroBuilder &Builder) const override {
6598 getArchDefines(Opts, Builder);
6600 bool hasFeature(StringRef Feature) const override {
6601 return Feature == "pnacl";
6603 void getTargetBuiltins(const Builtin::Info *&Records,
6604 unsigned &NumRecords) const override {
6606 BuiltinVaListKind getBuiltinVaListKind() const override {
6607 return TargetInfo::PNaClABIBuiltinVaList;
6609 void getGCCRegNames(const char * const *&Names,
6610 unsigned &NumNames) const override;
6611 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6612 unsigned &NumAliases) const override;
6613 bool validateAsmConstraint(const char *&Name,
6614 TargetInfo::ConstraintInfo &Info) const override {
6618 const char *getClobbers() const override {
6623 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6624 unsigned &NumNames) const {
6629 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6630 unsigned &NumAliases) const {
6635 class Le64TargetInfo : public TargetInfo {
6636 static const Builtin::Info BuiltinInfo[];
6639 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6641 NoAsmVariants = true;
6642 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6643 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6645 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
6648 void getTargetDefines(const LangOptions &Opts,
6649 MacroBuilder &Builder) const override {
6650 DefineStd(Builder, "unix", Opts);
6651 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6652 Builder.defineMacro("__ELF__");
6654 void getTargetBuiltins(const Builtin::Info *&Records,
6655 unsigned &NumRecords) const override {
6656 Records = BuiltinInfo;
6657 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
6659 BuiltinVaListKind getBuiltinVaListKind() const override {
6660 return TargetInfo::PNaClABIBuiltinVaList;
6662 const char *getClobbers() const override { return ""; }
6663 void getGCCRegNames(const char *const *&Names,
6664 unsigned &NumNames) const override {
6668 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6669 unsigned &NumAliases) const override {
6673 bool validateAsmConstraint(const char *&Name,
6674 TargetInfo::ConstraintInfo &Info) const override {
6678 bool hasProtectedVisibility() const override { return false; }
6680 } // end anonymous namespace.
6682 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
6683 #define BUILTIN(ID, TYPE, ATTRS) \
6684 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6685 #include "clang/Basic/BuiltinsLe64.def"
6689 static const unsigned SPIRAddrSpaceMap[] = {
6692 2, // opencl_constant
6693 4, // opencl_generic
6698 class SPIRTargetInfo : public TargetInfo {
6700 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6701 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6702 "SPIR target must use unknown OS");
6703 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6704 "SPIR target must use unknown environment type");
6706 TLSSupported = false;
6707 LongWidth = LongAlign = 64;
6708 AddrSpaceMap = &SPIRAddrSpaceMap;
6709 UseAddrSpaceMapMangling = true;
6710 // Define available target features
6711 // These must be defined in sorted order!
6712 NoAsmVariants = true;
6714 void getTargetDefines(const LangOptions &Opts,
6715 MacroBuilder &Builder) const override {
6716 DefineStd(Builder, "SPIR", Opts);
6718 bool hasFeature(StringRef Feature) const override {
6719 return Feature == "spir";
6722 void getTargetBuiltins(const Builtin::Info *&Records,
6723 unsigned &NumRecords) const override {}
6724 const char *getClobbers() const override {
6727 void getGCCRegNames(const char * const *&Names,
6728 unsigned &NumNames) const override {}
6730 validateAsmConstraint(const char *&Name,
6731 TargetInfo::ConstraintInfo &info) const override {
6734 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6735 unsigned &NumAliases) const override {}
6736 BuiltinVaListKind getBuiltinVaListKind() const override {
6737 return TargetInfo::VoidPtrBuiltinVaList;
6740 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6741 return (CC == CC_SpirFunction ||
6742 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning;
6745 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
6746 return CC_SpirFunction;
6751 class SPIR32TargetInfo : public SPIRTargetInfo {
6753 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6754 PointerWidth = PointerAlign = 32;
6755 SizeType = TargetInfo::UnsignedInt;
6756 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6758 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6759 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6761 void getTargetDefines(const LangOptions &Opts,
6762 MacroBuilder &Builder) const override {
6763 DefineStd(Builder, "SPIR32", Opts);
6767 class SPIR64TargetInfo : public SPIRTargetInfo {
6769 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6770 PointerWidth = PointerAlign = 64;
6771 SizeType = TargetInfo::UnsignedLong;
6772 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6773 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6774 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6776 void getTargetDefines(const LangOptions &Opts,
6777 MacroBuilder &Builder) const override {
6778 DefineStd(Builder, "SPIR64", Opts);
6782 class XCoreTargetInfo : public TargetInfo {
6783 static const Builtin::Info BuiltinInfo[];
6785 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6787 NoAsmVariants = true;
6790 DoubleAlign = LongDoubleAlign = 32;
6791 SizeType = UnsignedInt;
6792 PtrDiffType = SignedInt;
6793 IntPtrType = SignedInt;
6794 WCharType = UnsignedChar;
6795 WIntType = UnsignedInt;
6796 UseZeroLengthBitfieldAlignment = true;
6797 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6798 "-f64:32-a:0:32-n32";
6800 void getTargetDefines(const LangOptions &Opts,
6801 MacroBuilder &Builder) const override {
6802 Builder.defineMacro("__XS1B__");
6804 void getTargetBuiltins(const Builtin::Info *&Records,
6805 unsigned &NumRecords) const override {
6806 Records = BuiltinInfo;
6807 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
6809 BuiltinVaListKind getBuiltinVaListKind() const override {
6810 return TargetInfo::VoidPtrBuiltinVaList;
6812 const char *getClobbers() const override {
6815 void getGCCRegNames(const char * const *&Names,
6816 unsigned &NumNames) const override {
6817 static const char * const GCCRegNames[] = {
6818 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6819 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
6821 Names = GCCRegNames;
6822 NumNames = llvm::array_lengthof(GCCRegNames);
6824 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6825 unsigned &NumAliases) const override {
6829 bool validateAsmConstraint(const char *&Name,
6830 TargetInfo::ConstraintInfo &Info) const override {
6833 int getEHDataRegisterNumber(unsigned RegNo) const override {
6834 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6835 return (RegNo < 2)? RegNo : -1;
6839 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6840 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6841 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6843 #include "clang/Basic/BuiltinsXCore.def"
6845 } // end anonymous namespace.
6848 // x86_32 Android target
6849 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
6851 AndroidX86_32TargetInfo(const llvm::Triple &Triple)
6852 : LinuxTargetInfo<X86_32TargetInfo>(Triple) {
6854 LongDoubleWidth = 64;
6855 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6858 } // end anonymous namespace
6861 // x86_64 Android target
6862 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
6864 AndroidX86_64TargetInfo(const llvm::Triple &Triple)
6865 : LinuxTargetInfo<X86_64TargetInfo>(Triple) {
6866 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6869 } // end anonymous namespace
6872 //===----------------------------------------------------------------------===//
6874 //===----------------------------------------------------------------------===//
6876 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6877 llvm::Triple::OSType os = Triple.getOS();
6879 switch (Triple.getArch()) {
6883 case llvm::Triple::xcore:
6884 return new XCoreTargetInfo(Triple);
6886 case llvm::Triple::hexagon:
6887 return new HexagonTargetInfo(Triple);
6889 case llvm::Triple::aarch64:
6890 if (Triple.isOSDarwin())
6891 return new DarwinAArch64TargetInfo(Triple);
6894 case llvm::Triple::FreeBSD:
6895 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
6896 case llvm::Triple::Linux:
6897 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6898 case llvm::Triple::NetBSD:
6899 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6901 return new AArch64leTargetInfo(Triple);
6904 case llvm::Triple::aarch64_be:
6906 case llvm::Triple::FreeBSD:
6907 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
6908 case llvm::Triple::Linux:
6909 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6910 case llvm::Triple::NetBSD:
6911 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6913 return new AArch64beTargetInfo(Triple);
6916 case llvm::Triple::arm:
6917 case llvm::Triple::thumb:
6918 if (Triple.isOSBinFormatMachO())
6919 return new DarwinARMTargetInfo(Triple);
6922 case llvm::Triple::Linux:
6923 return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6924 case llvm::Triple::FreeBSD:
6925 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6926 case llvm::Triple::NetBSD:
6927 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6928 case llvm::Triple::OpenBSD:
6929 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6930 case llvm::Triple::Bitrig:
6931 return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6932 case llvm::Triple::RTEMS:
6933 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6934 case llvm::Triple::NaCl:
6935 return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6936 case llvm::Triple::Win32:
6937 switch (Triple.getEnvironment()) {
6939 return new ARMleTargetInfo(Triple);
6940 case llvm::Triple::Itanium:
6941 return new ItaniumWindowsARMleTargetInfo(Triple);
6942 case llvm::Triple::MSVC:
6943 return new MicrosoftARMleTargetInfo(Triple);
6946 return new ARMleTargetInfo(Triple);
6949 case llvm::Triple::armeb:
6950 case llvm::Triple::thumbeb:
6951 if (Triple.isOSDarwin())
6952 return new DarwinARMTargetInfo(Triple);
6955 case llvm::Triple::Linux:
6956 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6957 case llvm::Triple::FreeBSD:
6958 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6959 case llvm::Triple::NetBSD:
6960 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6961 case llvm::Triple::OpenBSD:
6962 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6963 case llvm::Triple::Bitrig:
6964 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6965 case llvm::Triple::RTEMS:
6966 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6967 case llvm::Triple::NaCl:
6968 return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6970 return new ARMbeTargetInfo(Triple);
6973 case llvm::Triple::bpfeb:
6974 case llvm::Triple::bpfel:
6975 return new BPFTargetInfo(Triple);
6977 case llvm::Triple::msp430:
6978 return new MSP430TargetInfo(Triple);
6980 case llvm::Triple::mips:
6982 case llvm::Triple::Linux:
6983 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6984 case llvm::Triple::RTEMS:
6985 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6986 case llvm::Triple::FreeBSD:
6987 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6988 case llvm::Triple::NetBSD:
6989 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6991 return new Mips32EBTargetInfo(Triple);
6994 case llvm::Triple::mipsel:
6996 case llvm::Triple::Linux:
6997 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6998 case llvm::Triple::RTEMS:
6999 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
7000 case llvm::Triple::FreeBSD:
7001 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
7002 case llvm::Triple::NetBSD:
7003 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
7004 case llvm::Triple::NaCl:
7005 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
7007 return new Mips32ELTargetInfo(Triple);
7010 case llvm::Triple::mips64:
7012 case llvm::Triple::Linux:
7013 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
7014 case llvm::Triple::RTEMS:
7015 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
7016 case llvm::Triple::FreeBSD:
7017 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7018 case llvm::Triple::NetBSD:
7019 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7020 case llvm::Triple::OpenBSD:
7021 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7023 return new Mips64EBTargetInfo(Triple);
7026 case llvm::Triple::mips64el:
7028 case llvm::Triple::Linux:
7029 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
7030 case llvm::Triple::RTEMS:
7031 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
7032 case llvm::Triple::FreeBSD:
7033 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7034 case llvm::Triple::NetBSD:
7035 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7036 case llvm::Triple::OpenBSD:
7037 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7039 return new Mips64ELTargetInfo(Triple);
7042 case llvm::Triple::le32:
7044 case llvm::Triple::NaCl:
7045 return new NaClTargetInfo<PNaClTargetInfo>(Triple);
7050 case llvm::Triple::le64:
7051 return new Le64TargetInfo(Triple);
7053 case llvm::Triple::ppc:
7054 if (Triple.isOSDarwin())
7055 return new DarwinPPC32TargetInfo(Triple);
7057 case llvm::Triple::Linux:
7058 return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
7059 case llvm::Triple::FreeBSD:
7060 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
7061 case llvm::Triple::NetBSD:
7062 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
7063 case llvm::Triple::OpenBSD:
7064 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
7065 case llvm::Triple::RTEMS:
7066 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
7068 return new PPC32TargetInfo(Triple);
7071 case llvm::Triple::ppc64:
7072 if (Triple.isOSDarwin())
7073 return new DarwinPPC64TargetInfo(Triple);
7075 case llvm::Triple::Linux:
7076 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7077 case llvm::Triple::Lv2:
7078 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
7079 case llvm::Triple::FreeBSD:
7080 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
7081 case llvm::Triple::NetBSD:
7082 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7084 return new PPC64TargetInfo(Triple);
7087 case llvm::Triple::ppc64le:
7089 case llvm::Triple::Linux:
7090 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7091 case llvm::Triple::NetBSD:
7092 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7094 return new PPC64TargetInfo(Triple);
7097 case llvm::Triple::nvptx:
7098 return new NVPTX32TargetInfo(Triple);
7099 case llvm::Triple::nvptx64:
7100 return new NVPTX64TargetInfo(Triple);
7102 case llvm::Triple::amdgcn:
7103 case llvm::Triple::r600:
7104 return new AMDGPUTargetInfo(Triple);
7106 case llvm::Triple::sparc:
7108 case llvm::Triple::Linux:
7109 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
7110 case llvm::Triple::Solaris:
7111 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple);
7112 case llvm::Triple::NetBSD:
7113 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
7114 case llvm::Triple::OpenBSD:
7115 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
7116 case llvm::Triple::RTEMS:
7117 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
7119 return new SparcV8TargetInfo(Triple);
7122 // The 'sparcel' architecture copies all the above cases except for Solaris.
7123 case llvm::Triple::sparcel:
7125 case llvm::Triple::Linux:
7126 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple);
7127 case llvm::Triple::NetBSD:
7128 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7129 case llvm::Triple::OpenBSD:
7130 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7131 case llvm::Triple::RTEMS:
7132 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple);
7134 return new SparcV8elTargetInfo(Triple);
7137 case llvm::Triple::sparcv9:
7139 case llvm::Triple::Linux:
7140 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
7141 case llvm::Triple::Solaris:
7142 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
7143 case llvm::Triple::NetBSD:
7144 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
7145 case llvm::Triple::OpenBSD:
7146 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
7147 case llvm::Triple::FreeBSD:
7148 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
7150 return new SparcV9TargetInfo(Triple);
7153 case llvm::Triple::systemz:
7155 case llvm::Triple::Linux:
7156 return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
7158 return new SystemZTargetInfo(Triple);
7161 case llvm::Triple::tce:
7162 return new TCETargetInfo(Triple);
7164 case llvm::Triple::x86:
7165 if (Triple.isOSDarwin())
7166 return new DarwinI386TargetInfo(Triple);
7169 case llvm::Triple::CloudABI:
7170 return new CloudABITargetInfo<X86_32TargetInfo>(Triple);
7171 case llvm::Triple::Linux: {
7172 switch (Triple.getEnvironment()) {
7174 return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
7175 case llvm::Triple::Android:
7176 return new AndroidX86_32TargetInfo(Triple);
7179 case llvm::Triple::DragonFly:
7180 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
7181 case llvm::Triple::NetBSD:
7182 return new NetBSDI386TargetInfo(Triple);
7183 case llvm::Triple::OpenBSD:
7184 return new OpenBSDI386TargetInfo(Triple);
7185 case llvm::Triple::Bitrig:
7186 return new BitrigI386TargetInfo(Triple);
7187 case llvm::Triple::FreeBSD:
7188 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7189 case llvm::Triple::KFreeBSD:
7190 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7191 case llvm::Triple::Minix:
7192 return new MinixTargetInfo<X86_32TargetInfo>(Triple);
7193 case llvm::Triple::Solaris:
7194 return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
7195 case llvm::Triple::Win32: {
7196 switch (Triple.getEnvironment()) {
7198 return new X86_32TargetInfo(Triple);
7199 case llvm::Triple::Cygnus:
7200 return new CygwinX86_32TargetInfo(Triple);
7201 case llvm::Triple::GNU:
7202 return new MinGWX86_32TargetInfo(Triple);
7203 case llvm::Triple::Itanium:
7204 case llvm::Triple::MSVC:
7205 return new MicrosoftX86_32TargetInfo(Triple);
7208 case llvm::Triple::Haiku:
7209 return new HaikuX86_32TargetInfo(Triple);
7210 case llvm::Triple::RTEMS:
7211 return new RTEMSX86_32TargetInfo(Triple);
7212 case llvm::Triple::NaCl:
7213 return new NaClTargetInfo<X86_32TargetInfo>(Triple);
7215 return new X86_32TargetInfo(Triple);
7218 case llvm::Triple::x86_64:
7219 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
7220 return new DarwinX86_64TargetInfo(Triple);
7223 case llvm::Triple::CloudABI:
7224 return new CloudABITargetInfo<X86_64TargetInfo>(Triple);
7225 case llvm::Triple::Linux: {
7226 switch (Triple.getEnvironment()) {
7228 return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
7229 case llvm::Triple::Android:
7230 return new AndroidX86_64TargetInfo(Triple);
7233 case llvm::Triple::DragonFly:
7234 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
7235 case llvm::Triple::NetBSD:
7236 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
7237 case llvm::Triple::OpenBSD:
7238 return new OpenBSDX86_64TargetInfo(Triple);
7239 case llvm::Triple::Bitrig:
7240 return new BitrigX86_64TargetInfo(Triple);
7241 case llvm::Triple::FreeBSD:
7242 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7243 case llvm::Triple::KFreeBSD:
7244 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7245 case llvm::Triple::Solaris:
7246 return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
7247 case llvm::Triple::Win32: {
7248 switch (Triple.getEnvironment()) {
7250 return new X86_64TargetInfo(Triple);
7251 case llvm::Triple::GNU:
7252 return new MinGWX86_64TargetInfo(Triple);
7253 case llvm::Triple::MSVC:
7254 return new MicrosoftX86_64TargetInfo(Triple);
7257 case llvm::Triple::NaCl:
7258 return new NaClTargetInfo<X86_64TargetInfo>(Triple);
7259 case llvm::Triple::PS4:
7260 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple);
7262 return new X86_64TargetInfo(Triple);
7265 case llvm::Triple::spir: {
7266 if (Triple.getOS() != llvm::Triple::UnknownOS ||
7267 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7269 return new SPIR32TargetInfo(Triple);
7271 case llvm::Triple::spir64: {
7272 if (Triple.getOS() != llvm::Triple::UnknownOS ||
7273 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7275 return new SPIR64TargetInfo(Triple);
7280 /// CreateTargetInfo - Return the target info object for the specified target
7283 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
7284 const std::shared_ptr<TargetOptions> &Opts) {
7285 llvm::Triple Triple(Opts->Triple);
7287 // Construct the target
7288 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
7290 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
7293 Target->TargetOpts = Opts;
7295 // Set the target CPU if specified.
7296 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
7297 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
7301 // Set the target ABI if specified.
7302 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
7303 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
7307 // Set the fp math unit.
7308 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
7309 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
7313 // Compute the default target features, we need the target to handle this
7314 // because features may have dependencies on one another.
7315 llvm::StringMap<bool> Features;
7316 Target->getDefaultFeatures(Features);
7318 // Apply the user specified deltas.
7319 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
7321 const char *Name = Opts->FeaturesAsWritten[I].c_str();
7322 // Apply the feature via the target.
7323 bool Enabled = Name[0] == '+';
7324 Target->setFeatureEnabled(Features, Name + 1, Enabled);
7327 // Add the features to the compile options.
7329 // FIXME: If we are completely confident that we have the right set, we only
7330 // need to pass the minuses.
7331 Opts->Features.clear();
7332 for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
7333 ie = Features.end(); it != ie; ++it)
7334 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
7335 if (!Target->handleTargetFeatures(Opts->Features, Diags))
7338 return Target.release();