1 //===--- Targets.cpp - Implement target feature support -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/Builtins.h"
16 #include "clang/Basic/Cuda.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetInfo.h"
22 #include "clang/Basic/TargetOptions.h"
23 #include "clang/Basic/Version.h"
24 #include "clang/Frontend/CodeGenOptions.h"
25 #include "llvm/ADT/APFloat.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/StringSwitch.h"
30 #include "llvm/ADT/Triple.h"
31 #include "llvm/MC/MCSectionMachO.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/TargetParser.h"
37 using namespace clang;
39 //===----------------------------------------------------------------------===//
40 // Common code shared among targets.
41 //===----------------------------------------------------------------------===//
43 /// DefineStd - Define a macro name and standard variants. For example if
44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
47 const LangOptions &Opts) {
48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
51 // in the user's namespace.
53 Builder.defineMacro(MacroName);
56 Builder.defineMacro("__" + MacroName);
59 Builder.defineMacro("__" + MacroName + "__");
62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
64 Builder.defineMacro("__" + CPUName);
65 Builder.defineMacro("__" + CPUName + "__");
67 Builder.defineMacro("__tune_" + CPUName + "__");
70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
71 const TargetOptions &Opts);
73 //===----------------------------------------------------------------------===//
74 // Defines specific to certain operating systems.
75 //===----------------------------------------------------------------------===//
78 template<typename TgtInfo>
79 class OSTargetInfo : public TgtInfo {
81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
82 MacroBuilder &Builder) const=0;
84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
85 : TgtInfo(Triple, Opts) {}
86 void getTargetDefines(const LangOptions &Opts,
87 MacroBuilder &Builder) const override {
88 TgtInfo::getTargetDefines(Opts, Builder);
89 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
95 template <typename Target>
96 class CloudABITargetInfo : public OSTargetInfo<Target> {
98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
99 MacroBuilder &Builder) const override {
100 Builder.defineMacro("__CloudABI__");
101 Builder.defineMacro("__ELF__");
103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
104 Builder.defineMacro("__STDC_ISO_10646__", "201206L");
105 Builder.defineMacro("__STDC_UTF_16__");
106 Builder.defineMacro("__STDC_UTF_32__");
110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
111 : OSTargetInfo<Target>(Triple, Opts) {}
114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
115 const llvm::Triple &Triple,
116 StringRef &PlatformName,
117 VersionTuple &PlatformMinVersion) {
118 Builder.defineMacro("__APPLE_CC__", "6000");
119 Builder.defineMacro("__APPLE__");
120 Builder.defineMacro("__STDC_NO_THREADS__");
121 Builder.defineMacro("OBJC_NEW_PROPERTIES");
122 // AddressSanitizer doesn't play well with source fortification, which is on
123 // by default on Darwin.
124 if (Opts.Sanitize.has(SanitizerKind::Address))
125 Builder.defineMacro("_FORTIFY_SOURCE", "0");
127 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode.
129 // __weak is always defined, for use in blocks and with objc pointers.
130 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
131 Builder.defineMacro("__strong", "");
132 Builder.defineMacro("__unsafe_unretained", "");
136 Builder.defineMacro("__STATIC__");
138 Builder.defineMacro("__DYNAMIC__");
140 if (Opts.POSIXThreads)
141 Builder.defineMacro("_REENTRANT");
143 // Get the platform type and version number from the triple.
144 unsigned Maj, Min, Rev;
145 if (Triple.isMacOSX()) {
146 Triple.getMacOSXVersion(Maj, Min, Rev);
147 PlatformName = "macos";
149 Triple.getOSVersion(Maj, Min, Rev);
150 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
153 // If -target arch-pc-win32-macho option specified, we're
154 // generating code for Win32 ABI. No need to emit
155 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
156 if (PlatformName == "win32") {
157 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
161 // Set the appropriate OS version define.
162 if (Triple.isiOS()) {
163 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
167 Str[1] = '0' + (Min / 10);
168 Str[2] = '0' + (Min % 10);
169 Str[3] = '0' + (Rev / 10);
170 Str[4] = '0' + (Rev % 10);
173 // Handle versions >= 10.
174 Str[0] = '0' + (Maj / 10);
175 Str[1] = '0' + (Maj % 10);
176 Str[2] = '0' + (Min / 10);
177 Str[3] = '0' + (Min % 10);
178 Str[4] = '0' + (Rev / 10);
179 Str[5] = '0' + (Rev % 10);
183 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str);
185 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
188 } else if (Triple.isWatchOS()) {
189 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
192 Str[1] = '0' + (Min / 10);
193 Str[2] = '0' + (Min % 10);
194 Str[3] = '0' + (Rev / 10);
195 Str[4] = '0' + (Rev % 10);
197 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str);
198 } else if (Triple.isMacOSX()) {
199 // Note that the Driver allows versions which aren't representable in the
200 // define (because we only get a single digit for the minor and micro
201 // revision numbers). So, we limit them to the maximum representable
203 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
205 if (Maj < 10 || (Maj == 10 && Min < 10)) {
206 Str[0] = '0' + (Maj / 10);
207 Str[1] = '0' + (Maj % 10);
208 Str[2] = '0' + std::min(Min, 9U);
209 Str[3] = '0' + std::min(Rev, 9U);
212 // Handle versions > 10.9.
213 Str[0] = '0' + (Maj / 10);
214 Str[1] = '0' + (Maj % 10);
215 Str[2] = '0' + (Min / 10);
216 Str[3] = '0' + (Min % 10);
217 Str[4] = '0' + (Rev / 10);
218 Str[5] = '0' + (Rev % 10);
221 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
224 // Tell users about the kernel if there is one.
225 if (Triple.isOSDarwin())
226 Builder.defineMacro("__MACH__");
228 // The Watch ABI uses Dwarf EH.
229 if(Triple.isWatchABI())
230 Builder.defineMacro("__ARM_DWARF_EH__");
232 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
235 template<typename Target>
236 class DarwinTargetInfo : public OSTargetInfo<Target> {
238 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
239 MacroBuilder &Builder) const override {
240 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
241 this->PlatformMinVersion);
245 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
246 : OSTargetInfo<Target>(Triple, Opts) {
247 // By default, no TLS, and we whitelist permitted architecture/OS
249 this->TLSSupported = false;
251 if (Triple.isMacOSX())
252 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7);
253 else if (Triple.isiOS()) {
254 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards.
255 if (Triple.getArch() == llvm::Triple::x86_64 ||
256 Triple.getArch() == llvm::Triple::aarch64)
257 this->TLSSupported = !Triple.isOSVersionLT(8);
258 else if (Triple.getArch() == llvm::Triple::x86 ||
259 Triple.getArch() == llvm::Triple::arm ||
260 Triple.getArch() == llvm::Triple::thumb)
261 this->TLSSupported = !Triple.isOSVersionLT(9);
262 } else if (Triple.isWatchOS())
263 this->TLSSupported = !Triple.isOSVersionLT(2);
265 this->MCountName = "\01mcount";
268 std::string isValidSectionSpecifier(StringRef SR) const override {
269 // Let MCSectionMachO validate this.
270 StringRef Segment, Section;
271 unsigned TAA, StubSize;
273 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
274 TAA, HasTAA, StubSize);
277 const char *getStaticInitSectionSpecifier() const override {
278 // FIXME: We should return 0 when building kexts.
279 return "__TEXT,__StaticInit,regular,pure_instructions";
282 /// Darwin does not support protected visibility. Darwin's "default"
283 /// is very similar to ELF's "protected"; Darwin requires a "weak"
284 /// attribute on declarations that can be dynamically replaced.
285 bool hasProtectedVisibility() const override {
289 unsigned getExnObjectAlignment() const override {
290 // The alignment of an exception object is 8-bytes for darwin since
291 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned))
292 // and therefore doesn't guarantee 16-byte alignment.
298 // DragonFlyBSD Target
299 template<typename Target>
300 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
302 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
303 MacroBuilder &Builder) const override {
304 // DragonFly defines; list based off of gcc output
305 Builder.defineMacro("__DragonFly__");
306 Builder.defineMacro("__DragonFly_cc_version", "100001");
307 Builder.defineMacro("__ELF__");
308 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
309 Builder.defineMacro("__tune_i386__");
310 DefineStd(Builder, "unix", Opts);
313 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
314 : OSTargetInfo<Target>(Triple, Opts) {
315 switch (Triple.getArch()) {
317 case llvm::Triple::x86:
318 case llvm::Triple::x86_64:
319 this->MCountName = ".mcount";
325 #ifndef FREEBSD_CC_VERSION
326 #define FREEBSD_CC_VERSION 0U
330 template<typename Target>
331 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
333 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
334 MacroBuilder &Builder) const override {
335 // FreeBSD defines; list based off of gcc output
337 unsigned Release = Triple.getOSMajorVersion();
340 unsigned CCVersion = FREEBSD_CC_VERSION;
342 CCVersion = Release * 100000U + 1U;
344 Builder.defineMacro("__FreeBSD__", Twine(Release));
345 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion));
346 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
347 DefineStd(Builder, "unix", Opts);
348 Builder.defineMacro("__ELF__");
350 // On FreeBSD, wchar_t contains the number of the code point as
351 // used by the character set of the locale. These character sets are
352 // not necessarily a superset of ASCII.
354 // FIXME: This is wrong; the macro refers to the numerical values
355 // of wchar_t *literals*, which are not locale-dependent. However,
356 // FreeBSD systems apparently depend on us getting this wrong, and
357 // setting this to 1 is conforming even if all the basic source
358 // character literals have the same encoding as char and wchar_t.
359 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
362 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
363 : OSTargetInfo<Target>(Triple, Opts) {
364 switch (Triple.getArch()) {
366 case llvm::Triple::x86:
367 case llvm::Triple::x86_64:
368 this->MCountName = ".mcount";
370 case llvm::Triple::mips:
371 case llvm::Triple::mipsel:
372 case llvm::Triple::ppc:
373 case llvm::Triple::ppc64:
374 case llvm::Triple::ppc64le:
375 this->MCountName = "_mcount";
377 case llvm::Triple::arm:
378 this->MCountName = "__mcount";
384 // GNU/kFreeBSD Target
385 template<typename Target>
386 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
388 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
389 MacroBuilder &Builder) const override {
390 // GNU/kFreeBSD defines; list based off of gcc output
392 DefineStd(Builder, "unix", Opts);
393 Builder.defineMacro("__FreeBSD_kernel__");
394 Builder.defineMacro("__GLIBC__");
395 Builder.defineMacro("__ELF__");
396 if (Opts.POSIXThreads)
397 Builder.defineMacro("_REENTRANT");
399 Builder.defineMacro("_GNU_SOURCE");
402 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
403 : OSTargetInfo<Target>(Triple, Opts) {}
407 template<typename Target>
408 class HaikuTargetInfo : public OSTargetInfo<Target> {
410 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
411 MacroBuilder &Builder) const override {
412 // Haiku defines; list based off of gcc output
413 Builder.defineMacro("__HAIKU__");
414 Builder.defineMacro("__ELF__");
415 DefineStd(Builder, "unix", Opts);
418 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
419 : OSTargetInfo<Target>(Triple, Opts) {
420 this->SizeType = TargetInfo::UnsignedLong;
421 this->IntPtrType = TargetInfo::SignedLong;
422 this->PtrDiffType = TargetInfo::SignedLong;
423 this->ProcessIDType = TargetInfo::SignedLong;
424 this->TLSSupported = false;
430 template<typename Target>
431 class MinixTargetInfo : public OSTargetInfo<Target> {
433 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
434 MacroBuilder &Builder) const override {
437 Builder.defineMacro("__minix", "3");
438 Builder.defineMacro("_EM_WSIZE", "4");
439 Builder.defineMacro("_EM_PSIZE", "4");
440 Builder.defineMacro("_EM_SSIZE", "2");
441 Builder.defineMacro("_EM_LSIZE", "4");
442 Builder.defineMacro("_EM_FSIZE", "4");
443 Builder.defineMacro("_EM_DSIZE", "8");
444 Builder.defineMacro("__ELF__");
445 DefineStd(Builder, "unix", Opts);
448 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
449 : OSTargetInfo<Target>(Triple, Opts) {}
453 template<typename Target>
454 class LinuxTargetInfo : public OSTargetInfo<Target> {
456 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
457 MacroBuilder &Builder) const override {
458 // Linux defines; list based off of gcc output
459 DefineStd(Builder, "unix", Opts);
460 DefineStd(Builder, "linux", Opts);
461 Builder.defineMacro("__gnu_linux__");
462 Builder.defineMacro("__ELF__");
463 if (Triple.isAndroid()) {
464 Builder.defineMacro("__ANDROID__", "1");
465 unsigned Maj, Min, Rev;
466 Triple.getEnvironmentVersion(Maj, Min, Rev);
467 this->PlatformName = "android";
468 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
470 Builder.defineMacro("__ANDROID_API__", Twine(Maj));
472 if (Opts.POSIXThreads)
473 Builder.defineMacro("_REENTRANT");
475 Builder.defineMacro("_GNU_SOURCE");
476 if (this->HasFloat128)
477 Builder.defineMacro("__FLOAT128__");
480 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
481 : OSTargetInfo<Target>(Triple, Opts) {
482 this->WIntType = TargetInfo::UnsignedInt;
484 switch (Triple.getArch()) {
487 case llvm::Triple::ppc:
488 case llvm::Triple::ppc64:
489 case llvm::Triple::ppc64le:
490 this->MCountName = "_mcount";
492 case llvm::Triple::x86:
493 case llvm::Triple::x86_64:
494 case llvm::Triple::systemz:
495 this->HasFloat128 = true;
500 const char *getStaticInitSectionSpecifier() const override {
501 return ".text.startup";
506 template<typename Target>
507 class NetBSDTargetInfo : public OSTargetInfo<Target> {
509 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
510 MacroBuilder &Builder) const override {
511 // NetBSD defines; list based off of gcc output
512 Builder.defineMacro("__NetBSD__");
513 Builder.defineMacro("__unix__");
514 Builder.defineMacro("__ELF__");
515 if (Opts.POSIXThreads)
516 Builder.defineMacro("_REENTRANT");
518 switch (Triple.getArch()) {
521 case llvm::Triple::arm:
522 case llvm::Triple::armeb:
523 case llvm::Triple::thumb:
524 case llvm::Triple::thumbeb:
525 Builder.defineMacro("__ARM_DWARF_EH__");
530 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
531 : OSTargetInfo<Target>(Triple, Opts) {
532 this->MCountName = "_mcount";
537 template<typename Target>
538 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
540 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
541 MacroBuilder &Builder) const override {
542 // OpenBSD defines; list based off of gcc output
544 Builder.defineMacro("__OpenBSD__");
545 DefineStd(Builder, "unix", Opts);
546 Builder.defineMacro("__ELF__");
547 if (Opts.POSIXThreads)
548 Builder.defineMacro("_REENTRANT");
549 if (this->HasFloat128)
550 Builder.defineMacro("__FLOAT128__");
553 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
554 : OSTargetInfo<Target>(Triple, Opts) {
555 this->TLSSupported = false;
557 switch (Triple.getArch()) {
558 case llvm::Triple::x86:
559 case llvm::Triple::x86_64:
560 this->HasFloat128 = true;
563 this->MCountName = "__mcount";
565 case llvm::Triple::mips64:
566 case llvm::Triple::mips64el:
567 case llvm::Triple::ppc:
568 case llvm::Triple::sparcv9:
569 this->MCountName = "_mcount";
576 template<typename Target>
577 class BitrigTargetInfo : public OSTargetInfo<Target> {
579 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
580 MacroBuilder &Builder) const override {
581 // Bitrig defines; list based off of gcc output
583 Builder.defineMacro("__Bitrig__");
584 DefineStd(Builder, "unix", Opts);
585 Builder.defineMacro("__ELF__");
586 if (Opts.POSIXThreads)
587 Builder.defineMacro("_REENTRANT");
589 switch (Triple.getArch()) {
592 case llvm::Triple::arm:
593 case llvm::Triple::armeb:
594 case llvm::Triple::thumb:
595 case llvm::Triple::thumbeb:
596 Builder.defineMacro("__ARM_DWARF_EH__");
601 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
602 : OSTargetInfo<Target>(Triple, Opts) {
603 this->MCountName = "__mcount";
608 template<typename Target>
609 class PSPTargetInfo : public OSTargetInfo<Target> {
611 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
612 MacroBuilder &Builder) const override {
613 // PSP defines; list based on the output of the pspdev gcc toolchain.
614 Builder.defineMacro("PSP");
615 Builder.defineMacro("_PSP");
616 Builder.defineMacro("__psp__");
617 Builder.defineMacro("__ELF__");
620 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {}
624 template<typename Target>
625 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
627 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
628 MacroBuilder &Builder) const override {
630 Builder.defineMacro("__PPC__");
631 Builder.defineMacro("__PPU__");
632 Builder.defineMacro("__CELLOS_LV2__");
633 Builder.defineMacro("__ELF__");
634 Builder.defineMacro("__LP32__");
635 Builder.defineMacro("_ARCH_PPC64");
636 Builder.defineMacro("__powerpc64__");
639 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
640 : OSTargetInfo<Target>(Triple, Opts) {
641 this->LongWidth = this->LongAlign = 32;
642 this->PointerWidth = this->PointerAlign = 32;
643 this->IntMaxType = TargetInfo::SignedLongLong;
644 this->Int64Type = TargetInfo::SignedLongLong;
645 this->SizeType = TargetInfo::UnsignedInt;
646 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64");
650 template <typename Target>
651 class PS4OSTargetInfo : public OSTargetInfo<Target> {
653 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
654 MacroBuilder &Builder) const override {
655 Builder.defineMacro("__FreeBSD__", "9");
656 Builder.defineMacro("__FreeBSD_cc_version", "900001");
657 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
658 DefineStd(Builder, "unix", Opts);
659 Builder.defineMacro("__ELF__");
660 Builder.defineMacro("__ORBIS__");
663 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
664 : OSTargetInfo<Target>(Triple, Opts) {
665 this->WCharType = this->UnsignedShort;
667 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits).
668 this->MaxTLSAlign = 256;
670 // On PS4, do not honor explicit bit field alignment,
671 // as in "__attribute__((aligned(2))) int b : 1;".
672 this->UseExplicitBitFieldAlignment = false;
674 switch (Triple.getArch()) {
676 case llvm::Triple::x86_64:
677 this->MCountName = ".mcount";
684 template<typename Target>
685 class SolarisTargetInfo : public OSTargetInfo<Target> {
687 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
688 MacroBuilder &Builder) const override {
689 DefineStd(Builder, "sun", Opts);
690 DefineStd(Builder, "unix", Opts);
691 Builder.defineMacro("__ELF__");
692 Builder.defineMacro("__svr4__");
693 Builder.defineMacro("__SVR4");
694 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
695 // newer, but to 500 for everything else. feature_test.h has a check to
696 // ensure that you are not using C99 with an old version of X/Open or C89
697 // with a new version.
699 Builder.defineMacro("_XOPEN_SOURCE", "600");
701 Builder.defineMacro("_XOPEN_SOURCE", "500");
703 Builder.defineMacro("__C99FEATURES__");
704 Builder.defineMacro("_LARGEFILE_SOURCE");
705 Builder.defineMacro("_LARGEFILE64_SOURCE");
706 Builder.defineMacro("__EXTENSIONS__");
707 Builder.defineMacro("_REENTRANT");
710 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
711 : OSTargetInfo<Target>(Triple, Opts) {
712 this->WCharType = this->SignedInt;
713 // FIXME: WIntType should be SignedLong
718 template<typename Target>
719 class WindowsTargetInfo : public OSTargetInfo<Target> {
721 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
722 MacroBuilder &Builder) const override {
723 Builder.defineMacro("_WIN32");
725 void getVisualStudioDefines(const LangOptions &Opts,
726 MacroBuilder &Builder) const {
727 if (Opts.CPlusPlus) {
729 Builder.defineMacro("_CPPRTTI");
731 if (Opts.CXXExceptions)
732 Builder.defineMacro("_CPPUNWIND");
736 Builder.defineMacro("__BOOL_DEFINED");
738 if (!Opts.CharIsSigned)
739 Builder.defineMacro("_CHAR_UNSIGNED");
741 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
742 // but it works for now.
743 if (Opts.POSIXThreads)
744 Builder.defineMacro("_MT");
746 if (Opts.MSCompatibilityVersion) {
747 Builder.defineMacro("_MSC_VER",
748 Twine(Opts.MSCompatibilityVersion / 100000));
749 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
750 // FIXME We cannot encode the revision information into 32-bits
751 Builder.defineMacro("_MSC_BUILD", Twine(1));
753 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
754 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
756 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) {
757 if (Opts.CPlusPlus1z)
758 Builder.defineMacro("_MSVC_LANG", "201403L");
759 else if (Opts.CPlusPlus14)
760 Builder.defineMacro("_MSVC_LANG", "201402L");
764 if (Opts.MicrosoftExt) {
765 Builder.defineMacro("_MSC_EXTENSIONS");
767 if (Opts.CPlusPlus11) {
768 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
769 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
770 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
774 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
778 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
779 : OSTargetInfo<Target>(Triple, Opts) {}
782 template <typename Target>
783 class NaClTargetInfo : public OSTargetInfo<Target> {
785 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
786 MacroBuilder &Builder) const override {
787 if (Opts.POSIXThreads)
788 Builder.defineMacro("_REENTRANT");
790 Builder.defineMacro("_GNU_SOURCE");
792 DefineStd(Builder, "unix", Opts);
793 Builder.defineMacro("__ELF__");
794 Builder.defineMacro("__native_client__");
798 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
799 : OSTargetInfo<Target>(Triple, Opts) {
800 this->LongAlign = 32;
801 this->LongWidth = 32;
802 this->PointerAlign = 32;
803 this->PointerWidth = 32;
804 this->IntMaxType = TargetInfo::SignedLongLong;
805 this->Int64Type = TargetInfo::SignedLongLong;
806 this->DoubleAlign = 64;
807 this->LongDoubleWidth = 64;
808 this->LongDoubleAlign = 64;
809 this->LongLongWidth = 64;
810 this->LongLongAlign = 64;
811 this->SizeType = TargetInfo::UnsignedInt;
812 this->PtrDiffType = TargetInfo::SignedInt;
813 this->IntPtrType = TargetInfo::SignedInt;
814 // RegParmMax is inherited from the underlying architecture.
815 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble();
816 if (Triple.getArch() == llvm::Triple::arm) {
817 // Handled in ARM's setABI().
818 } else if (Triple.getArch() == llvm::Triple::x86) {
819 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128");
820 } else if (Triple.getArch() == llvm::Triple::x86_64) {
821 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128");
822 } else if (Triple.getArch() == llvm::Triple::mipsel) {
823 // Handled on mips' setDataLayout.
825 assert(Triple.getArch() == llvm::Triple::le32);
826 this->resetDataLayout("e-p:32:32-i64:64");
832 template<typename Target>
833 class FuchsiaTargetInfo : public OSTargetInfo<Target> {
835 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
836 MacroBuilder &Builder) const override {
837 Builder.defineMacro("__Fuchsia__");
838 Builder.defineMacro("__ELF__");
839 if (Opts.POSIXThreads)
840 Builder.defineMacro("_REENTRANT");
841 // Required by the libc++ locale support.
843 Builder.defineMacro("_GNU_SOURCE");
846 FuchsiaTargetInfo(const llvm::Triple &Triple,
847 const TargetOptions &Opts)
848 : OSTargetInfo<Target>(Triple, Opts) {
849 this->MCountName = "__mcount";
853 // WebAssembly target
854 template <typename Target>
855 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> {
856 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
857 MacroBuilder &Builder) const final {
858 // A common platform macro.
859 if (Opts.POSIXThreads)
860 Builder.defineMacro("_REENTRANT");
861 // Follow g++ convention and predefine _GNU_SOURCE for C++.
863 Builder.defineMacro("_GNU_SOURCE");
866 // As an optimization, group static init code together in a section.
867 const char *getStaticInitSectionSpecifier() const final {
868 return ".text.__startup";
872 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple,
873 const TargetOptions &Opts)
874 : OSTargetInfo<Target>(Triple, Opts) {
875 this->MCountName = "__mcount";
876 this->TheCXXABI.set(TargetCXXABI::WebAssembly);
880 //===----------------------------------------------------------------------===//
881 // Specific target implementations.
882 //===----------------------------------------------------------------------===//
884 // PPC abstract base class
885 class PPCTargetInfo : public TargetInfo {
886 static const Builtin::Info BuiltinInfo[];
887 static const char * const GCCRegNames[];
888 static const TargetInfo::GCCRegAlias GCCRegAliases[];
891 // Target cpu features.
907 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
908 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false),
909 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
910 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) {
912 SimdDefaultAlign = 128;
913 LongDoubleWidth = LongDoubleAlign = 128;
914 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
917 /// \brief Flags for architecture specific defines.
920 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
921 ArchDefinePpcgr = 1 << 1,
922 ArchDefinePpcsq = 1 << 2,
923 ArchDefine440 = 1 << 3,
924 ArchDefine603 = 1 << 4,
925 ArchDefine604 = 1 << 5,
926 ArchDefinePwr4 = 1 << 6,
927 ArchDefinePwr5 = 1 << 7,
928 ArchDefinePwr5x = 1 << 8,
929 ArchDefinePwr6 = 1 << 9,
930 ArchDefinePwr6x = 1 << 10,
931 ArchDefinePwr7 = 1 << 11,
932 ArchDefinePwr8 = 1 << 12,
933 ArchDefinePwr9 = 1 << 13,
934 ArchDefineA2 = 1 << 14,
935 ArchDefineA2q = 1 << 15
938 // Set the language option for altivec based on our value.
939 void adjust(LangOptions &Opts) override {
942 TargetInfo::adjust(Opts);
945 // Note: GCC recognizes the following additional cpus:
946 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
947 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
949 bool setCPU(const std::string &Name) override {
950 bool CPUKnown = llvm::StringSwitch<bool>(Name)
951 .Case("generic", true)
973 .Case("e500mc", true)
975 .Case("power3", true)
977 .Case("power4", true)
979 .Case("power5", true)
981 .Case("power5x", true)
983 .Case("power6", true)
985 .Case("power6x", true)
987 .Case("power7", true)
989 .Case("power8", true)
991 .Case("power9", true)
993 .Case("powerpc", true)
995 .Case("powerpc64", true)
997 .Case("powerpc64le", true)
998 .Case("ppc64le", true)
1008 StringRef getABI() const override { return ABI; }
1010 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1011 return llvm::makeArrayRef(BuiltinInfo,
1012 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin);
1015 bool isCLZForZeroUndef() const override { return false; }
1017 void getTargetDefines(const LangOptions &Opts,
1018 MacroBuilder &Builder) const override;
1021 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
1023 const std::vector<std::string> &FeaturesVec) const override;
1025 bool handleTargetFeatures(std::vector<std::string> &Features,
1026 DiagnosticsEngine &Diags) override;
1027 bool hasFeature(StringRef Feature) const override;
1028 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
1029 bool Enabled) const override;
1031 ArrayRef<const char *> getGCCRegNames() const override;
1032 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
1033 bool validateAsmConstraint(const char *&Name,
1034 TargetInfo::ConstraintInfo &Info) const override {
1036 default: return false;
1039 case 'b': // Base register
1040 case 'f': // Floating point register
1041 Info.setAllowsRegister();
1043 // FIXME: The following are added to allow parsing.
1044 // I just took a guess at what the actions should be.
1045 // Also, is more specific checking needed? I.e. specific registers?
1046 case 'd': // Floating point register (containing 64-bit value)
1047 case 'v': // Altivec vector register
1048 Info.setAllowsRegister();
1052 case 'd':// VSX vector register to hold vector double data
1053 case 'f':// VSX vector register to hold vector float data
1054 case 's':// VSX vector register to hold scalar float data
1055 case 'a':// Any VSX register
1056 case 'c':// An individual CR bit
1061 Info.setAllowsRegister();
1062 Name++; // Skip over 'w'.
1064 case 'h': // `MQ', `CTR', or `LINK' register
1065 case 'q': // `MQ' register
1066 case 'c': // `CTR' register
1067 case 'l': // `LINK' register
1068 case 'x': // `CR' register (condition register) number 0
1069 case 'y': // `CR' register (condition register)
1070 case 'z': // `XER[CA]' carry bit (part of the XER register)
1071 Info.setAllowsRegister();
1073 case 'I': // Signed 16-bit constant
1074 case 'J': // Unsigned 16-bit constant shifted left 16 bits
1075 // (use `L' instead for SImode constants)
1076 case 'K': // Unsigned 16-bit constant
1077 case 'L': // Signed 16-bit constant shifted left 16 bits
1078 case 'M': // Constant larger than 31
1079 case 'N': // Exact power of 2
1080 case 'P': // Constant whose negation is a signed 16-bit constant
1081 case 'G': // Floating point constant that can be loaded into a
1082 // register with one instruction per word
1083 case 'H': // Integer/Floating point constant that can be loaded
1084 // into a register using three instructions
1086 case 'm': // Memory operand. Note that on PowerPC targets, m can
1087 // include addresses that update the base register. It
1088 // is therefore only safe to use `m' in an asm statement
1089 // if that asm statement accesses the operand exactly once.
1090 // The asm statement must also use `%U<opno>' as a
1091 // placeholder for the "update" flag in the corresponding
1092 // load or store instruction. For example:
1093 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
1095 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
1096 // is not. Use es rather than m if you don't want the base
1097 // register to be updated.
1101 // es: A "stable" memory operand; that is, one which does not
1102 // include any automodification of the base register. Unlike
1103 // `m', this constraint can be used in asm statements that
1104 // might access the operand several times, or that might not
1105 // access it at all.
1106 Info.setAllowsMemory();
1107 Name++; // Skip over 'e'.
1109 case 'Q': // Memory operand that is an offset from a register (it is
1110 // usually better to use `m' or `es' in asm statements)
1111 case 'Z': // Memory operand that is an indexed or indirect from a
1112 // register (it is usually better to use `m' or `es' in
1114 Info.setAllowsMemory();
1115 Info.setAllowsRegister();
1117 case 'R': // AIX TOC entry
1118 case 'a': // Address operand that is an indexed or indirect from a
1119 // register (`p' is preferable for asm statements)
1120 case 'S': // Constant suitable as a 64-bit mask operand
1121 case 'T': // Constant suitable as a 32-bit mask operand
1122 case 'U': // System V Release 4 small data area reference
1123 case 't': // AND masks that can be performed by two rldic{l, r}
1125 case 'W': // Vector constant that does not require memory
1126 case 'j': // Vector constant that is all zeros.
1132 std::string convertConstraint(const char *&Constraint) const override {
1134 switch (*Constraint) {
1137 // Two-character constraint; add "^" hint for later parsing.
1138 R = std::string("^") + std::string(Constraint, 2);
1142 return TargetInfo::convertConstraint(Constraint);
1146 const char *getClobbers() const override {
1149 int getEHDataRegisterNumber(unsigned RegNo) const override {
1150 if (RegNo == 0) return 3;
1151 if (RegNo == 1) return 4;
1155 bool hasSjLjLowering() const override {
1159 bool useFloat128ManglingForLongDouble() const override {
1160 return LongDoubleWidth == 128 &&
1161 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() &&
1162 getTriple().isOSBinFormatELF();
1166 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
1167 #define BUILTIN(ID, TYPE, ATTRS) \
1168 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1169 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1170 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1171 #include "clang/Basic/BuiltinsPPC.def"
1174 /// handleTargetFeatures - Perform initialization based on the user
1175 /// configured set of features.
1176 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1177 DiagnosticsEngine &Diags) {
1178 for (const auto &Feature : Features) {
1179 if (Feature == "+altivec") {
1181 } else if (Feature == "+vsx") {
1183 } else if (Feature == "+bpermd") {
1185 } else if (Feature == "+extdiv") {
1187 } else if (Feature == "+power8-vector") {
1189 } else if (Feature == "+crypto") {
1191 } else if (Feature == "+direct-move") {
1192 HasDirectMove = true;
1193 } else if (Feature == "+qpx") {
1195 } else if (Feature == "+htm") {
1197 } else if (Feature == "+float128") {
1199 } else if (Feature == "+power9-vector") {
1202 // TODO: Finish this list and add an assert that we've handled them
1209 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1210 /// #defines that are not tied to a specific subtarget.
1211 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1212 MacroBuilder &Builder) const {
1213 // Target identification.
1214 Builder.defineMacro("__ppc__");
1215 Builder.defineMacro("__PPC__");
1216 Builder.defineMacro("_ARCH_PPC");
1217 Builder.defineMacro("__powerpc__");
1218 Builder.defineMacro("__POWERPC__");
1219 if (PointerWidth == 64) {
1220 Builder.defineMacro("_ARCH_PPC64");
1221 Builder.defineMacro("__powerpc64__");
1222 Builder.defineMacro("__ppc64__");
1223 Builder.defineMacro("__PPC64__");
1226 // Target properties.
1227 if (getTriple().getArch() == llvm::Triple::ppc64le) {
1228 Builder.defineMacro("_LITTLE_ENDIAN");
1230 if (getTriple().getOS() != llvm::Triple::NetBSD &&
1231 getTriple().getOS() != llvm::Triple::OpenBSD)
1232 Builder.defineMacro("_BIG_ENDIAN");
1236 if (ABI == "elfv1" || ABI == "elfv1-qpx")
1237 Builder.defineMacro("_CALL_ELF", "1");
1239 Builder.defineMacro("_CALL_ELF", "2");
1241 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but
1242 // our suppport post-dates this and it should work on all 64-bit ppc linux
1243 // platforms. It is guaranteed to work on all elfv2 platforms.
1244 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64)
1245 Builder.defineMacro("_CALL_LINUX", "1");
1247 // Subtarget options.
1248 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1249 Builder.defineMacro("__REGISTER_PREFIX__", "");
1251 // FIXME: Should be controlled by command line option.
1252 if (LongDoubleWidth == 128) {
1253 Builder.defineMacro("__LONG_DOUBLE_128__");
1254 Builder.defineMacro("__LONGDOUBLE128");
1257 // Define this for elfv2 (64-bit only) or 64-bit darwin.
1258 if (ABI == "elfv2" ||
1259 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64))
1260 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16");
1262 // CPU identification.
1263 ArchDefineTypes defs =
1264 (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1265 .Case("440", ArchDefineName)
1266 .Case("450", ArchDefineName | ArchDefine440)
1267 .Case("601", ArchDefineName)
1268 .Case("602", ArchDefineName | ArchDefinePpcgr)
1269 .Case("603", ArchDefineName | ArchDefinePpcgr)
1270 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1271 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1272 .Case("604", ArchDefineName | ArchDefinePpcgr)
1273 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1274 .Case("620", ArchDefineName | ArchDefinePpcgr)
1275 .Case("630", ArchDefineName | ArchDefinePpcgr)
1276 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1277 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1278 .Case("750", ArchDefineName | ArchDefinePpcgr)
1279 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
1281 .Case("a2", ArchDefineA2)
1282 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1283 .Case("pwr3", ArchDefinePpcgr)
1284 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1285 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
1287 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 |
1288 ArchDefinePpcgr | ArchDefinePpcsq)
1289 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 |
1290 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1291 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x |
1292 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
1294 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 |
1295 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
1296 ArchDefinePpcgr | ArchDefinePpcsq)
1297 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x |
1298 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
1299 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1300 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 |
1301 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
1302 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
1304 .Case("power3", ArchDefinePpcgr)
1305 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1306 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
1308 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
1309 ArchDefinePpcgr | ArchDefinePpcsq)
1310 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
1311 ArchDefinePwr4 | ArchDefinePpcgr |
1313 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
1314 ArchDefinePwr5 | ArchDefinePwr4 |
1315 ArchDefinePpcgr | ArchDefinePpcsq)
1316 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 |
1317 ArchDefinePwr5x | ArchDefinePwr5 |
1318 ArchDefinePwr4 | ArchDefinePpcgr |
1320 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x |
1321 ArchDefinePwr6 | ArchDefinePwr5x |
1322 ArchDefinePwr5 | ArchDefinePwr4 |
1323 ArchDefinePpcgr | ArchDefinePpcsq)
1324 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
1325 ArchDefinePwr6x | ArchDefinePwr6 |
1326 ArchDefinePwr5x | ArchDefinePwr5 |
1327 ArchDefinePwr4 | ArchDefinePpcgr |
1329 // powerpc64le automatically defaults to at least power8.
1330 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x |
1331 ArchDefinePwr6 | ArchDefinePwr5x |
1332 ArchDefinePwr5 | ArchDefinePwr4 |
1333 ArchDefinePpcgr | ArchDefinePpcsq)
1334 .Default(ArchDefineNone);
1336 if (defs & ArchDefineName)
1337 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1338 if (defs & ArchDefinePpcgr)
1339 Builder.defineMacro("_ARCH_PPCGR");
1340 if (defs & ArchDefinePpcsq)
1341 Builder.defineMacro("_ARCH_PPCSQ");
1342 if (defs & ArchDefine440)
1343 Builder.defineMacro("_ARCH_440");
1344 if (defs & ArchDefine603)
1345 Builder.defineMacro("_ARCH_603");
1346 if (defs & ArchDefine604)
1347 Builder.defineMacro("_ARCH_604");
1348 if (defs & ArchDefinePwr4)
1349 Builder.defineMacro("_ARCH_PWR4");
1350 if (defs & ArchDefinePwr5)
1351 Builder.defineMacro("_ARCH_PWR5");
1352 if (defs & ArchDefinePwr5x)
1353 Builder.defineMacro("_ARCH_PWR5X");
1354 if (defs & ArchDefinePwr6)
1355 Builder.defineMacro("_ARCH_PWR6");
1356 if (defs & ArchDefinePwr6x)
1357 Builder.defineMacro("_ARCH_PWR6X");
1358 if (defs & ArchDefinePwr7)
1359 Builder.defineMacro("_ARCH_PWR7");
1360 if (defs & ArchDefinePwr8)
1361 Builder.defineMacro("_ARCH_PWR8");
1362 if (defs & ArchDefinePwr9)
1363 Builder.defineMacro("_ARCH_PWR9");
1364 if (defs & ArchDefineA2)
1365 Builder.defineMacro("_ARCH_A2");
1366 if (defs & ArchDefineA2q) {
1367 Builder.defineMacro("_ARCH_A2Q");
1368 Builder.defineMacro("_ARCH_QP");
1371 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1372 Builder.defineMacro("__bg__");
1373 Builder.defineMacro("__THW_BLUEGENE__");
1374 Builder.defineMacro("__bgq__");
1375 Builder.defineMacro("__TOS_BGQ__");
1379 Builder.defineMacro("__VEC__", "10206");
1380 Builder.defineMacro("__ALTIVEC__");
1383 Builder.defineMacro("__VSX__");
1385 Builder.defineMacro("__POWER8_VECTOR__");
1387 Builder.defineMacro("__CRYPTO__");
1389 Builder.defineMacro("__HTM__");
1391 Builder.defineMacro("__FLOAT128__");
1393 Builder.defineMacro("__POWER9_VECTOR__");
1395 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1396 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1397 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1398 if (PointerWidth == 64)
1399 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1401 // We have support for the bswap intrinsics so we can define this.
1402 Builder.defineMacro("__HAVE_BSWAP__", "1");
1404 // FIXME: The following are not yet generated here by Clang, but are
1405 // generated by GCC:
1408 // __RECIP_PRECISION__
1409 // __APPLE_ALTIVEC__
1416 // __CMODEL_MEDIUM__
1423 // Handle explicit options being passed to the compiler here: if we've
1424 // explicitly turned off vsx and turned on any of:
1429 // then go ahead and error since the customer has expressed an incompatible
1431 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
1432 const std::vector<std::string> &FeaturesVec) {
1434 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") !=
1435 FeaturesVec.end()) {
1436 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") !=
1437 FeaturesVec.end()) {
1438 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
1443 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") !=
1444 FeaturesVec.end()) {
1445 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
1450 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") !=
1451 FeaturesVec.end()) {
1452 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
1457 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") !=
1458 FeaturesVec.end()) {
1459 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector"
1468 bool PPCTargetInfo::initFeatureMap(
1469 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
1470 const std::vector<std::string> &FeaturesVec) const {
1471 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1482 .Case("ppc64", true)
1483 .Case("ppc64le", true)
1486 Features["qpx"] = (CPU == "a2q");
1487 Features["power9-vector"] = (CPU == "pwr9");
1488 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1489 .Case("ppc64le", true)
1493 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1494 .Case("ppc64le", true)
1498 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1499 .Case("ppc64le", true)
1504 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1505 .Case("ppc64le", true)
1510 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1511 .Case("ppc64le", true)
1515 Features["vsx"] = llvm::StringSwitch<bool>(CPU)
1516 .Case("ppc64le", true)
1521 Features["htm"] = llvm::StringSwitch<bool>(CPU)
1522 .Case("ppc64le", true)
1527 if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
1530 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1533 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1534 return llvm::StringSwitch<bool>(Feature)
1535 .Case("powerpc", true)
1536 .Case("altivec", HasAltivec)
1537 .Case("vsx", HasVSX)
1538 .Case("power8-vector", HasP8Vector)
1539 .Case("crypto", HasP8Crypto)
1540 .Case("direct-move", HasDirectMove)
1541 .Case("qpx", HasQPX)
1542 .Case("htm", HasHTM)
1543 .Case("bpermd", HasBPERMD)
1544 .Case("extdiv", HasExtDiv)
1545 .Case("float128", HasFloat128)
1546 .Case("power9-vector", HasP9Vector)
1550 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1551 StringRef Name, bool Enabled) const {
1553 // If we're enabling any of the vsx based features then enable vsx and
1554 // altivec. We'll diagnose any problems later.
1555 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name)
1557 .Case("direct-move", true)
1558 .Case("power8-vector", true)
1559 .Case("power9-vector", true)
1560 .Case("float128", true)
1563 Features["vsx"] = Features["altivec"] = true;
1564 if (Name == "power9-vector")
1565 Features["power8-vector"] = true;
1566 Features[Name] = true;
1568 // If we're disabling altivec or vsx go ahead and disable all of the vsx
1570 if ((Name == "altivec") || (Name == "vsx"))
1571 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] =
1572 Features["float128"] = Features["power9-vector"] = false;
1573 if (Name == "power8-vector")
1574 Features["power9-vector"] = false;
1575 Features[Name] = false;
1579 const char * const PPCTargetInfo::GCCRegNames[] = {
1580 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1581 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1582 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1583 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1584 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1585 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1586 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1587 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1588 "mq", "lr", "ctr", "ap",
1589 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1591 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1592 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1593 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1594 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1596 "spe_acc", "spefscr",
1600 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const {
1601 return llvm::makeArrayRef(GCCRegNames);
1604 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1605 // While some of these aliases do map to different registers
1606 // they still share the same register name.
1617 { { "10" }, "r10" },
1618 { { "11" }, "r11" },
1619 { { "12" }, "r12" },
1620 { { "13" }, "r13" },
1621 { { "14" }, "r14" },
1622 { { "15" }, "r15" },
1623 { { "16" }, "r16" },
1624 { { "17" }, "r17" },
1625 { { "18" }, "r18" },
1626 { { "19" }, "r19" },
1627 { { "20" }, "r20" },
1628 { { "21" }, "r21" },
1629 { { "22" }, "r22" },
1630 { { "23" }, "r23" },
1631 { { "24" }, "r24" },
1632 { { "25" }, "r25" },
1633 { { "26" }, "r26" },
1634 { { "27" }, "r27" },
1635 { { "28" }, "r28" },
1636 { { "29" }, "r29" },
1637 { { "30" }, "r30" },
1638 { { "31" }, "r31" },
1639 { { "fr0" }, "f0" },
1640 { { "fr1" }, "f1" },
1641 { { "fr2" }, "f2" },
1642 { { "fr3" }, "f3" },
1643 { { "fr4" }, "f4" },
1644 { { "fr5" }, "f5" },
1645 { { "fr6" }, "f6" },
1646 { { "fr7" }, "f7" },
1647 { { "fr8" }, "f8" },
1648 { { "fr9" }, "f9" },
1649 { { "fr10" }, "f10" },
1650 { { "fr11" }, "f11" },
1651 { { "fr12" }, "f12" },
1652 { { "fr13" }, "f13" },
1653 { { "fr14" }, "f14" },
1654 { { "fr15" }, "f15" },
1655 { { "fr16" }, "f16" },
1656 { { "fr17" }, "f17" },
1657 { { "fr18" }, "f18" },
1658 { { "fr19" }, "f19" },
1659 { { "fr20" }, "f20" },
1660 { { "fr21" }, "f21" },
1661 { { "fr22" }, "f22" },
1662 { { "fr23" }, "f23" },
1663 { { "fr24" }, "f24" },
1664 { { "fr25" }, "f25" },
1665 { { "fr26" }, "f26" },
1666 { { "fr27" }, "f27" },
1667 { { "fr28" }, "f28" },
1668 { { "fr29" }, "f29" },
1669 { { "fr30" }, "f30" },
1670 { { "fr31" }, "f31" },
1671 { { "cc" }, "cr0" },
1674 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
1675 return llvm::makeArrayRef(GCCRegAliases);
1678 class PPC32TargetInfo : public PPCTargetInfo {
1680 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1681 : PPCTargetInfo(Triple, Opts) {
1682 resetDataLayout("E-m:e-p:32:32-i64:64-n32");
1684 switch (getTriple().getOS()) {
1685 case llvm::Triple::Linux:
1686 case llvm::Triple::FreeBSD:
1687 case llvm::Triple::NetBSD:
1688 SizeType = UnsignedInt;
1689 PtrDiffType = SignedInt;
1690 IntPtrType = SignedInt;
1696 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1697 LongDoubleWidth = LongDoubleAlign = 64;
1698 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1701 // PPC32 supports atomics up to 4 bytes.
1702 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1705 BuiltinVaListKind getBuiltinVaListKind() const override {
1706 // This is the ELF definition, and is overridden by the Darwin sub-target
1707 return TargetInfo::PowerABIBuiltinVaList;
1711 // Note: ABI differences may eventually require us to have a separate
1712 // TargetInfo for little endian.
1713 class PPC64TargetInfo : public PPCTargetInfo {
1715 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1716 : PPCTargetInfo(Triple, Opts) {
1717 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1718 IntMaxType = SignedLong;
1719 Int64Type = SignedLong;
1721 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1722 resetDataLayout("e-m:e-i64:64-n32:64");
1725 resetDataLayout("E-m:e-i64:64-n32:64");
1729 switch (getTriple().getOS()) {
1730 case llvm::Triple::FreeBSD:
1731 LongDoubleWidth = LongDoubleAlign = 64;
1732 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1734 case llvm::Triple::NetBSD:
1735 IntMaxType = SignedLongLong;
1736 Int64Type = SignedLongLong;
1742 // PPC64 supports atomics up to 8 bytes.
1743 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1745 BuiltinVaListKind getBuiltinVaListKind() const override {
1746 return TargetInfo::CharPtrBuiltinVaList;
1748 // PPC64 Linux-specific ABI options.
1749 bool setABI(const std::string &Name) override {
1750 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1758 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> {
1760 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1761 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
1762 HasAlignMac68kSupport = true;
1763 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1764 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1766 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
1768 BuiltinVaListKind getBuiltinVaListKind() const override {
1769 return TargetInfo::CharPtrBuiltinVaList;
1773 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> {
1775 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1776 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
1777 HasAlignMac68kSupport = true;
1778 resetDataLayout("E-m:o-i64:64-n32:64");
1782 static const unsigned NVPTXAddrSpaceMap[] = {
1786 4, // opencl_constant
1787 // FIXME: generic has to be added to the target
1788 0, // opencl_generic
1794 class NVPTXTargetInfo : public TargetInfo {
1795 static const char *const GCCRegNames[];
1796 static const Builtin::Info BuiltinInfo[];
1798 std::unique_ptr<TargetInfo> HostTarget;
1801 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts,
1802 unsigned TargetPointerWidth)
1803 : TargetInfo(Triple) {
1804 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) &&
1805 "NVPTX only supports 32- and 64-bit modes.");
1807 TLSSupported = false;
1808 AddrSpaceMap = &NVPTXAddrSpaceMap;
1809 UseAddrSpaceMapMangling = true;
1811 // Define available target features
1812 // These must be defined in sorted order!
1813 NoAsmVariants = true;
1814 GPU = CudaArch::SM_20;
1816 if (TargetPointerWidth == 32)
1817 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64");
1819 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64");
1821 // If possible, get a TargetInfo for our host triple, so we can match its
1823 llvm::Triple HostTriple(Opts.HostTriple);
1824 if (!HostTriple.isNVPTX())
1825 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts));
1827 // If no host target, make some guesses about the data layout and return.
1829 LongWidth = LongAlign = TargetPointerWidth;
1830 PointerWidth = PointerAlign = TargetPointerWidth;
1831 switch (TargetPointerWidth) {
1833 SizeType = TargetInfo::UnsignedInt;
1834 PtrDiffType = TargetInfo::SignedInt;
1835 IntPtrType = TargetInfo::SignedInt;
1838 SizeType = TargetInfo::UnsignedLong;
1839 PtrDiffType = TargetInfo::SignedLong;
1840 IntPtrType = TargetInfo::SignedLong;
1843 llvm_unreachable("TargetPointerWidth must be 32 or 64");
1848 // Copy properties from host target.
1849 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0);
1850 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0);
1851 BoolWidth = HostTarget->getBoolWidth();
1852 BoolAlign = HostTarget->getBoolAlign();
1853 IntWidth = HostTarget->getIntWidth();
1854 IntAlign = HostTarget->getIntAlign();
1855 HalfWidth = HostTarget->getHalfWidth();
1856 HalfAlign = HostTarget->getHalfAlign();
1857 FloatWidth = HostTarget->getFloatWidth();
1858 FloatAlign = HostTarget->getFloatAlign();
1859 DoubleWidth = HostTarget->getDoubleWidth();
1860 DoubleAlign = HostTarget->getDoubleAlign();
1861 LongWidth = HostTarget->getLongWidth();
1862 LongAlign = HostTarget->getLongAlign();
1863 LongLongWidth = HostTarget->getLongLongWidth();
1864 LongLongAlign = HostTarget->getLongLongAlign();
1865 MinGlobalAlign = HostTarget->getMinGlobalAlign();
1866 NewAlign = HostTarget->getNewAlign();
1867 DefaultAlignForAttributeAligned =
1868 HostTarget->getDefaultAlignForAttributeAligned();
1869 SizeType = HostTarget->getSizeType();
1870 IntMaxType = HostTarget->getIntMaxType();
1871 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0);
1872 IntPtrType = HostTarget->getIntPtrType();
1873 WCharType = HostTarget->getWCharType();
1874 WIntType = HostTarget->getWIntType();
1875 Char16Type = HostTarget->getChar16Type();
1876 Char32Type = HostTarget->getChar32Type();
1877 Int64Type = HostTarget->getInt64Type();
1878 SigAtomicType = HostTarget->getSigAtomicType();
1879 ProcessIDType = HostTarget->getProcessIDType();
1881 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
1882 UseZeroLengthBitfieldAlignment =
1883 HostTarget->useZeroLengthBitfieldAlignment();
1884 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
1885 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
1887 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
1888 // we need those macros to be identical on host and device, because (among
1889 // other things) they affect which standard library classes are defined, and
1890 // we need all classes to be defined on both the host and device.
1891 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
1893 // Properties intentionally not copied from host:
1894 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the
1895 // host/device boundary.
1896 // - SuitableAlign: Not visible across the host/device boundary, and may
1897 // correctly be different on host/device, e.g. if host has wider vector
1898 // types than device.
1899 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same
1900 // as its double type, but that's not necessarily true on the host.
1901 // TODO: nvcc emits a warning when using long double on device; we should
1904 void getTargetDefines(const LangOptions &Opts,
1905 MacroBuilder &Builder) const override {
1906 Builder.defineMacro("__PTX__");
1907 Builder.defineMacro("__NVPTX__");
1908 if (Opts.CUDAIsDevice) {
1909 // Set __CUDA_ARCH__ for the GPU specified.
1910 std::string CUDAArchCode = [this] {
1912 case CudaArch::UNKNOWN:
1913 assert(false && "No GPU arch when compiling CUDA device code.");
1915 case CudaArch::SM_20:
1917 case CudaArch::SM_21:
1919 case CudaArch::SM_30:
1921 case CudaArch::SM_32:
1923 case CudaArch::SM_35:
1925 case CudaArch::SM_37:
1927 case CudaArch::SM_50:
1929 case CudaArch::SM_52:
1931 case CudaArch::SM_53:
1933 case CudaArch::SM_60:
1935 case CudaArch::SM_61:
1937 case CudaArch::SM_62:
1940 llvm_unreachable("unhandled CudaArch");
1942 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1945 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1946 return llvm::makeArrayRef(BuiltinInfo,
1947 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin);
1950 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
1952 const std::vector<std::string> &FeaturesVec) const override {
1953 Features["satom"] = GPU >= CudaArch::SM_60;
1954 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1957 bool hasFeature(StringRef Feature) const override {
1958 return llvm::StringSwitch<bool>(Feature)
1959 .Cases("ptx", "nvptx", true)
1960 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope.
1964 ArrayRef<const char *> getGCCRegNames() const override;
1965 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1969 bool validateAsmConstraint(const char *&Name,
1970 TargetInfo::ConstraintInfo &Info) const override {
1980 Info.setAllowsRegister();
1984 const char *getClobbers() const override {
1985 // FIXME: Is this really right?
1988 BuiltinVaListKind getBuiltinVaListKind() const override {
1990 return TargetInfo::CharPtrBuiltinVaList;
1992 bool setCPU(const std::string &Name) override {
1993 GPU = StringToCudaArch(Name);
1994 return GPU != CudaArch::UNKNOWN;
1996 void setSupportedOpenCLOpts() override {
1997 auto &Opts = getSupportedOpenCLOpts();
1998 Opts.support("cl_clang_storage_class_specifiers");
1999 Opts.support("cl_khr_gl_sharing");
2000 Opts.support("cl_khr_icd");
2002 Opts.support("cl_khr_fp64");
2003 Opts.support("cl_khr_byte_addressable_store");
2004 Opts.support("cl_khr_global_int32_base_atomics");
2005 Opts.support("cl_khr_global_int32_extended_atomics");
2006 Opts.support("cl_khr_local_int32_base_atomics");
2007 Opts.support("cl_khr_local_int32_extended_atomics");
2010 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2011 // CUDA compilations support all of the host's calling conventions.
2013 // TODO: We should warn if you apply a non-default CC to anything other than
2016 return HostTarget->checkCallingConvention(CC);
2017 return CCCR_Warning;
2021 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
2022 #define BUILTIN(ID, TYPE, ATTRS) \
2023 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2024 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
2025 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
2026 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2027 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2028 #include "clang/Basic/BuiltinsNVPTX.def"
2031 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
2033 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
2034 return llvm::makeArrayRef(GCCRegNames);
2037 static const LangAS::Map AMDGPUPrivateIsZeroMap = {
2041 2, // opencl_constant
2042 4, // opencl_generic
2047 static const LangAS::Map AMDGPUGenericIsZeroMap = {
2051 2, // opencl_constant
2052 0, // opencl_generic
2058 // If you edit the description strings, make sure you update
2059 // getPointerWidthV().
2061 static const char *const DataLayoutStringR600 =
2062 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2063 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
2065 static const char *const DataLayoutStringSIPrivateIsZero =
2066 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
2067 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2068 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
2070 static const char *const DataLayoutStringSIGenericIsZero =
2071 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
2072 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2073 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
2075 class AMDGPUTargetInfo final : public TargetInfo {
2076 static const Builtin::Info BuiltinInfo[];
2077 static const char * const GCCRegNames[];
2080 unsigned Generic, Global, Local, Constant, Private;
2081 AddrSpace(bool IsGenericZero_ = false){
2082 if (IsGenericZero_) {
2098 /// \brief The GPU profiles supported by the AMDGPU target.
2106 GK_EVERGREEN_DOUBLE_OPS,
2107 GK_NORTHERN_ISLANDS,
2120 static bool hasFullSpeedFMAF32(StringRef GPUName) {
2121 return parseAMDGCNName(GPUName) >= GK_GFX9;
2124 static bool isAMDGCN(const llvm::Triple &TT) {
2125 return TT.getArch() == llvm::Triple::amdgcn;
2128 static bool isGenericZero(const llvm::Triple &TT) {
2129 return TT.getEnvironmentName() == "amdgiz" ||
2130 TT.getEnvironmentName() == "amdgizcl";
2133 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
2134 : TargetInfo(Triple) ,
2135 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600),
2139 AS(isGenericZero(Triple)){
2140 if (getTriple().getArch() == llvm::Triple::amdgcn) {
2145 auto IsGenericZero = isGenericZero(Triple);
2146 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ?
2147 (IsGenericZero ? DataLayoutStringSIGenericIsZero :
2148 DataLayoutStringSIPrivateIsZero)
2149 : DataLayoutStringR600);
2150 assert(DataLayout->getAllocaAddrSpace() == AS.Private);
2152 AddrSpaceMap = IsGenericZero ? &AMDGPUGenericIsZeroMap :
2153 &AMDGPUPrivateIsZeroMap;
2154 UseAddrSpaceMapMangling = true;
2157 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
2158 if (GPU <= GK_CAYMAN)
2161 if (AddrSpace == AS.Private || AddrSpace == AS.Local) {
2167 uint64_t getMaxPointerWidth() const override {
2168 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32;
2171 const char * getClobbers() const override {
2175 ArrayRef<const char *> getGCCRegNames() const override;
2177 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2181 bool validateAsmConstraint(const char *&Name,
2182 TargetInfo::ConstraintInfo &Info) const override {
2187 Info.setAllowsRegister();
2193 bool initFeatureMap(llvm::StringMap<bool> &Features,
2194 DiagnosticsEngine &Diags, StringRef CPU,
2195 const std::vector<std::string> &FeatureVec) const override;
2197 void adjustTargetOptions(const CodeGenOptions &CGOpts,
2198 TargetOptions &TargetOpts) const override {
2199 bool hasFP32Denormals = false;
2200 bool hasFP64Denormals = false;
2201 for (auto &I : TargetOpts.FeaturesAsWritten) {
2202 if (I == "+fp32-denormals" || I == "-fp32-denormals")
2203 hasFP32Denormals = true;
2204 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals")
2205 hasFP64Denormals = true;
2207 if (!hasFP32Denormals)
2208 TargetOpts.Features.push_back(
2209 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) &&
2210 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str());
2211 // Always do not flush fp64 or fp16 denorms.
2212 if (!hasFP64Denormals && hasFP64)
2213 TargetOpts.Features.push_back("+fp64-fp16-denormals");
2216 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
2217 return llvm::makeArrayRef(BuiltinInfo,
2218 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin);
2221 void getTargetDefines(const LangOptions &Opts,
2222 MacroBuilder &Builder) const override {
2223 if (getTriple().getArch() == llvm::Triple::amdgcn)
2224 Builder.defineMacro("__AMDGCN__");
2226 Builder.defineMacro("__R600__");
2229 Builder.defineMacro("__HAS_FMAF__");
2231 Builder.defineMacro("__HAS_LDEXPF__");
2233 Builder.defineMacro("__HAS_FP64__");
2236 BuiltinVaListKind getBuiltinVaListKind() const override {
2237 return TargetInfo::CharPtrBuiltinVaList;
2240 static GPUKind parseR600Name(StringRef Name) {
2241 return llvm::StringSwitch<GPUKind>(Name)
2242 .Case("r600" , GK_R600)
2243 .Case("rv610", GK_R600)
2244 .Case("rv620", GK_R600)
2245 .Case("rv630", GK_R600)
2246 .Case("rv635", GK_R600)
2247 .Case("rs780", GK_R600)
2248 .Case("rs880", GK_R600)
2249 .Case("rv670", GK_R600_DOUBLE_OPS)
2250 .Case("rv710", GK_R700)
2251 .Case("rv730", GK_R700)
2252 .Case("rv740", GK_R700_DOUBLE_OPS)
2253 .Case("rv770", GK_R700_DOUBLE_OPS)
2254 .Case("palm", GK_EVERGREEN)
2255 .Case("cedar", GK_EVERGREEN)
2256 .Case("sumo", GK_EVERGREEN)
2257 .Case("sumo2", GK_EVERGREEN)
2258 .Case("redwood", GK_EVERGREEN)
2259 .Case("juniper", GK_EVERGREEN)
2260 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
2261 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
2262 .Case("barts", GK_NORTHERN_ISLANDS)
2263 .Case("turks", GK_NORTHERN_ISLANDS)
2264 .Case("caicos", GK_NORTHERN_ISLANDS)
2265 .Case("cayman", GK_CAYMAN)
2266 .Case("aruba", GK_CAYMAN)
2270 static GPUKind parseAMDGCNName(StringRef Name) {
2271 return llvm::StringSwitch<GPUKind>(Name)
2272 .Case("tahiti", GK_GFX6)
2273 .Case("pitcairn", GK_GFX6)
2274 .Case("verde", GK_GFX6)
2275 .Case("oland", GK_GFX6)
2276 .Case("hainan", GK_GFX6)
2277 .Case("bonaire", GK_GFX7)
2278 .Case("kabini", GK_GFX7)
2279 .Case("kaveri", GK_GFX7)
2280 .Case("hawaii", GK_GFX7)
2281 .Case("mullins", GK_GFX7)
2282 .Case("gfx700", GK_GFX7)
2283 .Case("gfx701", GK_GFX7)
2284 .Case("gfx702", GK_GFX7)
2285 .Case("tonga", GK_GFX8)
2286 .Case("iceland", GK_GFX8)
2287 .Case("carrizo", GK_GFX8)
2288 .Case("fiji", GK_GFX8)
2289 .Case("stoney", GK_GFX8)
2290 .Case("polaris10", GK_GFX8)
2291 .Case("polaris11", GK_GFX8)
2292 .Case("gfx800", GK_GFX8)
2293 .Case("gfx801", GK_GFX8)
2294 .Case("gfx802", GK_GFX8)
2295 .Case("gfx803", GK_GFX8)
2296 .Case("gfx804", GK_GFX8)
2297 .Case("gfx810", GK_GFX8)
2298 .Case("gfx900", GK_GFX9)
2299 .Case("gfx901", GK_GFX9)
2303 bool setCPU(const std::string &Name) override {
2304 if (getTriple().getArch() == llvm::Triple::amdgcn)
2305 GPU = parseAMDGCNName(Name);
2307 GPU = parseR600Name(Name);
2309 return GPU != GK_NONE;
2312 void setSupportedOpenCLOpts() override {
2313 auto &Opts = getSupportedOpenCLOpts();
2314 Opts.support("cl_clang_storage_class_specifiers");
2315 Opts.support("cl_khr_icd");
2318 Opts.support("cl_khr_fp64");
2319 if (GPU >= GK_EVERGREEN) {
2320 Opts.support("cl_khr_byte_addressable_store");
2321 Opts.support("cl_khr_global_int32_base_atomics");
2322 Opts.support("cl_khr_global_int32_extended_atomics");
2323 Opts.support("cl_khr_local_int32_base_atomics");
2324 Opts.support("cl_khr_local_int32_extended_atomics");
2326 if (GPU >= GK_GFX6) {
2327 Opts.support("cl_khr_fp16");
2328 Opts.support("cl_khr_int64_base_atomics");
2329 Opts.support("cl_khr_int64_extended_atomics");
2330 Opts.support("cl_khr_mipmap_image");
2331 Opts.support("cl_khr_subgroups");
2332 Opts.support("cl_khr_3d_image_writes");
2333 Opts.support("cl_amd_media_ops");
2334 Opts.support("cl_amd_media_ops2");
2338 LangAS::ID getOpenCLImageAddrSpace() const override {
2339 return LangAS::opencl_constant;
2342 /// \returns Target specific vtbl ptr address space.
2343 unsigned getVtblPtrAddressSpace() const override {
2344 // \todo: We currently have address spaces defined in AMDGPU Backend. It
2345 // would be nice if we could use it here instead of using bare numbers (same
2346 // applies to getDWARFAddressSpace).
2347 return 2; // constant.
2350 /// \returns If a target requires an address within a target specific address
2351 /// space \p AddressSpace to be converted in order to be used, then return the
2352 /// corresponding target specific DWARF address space.
2354 /// \returns Otherwise return None and no conversion will be emitted in the
2356 Optional<unsigned> getDWARFAddressSpace(
2357 unsigned AddressSpace) const override {
2358 const unsigned DWARF_Private = 1;
2359 const unsigned DWARF_Local = 2;
2360 if (AddressSpace == AS.Private) {
2361 return DWARF_Private;
2362 } else if (AddressSpace == AS.Local) {
2369 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2372 return CCCR_Warning;
2374 case CC_OpenCLKernel:
2379 // In amdgcn target the null pointer in global, constant, and generic
2380 // address space has value 0 but in private and local address space has
2382 uint64_t getNullPointerValue(unsigned AS) const override {
2383 return AS == LangAS::opencl_local ? ~0 : 0;
2387 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
2388 #define BUILTIN(ID, TYPE, ATTRS) \
2389 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2390 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2391 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2392 #include "clang/Basic/BuiltinsAMDGPU.def"
2394 const char * const AMDGPUTargetInfo::GCCRegNames[] = {
2395 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2396 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2397 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2398 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
2399 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
2400 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
2401 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
2402 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
2403 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
2404 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
2405 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
2406 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
2407 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
2408 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
2409 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
2410 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
2411 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
2412 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
2413 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
2414 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
2415 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
2416 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
2417 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
2418 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
2419 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
2420 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
2421 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
2422 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
2423 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
2424 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
2425 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
2426 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
2427 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2428 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
2429 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
2430 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
2431 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
2432 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
2433 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
2434 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
2435 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
2436 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
2437 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
2438 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
2439 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
2440 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
2441 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
2442 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127",
2443 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi",
2444 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi"
2447 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const {
2448 return llvm::makeArrayRef(GCCRegNames);
2451 bool AMDGPUTargetInfo::initFeatureMap(
2452 llvm::StringMap<bool> &Features,
2453 DiagnosticsEngine &Diags, StringRef CPU,
2454 const std::vector<std::string> &FeatureVec) const {
2456 // XXX - What does the member GPU mean if device name string passed here?
2457 if (getTriple().getArch() == llvm::Triple::amdgcn) {
2461 switch (parseAMDGCNName(CPU)) {
2467 Features["gfx9-insts"] = true;
2470 Features["s-memrealtime"] = true;
2471 Features["16-bit-insts"] = true;
2472 Features["dpp"] = true;
2478 llvm_unreachable("unhandled subtarget");
2484 switch (parseR600Name(CPU)) {
2488 case GK_NORTHERN_ISLANDS:
2490 case GK_R600_DOUBLE_OPS:
2491 case GK_R700_DOUBLE_OPS:
2492 case GK_EVERGREEN_DOUBLE_OPS:
2494 Features["fp64"] = true;
2499 llvm_unreachable("unhandled subtarget");
2503 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec);
2506 const Builtin::Info BuiltinInfoX86[] = {
2507 #define BUILTIN(ID, TYPE, ATTRS) \
2508 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2509 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2510 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2511 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
2512 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
2513 #include "clang/Basic/BuiltinsX86.def"
2515 #define BUILTIN(ID, TYPE, ATTRS) \
2516 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2517 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2518 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2519 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
2520 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
2521 #include "clang/Basic/BuiltinsX86_64.def"
2525 static const char* const GCCRegNames[] = {
2526 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
2527 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
2528 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
2529 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
2530 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
2531 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2532 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
2533 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
2534 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
2535 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23",
2536 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31",
2537 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23",
2538 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31",
2539 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7",
2540 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15",
2541 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23",
2542 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31",
2543 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7",
2546 const TargetInfo::AddlRegName AddlRegNames[] = {
2547 { { "al", "ah", "eax", "rax" }, 0 },
2548 { { "bl", "bh", "ebx", "rbx" }, 3 },
2549 { { "cl", "ch", "ecx", "rcx" }, 2 },
2550 { { "dl", "dh", "edx", "rdx" }, 1 },
2551 { { "esi", "rsi" }, 4 },
2552 { { "edi", "rdi" }, 5 },
2553 { { "esp", "rsp" }, 7 },
2554 { { "ebp", "rbp" }, 6 },
2555 { { "r8d", "r8w", "r8b" }, 38 },
2556 { { "r9d", "r9w", "r9b" }, 39 },
2557 { { "r10d", "r10w", "r10b" }, 40 },
2558 { { "r11d", "r11w", "r11b" }, 41 },
2559 { { "r12d", "r12w", "r12b" }, 42 },
2560 { { "r13d", "r13w", "r13b" }, 43 },
2561 { { "r14d", "r14w", "r14b" }, 44 },
2562 { { "r15d", "r15w", "r15b" }, 45 },
2565 // X86 target abstract base class; x86-32 and x86-64 are very close, so
2566 // most of the implementation can be shared.
2567 class X86TargetInfo : public TargetInfo {
2569 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
2572 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
2573 } MMX3DNowLevel = NoMMX3DNow;
2581 bool HasAES = false;
2582 bool HasPCLMUL = false;
2583 bool HasLZCNT = false;
2584 bool HasRDRND = false;
2585 bool HasFSGSBASE = false;
2586 bool HasBMI = false;
2587 bool HasBMI2 = false;
2588 bool HasPOPCNT = false;
2589 bool HasRTM = false;
2590 bool HasPRFCHW = false;
2591 bool HasRDSEED = false;
2592 bool HasADX = false;
2593 bool HasTBM = false;
2594 bool HasLWP = false;
2595 bool HasFMA = false;
2596 bool HasF16C = false;
2597 bool HasAVX512CD = false;
2598 bool HasAVX512ER = false;
2599 bool HasAVX512PF = false;
2600 bool HasAVX512DQ = false;
2601 bool HasAVX512BW = false;
2602 bool HasAVX512VL = false;
2603 bool HasAVX512VBMI = false;
2604 bool HasAVX512IFMA = false;
2605 bool HasSHA = false;
2606 bool HasMPX = false;
2607 bool HasSGX = false;
2608 bool HasCX16 = false;
2609 bool HasFXSR = false;
2610 bool HasXSAVE = false;
2611 bool HasXSAVEOPT = false;
2612 bool HasXSAVEC = false;
2613 bool HasXSAVES = false;
2614 bool HasMWAITX = false;
2615 bool HasCLZERO = false;
2616 bool HasPKU = false;
2617 bool HasCLFLUSHOPT = false;
2618 bool HasCLWB = false;
2619 bool HasMOVBE = false;
2620 bool HasPREFETCHWT1 = false;
2622 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2624 /// Each enumeration represents a particular CPU supported by Clang. These
2625 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2630 /// i386-generation processors.
2636 /// i486-generation processors.
2645 /// i586-generation processors, P5 microarchitecture based.
2653 /// i686-generation processors, P6 / Pentium M microarchitecture based.
2663 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2664 /// Clang however has some logic to suport this.
2665 // FIXME: Warn, deprecate, and potentially remove this.
2670 /// Netburst microarchitecture based processors.
2679 /// Core microarchitecture based processors.
2683 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2684 /// codename which GCC no longer accepts as an option to -march, but Clang
2685 /// has some logic for recognizing it.
2686 // FIXME: Warn, deprecate, and potentially remove this.
2698 /// Nehalem microarchitecture based processors.
2702 /// Westmere microarchitecture based processors.
2705 /// \name Sandy Bridge
2706 /// Sandy Bridge microarchitecture based processors.
2709 /// \name Ivy Bridge
2710 /// Ivy Bridge microarchitecture based processors.
2714 /// Haswell microarchitecture based processors.
2718 /// Broadwell microarchitecture based processors.
2721 /// \name Skylake Client
2722 /// Skylake client microarchitecture based processors.
2725 /// \name Skylake Server
2726 /// Skylake server microarchitecture based processors.
2729 /// \name Cannonlake Client
2730 /// Cannonlake client microarchitecture based processors.
2733 /// \name Knights Landing
2734 /// Knights Landing processor.
2738 /// Lakemont microarchitecture based processors.
2742 /// K6 architecture processors.
2750 /// K7 architecture processors.
2753 CK_AthlonThunderbird,
2760 /// K8 architecture processors.
2773 /// Bobcat architecture processors.
2780 /// Bulldozer architecture processors.
2789 /// Zen architecture processors.
2794 /// This specification is deprecated and will be removed in the future.
2795 /// Users should prefer \see CK_K8.
2796 // FIXME: Warn on this when the CPU is set to it.
2802 /// Geode processors.
2808 CPUKind getCPUKind(StringRef CPU) const {
2809 return llvm::StringSwitch<CPUKind>(CPU)
2810 .Case("i386", CK_i386)
2811 .Case("i486", CK_i486)
2812 .Case("winchip-c6", CK_WinChipC6)
2813 .Case("winchip2", CK_WinChip2)
2815 .Case("i586", CK_i586)
2816 .Case("pentium", CK_Pentium)
2817 .Case("pentium-mmx", CK_PentiumMMX)
2818 .Case("i686", CK_i686)
2819 .Case("pentiumpro", CK_PentiumPro)
2820 .Case("pentium2", CK_Pentium2)
2821 .Case("pentium3", CK_Pentium3)
2822 .Case("pentium3m", CK_Pentium3M)
2823 .Case("pentium-m", CK_PentiumM)
2824 .Case("c3-2", CK_C3_2)
2825 .Case("yonah", CK_Yonah)
2826 .Case("pentium4", CK_Pentium4)
2827 .Case("pentium4m", CK_Pentium4M)
2828 .Case("prescott", CK_Prescott)
2829 .Case("nocona", CK_Nocona)
2830 .Case("core2", CK_Core2)
2831 .Case("penryn", CK_Penryn)
2832 .Case("bonnell", CK_Bonnell)
2833 .Case("atom", CK_Bonnell) // Legacy name.
2834 .Case("silvermont", CK_Silvermont)
2835 .Case("slm", CK_Silvermont) // Legacy name.
2836 .Case("nehalem", CK_Nehalem)
2837 .Case("corei7", CK_Nehalem) // Legacy name.
2838 .Case("westmere", CK_Westmere)
2839 .Case("sandybridge", CK_SandyBridge)
2840 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2841 .Case("ivybridge", CK_IvyBridge)
2842 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2843 .Case("haswell", CK_Haswell)
2844 .Case("core-avx2", CK_Haswell) // Legacy name.
2845 .Case("broadwell", CK_Broadwell)
2846 .Case("skylake", CK_SkylakeClient)
2847 .Case("skylake-avx512", CK_SkylakeServer)
2848 .Case("skx", CK_SkylakeServer) // Legacy name.
2849 .Case("cannonlake", CK_Cannonlake)
2850 .Case("knl", CK_KNL)
2851 .Case("lakemont", CK_Lakemont)
2853 .Case("k6-2", CK_K6_2)
2854 .Case("k6-3", CK_K6_3)
2855 .Case("athlon", CK_Athlon)
2856 .Case("athlon-tbird", CK_AthlonThunderbird)
2857 .Case("athlon-4", CK_Athlon4)
2858 .Case("athlon-xp", CK_AthlonXP)
2859 .Case("athlon-mp", CK_AthlonMP)
2860 .Case("athlon64", CK_Athlon64)
2861 .Case("athlon64-sse3", CK_Athlon64SSE3)
2862 .Case("athlon-fx", CK_AthlonFX)
2864 .Case("k8-sse3", CK_K8SSE3)
2865 .Case("opteron", CK_Opteron)
2866 .Case("opteron-sse3", CK_OpteronSSE3)
2867 .Case("barcelona", CK_AMDFAM10)
2868 .Case("amdfam10", CK_AMDFAM10)
2869 .Case("btver1", CK_BTVER1)
2870 .Case("btver2", CK_BTVER2)
2871 .Case("bdver1", CK_BDVER1)
2872 .Case("bdver2", CK_BDVER2)
2873 .Case("bdver3", CK_BDVER3)
2874 .Case("bdver4", CK_BDVER4)
2875 .Case("znver1", CK_ZNVER1)
2876 .Case("x86-64", CK_x86_64)
2877 .Case("geode", CK_Geode)
2878 .Default(CK_Generic);
2885 } FPMath = FP_Default;
2888 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
2889 : TargetInfo(Triple) {
2890 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
2892 unsigned getFloatEvalMethod() const override {
2893 // X87 evaluates with 80 bits "long double" precision.
2894 return SSELevel == NoSSE ? 2 : 0;
2896 ArrayRef<const char *> getGCCRegNames() const override {
2897 return llvm::makeArrayRef(GCCRegNames);
2899 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2902 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
2903 return llvm::makeArrayRef(AddlRegNames);
2905 bool validateCpuSupports(StringRef Name) const override;
2906 bool validateAsmConstraint(const char *&Name,
2907 TargetInfo::ConstraintInfo &info) const override;
2909 bool validateGlobalRegisterVariable(StringRef RegName,
2911 bool &HasSizeMismatch) const override {
2912 // esp and ebp are the only 32-bit registers the x86 backend can currently
2914 if (RegName.equals("esp") || RegName.equals("ebp")) {
2915 // Check that the register size is 32-bit.
2916 HasSizeMismatch = RegSize != 32;
2923 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2925 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2927 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2929 std::string convertConstraint(const char *&Constraint) const override;
2930 const char *getClobbers() const override {
2931 return "~{dirflag},~{fpsr},~{flags}";
2934 StringRef getConstraintRegister(const StringRef &Constraint,
2935 const StringRef &Expression) const override {
2936 StringRef::iterator I, E;
2937 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) {
2944 // For the register constraints, return the matching register name
2957 // In case the constraint is 'r' we need to return Expression
2961 // Default value if there is no constraint for the register
2967 void getTargetDefines(const LangOptions &Opts,
2968 MacroBuilder &Builder) const override;
2969 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2971 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2973 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2975 void setFeatureEnabled(llvm::StringMap<bool> &Features,
2976 StringRef Name, bool Enabled) const override {
2977 setFeatureEnabledImpl(Features, Name, Enabled);
2979 // This exists purely to cut down on the number of virtual calls in
2980 // initFeatureMap which calls this repeatedly.
2981 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2982 StringRef Name, bool Enabled);
2984 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
2986 const std::vector<std::string> &FeaturesVec) const override;
2987 bool hasFeature(StringRef Feature) const override;
2988 bool handleTargetFeatures(std::vector<std::string> &Features,
2989 DiagnosticsEngine &Diags) override;
2990 StringRef getABI() const override {
2991 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
2993 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2995 if (getTriple().getArch() == llvm::Triple::x86 &&
2996 MMX3DNowLevel == NoMMX3DNow)
3000 bool setCPU(const std::string &Name) override {
3001 CPU = getCPUKind(Name);
3003 // Perform any per-CPU checks necessary to determine if this CPU is
3005 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
3006 // invalid without explaining *why*.
3009 // No processor selected!
3036 case CK_AthlonThunderbird:
3041 // Only accept certain architectures when compiling in 32-bit mode.
3042 if (getTriple().getArch() != llvm::Triple::x86)
3053 case CK_SandyBridge:
3057 case CK_SkylakeClient:
3058 case CK_SkylakeServer:
3062 case CK_Athlon64SSE3:
3067 case CK_OpteronSSE3:
3079 llvm_unreachable("Unhandled CPU kind");
3082 bool setFPMath(StringRef Name) override;
3084 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3085 // Most of the non-ARM calling conventions are i386 conventions.
3087 case CC_X86ThisCall:
3088 case CC_X86FastCall:
3090 case CC_X86VectorCall:
3095 case CC_IntelOclBicc:
3098 return CCCR_Warning;
3102 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3103 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
3106 bool hasSjLjLowering() const override {
3110 void setSupportedOpenCLOpts() override {
3111 getSupportedOpenCLOpts().supportAll();
3115 bool X86TargetInfo::setFPMath(StringRef Name) {
3116 if (Name == "387") {
3120 if (Name == "sse") {
3127 bool X86TargetInfo::initFeatureMap(
3128 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
3129 const std::vector<std::string> &FeaturesVec) const {
3130 // FIXME: This *really* should not be here.
3131 // X86_64 always has SSE2.
3132 if (getTriple().getArch() == llvm::Triple::x86_64)
3133 setFeatureEnabledImpl(Features, "sse2", true);
3135 const CPUKind Kind = getCPUKind(CPU);
3137 // Enable X87 for all X86 processors but Lakemont.
3138 if (Kind != CK_Lakemont)
3139 setFeatureEnabledImpl(Features, "x87", true);
3155 setFeatureEnabledImpl(Features, "mmx", true);
3160 setFeatureEnabledImpl(Features, "sse", true);
3161 setFeatureEnabledImpl(Features, "fxsr", true);
3167 setFeatureEnabledImpl(Features, "sse2", true);
3168 setFeatureEnabledImpl(Features, "fxsr", true);
3173 setFeatureEnabledImpl(Features, "sse3", true);
3174 setFeatureEnabledImpl(Features, "fxsr", true);
3175 setFeatureEnabledImpl(Features, "cx16", true);
3179 setFeatureEnabledImpl(Features, "ssse3", true);
3180 setFeatureEnabledImpl(Features, "fxsr", true);
3181 setFeatureEnabledImpl(Features, "cx16", true);
3184 setFeatureEnabledImpl(Features, "sse4.1", true);
3185 setFeatureEnabledImpl(Features, "fxsr", true);
3186 setFeatureEnabledImpl(Features, "cx16", true);
3189 setFeatureEnabledImpl(Features, "avx512ifma", true);
3190 setFeatureEnabledImpl(Features, "avx512vbmi", true);
3191 setFeatureEnabledImpl(Features, "sha", true);
3193 case CK_SkylakeServer:
3194 setFeatureEnabledImpl(Features, "avx512f", true);
3195 setFeatureEnabledImpl(Features, "avx512cd", true);
3196 setFeatureEnabledImpl(Features, "avx512dq", true);
3197 setFeatureEnabledImpl(Features, "avx512bw", true);
3198 setFeatureEnabledImpl(Features, "avx512vl", true);
3199 setFeatureEnabledImpl(Features, "pku", true);
3200 setFeatureEnabledImpl(Features, "clwb", true);
3202 case CK_SkylakeClient:
3203 setFeatureEnabledImpl(Features, "xsavec", true);
3204 setFeatureEnabledImpl(Features, "xsaves", true);
3205 setFeatureEnabledImpl(Features, "mpx", true);
3206 setFeatureEnabledImpl(Features, "sgx", true);
3207 setFeatureEnabledImpl(Features, "clflushopt", true);
3208 setFeatureEnabledImpl(Features, "rtm", true);
3211 setFeatureEnabledImpl(Features, "rdseed", true);
3212 setFeatureEnabledImpl(Features, "adx", true);
3215 setFeatureEnabledImpl(Features, "avx2", true);
3216 setFeatureEnabledImpl(Features, "lzcnt", true);
3217 setFeatureEnabledImpl(Features, "bmi", true);
3218 setFeatureEnabledImpl(Features, "bmi2", true);
3219 setFeatureEnabledImpl(Features, "fma", true);
3220 setFeatureEnabledImpl(Features, "movbe", true);
3223 setFeatureEnabledImpl(Features, "rdrnd", true);
3224 setFeatureEnabledImpl(Features, "f16c", true);
3225 setFeatureEnabledImpl(Features, "fsgsbase", true);
3227 case CK_SandyBridge:
3228 setFeatureEnabledImpl(Features, "avx", true);
3229 setFeatureEnabledImpl(Features, "xsave", true);
3230 setFeatureEnabledImpl(Features, "xsaveopt", true);
3234 setFeatureEnabledImpl(Features, "aes", true);
3235 setFeatureEnabledImpl(Features, "pclmul", true);
3238 setFeatureEnabledImpl(Features, "sse4.2", true);
3239 setFeatureEnabledImpl(Features, "fxsr", true);
3240 setFeatureEnabledImpl(Features, "cx16", true);
3243 setFeatureEnabledImpl(Features, "avx512f", true);
3244 setFeatureEnabledImpl(Features, "avx512cd", true);
3245 setFeatureEnabledImpl(Features, "avx512er", true);
3246 setFeatureEnabledImpl(Features, "avx512pf", true);
3247 setFeatureEnabledImpl(Features, "prefetchwt1", true);
3248 setFeatureEnabledImpl(Features, "fxsr", true);
3249 setFeatureEnabledImpl(Features, "rdseed", true);
3250 setFeatureEnabledImpl(Features, "adx", true);
3251 setFeatureEnabledImpl(Features, "lzcnt", true);
3252 setFeatureEnabledImpl(Features, "bmi", true);
3253 setFeatureEnabledImpl(Features, "bmi2", true);
3254 setFeatureEnabledImpl(Features, "rtm", true);
3255 setFeatureEnabledImpl(Features, "fma", true);
3256 setFeatureEnabledImpl(Features, "rdrnd", true);
3257 setFeatureEnabledImpl(Features, "f16c", true);
3258 setFeatureEnabledImpl(Features, "fsgsbase", true);
3259 setFeatureEnabledImpl(Features, "aes", true);
3260 setFeatureEnabledImpl(Features, "pclmul", true);
3261 setFeatureEnabledImpl(Features, "cx16", true);
3262 setFeatureEnabledImpl(Features, "xsaveopt", true);
3263 setFeatureEnabledImpl(Features, "xsave", true);
3264 setFeatureEnabledImpl(Features, "movbe", true);
3270 setFeatureEnabledImpl(Features, "3dnow", true);
3273 case CK_AthlonThunderbird:
3275 setFeatureEnabledImpl(Features, "3dnowa", true);
3280 setFeatureEnabledImpl(Features, "sse", true);
3281 setFeatureEnabledImpl(Features, "3dnowa", true);
3282 setFeatureEnabledImpl(Features, "fxsr", true);
3288 setFeatureEnabledImpl(Features, "sse2", true);
3289 setFeatureEnabledImpl(Features, "3dnowa", true);
3290 setFeatureEnabledImpl(Features, "fxsr", true);
3293 setFeatureEnabledImpl(Features, "sse4a", true);
3294 setFeatureEnabledImpl(Features, "lzcnt", true);
3295 setFeatureEnabledImpl(Features, "popcnt", true);
3298 case CK_OpteronSSE3:
3299 case CK_Athlon64SSE3:
3300 setFeatureEnabledImpl(Features, "sse3", true);
3301 setFeatureEnabledImpl(Features, "3dnowa", true);
3302 setFeatureEnabledImpl(Features, "fxsr", true);
3305 setFeatureEnabledImpl(Features, "avx", true);
3306 setFeatureEnabledImpl(Features, "aes", true);
3307 setFeatureEnabledImpl(Features, "pclmul", true);
3308 setFeatureEnabledImpl(Features, "bmi", true);
3309 setFeatureEnabledImpl(Features, "f16c", true);
3310 setFeatureEnabledImpl(Features, "xsaveopt", true);
3313 setFeatureEnabledImpl(Features, "ssse3", true);
3314 setFeatureEnabledImpl(Features, "sse4a", true);
3315 setFeatureEnabledImpl(Features, "lzcnt", true);
3316 setFeatureEnabledImpl(Features, "popcnt", true);
3317 setFeatureEnabledImpl(Features, "prfchw", true);
3318 setFeatureEnabledImpl(Features, "cx16", true);
3319 setFeatureEnabledImpl(Features, "fxsr", true);
3322 setFeatureEnabledImpl(Features, "adx", true);
3323 setFeatureEnabledImpl(Features, "aes", true);
3324 setFeatureEnabledImpl(Features, "avx2", true);
3325 setFeatureEnabledImpl(Features, "bmi", true);
3326 setFeatureEnabledImpl(Features, "bmi2", true);
3327 setFeatureEnabledImpl(Features, "clflushopt", true);
3328 setFeatureEnabledImpl(Features, "clzero", true);
3329 setFeatureEnabledImpl(Features, "cx16", true);
3330 setFeatureEnabledImpl(Features, "f16c", true);
3331 setFeatureEnabledImpl(Features, "fma", true);
3332 setFeatureEnabledImpl(Features, "fsgsbase", true);
3333 setFeatureEnabledImpl(Features, "fxsr", true);
3334 setFeatureEnabledImpl(Features, "lzcnt", true);
3335 setFeatureEnabledImpl(Features, "mwaitx", true);
3336 setFeatureEnabledImpl(Features, "movbe", true);
3337 setFeatureEnabledImpl(Features, "pclmul", true);
3338 setFeatureEnabledImpl(Features, "popcnt", true);
3339 setFeatureEnabledImpl(Features, "prfchw", true);
3340 setFeatureEnabledImpl(Features, "rdrnd", true);
3341 setFeatureEnabledImpl(Features, "rdseed", true);
3342 setFeatureEnabledImpl(Features, "sha", true);
3343 setFeatureEnabledImpl(Features, "sse4a", true);
3344 setFeatureEnabledImpl(Features, "xsave", true);
3345 setFeatureEnabledImpl(Features, "xsavec", true);
3346 setFeatureEnabledImpl(Features, "xsaveopt", true);
3347 setFeatureEnabledImpl(Features, "xsaves", true);
3350 setFeatureEnabledImpl(Features, "avx2", true);
3351 setFeatureEnabledImpl(Features, "bmi2", true);
3352 setFeatureEnabledImpl(Features, "mwaitx", true);
3355 setFeatureEnabledImpl(Features, "fsgsbase", true);
3356 setFeatureEnabledImpl(Features, "xsaveopt", true);
3359 setFeatureEnabledImpl(Features, "bmi", true);
3360 setFeatureEnabledImpl(Features, "fma", true);
3361 setFeatureEnabledImpl(Features, "f16c", true);
3362 setFeatureEnabledImpl(Features, "tbm", true);
3365 // xop implies avx, sse4a and fma4.
3366 setFeatureEnabledImpl(Features, "xop", true);
3367 setFeatureEnabledImpl(Features, "lwp", true);
3368 setFeatureEnabledImpl(Features, "lzcnt", true);
3369 setFeatureEnabledImpl(Features, "aes", true);
3370 setFeatureEnabledImpl(Features, "pclmul", true);
3371 setFeatureEnabledImpl(Features, "prfchw", true);
3372 setFeatureEnabledImpl(Features, "cx16", true);
3373 setFeatureEnabledImpl(Features, "fxsr", true);
3374 setFeatureEnabledImpl(Features, "xsave", true);
3377 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
3380 // Can't do this earlier because we need to be able to explicitly enable
3381 // or disable these features and the things that they depend upon.
3383 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
3384 auto I = Features.find("sse4.2");
3385 if (I != Features.end() && I->getValue() &&
3386 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
3388 Features["popcnt"] = true;
3390 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
3391 I = Features.find("3dnow");
3392 if (I != Features.end() && I->getValue() &&
3393 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
3395 Features["prfchw"] = true;
3397 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
3399 I = Features.find("sse");
3400 if (I != Features.end() && I->getValue() &&
3401 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
3403 Features["mmx"] = true;
3408 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
3409 X86SSEEnum Level, bool Enabled) {
3413 Features["avx512f"] = true;
3415 Features["avx2"] = true;
3417 Features["avx"] = true;
3418 Features["xsave"] = true;
3420 Features["sse4.2"] = true;
3422 Features["sse4.1"] = true;
3424 Features["ssse3"] = true;
3426 Features["sse3"] = true;
3428 Features["sse2"] = true;
3430 Features["sse"] = true;
3440 Features["sse"] = false;
3442 Features["sse2"] = Features["pclmul"] = Features["aes"] =
3443 Features["sha"] = false;
3445 Features["sse3"] = false;
3446 setXOPLevel(Features, NoXOP, false);
3448 Features["ssse3"] = false;
3450 Features["sse4.1"] = false;
3452 Features["sse4.2"] = false;
3454 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
3455 Features["xsaveopt"] = false;
3456 setXOPLevel(Features, FMA4, false);
3458 Features["avx2"] = false;
3460 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
3461 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
3462 Features["avx512vl"] = Features["avx512vbmi"] =
3463 Features["avx512ifma"] = false;
3467 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
3468 MMX3DNowEnum Level, bool Enabled) {
3471 case AMD3DNowAthlon:
3472 Features["3dnowa"] = true;
3474 Features["3dnow"] = true;
3476 Features["mmx"] = true;
3486 Features["mmx"] = false;
3488 Features["3dnow"] = false;
3489 case AMD3DNowAthlon:
3490 Features["3dnowa"] = false;
3494 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
3499 Features["xop"] = true;
3501 Features["fma4"] = true;
3502 setSSELevel(Features, AVX, true);
3504 Features["sse4a"] = true;
3505 setSSELevel(Features, SSE3, true);
3515 Features["sse4a"] = false;
3517 Features["fma4"] = false;
3519 Features["xop"] = false;
3523 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
3524 StringRef Name, bool Enabled) {
3525 // This is a bit of a hack to deal with the sse4 target feature when used
3526 // as part of the target attribute. We handle sse4 correctly everywhere
3527 // else. See below for more information on how we handle the sse4 options.
3529 Features[Name] = Enabled;
3531 if (Name == "mmx") {
3532 setMMXLevel(Features, MMX, Enabled);
3533 } else if (Name == "sse") {
3534 setSSELevel(Features, SSE1, Enabled);
3535 } else if (Name == "sse2") {
3536 setSSELevel(Features, SSE2, Enabled);
3537 } else if (Name == "sse3") {
3538 setSSELevel(Features, SSE3, Enabled);
3539 } else if (Name == "ssse3") {
3540 setSSELevel(Features, SSSE3, Enabled);
3541 } else if (Name == "sse4.2") {
3542 setSSELevel(Features, SSE42, Enabled);
3543 } else if (Name == "sse4.1") {
3544 setSSELevel(Features, SSE41, Enabled);
3545 } else if (Name == "3dnow") {
3546 setMMXLevel(Features, AMD3DNow, Enabled);
3547 } else if (Name == "3dnowa") {
3548 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
3549 } else if (Name == "aes") {
3551 setSSELevel(Features, SSE2, Enabled);
3552 } else if (Name == "pclmul") {
3554 setSSELevel(Features, SSE2, Enabled);
3555 } else if (Name == "avx") {
3556 setSSELevel(Features, AVX, Enabled);
3557 } else if (Name == "avx2") {
3558 setSSELevel(Features, AVX2, Enabled);
3559 } else if (Name == "avx512f") {
3560 setSSELevel(Features, AVX512F, Enabled);
3561 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
3562 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
3563 Name == "avx512vbmi" || Name == "avx512ifma") {
3565 setSSELevel(Features, AVX512F, Enabled);
3566 // Enable BWI instruction if VBMI is being enabled.
3567 if (Name == "avx512vbmi" && Enabled)
3568 Features["avx512bw"] = true;
3569 // Also disable VBMI if BWI is being disabled.
3570 if (Name == "avx512bw" && !Enabled)
3571 Features["avx512vbmi"] = false;
3572 } else if (Name == "fma") {
3574 setSSELevel(Features, AVX, Enabled);
3575 } else if (Name == "fma4") {
3576 setXOPLevel(Features, FMA4, Enabled);
3577 } else if (Name == "xop") {
3578 setXOPLevel(Features, XOP, Enabled);
3579 } else if (Name == "sse4a") {
3580 setXOPLevel(Features, SSE4A, Enabled);
3581 } else if (Name == "f16c") {
3583 setSSELevel(Features, AVX, Enabled);
3584 } else if (Name == "sha") {
3586 setSSELevel(Features, SSE2, Enabled);
3587 } else if (Name == "sse4") {
3588 // We can get here via the __target__ attribute since that's not controlled
3589 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
3590 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
3593 setSSELevel(Features, SSE42, Enabled);
3595 setSSELevel(Features, SSE41, Enabled);
3596 } else if (Name == "xsave") {
3598 Features["xsaveopt"] = false;
3599 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
3601 Features["xsave"] = true;
3605 /// handleTargetFeatures - Perform initialization based on the user
3606 /// configured set of features.
3607 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
3608 DiagnosticsEngine &Diags) {
3609 for (const auto &Feature : Features) {
3610 if (Feature[0] != '+')
3613 if (Feature == "+aes") {
3615 } else if (Feature == "+pclmul") {
3617 } else if (Feature == "+lzcnt") {
3619 } else if (Feature == "+rdrnd") {
3621 } else if (Feature == "+fsgsbase") {
3623 } else if (Feature == "+bmi") {
3625 } else if (Feature == "+bmi2") {
3627 } else if (Feature == "+popcnt") {
3629 } else if (Feature == "+rtm") {
3631 } else if (Feature == "+prfchw") {
3633 } else if (Feature == "+rdseed") {
3635 } else if (Feature == "+adx") {
3637 } else if (Feature == "+tbm") {
3639 } else if (Feature == "+lwp") {
3641 } else if (Feature == "+fma") {
3643 } else if (Feature == "+f16c") {
3645 } else if (Feature == "+avx512cd") {
3647 } else if (Feature == "+avx512er") {
3649 } else if (Feature == "+avx512pf") {
3651 } else if (Feature == "+avx512dq") {
3653 } else if (Feature == "+avx512bw") {
3655 } else if (Feature == "+avx512vl") {
3657 } else if (Feature == "+avx512vbmi") {
3658 HasAVX512VBMI = true;
3659 } else if (Feature == "+avx512ifma") {
3660 HasAVX512IFMA = true;
3661 } else if (Feature == "+sha") {
3663 } else if (Feature == "+mpx") {
3665 } else if (Feature == "+movbe") {
3667 } else if (Feature == "+sgx") {
3669 } else if (Feature == "+cx16") {
3671 } else if (Feature == "+fxsr") {
3673 } else if (Feature == "+xsave") {
3675 } else if (Feature == "+xsaveopt") {
3677 } else if (Feature == "+xsavec") {
3679 } else if (Feature == "+xsaves") {
3681 } else if (Feature == "+mwaitx") {
3683 } else if (Feature == "+pku") {
3685 } else if (Feature == "+clflushopt") {
3686 HasCLFLUSHOPT = true;
3687 } else if (Feature == "+clwb") {
3689 } else if (Feature == "+prefetchwt1") {
3690 HasPREFETCHWT1 = true;
3691 } else if (Feature == "+clzero") {
3695 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
3696 .Case("+avx512f", AVX512F)
3697 .Case("+avx2", AVX2)
3699 .Case("+sse4.2", SSE42)
3700 .Case("+sse4.1", SSE41)
3701 .Case("+ssse3", SSSE3)
3702 .Case("+sse3", SSE3)
3703 .Case("+sse2", SSE2)
3706 SSELevel = std::max(SSELevel, Level);
3708 MMX3DNowEnum ThreeDNowLevel =
3709 llvm::StringSwitch<MMX3DNowEnum>(Feature)
3710 .Case("+3dnowa", AMD3DNowAthlon)
3711 .Case("+3dnow", AMD3DNow)
3713 .Default(NoMMX3DNow);
3714 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
3716 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
3718 .Case("+fma4", FMA4)
3719 .Case("+sse4a", SSE4A)
3721 XOPLevel = std::max(XOPLevel, XLevel);
3724 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
3725 // matches the selected sse level.
3726 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
3727 (FPMath == FP_387 && SSELevel >= SSE1)) {
3728 Diags.Report(diag::err_target_unsupported_fpmath) <<
3729 (FPMath == FP_SSE ? "sse" : "387");
3734 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3738 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
3739 /// definitions for this particular subtarget.
3740 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
3741 MacroBuilder &Builder) const {
3742 // Target identification.
3743 if (getTriple().getArch() == llvm::Triple::x86_64) {
3744 Builder.defineMacro("__amd64__");
3745 Builder.defineMacro("__amd64");
3746 Builder.defineMacro("__x86_64");
3747 Builder.defineMacro("__x86_64__");
3748 if (getTriple().getArchName() == "x86_64h") {
3749 Builder.defineMacro("__x86_64h");
3750 Builder.defineMacro("__x86_64h__");
3753 DefineStd(Builder, "i386", Opts);
3756 // Subtarget options.
3757 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
3758 // truly should be based on -mtune options.
3763 // The rest are coming from the i386 define above.
3764 Builder.defineMacro("__tune_i386__");
3770 defineCPUMacros(Builder, "i486");
3773 Builder.defineMacro("__pentium_mmx__");
3774 Builder.defineMacro("__tune_pentium_mmx__");
3778 defineCPUMacros(Builder, "i586");
3779 defineCPUMacros(Builder, "pentium");
3784 Builder.defineMacro("__tune_pentium3__");
3788 Builder.defineMacro("__tune_pentium2__");
3791 Builder.defineMacro("__tune_i686__");
3792 Builder.defineMacro("__tune_pentiumpro__");
3795 Builder.defineMacro("__i686");
3796 Builder.defineMacro("__i686__");
3797 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3798 Builder.defineMacro("__pentiumpro");
3799 Builder.defineMacro("__pentiumpro__");
3803 defineCPUMacros(Builder, "pentium4");
3808 defineCPUMacros(Builder, "nocona");
3812 defineCPUMacros(Builder, "core2");
3815 defineCPUMacros(Builder, "atom");
3818 defineCPUMacros(Builder, "slm");
3822 case CK_SandyBridge:
3826 case CK_SkylakeClient:
3827 // FIXME: Historically, we defined this legacy name, it would be nice to
3828 // remove it at some point. We've never exposed fine-grained names for
3829 // recent primary x86 CPUs, and we should keep it that way.
3830 defineCPUMacros(Builder, "corei7");
3832 case CK_SkylakeServer:
3833 defineCPUMacros(Builder, "skx");
3838 defineCPUMacros(Builder, "knl");
3841 Builder.defineMacro("__tune_lakemont__");
3844 Builder.defineMacro("__k6_2__");
3845 Builder.defineMacro("__tune_k6_2__");
3848 if (CPU != CK_K6_2) { // In case of fallthrough
3849 // FIXME: GCC may be enabling these in cases where some other k6
3850 // architecture is specified but -m3dnow is explicitly provided. The
3851 // exact semantics need to be determined and emulated here.
3852 Builder.defineMacro("__k6_3__");
3853 Builder.defineMacro("__tune_k6_3__");
3857 defineCPUMacros(Builder, "k6");
3860 case CK_AthlonThunderbird:
3864 defineCPUMacros(Builder, "athlon");
3865 if (SSELevel != NoSSE) {
3866 Builder.defineMacro("__athlon_sse__");
3867 Builder.defineMacro("__tune_athlon_sse__");
3874 case CK_OpteronSSE3:
3876 case CK_Athlon64SSE3:
3878 defineCPUMacros(Builder, "k8");
3881 defineCPUMacros(Builder, "amdfam10");
3884 defineCPUMacros(Builder, "btver1");
3887 defineCPUMacros(Builder, "btver2");
3890 defineCPUMacros(Builder, "bdver1");
3893 defineCPUMacros(Builder, "bdver2");
3896 defineCPUMacros(Builder, "bdver3");
3899 defineCPUMacros(Builder, "bdver4");
3902 defineCPUMacros(Builder, "znver1");
3905 defineCPUMacros(Builder, "geode");
3909 // Target properties.
3910 Builder.defineMacro("__REGISTER_PREFIX__", "");
3912 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3913 // functions in glibc header files that use FP Stack inline asm which the
3914 // backend can't deal with (PR879).
3915 Builder.defineMacro("__NO_MATH_INLINES");
3918 Builder.defineMacro("__AES__");
3921 Builder.defineMacro("__PCLMUL__");
3924 Builder.defineMacro("__LZCNT__");
3927 Builder.defineMacro("__RDRND__");
3930 Builder.defineMacro("__FSGSBASE__");
3933 Builder.defineMacro("__BMI__");
3936 Builder.defineMacro("__BMI2__");
3939 Builder.defineMacro("__POPCNT__");
3942 Builder.defineMacro("__RTM__");
3945 Builder.defineMacro("__PRFCHW__");
3948 Builder.defineMacro("__RDSEED__");
3951 Builder.defineMacro("__ADX__");
3954 Builder.defineMacro("__TBM__");
3957 Builder.defineMacro("__LWP__");
3960 Builder.defineMacro("__MWAITX__");
3964 Builder.defineMacro("__XOP__");
3966 Builder.defineMacro("__FMA4__");
3968 Builder.defineMacro("__SSE4A__");
3974 Builder.defineMacro("__FMA__");
3977 Builder.defineMacro("__F16C__");
3980 Builder.defineMacro("__AVX512CD__");
3982 Builder.defineMacro("__AVX512ER__");
3984 Builder.defineMacro("__AVX512PF__");
3986 Builder.defineMacro("__AVX512DQ__");
3988 Builder.defineMacro("__AVX512BW__");
3990 Builder.defineMacro("__AVX512VL__");
3992 Builder.defineMacro("__AVX512VBMI__");
3994 Builder.defineMacro("__AVX512IFMA__");
3997 Builder.defineMacro("__SHA__");
4000 Builder.defineMacro("__FXSR__");
4002 Builder.defineMacro("__XSAVE__");
4004 Builder.defineMacro("__XSAVEOPT__");
4006 Builder.defineMacro("__XSAVEC__");
4008 Builder.defineMacro("__XSAVES__");
4010 Builder.defineMacro("__PKU__");
4012 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
4014 Builder.defineMacro("__CLFLUSHOPT__");
4016 Builder.defineMacro("__CLWB__");
4018 Builder.defineMacro("__MPX__");
4020 Builder.defineMacro("__SGX__");
4022 Builder.defineMacro("__PREFETCHWT1__");
4024 Builder.defineMacro("__CLZERO__");
4026 // Each case falls through to the previous one here.
4029 Builder.defineMacro("__AVX512F__");
4031 Builder.defineMacro("__AVX2__");
4033 Builder.defineMacro("__AVX__");
4035 Builder.defineMacro("__SSE4_2__");
4037 Builder.defineMacro("__SSE4_1__");
4039 Builder.defineMacro("__SSSE3__");
4041 Builder.defineMacro("__SSE3__");
4043 Builder.defineMacro("__SSE2__");
4044 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
4046 Builder.defineMacro("__SSE__");
4047 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
4052 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
4062 Builder.defineMacro("_M_IX86_FP", Twine(2));
4065 Builder.defineMacro("_M_IX86_FP", Twine(1));
4068 Builder.defineMacro("_M_IX86_FP", Twine(0));
4072 // Each case falls through to the previous one here.
4073 switch (MMX3DNowLevel) {
4074 case AMD3DNowAthlon:
4075 Builder.defineMacro("__3dNOW_A__");
4077 Builder.defineMacro("__3dNOW__");
4079 Builder.defineMacro("__MMX__");
4084 if (CPU >= CK_i486) {
4085 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4086 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4087 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4090 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4093 bool X86TargetInfo::hasFeature(StringRef Feature) const {
4094 return llvm::StringSwitch<bool>(Feature)
4095 .Case("aes", HasAES)
4096 .Case("avx", SSELevel >= AVX)
4097 .Case("avx2", SSELevel >= AVX2)
4098 .Case("avx512f", SSELevel >= AVX512F)
4099 .Case("avx512cd", HasAVX512CD)
4100 .Case("avx512er", HasAVX512ER)
4101 .Case("avx512pf", HasAVX512PF)
4102 .Case("avx512dq", HasAVX512DQ)
4103 .Case("avx512bw", HasAVX512BW)
4104 .Case("avx512vl", HasAVX512VL)
4105 .Case("avx512vbmi", HasAVX512VBMI)
4106 .Case("avx512ifma", HasAVX512IFMA)
4107 .Case("bmi", HasBMI)
4108 .Case("bmi2", HasBMI2)
4109 .Case("clflushopt", HasCLFLUSHOPT)
4110 .Case("clwb", HasCLWB)
4111 .Case("clzero", HasCLZERO)
4112 .Case("cx16", HasCX16)
4113 .Case("f16c", HasF16C)
4114 .Case("fma", HasFMA)
4115 .Case("fma4", XOPLevel >= FMA4)
4116 .Case("fsgsbase", HasFSGSBASE)
4117 .Case("fxsr", HasFXSR)
4118 .Case("lzcnt", HasLZCNT)
4119 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
4120 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
4121 .Case("mmx", MMX3DNowLevel >= MMX)
4122 .Case("movbe", HasMOVBE)
4123 .Case("mpx", HasMPX)
4124 .Case("pclmul", HasPCLMUL)
4125 .Case("pku", HasPKU)
4126 .Case("popcnt", HasPOPCNT)
4127 .Case("prefetchwt1", HasPREFETCHWT1)
4128 .Case("prfchw", HasPRFCHW)
4129 .Case("rdrnd", HasRDRND)
4130 .Case("rdseed", HasRDSEED)
4131 .Case("rtm", HasRTM)
4132 .Case("sgx", HasSGX)
4133 .Case("sha", HasSHA)
4134 .Case("sse", SSELevel >= SSE1)
4135 .Case("sse2", SSELevel >= SSE2)
4136 .Case("sse3", SSELevel >= SSE3)
4137 .Case("ssse3", SSELevel >= SSSE3)
4138 .Case("sse4.1", SSELevel >= SSE41)
4139 .Case("sse4.2", SSELevel >= SSE42)
4140 .Case("sse4a", XOPLevel >= SSE4A)
4141 .Case("tbm", HasTBM)
4142 .Case("lwp", HasLWP)
4144 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
4145 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
4146 .Case("xop", XOPLevel >= XOP)
4147 .Case("xsave", HasXSAVE)
4148 .Case("xsavec", HasXSAVEC)
4149 .Case("xsaves", HasXSAVES)
4150 .Case("xsaveopt", HasXSAVEOPT)
4154 // We can't use a generic validation scheme for the features accepted here
4155 // versus subtarget features accepted in the target attribute because the
4156 // bitfield structure that's initialized in the runtime only supports the
4157 // below currently rather than the full range of subtarget features. (See
4158 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
4159 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
4160 return llvm::StringSwitch<bool>(FeatureStr)
4163 .Case("popcnt", true)
4167 .Case("ssse3", true)
4168 .Case("sse4.1", true)
4169 .Case("sse4.2", true)
4172 .Case("sse4a", true)
4176 .Case("avx512f", true)
4180 .Case("pclmul", true)
4181 .Case("avx512vl", true)
4182 .Case("avx512bw", true)
4183 .Case("avx512dq", true)
4184 .Case("avx512cd", true)
4185 .Case("avx512er", true)
4186 .Case("avx512pf", true)
4187 .Case("avx512vbmi", true)
4188 .Case("avx512ifma", true)
4193 X86TargetInfo::validateAsmConstraint(const char *&Name,
4194 TargetInfo::ConstraintInfo &Info) const {
4196 default: return false;
4197 // Constant constraints.
4198 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
4200 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
4201 // x86_64 instructions.
4203 Info.setRequiresImmediate();
4206 Info.setRequiresImmediate(0, 31);
4209 Info.setRequiresImmediate(0, 63);
4212 Info.setRequiresImmediate(-128, 127);
4215 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) });
4218 Info.setRequiresImmediate(0, 3);
4221 Info.setRequiresImmediate(0, 255);
4224 Info.setRequiresImmediate(0, 127);
4226 // Register constraints.
4227 case 'Y': // 'Y' is the first character for several 2-character constraints.
4228 // Shift the pointer to the second character of the constraint.
4233 case '0': // First SSE register.
4234 case 't': // Any SSE register, when SSE2 is enabled.
4235 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
4236 case 'm': // Any MMX register, when inter-unit moves enabled.
4237 case 'k': // AVX512 arch mask registers: k1-k7.
4238 Info.setAllowsRegister();
4241 case 'f': // Any x87 floating point stack register.
4242 // Constraint 'f' cannot be used for output operands.
4243 if (Info.ConstraintStr[0] == '=')
4245 Info.setAllowsRegister();
4253 case 'A': // edx:eax.
4254 case 't': // Top of floating point stack.
4255 case 'u': // Second from top of floating point stack.
4256 case 'q': // Any register accessible as [r]l: a, b, c, and d.
4257 case 'y': // Any MMX register.
4258 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
4259 case 'x': // Any SSE register.
4260 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0
4261 // for intermideate k reg operations).
4262 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
4263 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
4264 case 'l': // "Index" registers: any general register that can be used as an
4265 // index in a base+index memory access.
4266 Info.setAllowsRegister();
4268 // Floating point constant constraints.
4269 case 'C': // SSE floating point constant.
4270 case 'G': // x87 floating point constant.
4275 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
4276 unsigned Size) const {
4277 // Strip off constraint modifiers.
4278 while (Constraint[0] == '=' ||
4279 Constraint[0] == '+' ||
4280 Constraint[0] == '&')
4281 Constraint = Constraint.substr(1);
4283 return validateOperandSize(Constraint, Size);
4286 bool X86TargetInfo::validateInputSize(StringRef Constraint,
4287 unsigned Size) const {
4288 return validateOperandSize(Constraint, Size);
4291 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
4292 unsigned Size) const {
4293 switch (Constraint[0]) {
4296 // Registers k0-k7 (AVX512) size limit is 64 bit.
4305 if (SSELevel >= AVX512F)
4306 // 512-bit zmm registers can be used if target supports AVX512F.
4307 return Size <= 512U;
4308 else if (SSELevel >= AVX)
4309 // 256-bit ymm registers can be used if target supports AVX.
4310 return Size <= 256U;
4311 return Size <= 128U;
4313 // 'Y' is the first character for several 2-character constraints.
4314 switch (Constraint[1]) {
4317 // 'Ym' is synonymous with 'y'.
4322 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
4323 if (SSELevel >= AVX512F)
4324 return Size <= 512U;
4325 else if (SSELevel >= AVX)
4326 return Size <= 256U;
4327 return SSELevel >= SSE2 && Size <= 128U;
4336 X86TargetInfo::convertConstraint(const char *&Constraint) const {
4337 switch (*Constraint) {
4338 case 'a': return std::string("{ax}");
4339 case 'b': return std::string("{bx}");
4340 case 'c': return std::string("{cx}");
4341 case 'd': return std::string("{dx}");
4342 case 'S': return std::string("{si}");
4343 case 'D': return std::string("{di}");
4344 case 'p': // address
4345 return std::string("im");
4346 case 't': // top of floating point stack.
4347 return std::string("{st}");
4348 case 'u': // second from top of floating point stack.
4349 return std::string("{st(1)}"); // second from top of floating point stack.
4351 switch (Constraint[1]) {
4353 // Break from inner switch and fall through (copy single char),
4354 // continue parsing after copying the current constraint into
4355 // the return string.
4358 // "^" hints llvm that this is a 2 letter constraint.
4359 // "Constraint++" is used to promote the string iterator
4360 // to the next constraint.
4361 return std::string("^") + std::string(Constraint++, 2);
4365 return std::string(1, *Constraint);
4369 // X86-32 generic target
4370 class X86_32TargetInfo : public X86TargetInfo {
4372 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4373 : X86TargetInfo(Triple, Opts) {
4374 DoubleAlign = LongLongAlign = 32;
4375 LongDoubleWidth = 96;
4376 LongDoubleAlign = 32;
4377 SuitableAlign = 128;
4378 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128");
4379 SizeType = UnsignedInt;
4380 PtrDiffType = SignedInt;
4381 IntPtrType = SignedInt;
4384 // Use fpret for all types.
4385 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
4386 (1 << TargetInfo::Double) |
4387 (1 << TargetInfo::LongDouble));
4389 // x86-32 has atomics up to 8 bytes
4390 // FIXME: Check that we actually have cmpxchg8b before setting
4391 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
4392 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4394 BuiltinVaListKind getBuiltinVaListKind() const override {
4395 return TargetInfo::CharPtrBuiltinVaList;
4398 int getEHDataRegisterNumber(unsigned RegNo) const override {
4399 if (RegNo == 0) return 0;
4400 if (RegNo == 1) return 2;
4403 bool validateOperandSize(StringRef Constraint,
4404 unsigned Size) const override {
4405 switch (Constraint[0]) {
4421 return X86TargetInfo::validateOperandSize(Constraint, Size);
4423 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4424 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
4425 Builtin::FirstTSBuiltin + 1);
4429 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
4431 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4432 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {}
4434 unsigned getFloatEvalMethod() const override {
4435 unsigned Major, Minor, Micro;
4436 getTriple().getOSVersion(Major, Minor, Micro);
4437 // New NetBSD uses the default rounding mode.
4438 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
4439 return X86_32TargetInfo::getFloatEvalMethod();
4440 // NetBSD before 6.99.26 defaults to "double" rounding.
4445 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
4447 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4448 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4449 SizeType = UnsignedLong;
4450 IntPtrType = SignedLong;
4451 PtrDiffType = SignedLong;
4455 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
4457 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4458 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4459 SizeType = UnsignedLong;
4460 IntPtrType = SignedLong;
4461 PtrDiffType = SignedLong;
4465 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
4467 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4468 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4469 LongDoubleWidth = 128;
4470 LongDoubleAlign = 128;
4471 SuitableAlign = 128;
4472 MaxVectorAlign = 256;
4473 // The watchOS simulator uses the builtin bool type for Objective-C.
4474 llvm::Triple T = llvm::Triple(Triple);
4476 UseSignedCharForObjCBool = false;
4477 SizeType = UnsignedLong;
4478 IntPtrType = SignedLong;
4479 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128");
4480 HasAlignMac68kSupport = true;
4483 bool handleTargetFeatures(std::vector<std::string> &Features,
4484 DiagnosticsEngine &Diags) override {
4485 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features,
4488 // We now know the features we have: we can decide how to align vectors.
4490 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4495 // x86-32 Windows target
4496 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
4498 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4499 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4500 WCharType = UnsignedShort;
4501 DoubleAlign = LongLongAlign = 64;
4503 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4504 resetDataLayout(IsWinCOFF
4505 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
4506 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4508 void getTargetDefines(const LangOptions &Opts,
4509 MacroBuilder &Builder) const override {
4510 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4514 // x86-32 Windows Visual Studio target
4515 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
4517 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple,
4518 const TargetOptions &Opts)
4519 : WindowsX86_32TargetInfo(Triple, Opts) {
4520 LongDoubleWidth = LongDoubleAlign = 64;
4521 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4523 void getTargetDefines(const LangOptions &Opts,
4524 MacroBuilder &Builder) const override {
4525 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4526 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
4527 // The value of the following reflects processor type.
4528 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
4529 // We lost the original triple, so we use the default.
4530 Builder.defineMacro("_M_IX86", "600");
4534 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4535 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang
4536 // supports __declspec natively under -fms-extensions, but we define a no-op
4537 // __declspec macro anyway for pre-processor compatibility.
4538 if (Opts.MicrosoftExt)
4539 Builder.defineMacro("__declspec", "__declspec");
4541 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
4543 if (!Opts.MicrosoftExt) {
4544 // Provide macros for all the calling convention keywords. Provide both
4545 // single and double underscore prefixed variants. These are available on
4546 // x64 as well as x86, even though they have no effect.
4547 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
4548 for (const char *CC : CCs) {
4549 std::string GCCSpelling = "__attribute__((__";
4551 GCCSpelling += "__))";
4552 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
4553 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
4558 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4559 Builder.defineMacro("__MSVCRT__");
4560 Builder.defineMacro("__MINGW32__");
4561 addCygMingDefines(Opts, Builder);
4564 // x86-32 MinGW target
4565 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
4567 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4568 : WindowsX86_32TargetInfo(Triple, Opts) {}
4569 void getTargetDefines(const LangOptions &Opts,
4570 MacroBuilder &Builder) const override {
4571 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4572 DefineStd(Builder, "WIN32", Opts);
4573 DefineStd(Builder, "WINNT", Opts);
4574 Builder.defineMacro("_X86_");
4575 addMinGWDefines(Opts, Builder);
4579 // x86-32 Cygwin target
4580 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
4582 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4583 : X86_32TargetInfo(Triple, Opts) {
4584 WCharType = UnsignedShort;
4585 DoubleAlign = LongLongAlign = 64;
4586 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4588 void getTargetDefines(const LangOptions &Opts,
4589 MacroBuilder &Builder) const override {
4590 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4591 Builder.defineMacro("_X86_");
4592 Builder.defineMacro("__CYGWIN__");
4593 Builder.defineMacro("__CYGWIN32__");
4594 addCygMingDefines(Opts, Builder);
4595 DefineStd(Builder, "unix", Opts);
4597 Builder.defineMacro("_GNU_SOURCE");
4601 // x86-32 Haiku target
4602 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> {
4604 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4605 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4607 void getTargetDefines(const LangOptions &Opts,
4608 MacroBuilder &Builder) const override {
4609 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4610 Builder.defineMacro("__INTEL__");
4614 // X86-32 MCU target
4615 class MCUX86_32TargetInfo : public X86_32TargetInfo {
4617 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4618 : X86_32TargetInfo(Triple, Opts) {
4619 LongDoubleWidth = 64;
4620 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4621 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32");
4622 WIntType = UnsignedInt;
4625 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4626 // On MCU we support only C calling convention.
4627 return CC == CC_C ? CCCR_OK : CCCR_Warning;
4630 void getTargetDefines(const LangOptions &Opts,
4631 MacroBuilder &Builder) const override {
4632 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4633 Builder.defineMacro("__iamcu");
4634 Builder.defineMacro("__iamcu__");
4637 bool allowsLargerPreferedTypeAlignment() const override {
4643 template<typename Target>
4644 class RTEMSTargetInfo : public OSTargetInfo<Target> {
4646 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4647 MacroBuilder &Builder) const override {
4648 // RTEMS defines; list based off of gcc output
4650 Builder.defineMacro("__rtems__");
4651 Builder.defineMacro("__ELF__");
4655 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4656 : OSTargetInfo<Target>(Triple, Opts) {
4657 switch (Triple.getArch()) {
4659 case llvm::Triple::x86:
4660 // this->MCountName = ".mcount";
4662 case llvm::Triple::mips:
4663 case llvm::Triple::mipsel:
4664 case llvm::Triple::ppc:
4665 case llvm::Triple::ppc64:
4666 case llvm::Triple::ppc64le:
4667 // this->MCountName = "_mcount";
4669 case llvm::Triple::arm:
4670 // this->MCountName = "__mcount";
4676 // x86-32 RTEMS target
4677 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
4679 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4680 : X86_32TargetInfo(Triple, Opts) {
4681 SizeType = UnsignedLong;
4682 IntPtrType = SignedLong;
4683 PtrDiffType = SignedLong;
4685 void getTargetDefines(const LangOptions &Opts,
4686 MacroBuilder &Builder) const override {
4687 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4688 Builder.defineMacro("__INTEL__");
4689 Builder.defineMacro("__rtems__");
4693 // x86-64 generic target
4694 class X86_64TargetInfo : public X86TargetInfo {
4696 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4697 : X86TargetInfo(Triple, Opts) {
4698 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
4700 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4701 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
4702 LongDoubleWidth = 128;
4703 LongDoubleAlign = 128;
4704 LargeArrayMinWidth = 128;
4705 LargeArrayAlign = 128;
4706 SuitableAlign = 128;
4707 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
4708 PtrDiffType = IsX32 ? SignedInt : SignedLong;
4709 IntPtrType = IsX32 ? SignedInt : SignedLong;
4710 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
4711 Int64Type = IsX32 ? SignedLongLong : SignedLong;
4714 // Pointers are 32-bit in x32.
4715 resetDataLayout(IsX32
4716 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
4717 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
4718 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128");
4720 // Use fpret only for long double.
4721 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
4723 // Use fp2ret for _Complex long double.
4724 ComplexLongDoubleUsesFP2Ret = true;
4726 // Make __builtin_ms_va_list available.
4727 HasBuiltinMSVaList = true;
4729 // x86-64 has atomics up to 16 bytes.
4730 MaxAtomicPromoteWidth = 128;
4731 MaxAtomicInlineWidth = 128;
4733 BuiltinVaListKind getBuiltinVaListKind() const override {
4734 return TargetInfo::X86_64ABIBuiltinVaList;
4737 int getEHDataRegisterNumber(unsigned RegNo) const override {
4738 if (RegNo == 0) return 0;
4739 if (RegNo == 1) return 1;
4743 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4747 case CC_X86VectorCall:
4748 case CC_IntelOclBicc:
4749 case CC_X86_64Win64:
4750 case CC_PreserveMost:
4751 case CC_PreserveAll:
4755 return CCCR_Warning;
4759 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
4763 // for x32 we need it here explicitly
4764 bool hasInt128Type() const override { return true; }
4765 unsigned getUnwindWordWidth() const override { return 64; }
4766 unsigned getRegisterWidth() const override { return 64; }
4768 bool validateGlobalRegisterVariable(StringRef RegName,
4770 bool &HasSizeMismatch) const override {
4771 // rsp and rbp are the only 64-bit registers the x86 backend can currently
4773 if (RegName.equals("rsp") || RegName.equals("rbp")) {
4774 // Check that the register size is 64-bit.
4775 HasSizeMismatch = RegSize != 64;
4779 // Check if the register is a 32-bit register the backend can handle.
4780 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize,
4783 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4784 return llvm::makeArrayRef(BuiltinInfoX86,
4785 X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
4789 // x86-64 Windows target
4790 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
4792 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4793 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4794 WCharType = UnsignedShort;
4795 LongWidth = LongAlign = 32;
4796 DoubleAlign = LongLongAlign = 64;
4797 IntMaxType = SignedLongLong;
4798 Int64Type = SignedLongLong;
4799 SizeType = UnsignedLongLong;
4800 PtrDiffType = SignedLongLong;
4801 IntPtrType = SignedLongLong;
4804 void getTargetDefines(const LangOptions &Opts,
4805 MacroBuilder &Builder) const override {
4806 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
4807 Builder.defineMacro("_WIN64");
4810 BuiltinVaListKind getBuiltinVaListKind() const override {
4811 return TargetInfo::CharPtrBuiltinVaList;
4814 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4817 case CC_X86ThisCall:
4818 case CC_X86FastCall:
4821 case CC_X86VectorCall:
4822 case CC_IntelOclBicc:
4828 return CCCR_Warning;
4833 // x86-64 Windows Visual Studio target
4834 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
4836 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple,
4837 const TargetOptions &Opts)
4838 : WindowsX86_64TargetInfo(Triple, Opts) {
4839 LongDoubleWidth = LongDoubleAlign = 64;
4840 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4842 void getTargetDefines(const LangOptions &Opts,
4843 MacroBuilder &Builder) const override {
4844 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4845 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
4846 Builder.defineMacro("_M_X64", "100");
4847 Builder.defineMacro("_M_AMD64", "100");
4851 // x86-64 MinGW target
4852 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
4854 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4855 : WindowsX86_64TargetInfo(Triple, Opts) {
4856 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
4857 // with x86 FP ops. Weird.
4858 LongDoubleWidth = LongDoubleAlign = 128;
4859 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
4862 void getTargetDefines(const LangOptions &Opts,
4863 MacroBuilder &Builder) const override {
4864 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4865 DefineStd(Builder, "WIN64", Opts);
4866 Builder.defineMacro("__MINGW64__");
4867 addMinGWDefines(Opts, Builder);
4869 // GCC defines this macro when it is using __gxx_personality_seh0.
4870 if (!Opts.SjLjExceptions)
4871 Builder.defineMacro("__SEH__");
4875 // x86-64 Cygwin target
4876 class CygwinX86_64TargetInfo : public X86_64TargetInfo {
4878 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4879 : X86_64TargetInfo(Triple, Opts) {
4880 TLSSupported = false;
4881 WCharType = UnsignedShort;
4883 void getTargetDefines(const LangOptions &Opts,
4884 MacroBuilder &Builder) const override {
4885 X86_64TargetInfo::getTargetDefines(Opts, Builder);
4886 Builder.defineMacro("__x86_64__");
4887 Builder.defineMacro("__CYGWIN__");
4888 Builder.defineMacro("__CYGWIN64__");
4889 addCygMingDefines(Opts, Builder);
4890 DefineStd(Builder, "unix", Opts);
4892 Builder.defineMacro("_GNU_SOURCE");
4894 // GCC defines this macro when it is using __gxx_personality_seh0.
4895 if (!Opts.SjLjExceptions)
4896 Builder.defineMacro("__SEH__");
4900 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
4902 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4903 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4904 Int64Type = SignedLongLong;
4905 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
4906 llvm::Triple T = llvm::Triple(Triple);
4908 UseSignedCharForObjCBool = false;
4909 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128");
4912 bool handleTargetFeatures(std::vector<std::string> &Features,
4913 DiagnosticsEngine &Diags) override {
4914 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features,
4917 // We now know the features we have: we can decide how to align vectors.
4919 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4924 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
4926 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4927 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4928 IntMaxType = SignedLongLong;
4929 Int64Type = SignedLongLong;
4933 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
4935 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4936 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4937 IntMaxType = SignedLongLong;
4938 Int64Type = SignedLongLong;
4942 class ARMTargetInfo : public TargetInfo {
4943 // Possible FPU choices.
4952 // Possible HWDiv features.
4954 HWDivThumb = (1 << 0),
4958 static bool FPUModeIsVFP(FPUMode Mode) {
4959 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
4962 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4963 static const char * const GCCRegNames[];
4965 std::string ABI, CPU;
4967 StringRef CPUProfile;
4977 unsigned ArchKind = llvm::ARM::AK_ARMV4T;
4978 unsigned ArchProfile;
4979 unsigned ArchVersion;
4983 unsigned IsAAPCS : 1;
4986 // Initialized via features.
4987 unsigned SoftFloat : 1;
4988 unsigned SoftFloatABI : 1;
4991 unsigned Crypto : 1;
4993 unsigned Unaligned : 1;
4996 LDREX_B = (1 << 0), /// byte (8-bit)
4997 LDREX_H = (1 << 1), /// half (16-bit)
4998 LDREX_W = (1 << 2), /// word (32-bit)
4999 LDREX_D = (1 << 3), /// double (64-bit)
5004 // ACLE 6.5.1 Hardware floating point
5006 HW_FP_HP = (1 << 1), /// half (16-bit)
5007 HW_FP_SP = (1 << 2), /// single (32-bit)
5008 HW_FP_DP = (1 << 3), /// double (64-bit)
5012 static const Builtin::Info BuiltinInfo[];
5014 void setABIAAPCS() {
5017 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
5018 const llvm::Triple &T = getTriple();
5020 // size_t is unsigned long on MachO-derived environments, NetBSD,
5021 // OpenBSD and Bitrig.
5022 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
5023 T.getOS() == llvm::Triple::OpenBSD ||
5024 T.getOS() == llvm::Triple::Bitrig)
5025 SizeType = UnsignedLong;
5027 SizeType = UnsignedInt;
5029 switch (T.getOS()) {
5030 case llvm::Triple::NetBSD:
5031 case llvm::Triple::OpenBSD:
5032 WCharType = SignedInt;
5034 case llvm::Triple::Win32:
5035 WCharType = UnsignedShort;
5037 case llvm::Triple::Linux:
5039 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
5040 WCharType = UnsignedInt;
5044 UseBitFieldTypeAlignment = true;
5046 ZeroLengthBitfieldBoundary = 0;
5048 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
5049 // so set preferred for small types to 32.
5050 if (T.isOSBinFormatMachO()) {
5051 resetDataLayout(BigEndian
5052 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
5053 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
5054 } else if (T.isOSWindows()) {
5055 assert(!BigEndian && "Windows on ARM does not support big endian");
5064 } else if (T.isOSNaCl()) {
5065 assert(!BigEndian && "NaCl on ARM does not support big endian");
5066 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128");
5068 resetDataLayout(BigEndian
5069 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
5070 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
5073 // FIXME: Enumerated types are variable width in straight AAPCS.
5076 void setABIAPCS(bool IsAAPCS16) {
5077 const llvm::Triple &T = getTriple();
5082 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
5084 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
5086 // size_t is unsigned int on FreeBSD.
5087 if (T.getOS() == llvm::Triple::FreeBSD)
5088 SizeType = UnsignedInt;
5090 SizeType = UnsignedLong;
5092 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
5093 WCharType = SignedInt;
5095 // Do not respect the alignment of bit-field types when laying out
5096 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
5097 UseBitFieldTypeAlignment = false;
5099 /// gcc forces the alignment to 4 bytes, regardless of the type of the
5100 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
5102 ZeroLengthBitfieldBoundary = 32;
5104 if (T.isOSBinFormatMachO() && IsAAPCS16) {
5105 assert(!BigEndian && "AAPCS16 does not support big-endian");
5106 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128");
5107 } else if (T.isOSBinFormatMachO())
5110 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
5111 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
5115 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
5116 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
5118 // FIXME: Override "preferred align" for double and long long.
5121 void setArchInfo() {
5122 StringRef ArchName = getTriple().getArchName();
5124 ArchISA = llvm::ARM::parseArchISA(ArchName);
5125 CPU = llvm::ARM::getDefaultCPU(ArchName);
5126 unsigned AK = llvm::ARM::parseArch(ArchName);
5127 if (AK != llvm::ARM::AK_INVALID)
5129 setArchInfo(ArchKind);
5132 void setArchInfo(unsigned Kind) {
5135 // cache TargetParser info
5137 SubArch = llvm::ARM::getSubArch(ArchKind);
5138 ArchProfile = llvm::ARM::parseArchProfile(SubArch);
5139 ArchVersion = llvm::ARM::parseArchVersion(SubArch);
5141 // cache CPU related strings
5142 CPUAttr = getCPUAttr();
5143 CPUProfile = getCPUProfile();
5147 // when triple does not specify a sub arch,
5148 // then we are not using inline atomics
5149 bool ShouldUseInlineAtomic =
5150 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) ||
5151 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
5152 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
5153 if (ArchProfile == llvm::ARM::PK_M) {
5154 MaxAtomicPromoteWidth = 32;
5155 if (ShouldUseInlineAtomic)
5156 MaxAtomicInlineWidth = 32;
5159 MaxAtomicPromoteWidth = 64;
5160 if (ShouldUseInlineAtomic)
5161 MaxAtomicInlineWidth = 64;
5165 bool isThumb() const {
5166 return (ArchISA == llvm::ARM::IK_THUMB);
5169 bool supportsThumb() const {
5170 return CPUAttr.count('T') || ArchVersion >= 6;
5173 bool supportsThumb2() const {
5174 return CPUAttr.equals("6T2") ||
5175 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE"));
5178 StringRef getCPUAttr() const {
5179 // For most sub-arches, the build attribute CPU name is enough.
5180 // For Cortex variants, it's slightly different.
5183 return llvm::ARM::getCPUAttr(ArchKind);
5184 case llvm::ARM::AK_ARMV6M:
5186 case llvm::ARM::AK_ARMV7S:
5188 case llvm::ARM::AK_ARMV7A:
5190 case llvm::ARM::AK_ARMV7R:
5192 case llvm::ARM::AK_ARMV7M:
5194 case llvm::ARM::AK_ARMV7EM:
5196 case llvm::ARM::AK_ARMV7VE:
5198 case llvm::ARM::AK_ARMV8A:
5200 case llvm::ARM::AK_ARMV8_1A:
5202 case llvm::ARM::AK_ARMV8_2A:
5204 case llvm::ARM::AK_ARMV8MBaseline:
5206 case llvm::ARM::AK_ARMV8MMainline:
5208 case llvm::ARM::AK_ARMV8R:
5213 StringRef getCPUProfile() const {
5214 switch(ArchProfile) {
5215 case llvm::ARM::PK_A:
5217 case llvm::ARM::PK_R:
5219 case llvm::ARM::PK_M:
5227 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5228 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0),
5231 switch (getTriple().getOS()) {
5232 case llvm::Triple::NetBSD:
5233 case llvm::Triple::OpenBSD:
5234 PtrDiffType = SignedLong;
5237 PtrDiffType = SignedInt;
5241 // Cache arch related info.
5244 // {} in inline assembly are neon specifiers, not assembly variant
5246 NoAsmVariants = true;
5248 // FIXME: This duplicates code from the driver that sets the -target-abi
5249 // option - this code is used if -target-abi isn't passed and should
5250 // be unified in some way.
5251 if (Triple.isOSBinFormatMachO()) {
5252 // The backend is hardwired to assume AAPCS for M-class processors, ensure
5253 // the frontend matches that.
5254 if (Triple.getEnvironment() == llvm::Triple::EABI ||
5255 Triple.getOS() == llvm::Triple::UnknownOS ||
5256 ArchProfile == llvm::ARM::PK_M) {
5258 } else if (Triple.isWatchABI()) {
5263 } else if (Triple.isOSWindows()) {
5264 // FIXME: this is invalid for WindowsCE
5267 // Select the default based on the platform.
5268 switch (Triple.getEnvironment()) {
5269 case llvm::Triple::Android:
5270 case llvm::Triple::GNUEABI:
5271 case llvm::Triple::GNUEABIHF:
5272 case llvm::Triple::MuslEABI:
5273 case llvm::Triple::MuslEABIHF:
5274 setABI("aapcs-linux");
5276 case llvm::Triple::EABIHF:
5277 case llvm::Triple::EABI:
5280 case llvm::Triple::GNU:
5284 if (Triple.getOS() == llvm::Triple::NetBSD)
5286 else if (Triple.getOS() == llvm::Triple::OpenBSD)
5287 setABI("aapcs-linux");
5294 // ARM targets default to using the ARM C++ ABI.
5295 TheCXXABI.set(TargetCXXABI::GenericARM);
5297 // ARM has atomics up to 8 bytes
5300 // Do force alignment of members that follow zero length bitfields. If
5301 // the alignment of the zero-length bitfield is greater than the member
5302 // that follows it, `bar', `bar' will be aligned as the type of the
5303 // zero length bitfield.
5304 UseZeroLengthBitfieldAlignment = true;
5306 if (Triple.getOS() == llvm::Triple::Linux ||
5307 Triple.getOS() == llvm::Triple::UnknownOS)
5309 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount";
5312 StringRef getABI() const override { return ABI; }
5314 bool setABI(const std::string &Name) override {
5317 // The defaults (above) are for AAPCS, check if we need to change them.
5319 // FIXME: We need support for -meabi... we could just mangle it into the
5321 if (Name == "apcs-gnu" || Name == "aapcs16") {
5322 setABIAPCS(Name == "aapcs16");
5325 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
5332 // FIXME: This should be based on Arch attributes, not CPU names.
5334 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
5336 const std::vector<std::string> &FeaturesVec) const override {
5338 std::vector<StringRef> TargetFeatures;
5339 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName());
5341 // get default FPU features
5342 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
5343 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
5345 // get default Extension features
5346 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
5347 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
5349 for (auto Feature : TargetFeatures)
5350 if (Feature[0] == '+')
5351 Features[Feature.drop_front(1)] = true;
5353 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
5356 bool handleTargetFeatures(std::vector<std::string> &Features,
5357 DiagnosticsEngine &Diags) override {
5363 SoftFloat = SoftFloatABI = false;
5366 // This does not diagnose illegal cases like having both
5367 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
5368 uint32_t HW_FP_remove = 0;
5369 for (const auto &Feature : Features) {
5370 if (Feature == "+soft-float") {
5372 } else if (Feature == "+soft-float-abi") {
5373 SoftFloatABI = true;
5374 } else if (Feature == "+vfp2") {
5376 HW_FP |= HW_FP_SP | HW_FP_DP;
5377 } else if (Feature == "+vfp3") {
5379 HW_FP |= HW_FP_SP | HW_FP_DP;
5380 } else if (Feature == "+vfp4") {
5382 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
5383 } else if (Feature == "+fp-armv8") {
5385 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
5386 } else if (Feature == "+neon") {
5388 HW_FP |= HW_FP_SP | HW_FP_DP;
5389 } else if (Feature == "+hwdiv") {
5390 HWDiv |= HWDivThumb;
5391 } else if (Feature == "+hwdiv-arm") {
5393 } else if (Feature == "+crc") {
5395 } else if (Feature == "+crypto") {
5397 } else if (Feature == "+dsp") {
5399 } else if (Feature == "+fp-only-sp") {
5400 HW_FP_remove |= HW_FP_DP;
5401 } else if (Feature == "+strict-align") {
5403 } else if (Feature == "+fp16") {
5407 HW_FP &= ~HW_FP_remove;
5409 switch (ArchVersion) {
5411 if (ArchProfile == llvm::ARM::PK_M)
5413 else if (ArchKind == llvm::ARM::AK_ARMV6K)
5414 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5419 if (ArchProfile == llvm::ARM::PK_M)
5420 LDREX = LDREX_W | LDREX_H | LDREX_B ;
5422 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5425 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5428 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
5429 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
5433 if (FPMath == FP_Neon)
5434 Features.push_back("+neonfp");
5435 else if (FPMath == FP_VFP)
5436 Features.push_back("-neonfp");
5438 // Remove front-end specific options which the backend handles differently.
5440 std::find(Features.begin(), Features.end(), "+soft-float-abi");
5441 if (Feature != Features.end())
5442 Features.erase(Feature);
5447 bool hasFeature(StringRef Feature) const override {
5448 return llvm::StringSwitch<bool>(Feature)
5450 .Case("aarch32", true)
5451 .Case("softfloat", SoftFloat)
5452 .Case("thumb", isThumb())
5453 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
5454 .Case("vfp", FPU && !SoftFloat)
5455 .Case("hwdiv", HWDiv & HWDivThumb)
5456 .Case("hwdiv-arm", HWDiv & HWDivARM)
5460 bool setCPU(const std::string &Name) override {
5461 if (Name != "generic")
5462 setArchInfo(llvm::ARM::parseCPUArch(Name));
5464 if (ArchKind == llvm::ARM::AK_INVALID)
5471 bool setFPMath(StringRef Name) override;
5473 void getTargetDefines(const LangOptions &Opts,
5474 MacroBuilder &Builder) const override {
5475 // Target identification.
5476 Builder.defineMacro("__arm");
5477 Builder.defineMacro("__arm__");
5478 // For bare-metal none-eabi.
5479 if (getTriple().getOS() == llvm::Triple::UnknownOS &&
5480 (getTriple().getEnvironment() == llvm::Triple::EABI ||
5481 getTriple().getEnvironment() == llvm::Triple::EABIHF))
5482 Builder.defineMacro("__ELF__");
5485 // Target properties.
5486 Builder.defineMacro("__REGISTER_PREFIX__", "");
5488 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
5489 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
5490 if (getTriple().isWatchABI())
5491 Builder.defineMacro("__ARM_ARCH_7K__", "2");
5493 if (!CPUAttr.empty())
5494 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
5496 // ACLE 6.4.1 ARM/Thumb instruction set architecture
5497 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
5498 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
5500 if (ArchVersion >= 8) {
5501 // ACLE 6.5.7 Crypto Extension
5503 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
5504 // ACLE 6.5.8 CRC32 Extension
5506 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
5507 // ACLE 6.5.10 Numeric Maximum and Minimum
5508 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
5509 // ACLE 6.5.9 Directed Rounding
5510 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
5513 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
5514 // is not defined for the M-profile.
5515 // NOTE that the default profile is assumed to be 'A'
5516 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M)
5517 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
5519 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original
5520 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the
5521 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all
5522 // v7 and v8 architectures excluding v8-M Baseline.
5523 if (supportsThumb2())
5524 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
5525 else if (supportsThumb())
5526 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
5528 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
5529 // instruction set such as ARM or Thumb.
5530 Builder.defineMacro("__ARM_32BIT_STATE", "1");
5532 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
5534 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
5535 if (!CPUProfile.empty())
5536 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
5538 // ACLE 6.4.3 Unaligned access supported in hardware
5540 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
5542 // ACLE 6.4.4 LDREX/STREX
5544 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX));
5547 if (ArchVersion == 5 ||
5548 (ArchVersion == 6 && CPUProfile != "M") ||
5550 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
5552 // ACLE 6.5.1 Hardware Floating Point
5554 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
5557 Builder.defineMacro("__ARM_ACLE", "200");
5559 // FP16 support (we currently only support IEEE format).
5560 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
5561 Builder.defineMacro("__ARM_FP16_ARGS", "1");
5563 // ACLE 6.5.3 Fused multiply-accumulate (FMA)
5564 if (ArchVersion >= 7 && (FPU & VFP4FPU))
5565 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
5567 // Subtarget options.
5569 // FIXME: It's more complicated than this and we don't really support
5571 // Windows on ARM does not "support" interworking
5572 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows())
5573 Builder.defineMacro("__THUMB_INTERWORK__");
5575 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
5576 // Embedded targets on Darwin follow AAPCS, but not EABI.
5577 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
5578 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows())
5579 Builder.defineMacro("__ARM_EABI__");
5580 Builder.defineMacro("__ARM_PCS", "1");
5583 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" ||
5585 Builder.defineMacro("__ARM_PCS_VFP", "1");
5588 Builder.defineMacro("__SOFTFP__");
5590 if (ArchKind == llvm::ARM::AK_XSCALE)
5591 Builder.defineMacro("__XSCALE__");
5594 Builder.defineMacro("__THUMBEL__");
5595 Builder.defineMacro("__thumb__");
5596 if (supportsThumb2())
5597 Builder.defineMacro("__thumb2__");
5600 // ACLE 6.4.9 32-bit SIMD instructions
5601 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
5602 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
5604 // ACLE 6.4.10 Hardware Integer Divide
5605 if (((HWDiv & HWDivThumb) && isThumb()) ||
5606 ((HWDiv & HWDivARM) && !isThumb())) {
5607 Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
5608 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
5611 // Note, this is always on in gcc, even though it doesn't make sense.
5612 Builder.defineMacro("__APCS_32__");
5614 if (FPUModeIsVFP((FPUMode) FPU)) {
5615 Builder.defineMacro("__VFP_FP__");
5617 Builder.defineMacro("__ARM_VFPV2__");
5619 Builder.defineMacro("__ARM_VFPV3__");
5621 Builder.defineMacro("__ARM_VFPV4__");
5623 Builder.defineMacro("__ARM_FPV5__");
5626 // This only gets set when Neon instructions are actually available, unlike
5627 // the VFP define, hence the soft float and arch check. This is subtly
5628 // different from gcc, we follow the intent which was that it should be set
5629 // when Neon instructions are actually available.
5630 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
5631 Builder.defineMacro("__ARM_NEON", "1");
5632 Builder.defineMacro("__ARM_NEON__");
5633 // current AArch32 NEON implementations do not support double-precision
5634 // floating-point even when it is present in VFP.
5635 Builder.defineMacro("__ARM_NEON_FP",
5636 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP));
5639 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
5640 Opts.ShortWChar ? "2" : "4");
5642 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5643 Opts.ShortEnums ? "1" : "4");
5645 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") {
5646 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
5647 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
5648 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
5649 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
5652 // ACLE 6.4.7 DSP instructions
5654 Builder.defineMacro("__ARM_FEATURE_DSP", "1");
5657 // ACLE 6.4.8 Saturation instructions
5659 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) {
5660 Builder.defineMacro("__ARM_FEATURE_SAT", "1");
5664 // ACLE 6.4.6 Q (saturation) flag
5666 Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
5668 if (Opts.UnsafeFPMath)
5669 Builder.defineMacro("__ARM_FP_FAST", "1");
5671 if (ArchKind == llvm::ARM::AK_ARMV8_1A)
5672 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
5675 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5676 return llvm::makeArrayRef(BuiltinInfo,
5677 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin);
5679 bool isCLZForZeroUndef() const override { return false; }
5680 BuiltinVaListKind getBuiltinVaListKind() const override {
5682 ? AAPCSABIBuiltinVaList
5683 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList
5684 : TargetInfo::VoidPtrBuiltinVaList);
5686 ArrayRef<const char *> getGCCRegNames() const override;
5687 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5688 bool validateAsmConstraint(const char *&Name,
5689 TargetInfo::ConstraintInfo &Info) const override {
5694 case 't': // VFP Floating point register single precision
5695 case 'w': // VFP Floating point register double precision
5696 Info.setAllowsRegister();
5705 case 'Q': // A memory address that is a single base register.
5706 Info.setAllowsMemory();
5708 case 'U': // a memory reference...
5710 case 'q': // ...ARMV4 ldrsb
5711 case 'v': // ...VFP load/store (reg+constant offset)
5712 case 'y': // ...iWMMXt load/store
5713 case 't': // address valid for load/store opaque types wider
5715 case 'n': // valid address for Neon doubleword vector load/store
5716 case 'm': // valid address for Neon element and structure load/store
5717 case 's': // valid address for non-offset loads/stores of quad-word
5718 // values in four ARM registers
5719 Info.setAllowsMemory();
5726 std::string convertConstraint(const char *&Constraint) const override {
5728 switch (*Constraint) {
5729 case 'U': // Two-character constraint; add "^" hint for later parsing.
5730 R = std::string("^") + std::string(Constraint, 2);
5733 case 'p': // 'p' should be translated to 'r' by default.
5734 R = std::string("r");
5737 return std::string(1, *Constraint);
5742 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5743 std::string &SuggestedModifier) const override {
5744 bool isOutput = (Constraint[0] == '=');
5745 bool isInOut = (Constraint[0] == '+');
5747 // Strip off constraint modifiers.
5748 while (Constraint[0] == '=' ||
5749 Constraint[0] == '+' ||
5750 Constraint[0] == '&')
5751 Constraint = Constraint.substr(1);
5753 switch (Constraint[0]) {
5758 return (isInOut || isOutput || Size <= 64);
5760 // A register of size 32 cannot fit a vector type.
5768 const char *getClobbers() const override {
5769 // FIXME: Is this really right?
5773 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5780 return CCCR_Warning;
5784 int getEHDataRegisterNumber(unsigned RegNo) const override {
5785 if (RegNo == 0) return 0;
5786 if (RegNo == 1) return 1;
5790 bool hasSjLjLowering() const override {
5795 bool ARMTargetInfo::setFPMath(StringRef Name) {
5796 if (Name == "neon") {
5799 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
5807 const char * const ARMTargetInfo::GCCRegNames[] = {
5808 // Integer registers
5809 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5810 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
5813 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
5814 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
5815 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
5816 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5819 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
5820 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
5821 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
5822 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5825 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
5826 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
5829 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
5830 return llvm::makeArrayRef(GCCRegNames);
5833 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
5843 { { "v6", "rfp" }, "r9" },
5844 { { "sl" }, "r10" },
5845 { { "fp" }, "r11" },
5846 { { "ip" }, "r12" },
5847 { { "r13" }, "sp" },
5848 { { "r14" }, "lr" },
5849 { { "r15" }, "pc" },
5850 // The S, D and Q registers overlap, but aren't really aliases; we
5851 // don't want to substitute one of these for a different-sized one.
5854 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
5855 return llvm::makeArrayRef(GCCRegAliases);
5858 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
5859 #define BUILTIN(ID, TYPE, ATTRS) \
5860 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5861 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5862 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5863 #include "clang/Basic/BuiltinsNEON.def"
5865 #define BUILTIN(ID, TYPE, ATTRS) \
5866 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5867 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \
5868 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr },
5869 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5870 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5871 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
5872 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
5873 #include "clang/Basic/BuiltinsARM.def"
5876 class ARMleTargetInfo : public ARMTargetInfo {
5878 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5879 : ARMTargetInfo(Triple, Opts) {}
5880 void getTargetDefines(const LangOptions &Opts,
5881 MacroBuilder &Builder) const override {
5882 Builder.defineMacro("__ARMEL__");
5883 ARMTargetInfo::getTargetDefines(Opts, Builder);
5887 class ARMbeTargetInfo : public ARMTargetInfo {
5889 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5890 : ARMTargetInfo(Triple, Opts) {}
5891 void getTargetDefines(const LangOptions &Opts,
5892 MacroBuilder &Builder) const override {
5893 Builder.defineMacro("__ARMEB__");
5894 Builder.defineMacro("__ARM_BIG_ENDIAN");
5895 ARMTargetInfo::getTargetDefines(Opts, Builder);
5899 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
5900 const llvm::Triple Triple;
5902 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5903 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
5904 WCharType = UnsignedShort;
5905 SizeType = UnsignedInt;
5907 void getVisualStudioDefines(const LangOptions &Opts,
5908 MacroBuilder &Builder) const {
5909 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
5911 // FIXME: this is invalid for WindowsCE
5912 Builder.defineMacro("_M_ARM_NT", "1");
5913 Builder.defineMacro("_M_ARMT", "_M_ARM");
5914 Builder.defineMacro("_M_THUMB", "_M_ARM");
5916 assert((Triple.getArch() == llvm::Triple::arm ||
5917 Triple.getArch() == llvm::Triple::thumb) &&
5918 "invalid architecture for Windows ARM target info");
5919 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
5920 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
5922 // TODO map the complete set of values
5923 // 31: VFPv3 40: VFPv4
5924 Builder.defineMacro("_M_ARM_FP", "31");
5926 BuiltinVaListKind getBuiltinVaListKind() const override {
5927 return TargetInfo::CharPtrBuiltinVaList;
5929 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5932 case CC_X86ThisCall:
5933 case CC_X86FastCall:
5934 case CC_X86VectorCall:
5939 return CCCR_Warning;
5944 // Windows ARM + Itanium C++ ABI Target
5945 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
5947 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple,
5948 const TargetOptions &Opts)
5949 : WindowsARMTargetInfo(Triple, Opts) {
5950 TheCXXABI.set(TargetCXXABI::GenericARM);
5953 void getTargetDefines(const LangOptions &Opts,
5954 MacroBuilder &Builder) const override {
5955 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5957 if (Opts.MSVCCompat)
5958 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5962 // Windows ARM, MS (C++) ABI
5963 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
5965 MicrosoftARMleTargetInfo(const llvm::Triple &Triple,
5966 const TargetOptions &Opts)
5967 : WindowsARMTargetInfo(Triple, Opts) {
5968 TheCXXABI.set(TargetCXXABI::Microsoft);
5971 void getTargetDefines(const LangOptions &Opts,
5972 MacroBuilder &Builder) const override {
5973 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5974 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5979 class MinGWARMTargetInfo : public WindowsARMTargetInfo {
5981 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5982 : WindowsARMTargetInfo(Triple, Opts) {
5983 TheCXXABI.set(TargetCXXABI::GenericARM);
5986 void getTargetDefines(const LangOptions &Opts,
5987 MacroBuilder &Builder) const override {
5988 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5989 DefineStd(Builder, "WIN32", Opts);
5990 DefineStd(Builder, "WINNT", Opts);
5991 Builder.defineMacro("_ARM_");
5992 addMinGWDefines(Opts, Builder);
5996 // ARM Cygwin target
5997 class CygwinARMTargetInfo : public ARMleTargetInfo {
5999 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6000 : ARMleTargetInfo(Triple, Opts) {
6001 TLSSupported = false;
6002 WCharType = UnsignedShort;
6003 DoubleAlign = LongLongAlign = 64;
6004 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
6006 void getTargetDefines(const LangOptions &Opts,
6007 MacroBuilder &Builder) const override {
6008 ARMleTargetInfo::getTargetDefines(Opts, Builder);
6009 Builder.defineMacro("_ARM_");
6010 Builder.defineMacro("__CYGWIN__");
6011 Builder.defineMacro("__CYGWIN32__");
6012 DefineStd(Builder, "unix", Opts);
6014 Builder.defineMacro("_GNU_SOURCE");
6018 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> {
6020 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
6021 MacroBuilder &Builder) const override {
6022 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
6026 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6027 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
6028 HasAlignMac68kSupport = true;
6029 // iOS always has 64-bit atomic instructions.
6030 // FIXME: This should be based off of the target features in
6032 MaxAtomicInlineWidth = 64;
6034 if (Triple.isWatchABI()) {
6035 // Darwin on iOS uses a variant of the ARM C++ ABI.
6036 TheCXXABI.set(TargetCXXABI::WatchOS);
6038 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that
6039 // size_t is long, it's a bit weird for it to be int.
6040 PtrDiffType = SignedLong;
6042 // BOOL should be a real boolean on the new ABI
6043 UseSignedCharForObjCBool = false;
6045 TheCXXABI.set(TargetCXXABI::iOS);
6049 class AArch64TargetInfo : public TargetInfo {
6050 virtual void setDataLayout() = 0;
6051 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6052 static const char *const GCCRegNames[];
6065 static const Builtin::Info BuiltinInfo[];
6070 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6071 : TargetInfo(Triple), ABI("aapcs") {
6072 if (getTriple().getOS() == llvm::Triple::NetBSD ||
6073 getTriple().getOS() == llvm::Triple::OpenBSD) {
6074 WCharType = SignedInt;
6076 // NetBSD apparently prefers consistency across ARM targets to consistency
6077 // across 64-bit targets.
6078 Int64Type = SignedLongLong;
6079 IntMaxType = SignedLongLong;
6081 WCharType = UnsignedInt;
6082 Int64Type = SignedLong;
6083 IntMaxType = SignedLong;
6086 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6087 MaxVectorAlign = 128;
6088 MaxAtomicInlineWidth = 128;
6089 MaxAtomicPromoteWidth = 128;
6091 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
6092 LongDoubleFormat = &llvm::APFloat::IEEEquad();
6094 // {} in inline assembly are neon specifiers, not assembly variant
6096 NoAsmVariants = true;
6098 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
6099 // contributes to the alignment of the containing aggregate in the same way
6100 // a plain (non bit-field) member of that type would, without exception for
6101 // zero-sized or anonymous bit-fields."
6102 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
6103 UseZeroLengthBitfieldAlignment = true;
6105 // AArch64 targets default to using the ARM C++ ABI.
6106 TheCXXABI.set(TargetCXXABI::GenericAArch64);
6108 if (Triple.getOS() == llvm::Triple::Linux)
6109 this->MCountName = "\01_mcount";
6110 else if (Triple.getOS() == llvm::Triple::UnknownOS)
6111 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount";
6114 StringRef getABI() const override { return ABI; }
6115 bool setABI(const std::string &Name) override {
6116 if (Name != "aapcs" && Name != "darwinpcs")
6123 bool setCPU(const std::string &Name) override {
6124 return Name == "generic" ||
6125 llvm::AArch64::parseCPUArch(Name) !=
6126 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID);
6129 void getTargetDefines(const LangOptions &Opts,
6130 MacroBuilder &Builder) const override {
6131 // Target identification.
6132 Builder.defineMacro("__aarch64__");
6133 // For bare-metal none-eabi.
6134 if (getTriple().getOS() == llvm::Triple::UnknownOS &&
6135 (getTriple().getEnvironment() == llvm::Triple::EABI ||
6136 getTriple().getEnvironment() == llvm::Triple::EABIHF))
6137 Builder.defineMacro("__ELF__");
6139 // Target properties.
6140 Builder.defineMacro("_LP64");
6141 Builder.defineMacro("__LP64__");
6143 // ACLE predefines. Many can only have one possible value on v8 AArch64.
6144 Builder.defineMacro("__ARM_ACLE", "200");
6145 Builder.defineMacro("__ARM_ARCH", "8");
6146 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
6148 Builder.defineMacro("__ARM_64BIT_STATE", "1");
6149 Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
6150 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
6152 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
6153 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
6154 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
6155 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
6156 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
6157 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
6158 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
6160 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
6162 // 0xe implies support for half, single and double precision operations.
6163 Builder.defineMacro("__ARM_FP", "0xE");
6165 // PCS specifies this for SysV variants, which is all we support. Other ABIs
6166 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
6167 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
6168 Builder.defineMacro("__ARM_FP16_ARGS", "1");
6170 if (Opts.UnsafeFPMath)
6171 Builder.defineMacro("__ARM_FP_FAST", "1");
6173 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
6175 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
6176 Opts.ShortEnums ? "1" : "4");
6178 if (FPU == NeonMode) {
6179 Builder.defineMacro("__ARM_NEON", "1");
6180 // 64-bit NEON supports half, single and double precision operations.
6181 Builder.defineMacro("__ARM_NEON_FP", "0xE");
6185 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
6188 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
6191 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
6194 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
6196 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
6197 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
6198 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
6199 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
6200 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
6203 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6204 return llvm::makeArrayRef(BuiltinInfo,
6205 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin);
6208 bool hasFeature(StringRef Feature) const override {
6209 return Feature == "aarch64" ||
6210 Feature == "arm64" ||
6212 (Feature == "neon" && FPU == NeonMode);
6215 bool handleTargetFeatures(std::vector<std::string> &Features,
6216 DiagnosticsEngine &Diags) override {
6223 for (const auto &Feature : Features) {
6224 if (Feature == "+neon")
6226 if (Feature == "+crc")
6228 if (Feature == "+crypto")
6230 if (Feature == "+strict-align")
6232 if (Feature == "+v8.1a")
6241 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6245 case CC_PreserveMost:
6246 case CC_PreserveAll:
6249 return CCCR_Warning;
6253 bool isCLZForZeroUndef() const override { return false; }
6255 BuiltinVaListKind getBuiltinVaListKind() const override {
6256 return TargetInfo::AArch64ABIBuiltinVaList;
6259 ArrayRef<const char *> getGCCRegNames() const override;
6260 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6262 bool validateAsmConstraint(const char *&Name,
6263 TargetInfo::ConstraintInfo &Info) const override {
6267 case 'w': // Floating point and SIMD registers (V0-V31)
6268 Info.setAllowsRegister();
6270 case 'I': // Constant that can be used with an ADD instruction
6271 case 'J': // Constant that can be used with a SUB instruction
6272 case 'K': // Constant that can be used with a 32-bit logical instruction
6273 case 'L': // Constant that can be used with a 64-bit logical instruction
6274 case 'M': // Constant that can be used as a 32-bit MOV immediate
6275 case 'N': // Constant that can be used as a 64-bit MOV immediate
6276 case 'Y': // Floating point constant zero
6277 case 'Z': // Integer constant zero
6279 case 'Q': // A memory reference with base register and no offset
6280 Info.setAllowsMemory();
6282 case 'S': // A symbolic address
6283 Info.setAllowsRegister();
6286 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
6287 // Utf: A memory address suitable for ldp/stp in TF mode.
6288 // Usa: An absolute symbolic address.
6289 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
6290 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
6291 case 'z': // Zero register, wzr or xzr
6292 Info.setAllowsRegister();
6294 case 'x': // Floating point and SIMD registers (V0-V15)
6295 Info.setAllowsRegister();
6302 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
6303 std::string &SuggestedModifier) const override {
6304 // Strip off constraint modifiers.
6305 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
6306 Constraint = Constraint.substr(1);
6308 switch (Constraint[0]) {
6316 // For now assume that the person knows what they're
6317 // doing with the modifier.
6320 // By default an 'r' constraint will be in the 'x'
6325 SuggestedModifier = "w";
6332 const char *getClobbers() const override { return ""; }
6334 int getEHDataRegisterNumber(unsigned RegNo) const override {
6343 const char *const AArch64TargetInfo::GCCRegNames[] = {
6344 // 32-bit Integer registers
6345 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
6346 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
6347 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
6349 // 64-bit Integer registers
6350 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
6351 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
6352 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
6354 // 32-bit floating point regsisters
6355 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
6356 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
6357 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
6359 // 64-bit floating point regsisters
6360 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
6361 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
6362 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
6365 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
6366 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
6367 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
6370 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
6371 return llvm::makeArrayRef(GCCRegNames);
6374 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
6375 { { "w31" }, "wsp" },
6376 { { "x29" }, "fp" },
6377 { { "x30" }, "lr" },
6378 { { "x31" }, "sp" },
6379 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
6380 // don't want to substitute one of these for a different-sized one.
6383 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
6384 return llvm::makeArrayRef(GCCRegAliases);
6387 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
6388 #define BUILTIN(ID, TYPE, ATTRS) \
6389 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6390 #include "clang/Basic/BuiltinsNEON.def"
6392 #define BUILTIN(ID, TYPE, ATTRS) \
6393 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6394 #include "clang/Basic/BuiltinsAArch64.def"
6397 class AArch64leTargetInfo : public AArch64TargetInfo {
6398 void setDataLayout() override {
6399 if (getTriple().isOSBinFormatMachO())
6400 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128");
6402 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6406 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6407 : AArch64TargetInfo(Triple, Opts) {
6409 void getTargetDefines(const LangOptions &Opts,
6410 MacroBuilder &Builder) const override {
6411 Builder.defineMacro("__AARCH64EL__");
6412 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6416 class AArch64beTargetInfo : public AArch64TargetInfo {
6417 void setDataLayout() override {
6418 assert(!getTriple().isOSBinFormatMachO());
6419 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6423 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6424 : AArch64TargetInfo(Triple, Opts) {}
6425 void getTargetDefines(const LangOptions &Opts,
6426 MacroBuilder &Builder) const override {
6427 Builder.defineMacro("__AARCH64EB__");
6428 Builder.defineMacro("__AARCH_BIG_ENDIAN");
6429 Builder.defineMacro("__ARM_BIG_ENDIAN");
6430 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6434 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
6436 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
6437 MacroBuilder &Builder) const override {
6438 Builder.defineMacro("__AARCH64_SIMD__");
6439 Builder.defineMacro("__ARM64_ARCH_8__");
6440 Builder.defineMacro("__ARM_NEON__");
6441 Builder.defineMacro("__LITTLE_ENDIAN__");
6442 Builder.defineMacro("__REGISTER_PREFIX__", "");
6443 Builder.defineMacro("__arm64", "1");
6444 Builder.defineMacro("__arm64__", "1");
6446 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
6450 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6451 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
6452 Int64Type = SignedLongLong;
6453 WCharType = SignedInt;
6454 UseSignedCharForObjCBool = false;
6456 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
6457 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
6459 TheCXXABI.set(TargetCXXABI::iOS64);
6462 BuiltinVaListKind getBuiltinVaListKind() const override {
6463 return TargetInfo::CharPtrBuiltinVaList;
6467 // Hexagon abstract base class
6468 class HexagonTargetInfo : public TargetInfo {
6469 static const Builtin::Info BuiltinInfo[];
6470 static const char * const GCCRegNames[];
6471 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6473 bool HasHVX, HasHVXDouble;
6477 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6478 : TargetInfo(Triple) {
6479 // Specify the vector alignment explicitly. For v512x1, the calculated
6480 // alignment would be 512*alignment(i1), which is 512 bytes, instead of
6481 // the required minimum of 64 bytes.
6482 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-"
6483 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
6484 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048");
6485 SizeType = UnsignedInt;
6486 PtrDiffType = SignedInt;
6487 IntPtrType = SignedInt;
6489 // {} in inline assembly are packet specifiers, not assembly variant
6491 NoAsmVariants = true;
6493 LargeArrayMinWidth = 64;
6494 LargeArrayAlign = 64;
6495 UseBitFieldTypeAlignment = true;
6496 ZeroLengthBitfieldBoundary = 32;
6497 HasHVX = HasHVXDouble = false;
6498 UseLongCalls = false;
6501 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6502 return llvm::makeArrayRef(BuiltinInfo,
6503 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin);
6506 bool validateAsmConstraint(const char *&Name,
6507 TargetInfo::ConstraintInfo &Info) const override {
6512 Info.setAllowsRegister();
6517 // Relocatable constant.
6523 void getTargetDefines(const LangOptions &Opts,
6524 MacroBuilder &Builder) const override;
6526 bool isCLZForZeroUndef() const override { return false; }
6528 bool hasFeature(StringRef Feature) const override {
6529 return llvm::StringSwitch<bool>(Feature)
6530 .Case("hexagon", true)
6531 .Case("hvx", HasHVX)
6532 .Case("hvx-double", HasHVXDouble)
6533 .Case("long-calls", UseLongCalls)
6537 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6538 StringRef CPU, const std::vector<std::string> &FeaturesVec)
6541 bool handleTargetFeatures(std::vector<std::string> &Features,
6542 DiagnosticsEngine &Diags) override;
6544 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
6545 bool Enabled) const override;
6547 BuiltinVaListKind getBuiltinVaListKind() const override {
6548 return TargetInfo::CharPtrBuiltinVaList;
6550 ArrayRef<const char *> getGCCRegNames() const override;
6551 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6552 const char *getClobbers() const override {
6556 static const char *getHexagonCPUSuffix(StringRef Name) {
6557 return llvm::StringSwitch<const char*>(Name)
6558 .Case("hexagonv4", "4")
6559 .Case("hexagonv5", "5")
6560 .Case("hexagonv55", "55")
6561 .Case("hexagonv60", "60")
6562 .Case("hexagonv62", "62")
6566 bool setCPU(const std::string &Name) override {
6567 if (!getHexagonCPUSuffix(Name))
6573 int getEHDataRegisterNumber(unsigned RegNo) const override {
6574 return RegNo < 2 ? RegNo : -1;
6578 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
6579 MacroBuilder &Builder) const {
6580 Builder.defineMacro("__qdsp6__", "1");
6581 Builder.defineMacro("__hexagon__", "1");
6583 if (CPU == "hexagonv4") {
6584 Builder.defineMacro("__HEXAGON_V4__");
6585 Builder.defineMacro("__HEXAGON_ARCH__", "4");
6586 if (Opts.HexagonQdsp6Compat) {
6587 Builder.defineMacro("__QDSP6_V4__");
6588 Builder.defineMacro("__QDSP6_ARCH__", "4");
6590 } else if (CPU == "hexagonv5") {
6591 Builder.defineMacro("__HEXAGON_V5__");
6592 Builder.defineMacro("__HEXAGON_ARCH__", "5");
6593 if(Opts.HexagonQdsp6Compat) {
6594 Builder.defineMacro("__QDSP6_V5__");
6595 Builder.defineMacro("__QDSP6_ARCH__", "5");
6597 } else if (CPU == "hexagonv55") {
6598 Builder.defineMacro("__HEXAGON_V55__");
6599 Builder.defineMacro("__HEXAGON_ARCH__", "55");
6600 Builder.defineMacro("__QDSP6_V55__");
6601 Builder.defineMacro("__QDSP6_ARCH__", "55");
6602 } else if (CPU == "hexagonv60") {
6603 Builder.defineMacro("__HEXAGON_V60__");
6604 Builder.defineMacro("__HEXAGON_ARCH__", "60");
6605 Builder.defineMacro("__QDSP6_V60__");
6606 Builder.defineMacro("__QDSP6_ARCH__", "60");
6607 } else if (CPU == "hexagonv62") {
6608 Builder.defineMacro("__HEXAGON_V62__");
6609 Builder.defineMacro("__HEXAGON_ARCH__", "62");
6612 if (hasFeature("hvx")) {
6613 Builder.defineMacro("__HVX__");
6614 if (hasFeature("hvx-double"))
6615 Builder.defineMacro("__HVXDBL__");
6619 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features,
6620 DiagnosticsEngine &Diags, StringRef CPU,
6621 const std::vector<std::string> &FeaturesVec) const {
6622 // Default for v60: -hvx, -hvx-double.
6623 Features["hvx"] = false;
6624 Features["hvx-double"] = false;
6625 Features["long-calls"] = false;
6627 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6630 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
6631 DiagnosticsEngine &Diags) {
6632 for (auto &F : Features) {
6635 else if (F == "-hvx")
6636 HasHVX = HasHVXDouble = false;
6637 else if (F == "+hvx-double")
6638 HasHVX = HasHVXDouble = true;
6639 else if (F == "-hvx-double")
6640 HasHVXDouble = false;
6642 if (F == "+long-calls")
6643 UseLongCalls = true;
6644 else if (F == "-long-calls")
6645 UseLongCalls = false;
6650 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
6651 StringRef Name, bool Enabled) const {
6653 if (Name == "hvx-double")
6654 Features["hvx"] = true;
6657 Features["hvx-double"] = false;
6659 Features[Name] = Enabled;
6662 const char *const HexagonTargetInfo::GCCRegNames[] = {
6663 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6664 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6665 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6666 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
6667 "p0", "p1", "p2", "p3",
6668 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
6671 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const {
6672 return llvm::makeArrayRef(GCCRegNames);
6675 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
6676 { { "sp" }, "r29" },
6677 { { "fp" }, "r30" },
6678 { { "lr" }, "r31" },
6681 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const {
6682 return llvm::makeArrayRef(GCCRegAliases);
6686 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
6687 #define BUILTIN(ID, TYPE, ATTRS) \
6688 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6689 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6690 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6691 #include "clang/Basic/BuiltinsHexagon.def"
6694 class LanaiTargetInfo : public TargetInfo {
6695 // Class for Lanai (32-bit).
6696 // The CPU profiles supported by the Lanai backend
6702 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6703 static const char *const GCCRegNames[];
6706 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6707 : TargetInfo(Triple) {
6708 // Description string has to be kept in sync with backend.
6709 resetDataLayout("E" // Big endian
6710 "-m:e" // ELF name manging
6711 "-p:32:32" // 32 bit pointers, 32 bit aligned
6712 "-i64:64" // 64 bit integers, 64 bit aligned
6713 "-a:0:32" // 32 bit alignment of objects of aggregate type
6714 "-n32" // 32 bit native integer width
6715 "-S64" // 64 bit natural stack alignment
6718 // Setting RegParmMax equal to what mregparm was set to in the old
6722 // Set the default CPU to V11
6725 // Temporary approach to make everything at least word-aligned and allow for
6726 // safely casting between pointers with different alignment requirements.
6727 // TODO: Remove this when there are no more cast align warnings on the
6729 MinGlobalAlign = 32;
6732 void getTargetDefines(const LangOptions &Opts,
6733 MacroBuilder &Builder) const override {
6734 // Define __lanai__ when building for target lanai.
6735 Builder.defineMacro("__lanai__");
6737 // Set define for the CPU specified.
6740 Builder.defineMacro("__LANAI_V11__");
6743 llvm_unreachable("Unhandled target CPU");
6747 bool setCPU(const std::string &Name) override {
6748 CPU = llvm::StringSwitch<CPUKind>(Name)
6749 .Case("v11", CK_V11)
6752 return CPU != CK_NONE;
6755 bool hasFeature(StringRef Feature) const override {
6756 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false);
6759 ArrayRef<const char *> getGCCRegNames() const override;
6761 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6763 BuiltinVaListKind getBuiltinVaListKind() const override {
6764 return TargetInfo::VoidPtrBuiltinVaList;
6767 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
6769 bool validateAsmConstraint(const char *&Name,
6770 TargetInfo::ConstraintInfo &info) const override {
6774 const char *getClobbers() const override { return ""; }
6777 const char *const LanaiTargetInfo::GCCRegNames[] = {
6778 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
6779 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
6780 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
6782 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const {
6783 return llvm::makeArrayRef(GCCRegNames);
6786 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = {
6796 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const {
6797 return llvm::makeArrayRef(GCCRegAliases);
6800 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
6801 class SparcTargetInfo : public TargetInfo {
6802 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6803 static const char * const GCCRegNames[];
6806 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6807 : TargetInfo(Triple), SoftFloat(false) {}
6809 int getEHDataRegisterNumber(unsigned RegNo) const override {
6810 if (RegNo == 0) return 24;
6811 if (RegNo == 1) return 25;
6815 bool handleTargetFeatures(std::vector<std::string> &Features,
6816 DiagnosticsEngine &Diags) override {
6817 // Check if software floating point is enabled
6818 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
6819 if (Feature != Features.end()) {
6824 void getTargetDefines(const LangOptions &Opts,
6825 MacroBuilder &Builder) const override {
6826 DefineStd(Builder, "sparc", Opts);
6827 Builder.defineMacro("__REGISTER_PREFIX__", "");
6830 Builder.defineMacro("SOFT_FLOAT", "1");
6833 bool hasFeature(StringRef Feature) const override {
6834 return llvm::StringSwitch<bool>(Feature)
6835 .Case("softfloat", SoftFloat)
6836 .Case("sparc", true)
6840 bool hasSjLjLowering() const override {
6844 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6845 // FIXME: Implement!
6848 BuiltinVaListKind getBuiltinVaListKind() const override {
6849 return TargetInfo::VoidPtrBuiltinVaList;
6851 ArrayRef<const char *> getGCCRegNames() const override;
6852 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6853 bool validateAsmConstraint(const char *&Name,
6854 TargetInfo::ConstraintInfo &info) const override {
6855 // FIXME: Implement!
6857 case 'I': // Signed 13-bit constant
6859 case 'K': // 32-bit constant with the low 12 bits clear
6860 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
6861 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
6862 case 'N': // Same as 'K' but zext (required for SIMode)
6863 case 'O': // The constant 4096
6868 const char *getClobbers() const override {
6869 // FIXME: Implement!
6873 // No Sparc V7 for now, the backend doesn't support it anyway.
6904 enum CPUGeneration {
6909 CPUGeneration getCPUGeneration(CPUKind Kind) const {
6917 case CK_SPARCLITE86X:
6924 case CK_LEON2_AT697E:
6925 case CK_LEON2_AT697F:
6927 case CK_LEON3_UT699:
6928 case CK_LEON3_GR712RC:
6930 case CK_LEON4_GR740:
6934 case CK_ULTRASPARC3:
6941 llvm_unreachable("Unexpected CPU kind");
6944 CPUKind getCPUKind(StringRef Name) const {
6945 return llvm::StringSwitch<CPUKind>(Name)
6947 .Case("supersparc", CK_SUPERSPARC)
6948 .Case("sparclite", CK_SPARCLITE)
6949 .Case("f934", CK_F934)
6950 .Case("hypersparc", CK_HYPERSPARC)
6951 .Case("sparclite86x", CK_SPARCLITE86X)
6952 .Case("sparclet", CK_SPARCLET)
6953 .Case("tsc701", CK_TSC701)
6955 .Case("ultrasparc", CK_ULTRASPARC)
6956 .Case("ultrasparc3", CK_ULTRASPARC3)
6957 .Case("niagara", CK_NIAGARA)
6958 .Case("niagara2", CK_NIAGARA2)
6959 .Case("niagara3", CK_NIAGARA3)
6960 .Case("niagara4", CK_NIAGARA4)
6961 .Case("ma2100", CK_MYRIAD2100)
6962 .Case("ma2150", CK_MYRIAD2150)
6963 .Case("ma2450", CK_MYRIAD2450)
6964 // FIXME: the myriad2[.n] spellings are obsolete,
6965 // but a grace period is needed to allow updating dependent builds.
6966 .Case("myriad2", CK_MYRIAD2100)
6967 .Case("myriad2.1", CK_MYRIAD2100)
6968 .Case("myriad2.2", CK_MYRIAD2150)
6969 .Case("leon2", CK_LEON2)
6970 .Case("at697e", CK_LEON2_AT697E)
6971 .Case("at697f", CK_LEON2_AT697F)
6972 .Case("leon3", CK_LEON3)
6973 .Case("ut699", CK_LEON3_UT699)
6974 .Case("gr712rc", CK_LEON3_GR712RC)
6975 .Case("leon4", CK_LEON4)
6976 .Case("gr740", CK_LEON4_GR740)
6977 .Default(CK_GENERIC);
6980 bool setCPU(const std::string &Name) override {
6981 CPU = getCPUKind(Name);
6982 return CPU != CK_GENERIC;
6986 const char * const SparcTargetInfo::GCCRegNames[] = {
6987 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6988 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6989 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6990 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6993 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
6994 return llvm::makeArrayRef(GCCRegNames);
6997 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
7008 { { "o2" }, "r10" },
7009 { { "o3" }, "r11" },
7010 { { "o4" }, "r12" },
7011 { { "o5" }, "r13" },
7012 { { "o6", "sp" }, "r14" },
7013 { { "o7" }, "r15" },
7014 { { "l0" }, "r16" },
7015 { { "l1" }, "r17" },
7016 { { "l2" }, "r18" },
7017 { { "l3" }, "r19" },
7018 { { "l4" }, "r20" },
7019 { { "l5" }, "r21" },
7020 { { "l6" }, "r22" },
7021 { { "l7" }, "r23" },
7022 { { "i0" }, "r24" },
7023 { { "i1" }, "r25" },
7024 { { "i2" }, "r26" },
7025 { { "i3" }, "r27" },
7026 { { "i4" }, "r28" },
7027 { { "i5" }, "r29" },
7028 { { "i6", "fp" }, "r30" },
7029 { { "i7" }, "r31" },
7032 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
7033 return llvm::makeArrayRef(GCCRegAliases);
7036 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
7037 class SparcV8TargetInfo : public SparcTargetInfo {
7039 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7040 : SparcTargetInfo(Triple, Opts) {
7041 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64");
7042 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
7043 switch (getTriple().getOS()) {
7045 SizeType = UnsignedInt;
7046 IntPtrType = SignedInt;
7047 PtrDiffType = SignedInt;
7049 case llvm::Triple::NetBSD:
7050 case llvm::Triple::OpenBSD:
7051 SizeType = UnsignedLong;
7052 IntPtrType = SignedLong;
7053 PtrDiffType = SignedLong;
7056 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops
7057 // on up to 64 bits.
7058 MaxAtomicPromoteWidth = 64;
7059 MaxAtomicInlineWidth = 32;
7062 void getTargetDefines(const LangOptions &Opts,
7063 MacroBuilder &Builder) const override {
7064 SparcTargetInfo::getTargetDefines(Opts, Builder);
7065 switch (getCPUGeneration(CPU)) {
7067 Builder.defineMacro("__sparcv8");
7068 if (getTriple().getOS() != llvm::Triple::Solaris)
7069 Builder.defineMacro("__sparcv8__");
7072 Builder.defineMacro("__sparcv9");
7073 if (getTriple().getOS() != llvm::Triple::Solaris) {
7074 Builder.defineMacro("__sparcv9__");
7075 Builder.defineMacro("__sparc_v9__");
7079 if (getTriple().getVendor() == llvm::Triple::Myriad) {
7080 std::string MyriadArchValue, Myriad2Value;
7081 Builder.defineMacro("__sparc_v8__");
7082 Builder.defineMacro("__leon__");
7085 MyriadArchValue = "__ma2150";
7089 MyriadArchValue = "__ma2450";
7093 MyriadArchValue = "__ma2100";
7097 Builder.defineMacro(MyriadArchValue, "1");
7098 Builder.defineMacro(MyriadArchValue+"__", "1");
7099 Builder.defineMacro("__myriad2__", Myriad2Value);
7100 Builder.defineMacro("__myriad2", Myriad2Value);
7104 bool hasSjLjLowering() const override {
7109 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
7110 class SparcV8elTargetInfo : public SparcV8TargetInfo {
7112 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7113 : SparcV8TargetInfo(Triple, Opts) {
7114 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64");
7118 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
7119 class SparcV9TargetInfo : public SparcTargetInfo {
7121 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7122 : SparcTargetInfo(Triple, Opts) {
7123 // FIXME: Support Sparc quad-precision long double?
7124 resetDataLayout("E-m:e-i64:64-n32:64-S128");
7125 // This is an LP64 platform.
7126 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7128 // OpenBSD uses long long for int64_t and intmax_t.
7129 if (getTriple().getOS() == llvm::Triple::OpenBSD)
7130 IntMaxType = SignedLongLong;
7132 IntMaxType = SignedLong;
7133 Int64Type = IntMaxType;
7135 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
7136 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
7137 LongDoubleWidth = 128;
7138 LongDoubleAlign = 128;
7139 LongDoubleFormat = &llvm::APFloat::IEEEquad();
7140 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7143 void getTargetDefines(const LangOptions &Opts,
7144 MacroBuilder &Builder) const override {
7145 SparcTargetInfo::getTargetDefines(Opts, Builder);
7146 Builder.defineMacro("__sparcv9");
7147 Builder.defineMacro("__arch64__");
7148 // Solaris doesn't need these variants, but the BSDs do.
7149 if (getTriple().getOS() != llvm::Triple::Solaris) {
7150 Builder.defineMacro("__sparc64__");
7151 Builder.defineMacro("__sparc_v9__");
7152 Builder.defineMacro("__sparcv9__");
7156 bool setCPU(const std::string &Name) override {
7157 if (!SparcTargetInfo::setCPU(Name))
7159 return getCPUGeneration(CPU) == CG_V9;
7163 class SystemZTargetInfo : public TargetInfo {
7164 static const Builtin::Info BuiltinInfo[];
7165 static const char *const GCCRegNames[];
7167 bool HasTransactionalExecution;
7171 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7172 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false),
7174 IntMaxType = SignedLong;
7175 Int64Type = SignedLong;
7176 TLSSupported = true;
7177 IntWidth = IntAlign = 32;
7178 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
7179 PointerWidth = PointerAlign = 64;
7180 LongDoubleWidth = 128;
7181 LongDoubleAlign = 64;
7182 LongDoubleFormat = &llvm::APFloat::IEEEquad();
7183 DefaultAlignForAttributeAligned = 64;
7184 MinGlobalAlign = 16;
7185 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64");
7186 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7188 void getTargetDefines(const LangOptions &Opts,
7189 MacroBuilder &Builder) const override {
7190 Builder.defineMacro("__s390__");
7191 Builder.defineMacro("__s390x__");
7192 Builder.defineMacro("__zarch__");
7193 Builder.defineMacro("__LONG_DOUBLE_128__");
7195 const std::string ISARev = llvm::StringSwitch<std::string>(CPU)
7196 .Cases("arch8", "z10", "8")
7197 .Cases("arch9", "z196", "9")
7198 .Cases("arch10", "zEC12", "10")
7199 .Cases("arch11", "z13", "11")
7201 if (!ISARev.empty())
7202 Builder.defineMacro("__ARCH__", ISARev);
7204 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
7205 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
7206 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
7207 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
7209 if (HasTransactionalExecution)
7210 Builder.defineMacro("__HTM__");
7212 Builder.defineMacro("__VX__");
7214 Builder.defineMacro("__VEC__", "10301");
7216 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7217 return llvm::makeArrayRef(BuiltinInfo,
7218 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin);
7221 ArrayRef<const char *> getGCCRegNames() const override;
7222 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7226 bool validateAsmConstraint(const char *&Name,
7227 TargetInfo::ConstraintInfo &info) const override;
7228 const char *getClobbers() const override {
7229 // FIXME: Is this really right?
7232 BuiltinVaListKind getBuiltinVaListKind() const override {
7233 return TargetInfo::SystemZBuiltinVaList;
7235 bool setCPU(const std::string &Name) override {
7237 bool CPUKnown = llvm::StringSwitch<bool>(Name)
7239 .Case("arch8", true)
7241 .Case("arch9", true)
7242 .Case("zEC12", true)
7243 .Case("arch10", true)
7245 .Case("arch11", true)
7251 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7253 const std::vector<std::string> &FeaturesVec) const override {
7254 if (CPU == "zEC12" || CPU == "arch10")
7255 Features["transactional-execution"] = true;
7256 if (CPU == "z13" || CPU == "arch11") {
7257 Features["transactional-execution"] = true;
7258 Features["vector"] = true;
7260 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7263 bool handleTargetFeatures(std::vector<std::string> &Features,
7264 DiagnosticsEngine &Diags) override {
7265 HasTransactionalExecution = false;
7266 for (const auto &Feature : Features) {
7267 if (Feature == "+transactional-execution")
7268 HasTransactionalExecution = true;
7269 else if (Feature == "+vector")
7272 // If we use the vector ABI, vector types are 64-bit aligned.
7274 MaxVectorAlign = 64;
7275 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
7276 "-v128:64-a:8:16-n32:64");
7281 bool hasFeature(StringRef Feature) const override {
7282 return llvm::StringSwitch<bool>(Feature)
7283 .Case("systemz", true)
7284 .Case("htm", HasTransactionalExecution)
7285 .Case("vx", HasVector)
7289 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
7295 return CCCR_Warning;
7299 StringRef getABI() const override {
7305 bool useFloat128ManglingForLongDouble() const override {
7310 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
7311 #define BUILTIN(ID, TYPE, ATTRS) \
7312 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7313 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
7314 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
7315 #include "clang/Basic/BuiltinsSystemZ.def"
7318 const char *const SystemZTargetInfo::GCCRegNames[] = {
7319 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7320 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7321 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
7322 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
7325 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
7326 return llvm::makeArrayRef(GCCRegNames);
7329 bool SystemZTargetInfo::
7330 validateAsmConstraint(const char *&Name,
7331 TargetInfo::ConstraintInfo &Info) const {
7336 case 'a': // Address register
7337 case 'd': // Data register (equivalent to 'r')
7338 case 'f': // Floating-point register
7339 Info.setAllowsRegister();
7342 case 'I': // Unsigned 8-bit constant
7343 case 'J': // Unsigned 12-bit constant
7344 case 'K': // Signed 16-bit constant
7345 case 'L': // Signed 20-bit displacement (on all targets we support)
7346 case 'M': // 0x7fffffff
7349 case 'Q': // Memory with base and unsigned 12-bit displacement
7350 case 'R': // Likewise, plus an index
7351 case 'S': // Memory with base and signed 20-bit displacement
7352 case 'T': // Likewise, plus an index
7353 Info.setAllowsMemory();
7358 class MSP430TargetInfo : public TargetInfo {
7359 static const char *const GCCRegNames[];
7362 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7363 : TargetInfo(Triple) {
7364 TLSSupported = false;
7369 LongAlign = LongLongAlign = 16;
7373 SizeType = UnsignedInt;
7374 IntMaxType = SignedLongLong;
7375 IntPtrType = SignedInt;
7376 PtrDiffType = SignedInt;
7377 SigAtomicType = SignedLong;
7378 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16");
7380 void getTargetDefines(const LangOptions &Opts,
7381 MacroBuilder &Builder) const override {
7382 Builder.defineMacro("MSP430");
7383 Builder.defineMacro("__MSP430__");
7384 // FIXME: defines for different 'flavours' of MCU
7386 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7387 // FIXME: Implement.
7390 bool hasFeature(StringRef Feature) const override {
7391 return Feature == "msp430";
7393 ArrayRef<const char *> getGCCRegNames() const override;
7394 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7398 bool validateAsmConstraint(const char *&Name,
7399 TargetInfo::ConstraintInfo &info) const override {
7402 case 'K': // the constant 1
7403 case 'L': // constant -1^20 .. 1^19
7404 case 'M': // constant 1-4:
7407 // No target constraints for now.
7410 const char *getClobbers() const override {
7411 // FIXME: Is this really right?
7414 BuiltinVaListKind getBuiltinVaListKind() const override {
7416 return TargetInfo::CharPtrBuiltinVaList;
7420 const char *const MSP430TargetInfo::GCCRegNames[] = {
7421 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7422 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
7424 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const {
7425 return llvm::makeArrayRef(GCCRegNames);
7428 // LLVM and Clang cannot be used directly to output native binaries for
7429 // target, but is used to compile C code to llvm bitcode with correct
7430 // type and alignment information.
7432 // TCE uses the llvm bitcode as input and uses it for generating customized
7433 // target processor and program binary. TCE co-design environment is
7434 // publicly available in http://tce.cs.tut.fi
7436 static const unsigned TCEOpenCLAddrSpaceMap[] = {
7440 5, // opencl_constant
7441 // FIXME: generic has to be added to the target
7442 0, // opencl_generic
7448 class TCETargetInfo : public TargetInfo {
7450 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7451 : TargetInfo(Triple) {
7452 TLSSupported = false;
7454 LongWidth = LongLongWidth = 32;
7457 LongAlign = LongLongAlign = 32;
7460 SizeType = UnsignedInt;
7461 IntMaxType = SignedLong;
7462 IntPtrType = SignedInt;
7463 PtrDiffType = SignedInt;
7468 LongDoubleWidth = 32;
7469 LongDoubleAlign = 32;
7470 FloatFormat = &llvm::APFloat::IEEEsingle();
7471 DoubleFormat = &llvm::APFloat::IEEEsingle();
7472 LongDoubleFormat = &llvm::APFloat::IEEEsingle();
7473 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-"
7474 "i16:16:32-i32:32:32-i64:32:32-"
7475 "f32:32:32-f64:32:32-v64:32:32-"
7476 "v128:32:32-v256:32:32-v512:32:32-"
7477 "v1024:32:32-a0:0:32-n32");
7478 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
7479 UseAddrSpaceMapMangling = true;
7482 void getTargetDefines(const LangOptions &Opts,
7483 MacroBuilder &Builder) const override {
7484 DefineStd(Builder, "tce", Opts);
7485 Builder.defineMacro("__TCE__");
7486 Builder.defineMacro("__TCE_V1__");
7488 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; }
7490 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7491 const char *getClobbers() const override { return ""; }
7492 BuiltinVaListKind getBuiltinVaListKind() const override {
7493 return TargetInfo::VoidPtrBuiltinVaList;
7495 ArrayRef<const char *> getGCCRegNames() const override { return None; }
7496 bool validateAsmConstraint(const char *&Name,
7497 TargetInfo::ConstraintInfo &info) const override {
7500 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7505 class TCELETargetInfo : public TCETargetInfo {
7507 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7508 : TCETargetInfo(Triple, Opts) {
7511 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-"
7512 "i16:16:32-i32:32:32-i64:32:32-"
7513 "f32:32:32-f64:32:32-v64:32:32-"
7514 "v128:32:32-v256:32:32-v512:32:32-"
7515 "v1024:32:32-a0:0:32-n32");
7519 virtual void getTargetDefines(const LangOptions &Opts,
7520 MacroBuilder &Builder) const {
7521 DefineStd(Builder, "tcele", Opts);
7522 Builder.defineMacro("__TCE__");
7523 Builder.defineMacro("__TCE_V1__");
7524 Builder.defineMacro("__TCELE__");
7525 Builder.defineMacro("__TCELE_V1__");
7530 class BPFTargetInfo : public TargetInfo {
7532 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7533 : TargetInfo(Triple) {
7534 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7535 SizeType = UnsignedLong;
7536 PtrDiffType = SignedLong;
7537 IntPtrType = SignedLong;
7538 IntMaxType = SignedLong;
7539 Int64Type = SignedLong;
7541 if (Triple.getArch() == llvm::Triple::bpfeb) {
7542 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128");
7544 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
7546 MaxAtomicPromoteWidth = 64;
7547 MaxAtomicInlineWidth = 64;
7548 TLSSupported = false;
7550 void getTargetDefines(const LangOptions &Opts,
7551 MacroBuilder &Builder) const override {
7552 DefineStd(Builder, "bpf", Opts);
7553 Builder.defineMacro("__BPF__");
7555 bool hasFeature(StringRef Feature) const override {
7556 return Feature == "bpf";
7559 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7560 const char *getClobbers() const override {
7563 BuiltinVaListKind getBuiltinVaListKind() const override {
7564 return TargetInfo::VoidPtrBuiltinVaList;
7566 ArrayRef<const char *> getGCCRegNames() const override {
7569 bool validateAsmConstraint(const char *&Name,
7570 TargetInfo::ConstraintInfo &info) const override {
7573 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7578 class MipsTargetInfo : public TargetInfo {
7579 void setDataLayout() {
7583 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
7584 else if (ABI == "n32")
7585 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7586 else if (ABI == "n64")
7587 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7589 llvm_unreachable("Invalid ABI");
7592 resetDataLayout(("E-" + Layout).str());
7594 resetDataLayout(("e-" + Layout).str());
7598 static const Builtin::Info BuiltinInfo[];
7605 bool CanUseBSDABICalls;
7607 HardFloat, SoftFloat
7619 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7620 : TargetInfo(Triple), IsMips16(false), IsMicromips(false),
7621 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false),
7622 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP),
7623 HasMSA(false), HasFP64(false) {
7624 TheCXXABI.set(TargetCXXABI::GenericMIPS);
7626 setABI((getTriple().getArch() == llvm::Triple::mips ||
7627 getTriple().getArch() == llvm::Triple::mipsel)
7631 CPU = ABI == "o32" ? "mips32r2" : "mips64r2";
7633 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD ||
7634 Triple.getOS() == llvm::Triple::OpenBSD;
7637 bool isNaN2008Default() const {
7638 return CPU == "mips32r6" || CPU == "mips64r6";
7641 bool isFP64Default() const {
7642 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
7645 bool isNan2008() const override {
7649 bool processorSupportsGPR64() const {
7650 return llvm::StringSwitch<bool>(CPU)
7651 .Case("mips3", true)
7652 .Case("mips4", true)
7653 .Case("mips5", true)
7654 .Case("mips64", true)
7655 .Case("mips64r2", true)
7656 .Case("mips64r3", true)
7657 .Case("mips64r5", true)
7658 .Case("mips64r6", true)
7659 .Case("octeon", true)
7664 StringRef getABI() const override { return ABI; }
7665 bool setABI(const std::string &Name) override {
7666 if (Name == "o32") {
7672 if (Name == "n32") {
7677 if (Name == "n64") {
7685 void setO32ABITypes() {
7686 Int64Type = SignedLongLong;
7687 IntMaxType = Int64Type;
7688 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
7689 LongDoubleWidth = LongDoubleAlign = 64;
7690 LongWidth = LongAlign = 32;
7691 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
7692 PointerWidth = PointerAlign = 32;
7693 PtrDiffType = SignedInt;
7694 SizeType = UnsignedInt;
7698 void setN32N64ABITypes() {
7699 LongDoubleWidth = LongDoubleAlign = 128;
7700 LongDoubleFormat = &llvm::APFloat::IEEEquad();
7701 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
7702 LongDoubleWidth = LongDoubleAlign = 64;
7703 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
7705 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7706 SuitableAlign = 128;
7709 void setN64ABITypes() {
7710 setN32N64ABITypes();
7711 if (getTriple().getOS() == llvm::Triple::OpenBSD) {
7712 Int64Type = SignedLongLong;
7714 Int64Type = SignedLong;
7716 IntMaxType = Int64Type;
7717 LongWidth = LongAlign = 64;
7718 PointerWidth = PointerAlign = 64;
7719 PtrDiffType = SignedLong;
7720 SizeType = UnsignedLong;
7723 void setN32ABITypes() {
7724 setN32N64ABITypes();
7725 Int64Type = SignedLongLong;
7726 IntMaxType = Int64Type;
7727 LongWidth = LongAlign = 32;
7728 PointerWidth = PointerAlign = 32;
7729 PtrDiffType = SignedInt;
7730 SizeType = UnsignedInt;
7733 bool setCPU(const std::string &Name) override {
7735 return llvm::StringSwitch<bool>(Name)
7736 .Case("mips1", true)
7737 .Case("mips2", true)
7738 .Case("mips3", true)
7739 .Case("mips4", true)
7740 .Case("mips5", true)
7741 .Case("mips32", true)
7742 .Case("mips32r2", true)
7743 .Case("mips32r3", true)
7744 .Case("mips32r5", true)
7745 .Case("mips32r6", true)
7746 .Case("mips64", true)
7747 .Case("mips64r2", true)
7748 .Case("mips64r3", true)
7749 .Case("mips64r5", true)
7750 .Case("mips64r6", true)
7751 .Case("octeon", true)
7752 .Case("p5600", true)
7755 const std::string& getCPU() const { return CPU; }
7757 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7759 const std::vector<std::string> &FeaturesVec) const override {
7762 if (CPU == "octeon")
7763 Features["mips64r2"] = Features["cnmips"] = true;
7765 Features[CPU] = true;
7766 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7769 void getTargetDefines(const LangOptions &Opts,
7770 MacroBuilder &Builder) const override {
7772 DefineStd(Builder, "MIPSEB", Opts);
7773 Builder.defineMacro("_MIPSEB");
7775 DefineStd(Builder, "MIPSEL", Opts);
7776 Builder.defineMacro("_MIPSEL");
7779 Builder.defineMacro("__mips__");
7780 Builder.defineMacro("_mips");
7782 Builder.defineMacro("mips");
7785 Builder.defineMacro("__mips", "32");
7786 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
7788 Builder.defineMacro("__mips", "64");
7789 Builder.defineMacro("__mips64");
7790 Builder.defineMacro("__mips64__");
7791 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
7794 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU())
7795 .Cases("mips32", "mips64", "1")
7796 .Cases("mips32r2", "mips64r2", "2")
7797 .Cases("mips32r3", "mips64r3", "3")
7798 .Cases("mips32r5", "mips64r5", "5")
7799 .Cases("mips32r6", "mips64r6", "6")
7801 if (!ISARev.empty())
7802 Builder.defineMacro("__mips_isa_rev", ISARev);
7805 Builder.defineMacro("__mips_o32");
7806 Builder.defineMacro("_ABIO32", "1");
7807 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
7808 } else if (ABI == "n32") {
7809 Builder.defineMacro("__mips_n32");
7810 Builder.defineMacro("_ABIN32", "2");
7811 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
7812 } else if (ABI == "n64") {
7813 Builder.defineMacro("__mips_n64");
7814 Builder.defineMacro("_ABI64", "3");
7815 Builder.defineMacro("_MIPS_SIM", "_ABI64");
7817 llvm_unreachable("Invalid ABI.");
7819 if (!IsNoABICalls) {
7820 Builder.defineMacro("__mips_abicalls");
7821 if (CanUseBSDABICalls)
7822 Builder.defineMacro("__ABICALLS__");
7825 Builder.defineMacro("__REGISTER_PREFIX__", "");
7829 Builder.defineMacro("__mips_hard_float", Twine(1));
7832 Builder.defineMacro("__mips_soft_float", Twine(1));
7837 Builder.defineMacro("__mips_single_float", Twine(1));
7839 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
7840 Builder.defineMacro("_MIPS_FPSET",
7841 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
7844 Builder.defineMacro("__mips16", Twine(1));
7847 Builder.defineMacro("__mips_micromips", Twine(1));
7850 Builder.defineMacro("__mips_nan2008", Twine(1));
7856 Builder.defineMacro("__mips_dsp_rev", Twine(1));
7857 Builder.defineMacro("__mips_dsp", Twine(1));
7860 Builder.defineMacro("__mips_dsp_rev", Twine(2));
7861 Builder.defineMacro("__mips_dspr2", Twine(1));
7862 Builder.defineMacro("__mips_dsp", Twine(1));
7867 Builder.defineMacro("__mips_msa", Twine(1));
7869 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
7870 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
7871 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
7873 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
7874 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
7876 // These shouldn't be defined for MIPS-I but there's no need to check
7877 // for that since MIPS-I isn't supported.
7878 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
7879 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
7880 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
7882 // 32-bit MIPS processors don't have the necessary lld/scd instructions
7883 // found in 64-bit processors. In the case of O32 on a 64-bit processor,
7884 // the instructions exist but using them violates the ABI since they
7885 // require 64-bit GPRs and O32 only supports 32-bit GPRs.
7886 if (ABI == "n32" || ABI == "n64")
7887 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
7890 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7891 return llvm::makeArrayRef(BuiltinInfo,
7892 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin);
7894 bool hasFeature(StringRef Feature) const override {
7895 return llvm::StringSwitch<bool>(Feature)
7897 .Case("fp64", HasFP64)
7900 BuiltinVaListKind getBuiltinVaListKind() const override {
7901 return TargetInfo::VoidPtrBuiltinVaList;
7903 ArrayRef<const char *> getGCCRegNames() const override {
7904 static const char *const GCCRegNames[] = {
7905 // CPU register names
7906 // Must match second column of GCCRegAliases
7907 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
7908 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
7909 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
7910 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
7911 // Floating point register names
7912 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
7913 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
7914 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
7915 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
7916 // Hi/lo and condition register names
7917 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
7918 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo",
7920 // MSA register names
7921 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
7922 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
7923 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
7924 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
7925 // MSA control register names
7926 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
7927 "$msarequest", "$msamap", "$msaunmap"
7929 return llvm::makeArrayRef(GCCRegNames);
7931 bool validateAsmConstraint(const char *&Name,
7932 TargetInfo::ConstraintInfo &Info) const override {
7936 case 'r': // CPU registers.
7937 case 'd': // Equivalent to "r" unless generating MIPS16 code.
7938 case 'y': // Equivalent to "r", backward compatibility only.
7939 case 'f': // floating-point registers.
7940 case 'c': // $25 for indirect jumps
7941 case 'l': // lo register
7942 case 'x': // hilo register pair
7943 Info.setAllowsRegister();
7945 case 'I': // Signed 16-bit constant
7946 case 'J': // Integer 0
7947 case 'K': // Unsigned 16-bit constant
7948 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
7949 case 'M': // Constants not loadable via lui, addiu, or ori
7950 case 'N': // Constant -1 to -65535
7951 case 'O': // A signed 15-bit constant
7952 case 'P': // A constant between 1 go 65535
7954 case 'R': // An address that can be used in a non-macro load or store
7955 Info.setAllowsMemory();
7958 if (Name[1] == 'C') { // An address usable by ll, and sc.
7959 Info.setAllowsMemory();
7960 Name++; // Skip over 'Z'.
7967 std::string convertConstraint(const char *&Constraint) const override {
7969 switch (*Constraint) {
7970 case 'Z': // Two-character constraint; add "^" hint for later parsing.
7971 if (Constraint[1] == 'C') {
7972 R = std::string("^") + std::string(Constraint, 2);
7978 return TargetInfo::convertConstraint(Constraint);
7981 const char *getClobbers() const override {
7982 // In GCC, $1 is not widely used in generated code (it's used only in a few
7983 // specific situations), so there is no real need for users to add it to
7984 // the clobbers list if they want to use it in their inline assembly code.
7986 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
7987 // code generation, so using it in inline assembly without adding it to the
7988 // clobbers list can cause conflicts between the inline assembly code and
7989 // the surrounding generated code.
7991 // Another problem is that LLVM is allowed to choose $1 for inline assembly
7992 // operands, which will conflict with the ".set at" assembler option (which
7993 // we use only for inline assembly, in order to maintain compatibility with
7994 // GCC) and will also conflict with the user's usage of $1.
7996 // The easiest way to avoid these conflicts and keep $1 as an allocatable
7997 // register for generated code is to automatically clobber $1 for all inline
8000 // FIXME: We should automatically clobber $1 only for inline assembly code
8001 // which actually uses it. This would allow LLVM to use $1 for inline
8002 // assembly operands if the user's assembly code doesn't use it.
8006 bool handleTargetFeatures(std::vector<std::string> &Features,
8007 DiagnosticsEngine &Diags) override {
8009 IsMicromips = false;
8010 IsNan2008 = isNaN2008Default();
8011 IsSingleFloat = false;
8012 FloatABI = HardFloat;
8014 HasFP64 = isFP64Default();
8016 for (const auto &Feature : Features) {
8017 if (Feature == "+single-float")
8018 IsSingleFloat = true;
8019 else if (Feature == "+soft-float")
8020 FloatABI = SoftFloat;
8021 else if (Feature == "+mips16")
8023 else if (Feature == "+micromips")
8025 else if (Feature == "+dsp")
8026 DspRev = std::max(DspRev, DSP1);
8027 else if (Feature == "+dspr2")
8028 DspRev = std::max(DspRev, DSP2);
8029 else if (Feature == "+msa")
8031 else if (Feature == "+fp64")
8033 else if (Feature == "-fp64")
8035 else if (Feature == "+nan2008")
8037 else if (Feature == "-nan2008")
8039 else if (Feature == "+noabicalls")
8040 IsNoABICalls = true;
8048 int getEHDataRegisterNumber(unsigned RegNo) const override {
8049 if (RegNo == 0) return 4;
8050 if (RegNo == 1) return 5;
8054 bool isCLZForZeroUndef() const override { return false; }
8056 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8057 static const TargetInfo::GCCRegAlias O32RegAliases[] = {
8058 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
8059 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
8060 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"},
8061 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"},
8062 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"},
8063 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
8064 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
8065 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
8066 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
8067 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
8069 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = {
8070 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
8071 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
8072 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"},
8073 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"},
8074 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"},
8075 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
8076 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
8077 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
8078 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
8079 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
8082 return llvm::makeArrayRef(O32RegAliases);
8083 return llvm::makeArrayRef(NewABIRegAliases);
8086 bool hasInt128Type() const override {
8087 return ABI == "n32" || ABI == "n64";
8090 bool validateTarget(DiagnosticsEngine &Diags) const override {
8091 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle
8092 // this yet. It's better to fail here than on the backend assertion.
8093 if (processorSupportsGPR64() && ABI == "o32") {
8094 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
8098 // 64-bit ABI's require 64-bit CPU's.
8099 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) {
8100 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
8104 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend
8105 // can't handle this yet. It's better to fail here than on the
8106 // backend assertion.
8107 if ((getTriple().getArch() == llvm::Triple::mips64 ||
8108 getTriple().getArch() == llvm::Triple::mips64el) &&
8110 Diags.Report(diag::err_target_unsupported_abi_for_triple)
8111 << ABI << getTriple().str();
8115 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend
8116 // can't handle this yet. It's better to fail here than on the
8117 // backend assertion.
8118 if ((getTriple().getArch() == llvm::Triple::mips ||
8119 getTriple().getArch() == llvm::Triple::mipsel) &&
8120 (ABI == "n32" || ABI == "n64")) {
8121 Diags.Report(diag::err_target_unsupported_abi_for_triple)
8122 << ABI << getTriple().str();
8130 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = {
8131 #define BUILTIN(ID, TYPE, ATTRS) \
8132 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8133 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8134 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8135 #include "clang/Basic/BuiltinsMips.def"
8138 class PNaClTargetInfo : public TargetInfo {
8140 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8141 : TargetInfo(Triple) {
8142 this->LongAlign = 32;
8143 this->LongWidth = 32;
8144 this->PointerAlign = 32;
8145 this->PointerWidth = 32;
8146 this->IntMaxType = TargetInfo::SignedLongLong;
8147 this->Int64Type = TargetInfo::SignedLongLong;
8148 this->DoubleAlign = 64;
8149 this->LongDoubleWidth = 64;
8150 this->LongDoubleAlign = 64;
8151 this->SizeType = TargetInfo::UnsignedInt;
8152 this->PtrDiffType = TargetInfo::SignedInt;
8153 this->IntPtrType = TargetInfo::SignedInt;
8154 this->RegParmMax = 0; // Disallow regparm
8157 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
8158 Builder.defineMacro("__le32__");
8159 Builder.defineMacro("__pnacl__");
8161 void getTargetDefines(const LangOptions &Opts,
8162 MacroBuilder &Builder) const override {
8163 getArchDefines(Opts, Builder);
8165 bool hasFeature(StringRef Feature) const override {
8166 return Feature == "pnacl";
8168 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
8169 BuiltinVaListKind getBuiltinVaListKind() const override {
8170 return TargetInfo::PNaClABIBuiltinVaList;
8172 ArrayRef<const char *> getGCCRegNames() const override;
8173 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
8174 bool validateAsmConstraint(const char *&Name,
8175 TargetInfo::ConstraintInfo &Info) const override {
8179 const char *getClobbers() const override {
8184 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const {
8188 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const {
8192 // We attempt to use PNaCl (le32) frontend and Mips32EL backend.
8193 class NaClMips32TargetInfo : public MipsTargetInfo {
8195 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8196 : MipsTargetInfo(Triple, Opts) {}
8198 BuiltinVaListKind getBuiltinVaListKind() const override {
8199 return TargetInfo::PNaClABIBuiltinVaList;
8203 class Le64TargetInfo : public TargetInfo {
8204 static const Builtin::Info BuiltinInfo[];
8207 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8208 : TargetInfo(Triple) {
8209 NoAsmVariants = true;
8210 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
8211 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8212 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128");
8215 void getTargetDefines(const LangOptions &Opts,
8216 MacroBuilder &Builder) const override {
8217 DefineStd(Builder, "unix", Opts);
8218 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
8219 Builder.defineMacro("__ELF__");
8221 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8222 return llvm::makeArrayRef(BuiltinInfo,
8223 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin);
8225 BuiltinVaListKind getBuiltinVaListKind() const override {
8226 return TargetInfo::PNaClABIBuiltinVaList;
8228 const char *getClobbers() const override { return ""; }
8229 ArrayRef<const char *> getGCCRegNames() const override {
8232 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8235 bool validateAsmConstraint(const char *&Name,
8236 TargetInfo::ConstraintInfo &Info) const override {
8240 bool hasProtectedVisibility() const override { return false; }
8243 class WebAssemblyTargetInfo : public TargetInfo {
8244 static const Builtin::Info BuiltinInfo[];
8252 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &)
8253 : TargetInfo(T), SIMDLevel(NoSIMD) {
8254 NoAsmVariants = true;
8255 SuitableAlign = 128;
8256 LargeArrayMinWidth = 128;
8257 LargeArrayAlign = 128;
8258 SimdDefaultAlign = 128;
8259 SigAtomicType = SignedLong;
8260 LongDoubleWidth = LongDoubleAlign = 128;
8261 LongDoubleFormat = &llvm::APFloat::IEEEquad();
8262 SizeType = UnsignedInt;
8263 PtrDiffType = SignedInt;
8264 IntPtrType = SignedInt;
8268 void getTargetDefines(const LangOptions &Opts,
8269 MacroBuilder &Builder) const override {
8270 defineCPUMacros(Builder, "wasm", /*Tuning=*/false);
8271 if (SIMDLevel >= SIMD128)
8272 Builder.defineMacro("__wasm_simd128__");
8277 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
8279 const std::vector<std::string> &FeaturesVec) const override {
8280 if (CPU == "bleeding-edge")
8281 Features["simd128"] = true;
8282 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
8284 bool hasFeature(StringRef Feature) const final {
8285 return llvm::StringSwitch<bool>(Feature)
8286 .Case("simd128", SIMDLevel >= SIMD128)
8289 bool handleTargetFeatures(std::vector<std::string> &Features,
8290 DiagnosticsEngine &Diags) final {
8291 for (const auto &Feature : Features) {
8292 if (Feature == "+simd128") {
8293 SIMDLevel = std::max(SIMDLevel, SIMD128);
8296 if (Feature == "-simd128") {
8297 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1));
8301 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature
8302 << "-target-feature";
8307 bool setCPU(const std::string &Name) final {
8308 return llvm::StringSwitch<bool>(Name)
8310 .Case("bleeding-edge", true)
8311 .Case("generic", true)
8314 ArrayRef<Builtin::Info> getTargetBuiltins() const final {
8315 return llvm::makeArrayRef(BuiltinInfo,
8316 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin);
8318 BuiltinVaListKind getBuiltinVaListKind() const final {
8319 return VoidPtrBuiltinVaList;
8321 ArrayRef<const char *> getGCCRegNames() const final {
8324 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final {
8328 validateAsmConstraint(const char *&Name,
8329 TargetInfo::ConstraintInfo &Info) const final {
8332 const char *getClobbers() const final { return ""; }
8333 bool isCLZForZeroUndef() const final { return false; }
8334 bool hasInt128Type() const final { return true; }
8335 IntType getIntTypeByWidth(unsigned BitWidth,
8336 bool IsSigned) const final {
8337 // WebAssembly prefers long long for explicitly 64-bit integers.
8338 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
8339 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
8341 IntType getLeastIntTypeByWidth(unsigned BitWidth,
8342 bool IsSigned) const final {
8343 // WebAssembly uses long long for int_least64_t and int_fast64_t.
8344 return BitWidth == 64
8345 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
8346 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
8350 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = {
8351 #define BUILTIN(ID, TYPE, ATTRS) \
8352 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8353 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8354 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8355 #include "clang/Basic/BuiltinsWebAssembly.def"
8358 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo {
8360 explicit WebAssembly32TargetInfo(const llvm::Triple &T,
8361 const TargetOptions &Opts)
8362 : WebAssemblyTargetInfo(T, Opts) {
8363 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
8364 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128");
8368 void getTargetDefines(const LangOptions &Opts,
8369 MacroBuilder &Builder) const override {
8370 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
8371 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false);
8375 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo {
8377 explicit WebAssembly64TargetInfo(const llvm::Triple &T,
8378 const TargetOptions &Opts)
8379 : WebAssemblyTargetInfo(T, Opts) {
8380 LongAlign = LongWidth = 64;
8381 PointerAlign = PointerWidth = 64;
8382 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8383 SizeType = UnsignedLong;
8384 PtrDiffType = SignedLong;
8385 IntPtrType = SignedLong;
8386 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
8390 void getTargetDefines(const LangOptions &Opts,
8391 MacroBuilder &Builder) const override {
8392 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
8393 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false);
8397 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
8398 #define BUILTIN(ID, TYPE, ATTRS) \
8399 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8400 #include "clang/Basic/BuiltinsLe64.def"
8403 static const unsigned SPIRAddrSpaceMap[] = {
8407 2, // opencl_constant
8408 4, // opencl_generic
8413 class SPIRTargetInfo : public TargetInfo {
8415 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8416 : TargetInfo(Triple) {
8417 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
8418 "SPIR target must use unknown OS");
8419 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
8420 "SPIR target must use unknown environment type");
8421 TLSSupported = false;
8422 LongWidth = LongAlign = 64;
8423 AddrSpaceMap = &SPIRAddrSpaceMap;
8424 UseAddrSpaceMapMangling = true;
8425 // Define available target features
8426 // These must be defined in sorted order!
8427 NoAsmVariants = true;
8429 void getTargetDefines(const LangOptions &Opts,
8430 MacroBuilder &Builder) const override {
8431 DefineStd(Builder, "SPIR", Opts);
8433 bool hasFeature(StringRef Feature) const override {
8434 return Feature == "spir";
8437 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
8438 const char *getClobbers() const override { return ""; }
8439 ArrayRef<const char *> getGCCRegNames() const override { return None; }
8440 bool validateAsmConstraint(const char *&Name,
8441 TargetInfo::ConstraintInfo &info) const override {
8444 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8447 BuiltinVaListKind getBuiltinVaListKind() const override {
8448 return TargetInfo::VoidPtrBuiltinVaList;
8451 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
8452 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK
8456 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
8457 return CC_SpirFunction;
8460 void setSupportedOpenCLOpts() override {
8461 // Assume all OpenCL extensions and optional core features are supported
8462 // for SPIR since it is a generic target.
8463 getSupportedOpenCLOpts().supportAll();
8467 class SPIR32TargetInfo : public SPIRTargetInfo {
8469 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8470 : SPIRTargetInfo(Triple, Opts) {
8471 PointerWidth = PointerAlign = 32;
8472 SizeType = TargetInfo::UnsignedInt;
8473 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
8474 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
8475 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
8477 void getTargetDefines(const LangOptions &Opts,
8478 MacroBuilder &Builder) const override {
8479 DefineStd(Builder, "SPIR32", Opts);
8483 class SPIR64TargetInfo : public SPIRTargetInfo {
8485 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8486 : SPIRTargetInfo(Triple, Opts) {
8487 PointerWidth = PointerAlign = 64;
8488 SizeType = TargetInfo::UnsignedLong;
8489 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
8490 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
8491 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
8493 void getTargetDefines(const LangOptions &Opts,
8494 MacroBuilder &Builder) const override {
8495 DefineStd(Builder, "SPIR64", Opts);
8499 class XCoreTargetInfo : public TargetInfo {
8500 static const Builtin::Info BuiltinInfo[];
8502 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8503 : TargetInfo(Triple) {
8504 NoAsmVariants = true;
8507 DoubleAlign = LongDoubleAlign = 32;
8508 SizeType = UnsignedInt;
8509 PtrDiffType = SignedInt;
8510 IntPtrType = SignedInt;
8511 WCharType = UnsignedChar;
8512 WIntType = UnsignedInt;
8513 UseZeroLengthBitfieldAlignment = true;
8514 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
8515 "-f64:32-a:0:32-n32");
8517 void getTargetDefines(const LangOptions &Opts,
8518 MacroBuilder &Builder) const override {
8519 Builder.defineMacro("__XS1B__");
8521 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8522 return llvm::makeArrayRef(BuiltinInfo,
8523 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin);
8525 BuiltinVaListKind getBuiltinVaListKind() const override {
8526 return TargetInfo::VoidPtrBuiltinVaList;
8528 const char *getClobbers() const override {
8531 ArrayRef<const char *> getGCCRegNames() const override {
8532 static const char * const GCCRegNames[] = {
8533 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8534 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
8536 return llvm::makeArrayRef(GCCRegNames);
8538 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8541 bool validateAsmConstraint(const char *&Name,
8542 TargetInfo::ConstraintInfo &Info) const override {
8545 int getEHDataRegisterNumber(unsigned RegNo) const override {
8546 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
8547 return (RegNo < 2)? RegNo : -1;
8549 bool allowsLargerPreferedTypeAlignment() const override {
8554 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
8555 #define BUILTIN(ID, TYPE, ATTRS) \
8556 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8557 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8558 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8559 #include "clang/Basic/BuiltinsXCore.def"
8562 // x86_32 Android target
8563 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
8565 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8566 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) {
8568 LongDoubleWidth = 64;
8569 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
8573 // x86_64 Android target
8574 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
8576 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8577 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) {
8578 LongDoubleFormat = &llvm::APFloat::IEEEquad();
8581 bool useFloat128ManglingForLongDouble() const override {
8586 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes
8587 class RenderScript32TargetInfo : public ARMleTargetInfo {
8589 RenderScript32TargetInfo(const llvm::Triple &Triple,
8590 const TargetOptions &Opts)
8591 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(),
8593 Triple.getEnvironmentName()),
8595 IsRenderScriptTarget = true;
8596 LongWidth = LongAlign = 64;
8598 void getTargetDefines(const LangOptions &Opts,
8599 MacroBuilder &Builder) const override {
8600 Builder.defineMacro("__RENDERSCRIPT__");
8601 ARMleTargetInfo::getTargetDefines(Opts, Builder);
8605 // 64-bit RenderScript is aarch64
8606 class RenderScript64TargetInfo : public AArch64leTargetInfo {
8608 RenderScript64TargetInfo(const llvm::Triple &Triple,
8609 const TargetOptions &Opts)
8610 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(),
8612 Triple.getEnvironmentName()),
8614 IsRenderScriptTarget = true;
8617 void getTargetDefines(const LangOptions &Opts,
8618 MacroBuilder &Builder) const override {
8619 Builder.defineMacro("__RENDERSCRIPT__");
8620 AArch64leTargetInfo::getTargetDefines(Opts, Builder);
8624 /// Information about a specific microcontroller.
8627 const char *DefineName;
8630 // This list should be kept up-to-date with AVRDevices.td in LLVM.
8631 static ArrayRef<MCUInfo> AVRMcus = {
8632 { "at90s1200", "__AVR_AT90S1200__" },
8633 { "attiny11", "__AVR_ATtiny11__" },
8634 { "attiny12", "__AVR_ATtiny12__" },
8635 { "attiny15", "__AVR_ATtiny15__" },
8636 { "attiny28", "__AVR_ATtiny28__" },
8637 { "at90s2313", "__AVR_AT90S2313__" },
8638 { "at90s2323", "__AVR_AT90S2323__" },
8639 { "at90s2333", "__AVR_AT90S2333__" },
8640 { "at90s2343", "__AVR_AT90S2343__" },
8641 { "attiny22", "__AVR_ATtiny22__" },
8642 { "attiny26", "__AVR_ATtiny26__" },
8643 { "at86rf401", "__AVR_AT86RF401__" },
8644 { "at90s4414", "__AVR_AT90S4414__" },
8645 { "at90s4433", "__AVR_AT90S4433__" },
8646 { "at90s4434", "__AVR_AT90S4434__" },
8647 { "at90s8515", "__AVR_AT90S8515__" },
8648 { "at90c8534", "__AVR_AT90c8534__" },
8649 { "at90s8535", "__AVR_AT90S8535__" },
8650 { "ata5272", "__AVR_ATA5272__" },
8651 { "attiny13", "__AVR_ATtiny13__" },
8652 { "attiny13a", "__AVR_ATtiny13A__" },
8653 { "attiny2313", "__AVR_ATtiny2313__" },
8654 { "attiny2313a", "__AVR_ATtiny2313A__" },
8655 { "attiny24", "__AVR_ATtiny24__" },
8656 { "attiny24a", "__AVR_ATtiny24A__" },
8657 { "attiny4313", "__AVR_ATtiny4313__" },
8658 { "attiny44", "__AVR_ATtiny44__" },
8659 { "attiny44a", "__AVR_ATtiny44A__" },
8660 { "attiny84", "__AVR_ATtiny84__" },
8661 { "attiny84a", "__AVR_ATtiny84A__" },
8662 { "attiny25", "__AVR_ATtiny25__" },
8663 { "attiny45", "__AVR_ATtiny45__" },
8664 { "attiny85", "__AVR_ATtiny85__" },
8665 { "attiny261", "__AVR_ATtiny261__" },
8666 { "attiny261a", "__AVR_ATtiny261A__" },
8667 { "attiny461", "__AVR_ATtiny461__" },
8668 { "attiny461a", "__AVR_ATtiny461A__" },
8669 { "attiny861", "__AVR_ATtiny861__" },
8670 { "attiny861a", "__AVR_ATtiny861A__" },
8671 { "attiny87", "__AVR_ATtiny87__" },
8672 { "attiny43u", "__AVR_ATtiny43U__" },
8673 { "attiny48", "__AVR_ATtiny48__" },
8674 { "attiny88", "__AVR_ATtiny88__" },
8675 { "attiny828", "__AVR_ATtiny828__" },
8676 { "at43usb355", "__AVR_AT43USB355__" },
8677 { "at76c711", "__AVR_AT76C711__" },
8678 { "atmega103", "__AVR_ATmega103__" },
8679 { "at43usb320", "__AVR_AT43USB320__" },
8680 { "attiny167", "__AVR_ATtiny167__" },
8681 { "at90usb82", "__AVR_AT90USB82__" },
8682 { "at90usb162", "__AVR_AT90USB162__" },
8683 { "ata5505", "__AVR_ATA5505__" },
8684 { "atmega8u2", "__AVR_ATmega8U2__" },
8685 { "atmega16u2", "__AVR_ATmega16U2__" },
8686 { "atmega32u2", "__AVR_ATmega32U2__" },
8687 { "attiny1634", "__AVR_ATtiny1634__" },
8688 { "atmega8", "__AVR_ATmega8__" },
8689 { "ata6289", "__AVR_ATA6289__" },
8690 { "atmega8a", "__AVR_ATmega8A__" },
8691 { "ata6285", "__AVR_ATA6285__" },
8692 { "ata6286", "__AVR_ATA6286__" },
8693 { "atmega48", "__AVR_ATmega48__" },
8694 { "atmega48a", "__AVR_ATmega48A__" },
8695 { "atmega48pa", "__AVR_ATmega48PA__" },
8696 { "atmega48p", "__AVR_ATmega48P__" },
8697 { "atmega88", "__AVR_ATmega88__" },
8698 { "atmega88a", "__AVR_ATmega88A__" },
8699 { "atmega88p", "__AVR_ATmega88P__" },
8700 { "atmega88pa", "__AVR_ATmega88PA__" },
8701 { "atmega8515", "__AVR_ATmega8515__" },
8702 { "atmega8535", "__AVR_ATmega8535__" },
8703 { "atmega8hva", "__AVR_ATmega8HVA__" },
8704 { "at90pwm1", "__AVR_AT90PWM1__" },
8705 { "at90pwm2", "__AVR_AT90PWM2__" },
8706 { "at90pwm2b", "__AVR_AT90PWM2B__" },
8707 { "at90pwm3", "__AVR_AT90PWM3__" },
8708 { "at90pwm3b", "__AVR_AT90PWM3B__" },
8709 { "at90pwm81", "__AVR_AT90PWM81__" },
8710 { "ata5790", "__AVR_ATA5790__" },
8711 { "ata5795", "__AVR_ATA5795__" },
8712 { "atmega16", "__AVR_ATmega16__" },
8713 { "atmega16a", "__AVR_ATmega16A__" },
8714 { "atmega161", "__AVR_ATmega161__" },
8715 { "atmega162", "__AVR_ATmega162__" },
8716 { "atmega163", "__AVR_ATmega163__" },
8717 { "atmega164a", "__AVR_ATmega164A__" },
8718 { "atmega164p", "__AVR_ATmega164P__" },
8719 { "atmega164pa", "__AVR_ATmega164PA__" },
8720 { "atmega165", "__AVR_ATmega165__" },
8721 { "atmega165a", "__AVR_ATmega165A__" },
8722 { "atmega165p", "__AVR_ATmega165P__" },
8723 { "atmega165pa", "__AVR_ATmega165PA__" },
8724 { "atmega168", "__AVR_ATmega168__" },
8725 { "atmega168a", "__AVR_ATmega168A__" },
8726 { "atmega168p", "__AVR_ATmega168P__" },
8727 { "atmega168pa", "__AVR_ATmega168PA__" },
8728 { "atmega169", "__AVR_ATmega169__" },
8729 { "atmega169a", "__AVR_ATmega169A__" },
8730 { "atmega169p", "__AVR_ATmega169P__" },
8731 { "atmega169pa", "__AVR_ATmega169PA__" },
8732 { "atmega32", "__AVR_ATmega32__" },
8733 { "atmega32a", "__AVR_ATmega32A__" },
8734 { "atmega323", "__AVR_ATmega323__" },
8735 { "atmega324a", "__AVR_ATmega324A__" },
8736 { "atmega324p", "__AVR_ATmega324P__" },
8737 { "atmega324pa", "__AVR_ATmega324PA__" },
8738 { "atmega325", "__AVR_ATmega325__" },
8739 { "atmega325a", "__AVR_ATmega325A__" },
8740 { "atmega325p", "__AVR_ATmega325P__" },
8741 { "atmega325pa", "__AVR_ATmega325PA__" },
8742 { "atmega3250", "__AVR_ATmega3250__" },
8743 { "atmega3250a", "__AVR_ATmega3250A__" },
8744 { "atmega3250p", "__AVR_ATmega3250P__" },
8745 { "atmega3250pa", "__AVR_ATmega3250PA__" },
8746 { "atmega328", "__AVR_ATmega328__" },
8747 { "atmega328p", "__AVR_ATmega328P__" },
8748 { "atmega329", "__AVR_ATmega329__" },
8749 { "atmega329a", "__AVR_ATmega329A__" },
8750 { "atmega329p", "__AVR_ATmega329P__" },
8751 { "atmega329pa", "__AVR_ATmega329PA__" },
8752 { "atmega3290", "__AVR_ATmega3290__" },
8753 { "atmega3290a", "__AVR_ATmega3290A__" },
8754 { "atmega3290p", "__AVR_ATmega3290P__" },
8755 { "atmega3290pa", "__AVR_ATmega3290PA__" },
8756 { "atmega406", "__AVR_ATmega406__" },
8757 { "atmega64", "__AVR_ATmega64__" },
8758 { "atmega64a", "__AVR_ATmega64A__" },
8759 { "atmega640", "__AVR_ATmega640__" },
8760 { "atmega644", "__AVR_ATmega644__" },
8761 { "atmega644a", "__AVR_ATmega644A__" },
8762 { "atmega644p", "__AVR_ATmega644P__" },
8763 { "atmega644pa", "__AVR_ATmega644PA__" },
8764 { "atmega645", "__AVR_ATmega645__" },
8765 { "atmega645a", "__AVR_ATmega645A__" },
8766 { "atmega645p", "__AVR_ATmega645P__" },
8767 { "atmega649", "__AVR_ATmega649__" },
8768 { "atmega649a", "__AVR_ATmega649A__" },
8769 { "atmega649p", "__AVR_ATmega649P__" },
8770 { "atmega6450", "__AVR_ATmega6450__" },
8771 { "atmega6450a", "__AVR_ATmega6450A__" },
8772 { "atmega6450p", "__AVR_ATmega6450P__" },
8773 { "atmega6490", "__AVR_ATmega6490__" },
8774 { "atmega6490a", "__AVR_ATmega6490A__" },
8775 { "atmega6490p", "__AVR_ATmega6490P__" },
8776 { "atmega64rfr2", "__AVR_ATmega64RFR2__" },
8777 { "atmega644rfr2", "__AVR_ATmega644RFR2__" },
8778 { "atmega16hva", "__AVR_ATmega16HVA__" },
8779 { "atmega16hva2", "__AVR_ATmega16HVA2__" },
8780 { "atmega16hvb", "__AVR_ATmega16HVB__" },
8781 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" },
8782 { "atmega32hvb", "__AVR_ATmega32HVB__" },
8783 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" },
8784 { "atmega64hve", "__AVR_ATmega64HVE__" },
8785 { "at90can32", "__AVR_AT90CAN32__" },
8786 { "at90can64", "__AVR_AT90CAN64__" },
8787 { "at90pwm161", "__AVR_AT90PWM161__" },
8788 { "at90pwm216", "__AVR_AT90PWM216__" },
8789 { "at90pwm316", "__AVR_AT90PWM316__" },
8790 { "atmega32c1", "__AVR_ATmega32C1__" },
8791 { "atmega64c1", "__AVR_ATmega64C1__" },
8792 { "atmega16m1", "__AVR_ATmega16M1__" },
8793 { "atmega32m1", "__AVR_ATmega32M1__" },
8794 { "atmega64m1", "__AVR_ATmega64M1__" },
8795 { "atmega16u4", "__AVR_ATmega16U4__" },
8796 { "atmega32u4", "__AVR_ATmega32U4__" },
8797 { "atmega32u6", "__AVR_ATmega32U6__" },
8798 { "at90usb646", "__AVR_AT90USB646__" },
8799 { "at90usb647", "__AVR_AT90USB647__" },
8800 { "at90scr100", "__AVR_AT90SCR100__" },
8801 { "at94k", "__AVR_AT94K__" },
8802 { "m3000", "__AVR_AT000__" },
8803 { "atmega128", "__AVR_ATmega128__" },
8804 { "atmega128a", "__AVR_ATmega128A__" },
8805 { "atmega1280", "__AVR_ATmega1280__" },
8806 { "atmega1281", "__AVR_ATmega1281__" },
8807 { "atmega1284", "__AVR_ATmega1284__" },
8808 { "atmega1284p", "__AVR_ATmega1284P__" },
8809 { "atmega128rfa1", "__AVR_ATmega128RFA1__" },
8810 { "atmega128rfr2", "__AVR_ATmega128RFR2__" },
8811 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" },
8812 { "at90can128", "__AVR_AT90CAN128__" },
8813 { "at90usb1286", "__AVR_AT90USB1286__" },
8814 { "at90usb1287", "__AVR_AT90USB1287__" },
8815 { "atmega2560", "__AVR_ATmega2560__" },
8816 { "atmega2561", "__AVR_ATmega2561__" },
8817 { "atmega256rfr2", "__AVR_ATmega256RFR2__" },
8818 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" },
8819 { "atxmega16a4", "__AVR_ATxmega16A4__" },
8820 { "atxmega16a4u", "__AVR_ATxmega16a4U__" },
8821 { "atxmega16c4", "__AVR_ATxmega16C4__" },
8822 { "atxmega16d4", "__AVR_ATxmega16D4__" },
8823 { "atxmega32a4", "__AVR_ATxmega32A4__" },
8824 { "atxmega32a4u", "__AVR_ATxmega32A4U__" },
8825 { "atxmega32c4", "__AVR_ATxmega32C4__" },
8826 { "atxmega32d4", "__AVR_ATxmega32D4__" },
8827 { "atxmega32e5", "__AVR_ATxmega32E5__" },
8828 { "atxmega16e5", "__AVR_ATxmega16E5__" },
8829 { "atxmega8e5", "__AVR_ATxmega8E5__" },
8830 { "atxmega32x1", "__AVR_ATxmega32X1__" },
8831 { "atxmega64a3", "__AVR_ATxmega64A3__" },
8832 { "atxmega64a3u", "__AVR_ATxmega64A3U__" },
8833 { "atxmega64a4u", "__AVR_ATxmega64A4U__" },
8834 { "atxmega64b1", "__AVR_ATxmega64B1__" },
8835 { "atxmega64b3", "__AVR_ATxmega64B3__" },
8836 { "atxmega64c3", "__AVR_ATxmega64C3__" },
8837 { "atxmega64d3", "__AVR_ATxmega64D3__" },
8838 { "atxmega64d4", "__AVR_ATxmega64D4__" },
8839 { "atxmega64a1", "__AVR_ATxmega64A1__" },
8840 { "atxmega64a1u", "__AVR_ATxmega64A1U__" },
8841 { "atxmega128a3", "__AVR_ATxmega128A3__" },
8842 { "atxmega128a3u", "__AVR_ATxmega128A3U__" },
8843 { "atxmega128b1", "__AVR_ATxmega128B1__" },
8844 { "atxmega128b3", "__AVR_ATxmega128B3__" },
8845 { "atxmega128c3", "__AVR_ATxmega128C3__" },
8846 { "atxmega128d3", "__AVR_ATxmega128D3__" },
8847 { "atxmega128d4", "__AVR_ATxmega128D4__" },
8848 { "atxmega192a3", "__AVR_ATxmega192A3__" },
8849 { "atxmega192a3u", "__AVR_ATxmega192A3U__" },
8850 { "atxmega192c3", "__AVR_ATxmega192C3__" },
8851 { "atxmega192d3", "__AVR_ATxmega192D3__" },
8852 { "atxmega256a3", "__AVR_ATxmega256A3__" },
8853 { "atxmega256a3u", "__AVR_ATxmega256A3U__" },
8854 { "atxmega256a3b", "__AVR_ATxmega256A3B__" },
8855 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" },
8856 { "atxmega256c3", "__AVR_ATxmega256C3__" },
8857 { "atxmega256d3", "__AVR_ATxmega256D3__" },
8858 { "atxmega384c3", "__AVR_ATxmega384C3__" },
8859 { "atxmega384d3", "__AVR_ATxmega384D3__" },
8860 { "atxmega128a1", "__AVR_ATxmega128A1__" },
8861 { "atxmega128a1u", "__AVR_ATxmega128A1U__" },
8862 { "atxmega128a4u", "__AVR_ATxmega128a4U__" },
8863 { "attiny4", "__AVR_ATtiny4__" },
8864 { "attiny5", "__AVR_ATtiny5__" },
8865 { "attiny9", "__AVR_ATtiny9__" },
8866 { "attiny10", "__AVR_ATtiny10__" },
8867 { "attiny20", "__AVR_ATtiny20__" },
8868 { "attiny40", "__AVR_ATtiny40__" },
8869 { "attiny102", "__AVR_ATtiny102__" },
8870 { "attiny104", "__AVR_ATtiny104__" },
8874 class AVRTargetInfo : public TargetInfo {
8876 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8877 : TargetInfo(Triple) {
8878 TLSSupported = false;
8888 DefaultAlignForAttributeAligned = 8;
8895 DoubleFormat = &llvm::APFloat::IEEEsingle();
8896 LongDoubleWidth = 32;
8897 LongDoubleAlign = 8;
8898 LongDoubleFormat = &llvm::APFloat::IEEEsingle();
8899 SizeType = UnsignedInt;
8900 PtrDiffType = SignedInt;
8901 IntPtrType = SignedInt;
8902 Char16Type = UnsignedInt;
8903 WCharType = SignedInt;
8904 WIntType = SignedInt;
8905 Char32Type = UnsignedLong;
8906 SigAtomicType = SignedChar;
8907 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64"
8908 "-f32:32:32-f64:64:64-n8");
8911 void getTargetDefines(const LangOptions &Opts,
8912 MacroBuilder &Builder) const override {
8913 Builder.defineMacro("AVR");
8914 Builder.defineMacro("__AVR");
8915 Builder.defineMacro("__AVR__");
8917 if (!this->CPU.empty()) {
8918 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(),
8919 [&](const MCUInfo &Info) { return Info.Name == this->CPU; });
8921 if (It != AVRMcus.end())
8922 Builder.defineMacro(It->DefineName);
8926 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8930 BuiltinVaListKind getBuiltinVaListKind() const override {
8931 return TargetInfo::VoidPtrBuiltinVaList;
8934 const char *getClobbers() const override {
8938 ArrayRef<const char *> getGCCRegNames() const override {
8939 static const char * const GCCRegNames[] = {
8940 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8941 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8942 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8943 "r24", "r25", "X", "Y", "Z", "SP"
8945 return llvm::makeArrayRef(GCCRegNames);
8948 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8952 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
8953 static const TargetInfo::AddlRegName AddlRegNames[] = {
8954 { { "r26", "r27"}, 26 },
8955 { { "r28", "r29"}, 27 },
8956 { { "r30", "r31"}, 28 },
8957 { { "SPL", "SPH"}, 29 },
8959 return llvm::makeArrayRef(AddlRegNames);
8962 bool validateAsmConstraint(const char *&Name,
8963 TargetInfo::ConstraintInfo &Info) const override {
8964 // There aren't any multi-character AVR specific constraints.
8965 if (StringRef(Name).size() > 1) return false;
8968 default: return false;
8969 case 'a': // Simple upper registers
8970 case 'b': // Base pointer registers pairs
8971 case 'd': // Upper register
8972 case 'l': // Lower registers
8973 case 'e': // Pointer register pairs
8974 case 'q': // Stack pointer register
8975 case 'r': // Any register
8976 case 'w': // Special upper register pairs
8977 case 't': // Temporary register
8978 case 'x': case 'X': // Pointer register pair X
8979 case 'y': case 'Y': // Pointer register pair Y
8980 case 'z': case 'Z': // Pointer register pair Z
8981 Info.setAllowsRegister();
8983 case 'I': // 6-bit positive integer constant
8984 Info.setRequiresImmediate(0, 63);
8986 case 'J': // 6-bit negative integer constant
8987 Info.setRequiresImmediate(-63, 0);
8989 case 'K': // Integer constant (Range: 2)
8990 Info.setRequiresImmediate(2);
8992 case 'L': // Integer constant (Range: 0)
8993 Info.setRequiresImmediate(0);
8995 case 'M': // 8-bit integer constant
8996 Info.setRequiresImmediate(0, 0xff);
8998 case 'N': // Integer constant (Range: -1)
8999 Info.setRequiresImmediate(-1);
9001 case 'O': // Integer constant (Range: 8, 16, 24)
9002 Info.setRequiresImmediate({8, 16, 24});
9004 case 'P': // Integer constant (Range: 1)
9005 Info.setRequiresImmediate(1);
9007 case 'R': // Integer constant (Range: -6 to 5)
9008 Info.setRequiresImmediate(-6, 5);
9010 case 'G': // Floating point constant
9011 case 'Q': // A memory address based on Y or Z pointer with displacement.
9018 IntType getIntTypeByWidth(unsigned BitWidth,
9019 bool IsSigned) const final {
9020 // AVR prefers int for 16-bit integers.
9021 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt)
9022 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
9025 IntType getLeastIntTypeByWidth(unsigned BitWidth,
9026 bool IsSigned) const final {
9027 // AVR uses int for int_least16_t and int_fast16_t.
9028 return BitWidth == 16
9029 ? (IsSigned ? SignedInt : UnsignedInt)
9030 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
9033 bool setCPU(const std::string &Name) override {
9034 bool IsFamily = llvm::StringSwitch<bool>(Name)
9037 .Case("avr25", true)
9039 .Case("avr31", true)
9040 .Case("avr35", true)
9043 .Case("avr51", true)
9045 .Case("avrxmega1", true)
9046 .Case("avrxmega2", true)
9047 .Case("avrxmega3", true)
9048 .Case("avrxmega4", true)
9049 .Case("avrxmega5", true)
9050 .Case("avrxmega6", true)
9051 .Case("avrxmega7", true)
9052 .Case("avrtiny", true)
9055 if (IsFamily) this->CPU = Name;
9057 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(),
9058 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end();
9060 if (IsMCU) this->CPU = Name;
9062 return IsFamily || IsMCU;
9069 } // end anonymous namespace
9071 //===----------------------------------------------------------------------===//
9073 //===----------------------------------------------------------------------===//
9075 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
9076 const TargetOptions &Opts) {
9077 llvm::Triple::OSType os = Triple.getOS();
9079 switch (Triple.getArch()) {
9083 case llvm::Triple::xcore:
9084 return new XCoreTargetInfo(Triple, Opts);
9086 case llvm::Triple::hexagon:
9087 return new HexagonTargetInfo(Triple, Opts);
9089 case llvm::Triple::lanai:
9090 return new LanaiTargetInfo(Triple, Opts);
9092 case llvm::Triple::aarch64:
9093 if (Triple.isOSDarwin())
9094 return new DarwinAArch64TargetInfo(Triple, Opts);
9097 case llvm::Triple::CloudABI:
9098 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts);
9099 case llvm::Triple::FreeBSD:
9100 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9101 case llvm::Triple::Fuchsia:
9102 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9103 case llvm::Triple::Linux:
9104 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9105 case llvm::Triple::NetBSD:
9106 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9107 case llvm::Triple::OpenBSD:
9108 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9110 return new AArch64leTargetInfo(Triple, Opts);
9113 case llvm::Triple::aarch64_be:
9115 case llvm::Triple::FreeBSD:
9116 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9117 case llvm::Triple::Fuchsia:
9118 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9119 case llvm::Triple::Linux:
9120 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9121 case llvm::Triple::NetBSD:
9122 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9124 return new AArch64beTargetInfo(Triple, Opts);
9127 case llvm::Triple::arm:
9128 case llvm::Triple::thumb:
9129 if (Triple.isOSBinFormatMachO())
9130 return new DarwinARMTargetInfo(Triple, Opts);
9133 case llvm::Triple::CloudABI:
9134 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts);
9135 case llvm::Triple::Linux:
9136 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts);
9137 case llvm::Triple::FreeBSD:
9138 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
9139 case llvm::Triple::NetBSD:
9140 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
9141 case llvm::Triple::OpenBSD:
9142 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
9143 case llvm::Triple::Bitrig:
9144 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts);
9145 case llvm::Triple::RTEMS:
9146 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts);
9147 case llvm::Triple::NaCl:
9148 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts);
9149 case llvm::Triple::Win32:
9150 switch (Triple.getEnvironment()) {
9151 case llvm::Triple::Cygnus:
9152 return new CygwinARMTargetInfo(Triple, Opts);
9153 case llvm::Triple::GNU:
9154 return new MinGWARMTargetInfo(Triple, Opts);
9155 case llvm::Triple::Itanium:
9156 return new ItaniumWindowsARMleTargetInfo(Triple, Opts);
9157 case llvm::Triple::MSVC:
9158 default: // Assume MSVC for unknown environments
9159 return new MicrosoftARMleTargetInfo(Triple, Opts);
9162 return new ARMleTargetInfo(Triple, Opts);
9165 case llvm::Triple::armeb:
9166 case llvm::Triple::thumbeb:
9167 if (Triple.isOSDarwin())
9168 return new DarwinARMTargetInfo(Triple, Opts);
9171 case llvm::Triple::Linux:
9172 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9173 case llvm::Triple::FreeBSD:
9174 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9175 case llvm::Triple::NetBSD:
9176 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9177 case llvm::Triple::OpenBSD:
9178 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9179 case llvm::Triple::Bitrig:
9180 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9181 case llvm::Triple::RTEMS:
9182 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9183 case llvm::Triple::NaCl:
9184 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9186 return new ARMbeTargetInfo(Triple, Opts);
9189 case llvm::Triple::avr:
9190 return new AVRTargetInfo(Triple, Opts);
9191 case llvm::Triple::bpfeb:
9192 case llvm::Triple::bpfel:
9193 return new BPFTargetInfo(Triple, Opts);
9195 case llvm::Triple::msp430:
9196 return new MSP430TargetInfo(Triple, Opts);
9198 case llvm::Triple::mips:
9200 case llvm::Triple::Linux:
9201 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9202 case llvm::Triple::RTEMS:
9203 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9204 case llvm::Triple::FreeBSD:
9205 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9206 case llvm::Triple::NetBSD:
9207 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9209 return new MipsTargetInfo(Triple, Opts);
9212 case llvm::Triple::mipsel:
9214 case llvm::Triple::Linux:
9215 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9216 case llvm::Triple::RTEMS:
9217 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9218 case llvm::Triple::FreeBSD:
9219 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9220 case llvm::Triple::NetBSD:
9221 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9222 case llvm::Triple::NaCl:
9223 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts);
9225 return new MipsTargetInfo(Triple, Opts);
9228 case llvm::Triple::mips64:
9230 case llvm::Triple::Linux:
9231 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9232 case llvm::Triple::RTEMS:
9233 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9234 case llvm::Triple::FreeBSD:
9235 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9236 case llvm::Triple::NetBSD:
9237 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9238 case llvm::Triple::OpenBSD:
9239 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9241 return new MipsTargetInfo(Triple, Opts);
9244 case llvm::Triple::mips64el:
9246 case llvm::Triple::Linux:
9247 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9248 case llvm::Triple::RTEMS:
9249 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9250 case llvm::Triple::FreeBSD:
9251 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9252 case llvm::Triple::NetBSD:
9253 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9254 case llvm::Triple::OpenBSD:
9255 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9257 return new MipsTargetInfo(Triple, Opts);
9260 case llvm::Triple::le32:
9262 case llvm::Triple::NaCl:
9263 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts);
9268 case llvm::Triple::le64:
9269 return new Le64TargetInfo(Triple, Opts);
9271 case llvm::Triple::ppc:
9272 if (Triple.isOSDarwin())
9273 return new DarwinPPC32TargetInfo(Triple, Opts);
9275 case llvm::Triple::Linux:
9276 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts);
9277 case llvm::Triple::FreeBSD:
9278 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
9279 case llvm::Triple::NetBSD:
9280 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
9281 case llvm::Triple::OpenBSD:
9282 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
9283 case llvm::Triple::RTEMS:
9284 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts);
9286 return new PPC32TargetInfo(Triple, Opts);
9289 case llvm::Triple::ppc64:
9290 if (Triple.isOSDarwin())
9291 return new DarwinPPC64TargetInfo(Triple, Opts);
9293 case llvm::Triple::Linux:
9294 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
9295 case llvm::Triple::Lv2:
9296 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts);
9297 case llvm::Triple::FreeBSD:
9298 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
9299 case llvm::Triple::NetBSD:
9300 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
9302 return new PPC64TargetInfo(Triple, Opts);
9305 case llvm::Triple::ppc64le:
9307 case llvm::Triple::Linux:
9308 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
9309 case llvm::Triple::NetBSD:
9310 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
9312 return new PPC64TargetInfo(Triple, Opts);
9315 case llvm::Triple::nvptx:
9316 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32);
9317 case llvm::Triple::nvptx64:
9318 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64);
9320 case llvm::Triple::amdgcn:
9321 case llvm::Triple::r600:
9322 return new AMDGPUTargetInfo(Triple, Opts);
9324 case llvm::Triple::sparc:
9326 case llvm::Triple::Linux:
9327 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9328 case llvm::Triple::Solaris:
9329 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9330 case llvm::Triple::NetBSD:
9331 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9332 case llvm::Triple::OpenBSD:
9333 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9334 case llvm::Triple::RTEMS:
9335 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9337 return new SparcV8TargetInfo(Triple, Opts);
9340 // The 'sparcel' architecture copies all the above cases except for Solaris.
9341 case llvm::Triple::sparcel:
9343 case llvm::Triple::Linux:
9344 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9345 case llvm::Triple::NetBSD:
9346 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9347 case llvm::Triple::OpenBSD:
9348 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9349 case llvm::Triple::RTEMS:
9350 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9352 return new SparcV8elTargetInfo(Triple, Opts);
9355 case llvm::Triple::sparcv9:
9357 case llvm::Triple::Linux:
9358 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9359 case llvm::Triple::Solaris:
9360 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9361 case llvm::Triple::NetBSD:
9362 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9363 case llvm::Triple::OpenBSD:
9364 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9365 case llvm::Triple::FreeBSD:
9366 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9368 return new SparcV9TargetInfo(Triple, Opts);
9371 case llvm::Triple::systemz:
9373 case llvm::Triple::Linux:
9374 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts);
9376 return new SystemZTargetInfo(Triple, Opts);
9379 case llvm::Triple::tce:
9380 return new TCETargetInfo(Triple, Opts);
9382 case llvm::Triple::tcele:
9383 return new TCELETargetInfo(Triple, Opts);
9385 case llvm::Triple::x86:
9386 if (Triple.isOSDarwin())
9387 return new DarwinI386TargetInfo(Triple, Opts);
9390 case llvm::Triple::CloudABI:
9391 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts);
9392 case llvm::Triple::Linux: {
9393 switch (Triple.getEnvironment()) {
9395 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts);
9396 case llvm::Triple::Android:
9397 return new AndroidX86_32TargetInfo(Triple, Opts);
9400 case llvm::Triple::DragonFly:
9401 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
9402 case llvm::Triple::NetBSD:
9403 return new NetBSDI386TargetInfo(Triple, Opts);
9404 case llvm::Triple::OpenBSD:
9405 return new OpenBSDI386TargetInfo(Triple, Opts);
9406 case llvm::Triple::Bitrig:
9407 return new BitrigI386TargetInfo(Triple, Opts);
9408 case llvm::Triple::FreeBSD:
9409 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
9410 case llvm::Triple::KFreeBSD:
9411 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
9412 case llvm::Triple::Minix:
9413 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts);
9414 case llvm::Triple::Solaris:
9415 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts);
9416 case llvm::Triple::Win32: {
9417 switch (Triple.getEnvironment()) {
9418 case llvm::Triple::Cygnus:
9419 return new CygwinX86_32TargetInfo(Triple, Opts);
9420 case llvm::Triple::GNU:
9421 return new MinGWX86_32TargetInfo(Triple, Opts);
9422 case llvm::Triple::Itanium:
9423 case llvm::Triple::MSVC:
9424 default: // Assume MSVC for unknown environments
9425 return new MicrosoftX86_32TargetInfo(Triple, Opts);
9428 case llvm::Triple::Haiku:
9429 return new HaikuX86_32TargetInfo(Triple, Opts);
9430 case llvm::Triple::RTEMS:
9431 return new RTEMSX86_32TargetInfo(Triple, Opts);
9432 case llvm::Triple::NaCl:
9433 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts);
9434 case llvm::Triple::ELFIAMCU:
9435 return new MCUX86_32TargetInfo(Triple, Opts);
9437 return new X86_32TargetInfo(Triple, Opts);
9440 case llvm::Triple::x86_64:
9441 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
9442 return new DarwinX86_64TargetInfo(Triple, Opts);
9445 case llvm::Triple::CloudABI:
9446 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts);
9447 case llvm::Triple::Linux: {
9448 switch (Triple.getEnvironment()) {
9450 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts);
9451 case llvm::Triple::Android:
9452 return new AndroidX86_64TargetInfo(Triple, Opts);
9455 case llvm::Triple::DragonFly:
9456 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9457 case llvm::Triple::NetBSD:
9458 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9459 case llvm::Triple::OpenBSD:
9460 return new OpenBSDX86_64TargetInfo(Triple, Opts);
9461 case llvm::Triple::Bitrig:
9462 return new BitrigX86_64TargetInfo(Triple, Opts);
9463 case llvm::Triple::FreeBSD:
9464 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9465 case llvm::Triple::Fuchsia:
9466 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts);
9467 case llvm::Triple::KFreeBSD:
9468 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9469 case llvm::Triple::Solaris:
9470 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts);
9471 case llvm::Triple::Win32: {
9472 switch (Triple.getEnvironment()) {
9473 case llvm::Triple::Cygnus:
9474 return new CygwinX86_64TargetInfo(Triple, Opts);
9475 case llvm::Triple::GNU:
9476 return new MinGWX86_64TargetInfo(Triple, Opts);
9477 case llvm::Triple::MSVC:
9478 default: // Assume MSVC for unknown environments
9479 return new MicrosoftX86_64TargetInfo(Triple, Opts);
9482 case llvm::Triple::Haiku:
9483 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts);
9484 case llvm::Triple::NaCl:
9485 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts);
9486 case llvm::Triple::PS4:
9487 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts);
9489 return new X86_64TargetInfo(Triple, Opts);
9492 case llvm::Triple::spir: {
9493 if (Triple.getOS() != llvm::Triple::UnknownOS ||
9494 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
9496 return new SPIR32TargetInfo(Triple, Opts);
9498 case llvm::Triple::spir64: {
9499 if (Triple.getOS() != llvm::Triple::UnknownOS ||
9500 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
9502 return new SPIR64TargetInfo(Triple, Opts);
9504 case llvm::Triple::wasm32:
9505 if (Triple.getSubArch() != llvm::Triple::NoSubArch ||
9506 Triple.getVendor() != llvm::Triple::UnknownVendor ||
9507 Triple.getOS() != llvm::Triple::UnknownOS ||
9508 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment ||
9509 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm()))
9511 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts);
9512 case llvm::Triple::wasm64:
9513 if (Triple.getSubArch() != llvm::Triple::NoSubArch ||
9514 Triple.getVendor() != llvm::Triple::UnknownVendor ||
9515 Triple.getOS() != llvm::Triple::UnknownOS ||
9516 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment ||
9517 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm()))
9519 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts);
9521 case llvm::Triple::renderscript32:
9522 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts);
9523 case llvm::Triple::renderscript64:
9524 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts);
9528 /// CreateTargetInfo - Return the target info object for the specified target
9531 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
9532 const std::shared_ptr<TargetOptions> &Opts) {
9533 llvm::Triple Triple(Opts->Triple);
9535 // Construct the target
9536 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts));
9538 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
9541 Target->TargetOpts = Opts;
9543 // Set the target CPU if specified.
9544 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
9545 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
9549 // Set the target ABI if specified.
9550 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
9551 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
9555 // Set the fp math unit.
9556 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
9557 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
9561 // Compute the default target features, we need the target to handle this
9562 // because features may have dependencies on one another.
9563 llvm::StringMap<bool> Features;
9564 if (!Target->initFeatureMap(Features, Diags, Opts->CPU,
9565 Opts->FeaturesAsWritten))
9568 // Add the features to the compile options.
9569 Opts->Features.clear();
9570 for (const auto &F : Features)
9571 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str());
9573 if (!Target->handleTargetFeatures(Opts->Features, Diags))
9576 Target->setSupportedOpenCLOpts();
9577 Target->setOpenCLExtensionOpts();
9579 if (!Target->validateTarget(Diags))
9582 return Target.release();