1 //===--- Targets.cpp - Implement target feature support -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "clang/Basic/Version.h"
23 #include "llvm/ADT/APFloat.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/ADT/Triple.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/TargetParser.h"
35 using namespace clang;
37 //===----------------------------------------------------------------------===//
38 // Common code shared among targets.
39 //===----------------------------------------------------------------------===//
41 /// DefineStd - Define a macro name and standard variants. For example if
42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
45 const LangOptions &Opts) {
46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
49 // in the user's namespace.
51 Builder.defineMacro(MacroName);
54 Builder.defineMacro("__" + MacroName);
57 Builder.defineMacro("__" + MacroName + "__");
60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
62 Builder.defineMacro("__" + CPUName);
63 Builder.defineMacro("__" + CPUName + "__");
65 Builder.defineMacro("__tune_" + CPUName + "__");
68 //===----------------------------------------------------------------------===//
69 // Defines specific to certain operating systems.
70 //===----------------------------------------------------------------------===//
73 template<typename TgtInfo>
74 class OSTargetInfo : public TgtInfo {
76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
77 MacroBuilder &Builder) const=0;
79 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
80 void getTargetDefines(const LangOptions &Opts,
81 MacroBuilder &Builder) const override {
82 TgtInfo::getTargetDefines(Opts, Builder);
83 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
89 template <typename Target>
90 class CloudABITargetInfo : public OSTargetInfo<Target> {
92 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
93 MacroBuilder &Builder) const override {
94 Builder.defineMacro("__CloudABI__");
95 Builder.defineMacro("__ELF__");
97 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
98 Builder.defineMacro("__STDC_ISO_10646__", "201206L");
99 Builder.defineMacro("__STDC_UTF_16__");
100 Builder.defineMacro("__STDC_UTF_32__");
104 CloudABITargetInfo(const llvm::Triple &Triple)
105 : OSTargetInfo<Target>(Triple) {
106 this->UserLabelPrefix = "";
110 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
111 const llvm::Triple &Triple,
112 StringRef &PlatformName,
113 VersionTuple &PlatformMinVersion) {
114 Builder.defineMacro("__APPLE_CC__", "6000");
115 Builder.defineMacro("__APPLE__");
116 Builder.defineMacro("OBJC_NEW_PROPERTIES");
117 // AddressSanitizer doesn't play well with source fortification, which is on
118 // by default on Darwin.
119 if (Opts.Sanitize.has(SanitizerKind::Address))
120 Builder.defineMacro("_FORTIFY_SOURCE", "0");
122 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode.
124 // __weak is always defined, for use in blocks and with objc pointers.
125 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
126 Builder.defineMacro("__strong", "");
127 Builder.defineMacro("__unsafe_unretained", "");
131 Builder.defineMacro("__STATIC__");
133 Builder.defineMacro("__DYNAMIC__");
135 if (Opts.POSIXThreads)
136 Builder.defineMacro("_REENTRANT");
138 // Get the platform type and version number from the triple.
139 unsigned Maj, Min, Rev;
140 if (Triple.isMacOSX()) {
141 Triple.getMacOSXVersion(Maj, Min, Rev);
142 PlatformName = "macosx";
144 Triple.getOSVersion(Maj, Min, Rev);
145 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
148 // If -target arch-pc-win32-macho option specified, we're
149 // generating code for Win32 ABI. No need to emit
150 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
151 if (PlatformName == "win32") {
152 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
156 // Set the appropriate OS version define.
157 if (Triple.isiOS()) {
158 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
161 Str[1] = '0' + (Min / 10);
162 Str[2] = '0' + (Min % 10);
163 Str[3] = '0' + (Rev / 10);
164 Str[4] = '0' + (Rev % 10);
167 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str);
169 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
172 } else if (Triple.isWatchOS()) {
173 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
176 Str[1] = '0' + (Min / 10);
177 Str[2] = '0' + (Min % 10);
178 Str[3] = '0' + (Rev / 10);
179 Str[4] = '0' + (Rev % 10);
181 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str);
182 } else if (Triple.isMacOSX()) {
183 // Note that the Driver allows versions which aren't representable in the
184 // define (because we only get a single digit for the minor and micro
185 // revision numbers). So, we limit them to the maximum representable
187 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
189 if (Maj < 10 || (Maj == 10 && Min < 10)) {
190 Str[0] = '0' + (Maj / 10);
191 Str[1] = '0' + (Maj % 10);
192 Str[2] = '0' + std::min(Min, 9U);
193 Str[3] = '0' + std::min(Rev, 9U);
196 // Handle versions > 10.9.
197 Str[0] = '0' + (Maj / 10);
198 Str[1] = '0' + (Maj % 10);
199 Str[2] = '0' + (Min / 10);
200 Str[3] = '0' + (Min % 10);
201 Str[4] = '0' + (Rev / 10);
202 Str[5] = '0' + (Rev % 10);
205 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
208 // Tell users about the kernel if there is one.
209 if (Triple.isOSDarwin())
210 Builder.defineMacro("__MACH__");
212 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
215 template<typename Target>
216 class DarwinTargetInfo : public OSTargetInfo<Target> {
218 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
219 MacroBuilder &Builder) const override {
220 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
221 this->PlatformMinVersion);
225 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
226 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
227 this->MCountName = "\01mcount";
230 std::string isValidSectionSpecifier(StringRef SR) const override {
231 // Let MCSectionMachO validate this.
232 StringRef Segment, Section;
233 unsigned TAA, StubSize;
235 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
236 TAA, HasTAA, StubSize);
239 const char *getStaticInitSectionSpecifier() const override {
240 // FIXME: We should return 0 when building kexts.
241 return "__TEXT,__StaticInit,regular,pure_instructions";
244 /// Darwin does not support protected visibility. Darwin's "default"
245 /// is very similar to ELF's "protected"; Darwin requires a "weak"
246 /// attribute on declarations that can be dynamically replaced.
247 bool hasProtectedVisibility() const override {
253 // DragonFlyBSD Target
254 template<typename Target>
255 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
257 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
258 MacroBuilder &Builder) const override {
259 // DragonFly defines; list based off of gcc output
260 Builder.defineMacro("__DragonFly__");
261 Builder.defineMacro("__DragonFly_cc_version", "100001");
262 Builder.defineMacro("__ELF__");
263 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
264 Builder.defineMacro("__tune_i386__");
265 DefineStd(Builder, "unix", Opts);
268 DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
269 : OSTargetInfo<Target>(Triple) {
270 this->UserLabelPrefix = "";
272 switch (Triple.getArch()) {
274 case llvm::Triple::x86:
275 case llvm::Triple::x86_64:
276 this->MCountName = ".mcount";
283 template<typename Target>
284 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
286 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
287 MacroBuilder &Builder) const override {
288 // FreeBSD defines; list based off of gcc output
290 unsigned Release = Triple.getOSMajorVersion();
294 Builder.defineMacro("__FreeBSD__", Twine(Release));
295 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
296 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
297 DefineStd(Builder, "unix", Opts);
298 Builder.defineMacro("__ELF__");
300 // On FreeBSD, wchar_t contains the number of the code point as
301 // used by the character set of the locale. These character sets are
302 // not necessarily a superset of ASCII.
304 // FIXME: This is wrong; the macro refers to the numerical values
305 // of wchar_t *literals*, which are not locale-dependent. However,
306 // FreeBSD systems apparently depend on us getting this wrong, and
307 // setting this to 1 is conforming even if all the basic source
308 // character literals have the same encoding as char and wchar_t.
309 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
312 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
313 this->UserLabelPrefix = "";
315 switch (Triple.getArch()) {
317 case llvm::Triple::x86:
318 case llvm::Triple::x86_64:
319 this->MCountName = ".mcount";
321 case llvm::Triple::mips:
322 case llvm::Triple::mipsel:
323 case llvm::Triple::ppc:
324 case llvm::Triple::ppc64:
325 case llvm::Triple::ppc64le:
326 this->MCountName = "_mcount";
328 case llvm::Triple::arm:
329 this->MCountName = "__mcount";
335 // GNU/kFreeBSD Target
336 template<typename Target>
337 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
339 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
340 MacroBuilder &Builder) const override {
341 // GNU/kFreeBSD defines; list based off of gcc output
343 DefineStd(Builder, "unix", Opts);
344 Builder.defineMacro("__FreeBSD_kernel__");
345 Builder.defineMacro("__GLIBC__");
346 Builder.defineMacro("__ELF__");
347 if (Opts.POSIXThreads)
348 Builder.defineMacro("_REENTRANT");
350 Builder.defineMacro("_GNU_SOURCE");
353 KFreeBSDTargetInfo(const llvm::Triple &Triple)
354 : OSTargetInfo<Target>(Triple) {
355 this->UserLabelPrefix = "";
360 template<typename Target>
361 class MinixTargetInfo : public OSTargetInfo<Target> {
363 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
364 MacroBuilder &Builder) const override {
367 Builder.defineMacro("__minix", "3");
368 Builder.defineMacro("_EM_WSIZE", "4");
369 Builder.defineMacro("_EM_PSIZE", "4");
370 Builder.defineMacro("_EM_SSIZE", "2");
371 Builder.defineMacro("_EM_LSIZE", "4");
372 Builder.defineMacro("_EM_FSIZE", "4");
373 Builder.defineMacro("_EM_DSIZE", "8");
374 Builder.defineMacro("__ELF__");
375 DefineStd(Builder, "unix", Opts);
378 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
379 this->UserLabelPrefix = "";
384 template<typename Target>
385 class LinuxTargetInfo : public OSTargetInfo<Target> {
387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
388 MacroBuilder &Builder) const override {
389 // Linux defines; list based off of gcc output
390 DefineStd(Builder, "unix", Opts);
391 DefineStd(Builder, "linux", Opts);
392 Builder.defineMacro("__gnu_linux__");
393 Builder.defineMacro("__ELF__");
394 if (Triple.isAndroid()) {
395 Builder.defineMacro("__ANDROID__", "1");
396 unsigned Maj, Min, Rev;
397 Triple.getEnvironmentVersion(Maj, Min, Rev);
398 this->PlatformName = "android";
399 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
401 if (Opts.POSIXThreads)
402 Builder.defineMacro("_REENTRANT");
404 Builder.defineMacro("_GNU_SOURCE");
407 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
408 this->UserLabelPrefix = "";
409 this->WIntType = TargetInfo::UnsignedInt;
411 switch (Triple.getArch()) {
414 case llvm::Triple::ppc:
415 case llvm::Triple::ppc64:
416 case llvm::Triple::ppc64le:
417 this->MCountName = "_mcount";
422 const char *getStaticInitSectionSpecifier() const override {
423 return ".text.startup";
428 template<typename Target>
429 class NetBSDTargetInfo : public OSTargetInfo<Target> {
431 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
432 MacroBuilder &Builder) const override {
433 // NetBSD defines; list based off of gcc output
434 Builder.defineMacro("__NetBSD__");
435 Builder.defineMacro("__unix__");
436 Builder.defineMacro("__ELF__");
437 if (Opts.POSIXThreads)
438 Builder.defineMacro("_POSIX_THREADS");
440 switch (Triple.getArch()) {
443 case llvm::Triple::arm:
444 case llvm::Triple::armeb:
445 case llvm::Triple::thumb:
446 case llvm::Triple::thumbeb:
447 Builder.defineMacro("__ARM_DWARF_EH__");
452 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
453 this->UserLabelPrefix = "";
454 this->MCountName = "_mcount";
459 template<typename Target>
460 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
462 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
463 MacroBuilder &Builder) const override {
464 // OpenBSD defines; list based off of gcc output
466 Builder.defineMacro("__OpenBSD__");
467 DefineStd(Builder, "unix", Opts);
468 Builder.defineMacro("__ELF__");
469 if (Opts.POSIXThreads)
470 Builder.defineMacro("_REENTRANT");
473 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
474 this->UserLabelPrefix = "";
475 this->TLSSupported = false;
477 switch (Triple.getArch()) {
479 case llvm::Triple::x86:
480 case llvm::Triple::x86_64:
481 case llvm::Triple::arm:
482 case llvm::Triple::sparc:
483 this->MCountName = "__mcount";
485 case llvm::Triple::mips64:
486 case llvm::Triple::mips64el:
487 case llvm::Triple::ppc:
488 case llvm::Triple::sparcv9:
489 this->MCountName = "_mcount";
496 template<typename Target>
497 class BitrigTargetInfo : public OSTargetInfo<Target> {
499 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
500 MacroBuilder &Builder) const override {
501 // Bitrig defines; list based off of gcc output
503 Builder.defineMacro("__Bitrig__");
504 DefineStd(Builder, "unix", Opts);
505 Builder.defineMacro("__ELF__");
506 if (Opts.POSIXThreads)
507 Builder.defineMacro("_REENTRANT");
509 switch (Triple.getArch()) {
512 case llvm::Triple::arm:
513 case llvm::Triple::armeb:
514 case llvm::Triple::thumb:
515 case llvm::Triple::thumbeb:
516 Builder.defineMacro("__ARM_DWARF_EH__");
521 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
522 this->UserLabelPrefix = "";
523 this->MCountName = "__mcount";
528 template<typename Target>
529 class PSPTargetInfo : public OSTargetInfo<Target> {
531 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
532 MacroBuilder &Builder) const override {
533 // PSP defines; list based on the output of the pspdev gcc toolchain.
534 Builder.defineMacro("PSP");
535 Builder.defineMacro("_PSP");
536 Builder.defineMacro("__psp__");
537 Builder.defineMacro("__ELF__");
540 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
541 this->UserLabelPrefix = "";
546 template<typename Target>
547 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
549 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
550 MacroBuilder &Builder) const override {
552 Builder.defineMacro("__PPC__");
553 Builder.defineMacro("__PPU__");
554 Builder.defineMacro("__CELLOS_LV2__");
555 Builder.defineMacro("__ELF__");
556 Builder.defineMacro("__LP32__");
557 Builder.defineMacro("_ARCH_PPC64");
558 Builder.defineMacro("__powerpc64__");
561 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
562 this->UserLabelPrefix = "";
563 this->LongWidth = this->LongAlign = 32;
564 this->PointerWidth = this->PointerAlign = 32;
565 this->IntMaxType = TargetInfo::SignedLongLong;
566 this->Int64Type = TargetInfo::SignedLongLong;
567 this->SizeType = TargetInfo::UnsignedInt;
568 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64";
572 template <typename Target>
573 class PS4OSTargetInfo : public OSTargetInfo<Target> {
575 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
576 MacroBuilder &Builder) const override {
577 Builder.defineMacro("__FreeBSD__", "9");
578 Builder.defineMacro("__FreeBSD_cc_version", "900001");
579 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
580 DefineStd(Builder, "unix", Opts);
581 Builder.defineMacro("__ELF__");
582 Builder.defineMacro("__PS4__");
585 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
586 this->WCharType = this->UnsignedShort;
588 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits).
589 this->MaxTLSAlign = 256;
590 this->UserLabelPrefix = "";
592 switch (Triple.getArch()) {
594 case llvm::Triple::x86_64:
595 this->MCountName = ".mcount";
602 template<typename Target>
603 class SolarisTargetInfo : public OSTargetInfo<Target> {
605 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
606 MacroBuilder &Builder) const override {
607 DefineStd(Builder, "sun", Opts);
608 DefineStd(Builder, "unix", Opts);
609 Builder.defineMacro("__ELF__");
610 Builder.defineMacro("__svr4__");
611 Builder.defineMacro("__SVR4");
612 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
613 // newer, but to 500 for everything else. feature_test.h has a check to
614 // ensure that you are not using C99 with an old version of X/Open or C89
615 // with a new version.
617 Builder.defineMacro("_XOPEN_SOURCE", "600");
619 Builder.defineMacro("_XOPEN_SOURCE", "500");
621 Builder.defineMacro("__C99FEATURES__");
622 Builder.defineMacro("_LARGEFILE_SOURCE");
623 Builder.defineMacro("_LARGEFILE64_SOURCE");
624 Builder.defineMacro("__EXTENSIONS__");
625 Builder.defineMacro("_REENTRANT");
628 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
629 this->UserLabelPrefix = "";
630 this->WCharType = this->SignedInt;
631 // FIXME: WIntType should be SignedLong
636 template<typename Target>
637 class WindowsTargetInfo : public OSTargetInfo<Target> {
639 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
640 MacroBuilder &Builder) const override {
641 Builder.defineMacro("_WIN32");
643 void getVisualStudioDefines(const LangOptions &Opts,
644 MacroBuilder &Builder) const {
645 if (Opts.CPlusPlus) {
647 Builder.defineMacro("_CPPRTTI");
649 if (Opts.CXXExceptions)
650 Builder.defineMacro("_CPPUNWIND");
654 Builder.defineMacro("__BOOL_DEFINED");
656 if (!Opts.CharIsSigned)
657 Builder.defineMacro("_CHAR_UNSIGNED");
659 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
660 // but it works for now.
661 if (Opts.POSIXThreads)
662 Builder.defineMacro("_MT");
664 if (Opts.MSCompatibilityVersion) {
665 Builder.defineMacro("_MSC_VER",
666 Twine(Opts.MSCompatibilityVersion / 100000));
667 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
668 // FIXME We cannot encode the revision information into 32-bits
669 Builder.defineMacro("_MSC_BUILD", Twine(1));
671 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
672 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
675 if (Opts.MicrosoftExt) {
676 Builder.defineMacro("_MSC_EXTENSIONS");
678 if (Opts.CPlusPlus11) {
679 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
680 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
681 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
685 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
689 WindowsTargetInfo(const llvm::Triple &Triple)
690 : OSTargetInfo<Target>(Triple) {}
693 template <typename Target>
694 class NaClTargetInfo : public OSTargetInfo<Target> {
696 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
697 MacroBuilder &Builder) const override {
698 if (Opts.POSIXThreads)
699 Builder.defineMacro("_REENTRANT");
701 Builder.defineMacro("_GNU_SOURCE");
703 DefineStd(Builder, "unix", Opts);
704 Builder.defineMacro("__ELF__");
705 Builder.defineMacro("__native_client__");
709 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
710 this->UserLabelPrefix = "";
711 this->LongAlign = 32;
712 this->LongWidth = 32;
713 this->PointerAlign = 32;
714 this->PointerWidth = 32;
715 this->IntMaxType = TargetInfo::SignedLongLong;
716 this->Int64Type = TargetInfo::SignedLongLong;
717 this->DoubleAlign = 64;
718 this->LongDoubleWidth = 64;
719 this->LongDoubleAlign = 64;
720 this->LongLongWidth = 64;
721 this->LongLongAlign = 64;
722 this->SizeType = TargetInfo::UnsignedInt;
723 this->PtrDiffType = TargetInfo::SignedInt;
724 this->IntPtrType = TargetInfo::SignedInt;
725 // RegParmMax is inherited from the underlying architecture
726 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
727 if (Triple.getArch() == llvm::Triple::arm) {
728 // Handled in ARM's setABI().
729 } else if (Triple.getArch() == llvm::Triple::x86) {
730 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
731 } else if (Triple.getArch() == llvm::Triple::x86_64) {
732 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
733 } else if (Triple.getArch() == llvm::Triple::mipsel) {
734 // Handled on mips' setDataLayoutString.
736 assert(Triple.getArch() == llvm::Triple::le32);
737 this->DataLayoutString = "e-p:32:32-i64:64";
742 // WebAssembly target
743 template <typename Target>
744 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> {
745 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
746 MacroBuilder &Builder) const final {
747 // A common platform macro.
748 if (Opts.POSIXThreads)
749 Builder.defineMacro("_REENTRANT");
750 // Follow g++ convention and predefine _GNU_SOURCE for C++.
752 Builder.defineMacro("_GNU_SOURCE");
755 // As an optimization, group static init code together in a section.
756 const char *getStaticInitSectionSpecifier() const final {
757 return ".text.__startup";
761 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple)
762 : OSTargetInfo<Target>(Triple) {
763 this->MCountName = "__mcount";
764 this->UserLabelPrefix = "";
765 this->TheCXXABI.set(TargetCXXABI::WebAssembly);
769 //===----------------------------------------------------------------------===//
770 // Specific target implementations.
771 //===----------------------------------------------------------------------===//
773 // PPC abstract base class
774 class PPCTargetInfo : public TargetInfo {
775 static const Builtin::Info BuiltinInfo[];
776 static const char * const GCCRegNames[];
777 static const TargetInfo::GCCRegAlias GCCRegAliases[];
780 // Target cpu features.
794 PPCTargetInfo(const llvm::Triple &Triple)
795 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
796 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
797 HasBPERMD(false), HasExtDiv(false) {
798 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
799 SimdDefaultAlign = 128;
800 LongDoubleWidth = LongDoubleAlign = 128;
801 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
804 /// \brief Flags for architecture specific defines.
807 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
808 ArchDefinePpcgr = 1 << 1,
809 ArchDefinePpcsq = 1 << 2,
810 ArchDefine440 = 1 << 3,
811 ArchDefine603 = 1 << 4,
812 ArchDefine604 = 1 << 5,
813 ArchDefinePwr4 = 1 << 6,
814 ArchDefinePwr5 = 1 << 7,
815 ArchDefinePwr5x = 1 << 8,
816 ArchDefinePwr6 = 1 << 9,
817 ArchDefinePwr6x = 1 << 10,
818 ArchDefinePwr7 = 1 << 11,
819 ArchDefinePwr8 = 1 << 12,
820 ArchDefineA2 = 1 << 13,
821 ArchDefineA2q = 1 << 14
824 // Note: GCC recognizes the following additional cpus:
825 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
826 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
828 bool setCPU(const std::string &Name) override {
829 bool CPUKnown = llvm::StringSwitch<bool>(Name)
830 .Case("generic", true)
852 .Case("e500mc", true)
854 .Case("power3", true)
856 .Case("power4", true)
858 .Case("power5", true)
860 .Case("power5x", true)
862 .Case("power6", true)
864 .Case("power6x", true)
866 .Case("power7", true)
868 .Case("power8", true)
870 .Case("powerpc", true)
872 .Case("powerpc64", true)
874 .Case("powerpc64le", true)
875 .Case("ppc64le", true)
885 StringRef getABI() const override { return ABI; }
887 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
888 return llvm::makeArrayRef(BuiltinInfo,
889 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin);
892 bool isCLZForZeroUndef() const override { return false; }
894 void getTargetDefines(const LangOptions &Opts,
895 MacroBuilder &Builder) const override;
898 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
900 const std::vector<std::string> &FeaturesVec) const override;
902 bool handleTargetFeatures(std::vector<std::string> &Features,
903 DiagnosticsEngine &Diags) override;
904 bool hasFeature(StringRef Feature) const override;
905 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
906 bool Enabled) const override;
908 ArrayRef<const char *> getGCCRegNames() const override;
909 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
910 bool validateAsmConstraint(const char *&Name,
911 TargetInfo::ConstraintInfo &Info) const override {
913 default: return false;
916 case 'b': // Base register
917 case 'f': // Floating point register
918 Info.setAllowsRegister();
920 // FIXME: The following are added to allow parsing.
921 // I just took a guess at what the actions should be.
922 // Also, is more specific checking needed? I.e. specific registers?
923 case 'd': // Floating point register (containing 64-bit value)
924 case 'v': // Altivec vector register
925 Info.setAllowsRegister();
929 case 'd':// VSX vector register to hold vector double data
930 case 'f':// VSX vector register to hold vector float data
931 case 's':// VSX vector register to hold scalar float data
932 case 'a':// Any VSX register
933 case 'c':// An individual CR bit
938 Info.setAllowsRegister();
939 Name++; // Skip over 'w'.
941 case 'h': // `MQ', `CTR', or `LINK' register
942 case 'q': // `MQ' register
943 case 'c': // `CTR' register
944 case 'l': // `LINK' register
945 case 'x': // `CR' register (condition register) number 0
946 case 'y': // `CR' register (condition register)
947 case 'z': // `XER[CA]' carry bit (part of the XER register)
948 Info.setAllowsRegister();
950 case 'I': // Signed 16-bit constant
951 case 'J': // Unsigned 16-bit constant shifted left 16 bits
952 // (use `L' instead for SImode constants)
953 case 'K': // Unsigned 16-bit constant
954 case 'L': // Signed 16-bit constant shifted left 16 bits
955 case 'M': // Constant larger than 31
956 case 'N': // Exact power of 2
957 case 'P': // Constant whose negation is a signed 16-bit constant
958 case 'G': // Floating point constant that can be loaded into a
959 // register with one instruction per word
960 case 'H': // Integer/Floating point constant that can be loaded
961 // into a register using three instructions
963 case 'm': // Memory operand. Note that on PowerPC targets, m can
964 // include addresses that update the base register. It
965 // is therefore only safe to use `m' in an asm statement
966 // if that asm statement accesses the operand exactly once.
967 // The asm statement must also use `%U<opno>' as a
968 // placeholder for the "update" flag in the corresponding
969 // load or store instruction. For example:
970 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
972 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
973 // is not. Use es rather than m if you don't want the base
974 // register to be updated.
978 // es: A "stable" memory operand; that is, one which does not
979 // include any automodification of the base register. Unlike
980 // `m', this constraint can be used in asm statements that
981 // might access the operand several times, or that might not
983 Info.setAllowsMemory();
984 Name++; // Skip over 'e'.
986 case 'Q': // Memory operand that is an offset from a register (it is
987 // usually better to use `m' or `es' in asm statements)
988 case 'Z': // Memory operand that is an indexed or indirect from a
989 // register (it is usually better to use `m' or `es' in
991 Info.setAllowsMemory();
992 Info.setAllowsRegister();
994 case 'R': // AIX TOC entry
995 case 'a': // Address operand that is an indexed or indirect from a
996 // register (`p' is preferable for asm statements)
997 case 'S': // Constant suitable as a 64-bit mask operand
998 case 'T': // Constant suitable as a 32-bit mask operand
999 case 'U': // System V Release 4 small data area reference
1000 case 't': // AND masks that can be performed by two rldic{l, r}
1002 case 'W': // Vector constant that does not require memory
1003 case 'j': // Vector constant that is all zeros.
1009 std::string convertConstraint(const char *&Constraint) const override {
1011 switch (*Constraint) {
1014 // Two-character constraint; add "^" hint for later parsing.
1015 R = std::string("^") + std::string(Constraint, 2);
1019 return TargetInfo::convertConstraint(Constraint);
1023 const char *getClobbers() const override {
1026 int getEHDataRegisterNumber(unsigned RegNo) const override {
1027 if (RegNo == 0) return 3;
1028 if (RegNo == 1) return 4;
1032 bool hasSjLjLowering() const override {
1036 bool useFloat128ManglingForLongDouble() const override {
1037 return LongDoubleWidth == 128 &&
1038 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble &&
1039 getTriple().isOSBinFormatELF();
1043 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
1044 #define BUILTIN(ID, TYPE, ATTRS) \
1045 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1046 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1047 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1048 #include "clang/Basic/BuiltinsPPC.def"
1051 /// handleTargetFeatures - Perform initialization based on the user
1052 /// configured set of features.
1053 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1054 DiagnosticsEngine &Diags) {
1055 for (const auto &Feature : Features) {
1056 if (Feature == "+vsx") {
1058 } else if (Feature == "+bpermd") {
1060 } else if (Feature == "+extdiv") {
1062 } else if (Feature == "+power8-vector") {
1064 } else if (Feature == "+crypto") {
1066 } else if (Feature == "+direct-move") {
1067 HasDirectMove = true;
1068 } else if (Feature == "+qpx") {
1070 } else if (Feature == "+htm") {
1073 // TODO: Finish this list and add an assert that we've handled them
1080 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1081 /// #defines that are not tied to a specific subtarget.
1082 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1083 MacroBuilder &Builder) const {
1084 // Target identification.
1085 Builder.defineMacro("__ppc__");
1086 Builder.defineMacro("__PPC__");
1087 Builder.defineMacro("_ARCH_PPC");
1088 Builder.defineMacro("__powerpc__");
1089 Builder.defineMacro("__POWERPC__");
1090 if (PointerWidth == 64) {
1091 Builder.defineMacro("_ARCH_PPC64");
1092 Builder.defineMacro("__powerpc64__");
1093 Builder.defineMacro("__ppc64__");
1094 Builder.defineMacro("__PPC64__");
1097 // Target properties.
1098 if (getTriple().getArch() == llvm::Triple::ppc64le) {
1099 Builder.defineMacro("_LITTLE_ENDIAN");
1101 if (getTriple().getOS() != llvm::Triple::NetBSD &&
1102 getTriple().getOS() != llvm::Triple::OpenBSD)
1103 Builder.defineMacro("_BIG_ENDIAN");
1107 if (ABI == "elfv1" || ABI == "elfv1-qpx")
1108 Builder.defineMacro("_CALL_ELF", "1");
1110 Builder.defineMacro("_CALL_ELF", "2");
1112 // Subtarget options.
1113 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1114 Builder.defineMacro("__REGISTER_PREFIX__", "");
1116 // FIXME: Should be controlled by command line option.
1117 if (LongDoubleWidth == 128)
1118 Builder.defineMacro("__LONG_DOUBLE_128__");
1121 Builder.defineMacro("__VEC__", "10206");
1122 Builder.defineMacro("__ALTIVEC__");
1125 // CPU identification.
1126 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1127 .Case("440", ArchDefineName)
1128 .Case("450", ArchDefineName | ArchDefine440)
1129 .Case("601", ArchDefineName)
1130 .Case("602", ArchDefineName | ArchDefinePpcgr)
1131 .Case("603", ArchDefineName | ArchDefinePpcgr)
1132 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1133 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1134 .Case("604", ArchDefineName | ArchDefinePpcgr)
1135 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1136 .Case("620", ArchDefineName | ArchDefinePpcgr)
1137 .Case("630", ArchDefineName | ArchDefinePpcgr)
1138 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1139 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1140 .Case("750", ArchDefineName | ArchDefinePpcgr)
1141 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1143 .Case("a2", ArchDefineA2)
1144 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1145 .Case("pwr3", ArchDefinePpcgr)
1146 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1147 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1149 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1150 | ArchDefinePpcgr | ArchDefinePpcsq)
1151 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1152 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1153 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1154 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1156 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1157 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1158 | ArchDefinePpcgr | ArchDefinePpcsq)
1159 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1160 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1161 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1162 .Case("power3", ArchDefinePpcgr)
1163 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1164 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1166 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1167 | ArchDefinePpcgr | ArchDefinePpcsq)
1168 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1169 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1170 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1171 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1173 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1174 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1175 | ArchDefinePpcgr | ArchDefinePpcsq)
1176 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1177 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1178 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1179 .Default(ArchDefineNone);
1181 if (defs & ArchDefineName)
1182 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1183 if (defs & ArchDefinePpcgr)
1184 Builder.defineMacro("_ARCH_PPCGR");
1185 if (defs & ArchDefinePpcsq)
1186 Builder.defineMacro("_ARCH_PPCSQ");
1187 if (defs & ArchDefine440)
1188 Builder.defineMacro("_ARCH_440");
1189 if (defs & ArchDefine603)
1190 Builder.defineMacro("_ARCH_603");
1191 if (defs & ArchDefine604)
1192 Builder.defineMacro("_ARCH_604");
1193 if (defs & ArchDefinePwr4)
1194 Builder.defineMacro("_ARCH_PWR4");
1195 if (defs & ArchDefinePwr5)
1196 Builder.defineMacro("_ARCH_PWR5");
1197 if (defs & ArchDefinePwr5x)
1198 Builder.defineMacro("_ARCH_PWR5X");
1199 if (defs & ArchDefinePwr6)
1200 Builder.defineMacro("_ARCH_PWR6");
1201 if (defs & ArchDefinePwr6x)
1202 Builder.defineMacro("_ARCH_PWR6X");
1203 if (defs & ArchDefinePwr7)
1204 Builder.defineMacro("_ARCH_PWR7");
1205 if (defs & ArchDefinePwr8)
1206 Builder.defineMacro("_ARCH_PWR8");
1207 if (defs & ArchDefineA2)
1208 Builder.defineMacro("_ARCH_A2");
1209 if (defs & ArchDefineA2q) {
1210 Builder.defineMacro("_ARCH_A2Q");
1211 Builder.defineMacro("_ARCH_QP");
1214 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1215 Builder.defineMacro("__bg__");
1216 Builder.defineMacro("__THW_BLUEGENE__");
1217 Builder.defineMacro("__bgq__");
1218 Builder.defineMacro("__TOS_BGQ__");
1222 Builder.defineMacro("__VSX__");
1224 Builder.defineMacro("__POWER8_VECTOR__");
1226 Builder.defineMacro("__CRYPTO__");
1228 Builder.defineMacro("__HTM__");
1230 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1231 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1232 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1233 if (PointerWidth == 64)
1234 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1236 // FIXME: The following are not yet generated here by Clang, but are
1237 // generated by GCC:
1240 // __RECIP_PRECISION__
1241 // __APPLE_ALTIVEC__
1250 // __CMODEL_MEDIUM__
1257 // Handle explicit options being passed to the compiler here: if we've
1258 // explicitly turned off vsx and turned on power8-vector or direct-move then
1259 // go ahead and error since the customer has expressed a somewhat incompatible
1261 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
1262 const std::vector<std::string> &FeaturesVec) {
1264 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") !=
1265 FeaturesVec.end()) {
1266 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") !=
1267 FeaturesVec.end()) {
1268 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
1273 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") !=
1274 FeaturesVec.end()) {
1275 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
1284 bool PPCTargetInfo::initFeatureMap(
1285 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
1286 const std::vector<std::string> &FeaturesVec) const {
1287 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1297 .Case("ppc64", true)
1298 .Case("ppc64le", true)
1301 Features["qpx"] = (CPU == "a2q");
1302 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1303 .Case("ppc64le", true)
1306 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1307 .Case("ppc64le", true)
1310 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1311 .Case("ppc64le", true)
1315 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1316 .Case("ppc64le", true)
1320 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1321 .Case("ppc64le", true)
1324 Features["vsx"] = llvm::StringSwitch<bool>(CPU)
1325 .Case("ppc64le", true)
1330 if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
1333 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1336 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1337 return llvm::StringSwitch<bool>(Feature)
1338 .Case("powerpc", true)
1339 .Case("vsx", HasVSX)
1340 .Case("power8-vector", HasP8Vector)
1341 .Case("crypto", HasP8Crypto)
1342 .Case("direct-move", HasDirectMove)
1343 .Case("qpx", HasQPX)
1344 .Case("htm", HasHTM)
1345 .Case("bpermd", HasBPERMD)
1346 .Case("extdiv", HasExtDiv)
1350 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1351 StringRef Name, bool Enabled) const {
1352 // If we're enabling direct-move or power8-vector go ahead and enable vsx
1353 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user
1354 // incompatible options.
1356 if (Name == "vsx") {
1357 Features[Name] = true;
1358 } else if (Name == "direct-move") {
1359 Features[Name] = Features["vsx"] = true;
1360 } else if (Name == "power8-vector") {
1361 Features[Name] = Features["vsx"] = true;
1363 Features[Name] = true;
1366 if (Name == "vsx") {
1367 Features[Name] = Features["direct-move"] = Features["power8-vector"] =
1370 Features[Name] = false;
1375 const char * const PPCTargetInfo::GCCRegNames[] = {
1376 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1377 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1378 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1379 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1380 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1381 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1382 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1383 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1384 "mq", "lr", "ctr", "ap",
1385 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1387 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1388 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1389 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1390 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1392 "spe_acc", "spefscr",
1396 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const {
1397 return llvm::makeArrayRef(GCCRegNames);
1400 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1401 // While some of these aliases do map to different registers
1402 // they still share the same register name.
1413 { { "10" }, "r10" },
1414 { { "11" }, "r11" },
1415 { { "12" }, "r12" },
1416 { { "13" }, "r13" },
1417 { { "14" }, "r14" },
1418 { { "15" }, "r15" },
1419 { { "16" }, "r16" },
1420 { { "17" }, "r17" },
1421 { { "18" }, "r18" },
1422 { { "19" }, "r19" },
1423 { { "20" }, "r20" },
1424 { { "21" }, "r21" },
1425 { { "22" }, "r22" },
1426 { { "23" }, "r23" },
1427 { { "24" }, "r24" },
1428 { { "25" }, "r25" },
1429 { { "26" }, "r26" },
1430 { { "27" }, "r27" },
1431 { { "28" }, "r28" },
1432 { { "29" }, "r29" },
1433 { { "30" }, "r30" },
1434 { { "31" }, "r31" },
1435 { { "fr0" }, "f0" },
1436 { { "fr1" }, "f1" },
1437 { { "fr2" }, "f2" },
1438 { { "fr3" }, "f3" },
1439 { { "fr4" }, "f4" },
1440 { { "fr5" }, "f5" },
1441 { { "fr6" }, "f6" },
1442 { { "fr7" }, "f7" },
1443 { { "fr8" }, "f8" },
1444 { { "fr9" }, "f9" },
1445 { { "fr10" }, "f10" },
1446 { { "fr11" }, "f11" },
1447 { { "fr12" }, "f12" },
1448 { { "fr13" }, "f13" },
1449 { { "fr14" }, "f14" },
1450 { { "fr15" }, "f15" },
1451 { { "fr16" }, "f16" },
1452 { { "fr17" }, "f17" },
1453 { { "fr18" }, "f18" },
1454 { { "fr19" }, "f19" },
1455 { { "fr20" }, "f20" },
1456 { { "fr21" }, "f21" },
1457 { { "fr22" }, "f22" },
1458 { { "fr23" }, "f23" },
1459 { { "fr24" }, "f24" },
1460 { { "fr25" }, "f25" },
1461 { { "fr26" }, "f26" },
1462 { { "fr27" }, "f27" },
1463 { { "fr28" }, "f28" },
1464 { { "fr29" }, "f29" },
1465 { { "fr30" }, "f30" },
1466 { { "fr31" }, "f31" },
1467 { { "cc" }, "cr0" },
1470 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
1471 return llvm::makeArrayRef(GCCRegAliases);
1474 class PPC32TargetInfo : public PPCTargetInfo {
1476 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1477 DataLayoutString = "E-m:e-p:32:32-i64:64-n32";
1479 switch (getTriple().getOS()) {
1480 case llvm::Triple::Linux:
1481 case llvm::Triple::FreeBSD:
1482 case llvm::Triple::NetBSD:
1483 SizeType = UnsignedInt;
1484 PtrDiffType = SignedInt;
1485 IntPtrType = SignedInt;
1491 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1492 LongDoubleWidth = LongDoubleAlign = 64;
1493 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1496 // PPC32 supports atomics up to 4 bytes.
1497 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1500 BuiltinVaListKind getBuiltinVaListKind() const override {
1501 // This is the ELF definition, and is overridden by the Darwin sub-target
1502 return TargetInfo::PowerABIBuiltinVaList;
1506 // Note: ABI differences may eventually require us to have a separate
1507 // TargetInfo for little endian.
1508 class PPC64TargetInfo : public PPCTargetInfo {
1510 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1511 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1512 IntMaxType = SignedLong;
1513 Int64Type = SignedLong;
1515 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1516 DataLayoutString = "e-m:e-i64:64-n32:64";
1519 DataLayoutString = "E-m:e-i64:64-n32:64";
1523 switch (getTriple().getOS()) {
1524 case llvm::Triple::FreeBSD:
1525 LongDoubleWidth = LongDoubleAlign = 64;
1526 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1528 case llvm::Triple::NetBSD:
1529 IntMaxType = SignedLongLong;
1530 Int64Type = SignedLongLong;
1536 // PPC64 supports atomics up to 8 bytes.
1537 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1539 BuiltinVaListKind getBuiltinVaListKind() const override {
1540 return TargetInfo::CharPtrBuiltinVaList;
1542 // PPC64 Linux-specific ABI options.
1543 bool setABI(const std::string &Name) override {
1544 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1552 class DarwinPPC32TargetInfo :
1553 public DarwinTargetInfo<PPC32TargetInfo> {
1555 DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1556 : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1557 HasAlignMac68kSupport = true;
1558 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1559 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1561 SuitableAlign = 128;
1562 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32";
1564 BuiltinVaListKind getBuiltinVaListKind() const override {
1565 return TargetInfo::CharPtrBuiltinVaList;
1569 class DarwinPPC64TargetInfo :
1570 public DarwinTargetInfo<PPC64TargetInfo> {
1572 DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1573 : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1574 HasAlignMac68kSupport = true;
1575 SuitableAlign = 128;
1576 DataLayoutString = "E-m:o-i64:64-n32:64";
1580 static const unsigned NVPTXAddrSpaceMap[] = {
1583 4, // opencl_constant
1584 // FIXME: generic has to be added to the target
1585 0, // opencl_generic
1591 class NVPTXTargetInfo : public TargetInfo {
1592 static const char *const GCCRegNames[];
1593 static const Builtin::Info BuiltinInfo[];
1595 // The GPU profiles supported by the NVPTX backend
1606 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1608 TLSSupported = false;
1609 LongWidth = LongAlign = 64;
1610 AddrSpaceMap = &NVPTXAddrSpaceMap;
1611 UseAddrSpaceMapMangling = true;
1612 // Define available target features
1613 // These must be defined in sorted order!
1614 NoAsmVariants = true;
1615 // Set the default GPU to sm20
1618 void getTargetDefines(const LangOptions &Opts,
1619 MacroBuilder &Builder) const override {
1620 Builder.defineMacro("__PTX__");
1621 Builder.defineMacro("__NVPTX__");
1622 if (Opts.CUDAIsDevice) {
1623 // Set __CUDA_ARCH__ for the GPU specified.
1624 std::string CUDAArchCode;
1627 CUDAArchCode = "200";
1630 CUDAArchCode = "210";
1633 CUDAArchCode = "300";
1636 CUDAArchCode = "350";
1639 CUDAArchCode = "370";
1642 llvm_unreachable("Unhandled target CPU");
1644 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1647 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1648 return llvm::makeArrayRef(BuiltinInfo,
1649 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin);
1651 bool hasFeature(StringRef Feature) const override {
1652 return Feature == "ptx" || Feature == "nvptx";
1655 ArrayRef<const char *> getGCCRegNames() const override;
1656 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1660 bool validateAsmConstraint(const char *&Name,
1661 TargetInfo::ConstraintInfo &Info) const override {
1671 Info.setAllowsRegister();
1675 const char *getClobbers() const override {
1676 // FIXME: Is this really right?
1679 BuiltinVaListKind getBuiltinVaListKind() const override {
1681 return TargetInfo::CharPtrBuiltinVaList;
1683 bool setCPU(const std::string &Name) override {
1684 GPU = llvm::StringSwitch<GPUKind>(Name)
1685 .Case("sm_20", GK_SM20)
1686 .Case("sm_21", GK_SM21)
1687 .Case("sm_30", GK_SM30)
1688 .Case("sm_35", GK_SM35)
1689 .Case("sm_37", GK_SM37)
1692 return GPU != GK_NONE;
1696 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1697 #define BUILTIN(ID, TYPE, ATTRS) \
1698 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1699 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1700 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1701 #include "clang/Basic/BuiltinsNVPTX.def"
1704 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
1706 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
1707 return llvm::makeArrayRef(GCCRegNames);
1710 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1712 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1713 LongWidth = LongAlign = 32;
1714 PointerWidth = PointerAlign = 32;
1715 SizeType = TargetInfo::UnsignedInt;
1716 PtrDiffType = TargetInfo::SignedInt;
1717 IntPtrType = TargetInfo::SignedInt;
1718 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1722 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1724 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1725 PointerWidth = PointerAlign = 64;
1726 SizeType = TargetInfo::UnsignedLong;
1727 PtrDiffType = TargetInfo::SignedLong;
1728 IntPtrType = TargetInfo::SignedLong;
1729 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64";
1733 static const unsigned AMDGPUAddrSpaceMap[] = {
1736 2, // opencl_constant
1737 4, // opencl_generic
1743 // If you edit the description strings, make sure you update
1744 // getPointerWidthV().
1746 static const char *const DataLayoutStringR600 =
1747 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1748 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1750 static const char *const DataLayoutStringR600DoubleOps =
1751 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1752 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1754 static const char *const DataLayoutStringSI =
1755 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1756 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1757 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1759 class AMDGPUTargetInfo : public TargetInfo {
1760 static const Builtin::Info BuiltinInfo[];
1761 static const char * const GCCRegNames[];
1763 /// \brief The GPU profiles supported by the AMDGPU target.
1771 GK_EVERGREEN_DOUBLE_OPS,
1772 GK_NORTHERN_ISLANDS,
1774 GK_SOUTHERN_ISLANDS,
1784 AMDGPUTargetInfo(const llvm::Triple &Triple)
1785 : TargetInfo(Triple) {
1787 if (Triple.getArch() == llvm::Triple::amdgcn) {
1788 DataLayoutString = DataLayoutStringSI;
1789 GPU = GK_SOUTHERN_ISLANDS;
1794 DataLayoutString = DataLayoutStringR600;
1800 AddrSpaceMap = &AMDGPUAddrSpaceMap;
1801 UseAddrSpaceMapMangling = true;
1804 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1805 if (GPU <= GK_CAYMAN)
1818 const char * getClobbers() const override {
1822 ArrayRef<const char *> getGCCRegNames() const override;
1824 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1828 bool validateAsmConstraint(const char *&Name,
1829 TargetInfo::ConstraintInfo &Info) const override {
1834 Info.setAllowsRegister();
1840 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1841 return llvm::makeArrayRef(BuiltinInfo,
1842 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin);
1845 void getTargetDefines(const LangOptions &Opts,
1846 MacroBuilder &Builder) const override {
1847 Builder.defineMacro("__R600__");
1849 Builder.defineMacro("__HAS_FMAF__");
1851 Builder.defineMacro("__HAS_LDEXPF__");
1852 if (hasFP64 && Opts.OpenCL)
1853 Builder.defineMacro("cl_khr_fp64");
1855 if (GPU >= GK_NORTHERN_ISLANDS) {
1856 Builder.defineMacro("cl_khr_byte_addressable_store");
1857 Builder.defineMacro("cl_khr_global_int32_base_atomics");
1858 Builder.defineMacro("cl_khr_global_int32_extended_atomics");
1859 Builder.defineMacro("cl_khr_local_int32_base_atomics");
1860 Builder.defineMacro("cl_khr_local_int32_extended_atomics");
1865 BuiltinVaListKind getBuiltinVaListKind() const override {
1866 return TargetInfo::CharPtrBuiltinVaList;
1869 bool setCPU(const std::string &Name) override {
1870 GPU = llvm::StringSwitch<GPUKind>(Name)
1871 .Case("r600" , GK_R600)
1872 .Case("rv610", GK_R600)
1873 .Case("rv620", GK_R600)
1874 .Case("rv630", GK_R600)
1875 .Case("rv635", GK_R600)
1876 .Case("rs780", GK_R600)
1877 .Case("rs880", GK_R600)
1878 .Case("rv670", GK_R600_DOUBLE_OPS)
1879 .Case("rv710", GK_R700)
1880 .Case("rv730", GK_R700)
1881 .Case("rv740", GK_R700_DOUBLE_OPS)
1882 .Case("rv770", GK_R700_DOUBLE_OPS)
1883 .Case("palm", GK_EVERGREEN)
1884 .Case("cedar", GK_EVERGREEN)
1885 .Case("sumo", GK_EVERGREEN)
1886 .Case("sumo2", GK_EVERGREEN)
1887 .Case("redwood", GK_EVERGREEN)
1888 .Case("juniper", GK_EVERGREEN)
1889 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
1890 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
1891 .Case("barts", GK_NORTHERN_ISLANDS)
1892 .Case("turks", GK_NORTHERN_ISLANDS)
1893 .Case("caicos", GK_NORTHERN_ISLANDS)
1894 .Case("cayman", GK_CAYMAN)
1895 .Case("aruba", GK_CAYMAN)
1896 .Case("tahiti", GK_SOUTHERN_ISLANDS)
1897 .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1898 .Case("verde", GK_SOUTHERN_ISLANDS)
1899 .Case("oland", GK_SOUTHERN_ISLANDS)
1900 .Case("hainan", GK_SOUTHERN_ISLANDS)
1901 .Case("bonaire", GK_SEA_ISLANDS)
1902 .Case("kabini", GK_SEA_ISLANDS)
1903 .Case("kaveri", GK_SEA_ISLANDS)
1904 .Case("hawaii", GK_SEA_ISLANDS)
1905 .Case("mullins", GK_SEA_ISLANDS)
1906 .Case("tonga", GK_VOLCANIC_ISLANDS)
1907 .Case("iceland", GK_VOLCANIC_ISLANDS)
1908 .Case("carrizo", GK_VOLCANIC_ISLANDS)
1911 if (GPU == GK_NONE) {
1915 // Set the correct data layout
1921 case GK_NORTHERN_ISLANDS:
1922 DataLayoutString = DataLayoutStringR600;
1927 case GK_R600_DOUBLE_OPS:
1928 case GK_R700_DOUBLE_OPS:
1929 case GK_EVERGREEN_DOUBLE_OPS:
1931 DataLayoutString = DataLayoutStringR600DoubleOps;
1936 case GK_SOUTHERN_ISLANDS:
1937 case GK_SEA_ISLANDS:
1938 case GK_VOLCANIC_ISLANDS:
1939 DataLayoutString = DataLayoutStringSI;
1950 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
1951 #define BUILTIN(ID, TYPE, ATTRS) \
1952 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1953 #include "clang/Basic/BuiltinsAMDGPU.def"
1955 const char * const AMDGPUTargetInfo::GCCRegNames[] = {
1956 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1957 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1958 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1959 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1960 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
1961 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
1962 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
1963 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
1964 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
1965 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
1966 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
1967 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
1968 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
1969 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
1970 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
1971 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
1972 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
1973 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
1974 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
1975 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
1976 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
1977 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
1978 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
1979 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
1980 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
1981 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
1982 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
1983 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
1984 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
1985 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
1986 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
1987 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
1988 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1989 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
1990 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
1991 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
1992 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
1993 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
1994 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
1995 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
1996 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
1997 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
1998 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
1999 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
2000 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
2001 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
2002 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
2003 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127"
2004 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi",
2005 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi"
2008 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const {
2009 return llvm::makeArrayRef(GCCRegNames);
2012 // Namespace for x86 abstract base class
2013 const Builtin::Info BuiltinInfo[] = {
2014 #define BUILTIN(ID, TYPE, ATTRS) \
2015 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2016 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
2017 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
2018 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2019 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2020 #include "clang/Basic/BuiltinsX86.def"
2023 static const char* const GCCRegNames[] = {
2024 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
2025 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
2026 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
2027 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
2028 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
2029 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2030 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
2031 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
2032 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
2035 const TargetInfo::AddlRegName AddlRegNames[] = {
2036 { { "al", "ah", "eax", "rax" }, 0 },
2037 { { "bl", "bh", "ebx", "rbx" }, 3 },
2038 { { "cl", "ch", "ecx", "rcx" }, 2 },
2039 { { "dl", "dh", "edx", "rdx" }, 1 },
2040 { { "esi", "rsi" }, 4 },
2041 { { "edi", "rdi" }, 5 },
2042 { { "esp", "rsp" }, 7 },
2043 { { "ebp", "rbp" }, 6 },
2044 { { "r8d", "r8w", "r8b" }, 38 },
2045 { { "r9d", "r9w", "r9b" }, 39 },
2046 { { "r10d", "r10w", "r10b" }, 40 },
2047 { { "r11d", "r11w", "r11b" }, 41 },
2048 { { "r12d", "r12w", "r12b" }, 42 },
2049 { { "r13d", "r13w", "r13b" }, 43 },
2050 { { "r14d", "r14w", "r14b" }, 44 },
2051 { { "r15d", "r15w", "r15b" }, 45 },
2054 // X86 target abstract base class; x86-32 and x86-64 are very close, so
2055 // most of the implementation can be shared.
2056 class X86TargetInfo : public TargetInfo {
2058 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
2061 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
2062 } MMX3DNowLevel = NoMMX3DNow;
2070 bool HasAES = false;
2071 bool HasPCLMUL = false;
2072 bool HasLZCNT = false;
2073 bool HasRDRND = false;
2074 bool HasFSGSBASE = false;
2075 bool HasBMI = false;
2076 bool HasBMI2 = false;
2077 bool HasPOPCNT = false;
2078 bool HasRTM = false;
2079 bool HasPRFCHW = false;
2080 bool HasRDSEED = false;
2081 bool HasADX = false;
2082 bool HasTBM = false;
2083 bool HasFMA = false;
2084 bool HasF16C = false;
2085 bool HasAVX512CD = false;
2086 bool HasAVX512ER = false;
2087 bool HasAVX512PF = false;
2088 bool HasAVX512DQ = false;
2089 bool HasAVX512BW = false;
2090 bool HasAVX512VL = false;
2091 bool HasSHA = false;
2092 bool HasCX16 = false;
2093 bool HasFXSR = false;
2094 bool HasXSAVE = false;
2095 bool HasXSAVEOPT = false;
2096 bool HasXSAVEC = false;
2097 bool HasXSAVES = false;
2098 bool HasPKU = false;
2100 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2102 /// Each enumeration represents a particular CPU supported by Clang. These
2103 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2108 /// i386-generation processors.
2114 /// i486-generation processors.
2123 /// i586-generation processors, P5 microarchitecture based.
2131 /// i686-generation processors, P6 / Pentium M microarchitecture based.
2141 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2142 /// Clang however has some logic to suport this.
2143 // FIXME: Warn, deprecate, and potentially remove this.
2148 /// Netburst microarchitecture based processors.
2157 /// Core microarchitecture based processors.
2161 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2162 /// codename which GCC no longer accepts as an option to -march, but Clang
2163 /// has some logic for recognizing it.
2164 // FIXME: Warn, deprecate, and potentially remove this.
2176 /// Nehalem microarchitecture based processors.
2180 /// Westmere microarchitecture based processors.
2183 /// \name Sandy Bridge
2184 /// Sandy Bridge microarchitecture based processors.
2187 /// \name Ivy Bridge
2188 /// Ivy Bridge microarchitecture based processors.
2192 /// Haswell microarchitecture based processors.
2196 /// Broadwell microarchitecture based processors.
2200 /// Skylake microarchitecture based processors.
2203 /// \name Knights Landing
2204 /// Knights Landing processor.
2208 /// K6 architecture processors.
2216 /// K7 architecture processors.
2219 CK_AthlonThunderbird,
2226 /// K8 architecture processors.
2239 /// Bobcat architecture processors.
2246 /// Bulldozer architecture processors.
2254 /// This specification is deprecated and will be removed in the future.
2255 /// Users should prefer \see CK_K8.
2256 // FIXME: Warn on this when the CPU is set to it.
2262 /// Geode processors.
2268 CPUKind getCPUKind(StringRef CPU) const {
2269 return llvm::StringSwitch<CPUKind>(CPU)
2270 .Case("i386", CK_i386)
2271 .Case("i486", CK_i486)
2272 .Case("winchip-c6", CK_WinChipC6)
2273 .Case("winchip2", CK_WinChip2)
2275 .Case("i586", CK_i586)
2276 .Case("pentium", CK_Pentium)
2277 .Case("pentium-mmx", CK_PentiumMMX)
2278 .Case("i686", CK_i686)
2279 .Case("pentiumpro", CK_PentiumPro)
2280 .Case("pentium2", CK_Pentium2)
2281 .Case("pentium3", CK_Pentium3)
2282 .Case("pentium3m", CK_Pentium3M)
2283 .Case("pentium-m", CK_PentiumM)
2284 .Case("c3-2", CK_C3_2)
2285 .Case("yonah", CK_Yonah)
2286 .Case("pentium4", CK_Pentium4)
2287 .Case("pentium4m", CK_Pentium4M)
2288 .Case("prescott", CK_Prescott)
2289 .Case("nocona", CK_Nocona)
2290 .Case("core2", CK_Core2)
2291 .Case("penryn", CK_Penryn)
2292 .Case("bonnell", CK_Bonnell)
2293 .Case("atom", CK_Bonnell) // Legacy name.
2294 .Case("silvermont", CK_Silvermont)
2295 .Case("slm", CK_Silvermont) // Legacy name.
2296 .Case("nehalem", CK_Nehalem)
2297 .Case("corei7", CK_Nehalem) // Legacy name.
2298 .Case("westmere", CK_Westmere)
2299 .Case("sandybridge", CK_SandyBridge)
2300 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2301 .Case("ivybridge", CK_IvyBridge)
2302 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2303 .Case("haswell", CK_Haswell)
2304 .Case("core-avx2", CK_Haswell) // Legacy name.
2305 .Case("broadwell", CK_Broadwell)
2306 .Case("skylake", CK_Skylake)
2307 .Case("skx", CK_Skylake) // Legacy name.
2308 .Case("knl", CK_KNL)
2310 .Case("k6-2", CK_K6_2)
2311 .Case("k6-3", CK_K6_3)
2312 .Case("athlon", CK_Athlon)
2313 .Case("athlon-tbird", CK_AthlonThunderbird)
2314 .Case("athlon-4", CK_Athlon4)
2315 .Case("athlon-xp", CK_AthlonXP)
2316 .Case("athlon-mp", CK_AthlonMP)
2317 .Case("athlon64", CK_Athlon64)
2318 .Case("athlon64-sse3", CK_Athlon64SSE3)
2319 .Case("athlon-fx", CK_AthlonFX)
2321 .Case("k8-sse3", CK_K8SSE3)
2322 .Case("opteron", CK_Opteron)
2323 .Case("opteron-sse3", CK_OpteronSSE3)
2324 .Case("barcelona", CK_AMDFAM10)
2325 .Case("amdfam10", CK_AMDFAM10)
2326 .Case("btver1", CK_BTVER1)
2327 .Case("btver2", CK_BTVER2)
2328 .Case("bdver1", CK_BDVER1)
2329 .Case("bdver2", CK_BDVER2)
2330 .Case("bdver3", CK_BDVER3)
2331 .Case("bdver4", CK_BDVER4)
2332 .Case("x86-64", CK_x86_64)
2333 .Case("geode", CK_Geode)
2334 .Default(CK_Generic);
2341 } FPMath = FP_Default;
2344 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
2346 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
2348 unsigned getFloatEvalMethod() const override {
2349 // X87 evaluates with 80 bits "long double" precision.
2350 return SSELevel == NoSSE ? 2 : 0;
2352 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
2353 return llvm::makeArrayRef(BuiltinInfo,
2354 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin);
2356 ArrayRef<const char *> getGCCRegNames() const override {
2357 return llvm::makeArrayRef(GCCRegNames);
2359 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2362 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
2363 return llvm::makeArrayRef(AddlRegNames);
2365 bool validateCpuSupports(StringRef Name) const override;
2366 bool validateAsmConstraint(const char *&Name,
2367 TargetInfo::ConstraintInfo &info) const override;
2369 bool validateGlobalRegisterVariable(StringRef RegName,
2371 bool &HasSizeMismatch) const override {
2372 // esp and ebp are the only 32-bit registers the x86 backend can currently
2374 if (RegName.equals("esp") || RegName.equals("ebp")) {
2375 // Check that the register size is 32-bit.
2376 HasSizeMismatch = RegSize != 32;
2383 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2385 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2387 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2389 std::string convertConstraint(const char *&Constraint) const override;
2390 const char *getClobbers() const override {
2391 return "~{dirflag},~{fpsr},~{flags}";
2393 void getTargetDefines(const LangOptions &Opts,
2394 MacroBuilder &Builder) const override;
2395 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2397 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2399 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2401 void setFeatureEnabled(llvm::StringMap<bool> &Features,
2402 StringRef Name, bool Enabled) const override {
2403 setFeatureEnabledImpl(Features, Name, Enabled);
2405 // This exists purely to cut down on the number of virtual calls in
2406 // initFeatureMap which calls this repeatedly.
2407 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2408 StringRef Name, bool Enabled);
2410 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
2412 const std::vector<std::string> &FeaturesVec) const override;
2413 bool hasFeature(StringRef Feature) const override;
2414 bool handleTargetFeatures(std::vector<std::string> &Features,
2415 DiagnosticsEngine &Diags) override;
2416 StringRef getABI() const override {
2417 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
2419 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2421 if (getTriple().getArch() == llvm::Triple::x86 &&
2422 MMX3DNowLevel == NoMMX3DNow)
2426 bool setCPU(const std::string &Name) override {
2427 CPU = getCPUKind(Name);
2429 // Perform any per-CPU checks necessary to determine if this CPU is
2431 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2432 // invalid without explaining *why*.
2435 // No processor selected!
2461 case CK_AthlonThunderbird:
2466 // Only accept certain architectures when compiling in 32-bit mode.
2467 if (getTriple().getArch() != llvm::Triple::x86)
2478 case CK_SandyBridge:
2485 case CK_Athlon64SSE3:
2490 case CK_OpteronSSE3:
2501 llvm_unreachable("Unhandled CPU kind");
2504 bool setFPMath(StringRef Name) override;
2506 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2507 // We accept all non-ARM calling conventions
2508 return (CC == CC_X86ThisCall ||
2509 CC == CC_X86FastCall ||
2510 CC == CC_X86StdCall ||
2511 CC == CC_X86VectorCall ||
2513 CC == CC_X86Pascal ||
2514 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2517 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2518 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2521 bool hasSjLjLowering() const override {
2526 bool X86TargetInfo::setFPMath(StringRef Name) {
2527 if (Name == "387") {
2531 if (Name == "sse") {
2538 bool X86TargetInfo::initFeatureMap(
2539 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
2540 const std::vector<std::string> &FeaturesVec) const {
2541 // FIXME: This *really* should not be here.
2542 // X86_64 always has SSE2.
2543 if (getTriple().getArch() == llvm::Triple::x86_64)
2544 setFeatureEnabledImpl(Features, "sse2", true);
2546 switch (getCPUKind(CPU)) {
2559 setFeatureEnabledImpl(Features, "mmx", true);
2564 setFeatureEnabledImpl(Features, "sse", true);
2565 setFeatureEnabledImpl(Features, "fxsr", true);
2571 setFeatureEnabledImpl(Features, "sse2", true);
2572 setFeatureEnabledImpl(Features, "fxsr", true);
2577 setFeatureEnabledImpl(Features, "sse3", true);
2578 setFeatureEnabledImpl(Features, "fxsr", true);
2579 setFeatureEnabledImpl(Features, "cx16", true);
2583 setFeatureEnabledImpl(Features, "ssse3", true);
2584 setFeatureEnabledImpl(Features, "fxsr", true);
2585 setFeatureEnabledImpl(Features, "cx16", true);
2588 setFeatureEnabledImpl(Features, "sse4.1", true);
2589 setFeatureEnabledImpl(Features, "fxsr", true);
2590 setFeatureEnabledImpl(Features, "cx16", true);
2593 setFeatureEnabledImpl(Features, "avx512f", true);
2594 setFeatureEnabledImpl(Features, "avx512cd", true);
2595 setFeatureEnabledImpl(Features, "avx512dq", true);
2596 setFeatureEnabledImpl(Features, "avx512bw", true);
2597 setFeatureEnabledImpl(Features, "avx512vl", true);
2598 setFeatureEnabledImpl(Features, "xsavec", true);
2599 setFeatureEnabledImpl(Features, "xsaves", true);
2600 setFeatureEnabledImpl(Features, "pku", true);
2603 setFeatureEnabledImpl(Features, "rdseed", true);
2604 setFeatureEnabledImpl(Features, "adx", true);
2607 setFeatureEnabledImpl(Features, "avx2", true);
2608 setFeatureEnabledImpl(Features, "lzcnt", true);
2609 setFeatureEnabledImpl(Features, "bmi", true);
2610 setFeatureEnabledImpl(Features, "bmi2", true);
2611 setFeatureEnabledImpl(Features, "rtm", true);
2612 setFeatureEnabledImpl(Features, "fma", true);
2615 setFeatureEnabledImpl(Features, "rdrnd", true);
2616 setFeatureEnabledImpl(Features, "f16c", true);
2617 setFeatureEnabledImpl(Features, "fsgsbase", true);
2619 case CK_SandyBridge:
2620 setFeatureEnabledImpl(Features, "avx", true);
2621 setFeatureEnabledImpl(Features, "xsave", true);
2622 setFeatureEnabledImpl(Features, "xsaveopt", true);
2626 setFeatureEnabledImpl(Features, "aes", true);
2627 setFeatureEnabledImpl(Features, "pclmul", true);
2630 setFeatureEnabledImpl(Features, "sse4.2", true);
2631 setFeatureEnabledImpl(Features, "fxsr", true);
2632 setFeatureEnabledImpl(Features, "cx16", true);
2635 setFeatureEnabledImpl(Features, "avx512f", true);
2636 setFeatureEnabledImpl(Features, "avx512cd", true);
2637 setFeatureEnabledImpl(Features, "avx512er", true);
2638 setFeatureEnabledImpl(Features, "avx512pf", true);
2639 setFeatureEnabledImpl(Features, "fxsr", true);
2640 setFeatureEnabledImpl(Features, "rdseed", true);
2641 setFeatureEnabledImpl(Features, "adx", true);
2642 setFeatureEnabledImpl(Features, "lzcnt", true);
2643 setFeatureEnabledImpl(Features, "bmi", true);
2644 setFeatureEnabledImpl(Features, "bmi2", true);
2645 setFeatureEnabledImpl(Features, "rtm", true);
2646 setFeatureEnabledImpl(Features, "fma", true);
2647 setFeatureEnabledImpl(Features, "rdrnd", true);
2648 setFeatureEnabledImpl(Features, "f16c", true);
2649 setFeatureEnabledImpl(Features, "fsgsbase", true);
2650 setFeatureEnabledImpl(Features, "aes", true);
2651 setFeatureEnabledImpl(Features, "pclmul", true);
2652 setFeatureEnabledImpl(Features, "cx16", true);
2653 setFeatureEnabledImpl(Features, "xsaveopt", true);
2654 setFeatureEnabledImpl(Features, "xsave", true);
2660 setFeatureEnabledImpl(Features, "3dnow", true);
2663 case CK_AthlonThunderbird:
2665 setFeatureEnabledImpl(Features, "3dnowa", true);
2670 setFeatureEnabledImpl(Features, "sse", true);
2671 setFeatureEnabledImpl(Features, "3dnowa", true);
2672 setFeatureEnabledImpl(Features, "fxsr", true);
2678 setFeatureEnabledImpl(Features, "sse2", true);
2679 setFeatureEnabledImpl(Features, "3dnowa", true);
2680 setFeatureEnabledImpl(Features, "fxsr", true);
2683 setFeatureEnabledImpl(Features, "sse4a", true);
2684 setFeatureEnabledImpl(Features, "lzcnt", true);
2685 setFeatureEnabledImpl(Features, "popcnt", true);
2688 case CK_OpteronSSE3:
2689 case CK_Athlon64SSE3:
2690 setFeatureEnabledImpl(Features, "sse3", true);
2691 setFeatureEnabledImpl(Features, "3dnowa", true);
2692 setFeatureEnabledImpl(Features, "fxsr", true);
2695 setFeatureEnabledImpl(Features, "avx", true);
2696 setFeatureEnabledImpl(Features, "aes", true);
2697 setFeatureEnabledImpl(Features, "pclmul", true);
2698 setFeatureEnabledImpl(Features, "bmi", true);
2699 setFeatureEnabledImpl(Features, "f16c", true);
2700 setFeatureEnabledImpl(Features, "xsaveopt", true);
2703 setFeatureEnabledImpl(Features, "ssse3", true);
2704 setFeatureEnabledImpl(Features, "sse4a", true);
2705 setFeatureEnabledImpl(Features, "lzcnt", true);
2706 setFeatureEnabledImpl(Features, "popcnt", true);
2707 setFeatureEnabledImpl(Features, "prfchw", true);
2708 setFeatureEnabledImpl(Features, "cx16", true);
2709 setFeatureEnabledImpl(Features, "fxsr", true);
2710 setFeatureEnabledImpl(Features, "xsave", true);
2713 setFeatureEnabledImpl(Features, "avx2", true);
2714 setFeatureEnabledImpl(Features, "bmi2", true);
2717 setFeatureEnabledImpl(Features, "fsgsbase", true);
2718 setFeatureEnabledImpl(Features, "xsaveopt", true);
2721 setFeatureEnabledImpl(Features, "bmi", true);
2722 setFeatureEnabledImpl(Features, "fma", true);
2723 setFeatureEnabledImpl(Features, "f16c", true);
2724 setFeatureEnabledImpl(Features, "tbm", true);
2727 // xop implies avx, sse4a and fma4.
2728 setFeatureEnabledImpl(Features, "xop", true);
2729 setFeatureEnabledImpl(Features, "lzcnt", true);
2730 setFeatureEnabledImpl(Features, "aes", true);
2731 setFeatureEnabledImpl(Features, "pclmul", true);
2732 setFeatureEnabledImpl(Features, "prfchw", true);
2733 setFeatureEnabledImpl(Features, "cx16", true);
2734 setFeatureEnabledImpl(Features, "fxsr", true);
2735 setFeatureEnabledImpl(Features, "xsave", true);
2738 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
2741 // Can't do this earlier because we need to be able to explicitly enable
2742 // or disable these features and the things that they depend upon.
2744 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2745 auto I = Features.find("sse4.2");
2746 if (I != Features.end() && I->getValue() &&
2747 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
2749 Features["popcnt"] = true;
2751 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2752 I = Features.find("3dnow");
2753 if (I != Features.end() && I->getValue() &&
2754 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
2756 Features["prfchw"] = true;
2758 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2760 I = Features.find("sse");
2761 if (I != Features.end() && I->getValue() &&
2762 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
2764 Features["mmx"] = true;
2769 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2770 X86SSEEnum Level, bool Enabled) {
2774 Features["avx512f"] = true;
2776 Features["avx2"] = true;
2778 Features["avx"] = true;
2779 Features["xsave"] = true;
2781 Features["sse4.2"] = true;
2783 Features["sse4.1"] = true;
2785 Features["ssse3"] = true;
2787 Features["sse3"] = true;
2789 Features["sse2"] = true;
2791 Features["sse"] = true;
2801 Features["sse"] = false;
2803 Features["sse2"] = Features["pclmul"] = Features["aes"] =
2804 Features["sha"] = false;
2806 Features["sse3"] = false;
2807 setXOPLevel(Features, NoXOP, false);
2809 Features["ssse3"] = false;
2811 Features["sse4.1"] = false;
2813 Features["sse4.2"] = false;
2815 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
2816 Features["xsaveopt"] = false;
2817 setXOPLevel(Features, FMA4, false);
2819 Features["avx2"] = false;
2821 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2822 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2823 Features["avx512vl"] = false;
2827 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2828 MMX3DNowEnum Level, bool Enabled) {
2831 case AMD3DNowAthlon:
2832 Features["3dnowa"] = true;
2834 Features["3dnow"] = true;
2836 Features["mmx"] = true;
2846 Features["mmx"] = false;
2848 Features["3dnow"] = false;
2849 case AMD3DNowAthlon:
2850 Features["3dnowa"] = false;
2854 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2859 Features["xop"] = true;
2861 Features["fma4"] = true;
2862 setSSELevel(Features, AVX, true);
2864 Features["sse4a"] = true;
2865 setSSELevel(Features, SSE3, true);
2875 Features["sse4a"] = false;
2877 Features["fma4"] = false;
2879 Features["xop"] = false;
2883 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2884 StringRef Name, bool Enabled) {
2885 // This is a bit of a hack to deal with the sse4 target feature when used
2886 // as part of the target attribute. We handle sse4 correctly everywhere
2887 // else. See below for more information on how we handle the sse4 options.
2889 Features[Name] = Enabled;
2891 if (Name == "mmx") {
2892 setMMXLevel(Features, MMX, Enabled);
2893 } else if (Name == "sse") {
2894 setSSELevel(Features, SSE1, Enabled);
2895 } else if (Name == "sse2") {
2896 setSSELevel(Features, SSE2, Enabled);
2897 } else if (Name == "sse3") {
2898 setSSELevel(Features, SSE3, Enabled);
2899 } else if (Name == "ssse3") {
2900 setSSELevel(Features, SSSE3, Enabled);
2901 } else if (Name == "sse4.2") {
2902 setSSELevel(Features, SSE42, Enabled);
2903 } else if (Name == "sse4.1") {
2904 setSSELevel(Features, SSE41, Enabled);
2905 } else if (Name == "3dnow") {
2906 setMMXLevel(Features, AMD3DNow, Enabled);
2907 } else if (Name == "3dnowa") {
2908 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2909 } else if (Name == "aes") {
2911 setSSELevel(Features, SSE2, Enabled);
2912 } else if (Name == "pclmul") {
2914 setSSELevel(Features, SSE2, Enabled);
2915 } else if (Name == "avx") {
2916 setSSELevel(Features, AVX, Enabled);
2917 } else if (Name == "avx2") {
2918 setSSELevel(Features, AVX2, Enabled);
2919 } else if (Name == "avx512f") {
2920 setSSELevel(Features, AVX512F, Enabled);
2921 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2922 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2924 setSSELevel(Features, AVX512F, Enabled);
2925 } else if (Name == "fma") {
2927 setSSELevel(Features, AVX, Enabled);
2928 } else if (Name == "fma4") {
2929 setXOPLevel(Features, FMA4, Enabled);
2930 } else if (Name == "xop") {
2931 setXOPLevel(Features, XOP, Enabled);
2932 } else if (Name == "sse4a") {
2933 setXOPLevel(Features, SSE4A, Enabled);
2934 } else if (Name == "f16c") {
2936 setSSELevel(Features, AVX, Enabled);
2937 } else if (Name == "sha") {
2939 setSSELevel(Features, SSE2, Enabled);
2940 } else if (Name == "sse4") {
2941 // We can get here via the __target__ attribute since that's not controlled
2942 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
2943 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
2946 setSSELevel(Features, SSE42, Enabled);
2948 setSSELevel(Features, SSE41, Enabled);
2949 } else if (Name == "xsave") {
2951 setSSELevel(Features, AVX, Enabled);
2953 Features["xsaveopt"] = false;
2954 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
2956 Features["xsave"] = true;
2957 setSSELevel(Features, AVX, Enabled);
2962 /// handleTargetFeatures - Perform initialization based on the user
2963 /// configured set of features.
2964 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2965 DiagnosticsEngine &Diags) {
2966 for (const auto &Feature : Features) {
2967 if (Feature[0] != '+')
2970 if (Feature == "+aes") {
2972 } else if (Feature == "+pclmul") {
2974 } else if (Feature == "+lzcnt") {
2976 } else if (Feature == "+rdrnd") {
2978 } else if (Feature == "+fsgsbase") {
2980 } else if (Feature == "+bmi") {
2982 } else if (Feature == "+bmi2") {
2984 } else if (Feature == "+popcnt") {
2986 } else if (Feature == "+rtm") {
2988 } else if (Feature == "+prfchw") {
2990 } else if (Feature == "+rdseed") {
2992 } else if (Feature == "+adx") {
2994 } else if (Feature == "+tbm") {
2996 } else if (Feature == "+fma") {
2998 } else if (Feature == "+f16c") {
3000 } else if (Feature == "+avx512cd") {
3002 } else if (Feature == "+avx512er") {
3004 } else if (Feature == "+avx512pf") {
3006 } else if (Feature == "+avx512dq") {
3008 } else if (Feature == "+avx512bw") {
3010 } else if (Feature == "+avx512vl") {
3012 } else if (Feature == "+sha") {
3014 } else if (Feature == "+cx16") {
3016 } else if (Feature == "+fxsr") {
3018 } else if (Feature == "+xsave") {
3020 } else if (Feature == "+xsaveopt") {
3022 } else if (Feature == "+xsavec") {
3024 } else if (Feature == "+xsaves") {
3026 } else if (Feature == "+pku") {
3030 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
3031 .Case("+avx512f", AVX512F)
3032 .Case("+avx2", AVX2)
3034 .Case("+sse4.2", SSE42)
3035 .Case("+sse4.1", SSE41)
3036 .Case("+ssse3", SSSE3)
3037 .Case("+sse3", SSE3)
3038 .Case("+sse2", SSE2)
3041 SSELevel = std::max(SSELevel, Level);
3043 MMX3DNowEnum ThreeDNowLevel =
3044 llvm::StringSwitch<MMX3DNowEnum>(Feature)
3045 .Case("+3dnowa", AMD3DNowAthlon)
3046 .Case("+3dnow", AMD3DNow)
3048 .Default(NoMMX3DNow);
3049 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
3051 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
3053 .Case("+fma4", FMA4)
3054 .Case("+sse4a", SSE4A)
3056 XOPLevel = std::max(XOPLevel, XLevel);
3059 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
3060 // matches the selected sse level.
3061 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
3062 (FPMath == FP_387 && SSELevel >= SSE1)) {
3063 Diags.Report(diag::err_target_unsupported_fpmath) <<
3064 (FPMath == FP_SSE ? "sse" : "387");
3069 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3073 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
3074 /// definitions for this particular subtarget.
3075 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
3076 MacroBuilder &Builder) const {
3077 // Target identification.
3078 if (getTriple().getArch() == llvm::Triple::x86_64) {
3079 Builder.defineMacro("__amd64__");
3080 Builder.defineMacro("__amd64");
3081 Builder.defineMacro("__x86_64");
3082 Builder.defineMacro("__x86_64__");
3083 if (getTriple().getArchName() == "x86_64h") {
3084 Builder.defineMacro("__x86_64h");
3085 Builder.defineMacro("__x86_64h__");
3088 DefineStd(Builder, "i386", Opts);
3091 // Subtarget options.
3092 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
3093 // truly should be based on -mtune options.
3098 // The rest are coming from the i386 define above.
3099 Builder.defineMacro("__tune_i386__");
3105 defineCPUMacros(Builder, "i486");
3108 Builder.defineMacro("__pentium_mmx__");
3109 Builder.defineMacro("__tune_pentium_mmx__");
3113 defineCPUMacros(Builder, "i586");
3114 defineCPUMacros(Builder, "pentium");
3119 Builder.defineMacro("__tune_pentium3__");
3123 Builder.defineMacro("__tune_pentium2__");
3126 Builder.defineMacro("__tune_i686__");
3127 Builder.defineMacro("__tune_pentiumpro__");
3130 Builder.defineMacro("__i686");
3131 Builder.defineMacro("__i686__");
3132 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3133 Builder.defineMacro("__pentiumpro");
3134 Builder.defineMacro("__pentiumpro__");
3138 defineCPUMacros(Builder, "pentium4");
3143 defineCPUMacros(Builder, "nocona");
3147 defineCPUMacros(Builder, "core2");
3150 defineCPUMacros(Builder, "atom");
3153 defineCPUMacros(Builder, "slm");
3157 case CK_SandyBridge:
3161 // FIXME: Historically, we defined this legacy name, it would be nice to
3162 // remove it at some point. We've never exposed fine-grained names for
3163 // recent primary x86 CPUs, and we should keep it that way.
3164 defineCPUMacros(Builder, "corei7");
3167 // FIXME: Historically, we defined this legacy name, it would be nice to
3168 // remove it at some point. This is the only fine-grained CPU macro in the
3169 // main intel CPU line, and it would be better to not have these and force
3170 // people to use ISA macros.
3171 defineCPUMacros(Builder, "skx");
3174 defineCPUMacros(Builder, "knl");
3177 Builder.defineMacro("__k6_2__");
3178 Builder.defineMacro("__tune_k6_2__");
3181 if (CPU != CK_K6_2) { // In case of fallthrough
3182 // FIXME: GCC may be enabling these in cases where some other k6
3183 // architecture is specified but -m3dnow is explicitly provided. The
3184 // exact semantics need to be determined and emulated here.
3185 Builder.defineMacro("__k6_3__");
3186 Builder.defineMacro("__tune_k6_3__");
3190 defineCPUMacros(Builder, "k6");
3193 case CK_AthlonThunderbird:
3197 defineCPUMacros(Builder, "athlon");
3198 if (SSELevel != NoSSE) {
3199 Builder.defineMacro("__athlon_sse__");
3200 Builder.defineMacro("__tune_athlon_sse__");
3207 case CK_OpteronSSE3:
3209 case CK_Athlon64SSE3:
3211 defineCPUMacros(Builder, "k8");
3214 defineCPUMacros(Builder, "amdfam10");
3217 defineCPUMacros(Builder, "btver1");
3220 defineCPUMacros(Builder, "btver2");
3223 defineCPUMacros(Builder, "bdver1");
3226 defineCPUMacros(Builder, "bdver2");
3229 defineCPUMacros(Builder, "bdver3");
3232 defineCPUMacros(Builder, "bdver4");
3235 defineCPUMacros(Builder, "geode");
3239 // Target properties.
3240 Builder.defineMacro("__REGISTER_PREFIX__", "");
3242 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3243 // functions in glibc header files that use FP Stack inline asm which the
3244 // backend can't deal with (PR879).
3245 Builder.defineMacro("__NO_MATH_INLINES");
3248 Builder.defineMacro("__AES__");
3251 Builder.defineMacro("__PCLMUL__");
3254 Builder.defineMacro("__LZCNT__");
3257 Builder.defineMacro("__RDRND__");
3260 Builder.defineMacro("__FSGSBASE__");
3263 Builder.defineMacro("__BMI__");
3266 Builder.defineMacro("__BMI2__");
3269 Builder.defineMacro("__POPCNT__");
3272 Builder.defineMacro("__RTM__");
3275 Builder.defineMacro("__PRFCHW__");
3278 Builder.defineMacro("__RDSEED__");
3281 Builder.defineMacro("__ADX__");
3284 Builder.defineMacro("__TBM__");
3288 Builder.defineMacro("__XOP__");
3290 Builder.defineMacro("__FMA4__");
3292 Builder.defineMacro("__SSE4A__");
3298 Builder.defineMacro("__FMA__");
3301 Builder.defineMacro("__F16C__");
3304 Builder.defineMacro("__AVX512CD__");
3306 Builder.defineMacro("__AVX512ER__");
3308 Builder.defineMacro("__AVX512PF__");
3310 Builder.defineMacro("__AVX512DQ__");
3312 Builder.defineMacro("__AVX512BW__");
3314 Builder.defineMacro("__AVX512VL__");
3317 Builder.defineMacro("__SHA__");
3320 Builder.defineMacro("__FXSR__");
3322 Builder.defineMacro("__XSAVE__");
3324 Builder.defineMacro("__XSAVEOPT__");
3326 Builder.defineMacro("__XSAVEC__");
3328 Builder.defineMacro("__XSAVES__");
3330 Builder.defineMacro("__PKU__");
3332 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3334 // Each case falls through to the previous one here.
3337 Builder.defineMacro("__AVX512F__");
3339 Builder.defineMacro("__AVX2__");
3341 Builder.defineMacro("__AVX__");
3343 Builder.defineMacro("__SSE4_2__");
3345 Builder.defineMacro("__SSE4_1__");
3347 Builder.defineMacro("__SSSE3__");
3349 Builder.defineMacro("__SSE3__");
3351 Builder.defineMacro("__SSE2__");
3352 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
3354 Builder.defineMacro("__SSE__");
3355 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
3360 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3370 Builder.defineMacro("_M_IX86_FP", Twine(2));
3373 Builder.defineMacro("_M_IX86_FP", Twine(1));
3376 Builder.defineMacro("_M_IX86_FP", Twine(0));
3380 // Each case falls through to the previous one here.
3381 switch (MMX3DNowLevel) {
3382 case AMD3DNowAthlon:
3383 Builder.defineMacro("__3dNOW_A__");
3385 Builder.defineMacro("__3dNOW__");
3387 Builder.defineMacro("__MMX__");
3392 if (CPU >= CK_i486) {
3393 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3394 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3395 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3398 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3401 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3402 return llvm::StringSwitch<bool>(Feature)
3403 .Case("aes", HasAES)
3404 .Case("avx", SSELevel >= AVX)
3405 .Case("avx2", SSELevel >= AVX2)
3406 .Case("avx512f", SSELevel >= AVX512F)
3407 .Case("avx512cd", HasAVX512CD)
3408 .Case("avx512er", HasAVX512ER)
3409 .Case("avx512pf", HasAVX512PF)
3410 .Case("avx512dq", HasAVX512DQ)
3411 .Case("avx512bw", HasAVX512BW)
3412 .Case("avx512vl", HasAVX512VL)
3413 .Case("bmi", HasBMI)
3414 .Case("bmi2", HasBMI2)
3415 .Case("cx16", HasCX16)
3416 .Case("f16c", HasF16C)
3417 .Case("fma", HasFMA)
3418 .Case("fma4", XOPLevel >= FMA4)
3419 .Case("fsgsbase", HasFSGSBASE)
3420 .Case("fxsr", HasFXSR)
3421 .Case("lzcnt", HasLZCNT)
3422 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3423 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3424 .Case("mmx", MMX3DNowLevel >= MMX)
3425 .Case("pclmul", HasPCLMUL)
3426 .Case("popcnt", HasPOPCNT)
3427 .Case("prfchw", HasPRFCHW)
3428 .Case("rdrnd", HasRDRND)
3429 .Case("rdseed", HasRDSEED)
3430 .Case("rtm", HasRTM)
3431 .Case("sha", HasSHA)
3432 .Case("sse", SSELevel >= SSE1)
3433 .Case("sse2", SSELevel >= SSE2)
3434 .Case("sse3", SSELevel >= SSE3)
3435 .Case("ssse3", SSELevel >= SSSE3)
3436 .Case("sse4.1", SSELevel >= SSE41)
3437 .Case("sse4.2", SSELevel >= SSE42)
3438 .Case("sse4a", XOPLevel >= SSE4A)
3439 .Case("tbm", HasTBM)
3441 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3442 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3443 .Case("xop", XOPLevel >= XOP)
3444 .Case("xsave", HasXSAVE)
3445 .Case("xsavec", HasXSAVEC)
3446 .Case("xsaves", HasXSAVES)
3447 .Case("xsaveopt", HasXSAVEOPT)
3448 .Case("pku", HasPKU)
3452 // We can't use a generic validation scheme for the features accepted here
3453 // versus subtarget features accepted in the target attribute because the
3454 // bitfield structure that's initialized in the runtime only supports the
3455 // below currently rather than the full range of subtarget features. (See
3456 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
3457 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
3458 return llvm::StringSwitch<bool>(FeatureStr)
3461 .Case("popcnt", true)
3465 .Case("sse4.1", true)
3466 .Case("sse4.2", true)
3469 .Case("sse4a", true)
3473 .Case("avx512f", true)
3480 X86TargetInfo::validateAsmConstraint(const char *&Name,
3481 TargetInfo::ConstraintInfo &Info) const {
3483 default: return false;
3484 // Constant constraints.
3485 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
3487 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3488 // x86_64 instructions.
3490 Info.setRequiresImmediate();
3493 Info.setRequiresImmediate(0, 31);
3496 Info.setRequiresImmediate(0, 63);
3499 Info.setRequiresImmediate(-128, 127);
3502 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) });
3505 Info.setRequiresImmediate(0, 3);
3508 Info.setRequiresImmediate(0, 255);
3511 Info.setRequiresImmediate(0, 127);
3513 // Register constraints.
3514 case 'Y': // 'Y' is the first character for several 2-character constraints.
3515 // Shift the pointer to the second character of the constraint.
3520 case '0': // First SSE register.
3521 case 't': // Any SSE register, when SSE2 is enabled.
3522 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
3523 case 'm': // Any MMX register, when inter-unit moves enabled.
3524 Info.setAllowsRegister();
3527 case 'f': // Any x87 floating point stack register.
3528 // Constraint 'f' cannot be used for output operands.
3529 if (Info.ConstraintStr[0] == '=')
3531 Info.setAllowsRegister();
3539 case 'A': // edx:eax.
3540 case 't': // Top of floating point stack.
3541 case 'u': // Second from top of floating point stack.
3542 case 'q': // Any register accessible as [r]l: a, b, c, and d.
3543 case 'y': // Any MMX register.
3544 case 'x': // Any SSE register.
3545 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3546 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3547 case 'l': // "Index" registers: any general register that can be used as an
3548 // index in a base+index memory access.
3549 Info.setAllowsRegister();
3551 // Floating point constant constraints.
3552 case 'C': // SSE floating point constant.
3553 case 'G': // x87 floating point constant.
3558 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3559 unsigned Size) const {
3560 // Strip off constraint modifiers.
3561 while (Constraint[0] == '=' ||
3562 Constraint[0] == '+' ||
3563 Constraint[0] == '&')
3564 Constraint = Constraint.substr(1);
3566 return validateOperandSize(Constraint, Size);
3569 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3570 unsigned Size) const {
3571 return validateOperandSize(Constraint, Size);
3574 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3575 unsigned Size) const {
3576 switch (Constraint[0]) {
3585 if (SSELevel >= AVX512F)
3586 // 512-bit zmm registers can be used if target supports AVX512F.
3587 return Size <= 512U;
3588 else if (SSELevel >= AVX)
3589 // 256-bit ymm registers can be used if target supports AVX.
3590 return Size <= 256U;
3591 return Size <= 128U;
3593 // 'Y' is the first character for several 2-character constraints.
3594 switch (Constraint[1]) {
3597 // 'Ym' is synonymous with 'y'.
3601 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
3602 if (SSELevel >= AVX512F)
3603 return Size <= 512U;
3604 else if (SSELevel >= AVX)
3605 return Size <= 256U;
3606 return SSELevel >= SSE2 && Size <= 128U;
3615 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3616 switch (*Constraint) {
3617 case 'a': return std::string("{ax}");
3618 case 'b': return std::string("{bx}");
3619 case 'c': return std::string("{cx}");
3620 case 'd': return std::string("{dx}");
3621 case 'S': return std::string("{si}");
3622 case 'D': return std::string("{di}");
3623 case 'p': // address
3624 return std::string("im");
3625 case 't': // top of floating point stack.
3626 return std::string("{st}");
3627 case 'u': // second from top of floating point stack.
3628 return std::string("{st(1)}"); // second from top of floating point stack.
3630 return std::string(1, *Constraint);
3634 // X86-32 generic target
3635 class X86_32TargetInfo : public X86TargetInfo {
3637 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3638 DoubleAlign = LongLongAlign = 32;
3639 LongDoubleWidth = 96;
3640 LongDoubleAlign = 32;
3641 SuitableAlign = 128;
3642 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3643 SizeType = UnsignedInt;
3644 PtrDiffType = SignedInt;
3645 IntPtrType = SignedInt;
3648 // Use fpret for all types.
3649 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3650 (1 << TargetInfo::Double) |
3651 (1 << TargetInfo::LongDouble));
3653 // x86-32 has atomics up to 8 bytes
3654 // FIXME: Check that we actually have cmpxchg8b before setting
3655 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3656 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3658 BuiltinVaListKind getBuiltinVaListKind() const override {
3659 return TargetInfo::CharPtrBuiltinVaList;
3662 int getEHDataRegisterNumber(unsigned RegNo) const override {
3663 if (RegNo == 0) return 0;
3664 if (RegNo == 1) return 2;
3667 bool validateOperandSize(StringRef Constraint,
3668 unsigned Size) const override {
3669 switch (Constraint[0]) {
3685 return X86TargetInfo::validateOperandSize(Constraint, Size);
3689 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3691 NetBSDI386TargetInfo(const llvm::Triple &Triple)
3692 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3694 unsigned getFloatEvalMethod() const override {
3695 unsigned Major, Minor, Micro;
3696 getTriple().getOSVersion(Major, Minor, Micro);
3697 // New NetBSD uses the default rounding mode.
3698 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3699 return X86_32TargetInfo::getFloatEvalMethod();
3700 // NetBSD before 6.99.26 defaults to "double" rounding.
3705 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3707 OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3708 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3709 SizeType = UnsignedLong;
3710 IntPtrType = SignedLong;
3711 PtrDiffType = SignedLong;
3715 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3717 BitrigI386TargetInfo(const llvm::Triple &Triple)
3718 : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3719 SizeType = UnsignedLong;
3720 IntPtrType = SignedLong;
3721 PtrDiffType = SignedLong;
3725 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3727 DarwinI386TargetInfo(const llvm::Triple &Triple)
3728 : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3729 LongDoubleWidth = 128;
3730 LongDoubleAlign = 128;
3731 SuitableAlign = 128;
3732 MaxVectorAlign = 256;
3733 // The watchOS simulator uses the builtin bool type for Objective-C.
3734 llvm::Triple T = llvm::Triple(Triple);
3736 UseSignedCharForObjCBool = false;
3737 SizeType = UnsignedLong;
3738 IntPtrType = SignedLong;
3739 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3740 HasAlignMac68kSupport = true;
3743 bool handleTargetFeatures(std::vector<std::string> &Features,
3744 DiagnosticsEngine &Diags) override {
3745 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features,
3748 // We now know the features we have: we can decide how to align vectors.
3750 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3755 // x86-32 Windows target
3756 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3758 WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3759 : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3760 WCharType = UnsignedShort;
3761 DoubleAlign = LongLongAlign = 64;
3763 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3764 DataLayoutString = IsWinCOFF
3765 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
3766 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3768 void getTargetDefines(const LangOptions &Opts,
3769 MacroBuilder &Builder) const override {
3770 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3774 // x86-32 Windows Visual Studio target
3775 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3777 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3778 : WindowsX86_32TargetInfo(Triple) {
3779 LongDoubleWidth = LongDoubleAlign = 64;
3780 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3782 void getTargetDefines(const LangOptions &Opts,
3783 MacroBuilder &Builder) const override {
3784 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3785 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3786 // The value of the following reflects processor type.
3787 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3788 // We lost the original triple, so we use the default.
3789 Builder.defineMacro("_M_IX86", "600");
3793 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3794 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang
3795 // supports __declspec natively under -fms-extensions, but we define a no-op
3796 // __declspec macro anyway for pre-processor compatibility.
3797 if (Opts.MicrosoftExt)
3798 Builder.defineMacro("__declspec", "__declspec");
3800 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3802 if (!Opts.MicrosoftExt) {
3803 // Provide macros for all the calling convention keywords. Provide both
3804 // single and double underscore prefixed variants. These are available on
3805 // x64 as well as x86, even though they have no effect.
3806 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3807 for (const char *CC : CCs) {
3808 std::string GCCSpelling = "__attribute__((__";
3810 GCCSpelling += "__))";
3811 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3812 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3817 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3818 Builder.defineMacro("__MSVCRT__");
3819 Builder.defineMacro("__MINGW32__");
3820 addCygMingDefines(Opts, Builder);
3823 // x86-32 MinGW target
3824 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3826 MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3827 : WindowsX86_32TargetInfo(Triple) {}
3828 void getTargetDefines(const LangOptions &Opts,
3829 MacroBuilder &Builder) const override {
3830 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3831 DefineStd(Builder, "WIN32", Opts);
3832 DefineStd(Builder, "WINNT", Opts);
3833 Builder.defineMacro("_X86_");
3834 addMinGWDefines(Opts, Builder);
3838 // x86-32 Cygwin target
3839 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3841 CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3842 : X86_32TargetInfo(Triple) {
3843 WCharType = UnsignedShort;
3844 DoubleAlign = LongLongAlign = 64;
3845 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3847 void getTargetDefines(const LangOptions &Opts,
3848 MacroBuilder &Builder) const override {
3849 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3850 Builder.defineMacro("_X86_");
3851 Builder.defineMacro("__CYGWIN__");
3852 Builder.defineMacro("__CYGWIN32__");
3853 addCygMingDefines(Opts, Builder);
3854 DefineStd(Builder, "unix", Opts);
3856 Builder.defineMacro("_GNU_SOURCE");
3860 // x86-32 Haiku target
3861 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3863 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3864 SizeType = UnsignedLong;
3865 IntPtrType = SignedLong;
3866 PtrDiffType = SignedLong;
3867 ProcessIDType = SignedLong;
3868 this->UserLabelPrefix = "";
3869 this->TLSSupported = false;
3871 void getTargetDefines(const LangOptions &Opts,
3872 MacroBuilder &Builder) const override {
3873 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3874 Builder.defineMacro("__INTEL__");
3875 Builder.defineMacro("__HAIKU__");
3879 // X86-32 MCU target
3880 class MCUX86_32TargetInfo : public X86_32TargetInfo {
3882 MCUX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3883 LongDoubleWidth = 64;
3884 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3887 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3888 // On MCU we support only C calling convention.
3889 return CC == CC_C ? CCCR_OK : CCCR_Warning;
3892 void getTargetDefines(const LangOptions &Opts,
3893 MacroBuilder &Builder) const override {
3894 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3895 Builder.defineMacro("__iamcu");
3896 Builder.defineMacro("__iamcu__");
3901 template<typename Target>
3902 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3904 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3905 MacroBuilder &Builder) const override {
3906 // RTEMS defines; list based off of gcc output
3908 Builder.defineMacro("__rtems__");
3909 Builder.defineMacro("__ELF__");
3913 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3914 this->UserLabelPrefix = "";
3916 switch (Triple.getArch()) {
3918 case llvm::Triple::x86:
3919 // this->MCountName = ".mcount";
3921 case llvm::Triple::mips:
3922 case llvm::Triple::mipsel:
3923 case llvm::Triple::ppc:
3924 case llvm::Triple::ppc64:
3925 case llvm::Triple::ppc64le:
3926 // this->MCountName = "_mcount";
3928 case llvm::Triple::arm:
3929 // this->MCountName = "__mcount";
3935 // x86-32 RTEMS target
3936 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3938 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3939 SizeType = UnsignedLong;
3940 IntPtrType = SignedLong;
3941 PtrDiffType = SignedLong;
3942 this->UserLabelPrefix = "";
3944 void getTargetDefines(const LangOptions &Opts,
3945 MacroBuilder &Builder) const override {
3946 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3947 Builder.defineMacro("__INTEL__");
3948 Builder.defineMacro("__rtems__");
3952 // x86-64 generic target
3953 class X86_64TargetInfo : public X86TargetInfo {
3955 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3956 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3958 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3959 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3960 LongDoubleWidth = 128;
3961 LongDoubleAlign = 128;
3962 LargeArrayMinWidth = 128;
3963 LargeArrayAlign = 128;
3964 SuitableAlign = 128;
3965 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
3966 PtrDiffType = IsX32 ? SignedInt : SignedLong;
3967 IntPtrType = IsX32 ? SignedInt : SignedLong;
3968 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
3969 Int64Type = IsX32 ? SignedLongLong : SignedLong;
3972 // Pointers are 32-bit in x32.
3973 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3975 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
3976 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3978 // Use fpret only for long double.
3979 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3981 // Use fp2ret for _Complex long double.
3982 ComplexLongDoubleUsesFP2Ret = true;
3984 // Make __builtin_ms_va_list available.
3985 HasBuiltinMSVaList = true;
3987 // x86-64 has atomics up to 16 bytes.
3988 MaxAtomicPromoteWidth = 128;
3989 MaxAtomicInlineWidth = 128;
3991 BuiltinVaListKind getBuiltinVaListKind() const override {
3992 return TargetInfo::X86_64ABIBuiltinVaList;
3995 int getEHDataRegisterNumber(unsigned RegNo) const override {
3996 if (RegNo == 0) return 0;
3997 if (RegNo == 1) return 1;
4001 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4002 return (CC == CC_C ||
4003 CC == CC_X86VectorCall ||
4004 CC == CC_IntelOclBicc ||
4005 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
4008 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
4012 // for x32 we need it here explicitly
4013 bool hasInt128Type() const override { return true; }
4015 bool validateGlobalRegisterVariable(StringRef RegName,
4017 bool &HasSizeMismatch) const override {
4018 // rsp and rbp are the only 64-bit registers the x86 backend can currently
4020 if (RegName.equals("rsp") || RegName.equals("rbp")) {
4021 // Check that the register size is 64-bit.
4022 HasSizeMismatch = RegSize != 64;
4026 // Check if the register is a 32-bit register the backend can handle.
4027 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize,
4032 // x86-64 Windows target
4033 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
4035 WindowsX86_64TargetInfo(const llvm::Triple &Triple)
4036 : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
4037 WCharType = UnsignedShort;
4038 LongWidth = LongAlign = 32;
4039 DoubleAlign = LongLongAlign = 64;
4040 IntMaxType = SignedLongLong;
4041 Int64Type = SignedLongLong;
4042 SizeType = UnsignedLongLong;
4043 PtrDiffType = SignedLongLong;
4044 IntPtrType = SignedLongLong;
4045 this->UserLabelPrefix = "";
4048 void getTargetDefines(const LangOptions &Opts,
4049 MacroBuilder &Builder) const override {
4050 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
4051 Builder.defineMacro("_WIN64");
4054 BuiltinVaListKind getBuiltinVaListKind() const override {
4055 return TargetInfo::CharPtrBuiltinVaList;
4058 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4061 case CC_X86ThisCall:
4062 case CC_X86FastCall:
4065 case CC_X86VectorCall:
4066 case CC_IntelOclBicc:
4070 return CCCR_Warning;
4075 // x86-64 Windows Visual Studio target
4076 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
4078 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
4079 : WindowsX86_64TargetInfo(Triple) {
4080 LongDoubleWidth = LongDoubleAlign = 64;
4081 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4083 void getTargetDefines(const LangOptions &Opts,
4084 MacroBuilder &Builder) const override {
4085 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4086 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
4087 Builder.defineMacro("_M_X64", "100");
4088 Builder.defineMacro("_M_AMD64", "100");
4092 // x86-64 MinGW target
4093 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
4095 MinGWX86_64TargetInfo(const llvm::Triple &Triple)
4096 : WindowsX86_64TargetInfo(Triple) {
4097 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
4098 // with x86 FP ops. Weird.
4099 LongDoubleWidth = LongDoubleAlign = 128;
4100 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
4103 void getTargetDefines(const LangOptions &Opts,
4104 MacroBuilder &Builder) const override {
4105 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4106 DefineStd(Builder, "WIN64", Opts);
4107 Builder.defineMacro("__MINGW64__");
4108 addMinGWDefines(Opts, Builder);
4110 // GCC defines this macro when it is using __gxx_personality_seh0.
4111 if (!Opts.SjLjExceptions)
4112 Builder.defineMacro("__SEH__");
4116 // x86-64 Cygwin target
4117 class CygwinX86_64TargetInfo : public X86_64TargetInfo {
4119 CygwinX86_64TargetInfo(const llvm::Triple &Triple)
4120 : X86_64TargetInfo(Triple) {
4121 TLSSupported = false;
4122 WCharType = UnsignedShort;
4124 void getTargetDefines(const LangOptions &Opts,
4125 MacroBuilder &Builder) const override {
4126 X86_64TargetInfo::getTargetDefines(Opts, Builder);
4127 Builder.defineMacro("__x86_64__");
4128 Builder.defineMacro("__CYGWIN__");
4129 Builder.defineMacro("__CYGWIN64__");
4130 addCygMingDefines(Opts, Builder);
4131 DefineStd(Builder, "unix", Opts);
4133 Builder.defineMacro("_GNU_SOURCE");
4135 // GCC defines this macro when it is using __gxx_personality_seh0.
4136 if (!Opts.SjLjExceptions)
4137 Builder.defineMacro("__SEH__");
4141 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
4143 DarwinX86_64TargetInfo(const llvm::Triple &Triple)
4144 : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
4145 Int64Type = SignedLongLong;
4146 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
4147 llvm::Triple T = llvm::Triple(Triple);
4149 UseSignedCharForObjCBool = false;
4150 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
4153 bool handleTargetFeatures(std::vector<std::string> &Features,
4154 DiagnosticsEngine &Diags) override {
4155 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features,
4158 // We now know the features we have: we can decide how to align vectors.
4160 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4165 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
4167 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
4168 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
4169 IntMaxType = SignedLongLong;
4170 Int64Type = SignedLongLong;
4174 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
4176 BitrigX86_64TargetInfo(const llvm::Triple &Triple)
4177 : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
4178 IntMaxType = SignedLongLong;
4179 Int64Type = SignedLongLong;
4183 class ARMTargetInfo : public TargetInfo {
4184 // Possible FPU choices.
4193 // Possible HWDiv features.
4195 HWDivThumb = (1 << 0),
4199 static bool FPUModeIsVFP(FPUMode Mode) {
4200 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
4203 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4204 static const char * const GCCRegNames[];
4206 std::string ABI, CPU;
4208 StringRef CPUProfile;
4218 unsigned ArchKind = llvm::ARM::AK_ARMV4T;
4219 unsigned ArchProfile;
4220 unsigned ArchVersion;
4224 unsigned IsAAPCS : 1;
4227 // Initialized via features.
4228 unsigned SoftFloat : 1;
4229 unsigned SoftFloatABI : 1;
4232 unsigned Crypto : 1;
4234 unsigned Unaligned : 1;
4237 LDREX_B = (1 << 0), /// byte (8-bit)
4238 LDREX_H = (1 << 1), /// half (16-bit)
4239 LDREX_W = (1 << 2), /// word (32-bit)
4240 LDREX_D = (1 << 3), /// double (64-bit)
4245 // ACLE 6.5.1 Hardware floating point
4247 HW_FP_HP = (1 << 1), /// half (16-bit)
4248 HW_FP_SP = (1 << 2), /// single (32-bit)
4249 HW_FP_DP = (1 << 3), /// double (64-bit)
4253 static const Builtin::Info BuiltinInfo[];
4255 void setABIAAPCS() {
4258 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4259 const llvm::Triple &T = getTriple();
4261 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig.
4262 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
4263 T.getOS() == llvm::Triple::Bitrig)
4264 SizeType = UnsignedLong;
4266 SizeType = UnsignedInt;
4268 switch (T.getOS()) {
4269 case llvm::Triple::NetBSD:
4270 WCharType = SignedInt;
4272 case llvm::Triple::Win32:
4273 WCharType = UnsignedShort;
4275 case llvm::Triple::Linux:
4277 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
4278 WCharType = UnsignedInt;
4282 UseBitFieldTypeAlignment = true;
4284 ZeroLengthBitfieldBoundary = 0;
4286 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
4287 // so set preferred for small types to 32.
4288 if (T.isOSBinFormatMachO()) {
4290 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4291 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4292 } else if (T.isOSWindows()) {
4293 assert(!BigEndian && "Windows on ARM does not support big endian");
4294 DataLayoutString = "e"
4302 } else if (T.isOSNaCl()) {
4303 assert(!BigEndian && "NaCl on ARM does not support big endian");
4304 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
4307 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4308 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4311 // FIXME: Enumerated types are variable width in straight AAPCS.
4314 void setABIAPCS(bool IsAAPCS16) {
4315 const llvm::Triple &T = getTriple();
4320 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4322 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
4324 // size_t is unsigned int on FreeBSD.
4325 if (T.getOS() == llvm::Triple::FreeBSD)
4326 SizeType = UnsignedInt;
4328 SizeType = UnsignedLong;
4330 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
4331 WCharType = SignedInt;
4333 // Do not respect the alignment of bit-field types when laying out
4334 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
4335 UseBitFieldTypeAlignment = false;
4337 /// gcc forces the alignment to 4 bytes, regardless of the type of the
4338 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
4340 ZeroLengthBitfieldBoundary = 32;
4342 if (T.isOSBinFormatMachO() && IsAAPCS16) {
4343 assert(!BigEndian && "AAPCS16 does not support big-endian");
4344 DataLayoutString = "e-m:o-p:32:32-i64:64-a:0:32-n32-S128";
4345 } else if (T.isOSBinFormatMachO())
4348 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4349 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4353 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4354 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4356 // FIXME: Override "preferred align" for double and long long.
4359 void setArchInfo() {
4360 StringRef ArchName = getTriple().getArchName();
4362 ArchISA = llvm::ARM::parseArchISA(ArchName);
4363 CPU = llvm::ARM::getDefaultCPU(ArchName);
4364 unsigned AK = llvm::ARM::parseArch(ArchName);
4365 if (AK != llvm::ARM::AK_INVALID)
4367 setArchInfo(ArchKind);
4370 void setArchInfo(unsigned Kind) {
4373 // cache TargetParser info
4375 SubArch = llvm::ARM::getSubArch(ArchKind);
4376 ArchProfile = llvm::ARM::parseArchProfile(SubArch);
4377 ArchVersion = llvm::ARM::parseArchVersion(SubArch);
4379 // cache CPU related strings
4380 CPUAttr = getCPUAttr();
4381 CPUProfile = getCPUProfile();
4385 // when triple does not specify a sub arch,
4386 // then we are not using inline atomics
4387 bool ShouldUseInlineAtomic =
4388 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) ||
4389 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
4390 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4391 if (ArchProfile == llvm::ARM::PK_M) {
4392 MaxAtomicPromoteWidth = 32;
4393 if (ShouldUseInlineAtomic)
4394 MaxAtomicInlineWidth = 32;
4397 MaxAtomicPromoteWidth = 64;
4398 if (ShouldUseInlineAtomic)
4399 MaxAtomicInlineWidth = 64;
4403 bool isThumb() const {
4404 return (ArchISA == llvm::ARM::IK_THUMB);
4407 bool supportsThumb() const {
4408 return CPUAttr.count('T') || ArchVersion >= 6;
4411 bool supportsThumb2() const {
4412 return CPUAttr.equals("6T2") || ArchVersion >= 7;
4415 StringRef getCPUAttr() const {
4416 // For most sub-arches, the build attribute CPU name is enough.
4417 // For Cortex variants, it's slightly different.
4420 return llvm::ARM::getCPUAttr(ArchKind);
4421 case llvm::ARM::AK_ARMV6M:
4423 case llvm::ARM::AK_ARMV7S:
4425 case llvm::ARM::AK_ARMV7A:
4427 case llvm::ARM::AK_ARMV7R:
4429 case llvm::ARM::AK_ARMV7M:
4431 case llvm::ARM::AK_ARMV7EM:
4433 case llvm::ARM::AK_ARMV8A:
4435 case llvm::ARM::AK_ARMV8_1A:
4440 StringRef getCPUProfile() const {
4441 switch(ArchProfile) {
4442 case llvm::ARM::PK_A:
4444 case llvm::ARM::PK_R:
4446 case llvm::ARM::PK_M:
4454 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
4455 : TargetInfo(Triple), FPMath(FP_Default),
4456 IsAAPCS(true), LDREX(0), HW_FP(0) {
4457 BigEndian = IsBigEndian;
4459 switch (getTriple().getOS()) {
4460 case llvm::Triple::NetBSD:
4461 PtrDiffType = SignedLong;
4464 PtrDiffType = SignedInt;
4468 // Cache arch related info.
4471 // {} in inline assembly are neon specifiers, not assembly variant
4473 NoAsmVariants = true;
4475 // FIXME: This duplicates code from the driver that sets the -target-abi
4476 // option - this code is used if -target-abi isn't passed and should
4477 // be unified in some way.
4478 if (Triple.isOSBinFormatMachO()) {
4479 // The backend is hardwired to assume AAPCS for M-class processors, ensure
4480 // the frontend matches that.
4481 if (Triple.getEnvironment() == llvm::Triple::EABI ||
4482 Triple.getOS() == llvm::Triple::UnknownOS ||
4483 StringRef(CPU).startswith("cortex-m")) {
4485 } else if (Triple.isWatchOS()) {
4490 } else if (Triple.isOSWindows()) {
4491 // FIXME: this is invalid for WindowsCE
4494 // Select the default based on the platform.
4495 switch (Triple.getEnvironment()) {
4496 case llvm::Triple::Android:
4497 case llvm::Triple::GNUEABI:
4498 case llvm::Triple::GNUEABIHF:
4499 setABI("aapcs-linux");
4501 case llvm::Triple::EABIHF:
4502 case llvm::Triple::EABI:
4505 case llvm::Triple::GNU:
4509 if (Triple.getOS() == llvm::Triple::NetBSD)
4517 // ARM targets default to using the ARM C++ ABI.
4518 TheCXXABI.set(TargetCXXABI::GenericARM);
4520 // ARM has atomics up to 8 bytes
4523 // Do force alignment of members that follow zero length bitfields. If
4524 // the alignment of the zero-length bitfield is greater than the member
4525 // that follows it, `bar', `bar' will be aligned as the type of the
4526 // zero length bitfield.
4527 UseZeroLengthBitfieldAlignment = true;
4530 StringRef getABI() const override { return ABI; }
4532 bool setABI(const std::string &Name) override {
4535 // The defaults (above) are for AAPCS, check if we need to change them.
4537 // FIXME: We need support for -meabi... we could just mangle it into the
4539 if (Name == "apcs-gnu" || Name == "aapcs16") {
4540 setABIAPCS(Name == "aapcs16");
4543 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
4550 // FIXME: This should be based on Arch attributes, not CPU names.
4552 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
4554 const std::vector<std::string> &FeaturesVec) const override {
4556 std::vector<const char*> TargetFeatures;
4557 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName());
4559 // get default FPU features
4560 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
4561 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
4563 // get default Extension features
4564 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
4565 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
4567 for (const char *Feature : TargetFeatures)
4568 if (Feature[0] == '+')
4569 Features[Feature+1] = true;
4571 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
4574 bool handleTargetFeatures(std::vector<std::string> &Features,
4575 DiagnosticsEngine &Diags) override {
4581 SoftFloat = SoftFloatABI = false;
4584 // This does not diagnose illegal cases like having both
4585 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
4586 uint32_t HW_FP_remove = 0;
4587 for (const auto &Feature : Features) {
4588 if (Feature == "+soft-float") {
4590 } else if (Feature == "+soft-float-abi") {
4591 SoftFloatABI = true;
4592 } else if (Feature == "+vfp2") {
4594 HW_FP |= HW_FP_SP | HW_FP_DP;
4595 } else if (Feature == "+vfp3") {
4597 HW_FP |= HW_FP_SP | HW_FP_DP;
4598 } else if (Feature == "+vfp4") {
4600 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
4601 } else if (Feature == "+fp-armv8") {
4603 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
4604 } else if (Feature == "+neon") {
4606 HW_FP |= HW_FP_SP | HW_FP_DP;
4607 } else if (Feature == "+hwdiv") {
4608 HWDiv |= HWDivThumb;
4609 } else if (Feature == "+hwdiv-arm") {
4611 } else if (Feature == "+crc") {
4613 } else if (Feature == "+crypto") {
4615 } else if (Feature == "+dsp") {
4617 } else if (Feature == "+fp-only-sp") {
4618 HW_FP_remove |= HW_FP_DP;
4619 } else if (Feature == "+strict-align") {
4621 } else if (Feature == "+fp16") {
4625 HW_FP &= ~HW_FP_remove;
4627 switch (ArchVersion) {
4629 if (ArchProfile == llvm::ARM::PK_M)
4631 else if (ArchKind == llvm::ARM::AK_ARMV6K)
4632 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
4637 if (ArchProfile == llvm::ARM::PK_M)
4638 LDREX = LDREX_W | LDREX_H | LDREX_B ;
4640 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
4643 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
4646 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4647 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4651 if (FPMath == FP_Neon)
4652 Features.push_back("+neonfp");
4653 else if (FPMath == FP_VFP)
4654 Features.push_back("-neonfp");
4656 // Remove front-end specific options which the backend handles differently.
4658 std::find(Features.begin(), Features.end(), "+soft-float-abi");
4659 if (Feature != Features.end())
4660 Features.erase(Feature);
4665 bool hasFeature(StringRef Feature) const override {
4666 return llvm::StringSwitch<bool>(Feature)
4668 .Case("aarch32", true)
4669 .Case("softfloat", SoftFloat)
4670 .Case("thumb", isThumb())
4671 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4672 .Case("hwdiv", HWDiv & HWDivThumb)
4673 .Case("hwdiv-arm", HWDiv & HWDivARM)
4677 bool setCPU(const std::string &Name) override {
4678 if (Name != "generic")
4679 setArchInfo(llvm::ARM::parseCPUArch(Name));
4681 if (ArchKind == llvm::ARM::AK_INVALID)
4688 bool setFPMath(StringRef Name) override;
4690 void getTargetDefines(const LangOptions &Opts,
4691 MacroBuilder &Builder) const override {
4692 // Target identification.
4693 Builder.defineMacro("__arm");
4694 Builder.defineMacro("__arm__");
4696 // Target properties.
4697 Builder.defineMacro("__REGISTER_PREFIX__", "");
4699 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
4700 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
4701 if (getTriple().isWatchOS())
4702 Builder.defineMacro("__ARM_ARCH_7K__", "2");
4704 if (!CPUAttr.empty())
4705 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
4707 // ACLE 6.4.1 ARM/Thumb instruction set architecture
4708 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4709 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
4711 if (ArchVersion >= 8) {
4712 // ACLE 6.5.7 Crypto Extension
4714 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
4715 // ACLE 6.5.8 CRC32 Extension
4717 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
4718 // ACLE 6.5.10 Numeric Maximum and Minimum
4719 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
4720 // ACLE 6.5.9 Directed Rounding
4721 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
4724 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
4725 // is not defined for the M-profile.
4726 // NOTE that the deffault profile is assumed to be 'A'
4727 if (CPUProfile.empty() || CPUProfile != "M")
4728 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4730 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4731 // Thumb ISA (including v6-M). It is set to 2 if the core supports the
4732 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4733 if (supportsThumb2())
4734 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4735 else if (supportsThumb())
4736 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4738 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4739 // instruction set such as ARM or Thumb.
4740 Builder.defineMacro("__ARM_32BIT_STATE", "1");
4742 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4744 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4745 if (!CPUProfile.empty())
4746 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4748 // ACLE 6.4.3 Unaligned access supported in hardware
4750 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
4752 // ACLE 6.4.4 LDREX/STREX
4754 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX));
4757 if (ArchVersion == 5 ||
4758 (ArchVersion == 6 && CPUProfile != "M") ||
4760 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
4762 // ACLE 6.5.1 Hardware Floating Point
4764 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4767 Builder.defineMacro("__ARM_ACLE", "200");
4769 // FP16 support (we currently only support IEEE format).
4770 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
4771 Builder.defineMacro("__ARM_FP16_ARGS", "1");
4773 // ACLE 6.5.3 Fused multiply-accumulate (FMA)
4774 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM"))
4775 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
4777 // Subtarget options.
4779 // FIXME: It's more complicated than this and we don't really support
4781 // Windows on ARM does not "support" interworking
4782 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows())
4783 Builder.defineMacro("__THUMB_INTERWORK__");
4785 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4786 // Embedded targets on Darwin follow AAPCS, but not EABI.
4787 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4788 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4789 Builder.defineMacro("__ARM_EABI__");
4790 Builder.defineMacro("__ARM_PCS", "1");
4792 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4793 Builder.defineMacro("__ARM_PCS_VFP", "1");
4797 Builder.defineMacro("__SOFTFP__");
4799 if (CPU == "xscale")
4800 Builder.defineMacro("__XSCALE__");
4803 Builder.defineMacro("__THUMBEL__");
4804 Builder.defineMacro("__thumb__");
4805 if (supportsThumb2())
4806 Builder.defineMacro("__thumb2__");
4809 // ACLE 6.4.9 32-bit SIMD instructions
4810 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
4811 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
4813 // ACLE 6.4.10 Hardware Integer Divide
4814 if (((HWDiv & HWDivThumb) && isThumb()) ||
4815 ((HWDiv & HWDivARM) && !isThumb())) {
4816 Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
4817 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4820 // Note, this is always on in gcc, even though it doesn't make sense.
4821 Builder.defineMacro("__APCS_32__");
4823 if (FPUModeIsVFP((FPUMode) FPU)) {
4824 Builder.defineMacro("__VFP_FP__");
4826 Builder.defineMacro("__ARM_VFPV2__");
4828 Builder.defineMacro("__ARM_VFPV3__");
4830 Builder.defineMacro("__ARM_VFPV4__");
4833 // This only gets set when Neon instructions are actually available, unlike
4834 // the VFP define, hence the soft float and arch check. This is subtly
4835 // different from gcc, we follow the intent which was that it should be set
4836 // when Neon instructions are actually available.
4837 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
4838 Builder.defineMacro("__ARM_NEON", "1");
4839 Builder.defineMacro("__ARM_NEON__");
4840 // current AArch32 NEON implementations do not support double-precision
4841 // floating-point even when it is present in VFP.
4842 Builder.defineMacro("__ARM_NEON_FP",
4843 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP));
4846 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4847 Opts.ShortWChar ? "2" : "4");
4849 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4850 Opts.ShortEnums ? "1" : "4");
4852 if (ArchVersion >= 6 && CPUAttr != "6M") {
4853 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4854 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4855 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4856 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4859 // ACLE 6.4.7 DSP instructions
4861 Builder.defineMacro("__ARM_FEATURE_DSP", "1");
4864 // ACLE 6.4.8 Saturation instructions
4866 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) {
4867 Builder.defineMacro("__ARM_FEATURE_SAT", "1");
4871 // ACLE 6.4.6 Q (saturation) flag
4873 Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
4875 if (Opts.UnsafeFPMath)
4876 Builder.defineMacro("__ARM_FP_FAST", "1");
4878 if (ArchKind == llvm::ARM::AK_ARMV8_1A)
4879 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
4882 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4883 return llvm::makeArrayRef(BuiltinInfo,
4884 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin);
4886 bool isCLZForZeroUndef() const override { return false; }
4887 BuiltinVaListKind getBuiltinVaListKind() const override {
4889 ? AAPCSABIBuiltinVaList
4890 : (getTriple().isWatchOS() ? TargetInfo::CharPtrBuiltinVaList
4891 : TargetInfo::VoidPtrBuiltinVaList);
4893 ArrayRef<const char *> getGCCRegNames() const override;
4894 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
4895 bool validateAsmConstraint(const char *&Name,
4896 TargetInfo::ConstraintInfo &Info) const override {
4901 case 'w': // VFP Floating point register single precision
4902 case 'P': // VFP Floating point register double precision
4903 Info.setAllowsRegister();
4912 case 'Q': // A memory address that is a single base register.
4913 Info.setAllowsMemory();
4915 case 'U': // a memory reference...
4917 case 'q': // ...ARMV4 ldrsb
4918 case 'v': // ...VFP load/store (reg+constant offset)
4919 case 'y': // ...iWMMXt load/store
4920 case 't': // address valid for load/store opaque types wider
4922 case 'n': // valid address for Neon doubleword vector load/store
4923 case 'm': // valid address for Neon element and structure load/store
4924 case 's': // valid address for non-offset loads/stores of quad-word
4925 // values in four ARM registers
4926 Info.setAllowsMemory();
4933 std::string convertConstraint(const char *&Constraint) const override {
4935 switch (*Constraint) {
4936 case 'U': // Two-character constraint; add "^" hint for later parsing.
4937 R = std::string("^") + std::string(Constraint, 2);
4940 case 'p': // 'p' should be translated to 'r' by default.
4941 R = std::string("r");
4944 return std::string(1, *Constraint);
4949 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4950 std::string &SuggestedModifier) const override {
4951 bool isOutput = (Constraint[0] == '=');
4952 bool isInOut = (Constraint[0] == '+');
4954 // Strip off constraint modifiers.
4955 while (Constraint[0] == '=' ||
4956 Constraint[0] == '+' ||
4957 Constraint[0] == '&')
4958 Constraint = Constraint.substr(1);
4960 switch (Constraint[0]) {
4965 return (isInOut || isOutput || Size <= 64);
4967 // A register of size 32 cannot fit a vector type.
4975 const char *getClobbers() const override {
4976 // FIXME: Is this really right?
4980 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4981 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4984 int getEHDataRegisterNumber(unsigned RegNo) const override {
4985 if (RegNo == 0) return 0;
4986 if (RegNo == 1) return 1;
4990 bool hasSjLjLowering() const override {
4995 bool ARMTargetInfo::setFPMath(StringRef Name) {
4996 if (Name == "neon") {
4999 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
5007 const char * const ARMTargetInfo::GCCRegNames[] = {
5008 // Integer registers
5009 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5010 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
5013 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
5014 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
5015 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
5016 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5019 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
5020 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
5021 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
5022 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5025 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
5026 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
5029 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
5030 return llvm::makeArrayRef(GCCRegNames);
5033 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
5043 { { "v6", "rfp" }, "r9" },
5044 { { "sl" }, "r10" },
5045 { { "fp" }, "r11" },
5046 { { "ip" }, "r12" },
5047 { { "r13" }, "sp" },
5048 { { "r14" }, "lr" },
5049 { { "r15" }, "pc" },
5050 // The S, D and Q registers overlap, but aren't really aliases; we
5051 // don't want to substitute one of these for a different-sized one.
5054 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
5055 return llvm::makeArrayRef(GCCRegAliases);
5058 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
5059 #define BUILTIN(ID, TYPE, ATTRS) \
5060 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5061 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5062 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5063 #include "clang/Basic/BuiltinsNEON.def"
5065 #define BUILTIN(ID, TYPE, ATTRS) \
5066 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5067 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \
5068 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr },
5069 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5070 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5071 #include "clang/Basic/BuiltinsARM.def"
5074 class ARMleTargetInfo : public ARMTargetInfo {
5076 ARMleTargetInfo(const llvm::Triple &Triple)
5077 : ARMTargetInfo(Triple, false) { }
5078 void getTargetDefines(const LangOptions &Opts,
5079 MacroBuilder &Builder) const override {
5080 Builder.defineMacro("__ARMEL__");
5081 ARMTargetInfo::getTargetDefines(Opts, Builder);
5085 class ARMbeTargetInfo : public ARMTargetInfo {
5087 ARMbeTargetInfo(const llvm::Triple &Triple)
5088 : ARMTargetInfo(Triple, true) { }
5089 void getTargetDefines(const LangOptions &Opts,
5090 MacroBuilder &Builder) const override {
5091 Builder.defineMacro("__ARMEB__");
5092 Builder.defineMacro("__ARM_BIG_ENDIAN");
5093 ARMTargetInfo::getTargetDefines(Opts, Builder);
5097 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
5098 const llvm::Triple Triple;
5100 WindowsARMTargetInfo(const llvm::Triple &Triple)
5101 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
5102 TLSSupported = false;
5103 WCharType = UnsignedShort;
5104 SizeType = UnsignedInt;
5105 UserLabelPrefix = "";
5107 void getVisualStudioDefines(const LangOptions &Opts,
5108 MacroBuilder &Builder) const {
5109 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
5111 // FIXME: this is invalid for WindowsCE
5112 Builder.defineMacro("_M_ARM_NT", "1");
5113 Builder.defineMacro("_M_ARMT", "_M_ARM");
5114 Builder.defineMacro("_M_THUMB", "_M_ARM");
5116 assert((Triple.getArch() == llvm::Triple::arm ||
5117 Triple.getArch() == llvm::Triple::thumb) &&
5118 "invalid architecture for Windows ARM target info");
5119 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
5120 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
5122 // TODO map the complete set of values
5123 // 31: VFPv3 40: VFPv4
5124 Builder.defineMacro("_M_ARM_FP", "31");
5126 BuiltinVaListKind getBuiltinVaListKind() const override {
5127 return TargetInfo::CharPtrBuiltinVaList;
5129 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5132 case CC_X86ThisCall:
5133 case CC_X86FastCall:
5134 case CC_X86VectorCall:
5139 return CCCR_Warning;
5144 // Windows ARM + Itanium C++ ABI Target
5145 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
5147 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
5148 : WindowsARMTargetInfo(Triple) {
5149 TheCXXABI.set(TargetCXXABI::GenericARM);
5152 void getTargetDefines(const LangOptions &Opts,
5153 MacroBuilder &Builder) const override {
5154 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5156 if (Opts.MSVCCompat)
5157 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5161 // Windows ARM, MS (C++) ABI
5162 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
5164 MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
5165 : WindowsARMTargetInfo(Triple) {
5166 TheCXXABI.set(TargetCXXABI::Microsoft);
5169 void getTargetDefines(const LangOptions &Opts,
5170 MacroBuilder &Builder) const override {
5171 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5172 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5177 class MinGWARMTargetInfo : public WindowsARMTargetInfo {
5179 MinGWARMTargetInfo(const llvm::Triple &Triple)
5180 : WindowsARMTargetInfo(Triple) {
5181 TheCXXABI.set(TargetCXXABI::GenericARM);
5184 void getTargetDefines(const LangOptions &Opts,
5185 MacroBuilder &Builder) const override {
5186 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5187 DefineStd(Builder, "WIN32", Opts);
5188 DefineStd(Builder, "WINNT", Opts);
5189 Builder.defineMacro("_ARM_");
5190 addMinGWDefines(Opts, Builder);
5194 // ARM Cygwin target
5195 class CygwinARMTargetInfo : public ARMleTargetInfo {
5197 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) {
5198 TLSSupported = false;
5199 WCharType = UnsignedShort;
5200 DoubleAlign = LongLongAlign = 64;
5201 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
5203 void getTargetDefines(const LangOptions &Opts,
5204 MacroBuilder &Builder) const override {
5205 ARMleTargetInfo::getTargetDefines(Opts, Builder);
5206 Builder.defineMacro("_ARM_");
5207 Builder.defineMacro("__CYGWIN__");
5208 Builder.defineMacro("__CYGWIN32__");
5209 DefineStd(Builder, "unix", Opts);
5211 Builder.defineMacro("_GNU_SOURCE");
5215 class DarwinARMTargetInfo :
5216 public DarwinTargetInfo<ARMleTargetInfo> {
5218 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5219 MacroBuilder &Builder) const override {
5220 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5224 DarwinARMTargetInfo(const llvm::Triple &Triple)
5225 : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
5226 HasAlignMac68kSupport = true;
5227 // iOS always has 64-bit atomic instructions.
5228 // FIXME: This should be based off of the target features in
5230 MaxAtomicInlineWidth = 64;
5232 if (Triple.isWatchOS()) {
5233 // Darwin on iOS uses a variant of the ARM C++ ABI.
5234 TheCXXABI.set(TargetCXXABI::WatchOS);
5236 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that
5237 // size_t is long, it's a bit weird for it to be int.
5238 PtrDiffType = SignedLong;
5240 // BOOL should be a real boolean on the new ABI
5241 UseSignedCharForObjCBool = false;
5243 TheCXXABI.set(TargetCXXABI::iOS);
5247 class AArch64TargetInfo : public TargetInfo {
5248 virtual void setDataLayoutString() = 0;
5249 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5250 static const char *const GCCRegNames[];
5263 static const Builtin::Info BuiltinInfo[];
5268 AArch64TargetInfo(const llvm::Triple &Triple)
5269 : TargetInfo(Triple), ABI("aapcs") {
5271 if (getTriple().getOS() == llvm::Triple::NetBSD) {
5272 WCharType = SignedInt;
5274 // NetBSD apparently prefers consistency across ARM targets to consistency
5275 // across 64-bit targets.
5276 Int64Type = SignedLongLong;
5277 IntMaxType = SignedLongLong;
5279 WCharType = UnsignedInt;
5280 Int64Type = SignedLong;
5281 IntMaxType = SignedLong;
5284 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5285 MaxVectorAlign = 128;
5286 MaxAtomicInlineWidth = 128;
5287 MaxAtomicPromoteWidth = 128;
5289 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
5290 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5292 // {} in inline assembly are neon specifiers, not assembly variant
5294 NoAsmVariants = true;
5296 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
5297 // contributes to the alignment of the containing aggregate in the same way
5298 // a plain (non bit-field) member of that type would, without exception for
5299 // zero-sized or anonymous bit-fields."
5300 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
5301 UseZeroLengthBitfieldAlignment = true;
5303 // AArch64 targets default to using the ARM C++ ABI.
5304 TheCXXABI.set(TargetCXXABI::GenericAArch64);
5307 StringRef getABI() const override { return ABI; }
5308 bool setABI(const std::string &Name) override {
5309 if (Name != "aapcs" && Name != "darwinpcs")
5316 bool setCPU(const std::string &Name) override {
5317 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5318 .Case("generic", true)
5319 .Cases("cortex-a53", "cortex-a57", "cortex-a72",
5320 "cortex-a35", "exynos-m1", true)
5321 .Case("cyclone", true)
5326 void getTargetDefines(const LangOptions &Opts,
5327 MacroBuilder &Builder) const override {
5328 // Target identification.
5329 Builder.defineMacro("__aarch64__");
5331 // Target properties.
5332 Builder.defineMacro("_LP64");
5333 Builder.defineMacro("__LP64__");
5335 // ACLE predefines. Many can only have one possible value on v8 AArch64.
5336 Builder.defineMacro("__ARM_ACLE", "200");
5337 Builder.defineMacro("__ARM_ARCH", "8");
5338 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
5340 Builder.defineMacro("__ARM_64BIT_STATE", "1");
5341 Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
5342 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
5344 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
5345 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
5346 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
5347 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
5348 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
5349 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
5350 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
5352 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
5354 // 0xe implies support for half, single and double precision operations.
5355 Builder.defineMacro("__ARM_FP", "0xE");
5357 // PCS specifies this for SysV variants, which is all we support. Other ABIs
5358 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
5359 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
5360 Builder.defineMacro("__ARM_FP16_ARGS", "1");
5362 if (Opts.UnsafeFPMath)
5363 Builder.defineMacro("__ARM_FP_FAST", "1");
5365 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
5367 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5368 Opts.ShortEnums ? "1" : "4");
5370 if (FPU == NeonMode) {
5371 Builder.defineMacro("__ARM_NEON", "1");
5372 // 64-bit NEON supports half, single and double precision operations.
5373 Builder.defineMacro("__ARM_NEON_FP", "0xE");
5377 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
5380 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
5383 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
5386 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
5388 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
5389 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
5390 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
5391 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
5392 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
5395 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5396 return llvm::makeArrayRef(BuiltinInfo,
5397 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin);
5400 bool hasFeature(StringRef Feature) const override {
5401 return Feature == "aarch64" ||
5402 Feature == "arm64" ||
5404 (Feature == "neon" && FPU == NeonMode);
5407 bool handleTargetFeatures(std::vector<std::string> &Features,
5408 DiagnosticsEngine &Diags) override {
5415 for (const auto &Feature : Features) {
5416 if (Feature == "+neon")
5418 if (Feature == "+crc")
5420 if (Feature == "+crypto")
5422 if (Feature == "+strict-align")
5424 if (Feature == "+v8.1a")
5428 setDataLayoutString();
5433 bool isCLZForZeroUndef() const override { return false; }
5435 BuiltinVaListKind getBuiltinVaListKind() const override {
5436 return TargetInfo::AArch64ABIBuiltinVaList;
5439 ArrayRef<const char *> getGCCRegNames() const override;
5440 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5442 bool validateAsmConstraint(const char *&Name,
5443 TargetInfo::ConstraintInfo &Info) const override {
5447 case 'w': // Floating point and SIMD registers (V0-V31)
5448 Info.setAllowsRegister();
5450 case 'I': // Constant that can be used with an ADD instruction
5451 case 'J': // Constant that can be used with a SUB instruction
5452 case 'K': // Constant that can be used with a 32-bit logical instruction
5453 case 'L': // Constant that can be used with a 64-bit logical instruction
5454 case 'M': // Constant that can be used as a 32-bit MOV immediate
5455 case 'N': // Constant that can be used as a 64-bit MOV immediate
5456 case 'Y': // Floating point constant zero
5457 case 'Z': // Integer constant zero
5459 case 'Q': // A memory reference with base register and no offset
5460 Info.setAllowsMemory();
5462 case 'S': // A symbolic address
5463 Info.setAllowsRegister();
5466 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
5467 // Utf: A memory address suitable for ldp/stp in TF mode.
5468 // Usa: An absolute symbolic address.
5469 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
5470 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
5471 case 'z': // Zero register, wzr or xzr
5472 Info.setAllowsRegister();
5474 case 'x': // Floating point and SIMD registers (V0-V15)
5475 Info.setAllowsRegister();
5482 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5483 std::string &SuggestedModifier) const override {
5484 // Strip off constraint modifiers.
5485 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
5486 Constraint = Constraint.substr(1);
5488 switch (Constraint[0]) {
5496 // For now assume that the person knows what they're
5497 // doing with the modifier.
5500 // By default an 'r' constraint will be in the 'x'
5505 SuggestedModifier = "w";
5512 const char *getClobbers() const override { return ""; }
5514 int getEHDataRegisterNumber(unsigned RegNo) const override {
5523 const char *const AArch64TargetInfo::GCCRegNames[] = {
5524 // 32-bit Integer registers
5525 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
5526 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
5527 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
5529 // 64-bit Integer registers
5530 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
5531 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
5532 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
5534 // 32-bit floating point regsisters
5535 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
5536 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
5537 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5539 // 64-bit floating point regsisters
5540 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
5541 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
5542 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5545 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
5546 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
5547 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
5550 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
5551 return llvm::makeArrayRef(GCCRegNames);
5554 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
5555 { { "w31" }, "wsp" },
5556 { { "x29" }, "fp" },
5557 { { "x30" }, "lr" },
5558 { { "x31" }, "sp" },
5559 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
5560 // don't want to substitute one of these for a different-sized one.
5563 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
5564 return llvm::makeArrayRef(GCCRegAliases);
5567 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
5568 #define BUILTIN(ID, TYPE, ATTRS) \
5569 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5570 #include "clang/Basic/BuiltinsNEON.def"
5572 #define BUILTIN(ID, TYPE, ATTRS) \
5573 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5574 #include "clang/Basic/BuiltinsAArch64.def"
5577 class AArch64leTargetInfo : public AArch64TargetInfo {
5578 void setDataLayoutString() override {
5579 if (getTriple().isOSBinFormatMachO())
5580 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128";
5582 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128";
5586 AArch64leTargetInfo(const llvm::Triple &Triple)
5587 : AArch64TargetInfo(Triple) {
5590 void getTargetDefines(const LangOptions &Opts,
5591 MacroBuilder &Builder) const override {
5592 Builder.defineMacro("__AARCH64EL__");
5593 AArch64TargetInfo::getTargetDefines(Opts, Builder);
5597 class AArch64beTargetInfo : public AArch64TargetInfo {
5598 void setDataLayoutString() override {
5599 assert(!getTriple().isOSBinFormatMachO());
5600 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128";
5604 AArch64beTargetInfo(const llvm::Triple &Triple)
5605 : AArch64TargetInfo(Triple) { }
5606 void getTargetDefines(const LangOptions &Opts,
5607 MacroBuilder &Builder) const override {
5608 Builder.defineMacro("__AARCH64EB__");
5609 Builder.defineMacro("__AARCH_BIG_ENDIAN");
5610 Builder.defineMacro("__ARM_BIG_ENDIAN");
5611 AArch64TargetInfo::getTargetDefines(Opts, Builder);
5615 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
5617 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5618 MacroBuilder &Builder) const override {
5619 Builder.defineMacro("__AARCH64_SIMD__");
5620 Builder.defineMacro("__ARM64_ARCH_8__");
5621 Builder.defineMacro("__ARM_NEON__");
5622 Builder.defineMacro("__LITTLE_ENDIAN__");
5623 Builder.defineMacro("__REGISTER_PREFIX__", "");
5624 Builder.defineMacro("__arm64", "1");
5625 Builder.defineMacro("__arm64__", "1");
5627 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5631 DarwinAArch64TargetInfo(const llvm::Triple &Triple)
5632 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
5633 Int64Type = SignedLongLong;
5634 WCharType = SignedInt;
5635 UseSignedCharForObjCBool = false;
5637 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
5638 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5640 TheCXXABI.set(TargetCXXABI::iOS64);
5643 BuiltinVaListKind getBuiltinVaListKind() const override {
5644 return TargetInfo::CharPtrBuiltinVaList;
5648 // Hexagon abstract base class
5649 class HexagonTargetInfo : public TargetInfo {
5650 static const Builtin::Info BuiltinInfo[];
5651 static const char * const GCCRegNames[];
5652 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5654 bool HasHVX, HasHVXDouble;
5657 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5659 DataLayoutString = "e-m:e-p:32:32:32-"
5660 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-"
5661 "f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32";
5662 SizeType = UnsignedInt;
5663 PtrDiffType = SignedInt;
5664 IntPtrType = SignedInt;
5666 // {} in inline assembly are packet specifiers, not assembly variant
5668 NoAsmVariants = true;
5670 LargeArrayMinWidth = 64;
5671 LargeArrayAlign = 64;
5672 UseBitFieldTypeAlignment = true;
5673 ZeroLengthBitfieldBoundary = 32;
5674 HasHVX = HasHVXDouble = false;
5677 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5678 return llvm::makeArrayRef(BuiltinInfo,
5679 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin);
5682 bool validateAsmConstraint(const char *&Name,
5683 TargetInfo::ConstraintInfo &Info) const override {
5687 void getTargetDefines(const LangOptions &Opts,
5688 MacroBuilder &Builder) const override;
5690 bool isCLZForZeroUndef() const override { return false; }
5692 bool hasFeature(StringRef Feature) const override {
5693 return llvm::StringSwitch<bool>(Feature)
5694 .Case("hexagon", true)
5695 .Case("hvx", HasHVX)
5696 .Case("hvx-double", HasHVXDouble)
5700 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
5701 StringRef CPU, const std::vector<std::string> &FeaturesVec)
5704 bool handleTargetFeatures(std::vector<std::string> &Features,
5705 DiagnosticsEngine &Diags) override;
5707 BuiltinVaListKind getBuiltinVaListKind() const override {
5708 return TargetInfo::CharPtrBuiltinVaList;
5710 ArrayRef<const char *> getGCCRegNames() const override;
5711 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5712 const char *getClobbers() const override {
5716 static const char *getHexagonCPUSuffix(StringRef Name) {
5717 return llvm::StringSwitch<const char*>(Name)
5718 .Case("hexagonv4", "4")
5719 .Case("hexagonv5", "5")
5720 .Case("hexagonv55", "55")
5721 .Case("hexagonv60", "60")
5725 bool setCPU(const std::string &Name) override {
5726 if (!getHexagonCPUSuffix(Name))
5732 int getEHDataRegisterNumber(unsigned RegNo) const override {
5733 return RegNo < 2 ? RegNo : -1;
5737 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5738 MacroBuilder &Builder) const {
5739 Builder.defineMacro("__qdsp6__", "1");
5740 Builder.defineMacro("__hexagon__", "1");
5742 if (CPU == "hexagonv4") {
5743 Builder.defineMacro("__HEXAGON_V4__");
5744 Builder.defineMacro("__HEXAGON_ARCH__", "4");
5745 if (Opts.HexagonQdsp6Compat) {
5746 Builder.defineMacro("__QDSP6_V4__");
5747 Builder.defineMacro("__QDSP6_ARCH__", "4");
5749 } else if (CPU == "hexagonv5") {
5750 Builder.defineMacro("__HEXAGON_V5__");
5751 Builder.defineMacro("__HEXAGON_ARCH__", "5");
5752 if(Opts.HexagonQdsp6Compat) {
5753 Builder.defineMacro("__QDSP6_V5__");
5754 Builder.defineMacro("__QDSP6_ARCH__", "5");
5756 } else if (CPU == "hexagonv60") {
5757 Builder.defineMacro("__HEXAGON_V60__");
5758 Builder.defineMacro("__HEXAGON_ARCH__", "60");
5759 Builder.defineMacro("__QDSP6_V60__");
5760 Builder.defineMacro("__QDSP6_ARCH__", "60");
5764 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
5765 DiagnosticsEngine &Diags) {
5766 for (auto &F : Features) {
5769 else if (F == "-hvx")
5770 HasHVX = HasHVXDouble = false;
5771 else if (F == "+hvx-double")
5772 HasHVX = HasHVXDouble = true;
5773 else if (F == "-hvx-double")
5774 HasHVXDouble = false;
5779 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features,
5780 DiagnosticsEngine &Diags, StringRef CPU,
5781 const std::vector<std::string> &FeaturesVec) const {
5782 // Default for v60: -hvx, -hvx-double.
5783 Features["hvx"] = false;
5784 Features["hvx-double"] = false;
5786 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
5790 const char *const HexagonTargetInfo::GCCRegNames[] = {
5791 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5792 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5793 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5794 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5795 "p0", "p1", "p2", "p3",
5796 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5799 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const {
5800 return llvm::makeArrayRef(GCCRegNames);
5803 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5804 { { "sp" }, "r29" },
5805 { { "fp" }, "r30" },
5806 { { "lr" }, "r31" },
5809 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const {
5810 return llvm::makeArrayRef(GCCRegAliases);
5814 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5815 #define BUILTIN(ID, TYPE, ATTRS) \
5816 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5817 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5818 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5819 #include "clang/Basic/BuiltinsHexagon.def"
5822 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5823 class SparcTargetInfo : public TargetInfo {
5824 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5825 static const char * const GCCRegNames[];
5828 SparcTargetInfo(const llvm::Triple &Triple)
5829 : TargetInfo(Triple), SoftFloat(false) {}
5831 bool handleTargetFeatures(std::vector<std::string> &Features,
5832 DiagnosticsEngine &Diags) override {
5833 // The backend doesn't actually handle soft float yet, but in case someone
5834 // is using the support for the front end continue to support it.
5835 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
5836 if (Feature != Features.end()) {
5838 Features.erase(Feature);
5842 void getTargetDefines(const LangOptions &Opts,
5843 MacroBuilder &Builder) const override {
5844 DefineStd(Builder, "sparc", Opts);
5845 Builder.defineMacro("__REGISTER_PREFIX__", "");
5848 Builder.defineMacro("SOFT_FLOAT", "1");
5851 bool hasFeature(StringRef Feature) const override {
5852 return llvm::StringSwitch<bool>(Feature)
5853 .Case("softfloat", SoftFloat)
5854 .Case("sparc", true)
5858 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5859 // FIXME: Implement!
5862 BuiltinVaListKind getBuiltinVaListKind() const override {
5863 return TargetInfo::VoidPtrBuiltinVaList;
5865 ArrayRef<const char *> getGCCRegNames() const override;
5866 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5867 bool validateAsmConstraint(const char *&Name,
5868 TargetInfo::ConstraintInfo &info) const override {
5869 // FIXME: Implement!
5871 case 'I': // Signed 13-bit constant
5873 case 'K': // 32-bit constant with the low 12 bits clear
5874 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5875 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5876 case 'N': // Same as 'K' but zext (required for SIMode)
5877 case 'O': // The constant 4096
5882 const char *getClobbers() const override {
5883 // FIXME: Implement!
5887 // No Sparc V7 for now, the backend doesn't support it anyway.
5907 enum CPUGeneration {
5912 CPUGeneration getCPUGeneration(CPUKind Kind) const {
5920 case CK_SPARCLITE86X:
5926 case CK_ULTRASPARC3:
5933 llvm_unreachable("Unexpected CPU kind");
5936 CPUKind getCPUKind(StringRef Name) const {
5937 return llvm::StringSwitch<CPUKind>(Name)
5939 .Case("supersparc", CK_SUPERSPARC)
5940 .Case("sparclite", CK_SPARCLITE)
5941 .Case("f934", CK_F934)
5942 .Case("hypersparc", CK_HYPERSPARC)
5943 .Case("sparclite86x", CK_SPARCLITE86X)
5944 .Case("sparclet", CK_SPARCLET)
5945 .Case("tsc701", CK_TSC701)
5947 .Case("ultrasparc", CK_ULTRASPARC)
5948 .Case("ultrasparc3", CK_ULTRASPARC3)
5949 .Case("niagara", CK_NIAGARA)
5950 .Case("niagara2", CK_NIAGARA2)
5951 .Case("niagara3", CK_NIAGARA3)
5952 .Case("niagara4", CK_NIAGARA4)
5953 .Default(CK_GENERIC);
5956 bool setCPU(const std::string &Name) override {
5957 CPU = getCPUKind(Name);
5958 return CPU != CK_GENERIC;
5962 const char * const SparcTargetInfo::GCCRegNames[] = {
5963 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5964 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5965 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5966 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5969 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
5970 return llvm::makeArrayRef(GCCRegNames);
5973 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5984 { { "o2" }, "r10" },
5985 { { "o3" }, "r11" },
5986 { { "o4" }, "r12" },
5987 { { "o5" }, "r13" },
5988 { { "o6", "sp" }, "r14" },
5989 { { "o7" }, "r15" },
5990 { { "l0" }, "r16" },
5991 { { "l1" }, "r17" },
5992 { { "l2" }, "r18" },
5993 { { "l3" }, "r19" },
5994 { { "l4" }, "r20" },
5995 { { "l5" }, "r21" },
5996 { { "l6" }, "r22" },
5997 { { "l7" }, "r23" },
5998 { { "i0" }, "r24" },
5999 { { "i1" }, "r25" },
6000 { { "i2" }, "r26" },
6001 { { "i3" }, "r27" },
6002 { { "i4" }, "r28" },
6003 { { "i5" }, "r29" },
6004 { { "i6", "fp" }, "r30" },
6005 { { "i7" }, "r31" },
6008 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
6009 return llvm::makeArrayRef(GCCRegAliases);
6012 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
6013 class SparcV8TargetInfo : public SparcTargetInfo {
6015 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
6016 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
6017 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
6018 switch (getTriple().getOS()) {
6020 SizeType = UnsignedInt;
6021 IntPtrType = SignedInt;
6022 PtrDiffType = SignedInt;
6024 case llvm::Triple::NetBSD:
6025 case llvm::Triple::OpenBSD:
6026 SizeType = UnsignedLong;
6027 IntPtrType = SignedLong;
6028 PtrDiffType = SignedLong;
6033 void getTargetDefines(const LangOptions &Opts,
6034 MacroBuilder &Builder) const override {
6035 SparcTargetInfo::getTargetDefines(Opts, Builder);
6036 switch (getCPUGeneration(CPU)) {
6038 Builder.defineMacro("__sparcv8");
6039 if (getTriple().getOS() != llvm::Triple::Solaris)
6040 Builder.defineMacro("__sparcv8__");
6043 Builder.defineMacro("__sparcv9");
6044 if (getTriple().getOS() != llvm::Triple::Solaris) {
6045 Builder.defineMacro("__sparcv9__");
6046 Builder.defineMacro("__sparc_v9__");
6053 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
6054 class SparcV8elTargetInfo : public SparcV8TargetInfo {
6056 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) {
6057 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64";
6062 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
6063 class SparcV9TargetInfo : public SparcTargetInfo {
6065 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
6066 // FIXME: Support Sparc quad-precision long double?
6067 DataLayoutString = "E-m:e-i64:64-n32:64-S128";
6068 // This is an LP64 platform.
6069 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6071 // OpenBSD uses long long for int64_t and intmax_t.
6072 if (getTriple().getOS() == llvm::Triple::OpenBSD)
6073 IntMaxType = SignedLongLong;
6075 IntMaxType = SignedLong;
6076 Int64Type = IntMaxType;
6078 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
6079 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
6080 LongDoubleWidth = 128;
6081 LongDoubleAlign = 128;
6082 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6083 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6086 void getTargetDefines(const LangOptions &Opts,
6087 MacroBuilder &Builder) const override {
6088 SparcTargetInfo::getTargetDefines(Opts, Builder);
6089 Builder.defineMacro("__sparcv9");
6090 Builder.defineMacro("__arch64__");
6091 // Solaris doesn't need these variants, but the BSDs do.
6092 if (getTriple().getOS() != llvm::Triple::Solaris) {
6093 Builder.defineMacro("__sparc64__");
6094 Builder.defineMacro("__sparc_v9__");
6095 Builder.defineMacro("__sparcv9__");
6099 bool setCPU(const std::string &Name) override {
6100 if (!SparcTargetInfo::setCPU(Name))
6102 return getCPUGeneration(CPU) == CG_V9;
6106 class SystemZTargetInfo : public TargetInfo {
6107 static const Builtin::Info BuiltinInfo[];
6108 static const char *const GCCRegNames[];
6110 bool HasTransactionalExecution;
6114 SystemZTargetInfo(const llvm::Triple &Triple)
6115 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false),
6117 IntMaxType = SignedLong;
6118 Int64Type = SignedLong;
6119 TLSSupported = true;
6120 IntWidth = IntAlign = 32;
6121 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
6122 PointerWidth = PointerAlign = 64;
6123 LongDoubleWidth = 128;
6124 LongDoubleAlign = 64;
6125 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6126 DefaultAlignForAttributeAligned = 64;
6127 MinGlobalAlign = 16;
6128 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
6129 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6131 void getTargetDefines(const LangOptions &Opts,
6132 MacroBuilder &Builder) const override {
6133 Builder.defineMacro("__s390__");
6134 Builder.defineMacro("__s390x__");
6135 Builder.defineMacro("__zarch__");
6136 Builder.defineMacro("__LONG_DOUBLE_128__");
6137 if (HasTransactionalExecution)
6138 Builder.defineMacro("__HTM__");
6140 Builder.defineMacro("__VEC__", "10301");
6142 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6143 return llvm::makeArrayRef(BuiltinInfo,
6144 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin);
6147 ArrayRef<const char *> getGCCRegNames() const override;
6148 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6152 bool validateAsmConstraint(const char *&Name,
6153 TargetInfo::ConstraintInfo &info) const override;
6154 const char *getClobbers() const override {
6155 // FIXME: Is this really right?
6158 BuiltinVaListKind getBuiltinVaListKind() const override {
6159 return TargetInfo::SystemZBuiltinVaList;
6161 bool setCPU(const std::string &Name) override {
6163 bool CPUKnown = llvm::StringSwitch<bool>(Name)
6166 .Case("zEC12", true)
6173 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6175 const std::vector<std::string> &FeaturesVec) const override {
6177 Features["transactional-execution"] = true;
6179 Features["transactional-execution"] = true;
6180 Features["vector"] = true;
6182 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6185 bool handleTargetFeatures(std::vector<std::string> &Features,
6186 DiagnosticsEngine &Diags) override {
6187 HasTransactionalExecution = false;
6188 for (const auto &Feature : Features) {
6189 if (Feature == "+transactional-execution")
6190 HasTransactionalExecution = true;
6191 else if (Feature == "+vector")
6194 // If we use the vector ABI, vector types are 64-bit aligned.
6196 MaxVectorAlign = 64;
6197 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
6198 "-v128:64-a:8:16-n32:64";
6203 bool hasFeature(StringRef Feature) const override {
6204 return llvm::StringSwitch<bool>(Feature)
6205 .Case("systemz", true)
6206 .Case("htm", HasTransactionalExecution)
6207 .Case("vx", HasVector)
6211 StringRef getABI() const override {
6217 bool useFloat128ManglingForLongDouble() const override {
6222 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
6223 #define BUILTIN(ID, TYPE, ATTRS) \
6224 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6225 #include "clang/Basic/BuiltinsSystemZ.def"
6228 const char *const SystemZTargetInfo::GCCRegNames[] = {
6229 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6230 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6231 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
6232 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
6235 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
6236 return llvm::makeArrayRef(GCCRegNames);
6239 bool SystemZTargetInfo::
6240 validateAsmConstraint(const char *&Name,
6241 TargetInfo::ConstraintInfo &Info) const {
6246 case 'a': // Address register
6247 case 'd': // Data register (equivalent to 'r')
6248 case 'f': // Floating-point register
6249 Info.setAllowsRegister();
6252 case 'I': // Unsigned 8-bit constant
6253 case 'J': // Unsigned 12-bit constant
6254 case 'K': // Signed 16-bit constant
6255 case 'L': // Signed 20-bit displacement (on all targets we support)
6256 case 'M': // 0x7fffffff
6259 case 'Q': // Memory with base and unsigned 12-bit displacement
6260 case 'R': // Likewise, plus an index
6261 case 'S': // Memory with base and signed 20-bit displacement
6262 case 'T': // Likewise, plus an index
6263 Info.setAllowsMemory();
6268 class MSP430TargetInfo : public TargetInfo {
6269 static const char *const GCCRegNames[];
6272 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6274 TLSSupported = false;
6279 LongAlign = LongLongAlign = 16;
6283 SizeType = UnsignedInt;
6284 IntMaxType = SignedLongLong;
6285 IntPtrType = SignedInt;
6286 PtrDiffType = SignedInt;
6287 SigAtomicType = SignedLong;
6288 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
6290 void getTargetDefines(const LangOptions &Opts,
6291 MacroBuilder &Builder) const override {
6292 Builder.defineMacro("MSP430");
6293 Builder.defineMacro("__MSP430__");
6294 // FIXME: defines for different 'flavours' of MCU
6296 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6297 // FIXME: Implement.
6300 bool hasFeature(StringRef Feature) const override {
6301 return Feature == "msp430";
6303 ArrayRef<const char *> getGCCRegNames() const override;
6304 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6308 bool validateAsmConstraint(const char *&Name,
6309 TargetInfo::ConstraintInfo &info) const override {
6312 case 'K': // the constant 1
6313 case 'L': // constant -1^20 .. 1^19
6314 case 'M': // constant 1-4:
6317 // No target constraints for now.
6320 const char *getClobbers() const override {
6321 // FIXME: Is this really right?
6324 BuiltinVaListKind getBuiltinVaListKind() const override {
6326 return TargetInfo::CharPtrBuiltinVaList;
6330 const char *const MSP430TargetInfo::GCCRegNames[] = {
6331 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6332 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
6334 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const {
6335 return llvm::makeArrayRef(GCCRegNames);
6338 // LLVM and Clang cannot be used directly to output native binaries for
6339 // target, but is used to compile C code to llvm bitcode with correct
6340 // type and alignment information.
6342 // TCE uses the llvm bitcode as input and uses it for generating customized
6343 // target processor and program binary. TCE co-design environment is
6344 // publicly available in http://tce.cs.tut.fi
6346 static const unsigned TCEOpenCLAddrSpaceMap[] = {
6349 5, // opencl_constant
6350 // FIXME: generic has to be added to the target
6351 0, // opencl_generic
6357 class TCETargetInfo : public TargetInfo {
6359 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6360 TLSSupported = false;
6362 LongWidth = LongLongWidth = 32;
6365 LongAlign = LongLongAlign = 32;
6368 SizeType = UnsignedInt;
6369 IntMaxType = SignedLong;
6370 IntPtrType = SignedInt;
6371 PtrDiffType = SignedInt;
6376 LongDoubleWidth = 32;
6377 LongDoubleAlign = 32;
6378 FloatFormat = &llvm::APFloat::IEEEsingle;
6379 DoubleFormat = &llvm::APFloat::IEEEsingle;
6380 LongDoubleFormat = &llvm::APFloat::IEEEsingle;
6381 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
6382 "-f64:32-v64:32-v128:32-a:0:32-n32";
6383 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
6384 UseAddrSpaceMapMangling = true;
6387 void getTargetDefines(const LangOptions &Opts,
6388 MacroBuilder &Builder) const override {
6389 DefineStd(Builder, "tce", Opts);
6390 Builder.defineMacro("__TCE__");
6391 Builder.defineMacro("__TCE_V1__");
6393 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; }
6395 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
6396 const char *getClobbers() const override { return ""; }
6397 BuiltinVaListKind getBuiltinVaListKind() const override {
6398 return TargetInfo::VoidPtrBuiltinVaList;
6400 ArrayRef<const char *> getGCCRegNames() const override { return None; }
6401 bool validateAsmConstraint(const char *&Name,
6402 TargetInfo::ConstraintInfo &info) const override {
6405 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6410 class BPFTargetInfo : public TargetInfo {
6412 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6413 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6414 SizeType = UnsignedLong;
6415 PtrDiffType = SignedLong;
6416 IntPtrType = SignedLong;
6417 IntMaxType = SignedLong;
6418 Int64Type = SignedLong;
6420 if (Triple.getArch() == llvm::Triple::bpfeb) {
6422 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128";
6425 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128";
6427 MaxAtomicPromoteWidth = 64;
6428 MaxAtomicInlineWidth = 64;
6429 TLSSupported = false;
6431 void getTargetDefines(const LangOptions &Opts,
6432 MacroBuilder &Builder) const override {
6433 DefineStd(Builder, "bpf", Opts);
6434 Builder.defineMacro("__BPF__");
6436 bool hasFeature(StringRef Feature) const override {
6437 return Feature == "bpf";
6440 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
6441 const char *getClobbers() const override {
6444 BuiltinVaListKind getBuiltinVaListKind() const override {
6445 return TargetInfo::VoidPtrBuiltinVaList;
6447 ArrayRef<const char *> getGCCRegNames() const override {
6450 bool validateAsmConstraint(const char *&Name,
6451 TargetInfo::ConstraintInfo &info) const override {
6454 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6459 class MipsTargetInfoBase : public TargetInfo {
6460 virtual void setDataLayoutString() = 0;
6462 static const Builtin::Info BuiltinInfo[];
6469 HardFloat, SoftFloat
6481 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
6482 const std::string &CPUStr)
6483 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
6484 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
6485 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
6486 TheCXXABI.set(TargetCXXABI::GenericMIPS);
6489 bool isNaN2008Default() const {
6490 return CPU == "mips32r6" || CPU == "mips64r6";
6493 bool isFP64Default() const {
6494 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
6497 bool isNan2008() const override {
6501 StringRef getABI() const override { return ABI; }
6502 bool setCPU(const std::string &Name) override {
6503 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
6504 getTriple().getArch() == llvm::Triple::mipsel;
6506 return llvm::StringSwitch<bool>(Name)
6507 .Case("mips1", IsMips32)
6508 .Case("mips2", IsMips32)
6509 .Case("mips3", true)
6510 .Case("mips4", true)
6511 .Case("mips5", true)
6512 .Case("mips32", IsMips32)
6513 .Case("mips32r2", IsMips32)
6514 .Case("mips32r3", IsMips32)
6515 .Case("mips32r5", IsMips32)
6516 .Case("mips32r6", IsMips32)
6517 .Case("mips64", true)
6518 .Case("mips64r2", true)
6519 .Case("mips64r3", true)
6520 .Case("mips64r5", true)
6521 .Case("mips64r6", true)
6522 .Case("octeon", true)
6523 .Case("p5600", true)
6526 const std::string& getCPU() const { return CPU; }
6528 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6530 const std::vector<std::string> &FeaturesVec) const override {
6531 if (CPU == "octeon")
6532 Features["mips64r2"] = Features["cnmips"] = true;
6534 Features[CPU] = true;
6535 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6538 void getTargetDefines(const LangOptions &Opts,
6539 MacroBuilder &Builder) const override {
6540 Builder.defineMacro("__mips__");
6541 Builder.defineMacro("_mips");
6543 Builder.defineMacro("mips");
6545 Builder.defineMacro("__REGISTER_PREFIX__", "");
6549 Builder.defineMacro("__mips_hard_float", Twine(1));
6552 Builder.defineMacro("__mips_soft_float", Twine(1));
6557 Builder.defineMacro("__mips_single_float", Twine(1));
6559 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
6560 Builder.defineMacro("_MIPS_FPSET",
6561 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
6564 Builder.defineMacro("__mips16", Twine(1));
6567 Builder.defineMacro("__mips_micromips", Twine(1));
6570 Builder.defineMacro("__mips_nan2008", Twine(1));
6576 Builder.defineMacro("__mips_dsp_rev", Twine(1));
6577 Builder.defineMacro("__mips_dsp", Twine(1));
6580 Builder.defineMacro("__mips_dsp_rev", Twine(2));
6581 Builder.defineMacro("__mips_dspr2", Twine(1));
6582 Builder.defineMacro("__mips_dsp", Twine(1));
6587 Builder.defineMacro("__mips_msa", Twine(1));
6589 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
6590 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
6591 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
6593 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
6594 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
6596 // These shouldn't be defined for MIPS-I but there's no need to check
6597 // for that since MIPS-I isn't supported.
6598 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
6599 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
6600 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
6603 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6604 return llvm::makeArrayRef(BuiltinInfo,
6605 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin);
6607 bool hasFeature(StringRef Feature) const override {
6608 return llvm::StringSwitch<bool>(Feature)
6610 .Case("fp64", HasFP64)
6613 BuiltinVaListKind getBuiltinVaListKind() const override {
6614 return TargetInfo::VoidPtrBuiltinVaList;
6616 ArrayRef<const char *> getGCCRegNames() const override {
6617 static const char *const GCCRegNames[] = {
6618 // CPU register names
6619 // Must match second column of GCCRegAliases
6620 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
6621 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
6622 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
6623 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
6624 // Floating point register names
6625 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
6626 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
6627 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
6628 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
6629 // Hi/lo and condition register names
6630 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
6631 "$fcc5","$fcc6","$fcc7",
6632 // MSA register names
6633 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
6634 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
6635 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
6636 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
6637 // MSA control register names
6638 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
6639 "$msarequest", "$msamap", "$msaunmap"
6641 return llvm::makeArrayRef(GCCRegNames);
6643 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0;
6644 bool validateAsmConstraint(const char *&Name,
6645 TargetInfo::ConstraintInfo &Info) const override {
6649 case 'r': // CPU registers.
6650 case 'd': // Equivalent to "r" unless generating MIPS16 code.
6651 case 'y': // Equivalent to "r", backward compatibility only.
6652 case 'f': // floating-point registers.
6653 case 'c': // $25 for indirect jumps
6654 case 'l': // lo register
6655 case 'x': // hilo register pair
6656 Info.setAllowsRegister();
6658 case 'I': // Signed 16-bit constant
6659 case 'J': // Integer 0
6660 case 'K': // Unsigned 16-bit constant
6661 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
6662 case 'M': // Constants not loadable via lui, addiu, or ori
6663 case 'N': // Constant -1 to -65535
6664 case 'O': // A signed 15-bit constant
6665 case 'P': // A constant between 1 go 65535
6667 case 'R': // An address that can be used in a non-macro load or store
6668 Info.setAllowsMemory();
6671 if (Name[1] == 'C') { // An address usable by ll, and sc.
6672 Info.setAllowsMemory();
6673 Name++; // Skip over 'Z'.
6680 std::string convertConstraint(const char *&Constraint) const override {
6682 switch (*Constraint) {
6683 case 'Z': // Two-character constraint; add "^" hint for later parsing.
6684 if (Constraint[1] == 'C') {
6685 R = std::string("^") + std::string(Constraint, 2);
6691 return TargetInfo::convertConstraint(Constraint);
6694 const char *getClobbers() const override {
6695 // In GCC, $1 is not widely used in generated code (it's used only in a few
6696 // specific situations), so there is no real need for users to add it to
6697 // the clobbers list if they want to use it in their inline assembly code.
6699 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
6700 // code generation, so using it in inline assembly without adding it to the
6701 // clobbers list can cause conflicts between the inline assembly code and
6702 // the surrounding generated code.
6704 // Another problem is that LLVM is allowed to choose $1 for inline assembly
6705 // operands, which will conflict with the ".set at" assembler option (which
6706 // we use only for inline assembly, in order to maintain compatibility with
6707 // GCC) and will also conflict with the user's usage of $1.
6709 // The easiest way to avoid these conflicts and keep $1 as an allocatable
6710 // register for generated code is to automatically clobber $1 for all inline
6713 // FIXME: We should automatically clobber $1 only for inline assembly code
6714 // which actually uses it. This would allow LLVM to use $1 for inline
6715 // assembly operands if the user's assembly code doesn't use it.
6719 bool handleTargetFeatures(std::vector<std::string> &Features,
6720 DiagnosticsEngine &Diags) override {
6722 IsMicromips = false;
6723 IsNan2008 = isNaN2008Default();
6724 IsSingleFloat = false;
6725 FloatABI = HardFloat;
6727 HasFP64 = isFP64Default();
6729 for (const auto &Feature : Features) {
6730 if (Feature == "+single-float")
6731 IsSingleFloat = true;
6732 else if (Feature == "+soft-float")
6733 FloatABI = SoftFloat;
6734 else if (Feature == "+mips16")
6736 else if (Feature == "+micromips")
6738 else if (Feature == "+dsp")
6739 DspRev = std::max(DspRev, DSP1);
6740 else if (Feature == "+dspr2")
6741 DspRev = std::max(DspRev, DSP2);
6742 else if (Feature == "+msa")
6744 else if (Feature == "+fp64")
6746 else if (Feature == "-fp64")
6748 else if (Feature == "+nan2008")
6750 else if (Feature == "-nan2008")
6754 setDataLayoutString();
6759 int getEHDataRegisterNumber(unsigned RegNo) const override {
6760 if (RegNo == 0) return 4;
6761 if (RegNo == 1) return 5;
6765 bool isCLZForZeroUndef() const override { return false; }
6768 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
6769 #define BUILTIN(ID, TYPE, ATTRS) \
6770 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6771 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6772 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6773 #include "clang/Basic/BuiltinsMips.def"
6776 class Mips32TargetInfoBase : public MipsTargetInfoBase {
6778 Mips32TargetInfoBase(const llvm::Triple &Triple)
6779 : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
6780 SizeType = UnsignedInt;
6781 PtrDiffType = SignedInt;
6782 Int64Type = SignedLongLong;
6783 IntMaxType = Int64Type;
6784 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
6786 bool setABI(const std::string &Name) override {
6787 if (Name == "o32" || Name == "eabi") {
6793 void getTargetDefines(const LangOptions &Opts,
6794 MacroBuilder &Builder) const override {
6795 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6797 Builder.defineMacro("__mips", "32");
6798 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
6800 const std::string& CPUStr = getCPU();
6801 if (CPUStr == "mips32")
6802 Builder.defineMacro("__mips_isa_rev", "1");
6803 else if (CPUStr == "mips32r2")
6804 Builder.defineMacro("__mips_isa_rev", "2");
6805 else if (CPUStr == "mips32r3")
6806 Builder.defineMacro("__mips_isa_rev", "3");
6807 else if (CPUStr == "mips32r5")
6808 Builder.defineMacro("__mips_isa_rev", "5");
6809 else if (CPUStr == "mips32r6")
6810 Builder.defineMacro("__mips_isa_rev", "6");
6813 Builder.defineMacro("__mips_o32");
6814 Builder.defineMacro("_ABIO32", "1");
6815 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
6817 else if (ABI == "eabi")
6818 Builder.defineMacro("__mips_eabi");
6820 llvm_unreachable("Invalid ABI for Mips32.");
6822 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6823 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6833 { { "t2" }, "$10" },
6834 { { "t3" }, "$11" },
6835 { { "t4" }, "$12" },
6836 { { "t5" }, "$13" },
6837 { { "t6" }, "$14" },
6838 { { "t7" }, "$15" },
6839 { { "s0" }, "$16" },
6840 { { "s1" }, "$17" },
6841 { { "s2" }, "$18" },
6842 { { "s3" }, "$19" },
6843 { { "s4" }, "$20" },
6844 { { "s5" }, "$21" },
6845 { { "s6" }, "$22" },
6846 { { "s7" }, "$23" },
6847 { { "t8" }, "$24" },
6848 { { "t9" }, "$25" },
6849 { { "k0" }, "$26" },
6850 { { "k1" }, "$27" },
6851 { { "gp" }, "$28" },
6852 { { "sp","$sp" }, "$29" },
6853 { { "fp","$fp" }, "$30" },
6856 return llvm::makeArrayRef(GCCRegAliases);
6860 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
6861 void setDataLayoutString() override {
6862 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6866 Mips32EBTargetInfo(const llvm::Triple &Triple)
6867 : Mips32TargetInfoBase(Triple) {
6869 void getTargetDefines(const LangOptions &Opts,
6870 MacroBuilder &Builder) const override {
6871 DefineStd(Builder, "MIPSEB", Opts);
6872 Builder.defineMacro("_MIPSEB");
6873 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6877 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
6878 void setDataLayoutString() override {
6879 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6883 Mips32ELTargetInfo(const llvm::Triple &Triple)
6884 : Mips32TargetInfoBase(Triple) {
6887 void getTargetDefines(const LangOptions &Opts,
6888 MacroBuilder &Builder) const override {
6889 DefineStd(Builder, "MIPSEL", Opts);
6890 Builder.defineMacro("_MIPSEL");
6891 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6895 class Mips64TargetInfoBase : public MipsTargetInfoBase {
6897 Mips64TargetInfoBase(const llvm::Triple &Triple)
6898 : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6899 LongDoubleWidth = LongDoubleAlign = 128;
6900 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6901 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6902 LongDoubleWidth = LongDoubleAlign = 64;
6903 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6906 SuitableAlign = 128;
6907 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6910 void setN64ABITypes() {
6911 LongWidth = LongAlign = 64;
6912 PointerWidth = PointerAlign = 64;
6913 SizeType = UnsignedLong;
6914 PtrDiffType = SignedLong;
6915 Int64Type = SignedLong;
6916 IntMaxType = Int64Type;
6919 void setN32ABITypes() {
6920 LongWidth = LongAlign = 32;
6921 PointerWidth = PointerAlign = 32;
6922 SizeType = UnsignedInt;
6923 PtrDiffType = SignedInt;
6924 Int64Type = SignedLongLong;
6925 IntMaxType = Int64Type;
6928 bool setABI(const std::string &Name) override {
6929 if (Name == "n32") {
6934 if (Name == "n64") {
6942 void getTargetDefines(const LangOptions &Opts,
6943 MacroBuilder &Builder) const override {
6944 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6946 Builder.defineMacro("__mips", "64");
6947 Builder.defineMacro("__mips64");
6948 Builder.defineMacro("__mips64__");
6949 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6951 const std::string& CPUStr = getCPU();
6952 if (CPUStr == "mips64")
6953 Builder.defineMacro("__mips_isa_rev", "1");
6954 else if (CPUStr == "mips64r2")
6955 Builder.defineMacro("__mips_isa_rev", "2");
6956 else if (CPUStr == "mips64r3")
6957 Builder.defineMacro("__mips_isa_rev", "3");
6958 else if (CPUStr == "mips64r5")
6959 Builder.defineMacro("__mips_isa_rev", "5");
6960 else if (CPUStr == "mips64r6")
6961 Builder.defineMacro("__mips_isa_rev", "6");
6964 Builder.defineMacro("__mips_n32");
6965 Builder.defineMacro("_ABIN32", "2");
6966 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6968 else if (ABI == "n64") {
6969 Builder.defineMacro("__mips_n64");
6970 Builder.defineMacro("_ABI64", "3");
6971 Builder.defineMacro("_MIPS_SIM", "_ABI64");
6974 llvm_unreachable("Invalid ABI for Mips64.");
6976 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
6978 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6979 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6989 { { "a6" }, "$10" },
6990 { { "a7" }, "$11" },
6991 { { "t0" }, "$12" },
6992 { { "t1" }, "$13" },
6993 { { "t2" }, "$14" },
6994 { { "t3" }, "$15" },
6995 { { "s0" }, "$16" },
6996 { { "s1" }, "$17" },
6997 { { "s2" }, "$18" },
6998 { { "s3" }, "$19" },
6999 { { "s4" }, "$20" },
7000 { { "s5" }, "$21" },
7001 { { "s6" }, "$22" },
7002 { { "s7" }, "$23" },
7003 { { "t8" }, "$24" },
7004 { { "t9" }, "$25" },
7005 { { "k0" }, "$26" },
7006 { { "k1" }, "$27" },
7007 { { "gp" }, "$28" },
7008 { { "sp","$sp" }, "$29" },
7009 { { "fp","$fp" }, "$30" },
7012 return llvm::makeArrayRef(GCCRegAliases);
7015 bool hasInt128Type() const override { return true; }
7018 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
7019 void setDataLayoutString() override {
7021 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7023 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7028 Mips64EBTargetInfo(const llvm::Triple &Triple)
7029 : Mips64TargetInfoBase(Triple) {}
7030 void getTargetDefines(const LangOptions &Opts,
7031 MacroBuilder &Builder) const override {
7032 DefineStd(Builder, "MIPSEB", Opts);
7033 Builder.defineMacro("_MIPSEB");
7034 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
7038 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
7039 void setDataLayoutString() override {
7041 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7043 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7046 Mips64ELTargetInfo(const llvm::Triple &Triple)
7047 : Mips64TargetInfoBase(Triple) {
7048 // Default ABI is n64.
7051 void getTargetDefines(const LangOptions &Opts,
7052 MacroBuilder &Builder) const override {
7053 DefineStd(Builder, "MIPSEL", Opts);
7054 Builder.defineMacro("_MIPSEL");
7055 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
7059 class PNaClTargetInfo : public TargetInfo {
7061 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
7063 this->UserLabelPrefix = "";
7064 this->LongAlign = 32;
7065 this->LongWidth = 32;
7066 this->PointerAlign = 32;
7067 this->PointerWidth = 32;
7068 this->IntMaxType = TargetInfo::SignedLongLong;
7069 this->Int64Type = TargetInfo::SignedLongLong;
7070 this->DoubleAlign = 64;
7071 this->LongDoubleWidth = 64;
7072 this->LongDoubleAlign = 64;
7073 this->SizeType = TargetInfo::UnsignedInt;
7074 this->PtrDiffType = TargetInfo::SignedInt;
7075 this->IntPtrType = TargetInfo::SignedInt;
7076 this->RegParmMax = 0; // Disallow regparm
7079 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
7080 Builder.defineMacro("__le32__");
7081 Builder.defineMacro("__pnacl__");
7083 void getTargetDefines(const LangOptions &Opts,
7084 MacroBuilder &Builder) const override {
7085 getArchDefines(Opts, Builder);
7087 bool hasFeature(StringRef Feature) const override {
7088 return Feature == "pnacl";
7090 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7091 BuiltinVaListKind getBuiltinVaListKind() const override {
7092 return TargetInfo::PNaClABIBuiltinVaList;
7094 ArrayRef<const char *> getGCCRegNames() const override;
7095 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
7096 bool validateAsmConstraint(const char *&Name,
7097 TargetInfo::ConstraintInfo &Info) const override {
7101 const char *getClobbers() const override {
7106 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const {
7110 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const {
7114 // We attempt to use PNaCl (le32) frontend and Mips32EL backend.
7115 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo {
7117 NaClMips32ELTargetInfo(const llvm::Triple &Triple) :
7118 Mips32ELTargetInfo(Triple) {
7121 BuiltinVaListKind getBuiltinVaListKind() const override {
7122 return TargetInfo::PNaClABIBuiltinVaList;
7126 class Le64TargetInfo : public TargetInfo {
7127 static const Builtin::Info BuiltinInfo[];
7130 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
7132 NoAsmVariants = true;
7133 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7134 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7135 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
7138 void getTargetDefines(const LangOptions &Opts,
7139 MacroBuilder &Builder) const override {
7140 DefineStd(Builder, "unix", Opts);
7141 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
7142 Builder.defineMacro("__ELF__");
7144 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7145 return llvm::makeArrayRef(BuiltinInfo,
7146 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin);
7148 BuiltinVaListKind getBuiltinVaListKind() const override {
7149 return TargetInfo::PNaClABIBuiltinVaList;
7151 const char *getClobbers() const override { return ""; }
7152 ArrayRef<const char *> getGCCRegNames() const override {
7155 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7158 bool validateAsmConstraint(const char *&Name,
7159 TargetInfo::ConstraintInfo &Info) const override {
7163 bool hasProtectedVisibility() const override { return false; }
7166 class WebAssemblyTargetInfo : public TargetInfo {
7167 static const Builtin::Info BuiltinInfo[];
7175 explicit WebAssemblyTargetInfo(const llvm::Triple &T)
7176 : TargetInfo(T), SIMDLevel(NoSIMD) {
7178 NoAsmVariants = true;
7179 SuitableAlign = 128;
7180 LargeArrayMinWidth = 128;
7181 LargeArrayAlign = 128;
7182 SimdDefaultAlign = 128;
7183 SigAtomicType = SignedLong;
7184 LongDoubleWidth = LongDoubleAlign = 128;
7185 LongDoubleFormat = &llvm::APFloat::IEEEquad;
7189 void getTargetDefines(const LangOptions &Opts,
7190 MacroBuilder &Builder) const override {
7191 defineCPUMacros(Builder, "wasm", /*Tuning=*/false);
7192 if (SIMDLevel >= SIMD128)
7193 Builder.defineMacro("__wasm_simd128__");
7198 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7200 const std::vector<std::string> &FeaturesVec) const override {
7201 if (CPU == "bleeding-edge")
7202 Features["simd128"] = true;
7203 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7205 bool hasFeature(StringRef Feature) const final {
7206 return llvm::StringSwitch<bool>(Feature)
7207 .Case("simd128", SIMDLevel >= SIMD128)
7210 bool handleTargetFeatures(std::vector<std::string> &Features,
7211 DiagnosticsEngine &Diags) final {
7212 for (const auto &Feature : Features) {
7213 if (Feature == "+simd128") {
7214 SIMDLevel = std::max(SIMDLevel, SIMD128);
7217 if (Feature == "-simd128") {
7218 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1));
7222 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature
7223 << "-target-feature";
7228 bool setCPU(const std::string &Name) final {
7229 return llvm::StringSwitch<bool>(Name)
7231 .Case("bleeding-edge", true)
7232 .Case("generic", true)
7235 ArrayRef<Builtin::Info> getTargetBuiltins() const final {
7236 return llvm::makeArrayRef(BuiltinInfo,
7237 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin);
7239 BuiltinVaListKind getBuiltinVaListKind() const final {
7240 return VoidPtrBuiltinVaList;
7242 ArrayRef<const char *> getGCCRegNames() const final {
7245 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final {
7249 validateAsmConstraint(const char *&Name,
7250 TargetInfo::ConstraintInfo &Info) const final {
7253 const char *getClobbers() const final { return ""; }
7254 bool isCLZForZeroUndef() const final { return false; }
7255 bool hasInt128Type() const final { return true; }
7256 IntType getIntTypeByWidth(unsigned BitWidth,
7257 bool IsSigned) const final {
7258 // WebAssembly prefers long long for explicitly 64-bit integers.
7259 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
7260 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
7262 IntType getLeastIntTypeByWidth(unsigned BitWidth,
7263 bool IsSigned) const final {
7264 // WebAssembly uses long long for int_least64_t and int_fast64_t.
7265 return BitWidth == 64
7266 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
7267 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
7271 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = {
7272 #define BUILTIN(ID, TYPE, ATTRS) \
7273 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7274 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
7275 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
7276 #include "clang/Basic/BuiltinsWebAssembly.def"
7279 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo {
7281 explicit WebAssembly32TargetInfo(const llvm::Triple &T)
7282 : WebAssemblyTargetInfo(T) {
7283 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
7284 DataLayoutString = "e-p:32:32-i64:64-n32:64-S128";
7288 void getTargetDefines(const LangOptions &Opts,
7289 MacroBuilder &Builder) const override {
7290 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
7291 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false);
7295 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo {
7297 explicit WebAssembly64TargetInfo(const llvm::Triple &T)
7298 : WebAssemblyTargetInfo(T) {
7299 LongAlign = LongWidth = 64;
7300 PointerAlign = PointerWidth = 64;
7301 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7302 DataLayoutString = "e-p:64:64-i64:64-n32:64-S128";
7306 void getTargetDefines(const LangOptions &Opts,
7307 MacroBuilder &Builder) const override {
7308 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
7309 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false);
7313 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
7314 #define BUILTIN(ID, TYPE, ATTRS) \
7315 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7316 #include "clang/Basic/BuiltinsLe64.def"
7319 static const unsigned SPIRAddrSpaceMap[] = {
7322 2, // opencl_constant
7323 4, // opencl_generic
7328 class SPIRTargetInfo : public TargetInfo {
7330 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
7331 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
7332 "SPIR target must use unknown OS");
7333 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
7334 "SPIR target must use unknown environment type");
7336 TLSSupported = false;
7337 LongWidth = LongAlign = 64;
7338 AddrSpaceMap = &SPIRAddrSpaceMap;
7339 UseAddrSpaceMapMangling = true;
7340 // Define available target features
7341 // These must be defined in sorted order!
7342 NoAsmVariants = true;
7344 void getTargetDefines(const LangOptions &Opts,
7345 MacroBuilder &Builder) const override {
7346 DefineStd(Builder, "SPIR", Opts);
7348 bool hasFeature(StringRef Feature) const override {
7349 return Feature == "spir";
7352 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7353 const char *getClobbers() const override { return ""; }
7354 ArrayRef<const char *> getGCCRegNames() const override { return None; }
7355 bool validateAsmConstraint(const char *&Name,
7356 TargetInfo::ConstraintInfo &info) const override {
7359 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7362 BuiltinVaListKind getBuiltinVaListKind() const override {
7363 return TargetInfo::VoidPtrBuiltinVaList;
7366 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
7367 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK
7371 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
7372 return CC_SpirFunction;
7376 class SPIR32TargetInfo : public SPIRTargetInfo {
7378 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
7379 PointerWidth = PointerAlign = 32;
7380 SizeType = TargetInfo::UnsignedInt;
7381 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
7382 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
7383 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
7385 void getTargetDefines(const LangOptions &Opts,
7386 MacroBuilder &Builder) const override {
7387 DefineStd(Builder, "SPIR32", Opts);
7391 class SPIR64TargetInfo : public SPIRTargetInfo {
7393 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
7394 PointerWidth = PointerAlign = 64;
7395 SizeType = TargetInfo::UnsignedLong;
7396 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
7397 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
7398 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
7400 void getTargetDefines(const LangOptions &Opts,
7401 MacroBuilder &Builder) const override {
7402 DefineStd(Builder, "SPIR64", Opts);
7406 class XCoreTargetInfo : public TargetInfo {
7407 static const Builtin::Info BuiltinInfo[];
7409 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
7411 NoAsmVariants = true;
7414 DoubleAlign = LongDoubleAlign = 32;
7415 SizeType = UnsignedInt;
7416 PtrDiffType = SignedInt;
7417 IntPtrType = SignedInt;
7418 WCharType = UnsignedChar;
7419 WIntType = UnsignedInt;
7420 UseZeroLengthBitfieldAlignment = true;
7421 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
7422 "-f64:32-a:0:32-n32";
7424 void getTargetDefines(const LangOptions &Opts,
7425 MacroBuilder &Builder) const override {
7426 Builder.defineMacro("__XS1B__");
7428 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7429 return llvm::makeArrayRef(BuiltinInfo,
7430 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin);
7432 BuiltinVaListKind getBuiltinVaListKind() const override {
7433 return TargetInfo::VoidPtrBuiltinVaList;
7435 const char *getClobbers() const override {
7438 ArrayRef<const char *> getGCCRegNames() const override {
7439 static const char * const GCCRegNames[] = {
7440 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7441 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
7443 return llvm::makeArrayRef(GCCRegNames);
7445 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7448 bool validateAsmConstraint(const char *&Name,
7449 TargetInfo::ConstraintInfo &Info) const override {
7452 int getEHDataRegisterNumber(unsigned RegNo) const override {
7453 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
7454 return (RegNo < 2)? RegNo : -1;
7458 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
7459 #define BUILTIN(ID, TYPE, ATTRS) \
7460 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7461 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
7462 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
7463 #include "clang/Basic/BuiltinsXCore.def"
7466 // x86_32 Android target
7467 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
7469 AndroidX86_32TargetInfo(const llvm::Triple &Triple)
7470 : LinuxTargetInfo<X86_32TargetInfo>(Triple) {
7472 LongDoubleWidth = 64;
7473 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
7477 // x86_64 Android target
7478 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
7480 AndroidX86_64TargetInfo(const llvm::Triple &Triple)
7481 : LinuxTargetInfo<X86_64TargetInfo>(Triple) {
7482 LongDoubleFormat = &llvm::APFloat::IEEEquad;
7485 bool useFloat128ManglingForLongDouble() const override {
7489 } // end anonymous namespace
7491 //===----------------------------------------------------------------------===//
7493 //===----------------------------------------------------------------------===//
7495 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
7496 llvm::Triple::OSType os = Triple.getOS();
7498 switch (Triple.getArch()) {
7502 case llvm::Triple::xcore:
7503 return new XCoreTargetInfo(Triple);
7505 case llvm::Triple::hexagon:
7506 return new HexagonTargetInfo(Triple);
7508 case llvm::Triple::aarch64:
7509 if (Triple.isOSDarwin())
7510 return new DarwinAArch64TargetInfo(Triple);
7513 case llvm::Triple::CloudABI:
7514 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple);
7515 case llvm::Triple::FreeBSD:
7516 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
7517 case llvm::Triple::Linux:
7518 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
7519 case llvm::Triple::NetBSD:
7520 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
7522 return new AArch64leTargetInfo(Triple);
7525 case llvm::Triple::aarch64_be:
7527 case llvm::Triple::FreeBSD:
7528 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
7529 case llvm::Triple::Linux:
7530 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
7531 case llvm::Triple::NetBSD:
7532 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
7534 return new AArch64beTargetInfo(Triple);
7537 case llvm::Triple::arm:
7538 case llvm::Triple::thumb:
7539 if (Triple.isOSBinFormatMachO())
7540 return new DarwinARMTargetInfo(Triple);
7543 case llvm::Triple::Linux:
7544 return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
7545 case llvm::Triple::FreeBSD:
7546 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
7547 case llvm::Triple::NetBSD:
7548 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
7549 case llvm::Triple::OpenBSD:
7550 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
7551 case llvm::Triple::Bitrig:
7552 return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
7553 case llvm::Triple::RTEMS:
7554 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
7555 case llvm::Triple::NaCl:
7556 return new NaClTargetInfo<ARMleTargetInfo>(Triple);
7557 case llvm::Triple::Win32:
7558 switch (Triple.getEnvironment()) {
7559 case llvm::Triple::Cygnus:
7560 return new CygwinARMTargetInfo(Triple);
7561 case llvm::Triple::GNU:
7562 return new MinGWARMTargetInfo(Triple);
7563 case llvm::Triple::Itanium:
7564 return new ItaniumWindowsARMleTargetInfo(Triple);
7565 case llvm::Triple::MSVC:
7566 default: // Assume MSVC for unknown environments
7567 return new MicrosoftARMleTargetInfo(Triple);
7570 return new ARMleTargetInfo(Triple);
7573 case llvm::Triple::armeb:
7574 case llvm::Triple::thumbeb:
7575 if (Triple.isOSDarwin())
7576 return new DarwinARMTargetInfo(Triple);
7579 case llvm::Triple::Linux:
7580 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
7581 case llvm::Triple::FreeBSD:
7582 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
7583 case llvm::Triple::NetBSD:
7584 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
7585 case llvm::Triple::OpenBSD:
7586 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
7587 case llvm::Triple::Bitrig:
7588 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
7589 case llvm::Triple::RTEMS:
7590 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
7591 case llvm::Triple::NaCl:
7592 return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
7594 return new ARMbeTargetInfo(Triple);
7597 case llvm::Triple::bpfeb:
7598 case llvm::Triple::bpfel:
7599 return new BPFTargetInfo(Triple);
7601 case llvm::Triple::msp430:
7602 return new MSP430TargetInfo(Triple);
7604 case llvm::Triple::mips:
7606 case llvm::Triple::Linux:
7607 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
7608 case llvm::Triple::RTEMS:
7609 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
7610 case llvm::Triple::FreeBSD:
7611 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
7612 case llvm::Triple::NetBSD:
7613 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
7615 return new Mips32EBTargetInfo(Triple);
7618 case llvm::Triple::mipsel:
7620 case llvm::Triple::Linux:
7621 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
7622 case llvm::Triple::RTEMS:
7623 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
7624 case llvm::Triple::FreeBSD:
7625 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
7626 case llvm::Triple::NetBSD:
7627 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
7628 case llvm::Triple::NaCl:
7629 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple);
7631 return new Mips32ELTargetInfo(Triple);
7634 case llvm::Triple::mips64:
7636 case llvm::Triple::Linux:
7637 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
7638 case llvm::Triple::RTEMS:
7639 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
7640 case llvm::Triple::FreeBSD:
7641 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7642 case llvm::Triple::NetBSD:
7643 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7644 case llvm::Triple::OpenBSD:
7645 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7647 return new Mips64EBTargetInfo(Triple);
7650 case llvm::Triple::mips64el:
7652 case llvm::Triple::Linux:
7653 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
7654 case llvm::Triple::RTEMS:
7655 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
7656 case llvm::Triple::FreeBSD:
7657 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7658 case llvm::Triple::NetBSD:
7659 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7660 case llvm::Triple::OpenBSD:
7661 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7663 return new Mips64ELTargetInfo(Triple);
7666 case llvm::Triple::le32:
7668 case llvm::Triple::NaCl:
7669 return new NaClTargetInfo<PNaClTargetInfo>(Triple);
7674 case llvm::Triple::le64:
7675 return new Le64TargetInfo(Triple);
7677 case llvm::Triple::ppc:
7678 if (Triple.isOSDarwin())
7679 return new DarwinPPC32TargetInfo(Triple);
7681 case llvm::Triple::Linux:
7682 return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
7683 case llvm::Triple::FreeBSD:
7684 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
7685 case llvm::Triple::NetBSD:
7686 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
7687 case llvm::Triple::OpenBSD:
7688 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
7689 case llvm::Triple::RTEMS:
7690 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
7692 return new PPC32TargetInfo(Triple);
7695 case llvm::Triple::ppc64:
7696 if (Triple.isOSDarwin())
7697 return new DarwinPPC64TargetInfo(Triple);
7699 case llvm::Triple::Linux:
7700 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7701 case llvm::Triple::Lv2:
7702 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
7703 case llvm::Triple::FreeBSD:
7704 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
7705 case llvm::Triple::NetBSD:
7706 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7708 return new PPC64TargetInfo(Triple);
7711 case llvm::Triple::ppc64le:
7713 case llvm::Triple::Linux:
7714 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7715 case llvm::Triple::NetBSD:
7716 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7718 return new PPC64TargetInfo(Triple);
7721 case llvm::Triple::nvptx:
7722 return new NVPTX32TargetInfo(Triple);
7723 case llvm::Triple::nvptx64:
7724 return new NVPTX64TargetInfo(Triple);
7726 case llvm::Triple::amdgcn:
7727 case llvm::Triple::r600:
7728 return new AMDGPUTargetInfo(Triple);
7730 case llvm::Triple::sparc:
7732 case llvm::Triple::Linux:
7733 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
7734 case llvm::Triple::Solaris:
7735 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple);
7736 case llvm::Triple::NetBSD:
7737 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
7738 case llvm::Triple::OpenBSD:
7739 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
7740 case llvm::Triple::RTEMS:
7741 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
7743 return new SparcV8TargetInfo(Triple);
7746 // The 'sparcel' architecture copies all the above cases except for Solaris.
7747 case llvm::Triple::sparcel:
7749 case llvm::Triple::Linux:
7750 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple);
7751 case llvm::Triple::NetBSD:
7752 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7753 case llvm::Triple::OpenBSD:
7754 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7755 case llvm::Triple::RTEMS:
7756 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple);
7758 return new SparcV8elTargetInfo(Triple);
7761 case llvm::Triple::sparcv9:
7763 case llvm::Triple::Linux:
7764 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
7765 case llvm::Triple::Solaris:
7766 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
7767 case llvm::Triple::NetBSD:
7768 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
7769 case llvm::Triple::OpenBSD:
7770 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
7771 case llvm::Triple::FreeBSD:
7772 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
7774 return new SparcV9TargetInfo(Triple);
7777 case llvm::Triple::systemz:
7779 case llvm::Triple::Linux:
7780 return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
7782 return new SystemZTargetInfo(Triple);
7785 case llvm::Triple::tce:
7786 return new TCETargetInfo(Triple);
7788 case llvm::Triple::x86:
7789 if (Triple.isOSDarwin())
7790 return new DarwinI386TargetInfo(Triple);
7793 case llvm::Triple::CloudABI:
7794 return new CloudABITargetInfo<X86_32TargetInfo>(Triple);
7795 case llvm::Triple::Linux: {
7796 switch (Triple.getEnvironment()) {
7798 return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
7799 case llvm::Triple::Android:
7800 return new AndroidX86_32TargetInfo(Triple);
7803 case llvm::Triple::DragonFly:
7804 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
7805 case llvm::Triple::NetBSD:
7806 return new NetBSDI386TargetInfo(Triple);
7807 case llvm::Triple::OpenBSD:
7808 return new OpenBSDI386TargetInfo(Triple);
7809 case llvm::Triple::Bitrig:
7810 return new BitrigI386TargetInfo(Triple);
7811 case llvm::Triple::FreeBSD:
7812 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7813 case llvm::Triple::KFreeBSD:
7814 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7815 case llvm::Triple::Minix:
7816 return new MinixTargetInfo<X86_32TargetInfo>(Triple);
7817 case llvm::Triple::Solaris:
7818 return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
7819 case llvm::Triple::Win32: {
7820 switch (Triple.getEnvironment()) {
7821 case llvm::Triple::Cygnus:
7822 return new CygwinX86_32TargetInfo(Triple);
7823 case llvm::Triple::GNU:
7824 return new MinGWX86_32TargetInfo(Triple);
7825 case llvm::Triple::Itanium:
7826 case llvm::Triple::MSVC:
7827 default: // Assume MSVC for unknown environments
7828 return new MicrosoftX86_32TargetInfo(Triple);
7831 case llvm::Triple::Haiku:
7832 return new HaikuX86_32TargetInfo(Triple);
7833 case llvm::Triple::RTEMS:
7834 return new RTEMSX86_32TargetInfo(Triple);
7835 case llvm::Triple::NaCl:
7836 return new NaClTargetInfo<X86_32TargetInfo>(Triple);
7837 case llvm::Triple::ELFIAMCU:
7838 return new MCUX86_32TargetInfo(Triple);
7840 return new X86_32TargetInfo(Triple);
7843 case llvm::Triple::x86_64:
7844 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
7845 return new DarwinX86_64TargetInfo(Triple);
7848 case llvm::Triple::CloudABI:
7849 return new CloudABITargetInfo<X86_64TargetInfo>(Triple);
7850 case llvm::Triple::Linux: {
7851 switch (Triple.getEnvironment()) {
7853 return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
7854 case llvm::Triple::Android:
7855 return new AndroidX86_64TargetInfo(Triple);
7858 case llvm::Triple::DragonFly:
7859 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
7860 case llvm::Triple::NetBSD:
7861 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
7862 case llvm::Triple::OpenBSD:
7863 return new OpenBSDX86_64TargetInfo(Triple);
7864 case llvm::Triple::Bitrig:
7865 return new BitrigX86_64TargetInfo(Triple);
7866 case llvm::Triple::FreeBSD:
7867 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7868 case llvm::Triple::KFreeBSD:
7869 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7870 case llvm::Triple::Solaris:
7871 return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
7872 case llvm::Triple::Win32: {
7873 switch (Triple.getEnvironment()) {
7874 case llvm::Triple::Cygnus:
7875 return new CygwinX86_64TargetInfo(Triple);
7876 case llvm::Triple::GNU:
7877 return new MinGWX86_64TargetInfo(Triple);
7878 case llvm::Triple::MSVC:
7879 default: // Assume MSVC for unknown environments
7880 return new MicrosoftX86_64TargetInfo(Triple);
7883 case llvm::Triple::NaCl:
7884 return new NaClTargetInfo<X86_64TargetInfo>(Triple);
7885 case llvm::Triple::PS4:
7886 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple);
7888 return new X86_64TargetInfo(Triple);
7891 case llvm::Triple::spir: {
7892 if (Triple.getOS() != llvm::Triple::UnknownOS ||
7893 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7895 return new SPIR32TargetInfo(Triple);
7897 case llvm::Triple::spir64: {
7898 if (Triple.getOS() != llvm::Triple::UnknownOS ||
7899 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7901 return new SPIR64TargetInfo(Triple);
7903 case llvm::Triple::wasm32:
7904 if (!(Triple == llvm::Triple("wasm32-unknown-unknown")))
7906 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple);
7907 case llvm::Triple::wasm64:
7908 if (!(Triple == llvm::Triple("wasm64-unknown-unknown")))
7910 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple);
7914 /// CreateTargetInfo - Return the target info object for the specified target
7917 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
7918 const std::shared_ptr<TargetOptions> &Opts) {
7919 llvm::Triple Triple(Opts->Triple);
7921 // Construct the target
7922 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
7924 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
7927 Target->TargetOpts = Opts;
7929 // Set the target CPU if specified.
7930 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
7931 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
7935 // Set the target ABI if specified.
7936 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
7937 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
7941 // Set the fp math unit.
7942 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
7943 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
7947 // Compute the default target features, we need the target to handle this
7948 // because features may have dependencies on one another.
7949 llvm::StringMap<bool> Features;
7950 if (!Target->initFeatureMap(Features, Diags, Opts->CPU,
7951 Opts->FeaturesAsWritten))
7954 // Add the features to the compile options.
7955 Opts->Features.clear();
7956 for (const auto &F : Features)
7957 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str());
7959 if (!Target->handleTargetFeatures(Opts->Features, Diags))
7962 return Target.release();