1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/MC/MCSectionMachO.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/TargetParser.h"
33 using namespace clang;
35 //===----------------------------------------------------------------------===//
36 // Common code shared among targets.
37 //===----------------------------------------------------------------------===//
39 /// DefineStd - Define a macro name and standard variants. For example if
40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
43 const LangOptions &Opts) {
44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
47 // in the user's namespace.
49 Builder.defineMacro(MacroName);
52 Builder.defineMacro("__" + MacroName);
55 Builder.defineMacro("__" + MacroName + "__");
58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
60 Builder.defineMacro("__" + CPUName);
61 Builder.defineMacro("__" + CPUName + "__");
63 Builder.defineMacro("__tune_" + CPUName + "__");
66 //===----------------------------------------------------------------------===//
67 // Defines specific to certain operating systems.
68 //===----------------------------------------------------------------------===//
71 template<typename TgtInfo>
72 class OSTargetInfo : public TgtInfo {
74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
75 MacroBuilder &Builder) const=0;
77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
78 void getTargetDefines(const LangOptions &Opts,
79 MacroBuilder &Builder) const override {
80 TgtInfo::getTargetDefines(Opts, Builder);
81 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
85 } // end anonymous namespace
88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
89 const llvm::Triple &Triple,
90 StringRef &PlatformName,
91 VersionTuple &PlatformMinVersion) {
92 Builder.defineMacro("__APPLE_CC__", "6000");
93 Builder.defineMacro("__APPLE__");
94 Builder.defineMacro("OBJC_NEW_PROPERTIES");
95 // AddressSanitizer doesn't play well with source fortification, which is on
96 // by default on Darwin.
97 if (Opts.Sanitize.has(SanitizerKind::Address))
98 Builder.defineMacro("_FORTIFY_SOURCE", "0");
100 if (!Opts.ObjCAutoRefCount) {
101 // __weak is always defined, for use in blocks and with objc pointers.
102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
104 // Darwin defines __strong even in C mode (just to nothing).
105 if (Opts.getGC() != LangOptions::NonGC)
106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
108 Builder.defineMacro("__strong", "");
110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even
111 // allow this in C, since one might have block pointers in structs that
112 // are used in pure C code and in Objective-C ARC.
113 Builder.defineMacro("__unsafe_unretained", "");
117 Builder.defineMacro("__STATIC__");
119 Builder.defineMacro("__DYNAMIC__");
121 if (Opts.POSIXThreads)
122 Builder.defineMacro("_REENTRANT");
124 // Get the platform type and version number from the triple.
125 unsigned Maj, Min, Rev;
126 if (Triple.isMacOSX()) {
127 Triple.getMacOSXVersion(Maj, Min, Rev);
128 PlatformName = "macosx";
130 Triple.getOSVersion(Maj, Min, Rev);
131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
134 // If -target arch-pc-win32-macho option specified, we're
135 // generating code for Win32 ABI. No need to emit
136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
137 if (PlatformName == "win32") {
138 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
142 // Set the appropriate OS version define.
143 if (Triple.isiOS()) {
144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
147 Str[1] = '0' + (Min / 10);
148 Str[2] = '0' + (Min % 10);
149 Str[3] = '0' + (Rev / 10);
150 Str[4] = '0' + (Rev % 10);
152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
154 } else if (Triple.isMacOSX()) {
155 // Note that the Driver allows versions which aren't representable in the
156 // define (because we only get a single digit for the minor and micro
157 // revision numbers). So, we limit them to the maximum representable
159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
161 if (Maj < 10 || (Maj == 10 && Min < 10)) {
162 Str[0] = '0' + (Maj / 10);
163 Str[1] = '0' + (Maj % 10);
164 Str[2] = '0' + std::min(Min, 9U);
165 Str[3] = '0' + std::min(Rev, 9U);
168 // Handle versions > 10.9.
169 Str[0] = '0' + (Maj / 10);
170 Str[1] = '0' + (Maj % 10);
171 Str[2] = '0' + (Min / 10);
172 Str[3] = '0' + (Min % 10);
173 Str[4] = '0' + (Rev / 10);
174 Str[5] = '0' + (Rev % 10);
177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
180 // Tell users about the kernel if there is one.
181 if (Triple.isOSDarwin())
182 Builder.defineMacro("__MACH__");
184 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
189 template <typename Target>
190 class CloudABITargetInfo : public OSTargetInfo<Target> {
192 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
193 MacroBuilder &Builder) const override {
194 Builder.defineMacro("__CloudABI__");
195 Builder.defineMacro("__ELF__");
197 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
198 Builder.defineMacro("__STDC_ISO_10646__", "201206L");
199 Builder.defineMacro("__STDC_UTF_16__");
200 Builder.defineMacro("__STDC_UTF_32__");
204 CloudABITargetInfo(const llvm::Triple &Triple)
205 : OSTargetInfo<Target>(Triple) {
206 this->UserLabelPrefix = "";
210 template<typename Target>
211 class DarwinTargetInfo : public OSTargetInfo<Target> {
213 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
214 MacroBuilder &Builder) const override {
215 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
216 this->PlatformMinVersion);
220 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
221 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
222 this->MCountName = "\01mcount";
225 std::string isValidSectionSpecifier(StringRef SR) const override {
226 // Let MCSectionMachO validate this.
227 StringRef Segment, Section;
228 unsigned TAA, StubSize;
230 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
231 TAA, HasTAA, StubSize);
234 const char *getStaticInitSectionSpecifier() const override {
235 // FIXME: We should return 0 when building kexts.
236 return "__TEXT,__StaticInit,regular,pure_instructions";
239 /// Darwin does not support protected visibility. Darwin's "default"
240 /// is very similar to ELF's "protected"; Darwin requires a "weak"
241 /// attribute on declarations that can be dynamically replaced.
242 bool hasProtectedVisibility() const override {
248 // DragonFlyBSD Target
249 template<typename Target>
250 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
252 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
253 MacroBuilder &Builder) const override {
254 // DragonFly defines; list based off of gcc output
255 Builder.defineMacro("__DragonFly__");
256 Builder.defineMacro("__DragonFly_cc_version", "100001");
257 Builder.defineMacro("__ELF__");
258 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
259 Builder.defineMacro("__tune_i386__");
260 DefineStd(Builder, "unix", Opts);
263 DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
264 : OSTargetInfo<Target>(Triple) {
265 this->UserLabelPrefix = "";
267 switch (Triple.getArch()) {
269 case llvm::Triple::x86:
270 case llvm::Triple::x86_64:
271 this->MCountName = ".mcount";
278 template<typename Target>
279 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
281 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
282 MacroBuilder &Builder) const override {
283 // FreeBSD defines; list based off of gcc output
285 unsigned Release = Triple.getOSMajorVersion();
289 Builder.defineMacro("__FreeBSD__", Twine(Release));
290 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
291 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
292 DefineStd(Builder, "unix", Opts);
293 Builder.defineMacro("__ELF__");
295 // On FreeBSD, wchar_t contains the number of the code point as
296 // used by the character set of the locale. These character sets are
297 // not necessarily a superset of ASCII.
299 // FIXME: This is wrong; the macro refers to the numerical values
300 // of wchar_t *literals*, which are not locale-dependent. However,
301 // FreeBSD systems apparently depend on us getting this wrong, and
302 // setting this to 1 is conforming even if all the basic source
303 // character literals have the same encoding as char and wchar_t.
304 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
307 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
308 this->UserLabelPrefix = "";
310 switch (Triple.getArch()) {
312 case llvm::Triple::x86:
313 case llvm::Triple::x86_64:
314 this->MCountName = ".mcount";
316 case llvm::Triple::mips:
317 case llvm::Triple::mipsel:
318 case llvm::Triple::ppc:
319 case llvm::Triple::ppc64:
320 case llvm::Triple::ppc64le:
321 this->MCountName = "_mcount";
323 case llvm::Triple::arm:
324 this->MCountName = "__mcount";
330 // GNU/kFreeBSD Target
331 template<typename Target>
332 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
334 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
335 MacroBuilder &Builder) const override {
336 // GNU/kFreeBSD defines; list based off of gcc output
338 DefineStd(Builder, "unix", Opts);
339 Builder.defineMacro("__FreeBSD_kernel__");
340 Builder.defineMacro("__GLIBC__");
341 Builder.defineMacro("__ELF__");
342 if (Opts.POSIXThreads)
343 Builder.defineMacro("_REENTRANT");
345 Builder.defineMacro("_GNU_SOURCE");
348 KFreeBSDTargetInfo(const llvm::Triple &Triple)
349 : OSTargetInfo<Target>(Triple) {
350 this->UserLabelPrefix = "";
355 template<typename Target>
356 class MinixTargetInfo : public OSTargetInfo<Target> {
358 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
359 MacroBuilder &Builder) const override {
362 Builder.defineMacro("__minix", "3");
363 Builder.defineMacro("_EM_WSIZE", "4");
364 Builder.defineMacro("_EM_PSIZE", "4");
365 Builder.defineMacro("_EM_SSIZE", "2");
366 Builder.defineMacro("_EM_LSIZE", "4");
367 Builder.defineMacro("_EM_FSIZE", "4");
368 Builder.defineMacro("_EM_DSIZE", "8");
369 Builder.defineMacro("__ELF__");
370 DefineStd(Builder, "unix", Opts);
373 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
374 this->UserLabelPrefix = "";
379 template<typename Target>
380 class LinuxTargetInfo : public OSTargetInfo<Target> {
382 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
383 MacroBuilder &Builder) const override {
384 // Linux defines; list based off of gcc output
385 DefineStd(Builder, "unix", Opts);
386 DefineStd(Builder, "linux", Opts);
387 Builder.defineMacro("__gnu_linux__");
388 Builder.defineMacro("__ELF__");
389 if (Triple.getEnvironment() == llvm::Triple::Android) {
390 Builder.defineMacro("__ANDROID__", "1");
391 unsigned Maj, Min, Rev;
392 Triple.getEnvironmentVersion(Maj, Min, Rev);
393 this->PlatformName = "android";
394 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
396 if (Opts.POSIXThreads)
397 Builder.defineMacro("_REENTRANT");
399 Builder.defineMacro("_GNU_SOURCE");
402 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
403 this->UserLabelPrefix = "";
404 this->WIntType = TargetInfo::UnsignedInt;
406 switch (Triple.getArch()) {
409 case llvm::Triple::ppc:
410 case llvm::Triple::ppc64:
411 case llvm::Triple::ppc64le:
412 this->MCountName = "_mcount";
417 const char *getStaticInitSectionSpecifier() const override {
418 return ".text.startup";
423 template<typename Target>
424 class NetBSDTargetInfo : public OSTargetInfo<Target> {
426 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
427 MacroBuilder &Builder) const override {
428 // NetBSD defines; list based off of gcc output
429 Builder.defineMacro("__NetBSD__");
430 Builder.defineMacro("__unix__");
431 Builder.defineMacro("__ELF__");
432 if (Opts.POSIXThreads)
433 Builder.defineMacro("_POSIX_THREADS");
435 switch (Triple.getArch()) {
438 case llvm::Triple::arm:
439 case llvm::Triple::armeb:
440 case llvm::Triple::thumb:
441 case llvm::Triple::thumbeb:
442 Builder.defineMacro("__ARM_DWARF_EH__");
447 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
448 this->UserLabelPrefix = "";
449 this->MCountName = "_mcount";
454 template<typename Target>
455 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
457 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
458 MacroBuilder &Builder) const override {
459 // OpenBSD defines; list based off of gcc output
461 Builder.defineMacro("__OpenBSD__");
462 DefineStd(Builder, "unix", Opts);
463 Builder.defineMacro("__ELF__");
464 if (Opts.POSIXThreads)
465 Builder.defineMacro("_REENTRANT");
468 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
469 this->UserLabelPrefix = "";
470 this->TLSSupported = false;
472 switch (Triple.getArch()) {
474 case llvm::Triple::x86:
475 case llvm::Triple::x86_64:
476 case llvm::Triple::arm:
477 case llvm::Triple::sparc:
478 this->MCountName = "__mcount";
480 case llvm::Triple::mips64:
481 case llvm::Triple::mips64el:
482 case llvm::Triple::ppc:
483 case llvm::Triple::sparcv9:
484 this->MCountName = "_mcount";
491 template<typename Target>
492 class BitrigTargetInfo : public OSTargetInfo<Target> {
494 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495 MacroBuilder &Builder) const override {
496 // Bitrig defines; list based off of gcc output
498 Builder.defineMacro("__Bitrig__");
499 DefineStd(Builder, "unix", Opts);
500 Builder.defineMacro("__ELF__");
501 if (Opts.POSIXThreads)
502 Builder.defineMacro("_REENTRANT");
504 switch (Triple.getArch()) {
507 case llvm::Triple::arm:
508 case llvm::Triple::armeb:
509 case llvm::Triple::thumb:
510 case llvm::Triple::thumbeb:
511 Builder.defineMacro("__ARM_DWARF_EH__");
516 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
517 this->UserLabelPrefix = "";
518 this->MCountName = "__mcount";
523 template<typename Target>
524 class PSPTargetInfo : public OSTargetInfo<Target> {
526 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
527 MacroBuilder &Builder) const override {
528 // PSP defines; list based on the output of the pspdev gcc toolchain.
529 Builder.defineMacro("PSP");
530 Builder.defineMacro("_PSP");
531 Builder.defineMacro("__psp__");
532 Builder.defineMacro("__ELF__");
535 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
536 this->UserLabelPrefix = "";
541 template<typename Target>
542 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
544 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
545 MacroBuilder &Builder) const override {
547 Builder.defineMacro("__PPC__");
548 Builder.defineMacro("__PPU__");
549 Builder.defineMacro("__CELLOS_LV2__");
550 Builder.defineMacro("__ELF__");
551 Builder.defineMacro("__LP32__");
552 Builder.defineMacro("_ARCH_PPC64");
553 Builder.defineMacro("__powerpc64__");
556 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
557 this->UserLabelPrefix = "";
558 this->LongWidth = this->LongAlign = 32;
559 this->PointerWidth = this->PointerAlign = 32;
560 this->IntMaxType = TargetInfo::SignedLongLong;
561 this->Int64Type = TargetInfo::SignedLongLong;
562 this->SizeType = TargetInfo::UnsignedInt;
563 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
567 template <typename Target>
568 class PS4OSTargetInfo : public OSTargetInfo<Target> {
570 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
571 MacroBuilder &Builder) const override {
572 Builder.defineMacro("__FreeBSD__", "9");
573 Builder.defineMacro("__FreeBSD_cc_version", "900001");
574 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
575 DefineStd(Builder, "unix", Opts);
576 Builder.defineMacro("__ELF__");
577 Builder.defineMacro("__PS4__");
580 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
581 this->WCharType = this->UnsignedShort;
583 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits).
584 this->MaxTLSAlign = 256;
585 this->UserLabelPrefix = "";
587 switch (Triple.getArch()) {
589 case llvm::Triple::x86_64:
590 this->MCountName = ".mcount";
597 template<typename Target>
598 class SolarisTargetInfo : public OSTargetInfo<Target> {
600 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
601 MacroBuilder &Builder) const override {
602 DefineStd(Builder, "sun", Opts);
603 DefineStd(Builder, "unix", Opts);
604 Builder.defineMacro("__ELF__");
605 Builder.defineMacro("__svr4__");
606 Builder.defineMacro("__SVR4");
607 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
608 // newer, but to 500 for everything else. feature_test.h has a check to
609 // ensure that you are not using C99 with an old version of X/Open or C89
610 // with a new version.
612 Builder.defineMacro("_XOPEN_SOURCE", "600");
614 Builder.defineMacro("_XOPEN_SOURCE", "500");
616 Builder.defineMacro("__C99FEATURES__");
617 Builder.defineMacro("_LARGEFILE_SOURCE");
618 Builder.defineMacro("_LARGEFILE64_SOURCE");
619 Builder.defineMacro("__EXTENSIONS__");
620 Builder.defineMacro("_REENTRANT");
623 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
624 this->UserLabelPrefix = "";
625 this->WCharType = this->SignedInt;
626 // FIXME: WIntType should be SignedLong
631 template<typename Target>
632 class WindowsTargetInfo : public OSTargetInfo<Target> {
634 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
635 MacroBuilder &Builder) const override {
636 Builder.defineMacro("_WIN32");
638 void getVisualStudioDefines(const LangOptions &Opts,
639 MacroBuilder &Builder) const {
640 if (Opts.CPlusPlus) {
642 Builder.defineMacro("_CPPRTTI");
644 if (Opts.CXXExceptions)
645 Builder.defineMacro("_CPPUNWIND");
648 if (!Opts.CharIsSigned)
649 Builder.defineMacro("_CHAR_UNSIGNED");
651 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
652 // but it works for now.
653 if (Opts.POSIXThreads)
654 Builder.defineMacro("_MT");
656 if (Opts.MSCompatibilityVersion) {
657 Builder.defineMacro("_MSC_VER",
658 Twine(Opts.MSCompatibilityVersion / 100000));
659 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
660 // FIXME We cannot encode the revision information into 32-bits
661 Builder.defineMacro("_MSC_BUILD", Twine(1));
663 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
664 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
667 if (Opts.MicrosoftExt) {
668 Builder.defineMacro("_MSC_EXTENSIONS");
670 if (Opts.CPlusPlus11) {
671 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
672 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
673 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
677 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
681 WindowsTargetInfo(const llvm::Triple &Triple)
682 : OSTargetInfo<Target>(Triple) {}
685 template <typename Target>
686 class NaClTargetInfo : public OSTargetInfo<Target> {
688 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
689 MacroBuilder &Builder) const override {
690 if (Opts.POSIXThreads)
691 Builder.defineMacro("_REENTRANT");
693 Builder.defineMacro("_GNU_SOURCE");
695 DefineStd(Builder, "unix", Opts);
696 Builder.defineMacro("__ELF__");
697 Builder.defineMacro("__native_client__");
701 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
702 this->UserLabelPrefix = "";
703 this->LongAlign = 32;
704 this->LongWidth = 32;
705 this->PointerAlign = 32;
706 this->PointerWidth = 32;
707 this->IntMaxType = TargetInfo::SignedLongLong;
708 this->Int64Type = TargetInfo::SignedLongLong;
709 this->DoubleAlign = 64;
710 this->LongDoubleWidth = 64;
711 this->LongDoubleAlign = 64;
712 this->LongLongWidth = 64;
713 this->LongLongAlign = 64;
714 this->SizeType = TargetInfo::UnsignedInt;
715 this->PtrDiffType = TargetInfo::SignedInt;
716 this->IntPtrType = TargetInfo::SignedInt;
717 // RegParmMax is inherited from the underlying architecture
718 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
719 if (Triple.getArch() == llvm::Triple::arm) {
720 // Handled in ARM's setABI().
721 } else if (Triple.getArch() == llvm::Triple::x86) {
722 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
723 } else if (Triple.getArch() == llvm::Triple::x86_64) {
724 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
725 } else if (Triple.getArch() == llvm::Triple::mipsel) {
726 // Handled on mips' setDescriptionString.
728 assert(Triple.getArch() == llvm::Triple::le32);
729 this->DescriptionString = "e-p:32:32-i64:64";
734 //===----------------------------------------------------------------------===//
735 // Specific target implementations.
736 //===----------------------------------------------------------------------===//
738 // PPC abstract base class
739 class PPCTargetInfo : public TargetInfo {
740 static const Builtin::Info BuiltinInfo[];
741 static const char * const GCCRegNames[];
742 static const TargetInfo::GCCRegAlias GCCRegAliases[];
745 // Target cpu features.
759 PPCTargetInfo(const llvm::Triple &Triple)
760 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
761 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
762 HasBPERMD(false), HasExtDiv(false) {
763 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
764 SimdDefaultAlign = 128;
765 LongDoubleWidth = LongDoubleAlign = 128;
766 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
769 /// \brief Flags for architecture specific defines.
772 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
773 ArchDefinePpcgr = 1 << 1,
774 ArchDefinePpcsq = 1 << 2,
775 ArchDefine440 = 1 << 3,
776 ArchDefine603 = 1 << 4,
777 ArchDefine604 = 1 << 5,
778 ArchDefinePwr4 = 1 << 6,
779 ArchDefinePwr5 = 1 << 7,
780 ArchDefinePwr5x = 1 << 8,
781 ArchDefinePwr6 = 1 << 9,
782 ArchDefinePwr6x = 1 << 10,
783 ArchDefinePwr7 = 1 << 11,
784 ArchDefinePwr8 = 1 << 12,
785 ArchDefineA2 = 1 << 13,
786 ArchDefineA2q = 1 << 14
789 // Note: GCC recognizes the following additional cpus:
790 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
791 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
793 bool setCPU(const std::string &Name) override {
794 bool CPUKnown = llvm::StringSwitch<bool>(Name)
795 .Case("generic", true)
817 .Case("e500mc", true)
819 .Case("power3", true)
821 .Case("power4", true)
823 .Case("power5", true)
825 .Case("power5x", true)
827 .Case("power6", true)
829 .Case("power6x", true)
831 .Case("power7", true)
833 .Case("power8", true)
835 .Case("powerpc", true)
837 .Case("powerpc64", true)
839 .Case("powerpc64le", true)
840 .Case("ppc64le", true)
850 StringRef getABI() const override { return ABI; }
852 void getTargetBuiltins(const Builtin::Info *&Records,
853 unsigned &NumRecords) const override {
854 Records = BuiltinInfo;
855 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
858 bool isCLZForZeroUndef() const override { return false; }
860 void getTargetDefines(const LangOptions &Opts,
861 MacroBuilder &Builder) const override;
863 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
865 bool handleTargetFeatures(std::vector<std::string> &Features,
866 DiagnosticsEngine &Diags) override;
867 bool hasFeature(StringRef Feature) const override;
868 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
869 bool Enabled) const override;
871 void getGCCRegNames(const char * const *&Names,
872 unsigned &NumNames) const override;
873 void getGCCRegAliases(const GCCRegAlias *&Aliases,
874 unsigned &NumAliases) const override;
875 bool validateAsmConstraint(const char *&Name,
876 TargetInfo::ConstraintInfo &Info) const override {
878 default: return false;
881 case 'b': // Base register
882 case 'f': // Floating point register
883 Info.setAllowsRegister();
885 // FIXME: The following are added to allow parsing.
886 // I just took a guess at what the actions should be.
887 // Also, is more specific checking needed? I.e. specific registers?
888 case 'd': // Floating point register (containing 64-bit value)
889 case 'v': // Altivec vector register
890 Info.setAllowsRegister();
894 case 'd':// VSX vector register to hold vector double data
895 case 'f':// VSX vector register to hold vector float data
896 case 's':// VSX vector register to hold scalar float data
897 case 'a':// Any VSX register
898 case 'c':// An individual CR bit
903 Info.setAllowsRegister();
904 Name++; // Skip over 'w'.
906 case 'h': // `MQ', `CTR', or `LINK' register
907 case 'q': // `MQ' register
908 case 'c': // `CTR' register
909 case 'l': // `LINK' register
910 case 'x': // `CR' register (condition register) number 0
911 case 'y': // `CR' register (condition register)
912 case 'z': // `XER[CA]' carry bit (part of the XER register)
913 Info.setAllowsRegister();
915 case 'I': // Signed 16-bit constant
916 case 'J': // Unsigned 16-bit constant shifted left 16 bits
917 // (use `L' instead for SImode constants)
918 case 'K': // Unsigned 16-bit constant
919 case 'L': // Signed 16-bit constant shifted left 16 bits
920 case 'M': // Constant larger than 31
921 case 'N': // Exact power of 2
922 case 'P': // Constant whose negation is a signed 16-bit constant
923 case 'G': // Floating point constant that can be loaded into a
924 // register with one instruction per word
925 case 'H': // Integer/Floating point constant that can be loaded
926 // into a register using three instructions
928 case 'm': // Memory operand. Note that on PowerPC targets, m can
929 // include addresses that update the base register. It
930 // is therefore only safe to use `m' in an asm statement
931 // if that asm statement accesses the operand exactly once.
932 // The asm statement must also use `%U<opno>' as a
933 // placeholder for the "update" flag in the corresponding
934 // load or store instruction. For example:
935 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
937 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
938 // is not. Use es rather than m if you don't want the base
939 // register to be updated.
943 // es: A "stable" memory operand; that is, one which does not
944 // include any automodification of the base register. Unlike
945 // `m', this constraint can be used in asm statements that
946 // might access the operand several times, or that might not
948 Info.setAllowsMemory();
949 Name++; // Skip over 'e'.
951 case 'Q': // Memory operand that is an offset from a register (it is
952 // usually better to use `m' or `es' in asm statements)
953 case 'Z': // Memory operand that is an indexed or indirect from a
954 // register (it is usually better to use `m' or `es' in
956 Info.setAllowsMemory();
957 Info.setAllowsRegister();
959 case 'R': // AIX TOC entry
960 case 'a': // Address operand that is an indexed or indirect from a
961 // register (`p' is preferable for asm statements)
962 case 'S': // Constant suitable as a 64-bit mask operand
963 case 'T': // Constant suitable as a 32-bit mask operand
964 case 'U': // System V Release 4 small data area reference
965 case 't': // AND masks that can be performed by two rldic{l, r}
967 case 'W': // Vector constant that does not require memory
968 case 'j': // Vector constant that is all zeros.
974 std::string convertConstraint(const char *&Constraint) const override {
976 switch (*Constraint) {
979 // Two-character constraint; add "^" hint for later parsing.
980 R = std::string("^") + std::string(Constraint, 2);
984 return TargetInfo::convertConstraint(Constraint);
988 const char *getClobbers() const override {
991 int getEHDataRegisterNumber(unsigned RegNo) const override {
992 if (RegNo == 0) return 3;
993 if (RegNo == 1) return 4;
997 bool hasSjLjLowering() const override {
1001 bool useFloat128ManglingForLongDouble() const override {
1002 return LongDoubleWidth == 128 &&
1003 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble &&
1004 getTriple().isOSBinFormatELF();
1008 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
1009 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1010 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1012 #include "clang/Basic/BuiltinsPPC.def"
1015 /// handleTargetFeatures - Perform initialization based on the user
1016 /// configured set of features.
1017 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1018 DiagnosticsEngine &Diags) {
1019 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
1020 // Ignore disabled features.
1021 if (Features[i][0] == '-')
1024 StringRef Feature = StringRef(Features[i]).substr(1);
1026 if (Feature == "vsx") {
1031 if (Feature == "bpermd") {
1036 if (Feature == "extdiv") {
1041 if (Feature == "power8-vector") {
1046 if (Feature == "crypto") {
1051 if (Feature == "direct-move") {
1052 HasDirectMove = true;
1056 if (Feature == "qpx") {
1061 if (Feature == "htm") {
1066 // TODO: Finish this list and add an assert that we've handled them
1069 if (!HasVSX && (HasP8Vector || HasDirectMove)) {
1071 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" <<
1073 else if (HasDirectMove)
1074 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" <<
1082 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1083 /// #defines that are not tied to a specific subtarget.
1084 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1085 MacroBuilder &Builder) const {
1086 // Target identification.
1087 Builder.defineMacro("__ppc__");
1088 Builder.defineMacro("__PPC__");
1089 Builder.defineMacro("_ARCH_PPC");
1090 Builder.defineMacro("__powerpc__");
1091 Builder.defineMacro("__POWERPC__");
1092 if (PointerWidth == 64) {
1093 Builder.defineMacro("_ARCH_PPC64");
1094 Builder.defineMacro("__powerpc64__");
1095 Builder.defineMacro("__ppc64__");
1096 Builder.defineMacro("__PPC64__");
1099 // Target properties.
1100 if (getTriple().getArch() == llvm::Triple::ppc64le) {
1101 Builder.defineMacro("_LITTLE_ENDIAN");
1103 if (getTriple().getOS() != llvm::Triple::NetBSD &&
1104 getTriple().getOS() != llvm::Triple::OpenBSD)
1105 Builder.defineMacro("_BIG_ENDIAN");
1109 if (ABI == "elfv1" || ABI == "elfv1-qpx")
1110 Builder.defineMacro("_CALL_ELF", "1");
1112 Builder.defineMacro("_CALL_ELF", "2");
1114 // Subtarget options.
1115 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1116 Builder.defineMacro("__REGISTER_PREFIX__", "");
1118 // FIXME: Should be controlled by command line option.
1119 if (LongDoubleWidth == 128)
1120 Builder.defineMacro("__LONG_DOUBLE_128__");
1123 Builder.defineMacro("__VEC__", "10206");
1124 Builder.defineMacro("__ALTIVEC__");
1127 // CPU identification.
1128 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1129 .Case("440", ArchDefineName)
1130 .Case("450", ArchDefineName | ArchDefine440)
1131 .Case("601", ArchDefineName)
1132 .Case("602", ArchDefineName | ArchDefinePpcgr)
1133 .Case("603", ArchDefineName | ArchDefinePpcgr)
1134 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1135 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1136 .Case("604", ArchDefineName | ArchDefinePpcgr)
1137 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1138 .Case("620", ArchDefineName | ArchDefinePpcgr)
1139 .Case("630", ArchDefineName | ArchDefinePpcgr)
1140 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1141 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1142 .Case("750", ArchDefineName | ArchDefinePpcgr)
1143 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1145 .Case("a2", ArchDefineA2)
1146 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1147 .Case("pwr3", ArchDefinePpcgr)
1148 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1149 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1151 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1152 | ArchDefinePpcgr | ArchDefinePpcsq)
1153 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1154 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1155 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1156 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1158 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1159 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1160 | ArchDefinePpcgr | ArchDefinePpcsq)
1161 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1162 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1163 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1164 .Case("power3", ArchDefinePpcgr)
1165 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1166 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1168 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1169 | ArchDefinePpcgr | ArchDefinePpcsq)
1170 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1171 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1172 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1173 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1175 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1176 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1177 | ArchDefinePpcgr | ArchDefinePpcsq)
1178 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1179 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1180 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1181 .Default(ArchDefineNone);
1183 if (defs & ArchDefineName)
1184 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1185 if (defs & ArchDefinePpcgr)
1186 Builder.defineMacro("_ARCH_PPCGR");
1187 if (defs & ArchDefinePpcsq)
1188 Builder.defineMacro("_ARCH_PPCSQ");
1189 if (defs & ArchDefine440)
1190 Builder.defineMacro("_ARCH_440");
1191 if (defs & ArchDefine603)
1192 Builder.defineMacro("_ARCH_603");
1193 if (defs & ArchDefine604)
1194 Builder.defineMacro("_ARCH_604");
1195 if (defs & ArchDefinePwr4)
1196 Builder.defineMacro("_ARCH_PWR4");
1197 if (defs & ArchDefinePwr5)
1198 Builder.defineMacro("_ARCH_PWR5");
1199 if (defs & ArchDefinePwr5x)
1200 Builder.defineMacro("_ARCH_PWR5X");
1201 if (defs & ArchDefinePwr6)
1202 Builder.defineMacro("_ARCH_PWR6");
1203 if (defs & ArchDefinePwr6x)
1204 Builder.defineMacro("_ARCH_PWR6X");
1205 if (defs & ArchDefinePwr7)
1206 Builder.defineMacro("_ARCH_PWR7");
1207 if (defs & ArchDefinePwr8)
1208 Builder.defineMacro("_ARCH_PWR8");
1209 if (defs & ArchDefineA2)
1210 Builder.defineMacro("_ARCH_A2");
1211 if (defs & ArchDefineA2q) {
1212 Builder.defineMacro("_ARCH_A2Q");
1213 Builder.defineMacro("_ARCH_QP");
1216 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1217 Builder.defineMacro("__bg__");
1218 Builder.defineMacro("__THW_BLUEGENE__");
1219 Builder.defineMacro("__bgq__");
1220 Builder.defineMacro("__TOS_BGQ__");
1224 Builder.defineMacro("__VSX__");
1226 Builder.defineMacro("__POWER8_VECTOR__");
1228 Builder.defineMacro("__CRYPTO__");
1230 Builder.defineMacro("__HTM__");
1231 if (getTriple().getArch() == llvm::Triple::ppc64le ||
1232 (defs & ArchDefinePwr8) || (CPU == "pwr8")) {
1233 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1234 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1235 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1236 if (PointerWidth == 64)
1237 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1240 // FIXME: The following are not yet generated here by Clang, but are
1241 // generated by GCC:
1244 // __RECIP_PRECISION__
1245 // __APPLE_ALTIVEC__
1254 // __CMODEL_MEDIUM__
1261 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1262 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1272 .Case("ppc64", true)
1273 .Case("ppc64le", true)
1276 Features["qpx"] = (CPU == "a2q");
1277 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1278 .Case("ppc64le", true)
1281 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1282 .Case("ppc64le", true)
1285 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1286 .Case("ppc64le", true)
1290 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1291 .Case("ppc64le", true)
1295 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1296 .Case("ppc64le", true)
1299 Features["vsx"] = llvm::StringSwitch<bool>(CPU)
1300 .Case("ppc64le", true)
1306 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1307 return llvm::StringSwitch<bool>(Feature)
1308 .Case("powerpc", true)
1309 .Case("vsx", HasVSX)
1310 .Case("power8-vector", HasP8Vector)
1311 .Case("crypto", HasP8Crypto)
1312 .Case("direct-move", HasDirectMove)
1313 .Case("qpx", HasQPX)
1314 .Case("htm", HasHTM)
1315 .Case("bpermd", HasBPERMD)
1316 .Case("extdiv", HasExtDiv)
1320 /* There is no clear way for the target to know which of the features in the
1321 final feature vector came from defaults and which are actually specified by
1322 the user. To that end, we use the fact that this function is not called on
1323 default features - only user specified ones. By the first time this
1324 function is called, the default features are populated.
1325 We then keep track of the features that the user specified so that we
1326 can ensure we do not override a user's request (only defaults).
1328 -mcpu=pwr8 -mno-vsx (should disable vsx and everything that depends on it)
1329 -mcpu=pwr8 -mdirect-move -mno-vsx (should actually be diagnosed)
1331 NOTE: Do not call this from PPCTargetInfo::getDefaultFeatures
1333 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1334 StringRef Name, bool Enabled) const {
1335 static llvm::StringMap<bool> ExplicitFeatures;
1336 ExplicitFeatures[Name] = Enabled;
1338 // At this point, -mno-vsx turns off the dependent features but we respect
1339 // the user's requests.
1340 if (!Enabled && Name == "vsx") {
1341 Features["direct-move"] = ExplicitFeatures["direct-move"];
1342 Features["power8-vector"] = ExplicitFeatures["power8-vector"];
1344 if ((Enabled && Name == "power8-vector") ||
1345 (Enabled && Name == "direct-move")) {
1346 if (ExplicitFeatures.find("vsx") == ExplicitFeatures.end()) {
1347 Features["vsx"] = true;
1350 Features[Name] = Enabled;
1353 const char * const PPCTargetInfo::GCCRegNames[] = {
1354 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1355 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1356 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1357 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1358 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1359 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1360 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1361 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1362 "mq", "lr", "ctr", "ap",
1363 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1365 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1366 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1367 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1368 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1370 "spe_acc", "spefscr",
1374 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1375 unsigned &NumNames) const {
1376 Names = GCCRegNames;
1377 NumNames = llvm::array_lengthof(GCCRegNames);
1380 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1381 // While some of these aliases do map to different registers
1382 // they still share the same register name.
1393 { { "10" }, "r10" },
1394 { { "11" }, "r11" },
1395 { { "12" }, "r12" },
1396 { { "13" }, "r13" },
1397 { { "14" }, "r14" },
1398 { { "15" }, "r15" },
1399 { { "16" }, "r16" },
1400 { { "17" }, "r17" },
1401 { { "18" }, "r18" },
1402 { { "19" }, "r19" },
1403 { { "20" }, "r20" },
1404 { { "21" }, "r21" },
1405 { { "22" }, "r22" },
1406 { { "23" }, "r23" },
1407 { { "24" }, "r24" },
1408 { { "25" }, "r25" },
1409 { { "26" }, "r26" },
1410 { { "27" }, "r27" },
1411 { { "28" }, "r28" },
1412 { { "29" }, "r29" },
1413 { { "30" }, "r30" },
1414 { { "31" }, "r31" },
1415 { { "fr0" }, "f0" },
1416 { { "fr1" }, "f1" },
1417 { { "fr2" }, "f2" },
1418 { { "fr3" }, "f3" },
1419 { { "fr4" }, "f4" },
1420 { { "fr5" }, "f5" },
1421 { { "fr6" }, "f6" },
1422 { { "fr7" }, "f7" },
1423 { { "fr8" }, "f8" },
1424 { { "fr9" }, "f9" },
1425 { { "fr10" }, "f10" },
1426 { { "fr11" }, "f11" },
1427 { { "fr12" }, "f12" },
1428 { { "fr13" }, "f13" },
1429 { { "fr14" }, "f14" },
1430 { { "fr15" }, "f15" },
1431 { { "fr16" }, "f16" },
1432 { { "fr17" }, "f17" },
1433 { { "fr18" }, "f18" },
1434 { { "fr19" }, "f19" },
1435 { { "fr20" }, "f20" },
1436 { { "fr21" }, "f21" },
1437 { { "fr22" }, "f22" },
1438 { { "fr23" }, "f23" },
1439 { { "fr24" }, "f24" },
1440 { { "fr25" }, "f25" },
1441 { { "fr26" }, "f26" },
1442 { { "fr27" }, "f27" },
1443 { { "fr28" }, "f28" },
1444 { { "fr29" }, "f29" },
1445 { { "fr30" }, "f30" },
1446 { { "fr31" }, "f31" },
1447 { { "cc" }, "cr0" },
1450 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1451 unsigned &NumAliases) const {
1452 Aliases = GCCRegAliases;
1453 NumAliases = llvm::array_lengthof(GCCRegAliases);
1456 class PPC32TargetInfo : public PPCTargetInfo {
1458 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1459 DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1461 switch (getTriple().getOS()) {
1462 case llvm::Triple::Linux:
1463 case llvm::Triple::FreeBSD:
1464 case llvm::Triple::NetBSD:
1465 SizeType = UnsignedInt;
1466 PtrDiffType = SignedInt;
1467 IntPtrType = SignedInt;
1473 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1474 LongDoubleWidth = LongDoubleAlign = 64;
1475 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1478 // PPC32 supports atomics up to 4 bytes.
1479 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1482 BuiltinVaListKind getBuiltinVaListKind() const override {
1483 // This is the ELF definition, and is overridden by the Darwin sub-target
1484 return TargetInfo::PowerABIBuiltinVaList;
1488 // Note: ABI differences may eventually require us to have a separate
1489 // TargetInfo for little endian.
1490 class PPC64TargetInfo : public PPCTargetInfo {
1492 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1493 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1494 IntMaxType = SignedLong;
1495 Int64Type = SignedLong;
1497 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1498 DescriptionString = "e-m:e-i64:64-n32:64";
1501 DescriptionString = "E-m:e-i64:64-n32:64";
1505 switch (getTriple().getOS()) {
1506 case llvm::Triple::FreeBSD:
1507 LongDoubleWidth = LongDoubleAlign = 64;
1508 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1510 case llvm::Triple::NetBSD:
1511 IntMaxType = SignedLongLong;
1512 Int64Type = SignedLongLong;
1518 // PPC64 supports atomics up to 8 bytes.
1519 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1521 BuiltinVaListKind getBuiltinVaListKind() const override {
1522 return TargetInfo::CharPtrBuiltinVaList;
1524 // PPC64 Linux-specific ABI options.
1525 bool setABI(const std::string &Name) override {
1526 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1534 class DarwinPPC32TargetInfo :
1535 public DarwinTargetInfo<PPC32TargetInfo> {
1537 DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1538 : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1539 HasAlignMac68kSupport = true;
1540 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1541 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1543 SuitableAlign = 128;
1544 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1546 BuiltinVaListKind getBuiltinVaListKind() const override {
1547 return TargetInfo::CharPtrBuiltinVaList;
1551 class DarwinPPC64TargetInfo :
1552 public DarwinTargetInfo<PPC64TargetInfo> {
1554 DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1555 : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1556 HasAlignMac68kSupport = true;
1557 SuitableAlign = 128;
1558 DescriptionString = "E-m:o-i64:64-n32:64";
1562 static const unsigned NVPTXAddrSpaceMap[] = {
1565 4, // opencl_constant
1566 // FIXME: generic has to be added to the target
1567 0, // opencl_generic
1572 class NVPTXTargetInfo : public TargetInfo {
1573 static const char * const GCCRegNames[];
1574 static const Builtin::Info BuiltinInfo[];
1576 // The GPU profiles supported by the NVPTX backend
1587 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1589 TLSSupported = false;
1590 LongWidth = LongAlign = 64;
1591 AddrSpaceMap = &NVPTXAddrSpaceMap;
1592 UseAddrSpaceMapMangling = true;
1593 // Define available target features
1594 // These must be defined in sorted order!
1595 NoAsmVariants = true;
1596 // Set the default GPU to sm20
1599 void getTargetDefines(const LangOptions &Opts,
1600 MacroBuilder &Builder) const override {
1601 Builder.defineMacro("__PTX__");
1602 Builder.defineMacro("__NVPTX__");
1603 if (Opts.CUDAIsDevice) {
1604 // Set __CUDA_ARCH__ for the GPU specified.
1605 std::string CUDAArchCode;
1608 CUDAArchCode = "200";
1611 CUDAArchCode = "210";
1614 CUDAArchCode = "300";
1617 CUDAArchCode = "350";
1620 CUDAArchCode = "370";
1623 llvm_unreachable("Unhandled target CPU");
1625 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1628 void getTargetBuiltins(const Builtin::Info *&Records,
1629 unsigned &NumRecords) const override {
1630 Records = BuiltinInfo;
1631 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1633 bool hasFeature(StringRef Feature) const override {
1634 return Feature == "ptx" || Feature == "nvptx";
1637 void getGCCRegNames(const char * const *&Names,
1638 unsigned &NumNames) const override;
1639 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1640 unsigned &NumAliases) const override {
1646 validateAsmConstraint(const char *&Name,
1647 TargetInfo::ConstraintInfo &Info) const override {
1649 default: return false;
1656 Info.setAllowsRegister();
1660 const char *getClobbers() const override {
1661 // FIXME: Is this really right?
1664 BuiltinVaListKind getBuiltinVaListKind() const override {
1666 return TargetInfo::CharPtrBuiltinVaList;
1668 bool setCPU(const std::string &Name) override {
1669 GPU = llvm::StringSwitch<GPUKind>(Name)
1670 .Case("sm_20", GK_SM20)
1671 .Case("sm_21", GK_SM21)
1672 .Case("sm_30", GK_SM30)
1673 .Case("sm_35", GK_SM35)
1674 .Case("sm_37", GK_SM37)
1677 return GPU != GK_NONE;
1681 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1682 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1683 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1685 #include "clang/Basic/BuiltinsNVPTX.def"
1688 const char * const NVPTXTargetInfo::GCCRegNames[] = {
1692 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1693 unsigned &NumNames) const {
1694 Names = GCCRegNames;
1695 NumNames = llvm::array_lengthof(GCCRegNames);
1698 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1700 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1701 PointerWidth = PointerAlign = 32;
1702 SizeType = TargetInfo::UnsignedInt;
1703 PtrDiffType = TargetInfo::SignedInt;
1704 IntPtrType = TargetInfo::SignedInt;
1705 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1709 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1711 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1712 PointerWidth = PointerAlign = 64;
1713 SizeType = TargetInfo::UnsignedLong;
1714 PtrDiffType = TargetInfo::SignedLong;
1715 IntPtrType = TargetInfo::SignedLong;
1716 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1720 static const unsigned AMDGPUAddrSpaceMap[] = {
1723 2, // opencl_constant
1724 4, // opencl_generic
1730 // If you edit the description strings, make sure you update
1731 // getPointerWidthV().
1733 static const char *DescriptionStringR600 =
1734 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1735 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1737 static const char *DescriptionStringR600DoubleOps =
1738 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1739 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1741 static const char *DescriptionStringSI =
1742 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1743 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1744 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1746 class AMDGPUTargetInfo : public TargetInfo {
1747 static const Builtin::Info BuiltinInfo[];
1748 static const char * const GCCRegNames[];
1750 /// \brief The GPU profiles supported by the AMDGPU target.
1758 GK_EVERGREEN_DOUBLE_OPS,
1759 GK_NORTHERN_ISLANDS,
1761 GK_SOUTHERN_ISLANDS,
1771 AMDGPUTargetInfo(const llvm::Triple &Triple)
1772 : TargetInfo(Triple) {
1774 if (Triple.getArch() == llvm::Triple::amdgcn) {
1775 DescriptionString = DescriptionStringSI;
1776 GPU = GK_SOUTHERN_ISLANDS;
1781 DescriptionString = DescriptionStringR600;
1787 AddrSpaceMap = &AMDGPUAddrSpaceMap;
1788 UseAddrSpaceMapMangling = true;
1791 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1792 if (GPU <= GK_CAYMAN)
1805 const char * getClobbers() const override {
1809 void getGCCRegNames(const char * const *&Names,
1810 unsigned &NumNames) const override;
1812 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1813 unsigned &NumAliases) const override {
1818 bool validateAsmConstraint(const char *&Name,
1819 TargetInfo::ConstraintInfo &info) const override {
1823 void getTargetBuiltins(const Builtin::Info *&Records,
1824 unsigned &NumRecords) const override {
1825 Records = BuiltinInfo;
1826 NumRecords = clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin;
1829 void getTargetDefines(const LangOptions &Opts,
1830 MacroBuilder &Builder) const override {
1831 Builder.defineMacro("__R600__");
1833 Builder.defineMacro("__HAS_FMAF__");
1835 Builder.defineMacro("__HAS_LDEXPF__");
1836 if (hasFP64 && Opts.OpenCL) {
1837 Builder.defineMacro("cl_khr_fp64");
1841 BuiltinVaListKind getBuiltinVaListKind() const override {
1842 return TargetInfo::CharPtrBuiltinVaList;
1845 bool setCPU(const std::string &Name) override {
1846 GPU = llvm::StringSwitch<GPUKind>(Name)
1847 .Case("r600" , GK_R600)
1848 .Case("rv610", GK_R600)
1849 .Case("rv620", GK_R600)
1850 .Case("rv630", GK_R600)
1851 .Case("rv635", GK_R600)
1852 .Case("rs780", GK_R600)
1853 .Case("rs880", GK_R600)
1854 .Case("rv670", GK_R600_DOUBLE_OPS)
1855 .Case("rv710", GK_R700)
1856 .Case("rv730", GK_R700)
1857 .Case("rv740", GK_R700_DOUBLE_OPS)
1858 .Case("rv770", GK_R700_DOUBLE_OPS)
1859 .Case("palm", GK_EVERGREEN)
1860 .Case("cedar", GK_EVERGREEN)
1861 .Case("sumo", GK_EVERGREEN)
1862 .Case("sumo2", GK_EVERGREEN)
1863 .Case("redwood", GK_EVERGREEN)
1864 .Case("juniper", GK_EVERGREEN)
1865 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
1866 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
1867 .Case("barts", GK_NORTHERN_ISLANDS)
1868 .Case("turks", GK_NORTHERN_ISLANDS)
1869 .Case("caicos", GK_NORTHERN_ISLANDS)
1870 .Case("cayman", GK_CAYMAN)
1871 .Case("aruba", GK_CAYMAN)
1872 .Case("tahiti", GK_SOUTHERN_ISLANDS)
1873 .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1874 .Case("verde", GK_SOUTHERN_ISLANDS)
1875 .Case("oland", GK_SOUTHERN_ISLANDS)
1876 .Case("hainan", GK_SOUTHERN_ISLANDS)
1877 .Case("bonaire", GK_SEA_ISLANDS)
1878 .Case("kabini", GK_SEA_ISLANDS)
1879 .Case("kaveri", GK_SEA_ISLANDS)
1880 .Case("hawaii", GK_SEA_ISLANDS)
1881 .Case("mullins", GK_SEA_ISLANDS)
1882 .Case("tonga", GK_VOLCANIC_ISLANDS)
1883 .Case("iceland", GK_VOLCANIC_ISLANDS)
1884 .Case("carrizo", GK_VOLCANIC_ISLANDS)
1887 if (GPU == GK_NONE) {
1891 // Set the correct data layout
1897 case GK_NORTHERN_ISLANDS:
1898 DescriptionString = DescriptionStringR600;
1903 case GK_R600_DOUBLE_OPS:
1904 case GK_R700_DOUBLE_OPS:
1905 case GK_EVERGREEN_DOUBLE_OPS:
1907 DescriptionString = DescriptionStringR600DoubleOps;
1912 case GK_SOUTHERN_ISLANDS:
1913 case GK_SEA_ISLANDS:
1914 case GK_VOLCANIC_ISLANDS:
1915 DescriptionString = DescriptionStringSI;
1926 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
1927 #define BUILTIN(ID, TYPE, ATTRS) \
1928 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1929 #include "clang/Basic/BuiltinsAMDGPU.def"
1931 const char * const AMDGPUTargetInfo::GCCRegNames[] = {
1932 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1933 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1934 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1935 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1936 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
1937 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
1938 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
1939 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
1940 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
1941 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
1942 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
1943 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
1944 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
1945 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
1946 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
1947 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
1948 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
1949 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
1950 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
1951 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
1952 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
1953 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
1954 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
1955 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
1956 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
1957 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
1958 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
1959 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
1960 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
1961 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
1962 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
1963 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
1964 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1965 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
1966 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
1967 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
1968 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
1969 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
1970 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
1971 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
1972 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
1973 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
1974 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
1975 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
1976 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
1977 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
1978 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
1979 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127"
1980 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi",
1981 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi"
1984 void AMDGPUTargetInfo::getGCCRegNames(const char * const *&Names,
1985 unsigned &NumNames) const {
1986 Names = GCCRegNames;
1987 NumNames = llvm::array_lengthof(GCCRegNames);
1990 // Namespace for x86 abstract base class
1991 const Builtin::Info BuiltinInfo[] = {
1992 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1993 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1995 #include "clang/Basic/BuiltinsX86.def"
1998 static const char* const GCCRegNames[] = {
1999 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
2000 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
2001 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
2002 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
2003 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
2004 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2005 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
2006 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
2007 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
2010 const TargetInfo::AddlRegName AddlRegNames[] = {
2011 { { "al", "ah", "eax", "rax" }, 0 },
2012 { { "bl", "bh", "ebx", "rbx" }, 3 },
2013 { { "cl", "ch", "ecx", "rcx" }, 2 },
2014 { { "dl", "dh", "edx", "rdx" }, 1 },
2015 { { "esi", "rsi" }, 4 },
2016 { { "edi", "rdi" }, 5 },
2017 { { "esp", "rsp" }, 7 },
2018 { { "ebp", "rbp" }, 6 },
2021 // X86 target abstract base class; x86-32 and x86-64 are very close, so
2022 // most of the implementation can be shared.
2023 class X86TargetInfo : public TargetInfo {
2025 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
2028 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
2052 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW,
2057 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2059 /// Each enumeration represents a particular CPU supported by Clang. These
2060 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2065 /// i386-generation processors.
2071 /// i486-generation processors.
2080 /// i586-generation processors, P5 microarchitecture based.
2088 /// i686-generation processors, P6 / Pentium M microarchitecture based.
2098 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2099 /// Clang however has some logic to suport this.
2100 // FIXME: Warn, deprecate, and potentially remove this.
2105 /// Netburst microarchitecture based processors.
2114 /// Core microarchitecture based processors.
2118 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2119 /// codename which GCC no longer accepts as an option to -march, but Clang
2120 /// has some logic for recognizing it.
2121 // FIXME: Warn, deprecate, and potentially remove this.
2133 /// Nehalem microarchitecture based processors.
2137 /// Westmere microarchitecture based processors.
2140 /// \name Sandy Bridge
2141 /// Sandy Bridge microarchitecture based processors.
2144 /// \name Ivy Bridge
2145 /// Ivy Bridge microarchitecture based processors.
2149 /// Haswell microarchitecture based processors.
2153 /// Broadwell microarchitecture based processors.
2157 /// Skylake microarchitecture based processors.
2160 /// \name Knights Landing
2161 /// Knights Landing processor.
2165 /// K6 architecture processors.
2173 /// K7 architecture processors.
2176 CK_AthlonThunderbird,
2183 /// K8 architecture processors.
2196 /// Bobcat architecture processors.
2203 /// Bulldozer architecture processors.
2211 /// This specification is deprecated and will be removed in the future.
2212 /// Users should prefer \see CK_K8.
2213 // FIXME: Warn on this when the CPU is set to it.
2219 /// Geode processors.
2232 X86TargetInfo(const llvm::Triple &Triple)
2233 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
2234 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
2235 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
2236 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
2237 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
2238 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
2239 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
2240 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
2242 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
2244 unsigned getFloatEvalMethod() const override {
2245 // X87 evaluates with 80 bits "long double" precision.
2246 return SSELevel == NoSSE ? 2 : 0;
2248 void getTargetBuiltins(const Builtin::Info *&Records,
2249 unsigned &NumRecords) const override {
2250 Records = BuiltinInfo;
2251 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
2253 void getGCCRegNames(const char * const *&Names,
2254 unsigned &NumNames) const override {
2255 Names = GCCRegNames;
2256 NumNames = llvm::array_lengthof(GCCRegNames);
2258 void getGCCRegAliases(const GCCRegAlias *&Aliases,
2259 unsigned &NumAliases) const override {
2263 void getGCCAddlRegNames(const AddlRegName *&Names,
2264 unsigned &NumNames) const override {
2265 Names = AddlRegNames;
2266 NumNames = llvm::array_lengthof(AddlRegNames);
2268 bool validateCpuSupports(StringRef Name) const override;
2269 bool validateAsmConstraint(const char *&Name,
2270 TargetInfo::ConstraintInfo &info) const override;
2272 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2274 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2276 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2278 std::string convertConstraint(const char *&Constraint) const override;
2279 const char *getClobbers() const override {
2280 return "~{dirflag},~{fpsr},~{flags}";
2282 void getTargetDefines(const LangOptions &Opts,
2283 MacroBuilder &Builder) const override;
2284 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2286 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2288 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2290 void setFeatureEnabled(llvm::StringMap<bool> &Features,
2291 StringRef Name, bool Enabled) const override {
2292 setFeatureEnabledImpl(Features, Name, Enabled);
2294 // This exists purely to cut down on the number of virtual calls in
2295 // getDefaultFeatures which calls this repeatedly.
2296 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2297 StringRef Name, bool Enabled);
2298 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
2299 bool hasFeature(StringRef Feature) const override;
2300 bool handleTargetFeatures(std::vector<std::string> &Features,
2301 DiagnosticsEngine &Diags) override;
2302 StringRef getABI() const override {
2303 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
2305 else if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2307 else if (getTriple().getArch() == llvm::Triple::x86 &&
2308 MMX3DNowLevel == NoMMX3DNow)
2312 bool setCPU(const std::string &Name) override {
2313 CPU = llvm::StringSwitch<CPUKind>(Name)
2314 .Case("i386", CK_i386)
2315 .Case("i486", CK_i486)
2316 .Case("winchip-c6", CK_WinChipC6)
2317 .Case("winchip2", CK_WinChip2)
2319 .Case("i586", CK_i586)
2320 .Case("pentium", CK_Pentium)
2321 .Case("pentium-mmx", CK_PentiumMMX)
2322 .Case("i686", CK_i686)
2323 .Case("pentiumpro", CK_PentiumPro)
2324 .Case("pentium2", CK_Pentium2)
2325 .Case("pentium3", CK_Pentium3)
2326 .Case("pentium3m", CK_Pentium3M)
2327 .Case("pentium-m", CK_PentiumM)
2328 .Case("c3-2", CK_C3_2)
2329 .Case("yonah", CK_Yonah)
2330 .Case("pentium4", CK_Pentium4)
2331 .Case("pentium4m", CK_Pentium4M)
2332 .Case("prescott", CK_Prescott)
2333 .Case("nocona", CK_Nocona)
2334 .Case("core2", CK_Core2)
2335 .Case("penryn", CK_Penryn)
2336 .Case("bonnell", CK_Bonnell)
2337 .Case("atom", CK_Bonnell) // Legacy name.
2338 .Case("silvermont", CK_Silvermont)
2339 .Case("slm", CK_Silvermont) // Legacy name.
2340 .Case("nehalem", CK_Nehalem)
2341 .Case("corei7", CK_Nehalem) // Legacy name.
2342 .Case("westmere", CK_Westmere)
2343 .Case("sandybridge", CK_SandyBridge)
2344 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2345 .Case("ivybridge", CK_IvyBridge)
2346 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2347 .Case("haswell", CK_Haswell)
2348 .Case("core-avx2", CK_Haswell) // Legacy name.
2349 .Case("broadwell", CK_Broadwell)
2350 .Case("skylake", CK_Skylake)
2351 .Case("skx", CK_Skylake) // Legacy name.
2352 .Case("knl", CK_KNL)
2354 .Case("k6-2", CK_K6_2)
2355 .Case("k6-3", CK_K6_3)
2356 .Case("athlon", CK_Athlon)
2357 .Case("athlon-tbird", CK_AthlonThunderbird)
2358 .Case("athlon-4", CK_Athlon4)
2359 .Case("athlon-xp", CK_AthlonXP)
2360 .Case("athlon-mp", CK_AthlonMP)
2361 .Case("athlon64", CK_Athlon64)
2362 .Case("athlon64-sse3", CK_Athlon64SSE3)
2363 .Case("athlon-fx", CK_AthlonFX)
2365 .Case("k8-sse3", CK_K8SSE3)
2366 .Case("opteron", CK_Opteron)
2367 .Case("opteron-sse3", CK_OpteronSSE3)
2368 .Case("barcelona", CK_AMDFAM10)
2369 .Case("amdfam10", CK_AMDFAM10)
2370 .Case("btver1", CK_BTVER1)
2371 .Case("btver2", CK_BTVER2)
2372 .Case("bdver1", CK_BDVER1)
2373 .Case("bdver2", CK_BDVER2)
2374 .Case("bdver3", CK_BDVER3)
2375 .Case("bdver4", CK_BDVER4)
2376 .Case("x86-64", CK_x86_64)
2377 .Case("geode", CK_Geode)
2378 .Default(CK_Generic);
2380 // Perform any per-CPU checks necessary to determine if this CPU is
2382 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2383 // invalid without explaining *why*.
2386 // No processor selected!
2412 case CK_AthlonThunderbird:
2417 // Only accept certain architectures when compiling in 32-bit mode.
2418 if (getTriple().getArch() != llvm::Triple::x86)
2429 case CK_SandyBridge:
2436 case CK_Athlon64SSE3:
2441 case CK_OpteronSSE3:
2452 llvm_unreachable("Unhandled CPU kind");
2455 bool setFPMath(StringRef Name) override;
2457 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2458 // We accept all non-ARM calling conventions
2459 return (CC == CC_X86ThisCall ||
2460 CC == CC_X86FastCall ||
2461 CC == CC_X86StdCall ||
2462 CC == CC_X86VectorCall ||
2464 CC == CC_X86Pascal ||
2465 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2468 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2469 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2472 bool hasSjLjLowering() const override {
2477 bool X86TargetInfo::setFPMath(StringRef Name) {
2478 if (Name == "387") {
2482 if (Name == "sse") {
2489 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2490 // FIXME: This *really* should not be here.
2492 // X86_64 always has SSE2.
2493 if (getTriple().getArch() == llvm::Triple::x86_64)
2494 setFeatureEnabledImpl(Features, "sse2", true);
2509 setFeatureEnabledImpl(Features, "mmx", true);
2514 setFeatureEnabledImpl(Features, "sse", true);
2520 setFeatureEnabledImpl(Features, "sse2", true);
2525 setFeatureEnabledImpl(Features, "sse3", true);
2526 setFeatureEnabledImpl(Features, "cx16", true);
2530 setFeatureEnabledImpl(Features, "ssse3", true);
2531 setFeatureEnabledImpl(Features, "cx16", true);
2534 setFeatureEnabledImpl(Features, "sse4.1", true);
2535 setFeatureEnabledImpl(Features, "cx16", true);
2538 setFeatureEnabledImpl(Features, "avx512f", true);
2539 setFeatureEnabledImpl(Features, "avx512cd", true);
2540 setFeatureEnabledImpl(Features, "avx512dq", true);
2541 setFeatureEnabledImpl(Features, "avx512bw", true);
2542 setFeatureEnabledImpl(Features, "avx512vl", true);
2545 setFeatureEnabledImpl(Features, "rdseed", true);
2546 setFeatureEnabledImpl(Features, "adx", true);
2549 setFeatureEnabledImpl(Features, "avx2", true);
2550 setFeatureEnabledImpl(Features, "lzcnt", true);
2551 setFeatureEnabledImpl(Features, "bmi", true);
2552 setFeatureEnabledImpl(Features, "bmi2", true);
2553 setFeatureEnabledImpl(Features, "rtm", true);
2554 setFeatureEnabledImpl(Features, "fma", true);
2557 setFeatureEnabledImpl(Features, "rdrnd", true);
2558 setFeatureEnabledImpl(Features, "f16c", true);
2559 setFeatureEnabledImpl(Features, "fsgsbase", true);
2561 case CK_SandyBridge:
2562 setFeatureEnabledImpl(Features, "avx", true);
2566 setFeatureEnabledImpl(Features, "aes", true);
2567 setFeatureEnabledImpl(Features, "pclmul", true);
2570 setFeatureEnabledImpl(Features, "sse4.2", true);
2571 setFeatureEnabledImpl(Features, "cx16", true);
2574 setFeatureEnabledImpl(Features, "avx512f", true);
2575 setFeatureEnabledImpl(Features, "avx512cd", true);
2576 setFeatureEnabledImpl(Features, "avx512er", true);
2577 setFeatureEnabledImpl(Features, "avx512pf", true);
2578 setFeatureEnabledImpl(Features, "rdseed", true);
2579 setFeatureEnabledImpl(Features, "adx", true);
2580 setFeatureEnabledImpl(Features, "lzcnt", true);
2581 setFeatureEnabledImpl(Features, "bmi", true);
2582 setFeatureEnabledImpl(Features, "bmi2", true);
2583 setFeatureEnabledImpl(Features, "rtm", true);
2584 setFeatureEnabledImpl(Features, "fma", true);
2585 setFeatureEnabledImpl(Features, "rdrnd", true);
2586 setFeatureEnabledImpl(Features, "f16c", true);
2587 setFeatureEnabledImpl(Features, "fsgsbase", true);
2588 setFeatureEnabledImpl(Features, "aes", true);
2589 setFeatureEnabledImpl(Features, "pclmul", true);
2590 setFeatureEnabledImpl(Features, "cx16", true);
2596 setFeatureEnabledImpl(Features, "3dnow", true);
2599 case CK_AthlonThunderbird:
2601 setFeatureEnabledImpl(Features, "3dnowa", true);
2606 setFeatureEnabledImpl(Features, "sse", true);
2607 setFeatureEnabledImpl(Features, "3dnowa", true);
2613 setFeatureEnabledImpl(Features, "sse2", true);
2614 setFeatureEnabledImpl(Features, "3dnowa", true);
2617 setFeatureEnabledImpl(Features, "sse4a", true);
2618 setFeatureEnabledImpl(Features, "lzcnt", true);
2619 setFeatureEnabledImpl(Features, "popcnt", true);
2622 case CK_OpteronSSE3:
2623 case CK_Athlon64SSE3:
2624 setFeatureEnabledImpl(Features, "sse3", true);
2625 setFeatureEnabledImpl(Features, "3dnowa", true);
2628 setFeatureEnabledImpl(Features, "avx", true);
2629 setFeatureEnabledImpl(Features, "aes", true);
2630 setFeatureEnabledImpl(Features, "pclmul", true);
2631 setFeatureEnabledImpl(Features, "bmi", true);
2632 setFeatureEnabledImpl(Features, "f16c", true);
2635 setFeatureEnabledImpl(Features, "ssse3", true);
2636 setFeatureEnabledImpl(Features, "sse4a", true);
2637 setFeatureEnabledImpl(Features, "lzcnt", true);
2638 setFeatureEnabledImpl(Features, "popcnt", true);
2639 setFeatureEnabledImpl(Features, "prfchw", true);
2640 setFeatureEnabledImpl(Features, "cx16", true);
2643 setFeatureEnabledImpl(Features, "avx2", true);
2644 setFeatureEnabledImpl(Features, "bmi2", true);
2647 setFeatureEnabledImpl(Features, "fsgsbase", true);
2650 setFeatureEnabledImpl(Features, "bmi", true);
2651 setFeatureEnabledImpl(Features, "fma", true);
2652 setFeatureEnabledImpl(Features, "f16c", true);
2653 setFeatureEnabledImpl(Features, "tbm", true);
2656 // xop implies avx, sse4a and fma4.
2657 setFeatureEnabledImpl(Features, "xop", true);
2658 setFeatureEnabledImpl(Features, "lzcnt", true);
2659 setFeatureEnabledImpl(Features, "aes", true);
2660 setFeatureEnabledImpl(Features, "pclmul", true);
2661 setFeatureEnabledImpl(Features, "prfchw", true);
2662 setFeatureEnabledImpl(Features, "cx16", true);
2667 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2668 X86SSEEnum Level, bool Enabled) {
2672 Features["avx512f"] = true;
2674 Features["avx2"] = true;
2676 Features["avx"] = true;
2678 Features["sse4.2"] = true;
2680 Features["sse4.1"] = true;
2682 Features["ssse3"] = true;
2684 Features["sse3"] = true;
2686 Features["sse2"] = true;
2688 Features["sse"] = true;
2698 Features["sse"] = false;
2700 Features["sse2"] = Features["pclmul"] = Features["aes"] =
2701 Features["sha"] = false;
2703 Features["sse3"] = false;
2704 setXOPLevel(Features, NoXOP, false);
2706 Features["ssse3"] = false;
2708 Features["sse4.1"] = false;
2710 Features["sse4.2"] = false;
2712 Features["fma"] = Features["avx"] = Features["f16c"] = false;
2713 setXOPLevel(Features, FMA4, false);
2715 Features["avx2"] = false;
2717 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2718 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2719 Features["avx512vl"] = false;
2723 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2724 MMX3DNowEnum Level, bool Enabled) {
2727 case AMD3DNowAthlon:
2728 Features["3dnowa"] = true;
2730 Features["3dnow"] = true;
2732 Features["mmx"] = true;
2742 Features["mmx"] = false;
2744 Features["3dnow"] = false;
2745 case AMD3DNowAthlon:
2746 Features["3dnowa"] = false;
2750 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2755 Features["xop"] = true;
2757 Features["fma4"] = true;
2758 setSSELevel(Features, AVX, true);
2760 Features["sse4a"] = true;
2761 setSSELevel(Features, SSE3, true);
2771 Features["sse4a"] = false;
2773 Features["fma4"] = false;
2775 Features["xop"] = false;
2779 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2780 StringRef Name, bool Enabled) {
2781 // This is a bit of a hack to deal with the sse4 target feature when used
2782 // as part of the target attribute. We handle sse4 correctly everywhere
2783 // else. See below for more information on how we handle the sse4 options.
2785 Features[Name] = Enabled;
2787 if (Name == "mmx") {
2788 setMMXLevel(Features, MMX, Enabled);
2789 } else if (Name == "sse") {
2790 setSSELevel(Features, SSE1, Enabled);
2791 } else if (Name == "sse2") {
2792 setSSELevel(Features, SSE2, Enabled);
2793 } else if (Name == "sse3") {
2794 setSSELevel(Features, SSE3, Enabled);
2795 } else if (Name == "ssse3") {
2796 setSSELevel(Features, SSSE3, Enabled);
2797 } else if (Name == "sse4.2") {
2798 setSSELevel(Features, SSE42, Enabled);
2799 } else if (Name == "sse4.1") {
2800 setSSELevel(Features, SSE41, Enabled);
2801 } else if (Name == "3dnow") {
2802 setMMXLevel(Features, AMD3DNow, Enabled);
2803 } else if (Name == "3dnowa") {
2804 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2805 } else if (Name == "aes") {
2807 setSSELevel(Features, SSE2, Enabled);
2808 } else if (Name == "pclmul") {
2810 setSSELevel(Features, SSE2, Enabled);
2811 } else if (Name == "avx") {
2812 setSSELevel(Features, AVX, Enabled);
2813 } else if (Name == "avx2") {
2814 setSSELevel(Features, AVX2, Enabled);
2815 } else if (Name == "avx512f") {
2816 setSSELevel(Features, AVX512F, Enabled);
2817 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2818 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2820 setSSELevel(Features, AVX512F, Enabled);
2821 } else if (Name == "fma") {
2823 setSSELevel(Features, AVX, Enabled);
2824 } else if (Name == "fma4") {
2825 setXOPLevel(Features, FMA4, Enabled);
2826 } else if (Name == "xop") {
2827 setXOPLevel(Features, XOP, Enabled);
2828 } else if (Name == "sse4a") {
2829 setXOPLevel(Features, SSE4A, Enabled);
2830 } else if (Name == "f16c") {
2832 setSSELevel(Features, AVX, Enabled);
2833 } else if (Name == "sha") {
2835 setSSELevel(Features, SSE2, Enabled);
2836 } else if (Name == "sse4") {
2837 // We can get here via the __target__ attribute since that's not controlled
2838 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
2839 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
2842 setSSELevel(Features, SSE42, Enabled);
2844 setSSELevel(Features, SSE41, Enabled);
2848 /// handleTargetFeatures - Perform initialization based on the user
2849 /// configured set of features.
2850 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2851 DiagnosticsEngine &Diags) {
2852 // Remember the maximum enabled sselevel.
2853 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2854 // Ignore disabled features.
2855 if (Features[i][0] == '-')
2858 StringRef Feature = StringRef(Features[i]).substr(1);
2860 if (Feature == "aes") {
2865 if (Feature == "pclmul") {
2870 if (Feature == "lzcnt") {
2875 if (Feature == "rdrnd") {
2880 if (Feature == "fsgsbase") {
2885 if (Feature == "bmi") {
2890 if (Feature == "bmi2") {
2895 if (Feature == "popcnt") {
2900 if (Feature == "rtm") {
2905 if (Feature == "prfchw") {
2910 if (Feature == "rdseed") {
2915 if (Feature == "adx") {
2920 if (Feature == "tbm") {
2925 if (Feature == "fma") {
2930 if (Feature == "f16c") {
2935 if (Feature == "avx512cd") {
2940 if (Feature == "avx512er") {
2945 if (Feature == "avx512pf") {
2950 if (Feature == "avx512dq") {
2955 if (Feature == "avx512bw") {
2960 if (Feature == "avx512vl") {
2965 if (Feature == "sha") {
2970 if (Feature == "cx16") {
2975 assert(Features[i][0] == '+' && "Invalid target feature!");
2976 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2977 .Case("avx512f", AVX512F)
2980 .Case("sse4.2", SSE42)
2981 .Case("sse4.1", SSE41)
2982 .Case("ssse3", SSSE3)
2987 SSELevel = std::max(SSELevel, Level);
2989 MMX3DNowEnum ThreeDNowLevel =
2990 llvm::StringSwitch<MMX3DNowEnum>(Feature)
2991 .Case("3dnowa", AMD3DNowAthlon)
2992 .Case("3dnow", AMD3DNow)
2994 .Default(NoMMX3DNow);
2995 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2997 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
3000 .Case("sse4a", SSE4A)
3002 XOPLevel = std::max(XOPLevel, XLevel);
3005 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
3006 // Can't do this earlier because we need to be able to explicitly enable
3007 // popcnt and still disable sse4.2.
3008 if (!HasPOPCNT && SSELevel >= SSE42 &&
3009 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
3011 Features.push_back("+popcnt");
3014 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
3015 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
3016 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
3018 Features.push_back("+prfchw");
3021 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
3022 // matches the selected sse level.
3023 if (FPMath == FP_SSE && SSELevel < SSE1) {
3024 Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
3026 } else if (FPMath == FP_387 && SSELevel >= SSE1) {
3027 Diags.Report(diag::err_target_unsupported_fpmath) << "387";
3031 // Don't tell the backend if we're turning off mmx; it will end up disabling
3032 // SSE, which we don't want.
3033 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
3035 std::vector<std::string>::iterator it;
3036 it = std::find(Features.begin(), Features.end(), "-mmx");
3037 if (it != Features.end())
3039 else if (SSELevel > NoSSE)
3040 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
3043 (getABI() == "avx512") ? 512 : (getABI() == "avx") ? 256 : 128;
3047 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
3048 /// definitions for this particular subtarget.
3049 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
3050 MacroBuilder &Builder) const {
3051 // Target identification.
3052 if (getTriple().getArch() == llvm::Triple::x86_64) {
3053 Builder.defineMacro("__amd64__");
3054 Builder.defineMacro("__amd64");
3055 Builder.defineMacro("__x86_64");
3056 Builder.defineMacro("__x86_64__");
3057 if (getTriple().getArchName() == "x86_64h") {
3058 Builder.defineMacro("__x86_64h");
3059 Builder.defineMacro("__x86_64h__");
3062 DefineStd(Builder, "i386", Opts);
3065 // Subtarget options.
3066 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
3067 // truly should be based on -mtune options.
3072 // The rest are coming from the i386 define above.
3073 Builder.defineMacro("__tune_i386__");
3079 defineCPUMacros(Builder, "i486");
3082 Builder.defineMacro("__pentium_mmx__");
3083 Builder.defineMacro("__tune_pentium_mmx__");
3087 defineCPUMacros(Builder, "i586");
3088 defineCPUMacros(Builder, "pentium");
3093 Builder.defineMacro("__tune_pentium3__");
3097 Builder.defineMacro("__tune_pentium2__");
3100 Builder.defineMacro("__tune_i686__");
3101 Builder.defineMacro("__tune_pentiumpro__");
3104 Builder.defineMacro("__i686");
3105 Builder.defineMacro("__i686__");
3106 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3107 Builder.defineMacro("__pentiumpro");
3108 Builder.defineMacro("__pentiumpro__");
3112 defineCPUMacros(Builder, "pentium4");
3117 defineCPUMacros(Builder, "nocona");
3121 defineCPUMacros(Builder, "core2");
3124 defineCPUMacros(Builder, "atom");
3127 defineCPUMacros(Builder, "slm");
3131 case CK_SandyBridge:
3135 // FIXME: Historically, we defined this legacy name, it would be nice to
3136 // remove it at some point. We've never exposed fine-grained names for
3137 // recent primary x86 CPUs, and we should keep it that way.
3138 defineCPUMacros(Builder, "corei7");
3141 // FIXME: Historically, we defined this legacy name, it would be nice to
3142 // remove it at some point. This is the only fine-grained CPU macro in the
3143 // main intel CPU line, and it would be better to not have these and force
3144 // people to use ISA macros.
3145 defineCPUMacros(Builder, "skx");
3148 defineCPUMacros(Builder, "knl");
3151 Builder.defineMacro("__k6_2__");
3152 Builder.defineMacro("__tune_k6_2__");
3155 if (CPU != CK_K6_2) { // In case of fallthrough
3156 // FIXME: GCC may be enabling these in cases where some other k6
3157 // architecture is specified but -m3dnow is explicitly provided. The
3158 // exact semantics need to be determined and emulated here.
3159 Builder.defineMacro("__k6_3__");
3160 Builder.defineMacro("__tune_k6_3__");
3164 defineCPUMacros(Builder, "k6");
3167 case CK_AthlonThunderbird:
3171 defineCPUMacros(Builder, "athlon");
3172 if (SSELevel != NoSSE) {
3173 Builder.defineMacro("__athlon_sse__");
3174 Builder.defineMacro("__tune_athlon_sse__");
3181 case CK_OpteronSSE3:
3183 case CK_Athlon64SSE3:
3185 defineCPUMacros(Builder, "k8");
3188 defineCPUMacros(Builder, "amdfam10");
3191 defineCPUMacros(Builder, "btver1");
3194 defineCPUMacros(Builder, "btver2");
3197 defineCPUMacros(Builder, "bdver1");
3200 defineCPUMacros(Builder, "bdver2");
3203 defineCPUMacros(Builder, "bdver3");
3206 defineCPUMacros(Builder, "bdver4");
3209 defineCPUMacros(Builder, "geode");
3213 // Target properties.
3214 Builder.defineMacro("__REGISTER_PREFIX__", "");
3216 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3217 // functions in glibc header files that use FP Stack inline asm which the
3218 // backend can't deal with (PR879).
3219 Builder.defineMacro("__NO_MATH_INLINES");
3222 Builder.defineMacro("__AES__");
3225 Builder.defineMacro("__PCLMUL__");
3228 Builder.defineMacro("__LZCNT__");
3231 Builder.defineMacro("__RDRND__");
3234 Builder.defineMacro("__FSGSBASE__");
3237 Builder.defineMacro("__BMI__");
3240 Builder.defineMacro("__BMI2__");
3243 Builder.defineMacro("__POPCNT__");
3246 Builder.defineMacro("__RTM__");
3249 Builder.defineMacro("__PRFCHW__");
3252 Builder.defineMacro("__RDSEED__");
3255 Builder.defineMacro("__ADX__");
3258 Builder.defineMacro("__TBM__");
3262 Builder.defineMacro("__XOP__");
3264 Builder.defineMacro("__FMA4__");
3266 Builder.defineMacro("__SSE4A__");
3272 Builder.defineMacro("__FMA__");
3275 Builder.defineMacro("__F16C__");
3278 Builder.defineMacro("__AVX512CD__");
3280 Builder.defineMacro("__AVX512ER__");
3282 Builder.defineMacro("__AVX512PF__");
3284 Builder.defineMacro("__AVX512DQ__");
3286 Builder.defineMacro("__AVX512BW__");
3288 Builder.defineMacro("__AVX512VL__");
3291 Builder.defineMacro("__SHA__");
3294 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3296 // Each case falls through to the previous one here.
3299 Builder.defineMacro("__AVX512F__");
3301 Builder.defineMacro("__AVX2__");
3303 Builder.defineMacro("__AVX__");
3305 Builder.defineMacro("__SSE4_2__");
3307 Builder.defineMacro("__SSE4_1__");
3309 Builder.defineMacro("__SSSE3__");
3311 Builder.defineMacro("__SSE3__");
3313 Builder.defineMacro("__SSE2__");
3314 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
3316 Builder.defineMacro("__SSE__");
3317 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
3322 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3332 Builder.defineMacro("_M_IX86_FP", Twine(2));
3335 Builder.defineMacro("_M_IX86_FP", Twine(1));
3338 Builder.defineMacro("_M_IX86_FP", Twine(0));
3342 // Each case falls through to the previous one here.
3343 switch (MMX3DNowLevel) {
3344 case AMD3DNowAthlon:
3345 Builder.defineMacro("__3dNOW_A__");
3347 Builder.defineMacro("__3dNOW__");
3349 Builder.defineMacro("__MMX__");
3354 if (CPU >= CK_i486) {
3355 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3356 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3357 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3360 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3363 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3364 return llvm::StringSwitch<bool>(Feature)
3365 .Case("aes", HasAES)
3366 .Case("avx", SSELevel >= AVX)
3367 .Case("avx2", SSELevel >= AVX2)
3368 .Case("avx512f", SSELevel >= AVX512F)
3369 .Case("avx512cd", HasAVX512CD)
3370 .Case("avx512er", HasAVX512ER)
3371 .Case("avx512pf", HasAVX512PF)
3372 .Case("avx512dq", HasAVX512DQ)
3373 .Case("avx512bw", HasAVX512BW)
3374 .Case("avx512vl", HasAVX512VL)
3375 .Case("bmi", HasBMI)
3376 .Case("bmi2", HasBMI2)
3377 .Case("cx16", HasCX16)
3378 .Case("f16c", HasF16C)
3379 .Case("fma", HasFMA)
3380 .Case("fma4", XOPLevel >= FMA4)
3381 .Case("fsgsbase", HasFSGSBASE)
3382 .Case("lzcnt", HasLZCNT)
3383 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3384 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3385 .Case("mmx", MMX3DNowLevel >= MMX)
3386 .Case("pclmul", HasPCLMUL)
3387 .Case("popcnt", HasPOPCNT)
3388 .Case("prfchw", HasPRFCHW)
3389 .Case("rdrnd", HasRDRND)
3390 .Case("rdseed", HasRDSEED)
3391 .Case("rtm", HasRTM)
3392 .Case("sha", HasSHA)
3393 .Case("sse", SSELevel >= SSE1)
3394 .Case("sse2", SSELevel >= SSE2)
3395 .Case("sse3", SSELevel >= SSE3)
3396 .Case("ssse3", SSELevel >= SSSE3)
3397 .Case("sse4.1", SSELevel >= SSE41)
3398 .Case("sse4.2", SSELevel >= SSE42)
3399 .Case("sse4a", XOPLevel >= SSE4A)
3400 .Case("tbm", HasTBM)
3402 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3403 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3404 .Case("xop", XOPLevel >= XOP)
3408 // We can't use a generic validation scheme for the features accepted here
3409 // versus subtarget features accepted in the target attribute because the
3410 // bitfield structure that's initialized in the runtime only supports the
3411 // below currently rather than the full range of subtarget features. (See
3412 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
3413 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
3414 return llvm::StringSwitch<bool>(FeatureStr)
3417 .Case("popcnt", true)
3421 .Case("sse4.1", true)
3422 .Case("sse4.2", true)
3425 .Case("sse4a", true)
3429 .Case("avx512f", true)
3436 X86TargetInfo::validateAsmConstraint(const char *&Name,
3437 TargetInfo::ConstraintInfo &Info) const {
3439 default: return false;
3441 Info.setRequiresImmediate(0, 31);
3444 Info.setRequiresImmediate(0, 63);
3447 Info.setRequiresImmediate(-128, 127);
3450 // FIXME: properly analyze this constraint:
3451 // must be one of 0xff, 0xffff, or 0xffffffff
3454 Info.setRequiresImmediate(0, 3);
3457 Info.setRequiresImmediate(0, 255);
3460 Info.setRequiresImmediate(0, 127);
3462 case 'Y': // first letter of a pair:
3463 switch (*(Name+1)) {
3464 default: return false;
3465 case '0': // First SSE register.
3466 case 't': // Any SSE register, when SSE2 is enabled.
3467 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
3468 case 'm': // any MMX register, when inter-unit moves enabled.
3469 break; // falls through to setAllowsRegister.
3471 case 'f': // any x87 floating point stack register.
3472 // Constraint 'f' cannot be used for output operands.
3473 if (Info.ConstraintStr[0] == '=')
3476 Info.setAllowsRegister();
3484 case 'A': // edx:eax.
3485 case 't': // top of floating point stack.
3486 case 'u': // second from top of floating point stack.
3487 case 'q': // Any register accessible as [r]l: a, b, c, and d.
3488 case 'y': // Any MMX register.
3489 case 'x': // Any SSE register.
3490 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3491 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3492 case 'l': // "Index" registers: any general register that can be used as an
3493 // index in a base+index memory access.
3494 Info.setAllowsRegister();
3496 case 'C': // SSE floating point constant.
3497 case 'G': // x87 floating point constant.
3498 case 'e': // 32-bit signed integer constant for use with zero-extending
3499 // x86_64 instructions.
3500 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3501 // x86_64 instructions.
3506 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3507 unsigned Size) const {
3508 // Strip off constraint modifiers.
3509 while (Constraint[0] == '=' ||
3510 Constraint[0] == '+' ||
3511 Constraint[0] == '&')
3512 Constraint = Constraint.substr(1);
3514 return validateOperandSize(Constraint, Size);
3517 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3518 unsigned Size) const {
3519 return validateOperandSize(Constraint, Size);
3522 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3523 unsigned Size) const {
3524 switch (Constraint[0]) {
3533 // 256-bit ymm registers can be used if target supports AVX.
3534 return Size <= (SSELevel >= AVX ? 256U : 128U);
3541 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3542 switch (*Constraint) {
3543 case 'a': return std::string("{ax}");
3544 case 'b': return std::string("{bx}");
3545 case 'c': return std::string("{cx}");
3546 case 'd': return std::string("{dx}");
3547 case 'S': return std::string("{si}");
3548 case 'D': return std::string("{di}");
3549 case 'p': // address
3550 return std::string("im");
3551 case 't': // top of floating point stack.
3552 return std::string("{st}");
3553 case 'u': // second from top of floating point stack.
3554 return std::string("{st(1)}"); // second from top of floating point stack.
3556 return std::string(1, *Constraint);
3560 // X86-32 generic target
3561 class X86_32TargetInfo : public X86TargetInfo {
3563 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3564 DoubleAlign = LongLongAlign = 32;
3565 LongDoubleWidth = 96;
3566 LongDoubleAlign = 32;
3567 SuitableAlign = 128;
3568 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3569 SizeType = UnsignedInt;
3570 PtrDiffType = SignedInt;
3571 IntPtrType = SignedInt;
3574 // Use fpret for all types.
3575 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3576 (1 << TargetInfo::Double) |
3577 (1 << TargetInfo::LongDouble));
3579 // x86-32 has atomics up to 8 bytes
3580 // FIXME: Check that we actually have cmpxchg8b before setting
3581 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3582 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3584 BuiltinVaListKind getBuiltinVaListKind() const override {
3585 return TargetInfo::CharPtrBuiltinVaList;
3588 int getEHDataRegisterNumber(unsigned RegNo) const override {
3589 if (RegNo == 0) return 0;
3590 if (RegNo == 1) return 2;
3593 bool validateOperandSize(StringRef Constraint,
3594 unsigned Size) const override {
3595 switch (Constraint[0]) {
3611 return X86TargetInfo::validateOperandSize(Constraint, Size);
3615 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3617 NetBSDI386TargetInfo(const llvm::Triple &Triple)
3618 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3620 unsigned getFloatEvalMethod() const override {
3621 unsigned Major, Minor, Micro;
3622 getTriple().getOSVersion(Major, Minor, Micro);
3623 // New NetBSD uses the default rounding mode.
3624 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3625 return X86_32TargetInfo::getFloatEvalMethod();
3626 // NetBSD before 6.99.26 defaults to "double" rounding.
3631 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3633 OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3634 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3635 SizeType = UnsignedLong;
3636 IntPtrType = SignedLong;
3637 PtrDiffType = SignedLong;
3641 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3643 BitrigI386TargetInfo(const llvm::Triple &Triple)
3644 : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3645 SizeType = UnsignedLong;
3646 IntPtrType = SignedLong;
3647 PtrDiffType = SignedLong;
3651 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3653 DarwinI386TargetInfo(const llvm::Triple &Triple)
3654 : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3655 LongDoubleWidth = 128;
3656 LongDoubleAlign = 128;
3657 SuitableAlign = 128;
3658 MaxVectorAlign = 256;
3659 SizeType = UnsignedLong;
3660 IntPtrType = SignedLong;
3661 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3662 HasAlignMac68kSupport = true;
3667 // x86-32 Windows target
3668 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3670 WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3671 : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3672 WCharType = UnsignedShort;
3673 DoubleAlign = LongLongAlign = 64;
3675 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3676 DescriptionString = IsWinCOFF
3677 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
3678 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3680 void getTargetDefines(const LangOptions &Opts,
3681 MacroBuilder &Builder) const override {
3682 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3686 // x86-32 Windows Visual Studio target
3687 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3689 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3690 : WindowsX86_32TargetInfo(Triple) {
3691 LongDoubleWidth = LongDoubleAlign = 64;
3692 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3694 void getTargetDefines(const LangOptions &Opts,
3695 MacroBuilder &Builder) const override {
3696 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3697 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3698 // The value of the following reflects processor type.
3699 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3700 // We lost the original triple, so we use the default.
3701 Builder.defineMacro("_M_IX86", "600");
3704 } // end anonymous namespace
3706 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3707 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang supports
3708 // __declspec natively under -fms-extensions, but we define a no-op __declspec
3709 // macro anyway for pre-processor compatibility.
3710 if (Opts.MicrosoftExt)
3711 Builder.defineMacro("__declspec", "__declspec");
3713 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3715 if (!Opts.MicrosoftExt) {
3716 // Provide macros for all the calling convention keywords. Provide both
3717 // single and double underscore prefixed variants. These are available on
3718 // x64 as well as x86, even though they have no effect.
3719 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3720 for (const char *CC : CCs) {
3721 std::string GCCSpelling = "__attribute__((__";
3723 GCCSpelling += "__))";
3724 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3725 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3730 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3731 Builder.defineMacro("__MSVCRT__");
3732 Builder.defineMacro("__MINGW32__");
3733 addCygMingDefines(Opts, Builder);
3737 // x86-32 MinGW target
3738 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3740 MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3741 : WindowsX86_32TargetInfo(Triple) {}
3742 void getTargetDefines(const LangOptions &Opts,
3743 MacroBuilder &Builder) const override {
3744 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3745 DefineStd(Builder, "WIN32", Opts);
3746 DefineStd(Builder, "WINNT", Opts);
3747 Builder.defineMacro("_X86_");
3748 addMinGWDefines(Opts, Builder);
3752 // x86-32 Cygwin target
3753 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3755 CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3756 : X86_32TargetInfo(Triple) {
3757 TLSSupported = false;
3758 WCharType = UnsignedShort;
3759 DoubleAlign = LongLongAlign = 64;
3760 DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3762 void getTargetDefines(const LangOptions &Opts,
3763 MacroBuilder &Builder) const override {
3764 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3765 Builder.defineMacro("_X86_");
3766 Builder.defineMacro("__CYGWIN__");
3767 Builder.defineMacro("__CYGWIN32__");
3768 addCygMingDefines(Opts, Builder);
3769 DefineStd(Builder, "unix", Opts);
3771 Builder.defineMacro("_GNU_SOURCE");
3775 // x86-32 Haiku target
3776 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3778 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3779 SizeType = UnsignedLong;
3780 IntPtrType = SignedLong;
3781 PtrDiffType = SignedLong;
3782 ProcessIDType = SignedLong;
3783 this->UserLabelPrefix = "";
3784 this->TLSSupported = false;
3786 void getTargetDefines(const LangOptions &Opts,
3787 MacroBuilder &Builder) const override {
3788 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3789 Builder.defineMacro("__INTEL__");
3790 Builder.defineMacro("__HAIKU__");
3795 template<typename Target>
3796 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3798 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3799 MacroBuilder &Builder) const override {
3800 // RTEMS defines; list based off of gcc output
3802 Builder.defineMacro("__rtems__");
3803 Builder.defineMacro("__ELF__");
3807 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3808 this->UserLabelPrefix = "";
3810 switch (Triple.getArch()) {
3812 case llvm::Triple::x86:
3813 // this->MCountName = ".mcount";
3815 case llvm::Triple::mips:
3816 case llvm::Triple::mipsel:
3817 case llvm::Triple::ppc:
3818 case llvm::Triple::ppc64:
3819 case llvm::Triple::ppc64le:
3820 // this->MCountName = "_mcount";
3822 case llvm::Triple::arm:
3823 // this->MCountName = "__mcount";
3829 // x86-32 RTEMS target
3830 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3832 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3833 SizeType = UnsignedLong;
3834 IntPtrType = SignedLong;
3835 PtrDiffType = SignedLong;
3836 this->UserLabelPrefix = "";
3838 void getTargetDefines(const LangOptions &Opts,
3839 MacroBuilder &Builder) const override {
3840 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3841 Builder.defineMacro("__INTEL__");
3842 Builder.defineMacro("__rtems__");
3846 // x86-64 generic target
3847 class X86_64TargetInfo : public X86TargetInfo {
3849 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3850 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3852 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3853 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3854 LongDoubleWidth = 128;
3855 LongDoubleAlign = 128;
3856 LargeArrayMinWidth = 128;
3857 LargeArrayAlign = 128;
3858 SuitableAlign = 128;
3859 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
3860 PtrDiffType = IsX32 ? SignedInt : SignedLong;
3861 IntPtrType = IsX32 ? SignedInt : SignedLong;
3862 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
3863 Int64Type = IsX32 ? SignedLongLong : SignedLong;
3866 // Pointers are 32-bit in x32.
3867 DescriptionString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3869 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
3870 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3872 // Use fpret only for long double.
3873 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3875 // Use fp2ret for _Complex long double.
3876 ComplexLongDoubleUsesFP2Ret = true;
3878 // x86-64 has atomics up to 16 bytes.
3879 MaxAtomicPromoteWidth = 128;
3880 MaxAtomicInlineWidth = 128;
3882 BuiltinVaListKind getBuiltinVaListKind() const override {
3883 return TargetInfo::X86_64ABIBuiltinVaList;
3886 int getEHDataRegisterNumber(unsigned RegNo) const override {
3887 if (RegNo == 0) return 0;
3888 if (RegNo == 1) return 1;
3892 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3893 return (CC == CC_C ||
3894 CC == CC_X86VectorCall ||
3895 CC == CC_IntelOclBicc ||
3896 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3899 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3903 // for x32 we need it here explicitly
3904 bool hasInt128Type() const override { return true; }
3907 // x86-64 Windows target
3908 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3910 WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3911 : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3912 WCharType = UnsignedShort;
3913 LongWidth = LongAlign = 32;
3914 DoubleAlign = LongLongAlign = 64;
3915 IntMaxType = SignedLongLong;
3916 Int64Type = SignedLongLong;
3917 SizeType = UnsignedLongLong;
3918 PtrDiffType = SignedLongLong;
3919 IntPtrType = SignedLongLong;
3920 this->UserLabelPrefix = "";
3923 void getTargetDefines(const LangOptions &Opts,
3924 MacroBuilder &Builder) const override {
3925 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3926 Builder.defineMacro("_WIN64");
3929 BuiltinVaListKind getBuiltinVaListKind() const override {
3930 return TargetInfo::CharPtrBuiltinVaList;
3933 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3936 case CC_X86ThisCall:
3937 case CC_X86FastCall:
3940 case CC_X86VectorCall:
3941 case CC_IntelOclBicc:
3945 return CCCR_Warning;
3950 // x86-64 Windows Visual Studio target
3951 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3953 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3954 : WindowsX86_64TargetInfo(Triple) {
3955 LongDoubleWidth = LongDoubleAlign = 64;
3956 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3958 void getTargetDefines(const LangOptions &Opts,
3959 MacroBuilder &Builder) const override {
3960 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3961 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3962 Builder.defineMacro("_M_X64");
3963 Builder.defineMacro("_M_AMD64");
3967 // x86-64 MinGW target
3968 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3970 MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3971 : WindowsX86_64TargetInfo(Triple) {
3972 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
3973 // with x86 FP ops. Weird.
3974 LongDoubleWidth = LongDoubleAlign = 128;
3975 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
3978 void getTargetDefines(const LangOptions &Opts,
3979 MacroBuilder &Builder) const override {
3980 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3981 DefineStd(Builder, "WIN64", Opts);
3982 Builder.defineMacro("__MINGW64__");
3983 addMinGWDefines(Opts, Builder);
3985 // GCC defines this macro when it is using __gxx_personality_seh0.
3986 if (!Opts.SjLjExceptions)
3987 Builder.defineMacro("__SEH__");
3991 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3993 DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3994 : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3995 Int64Type = SignedLongLong;
3996 MaxVectorAlign = 256;
3997 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3998 llvm::Triple T = llvm::Triple(Triple);
4000 UseSignedCharForObjCBool = false;
4001 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
4005 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
4007 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
4008 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
4009 IntMaxType = SignedLongLong;
4010 Int64Type = SignedLongLong;
4014 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
4016 BitrigX86_64TargetInfo(const llvm::Triple &Triple)
4017 : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
4018 IntMaxType = SignedLongLong;
4019 Int64Type = SignedLongLong;
4023 class ARMTargetInfo : public TargetInfo {
4024 // Possible FPU choices.
4033 // Possible HWDiv features.
4035 HWDivThumb = (1 << 0),
4039 static bool FPUModeIsVFP(FPUMode Mode) {
4040 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
4043 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4044 static const char * const GCCRegNames[];
4046 std::string ABI, CPU;
4056 unsigned IsAAPCS : 1;
4057 unsigned IsThumb : 1;
4060 // Initialized via features.
4061 unsigned SoftFloat : 1;
4062 unsigned SoftFloatABI : 1;
4065 unsigned Crypto : 1;
4067 // ACLE 6.5.1 Hardware floating point
4069 HW_FP_HP = (1 << 1), /// half (16-bit)
4070 HW_FP_SP = (1 << 2), /// single (32-bit)
4071 HW_FP_DP = (1 << 3), /// double (64-bit)
4075 static const Builtin::Info BuiltinInfo[];
4077 static bool shouldUseInlineAtomic(const llvm::Triple &T) {
4078 StringRef ArchName = T.getArchName();
4079 if (T.getArch() == llvm::Triple::arm ||
4080 T.getArch() == llvm::Triple::armeb) {
4081 StringRef VersionStr;
4082 if (ArchName.startswith("armv"))
4083 VersionStr = ArchName.substr(4, 1);
4084 else if (ArchName.startswith("armebv"))
4085 VersionStr = ArchName.substr(6, 1);
4089 if (VersionStr.getAsInteger(10, Version))
4091 return Version >= 6;
4093 assert(T.getArch() == llvm::Triple::thumb ||
4094 T.getArch() == llvm::Triple::thumbeb);
4095 StringRef VersionStr;
4096 if (ArchName.startswith("thumbv"))
4097 VersionStr = ArchName.substr(6, 1);
4098 else if (ArchName.startswith("thumbebv"))
4099 VersionStr = ArchName.substr(8, 1);
4103 if (VersionStr.getAsInteger(10, Version))
4105 return Version >= 7;
4108 void setABIAAPCS() {
4111 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4112 const llvm::Triple &T = getTriple();
4114 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig.
4115 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
4116 T.getOS() == llvm::Triple::Bitrig)
4117 SizeType = UnsignedLong;
4119 SizeType = UnsignedInt;
4121 switch (T.getOS()) {
4122 case llvm::Triple::NetBSD:
4123 WCharType = SignedInt;
4125 case llvm::Triple::Win32:
4126 WCharType = UnsignedShort;
4128 case llvm::Triple::Linux:
4130 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
4131 WCharType = UnsignedInt;
4135 UseBitFieldTypeAlignment = true;
4137 ZeroLengthBitfieldBoundary = 0;
4139 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
4140 // so set preferred for small types to 32.
4141 if (T.isOSBinFormatMachO()) {
4143 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4144 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4145 } else if (T.isOSWindows()) {
4146 assert(!BigEndian && "Windows on ARM does not support big endian");
4147 DescriptionString = "e"
4155 } else if (T.isOSNaCl()) {
4156 assert(!BigEndian && "NaCl on ARM does not support big endian");
4157 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
4160 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4161 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4164 // FIXME: Enumerated types are variable width in straight AAPCS.
4168 const llvm::Triple &T = getTriple();
4172 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
4174 // size_t is unsigned int on FreeBSD.
4175 if (T.getOS() == llvm::Triple::FreeBSD)
4176 SizeType = UnsignedInt;
4178 SizeType = UnsignedLong;
4180 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
4181 WCharType = SignedInt;
4183 // Do not respect the alignment of bit-field types when laying out
4184 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
4185 UseBitFieldTypeAlignment = false;
4187 /// gcc forces the alignment to 4 bytes, regardless of the type of the
4188 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
4190 ZeroLengthBitfieldBoundary = 32;
4192 if (T.isOSBinFormatMachO())
4195 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4196 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4200 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4201 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4203 // FIXME: Override "preferred align" for double and long long.
4207 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
4208 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
4209 IsAAPCS(true), HW_FP(0) {
4210 BigEndian = IsBigEndian;
4212 switch (getTriple().getOS()) {
4213 case llvm::Triple::NetBSD:
4214 PtrDiffType = SignedLong;
4217 PtrDiffType = SignedInt;
4221 // {} in inline assembly are neon specifiers, not assembly variant
4223 NoAsmVariants = true;
4225 // FIXME: Should we just treat this as a feature?
4226 IsThumb = getTriple().getArchName().startswith("thumb");
4228 // FIXME: This duplicates code from the driver that sets the -target-abi
4229 // option - this code is used if -target-abi isn't passed and should
4230 // be unified in some way.
4231 if (Triple.isOSBinFormatMachO()) {
4232 // The backend is hardwired to assume AAPCS for M-class processors, ensure
4233 // the frontend matches that.
4234 if (Triple.getEnvironment() == llvm::Triple::EABI ||
4235 Triple.getOS() == llvm::Triple::UnknownOS ||
4236 StringRef(CPU).startswith("cortex-m")) {
4241 } else if (Triple.isOSWindows()) {
4242 // FIXME: this is invalid for WindowsCE
4245 // Select the default based on the platform.
4246 switch (Triple.getEnvironment()) {
4247 case llvm::Triple::Android:
4248 case llvm::Triple::GNUEABI:
4249 case llvm::Triple::GNUEABIHF:
4250 setABI("aapcs-linux");
4252 case llvm::Triple::EABIHF:
4253 case llvm::Triple::EABI:
4256 case llvm::Triple::GNU:
4260 if (Triple.getOS() == llvm::Triple::NetBSD)
4268 // ARM targets default to using the ARM C++ ABI.
4269 TheCXXABI.set(TargetCXXABI::GenericARM);
4271 // ARM has atomics up to 8 bytes
4272 MaxAtomicPromoteWidth = 64;
4273 if (shouldUseInlineAtomic(getTriple()))
4274 MaxAtomicInlineWidth = 64;
4276 // Do force alignment of members that follow zero length bitfields. If
4277 // the alignment of the zero-length bitfield is greater than the member
4278 // that follows it, `bar', `bar' will be aligned as the type of the
4279 // zero length bitfield.
4280 UseZeroLengthBitfieldAlignment = true;
4283 StringRef getABI() const override { return ABI; }
4285 bool setABI(const std::string &Name) override {
4288 // The defaults (above) are for AAPCS, check if we need to change them.
4290 // FIXME: We need support for -meabi... we could just mangle it into the
4292 if (Name == "apcs-gnu") {
4296 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
4303 // FIXME: This should be based on Arch attributes, not CPU names.
4304 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
4305 StringRef ArchName = getTriple().getArchName();
4306 unsigned ArchKind = llvm::ARMTargetParser::parseArch(ArchName);
4307 bool IsV8 = (ArchKind == llvm::ARM::AK_ARMV8A ||
4308 ArchKind == llvm::ARM::AK_ARMV8_1A);
4310 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
4311 Features["vfp2"] = true;
4312 else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
4313 Features["vfp3"] = true;
4314 Features["neon"] = true;
4316 else if (CPU == "cortex-a5") {
4317 Features["vfp4"] = true;
4318 Features["neon"] = true;
4319 } else if (CPU == "swift" || CPU == "cortex-a7" ||
4320 CPU == "cortex-a12" || CPU == "cortex-a15" ||
4321 CPU == "cortex-a17" || CPU == "krait") {
4322 Features["vfp4"] = true;
4323 Features["neon"] = true;
4324 Features["hwdiv"] = true;
4325 Features["hwdiv-arm"] = true;
4326 } else if (CPU == "cyclone" || CPU == "cortex-a53" || CPU == "cortex-a57" ||
4327 CPU == "cortex-a72") {
4328 Features["fp-armv8"] = true;
4329 Features["neon"] = true;
4330 Features["hwdiv"] = true;
4331 Features["hwdiv-arm"] = true;
4332 Features["crc"] = true;
4333 Features["crypto"] = true;
4334 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || IsV8) {
4335 Features["hwdiv"] = true;
4336 Features["hwdiv-arm"] = true;
4337 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" ||
4338 CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") {
4339 Features["hwdiv"] = true;
4343 bool handleTargetFeatures(std::vector<std::string> &Features,
4344 DiagnosticsEngine &Diags) override {
4348 SoftFloat = SoftFloatABI = false;
4351 // This does not diagnose illegal cases like having both
4352 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
4353 uint32_t HW_FP_remove = 0;
4354 for (const auto &Feature : Features) {
4355 if (Feature == "+soft-float") {
4357 } else if (Feature == "+soft-float-abi") {
4358 SoftFloatABI = true;
4359 } else if (Feature == "+vfp2") {
4361 HW_FP |= HW_FP_SP | HW_FP_DP;
4362 } else if (Feature == "+vfp3") {
4364 HW_FP |= HW_FP_SP | HW_FP_DP;
4365 } else if (Feature == "+vfp4") {
4367 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
4368 } else if (Feature == "+fp-armv8") {
4370 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
4371 } else if (Feature == "+neon") {
4373 HW_FP |= HW_FP_SP | HW_FP_DP;
4374 } else if (Feature == "+hwdiv") {
4375 HWDiv |= HWDivThumb;
4376 } else if (Feature == "+hwdiv-arm") {
4378 } else if (Feature == "+crc") {
4380 } else if (Feature == "+crypto") {
4382 } else if (Feature == "+fp-only-sp") {
4383 HW_FP_remove |= HW_FP_DP | HW_FP_HP;
4386 HW_FP &= ~HW_FP_remove;
4388 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4389 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4393 if (FPMath == FP_Neon)
4394 Features.push_back("+neonfp");
4395 else if (FPMath == FP_VFP)
4396 Features.push_back("-neonfp");
4398 // Remove front-end specific options which the backend handles differently.
4400 std::find(Features.begin(), Features.end(), "+soft-float-abi");
4401 if (Feature != Features.end())
4402 Features.erase(Feature);
4407 bool hasFeature(StringRef Feature) const override {
4408 return llvm::StringSwitch<bool>(Feature)
4410 .Case("softfloat", SoftFloat)
4411 .Case("thumb", IsThumb)
4412 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4413 .Case("hwdiv", HWDiv & HWDivThumb)
4414 .Case("hwdiv-arm", HWDiv & HWDivARM)
4417 const char *getCPUDefineSuffix(StringRef Name) const {
4418 if(Name == "generic") {
4419 auto subarch = getTriple().getSubArch();
4421 case llvm::Triple::SubArchType::ARMSubArch_v8_1a:
4428 unsigned ArchKind = llvm::ARMTargetParser::parseCPUArch(Name);
4429 if (ArchKind == llvm::ARM::AK_INVALID)
4432 // For most sub-arches, the build attribute CPU name is enough.
4433 // For Cortex variants, it's slightly different.
4436 return llvm::ARMTargetParser::getCPUAttr(ArchKind);
4437 case llvm::ARM::AK_ARMV6M:
4438 case llvm::ARM::AK_ARMV6SM:
4440 case llvm::ARM::AK_ARMV7:
4441 case llvm::ARM::AK_ARMV7A:
4442 case llvm::ARM::AK_ARMV7S:
4444 case llvm::ARM::AK_ARMV7R:
4446 case llvm::ARM::AK_ARMV7M:
4448 case llvm::ARM::AK_ARMV7EM:
4450 case llvm::ARM::AK_ARMV8A:
4452 case llvm::ARM::AK_ARMV8_1A:
4456 const char *getCPUProfile(StringRef Name) const {
4457 if(Name == "generic") {
4458 auto subarch = getTriple().getSubArch();
4460 case llvm::Triple::SubArchType::ARMSubArch_v8_1a:
4467 unsigned CPUArch = llvm::ARMTargetParser::parseCPUArch(Name);
4468 if (CPUArch == llvm::ARM::AK_INVALID)
4471 StringRef ArchName = llvm::ARMTargetParser::getArchName(CPUArch);
4472 switch(llvm::ARMTargetParser::parseArchProfile(ArchName)) {
4473 case llvm::ARM::PK_A:
4475 case llvm::ARM::PK_R:
4477 case llvm::ARM::PK_M:
4483 bool setCPU(const std::string &Name) override {
4484 if (!getCPUDefineSuffix(Name))
4487 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4488 StringRef Profile = getCPUProfile(Name);
4489 if (Profile == "M" && MaxAtomicInlineWidth) {
4490 MaxAtomicPromoteWidth = 32;
4491 MaxAtomicInlineWidth = 32;
4497 bool setFPMath(StringRef Name) override;
4498 bool supportsThumb(StringRef ArchName, StringRef CPUArch,
4499 unsigned CPUArchVer) const {
4500 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
4501 (CPUArch.find('M') != StringRef::npos);
4503 bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
4504 unsigned CPUArchVer) const {
4505 // We check both CPUArchVer and ArchName because when only triple is
4506 // specified, the default CPU is arm1136j-s.
4507 return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
4508 ArchName.endswith("v8.1a") ||
4509 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
4511 void getTargetDefines(const LangOptions &Opts,
4512 MacroBuilder &Builder) const override {
4513 // Target identification.
4514 Builder.defineMacro("__arm");
4515 Builder.defineMacro("__arm__");
4517 // Target properties.
4518 Builder.defineMacro("__REGISTER_PREFIX__", "");
4520 StringRef CPUArch = getCPUDefineSuffix(CPU);
4521 unsigned int CPUArchVer;
4522 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
4523 llvm_unreachable("Invalid char for architecture version number");
4524 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
4526 // ACLE 6.4.1 ARM/Thumb instruction set architecture
4527 StringRef CPUProfile = getCPUProfile(CPU);
4528 StringRef ArchName = getTriple().getArchName();
4530 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4531 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
4532 if (CPUArch[0] >= '8') {
4533 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4534 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4537 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
4538 // is not defined for the M-profile.
4539 // NOTE that the deffault profile is assumed to be 'A'
4540 if (CPUProfile.empty() || CPUProfile != "M")
4541 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4543 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4544 // Thumb ISA (including v6-M). It is set to 2 if the core supports the
4545 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4546 if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4547 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4548 else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
4549 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4551 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4552 // instruction set such as ARM or Thumb.
4553 Builder.defineMacro("__ARM_32BIT_STATE", "1");
4555 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4557 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4558 if (!CPUProfile.empty())
4559 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4561 // ACLE 6.5.1 Hardware Floating Point
4563 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4566 Builder.defineMacro("__ARM_ACLE", "200");
4568 // Subtarget options.
4570 // FIXME: It's more complicated than this and we don't really support
4572 // Windows on ARM does not "support" interworking
4573 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
4574 Builder.defineMacro("__THUMB_INTERWORK__");
4576 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4577 // Embedded targets on Darwin follow AAPCS, but not EABI.
4578 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4579 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4580 Builder.defineMacro("__ARM_EABI__");
4581 Builder.defineMacro("__ARM_PCS", "1");
4583 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4584 Builder.defineMacro("__ARM_PCS_VFP", "1");
4588 Builder.defineMacro("__SOFTFP__");
4590 if (CPU == "xscale")
4591 Builder.defineMacro("__XSCALE__");
4594 Builder.defineMacro("__THUMBEL__");
4595 Builder.defineMacro("__thumb__");
4596 if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4597 Builder.defineMacro("__thumb2__");
4599 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4600 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4602 // Note, this is always on in gcc, even though it doesn't make sense.
4603 Builder.defineMacro("__APCS_32__");
4605 if (FPUModeIsVFP((FPUMode) FPU)) {
4606 Builder.defineMacro("__VFP_FP__");
4608 Builder.defineMacro("__ARM_VFPV2__");
4610 Builder.defineMacro("__ARM_VFPV3__");
4612 Builder.defineMacro("__ARM_VFPV4__");
4615 // This only gets set when Neon instructions are actually available, unlike
4616 // the VFP define, hence the soft float and arch check. This is subtly
4617 // different from gcc, we follow the intent which was that it should be set
4618 // when Neon instructions are actually available.
4619 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
4620 Builder.defineMacro("__ARM_NEON");
4621 Builder.defineMacro("__ARM_NEON__");
4624 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4625 Opts.ShortWChar ? "2" : "4");
4627 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4628 Opts.ShortEnums ? "1" : "4");
4631 Builder.defineMacro("__ARM_FEATURE_CRC32");
4634 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4636 if (CPUArchVer >= 6 && CPUArch != "6M") {
4637 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4638 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4639 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4640 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4643 bool is5EOrAbove = (CPUArchVer >= 6 ||
4645 CPUArch.find('E') != StringRef::npos));
4646 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer));
4647 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM"))
4648 Builder.defineMacro("__ARM_FEATURE_DSP");
4650 void getTargetBuiltins(const Builtin::Info *&Records,
4651 unsigned &NumRecords) const override {
4652 Records = BuiltinInfo;
4653 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4655 bool isCLZForZeroUndef() const override { return false; }
4656 BuiltinVaListKind getBuiltinVaListKind() const override {
4657 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4659 void getGCCRegNames(const char * const *&Names,
4660 unsigned &NumNames) const override;
4661 void getGCCRegAliases(const GCCRegAlias *&Aliases,
4662 unsigned &NumAliases) const override;
4663 bool validateAsmConstraint(const char *&Name,
4664 TargetInfo::ConstraintInfo &Info) const override {
4669 case 'w': // VFP Floating point register single precision
4670 case 'P': // VFP Floating point register double precision
4671 Info.setAllowsRegister();
4680 case 'Q': // A memory address that is a single base register.
4681 Info.setAllowsMemory();
4683 case 'U': // a memory reference...
4685 case 'q': // ...ARMV4 ldrsb
4686 case 'v': // ...VFP load/store (reg+constant offset)
4687 case 'y': // ...iWMMXt load/store
4688 case 't': // address valid for load/store opaque types wider
4690 case 'n': // valid address for Neon doubleword vector load/store
4691 case 'm': // valid address for Neon element and structure load/store
4692 case 's': // valid address for non-offset loads/stores of quad-word
4693 // values in four ARM registers
4694 Info.setAllowsMemory();
4701 std::string convertConstraint(const char *&Constraint) const override {
4703 switch (*Constraint) {
4704 case 'U': // Two-character constraint; add "^" hint for later parsing.
4705 R = std::string("^") + std::string(Constraint, 2);
4708 case 'p': // 'p' should be translated to 'r' by default.
4709 R = std::string("r");
4712 return std::string(1, *Constraint);
4717 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4718 std::string &SuggestedModifier) const override {
4719 bool isOutput = (Constraint[0] == '=');
4720 bool isInOut = (Constraint[0] == '+');
4722 // Strip off constraint modifiers.
4723 while (Constraint[0] == '=' ||
4724 Constraint[0] == '+' ||
4725 Constraint[0] == '&')
4726 Constraint = Constraint.substr(1);
4728 switch (Constraint[0]) {
4733 return (isInOut || isOutput || Size <= 64);
4735 // A register of size 32 cannot fit a vector type.
4743 const char *getClobbers() const override {
4744 // FIXME: Is this really right?
4748 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4749 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4752 int getEHDataRegisterNumber(unsigned RegNo) const override {
4753 if (RegNo == 0) return 0;
4754 if (RegNo == 1) return 1;
4759 bool ARMTargetInfo::setFPMath(StringRef Name) {
4760 if (Name == "neon") {
4763 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4771 const char * const ARMTargetInfo::GCCRegNames[] = {
4772 // Integer registers
4773 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4774 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4777 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4778 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4779 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4780 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4783 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4784 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4785 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4786 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4789 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4790 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4793 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4794 unsigned &NumNames) const {
4795 Names = GCCRegNames;
4796 NumNames = llvm::array_lengthof(GCCRegNames);
4799 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4809 { { "v6", "rfp" }, "r9" },
4810 { { "sl" }, "r10" },
4811 { { "fp" }, "r11" },
4812 { { "ip" }, "r12" },
4813 { { "r13" }, "sp" },
4814 { { "r14" }, "lr" },
4815 { { "r15" }, "pc" },
4816 // The S, D and Q registers overlap, but aren't really aliases; we
4817 // don't want to substitute one of these for a different-sized one.
4820 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4821 unsigned &NumAliases) const {
4822 Aliases = GCCRegAliases;
4823 NumAliases = llvm::array_lengthof(GCCRegAliases);
4826 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4827 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4828 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4830 #include "clang/Basic/BuiltinsNEON.def"
4832 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4833 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4834 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4836 #include "clang/Basic/BuiltinsARM.def"
4839 class ARMleTargetInfo : public ARMTargetInfo {
4841 ARMleTargetInfo(const llvm::Triple &Triple)
4842 : ARMTargetInfo(Triple, false) { }
4843 void getTargetDefines(const LangOptions &Opts,
4844 MacroBuilder &Builder) const override {
4845 Builder.defineMacro("__ARMEL__");
4846 ARMTargetInfo::getTargetDefines(Opts, Builder);
4850 class ARMbeTargetInfo : public ARMTargetInfo {
4852 ARMbeTargetInfo(const llvm::Triple &Triple)
4853 : ARMTargetInfo(Triple, true) { }
4854 void getTargetDefines(const LangOptions &Opts,
4855 MacroBuilder &Builder) const override {
4856 Builder.defineMacro("__ARMEB__");
4857 Builder.defineMacro("__ARM_BIG_ENDIAN");
4858 ARMTargetInfo::getTargetDefines(Opts, Builder);
4862 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4863 const llvm::Triple Triple;
4865 WindowsARMTargetInfo(const llvm::Triple &Triple)
4866 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4867 TLSSupported = false;
4868 WCharType = UnsignedShort;
4869 SizeType = UnsignedInt;
4870 UserLabelPrefix = "";
4872 void getVisualStudioDefines(const LangOptions &Opts,
4873 MacroBuilder &Builder) const {
4874 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4876 // FIXME: this is invalid for WindowsCE
4877 Builder.defineMacro("_M_ARM_NT", "1");
4878 Builder.defineMacro("_M_ARMT", "_M_ARM");
4879 Builder.defineMacro("_M_THUMB", "_M_ARM");
4881 assert((Triple.getArch() == llvm::Triple::arm ||
4882 Triple.getArch() == llvm::Triple::thumb) &&
4883 "invalid architecture for Windows ARM target info");
4884 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4885 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4887 // TODO map the complete set of values
4888 // 31: VFPv3 40: VFPv4
4889 Builder.defineMacro("_M_ARM_FP", "31");
4891 BuiltinVaListKind getBuiltinVaListKind() const override {
4892 return TargetInfo::CharPtrBuiltinVaList;
4896 // Windows ARM + Itanium C++ ABI Target
4897 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4899 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4900 : WindowsARMTargetInfo(Triple) {
4901 TheCXXABI.set(TargetCXXABI::GenericARM);
4904 void getTargetDefines(const LangOptions &Opts,
4905 MacroBuilder &Builder) const override {
4906 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4908 if (Opts.MSVCCompat)
4909 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4913 // Windows ARM, MS (C++) ABI
4914 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4916 MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4917 : WindowsARMTargetInfo(Triple) {
4918 TheCXXABI.set(TargetCXXABI::Microsoft);
4921 void getTargetDefines(const LangOptions &Opts,
4922 MacroBuilder &Builder) const override {
4923 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4924 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4928 class DarwinARMTargetInfo :
4929 public DarwinTargetInfo<ARMleTargetInfo> {
4931 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4932 MacroBuilder &Builder) const override {
4933 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4937 DarwinARMTargetInfo(const llvm::Triple &Triple)
4938 : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4939 HasAlignMac68kSupport = true;
4940 // iOS always has 64-bit atomic instructions.
4941 // FIXME: This should be based off of the target features in
4943 MaxAtomicInlineWidth = 64;
4945 // Darwin on iOS uses a variant of the ARM C++ ABI.
4946 TheCXXABI.set(TargetCXXABI::iOS);
4950 class AArch64TargetInfo : public TargetInfo {
4951 virtual void setDescriptionString() = 0;
4952 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4953 static const char *const GCCRegNames[];
4964 static const Builtin::Info BuiltinInfo[];
4969 AArch64TargetInfo(const llvm::Triple &Triple)
4970 : TargetInfo(Triple), ABI("aapcs") {
4972 if (getTriple().getOS() == llvm::Triple::NetBSD) {
4973 WCharType = SignedInt;
4975 // NetBSD apparently prefers consistency across ARM targets to consistency
4976 // across 64-bit targets.
4977 Int64Type = SignedLongLong;
4978 IntMaxType = SignedLongLong;
4980 WCharType = UnsignedInt;
4981 Int64Type = SignedLong;
4982 IntMaxType = SignedLong;
4985 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4986 MaxVectorAlign = 128;
4987 MaxAtomicInlineWidth = 128;
4988 MaxAtomicPromoteWidth = 128;
4990 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
4991 LongDoubleFormat = &llvm::APFloat::IEEEquad;
4993 // {} in inline assembly are neon specifiers, not assembly variant
4995 NoAsmVariants = true;
4997 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
4998 // contributes to the alignment of the containing aggregate in the same way
4999 // a plain (non bit-field) member of that type would, without exception for
5000 // zero-sized or anonymous bit-fields."
5001 UseBitFieldTypeAlignment = true;
5002 UseZeroLengthBitfieldAlignment = true;
5004 // AArch64 targets default to using the ARM C++ ABI.
5005 TheCXXABI.set(TargetCXXABI::GenericAArch64);
5008 StringRef getABI() const override { return ABI; }
5009 bool setABI(const std::string &Name) override {
5010 if (Name != "aapcs" && Name != "darwinpcs")
5017 bool setCPU(const std::string &Name) override {
5018 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5019 .Case("generic", true)
5020 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true)
5021 .Case("cyclone", true)
5026 void getTargetDefines(const LangOptions &Opts,
5027 MacroBuilder &Builder) const override {
5028 // Target identification.
5029 Builder.defineMacro("__aarch64__");
5031 // Target properties.
5032 Builder.defineMacro("_LP64");
5033 Builder.defineMacro("__LP64__");
5035 // ACLE predefines. Many can only have one possible value on v8 AArch64.
5036 Builder.defineMacro("__ARM_ACLE", "200");
5037 Builder.defineMacro("__ARM_ARCH", "8");
5038 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
5040 Builder.defineMacro("__ARM_64BIT_STATE");
5041 Builder.defineMacro("__ARM_PCS_AAPCS64");
5042 Builder.defineMacro("__ARM_ARCH_ISA_A64");
5044 Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
5045 Builder.defineMacro("__ARM_FEATURE_CLZ");
5046 Builder.defineMacro("__ARM_FEATURE_FMA");
5047 Builder.defineMacro("__ARM_FEATURE_DIV");
5048 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
5049 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
5050 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
5051 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
5053 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
5055 // 0xe implies support for half, single and double precision operations.
5056 Builder.defineMacro("__ARM_FP", "0xe");
5058 // PCS specifies this for SysV variants, which is all we support. Other ABIs
5059 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
5060 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
5062 if (Opts.FastMath || Opts.FiniteMathOnly)
5063 Builder.defineMacro("__ARM_FP_FAST");
5065 if (Opts.C99 && !Opts.Freestanding)
5066 Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
5068 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
5070 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5071 Opts.ShortEnums ? "1" : "4");
5073 if (FPU == NeonMode) {
5074 Builder.defineMacro("__ARM_NEON");
5075 // 64-bit NEON supports half, single and double precision operations.
5076 Builder.defineMacro("__ARM_NEON_FP", "0xe");
5080 Builder.defineMacro("__ARM_FEATURE_CRC32");
5083 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
5085 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
5086 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
5087 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
5088 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
5089 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
5092 void getTargetBuiltins(const Builtin::Info *&Records,
5093 unsigned &NumRecords) const override {
5094 Records = BuiltinInfo;
5095 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
5098 bool hasFeature(StringRef Feature) const override {
5099 return Feature == "aarch64" ||
5100 Feature == "arm64" ||
5101 (Feature == "neon" && FPU == NeonMode);
5104 bool handleTargetFeatures(std::vector<std::string> &Features,
5105 DiagnosticsEngine &Diags) override {
5109 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
5110 if (Features[i] == "+neon")
5112 if (Features[i] == "+crc")
5114 if (Features[i] == "+crypto")
5118 setDescriptionString();
5123 bool isCLZForZeroUndef() const override { return false; }
5125 BuiltinVaListKind getBuiltinVaListKind() const override {
5126 return TargetInfo::AArch64ABIBuiltinVaList;
5129 void getGCCRegNames(const char *const *&Names,
5130 unsigned &NumNames) const override;
5131 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5132 unsigned &NumAliases) const override;
5134 bool validateAsmConstraint(const char *&Name,
5135 TargetInfo::ConstraintInfo &Info) const override {
5139 case 'w': // Floating point and SIMD registers (V0-V31)
5140 Info.setAllowsRegister();
5142 case 'I': // Constant that can be used with an ADD instruction
5143 case 'J': // Constant that can be used with a SUB instruction
5144 case 'K': // Constant that can be used with a 32-bit logical instruction
5145 case 'L': // Constant that can be used with a 64-bit logical instruction
5146 case 'M': // Constant that can be used as a 32-bit MOV immediate
5147 case 'N': // Constant that can be used as a 64-bit MOV immediate
5148 case 'Y': // Floating point constant zero
5149 case 'Z': // Integer constant zero
5151 case 'Q': // A memory reference with base register and no offset
5152 Info.setAllowsMemory();
5154 case 'S': // A symbolic address
5155 Info.setAllowsRegister();
5158 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
5159 // Utf: A memory address suitable for ldp/stp in TF mode.
5160 // Usa: An absolute symbolic address.
5161 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
5162 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
5163 case 'z': // Zero register, wzr or xzr
5164 Info.setAllowsRegister();
5166 case 'x': // Floating point and SIMD registers (V0-V15)
5167 Info.setAllowsRegister();
5174 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5175 std::string &SuggestedModifier) const override {
5176 // Strip off constraint modifiers.
5177 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
5178 Constraint = Constraint.substr(1);
5180 switch (Constraint[0]) {
5188 // For now assume that the person knows what they're
5189 // doing with the modifier.
5192 // By default an 'r' constraint will be in the 'x'
5197 SuggestedModifier = "w";
5204 const char *getClobbers() const override { return ""; }
5206 int getEHDataRegisterNumber(unsigned RegNo) const override {
5215 const char *const AArch64TargetInfo::GCCRegNames[] = {
5216 // 32-bit Integer registers
5217 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
5218 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
5219 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
5221 // 64-bit Integer registers
5222 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
5223 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
5224 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
5226 // 32-bit floating point regsisters
5227 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
5228 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
5229 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5231 // 64-bit floating point regsisters
5232 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
5233 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
5234 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5237 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
5238 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
5239 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
5242 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
5243 unsigned &NumNames) const {
5244 Names = GCCRegNames;
5245 NumNames = llvm::array_lengthof(GCCRegNames);
5248 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
5249 { { "w31" }, "wsp" },
5250 { { "x29" }, "fp" },
5251 { { "x30" }, "lr" },
5252 { { "x31" }, "sp" },
5253 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
5254 // don't want to substitute one of these for a different-sized one.
5257 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5258 unsigned &NumAliases) const {
5259 Aliases = GCCRegAliases;
5260 NumAliases = llvm::array_lengthof(GCCRegAliases);
5263 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
5264 #define BUILTIN(ID, TYPE, ATTRS) \
5265 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5266 #include "clang/Basic/BuiltinsNEON.def"
5268 #define BUILTIN(ID, TYPE, ATTRS) \
5269 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5270 #include "clang/Basic/BuiltinsAArch64.def"
5273 class AArch64leTargetInfo : public AArch64TargetInfo {
5274 void setDescriptionString() override {
5275 if (getTriple().isOSBinFormatMachO())
5276 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
5278 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
5282 AArch64leTargetInfo(const llvm::Triple &Triple)
5283 : AArch64TargetInfo(Triple) {
5286 void getTargetDefines(const LangOptions &Opts,
5287 MacroBuilder &Builder) const override {
5288 Builder.defineMacro("__AARCH64EL__");
5289 AArch64TargetInfo::getTargetDefines(Opts, Builder);
5293 class AArch64beTargetInfo : public AArch64TargetInfo {
5294 void setDescriptionString() override {
5295 assert(!getTriple().isOSBinFormatMachO());
5296 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
5300 AArch64beTargetInfo(const llvm::Triple &Triple)
5301 : AArch64TargetInfo(Triple) { }
5302 void getTargetDefines(const LangOptions &Opts,
5303 MacroBuilder &Builder) const override {
5304 Builder.defineMacro("__AARCH64EB__");
5305 Builder.defineMacro("__AARCH_BIG_ENDIAN");
5306 Builder.defineMacro("__ARM_BIG_ENDIAN");
5307 AArch64TargetInfo::getTargetDefines(Opts, Builder);
5311 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
5313 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5314 MacroBuilder &Builder) const override {
5315 Builder.defineMacro("__AARCH64_SIMD__");
5316 Builder.defineMacro("__ARM64_ARCH_8__");
5317 Builder.defineMacro("__ARM_NEON__");
5318 Builder.defineMacro("__LITTLE_ENDIAN__");
5319 Builder.defineMacro("__REGISTER_PREFIX__", "");
5320 Builder.defineMacro("__arm64", "1");
5321 Builder.defineMacro("__arm64__", "1");
5323 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5327 DarwinAArch64TargetInfo(const llvm::Triple &Triple)
5328 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
5329 Int64Type = SignedLongLong;
5330 WCharType = SignedInt;
5331 UseSignedCharForObjCBool = false;
5333 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
5334 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5336 TheCXXABI.set(TargetCXXABI::iOS64);
5339 BuiltinVaListKind getBuiltinVaListKind() const override {
5340 return TargetInfo::CharPtrBuiltinVaList;
5344 // Hexagon abstract base class
5345 class HexagonTargetInfo : public TargetInfo {
5346 static const Builtin::Info BuiltinInfo[];
5347 static const char * const GCCRegNames[];
5348 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5351 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5353 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
5355 // {} in inline assembly are packet specifiers, not assembly variant
5357 NoAsmVariants = true;
5360 void getTargetBuiltins(const Builtin::Info *&Records,
5361 unsigned &NumRecords) const override {
5362 Records = BuiltinInfo;
5363 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
5366 bool validateAsmConstraint(const char *&Name,
5367 TargetInfo::ConstraintInfo &Info) const override {
5371 void getTargetDefines(const LangOptions &Opts,
5372 MacroBuilder &Builder) const override;
5374 bool hasFeature(StringRef Feature) const override {
5375 return Feature == "hexagon";
5378 BuiltinVaListKind getBuiltinVaListKind() const override {
5379 return TargetInfo::CharPtrBuiltinVaList;
5381 void getGCCRegNames(const char * const *&Names,
5382 unsigned &NumNames) const override;
5383 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5384 unsigned &NumAliases) const override;
5385 const char *getClobbers() const override {
5389 static const char *getHexagonCPUSuffix(StringRef Name) {
5390 return llvm::StringSwitch<const char*>(Name)
5391 .Case("hexagonv4", "4")
5392 .Case("hexagonv5", "5")
5396 bool setCPU(const std::string &Name) override {
5397 if (!getHexagonCPUSuffix(Name))
5405 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5406 MacroBuilder &Builder) const {
5407 Builder.defineMacro("qdsp6");
5408 Builder.defineMacro("__qdsp6", "1");
5409 Builder.defineMacro("__qdsp6__", "1");
5411 Builder.defineMacro("hexagon");
5412 Builder.defineMacro("__hexagon", "1");
5413 Builder.defineMacro("__hexagon__", "1");
5415 if(CPU == "hexagonv1") {
5416 Builder.defineMacro("__HEXAGON_V1__");
5417 Builder.defineMacro("__HEXAGON_ARCH__", "1");
5418 if(Opts.HexagonQdsp6Compat) {
5419 Builder.defineMacro("__QDSP6_V1__");
5420 Builder.defineMacro("__QDSP6_ARCH__", "1");
5423 else if(CPU == "hexagonv2") {
5424 Builder.defineMacro("__HEXAGON_V2__");
5425 Builder.defineMacro("__HEXAGON_ARCH__", "2");
5426 if(Opts.HexagonQdsp6Compat) {
5427 Builder.defineMacro("__QDSP6_V2__");
5428 Builder.defineMacro("__QDSP6_ARCH__", "2");
5431 else if(CPU == "hexagonv3") {
5432 Builder.defineMacro("__HEXAGON_V3__");
5433 Builder.defineMacro("__HEXAGON_ARCH__", "3");
5434 if(Opts.HexagonQdsp6Compat) {
5435 Builder.defineMacro("__QDSP6_V3__");
5436 Builder.defineMacro("__QDSP6_ARCH__", "3");
5439 else if(CPU == "hexagonv4") {
5440 Builder.defineMacro("__HEXAGON_V4__");
5441 Builder.defineMacro("__HEXAGON_ARCH__", "4");
5442 if(Opts.HexagonQdsp6Compat) {
5443 Builder.defineMacro("__QDSP6_V4__");
5444 Builder.defineMacro("__QDSP6_ARCH__", "4");
5447 else if(CPU == "hexagonv5") {
5448 Builder.defineMacro("__HEXAGON_V5__");
5449 Builder.defineMacro("__HEXAGON_ARCH__", "5");
5450 if(Opts.HexagonQdsp6Compat) {
5451 Builder.defineMacro("__QDSP6_V5__");
5452 Builder.defineMacro("__QDSP6_ARCH__", "5");
5457 const char * const HexagonTargetInfo::GCCRegNames[] = {
5458 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5459 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5460 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5461 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5462 "p0", "p1", "p2", "p3",
5463 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5466 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
5467 unsigned &NumNames) const {
5468 Names = GCCRegNames;
5469 NumNames = llvm::array_lengthof(GCCRegNames);
5473 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5474 { { "sp" }, "r29" },
5475 { { "fp" }, "r30" },
5476 { { "lr" }, "r31" },
5479 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5480 unsigned &NumAliases) const {
5481 Aliases = GCCRegAliases;
5482 NumAliases = llvm::array_lengthof(GCCRegAliases);
5486 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5487 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5488 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5490 #include "clang/Basic/BuiltinsHexagon.def"
5493 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5494 class SparcTargetInfo : public TargetInfo {
5495 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5496 static const char * const GCCRegNames[];
5499 SparcTargetInfo(const llvm::Triple &Triple)
5500 : TargetInfo(Triple), SoftFloat(false) {}
5502 bool handleTargetFeatures(std::vector<std::string> &Features,
5503 DiagnosticsEngine &Diags) override {
5504 // The backend doesn't actually handle soft float yet, but in case someone
5505 // is using the support for the front end continue to support it.
5506 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
5507 if (Feature != Features.end()) {
5509 Features.erase(Feature);
5513 void getTargetDefines(const LangOptions &Opts,
5514 MacroBuilder &Builder) const override {
5515 DefineStd(Builder, "sparc", Opts);
5516 Builder.defineMacro("__REGISTER_PREFIX__", "");
5519 Builder.defineMacro("SOFT_FLOAT", "1");
5522 bool hasFeature(StringRef Feature) const override {
5523 return llvm::StringSwitch<bool>(Feature)
5524 .Case("softfloat", SoftFloat)
5525 .Case("sparc", true)
5529 void getTargetBuiltins(const Builtin::Info *&Records,
5530 unsigned &NumRecords) const override {
5531 // FIXME: Implement!
5533 BuiltinVaListKind getBuiltinVaListKind() const override {
5534 return TargetInfo::VoidPtrBuiltinVaList;
5536 void getGCCRegNames(const char * const *&Names,
5537 unsigned &NumNames) const override;
5538 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5539 unsigned &NumAliases) const override;
5540 bool validateAsmConstraint(const char *&Name,
5541 TargetInfo::ConstraintInfo &info) const override {
5542 // FIXME: Implement!
5544 case 'I': // Signed 13-bit constant
5546 case 'K': // 32-bit constant with the low 12 bits clear
5547 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5548 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5549 case 'N': // Same as 'K' but zext (required for SIMode)
5550 case 'O': // The constant 4096
5555 const char *getClobbers() const override {
5556 // FIXME: Implement!
5561 const char * const SparcTargetInfo::GCCRegNames[] = {
5562 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5563 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5564 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5565 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5568 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5569 unsigned &NumNames) const {
5570 Names = GCCRegNames;
5571 NumNames = llvm::array_lengthof(GCCRegNames);
5574 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5585 { { "o2" }, "r10" },
5586 { { "o3" }, "r11" },
5587 { { "o4" }, "r12" },
5588 { { "o5" }, "r13" },
5589 { { "o6", "sp" }, "r14" },
5590 { { "o7" }, "r15" },
5591 { { "l0" }, "r16" },
5592 { { "l1" }, "r17" },
5593 { { "l2" }, "r18" },
5594 { { "l3" }, "r19" },
5595 { { "l4" }, "r20" },
5596 { { "l5" }, "r21" },
5597 { { "l6" }, "r22" },
5598 { { "l7" }, "r23" },
5599 { { "i0" }, "r24" },
5600 { { "i1" }, "r25" },
5601 { { "i2" }, "r26" },
5602 { { "i3" }, "r27" },
5603 { { "i4" }, "r28" },
5604 { { "i5" }, "r29" },
5605 { { "i6", "fp" }, "r30" },
5606 { { "i7" }, "r31" },
5609 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5610 unsigned &NumAliases) const {
5611 Aliases = GCCRegAliases;
5612 NumAliases = llvm::array_lengthof(GCCRegAliases);
5615 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
5616 class SparcV8TargetInfo : public SparcTargetInfo {
5618 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5619 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5620 // NetBSD uses long (same as llvm default); everyone else uses int.
5621 if (getTriple().getOS() == llvm::Triple::NetBSD) {
5622 SizeType = UnsignedLong;
5623 IntPtrType = SignedLong;
5624 PtrDiffType = SignedLong;
5626 SizeType = UnsignedInt;
5627 IntPtrType = SignedInt;
5628 PtrDiffType = SignedInt;
5632 void getTargetDefines(const LangOptions &Opts,
5633 MacroBuilder &Builder) const override {
5634 SparcTargetInfo::getTargetDefines(Opts, Builder);
5635 Builder.defineMacro("__sparcv8");
5639 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
5640 class SparcV8elTargetInfo : public SparcV8TargetInfo {
5642 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) {
5643 DescriptionString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64";
5648 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5649 class SparcV9TargetInfo : public SparcTargetInfo {
5651 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5652 // FIXME: Support Sparc quad-precision long double?
5653 DescriptionString = "E-m:e-i64:64-n32:64-S128";
5654 // This is an LP64 platform.
5655 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5657 // OpenBSD uses long long for int64_t and intmax_t.
5658 if (getTriple().getOS() == llvm::Triple::OpenBSD)
5659 IntMaxType = SignedLongLong;
5661 IntMaxType = SignedLong;
5662 Int64Type = IntMaxType;
5664 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5665 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5666 LongDoubleWidth = 128;
5667 LongDoubleAlign = 128;
5668 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5669 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5672 void getTargetDefines(const LangOptions &Opts,
5673 MacroBuilder &Builder) const override {
5674 SparcTargetInfo::getTargetDefines(Opts, Builder);
5675 Builder.defineMacro("__sparcv9");
5676 Builder.defineMacro("__arch64__");
5677 // Solaris doesn't need these variants, but the BSDs do.
5678 if (getTriple().getOS() != llvm::Triple::Solaris) {
5679 Builder.defineMacro("__sparc64__");
5680 Builder.defineMacro("__sparc_v9__");
5681 Builder.defineMacro("__sparcv9__");
5685 bool setCPU(const std::string &Name) override {
5686 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5688 .Case("ultrasparc", true)
5689 .Case("ultrasparc3", true)
5690 .Case("niagara", true)
5691 .Case("niagara2", true)
5692 .Case("niagara3", true)
5693 .Case("niagara4", true)
5696 // No need to store the CPU yet. There aren't any CPU-specific
5697 // macros to define.
5702 class SystemZTargetInfo : public TargetInfo {
5703 static const Builtin::Info BuiltinInfo[];
5704 static const char *const GCCRegNames[];
5706 bool HasTransactionalExecution;
5710 SystemZTargetInfo(const llvm::Triple &Triple)
5711 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) {
5712 IntMaxType = SignedLong;
5713 Int64Type = SignedLong;
5714 TLSSupported = true;
5715 IntWidth = IntAlign = 32;
5716 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5717 PointerWidth = PointerAlign = 64;
5718 LongDoubleWidth = 128;
5719 LongDoubleAlign = 64;
5720 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5721 DefaultAlignForAttributeAligned = 64;
5722 MinGlobalAlign = 16;
5723 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5724 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5726 void getTargetDefines(const LangOptions &Opts,
5727 MacroBuilder &Builder) const override {
5728 Builder.defineMacro("__s390__");
5729 Builder.defineMacro("__s390x__");
5730 Builder.defineMacro("__zarch__");
5731 Builder.defineMacro("__LONG_DOUBLE_128__");
5732 if (HasTransactionalExecution)
5733 Builder.defineMacro("__HTM__");
5735 Builder.defineMacro("__VEC__", "10301");
5737 void getTargetBuiltins(const Builtin::Info *&Records,
5738 unsigned &NumRecords) const override {
5739 Records = BuiltinInfo;
5740 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin;
5743 void getGCCRegNames(const char *const *&Names,
5744 unsigned &NumNames) const override;
5745 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5746 unsigned &NumAliases) const override {
5751 bool validateAsmConstraint(const char *&Name,
5752 TargetInfo::ConstraintInfo &info) const override;
5753 const char *getClobbers() const override {
5754 // FIXME: Is this really right?
5757 BuiltinVaListKind getBuiltinVaListKind() const override {
5758 return TargetInfo::SystemZBuiltinVaList;
5760 bool setCPU(const std::string &Name) override {
5762 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5765 .Case("zEC12", true)
5771 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5773 Features["transactional-execution"] = true;
5775 Features["transactional-execution"] = true;
5776 Features["vector"] = true;
5780 bool handleTargetFeatures(std::vector<std::string> &Features,
5781 DiagnosticsEngine &Diags) override {
5782 HasTransactionalExecution = false;
5783 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
5784 if (Features[i] == "+transactional-execution")
5785 HasTransactionalExecution = true;
5786 if (Features[i] == "+vector")
5789 // If we use the vector ABI, vector types are 64-bit aligned.
5791 MaxVectorAlign = 64;
5792 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
5793 "-v128:64-a:8:16-n32:64";
5798 bool hasFeature(StringRef Feature) const override {
5799 return llvm::StringSwitch<bool>(Feature)
5800 .Case("systemz", true)
5801 .Case("htm", HasTransactionalExecution)
5802 .Case("vx", HasVector)
5806 StringRef getABI() const override {
5812 bool useFloat128ManglingForLongDouble() const override {
5817 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
5818 #define BUILTIN(ID, TYPE, ATTRS) \
5819 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5820 #include "clang/Basic/BuiltinsSystemZ.def"
5823 const char *const SystemZTargetInfo::GCCRegNames[] = {
5824 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5825 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5826 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
5827 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
5830 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5831 unsigned &NumNames) const {
5832 Names = GCCRegNames;
5833 NumNames = llvm::array_lengthof(GCCRegNames);
5836 bool SystemZTargetInfo::
5837 validateAsmConstraint(const char *&Name,
5838 TargetInfo::ConstraintInfo &Info) const {
5843 case 'a': // Address register
5844 case 'd': // Data register (equivalent to 'r')
5845 case 'f': // Floating-point register
5846 Info.setAllowsRegister();
5849 case 'I': // Unsigned 8-bit constant
5850 case 'J': // Unsigned 12-bit constant
5851 case 'K': // Signed 16-bit constant
5852 case 'L': // Signed 20-bit displacement (on all targets we support)
5853 case 'M': // 0x7fffffff
5856 case 'Q': // Memory with base and unsigned 12-bit displacement
5857 case 'R': // Likewise, plus an index
5858 case 'S': // Memory with base and signed 20-bit displacement
5859 case 'T': // Likewise, plus an index
5860 Info.setAllowsMemory();
5865 class MSP430TargetInfo : public TargetInfo {
5866 static const char * const GCCRegNames[];
5868 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5870 TLSSupported = false;
5871 IntWidth = 16; IntAlign = 16;
5872 LongWidth = 32; LongLongWidth = 64;
5873 LongAlign = LongLongAlign = 16;
5874 PointerWidth = 16; PointerAlign = 16;
5876 SizeType = UnsignedInt;
5877 IntMaxType = SignedLongLong;
5878 IntPtrType = SignedInt;
5879 PtrDiffType = SignedInt;
5880 SigAtomicType = SignedLong;
5881 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5883 void getTargetDefines(const LangOptions &Opts,
5884 MacroBuilder &Builder) const override {
5885 Builder.defineMacro("MSP430");
5886 Builder.defineMacro("__MSP430__");
5887 // FIXME: defines for different 'flavours' of MCU
5889 void getTargetBuiltins(const Builtin::Info *&Records,
5890 unsigned &NumRecords) const override {
5891 // FIXME: Implement.
5895 bool hasFeature(StringRef Feature) const override {
5896 return Feature == "msp430";
5898 void getGCCRegNames(const char * const *&Names,
5899 unsigned &NumNames) const override;
5900 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5901 unsigned &NumAliases) const override {
5907 validateAsmConstraint(const char *&Name,
5908 TargetInfo::ConstraintInfo &info) const override {
5911 case 'K': // the constant 1
5912 case 'L': // constant -1^20 .. 1^19
5913 case 'M': // constant 1-4:
5916 // No target constraints for now.
5919 const char *getClobbers() const override {
5920 // FIXME: Is this really right?
5923 BuiltinVaListKind getBuiltinVaListKind() const override {
5925 return TargetInfo::CharPtrBuiltinVaList;
5929 const char * const MSP430TargetInfo::GCCRegNames[] = {
5930 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5931 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5934 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5935 unsigned &NumNames) const {
5936 Names = GCCRegNames;
5937 NumNames = llvm::array_lengthof(GCCRegNames);
5940 // LLVM and Clang cannot be used directly to output native binaries for
5941 // target, but is used to compile C code to llvm bitcode with correct
5942 // type and alignment information.
5944 // TCE uses the llvm bitcode as input and uses it for generating customized
5945 // target processor and program binary. TCE co-design environment is
5946 // publicly available in http://tce.cs.tut.fi
5948 static const unsigned TCEOpenCLAddrSpaceMap[] = {
5951 5, // opencl_constant
5952 // FIXME: generic has to be added to the target
5953 0, // opencl_generic
5959 class TCETargetInfo : public TargetInfo{
5961 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5962 TLSSupported = false;
5964 LongWidth = LongLongWidth = 32;
5967 LongAlign = LongLongAlign = 32;
5970 SizeType = UnsignedInt;
5971 IntMaxType = SignedLong;
5972 IntPtrType = SignedInt;
5973 PtrDiffType = SignedInt;
5978 LongDoubleWidth = 32;
5979 LongDoubleAlign = 32;
5980 FloatFormat = &llvm::APFloat::IEEEsingle;
5981 DoubleFormat = &llvm::APFloat::IEEEsingle;
5982 LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5983 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5984 "-f64:32-v64:32-v128:32-a:0:32-n32";
5985 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5986 UseAddrSpaceMapMangling = true;
5989 void getTargetDefines(const LangOptions &Opts,
5990 MacroBuilder &Builder) const override {
5991 DefineStd(Builder, "tce", Opts);
5992 Builder.defineMacro("__TCE__");
5993 Builder.defineMacro("__TCE_V1__");
5995 bool hasFeature(StringRef Feature) const override {
5996 return Feature == "tce";
5999 void getTargetBuiltins(const Builtin::Info *&Records,
6000 unsigned &NumRecords) const override {}
6001 const char *getClobbers() const override {
6004 BuiltinVaListKind getBuiltinVaListKind() const override {
6005 return TargetInfo::VoidPtrBuiltinVaList;
6007 void getGCCRegNames(const char * const *&Names,
6008 unsigned &NumNames) const override {}
6009 bool validateAsmConstraint(const char *&Name,
6010 TargetInfo::ConstraintInfo &info) const override{
6013 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6014 unsigned &NumAliases) const override {}
6017 class BPFTargetInfo : public TargetInfo {
6019 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6020 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6021 SizeType = UnsignedLong;
6022 PtrDiffType = SignedLong;
6023 IntPtrType = SignedLong;
6024 IntMaxType = SignedLong;
6025 Int64Type = SignedLong;
6027 if (Triple.getArch() == llvm::Triple::bpfeb) {
6029 DescriptionString = "E-m:e-p:64:64-i64:64-n32:64-S128";
6032 DescriptionString = "e-m:e-p:64:64-i64:64-n32:64-S128";
6034 MaxAtomicPromoteWidth = 64;
6035 MaxAtomicInlineWidth = 64;
6036 TLSSupported = false;
6038 void getTargetDefines(const LangOptions &Opts,
6039 MacroBuilder &Builder) const override {
6040 DefineStd(Builder, "bpf", Opts);
6041 Builder.defineMacro("__BPF__");
6043 bool hasFeature(StringRef Feature) const override {
6044 return Feature == "bpf";
6047 void getTargetBuiltins(const Builtin::Info *&Records,
6048 unsigned &NumRecords) const override {}
6049 const char *getClobbers() const override {
6052 BuiltinVaListKind getBuiltinVaListKind() const override {
6053 return TargetInfo::VoidPtrBuiltinVaList;
6055 void getGCCRegNames(const char * const *&Names,
6056 unsigned &NumNames) const override {
6060 bool validateAsmConstraint(const char *&Name,
6061 TargetInfo::ConstraintInfo &info) const override {
6064 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6065 unsigned &NumAliases) const override {
6071 class MipsTargetInfoBase : public TargetInfo {
6072 virtual void setDescriptionString() = 0;
6074 static const Builtin::Info BuiltinInfo[];
6081 HardFloat, SoftFloat
6093 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
6094 const std::string &CPUStr)
6095 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
6096 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
6097 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
6098 TheCXXABI.set(TargetCXXABI::GenericMIPS);
6101 bool isNaN2008Default() const {
6102 return CPU == "mips32r6" || CPU == "mips64r6";
6105 bool isFP64Default() const {
6106 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
6109 bool isNan2008() const override {
6113 StringRef getABI() const override { return ABI; }
6114 bool setCPU(const std::string &Name) override {
6115 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
6116 getTriple().getArch() == llvm::Triple::mipsel;
6118 return llvm::StringSwitch<bool>(Name)
6119 .Case("mips1", IsMips32)
6120 .Case("mips2", IsMips32)
6121 .Case("mips3", true)
6122 .Case("mips4", true)
6123 .Case("mips5", true)
6124 .Case("mips32", IsMips32)
6125 .Case("mips32r2", IsMips32)
6126 .Case("mips32r3", IsMips32)
6127 .Case("mips32r5", IsMips32)
6128 .Case("mips32r6", IsMips32)
6129 .Case("mips64", true)
6130 .Case("mips64r2", true)
6131 .Case("mips64r3", true)
6132 .Case("mips64r5", true)
6133 .Case("mips64r6", true)
6134 .Case("octeon", true)
6137 const std::string& getCPU() const { return CPU; }
6138 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6139 if (CPU == "octeon")
6140 Features["mips64r2"] = Features["cnmips"] = true;
6142 Features[CPU] = true;
6145 void getTargetDefines(const LangOptions &Opts,
6146 MacroBuilder &Builder) const override {
6147 Builder.defineMacro("__mips__");
6148 Builder.defineMacro("_mips");
6150 Builder.defineMacro("mips");
6152 Builder.defineMacro("__REGISTER_PREFIX__", "");
6156 Builder.defineMacro("__mips_hard_float", Twine(1));
6159 Builder.defineMacro("__mips_soft_float", Twine(1));
6164 Builder.defineMacro("__mips_single_float", Twine(1));
6166 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
6167 Builder.defineMacro("_MIPS_FPSET",
6168 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
6171 Builder.defineMacro("__mips16", Twine(1));
6174 Builder.defineMacro("__mips_micromips", Twine(1));
6177 Builder.defineMacro("__mips_nan2008", Twine(1));
6183 Builder.defineMacro("__mips_dsp_rev", Twine(1));
6184 Builder.defineMacro("__mips_dsp", Twine(1));
6187 Builder.defineMacro("__mips_dsp_rev", Twine(2));
6188 Builder.defineMacro("__mips_dspr2", Twine(1));
6189 Builder.defineMacro("__mips_dsp", Twine(1));
6194 Builder.defineMacro("__mips_msa", Twine(1));
6196 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
6197 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
6198 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
6200 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
6201 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
6204 void getTargetBuiltins(const Builtin::Info *&Records,
6205 unsigned &NumRecords) const override {
6206 Records = BuiltinInfo;
6207 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
6209 bool hasFeature(StringRef Feature) const override {
6210 return llvm::StringSwitch<bool>(Feature)
6212 .Case("fp64", HasFP64)
6215 BuiltinVaListKind getBuiltinVaListKind() const override {
6216 return TargetInfo::VoidPtrBuiltinVaList;
6218 void getGCCRegNames(const char * const *&Names,
6219 unsigned &NumNames) const override {
6220 static const char *const GCCRegNames[] = {
6221 // CPU register names
6222 // Must match second column of GCCRegAliases
6223 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
6224 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
6225 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
6226 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
6227 // Floating point register names
6228 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
6229 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
6230 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
6231 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
6232 // Hi/lo and condition register names
6233 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
6234 "$fcc5","$fcc6","$fcc7",
6235 // MSA register names
6236 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
6237 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
6238 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
6239 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
6240 // MSA control register names
6241 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
6242 "$msarequest", "$msamap", "$msaunmap"
6244 Names = GCCRegNames;
6245 NumNames = llvm::array_lengthof(GCCRegNames);
6247 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6248 unsigned &NumAliases) const override = 0;
6249 bool validateAsmConstraint(const char *&Name,
6250 TargetInfo::ConstraintInfo &Info) const override {
6254 case 'r': // CPU registers.
6255 case 'd': // Equivalent to "r" unless generating MIPS16 code.
6256 case 'y': // Equivalent to "r", backward compatibility only.
6257 case 'f': // floating-point registers.
6258 case 'c': // $25 for indirect jumps
6259 case 'l': // lo register
6260 case 'x': // hilo register pair
6261 Info.setAllowsRegister();
6263 case 'I': // Signed 16-bit constant
6264 case 'J': // Integer 0
6265 case 'K': // Unsigned 16-bit constant
6266 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
6267 case 'M': // Constants not loadable via lui, addiu, or ori
6268 case 'N': // Constant -1 to -65535
6269 case 'O': // A signed 15-bit constant
6270 case 'P': // A constant between 1 go 65535
6272 case 'R': // An address that can be used in a non-macro load or store
6273 Info.setAllowsMemory();
6276 if (Name[1] == 'C') { // An address usable by ll, and sc.
6277 Info.setAllowsMemory();
6278 Name++; // Skip over 'Z'.
6285 std::string convertConstraint(const char *&Constraint) const override {
6287 switch (*Constraint) {
6288 case 'Z': // Two-character constraint; add "^" hint for later parsing.
6289 if (Constraint[1] == 'C') {
6290 R = std::string("^") + std::string(Constraint, 2);
6296 return TargetInfo::convertConstraint(Constraint);
6299 const char *getClobbers() const override {
6300 // In GCC, $1 is not widely used in generated code (it's used only in a few
6301 // specific situations), so there is no real need for users to add it to
6302 // the clobbers list if they want to use it in their inline assembly code.
6304 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
6305 // code generation, so using it in inline assembly without adding it to the
6306 // clobbers list can cause conflicts between the inline assembly code and
6307 // the surrounding generated code.
6309 // Another problem is that LLVM is allowed to choose $1 for inline assembly
6310 // operands, which will conflict with the ".set at" assembler option (which
6311 // we use only for inline assembly, in order to maintain compatibility with
6312 // GCC) and will also conflict with the user's usage of $1.
6314 // The easiest way to avoid these conflicts and keep $1 as an allocatable
6315 // register for generated code is to automatically clobber $1 for all inline
6318 // FIXME: We should automatically clobber $1 only for inline assembly code
6319 // which actually uses it. This would allow LLVM to use $1 for inline
6320 // assembly operands if the user's assembly code doesn't use it.
6324 bool handleTargetFeatures(std::vector<std::string> &Features,
6325 DiagnosticsEngine &Diags) override {
6327 IsMicromips = false;
6328 IsNan2008 = isNaN2008Default();
6329 IsSingleFloat = false;
6330 FloatABI = HardFloat;
6332 HasFP64 = isFP64Default();
6334 for (std::vector<std::string>::iterator it = Features.begin(),
6335 ie = Features.end(); it != ie; ++it) {
6336 if (*it == "+single-float")
6337 IsSingleFloat = true;
6338 else if (*it == "+soft-float")
6339 FloatABI = SoftFloat;
6340 else if (*it == "+mips16")
6342 else if (*it == "+micromips")
6344 else if (*it == "+dsp")
6345 DspRev = std::max(DspRev, DSP1);
6346 else if (*it == "+dspr2")
6347 DspRev = std::max(DspRev, DSP2);
6348 else if (*it == "+msa")
6350 else if (*it == "+fp64")
6352 else if (*it == "-fp64")
6354 else if (*it == "+nan2008")
6356 else if (*it == "-nan2008")
6360 setDescriptionString();
6365 int getEHDataRegisterNumber(unsigned RegNo) const override {
6366 if (RegNo == 0) return 4;
6367 if (RegNo == 1) return 5;
6371 bool isCLZForZeroUndef() const override { return false; }
6374 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
6375 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6376 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6378 #include "clang/Basic/BuiltinsMips.def"
6381 class Mips32TargetInfoBase : public MipsTargetInfoBase {
6383 Mips32TargetInfoBase(const llvm::Triple &Triple)
6384 : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
6385 SizeType = UnsignedInt;
6386 PtrDiffType = SignedInt;
6387 Int64Type = SignedLongLong;
6388 IntMaxType = Int64Type;
6389 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
6391 bool setABI(const std::string &Name) override {
6392 if (Name == "o32" || Name == "eabi") {
6398 void getTargetDefines(const LangOptions &Opts,
6399 MacroBuilder &Builder) const override {
6400 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6402 Builder.defineMacro("__mips", "32");
6403 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
6405 const std::string& CPUStr = getCPU();
6406 if (CPUStr == "mips32")
6407 Builder.defineMacro("__mips_isa_rev", "1");
6408 else if (CPUStr == "mips32r2")
6409 Builder.defineMacro("__mips_isa_rev", "2");
6410 else if (CPUStr == "mips32r3")
6411 Builder.defineMacro("__mips_isa_rev", "3");
6412 else if (CPUStr == "mips32r5")
6413 Builder.defineMacro("__mips_isa_rev", "5");
6414 else if (CPUStr == "mips32r6")
6415 Builder.defineMacro("__mips_isa_rev", "6");
6418 Builder.defineMacro("__mips_o32");
6419 Builder.defineMacro("_ABIO32", "1");
6420 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
6422 else if (ABI == "eabi")
6423 Builder.defineMacro("__mips_eabi");
6425 llvm_unreachable("Invalid ABI for Mips32.");
6427 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6428 unsigned &NumAliases) const override {
6429 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6439 { { "t2" }, "$10" },
6440 { { "t3" }, "$11" },
6441 { { "t4" }, "$12" },
6442 { { "t5" }, "$13" },
6443 { { "t6" }, "$14" },
6444 { { "t7" }, "$15" },
6445 { { "s0" }, "$16" },
6446 { { "s1" }, "$17" },
6447 { { "s2" }, "$18" },
6448 { { "s3" }, "$19" },
6449 { { "s4" }, "$20" },
6450 { { "s5" }, "$21" },
6451 { { "s6" }, "$22" },
6452 { { "s7" }, "$23" },
6453 { { "t8" }, "$24" },
6454 { { "t9" }, "$25" },
6455 { { "k0" }, "$26" },
6456 { { "k1" }, "$27" },
6457 { { "gp" }, "$28" },
6458 { { "sp","$sp" }, "$29" },
6459 { { "fp","$fp" }, "$30" },
6462 Aliases = GCCRegAliases;
6463 NumAliases = llvm::array_lengthof(GCCRegAliases);
6467 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
6468 void setDescriptionString() override {
6469 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6473 Mips32EBTargetInfo(const llvm::Triple &Triple)
6474 : Mips32TargetInfoBase(Triple) {
6476 void getTargetDefines(const LangOptions &Opts,
6477 MacroBuilder &Builder) const override {
6478 DefineStd(Builder, "MIPSEB", Opts);
6479 Builder.defineMacro("_MIPSEB");
6480 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6484 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
6485 void setDescriptionString() override {
6486 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6490 Mips32ELTargetInfo(const llvm::Triple &Triple)
6491 : Mips32TargetInfoBase(Triple) {
6494 void getTargetDefines(const LangOptions &Opts,
6495 MacroBuilder &Builder) const override {
6496 DefineStd(Builder, "MIPSEL", Opts);
6497 Builder.defineMacro("_MIPSEL");
6498 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6502 class Mips64TargetInfoBase : public MipsTargetInfoBase {
6504 Mips64TargetInfoBase(const llvm::Triple &Triple)
6505 : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6506 LongDoubleWidth = LongDoubleAlign = 128;
6507 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6508 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6509 LongDoubleWidth = LongDoubleAlign = 64;
6510 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6513 SuitableAlign = 128;
6514 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6517 void setN64ABITypes() {
6518 LongWidth = LongAlign = 64;
6519 PointerWidth = PointerAlign = 64;
6520 SizeType = UnsignedLong;
6521 PtrDiffType = SignedLong;
6522 Int64Type = SignedLong;
6523 IntMaxType = Int64Type;
6526 void setN32ABITypes() {
6527 LongWidth = LongAlign = 32;
6528 PointerWidth = PointerAlign = 32;
6529 SizeType = UnsignedInt;
6530 PtrDiffType = SignedInt;
6531 Int64Type = SignedLongLong;
6532 IntMaxType = Int64Type;
6535 bool setABI(const std::string &Name) override {
6536 if (Name == "n32") {
6541 if (Name == "n64") {
6549 void getTargetDefines(const LangOptions &Opts,
6550 MacroBuilder &Builder) const override {
6551 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6553 Builder.defineMacro("__mips", "64");
6554 Builder.defineMacro("__mips64");
6555 Builder.defineMacro("__mips64__");
6556 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6558 const std::string& CPUStr = getCPU();
6559 if (CPUStr == "mips64")
6560 Builder.defineMacro("__mips_isa_rev", "1");
6561 else if (CPUStr == "mips64r2")
6562 Builder.defineMacro("__mips_isa_rev", "2");
6563 else if (CPUStr == "mips64r3")
6564 Builder.defineMacro("__mips_isa_rev", "3");
6565 else if (CPUStr == "mips64r5")
6566 Builder.defineMacro("__mips_isa_rev", "5");
6567 else if (CPUStr == "mips64r6")
6568 Builder.defineMacro("__mips_isa_rev", "6");
6571 Builder.defineMacro("__mips_n32");
6572 Builder.defineMacro("_ABIN32", "2");
6573 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6575 else if (ABI == "n64") {
6576 Builder.defineMacro("__mips_n64");
6577 Builder.defineMacro("_ABI64", "3");
6578 Builder.defineMacro("_MIPS_SIM", "_ABI64");
6581 llvm_unreachable("Invalid ABI for Mips64.");
6583 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6584 unsigned &NumAliases) const override {
6585 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6595 { { "a6" }, "$10" },
6596 { { "a7" }, "$11" },
6597 { { "t0" }, "$12" },
6598 { { "t1" }, "$13" },
6599 { { "t2" }, "$14" },
6600 { { "t3" }, "$15" },
6601 { { "s0" }, "$16" },
6602 { { "s1" }, "$17" },
6603 { { "s2" }, "$18" },
6604 { { "s3" }, "$19" },
6605 { { "s4" }, "$20" },
6606 { { "s5" }, "$21" },
6607 { { "s6" }, "$22" },
6608 { { "s7" }, "$23" },
6609 { { "t8" }, "$24" },
6610 { { "t9" }, "$25" },
6611 { { "k0" }, "$26" },
6612 { { "k1" }, "$27" },
6613 { { "gp" }, "$28" },
6614 { { "sp","$sp" }, "$29" },
6615 { { "fp","$fp" }, "$30" },
6618 Aliases = GCCRegAliases;
6619 NumAliases = llvm::array_lengthof(GCCRegAliases);
6622 bool hasInt128Type() const override { return true; }
6625 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
6626 void setDescriptionString() override {
6628 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6630 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6635 Mips64EBTargetInfo(const llvm::Triple &Triple)
6636 : Mips64TargetInfoBase(Triple) {}
6637 void getTargetDefines(const LangOptions &Opts,
6638 MacroBuilder &Builder) const override {
6639 DefineStd(Builder, "MIPSEB", Opts);
6640 Builder.defineMacro("_MIPSEB");
6641 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6645 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
6646 void setDescriptionString() override {
6648 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6650 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6653 Mips64ELTargetInfo(const llvm::Triple &Triple)
6654 : Mips64TargetInfoBase(Triple) {
6655 // Default ABI is n64.
6658 void getTargetDefines(const LangOptions &Opts,
6659 MacroBuilder &Builder) const override {
6660 DefineStd(Builder, "MIPSEL", Opts);
6661 Builder.defineMacro("_MIPSEL");
6662 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6666 class PNaClTargetInfo : public TargetInfo {
6668 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6670 this->UserLabelPrefix = "";
6671 this->LongAlign = 32;
6672 this->LongWidth = 32;
6673 this->PointerAlign = 32;
6674 this->PointerWidth = 32;
6675 this->IntMaxType = TargetInfo::SignedLongLong;
6676 this->Int64Type = TargetInfo::SignedLongLong;
6677 this->DoubleAlign = 64;
6678 this->LongDoubleWidth = 64;
6679 this->LongDoubleAlign = 64;
6680 this->SizeType = TargetInfo::UnsignedInt;
6681 this->PtrDiffType = TargetInfo::SignedInt;
6682 this->IntPtrType = TargetInfo::SignedInt;
6683 this->RegParmMax = 0; // Disallow regparm
6686 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6688 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6689 Builder.defineMacro("__le32__");
6690 Builder.defineMacro("__pnacl__");
6692 void getTargetDefines(const LangOptions &Opts,
6693 MacroBuilder &Builder) const override {
6694 getArchDefines(Opts, Builder);
6696 bool hasFeature(StringRef Feature) const override {
6697 return Feature == "pnacl";
6699 void getTargetBuiltins(const Builtin::Info *&Records,
6700 unsigned &NumRecords) const override {
6702 BuiltinVaListKind getBuiltinVaListKind() const override {
6703 return TargetInfo::PNaClABIBuiltinVaList;
6705 void getGCCRegNames(const char * const *&Names,
6706 unsigned &NumNames) const override;
6707 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6708 unsigned &NumAliases) const override;
6709 bool validateAsmConstraint(const char *&Name,
6710 TargetInfo::ConstraintInfo &Info) const override {
6714 const char *getClobbers() const override {
6719 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6720 unsigned &NumNames) const {
6725 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6726 unsigned &NumAliases) const {
6731 // We attempt to use PNaCl (le32) frontend and Mips32EL backend.
6732 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo {
6734 NaClMips32ELTargetInfo(const llvm::Triple &Triple) :
6735 Mips32ELTargetInfo(Triple) {
6736 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 0;
6739 BuiltinVaListKind getBuiltinVaListKind() const override {
6740 return TargetInfo::PNaClABIBuiltinVaList;
6744 class Le64TargetInfo : public TargetInfo {
6745 static const Builtin::Info BuiltinInfo[];
6748 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6750 NoAsmVariants = true;
6751 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6752 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6754 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
6757 void getTargetDefines(const LangOptions &Opts,
6758 MacroBuilder &Builder) const override {
6759 DefineStd(Builder, "unix", Opts);
6760 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6761 Builder.defineMacro("__ELF__");
6763 void getTargetBuiltins(const Builtin::Info *&Records,
6764 unsigned &NumRecords) const override {
6765 Records = BuiltinInfo;
6766 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
6768 BuiltinVaListKind getBuiltinVaListKind() const override {
6769 return TargetInfo::PNaClABIBuiltinVaList;
6771 const char *getClobbers() const override { return ""; }
6772 void getGCCRegNames(const char *const *&Names,
6773 unsigned &NumNames) const override {
6777 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6778 unsigned &NumAliases) const override {
6782 bool validateAsmConstraint(const char *&Name,
6783 TargetInfo::ConstraintInfo &Info) const override {
6787 bool hasProtectedVisibility() const override { return false; }
6789 } // end anonymous namespace.
6791 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
6792 #define BUILTIN(ID, TYPE, ATTRS) \
6793 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6794 #include "clang/Basic/BuiltinsLe64.def"
6798 static const unsigned SPIRAddrSpaceMap[] = {
6801 2, // opencl_constant
6802 4, // opencl_generic
6807 class SPIRTargetInfo : public TargetInfo {
6809 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6810 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6811 "SPIR target must use unknown OS");
6812 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6813 "SPIR target must use unknown environment type");
6815 TLSSupported = false;
6816 LongWidth = LongAlign = 64;
6817 AddrSpaceMap = &SPIRAddrSpaceMap;
6818 UseAddrSpaceMapMangling = true;
6819 // Define available target features
6820 // These must be defined in sorted order!
6821 NoAsmVariants = true;
6823 void getTargetDefines(const LangOptions &Opts,
6824 MacroBuilder &Builder) const override {
6825 DefineStd(Builder, "SPIR", Opts);
6827 bool hasFeature(StringRef Feature) const override {
6828 return Feature == "spir";
6831 void getTargetBuiltins(const Builtin::Info *&Records,
6832 unsigned &NumRecords) const override {}
6833 const char *getClobbers() const override {
6836 void getGCCRegNames(const char * const *&Names,
6837 unsigned &NumNames) const override {}
6839 validateAsmConstraint(const char *&Name,
6840 TargetInfo::ConstraintInfo &info) const override {
6843 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6844 unsigned &NumAliases) const override {}
6845 BuiltinVaListKind getBuiltinVaListKind() const override {
6846 return TargetInfo::VoidPtrBuiltinVaList;
6849 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6850 return (CC == CC_SpirFunction ||
6851 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning;
6854 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
6855 return CC_SpirFunction;
6860 class SPIR32TargetInfo : public SPIRTargetInfo {
6862 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6863 PointerWidth = PointerAlign = 32;
6864 SizeType = TargetInfo::UnsignedInt;
6865 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6867 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6868 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6870 void getTargetDefines(const LangOptions &Opts,
6871 MacroBuilder &Builder) const override {
6872 DefineStd(Builder, "SPIR32", Opts);
6876 class SPIR64TargetInfo : public SPIRTargetInfo {
6878 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6879 PointerWidth = PointerAlign = 64;
6880 SizeType = TargetInfo::UnsignedLong;
6881 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6882 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6883 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6885 void getTargetDefines(const LangOptions &Opts,
6886 MacroBuilder &Builder) const override {
6887 DefineStd(Builder, "SPIR64", Opts);
6891 class XCoreTargetInfo : public TargetInfo {
6892 static const Builtin::Info BuiltinInfo[];
6894 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6896 NoAsmVariants = true;
6899 DoubleAlign = LongDoubleAlign = 32;
6900 SizeType = UnsignedInt;
6901 PtrDiffType = SignedInt;
6902 IntPtrType = SignedInt;
6903 WCharType = UnsignedChar;
6904 WIntType = UnsignedInt;
6905 UseZeroLengthBitfieldAlignment = true;
6906 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6907 "-f64:32-a:0:32-n32";
6909 void getTargetDefines(const LangOptions &Opts,
6910 MacroBuilder &Builder) const override {
6911 Builder.defineMacro("__XS1B__");
6913 void getTargetBuiltins(const Builtin::Info *&Records,
6914 unsigned &NumRecords) const override {
6915 Records = BuiltinInfo;
6916 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
6918 BuiltinVaListKind getBuiltinVaListKind() const override {
6919 return TargetInfo::VoidPtrBuiltinVaList;
6921 const char *getClobbers() const override {
6924 void getGCCRegNames(const char * const *&Names,
6925 unsigned &NumNames) const override {
6926 static const char * const GCCRegNames[] = {
6927 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6928 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
6930 Names = GCCRegNames;
6931 NumNames = llvm::array_lengthof(GCCRegNames);
6933 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6934 unsigned &NumAliases) const override {
6938 bool validateAsmConstraint(const char *&Name,
6939 TargetInfo::ConstraintInfo &Info) const override {
6942 int getEHDataRegisterNumber(unsigned RegNo) const override {
6943 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6944 return (RegNo < 2)? RegNo : -1;
6948 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6949 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6950 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6952 #include "clang/Basic/BuiltinsXCore.def"
6954 } // end anonymous namespace.
6957 // x86_32 Android target
6958 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
6960 AndroidX86_32TargetInfo(const llvm::Triple &Triple)
6961 : LinuxTargetInfo<X86_32TargetInfo>(Triple) {
6963 LongDoubleWidth = 64;
6964 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6967 } // end anonymous namespace
6970 // x86_64 Android target
6971 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
6973 AndroidX86_64TargetInfo(const llvm::Triple &Triple)
6974 : LinuxTargetInfo<X86_64TargetInfo>(Triple) {
6975 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6978 bool useFloat128ManglingForLongDouble() const override {
6982 } // end anonymous namespace
6985 //===----------------------------------------------------------------------===//
6987 //===----------------------------------------------------------------------===//
6989 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6990 llvm::Triple::OSType os = Triple.getOS();
6992 switch (Triple.getArch()) {
6996 case llvm::Triple::xcore:
6997 return new XCoreTargetInfo(Triple);
6999 case llvm::Triple::hexagon:
7000 return new HexagonTargetInfo(Triple);
7002 case llvm::Triple::aarch64:
7003 if (Triple.isOSDarwin())
7004 return new DarwinAArch64TargetInfo(Triple);
7007 case llvm::Triple::FreeBSD:
7008 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
7009 case llvm::Triple::Linux:
7010 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
7011 case llvm::Triple::NetBSD:
7012 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
7014 return new AArch64leTargetInfo(Triple);
7017 case llvm::Triple::aarch64_be:
7019 case llvm::Triple::FreeBSD:
7020 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
7021 case llvm::Triple::Linux:
7022 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
7023 case llvm::Triple::NetBSD:
7024 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
7026 return new AArch64beTargetInfo(Triple);
7029 case llvm::Triple::arm:
7030 case llvm::Triple::thumb:
7031 if (Triple.isOSBinFormatMachO())
7032 return new DarwinARMTargetInfo(Triple);
7035 case llvm::Triple::Linux:
7036 return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
7037 case llvm::Triple::FreeBSD:
7038 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
7039 case llvm::Triple::NetBSD:
7040 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
7041 case llvm::Triple::OpenBSD:
7042 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
7043 case llvm::Triple::Bitrig:
7044 return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
7045 case llvm::Triple::RTEMS:
7046 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
7047 case llvm::Triple::NaCl:
7048 return new NaClTargetInfo<ARMleTargetInfo>(Triple);
7049 case llvm::Triple::Win32:
7050 switch (Triple.getEnvironment()) {
7051 case llvm::Triple::Itanium:
7052 return new ItaniumWindowsARMleTargetInfo(Triple);
7053 case llvm::Triple::MSVC:
7054 default: // Assume MSVC for unknown environments
7055 return new MicrosoftARMleTargetInfo(Triple);
7058 return new ARMleTargetInfo(Triple);
7061 case llvm::Triple::armeb:
7062 case llvm::Triple::thumbeb:
7063 if (Triple.isOSDarwin())
7064 return new DarwinARMTargetInfo(Triple);
7067 case llvm::Triple::Linux:
7068 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
7069 case llvm::Triple::FreeBSD:
7070 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
7071 case llvm::Triple::NetBSD:
7072 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
7073 case llvm::Triple::OpenBSD:
7074 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
7075 case llvm::Triple::Bitrig:
7076 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
7077 case llvm::Triple::RTEMS:
7078 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
7079 case llvm::Triple::NaCl:
7080 return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
7082 return new ARMbeTargetInfo(Triple);
7085 case llvm::Triple::bpfeb:
7086 case llvm::Triple::bpfel:
7087 return new BPFTargetInfo(Triple);
7089 case llvm::Triple::msp430:
7090 return new MSP430TargetInfo(Triple);
7092 case llvm::Triple::mips:
7094 case llvm::Triple::Linux:
7095 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
7096 case llvm::Triple::RTEMS:
7097 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
7098 case llvm::Triple::FreeBSD:
7099 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
7100 case llvm::Triple::NetBSD:
7101 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
7103 return new Mips32EBTargetInfo(Triple);
7106 case llvm::Triple::mipsel:
7108 case llvm::Triple::Linux:
7109 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
7110 case llvm::Triple::RTEMS:
7111 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
7112 case llvm::Triple::FreeBSD:
7113 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
7114 case llvm::Triple::NetBSD:
7115 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
7116 case llvm::Triple::NaCl:
7117 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple);
7119 return new Mips32ELTargetInfo(Triple);
7122 case llvm::Triple::mips64:
7124 case llvm::Triple::Linux:
7125 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
7126 case llvm::Triple::RTEMS:
7127 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
7128 case llvm::Triple::FreeBSD:
7129 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7130 case llvm::Triple::NetBSD:
7131 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7132 case llvm::Triple::OpenBSD:
7133 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7135 return new Mips64EBTargetInfo(Triple);
7138 case llvm::Triple::mips64el:
7140 case llvm::Triple::Linux:
7141 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
7142 case llvm::Triple::RTEMS:
7143 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
7144 case llvm::Triple::FreeBSD:
7145 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7146 case llvm::Triple::NetBSD:
7147 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7148 case llvm::Triple::OpenBSD:
7149 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7151 return new Mips64ELTargetInfo(Triple);
7154 case llvm::Triple::le32:
7156 case llvm::Triple::NaCl:
7157 return new NaClTargetInfo<PNaClTargetInfo>(Triple);
7162 case llvm::Triple::le64:
7163 return new Le64TargetInfo(Triple);
7165 case llvm::Triple::ppc:
7166 if (Triple.isOSDarwin())
7167 return new DarwinPPC32TargetInfo(Triple);
7169 case llvm::Triple::Linux:
7170 return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
7171 case llvm::Triple::FreeBSD:
7172 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
7173 case llvm::Triple::NetBSD:
7174 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
7175 case llvm::Triple::OpenBSD:
7176 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
7177 case llvm::Triple::RTEMS:
7178 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
7180 return new PPC32TargetInfo(Triple);
7183 case llvm::Triple::ppc64:
7184 if (Triple.isOSDarwin())
7185 return new DarwinPPC64TargetInfo(Triple);
7187 case llvm::Triple::Linux:
7188 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7189 case llvm::Triple::Lv2:
7190 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
7191 case llvm::Triple::FreeBSD:
7192 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
7193 case llvm::Triple::NetBSD:
7194 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7196 return new PPC64TargetInfo(Triple);
7199 case llvm::Triple::ppc64le:
7201 case llvm::Triple::Linux:
7202 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7203 case llvm::Triple::NetBSD:
7204 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7206 return new PPC64TargetInfo(Triple);
7209 case llvm::Triple::nvptx:
7210 return new NVPTX32TargetInfo(Triple);
7211 case llvm::Triple::nvptx64:
7212 return new NVPTX64TargetInfo(Triple);
7214 case llvm::Triple::amdgcn:
7215 case llvm::Triple::r600:
7216 return new AMDGPUTargetInfo(Triple);
7218 case llvm::Triple::sparc:
7220 case llvm::Triple::Linux:
7221 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
7222 case llvm::Triple::Solaris:
7223 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple);
7224 case llvm::Triple::NetBSD:
7225 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
7226 case llvm::Triple::OpenBSD:
7227 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
7228 case llvm::Triple::RTEMS:
7229 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
7231 return new SparcV8TargetInfo(Triple);
7234 // The 'sparcel' architecture copies all the above cases except for Solaris.
7235 case llvm::Triple::sparcel:
7237 case llvm::Triple::Linux:
7238 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple);
7239 case llvm::Triple::NetBSD:
7240 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7241 case llvm::Triple::OpenBSD:
7242 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7243 case llvm::Triple::RTEMS:
7244 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple);
7246 return new SparcV8elTargetInfo(Triple);
7249 case llvm::Triple::sparcv9:
7251 case llvm::Triple::Linux:
7252 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
7253 case llvm::Triple::Solaris:
7254 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
7255 case llvm::Triple::NetBSD:
7256 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
7257 case llvm::Triple::OpenBSD:
7258 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
7259 case llvm::Triple::FreeBSD:
7260 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
7262 return new SparcV9TargetInfo(Triple);
7265 case llvm::Triple::systemz:
7267 case llvm::Triple::Linux:
7268 return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
7270 return new SystemZTargetInfo(Triple);
7273 case llvm::Triple::tce:
7274 return new TCETargetInfo(Triple);
7276 case llvm::Triple::x86:
7277 if (Triple.isOSDarwin())
7278 return new DarwinI386TargetInfo(Triple);
7281 case llvm::Triple::CloudABI:
7282 return new CloudABITargetInfo<X86_32TargetInfo>(Triple);
7283 case llvm::Triple::Linux: {
7284 switch (Triple.getEnvironment()) {
7286 return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
7287 case llvm::Triple::Android:
7288 return new AndroidX86_32TargetInfo(Triple);
7291 case llvm::Triple::DragonFly:
7292 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
7293 case llvm::Triple::NetBSD:
7294 return new NetBSDI386TargetInfo(Triple);
7295 case llvm::Triple::OpenBSD:
7296 return new OpenBSDI386TargetInfo(Triple);
7297 case llvm::Triple::Bitrig:
7298 return new BitrigI386TargetInfo(Triple);
7299 case llvm::Triple::FreeBSD:
7300 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7301 case llvm::Triple::KFreeBSD:
7302 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7303 case llvm::Triple::Minix:
7304 return new MinixTargetInfo<X86_32TargetInfo>(Triple);
7305 case llvm::Triple::Solaris:
7306 return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
7307 case llvm::Triple::Win32: {
7308 switch (Triple.getEnvironment()) {
7309 case llvm::Triple::Cygnus:
7310 return new CygwinX86_32TargetInfo(Triple);
7311 case llvm::Triple::GNU:
7312 return new MinGWX86_32TargetInfo(Triple);
7313 case llvm::Triple::Itanium:
7314 case llvm::Triple::MSVC:
7315 default: // Assume MSVC for unknown environments
7316 return new MicrosoftX86_32TargetInfo(Triple);
7319 case llvm::Triple::Haiku:
7320 return new HaikuX86_32TargetInfo(Triple);
7321 case llvm::Triple::RTEMS:
7322 return new RTEMSX86_32TargetInfo(Triple);
7323 case llvm::Triple::NaCl:
7324 return new NaClTargetInfo<X86_32TargetInfo>(Triple);
7326 return new X86_32TargetInfo(Triple);
7329 case llvm::Triple::x86_64:
7330 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
7331 return new DarwinX86_64TargetInfo(Triple);
7334 case llvm::Triple::CloudABI:
7335 return new CloudABITargetInfo<X86_64TargetInfo>(Triple);
7336 case llvm::Triple::Linux: {
7337 switch (Triple.getEnvironment()) {
7339 return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
7340 case llvm::Triple::Android:
7341 return new AndroidX86_64TargetInfo(Triple);
7344 case llvm::Triple::DragonFly:
7345 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
7346 case llvm::Triple::NetBSD:
7347 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
7348 case llvm::Triple::OpenBSD:
7349 return new OpenBSDX86_64TargetInfo(Triple);
7350 case llvm::Triple::Bitrig:
7351 return new BitrigX86_64TargetInfo(Triple);
7352 case llvm::Triple::FreeBSD:
7353 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7354 case llvm::Triple::KFreeBSD:
7355 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7356 case llvm::Triple::Solaris:
7357 return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
7358 case llvm::Triple::Win32: {
7359 switch (Triple.getEnvironment()) {
7360 case llvm::Triple::GNU:
7361 return new MinGWX86_64TargetInfo(Triple);
7362 case llvm::Triple::MSVC:
7363 default: // Assume MSVC for unknown environments
7364 return new MicrosoftX86_64TargetInfo(Triple);
7367 case llvm::Triple::NaCl:
7368 return new NaClTargetInfo<X86_64TargetInfo>(Triple);
7369 case llvm::Triple::PS4:
7370 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple);
7372 return new X86_64TargetInfo(Triple);
7375 case llvm::Triple::spir: {
7376 if (Triple.getOS() != llvm::Triple::UnknownOS ||
7377 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7379 return new SPIR32TargetInfo(Triple);
7381 case llvm::Triple::spir64: {
7382 if (Triple.getOS() != llvm::Triple::UnknownOS ||
7383 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7385 return new SPIR64TargetInfo(Triple);
7390 /// CreateTargetInfo - Return the target info object for the specified target
7393 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
7394 const std::shared_ptr<TargetOptions> &Opts) {
7395 llvm::Triple Triple(Opts->Triple);
7397 // Construct the target
7398 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
7400 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
7403 Target->TargetOpts = Opts;
7405 // Set the target CPU if specified.
7406 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
7407 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
7411 // Set the target ABI if specified.
7412 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
7413 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
7417 // Set the fp math unit.
7418 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
7419 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
7423 // Compute the default target features, we need the target to handle this
7424 // because features may have dependencies on one another.
7425 llvm::StringMap<bool> Features;
7426 Target->getDefaultFeatures(Features);
7428 // Apply the user specified deltas.
7429 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
7431 const char *Name = Opts->FeaturesAsWritten[I].c_str();
7432 // Apply the feature via the target.
7433 bool Enabled = Name[0] == '+';
7434 Target->setFeatureEnabled(Features, Name + 1, Enabled);
7437 // Add the features to the compile options.
7439 // FIXME: If we are completely confident that we have the right set, we only
7440 // need to pass the minuses.
7441 Opts->Features.clear();
7442 for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
7443 ie = Features.end(); it != ie; ++it)
7444 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
7445 if (!Target->handleTargetFeatures(Opts->Features, Diags))
7448 return Target.release();