1 //===--- Targets.cpp - Implement target feature support -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/Builtins.h"
16 #include "clang/Basic/Cuda.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetInfo.h"
22 #include "clang/Basic/TargetOptions.h"
23 #include "clang/Basic/Version.h"
24 #include "clang/Frontend/CodeGenOptions.h"
25 #include "llvm/ADT/APFloat.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/StringSwitch.h"
30 #include "llvm/ADT/Triple.h"
31 #include "llvm/MC/MCSectionMachO.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/TargetParser.h"
37 using namespace clang;
39 //===----------------------------------------------------------------------===//
40 // Common code shared among targets.
41 //===----------------------------------------------------------------------===//
43 /// DefineStd - Define a macro name and standard variants. For example if
44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
47 const LangOptions &Opts) {
48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
51 // in the user's namespace.
53 Builder.defineMacro(MacroName);
56 Builder.defineMacro("__" + MacroName);
59 Builder.defineMacro("__" + MacroName + "__");
62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
64 Builder.defineMacro("__" + CPUName);
65 Builder.defineMacro("__" + CPUName + "__");
67 Builder.defineMacro("__tune_" + CPUName + "__");
70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
71 const TargetOptions &Opts);
73 //===----------------------------------------------------------------------===//
74 // Defines specific to certain operating systems.
75 //===----------------------------------------------------------------------===//
78 template<typename TgtInfo>
79 class OSTargetInfo : public TgtInfo {
81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
82 MacroBuilder &Builder) const=0;
84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
85 : TgtInfo(Triple, Opts) {}
86 void getTargetDefines(const LangOptions &Opts,
87 MacroBuilder &Builder) const override {
88 TgtInfo::getTargetDefines(Opts, Builder);
89 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
95 template <typename Target>
96 class CloudABITargetInfo : public OSTargetInfo<Target> {
98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
99 MacroBuilder &Builder) const override {
100 Builder.defineMacro("__CloudABI__");
101 Builder.defineMacro("__ELF__");
103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
104 Builder.defineMacro("__STDC_ISO_10646__", "201206L");
105 Builder.defineMacro("__STDC_UTF_16__");
106 Builder.defineMacro("__STDC_UTF_32__");
110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
111 : OSTargetInfo<Target>(Triple, Opts) {}
114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
115 const llvm::Triple &Triple,
116 StringRef &PlatformName,
117 VersionTuple &PlatformMinVersion) {
118 Builder.defineMacro("__APPLE_CC__", "6000");
119 Builder.defineMacro("__APPLE__");
120 Builder.defineMacro("OBJC_NEW_PROPERTIES");
121 // AddressSanitizer doesn't play well with source fortification, which is on
122 // by default on Darwin.
123 if (Opts.Sanitize.has(SanitizerKind::Address))
124 Builder.defineMacro("_FORTIFY_SOURCE", "0");
126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode.
128 // __weak is always defined, for use in blocks and with objc pointers.
129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
130 Builder.defineMacro("__strong", "");
131 Builder.defineMacro("__unsafe_unretained", "");
135 Builder.defineMacro("__STATIC__");
137 Builder.defineMacro("__DYNAMIC__");
139 if (Opts.POSIXThreads)
140 Builder.defineMacro("_REENTRANT");
142 // Get the platform type and version number from the triple.
143 unsigned Maj, Min, Rev;
144 if (Triple.isMacOSX()) {
145 Triple.getMacOSXVersion(Maj, Min, Rev);
146 PlatformName = "macos";
148 Triple.getOSVersion(Maj, Min, Rev);
149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
152 // If -target arch-pc-win32-macho option specified, we're
153 // generating code for Win32 ABI. No need to emit
154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
155 if (PlatformName == "win32") {
156 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
160 // Set the appropriate OS version define.
161 if (Triple.isiOS()) {
162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
166 Str[1] = '0' + (Min / 10);
167 Str[2] = '0' + (Min % 10);
168 Str[3] = '0' + (Rev / 10);
169 Str[4] = '0' + (Rev % 10);
172 // Handle versions >= 10.
173 Str[0] = '0' + (Maj / 10);
174 Str[1] = '0' + (Maj % 10);
175 Str[2] = '0' + (Min / 10);
176 Str[3] = '0' + (Min % 10);
177 Str[4] = '0' + (Rev / 10);
178 Str[5] = '0' + (Rev % 10);
182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str);
184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
187 } else if (Triple.isWatchOS()) {
188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
191 Str[1] = '0' + (Min / 10);
192 Str[2] = '0' + (Min % 10);
193 Str[3] = '0' + (Rev / 10);
194 Str[4] = '0' + (Rev % 10);
196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str);
197 } else if (Triple.isMacOSX()) {
198 // Note that the Driver allows versions which aren't representable in the
199 // define (because we only get a single digit for the minor and micro
200 // revision numbers). So, we limit them to the maximum representable
202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
204 if (Maj < 10 || (Maj == 10 && Min < 10)) {
205 Str[0] = '0' + (Maj / 10);
206 Str[1] = '0' + (Maj % 10);
207 Str[2] = '0' + std::min(Min, 9U);
208 Str[3] = '0' + std::min(Rev, 9U);
211 // Handle versions > 10.9.
212 Str[0] = '0' + (Maj / 10);
213 Str[1] = '0' + (Maj % 10);
214 Str[2] = '0' + (Min / 10);
215 Str[3] = '0' + (Min % 10);
216 Str[4] = '0' + (Rev / 10);
217 Str[5] = '0' + (Rev % 10);
220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
223 // Tell users about the kernel if there is one.
224 if (Triple.isOSDarwin())
225 Builder.defineMacro("__MACH__");
227 // The Watch ABI uses Dwarf EH.
228 if(Triple.isWatchABI())
229 Builder.defineMacro("__ARM_DWARF_EH__");
231 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
234 template<typename Target>
235 class DarwinTargetInfo : public OSTargetInfo<Target> {
237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
238 MacroBuilder &Builder) const override {
239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
240 this->PlatformMinVersion);
244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
245 : OSTargetInfo<Target>(Triple, Opts) {
246 // By default, no TLS, and we whitelist permitted architecture/OS
248 this->TLSSupported = false;
250 if (Triple.isMacOSX())
251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7);
252 else if (Triple.isiOS()) {
253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards.
254 if (Triple.getArch() == llvm::Triple::x86_64 ||
255 Triple.getArch() == llvm::Triple::aarch64)
256 this->TLSSupported = !Triple.isOSVersionLT(8);
257 else if (Triple.getArch() == llvm::Triple::x86 ||
258 Triple.getArch() == llvm::Triple::arm ||
259 Triple.getArch() == llvm::Triple::thumb)
260 this->TLSSupported = !Triple.isOSVersionLT(9);
261 } else if (Triple.isWatchOS())
262 this->TLSSupported = !Triple.isOSVersionLT(2);
264 this->MCountName = "\01mcount";
267 std::string isValidSectionSpecifier(StringRef SR) const override {
268 // Let MCSectionMachO validate this.
269 StringRef Segment, Section;
270 unsigned TAA, StubSize;
272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
273 TAA, HasTAA, StubSize);
276 const char *getStaticInitSectionSpecifier() const override {
277 // FIXME: We should return 0 when building kexts.
278 return "__TEXT,__StaticInit,regular,pure_instructions";
281 /// Darwin does not support protected visibility. Darwin's "default"
282 /// is very similar to ELF's "protected"; Darwin requires a "weak"
283 /// attribute on declarations that can be dynamically replaced.
284 bool hasProtectedVisibility() const override {
288 unsigned getExnObjectAlignment() const override {
289 // The alignment of an exception object is 8-bytes for darwin since
290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned))
291 // and therefore doesn't guarantee 16-byte alignment.
297 // DragonFlyBSD Target
298 template<typename Target>
299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
302 MacroBuilder &Builder) const override {
303 // DragonFly defines; list based off of gcc output
304 Builder.defineMacro("__DragonFly__");
305 Builder.defineMacro("__DragonFly_cc_version", "100001");
306 Builder.defineMacro("__ELF__");
307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
308 Builder.defineMacro("__tune_i386__");
309 DefineStd(Builder, "unix", Opts);
312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
313 : OSTargetInfo<Target>(Triple, Opts) {
314 switch (Triple.getArch()) {
316 case llvm::Triple::x86:
317 case llvm::Triple::x86_64:
318 this->MCountName = ".mcount";
324 #ifndef FREEBSD_CC_VERSION
325 #define FREEBSD_CC_VERSION 0U
329 template<typename Target>
330 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
333 MacroBuilder &Builder) const override {
334 // FreeBSD defines; list based off of gcc output
336 unsigned Release = Triple.getOSMajorVersion();
339 unsigned CCVersion = FREEBSD_CC_VERSION;
341 CCVersion = Release * 100000U + 1U;
343 Builder.defineMacro("__FreeBSD__", Twine(Release));
344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion));
345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
346 DefineStd(Builder, "unix", Opts);
347 Builder.defineMacro("__ELF__");
349 // On FreeBSD, wchar_t contains the number of the code point as
350 // used by the character set of the locale. These character sets are
351 // not necessarily a superset of ASCII.
353 // FIXME: This is wrong; the macro refers to the numerical values
354 // of wchar_t *literals*, which are not locale-dependent. However,
355 // FreeBSD systems apparently depend on us getting this wrong, and
356 // setting this to 1 is conforming even if all the basic source
357 // character literals have the same encoding as char and wchar_t.
358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
362 : OSTargetInfo<Target>(Triple, Opts) {
363 switch (Triple.getArch()) {
365 case llvm::Triple::x86:
366 case llvm::Triple::x86_64:
367 this->MCountName = ".mcount";
369 case llvm::Triple::mips:
370 case llvm::Triple::mipsel:
371 case llvm::Triple::ppc:
372 case llvm::Triple::ppc64:
373 case llvm::Triple::ppc64le:
374 this->MCountName = "_mcount";
376 case llvm::Triple::arm:
377 this->MCountName = "__mcount";
383 // GNU/kFreeBSD Target
384 template<typename Target>
385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
388 MacroBuilder &Builder) const override {
389 // GNU/kFreeBSD defines; list based off of gcc output
391 DefineStd(Builder, "unix", Opts);
392 Builder.defineMacro("__FreeBSD_kernel__");
393 Builder.defineMacro("__GLIBC__");
394 Builder.defineMacro("__ELF__");
395 if (Opts.POSIXThreads)
396 Builder.defineMacro("_REENTRANT");
398 Builder.defineMacro("_GNU_SOURCE");
401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
402 : OSTargetInfo<Target>(Triple, Opts) {}
406 template<typename Target>
407 class HaikuTargetInfo : public OSTargetInfo<Target> {
409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
410 MacroBuilder &Builder) const override {
411 // Haiku defines; list based off of gcc output
412 Builder.defineMacro("__HAIKU__");
413 Builder.defineMacro("__ELF__");
414 DefineStd(Builder, "unix", Opts);
417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
418 : OSTargetInfo<Target>(Triple, Opts) {
419 this->SizeType = TargetInfo::UnsignedLong;
420 this->IntPtrType = TargetInfo::SignedLong;
421 this->PtrDiffType = TargetInfo::SignedLong;
422 this->ProcessIDType = TargetInfo::SignedLong;
423 this->TLSSupported = false;
429 template<typename Target>
430 class MinixTargetInfo : public OSTargetInfo<Target> {
432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
433 MacroBuilder &Builder) const override {
436 Builder.defineMacro("__minix", "3");
437 Builder.defineMacro("_EM_WSIZE", "4");
438 Builder.defineMacro("_EM_PSIZE", "4");
439 Builder.defineMacro("_EM_SSIZE", "2");
440 Builder.defineMacro("_EM_LSIZE", "4");
441 Builder.defineMacro("_EM_FSIZE", "4");
442 Builder.defineMacro("_EM_DSIZE", "8");
443 Builder.defineMacro("__ELF__");
444 DefineStd(Builder, "unix", Opts);
447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
448 : OSTargetInfo<Target>(Triple, Opts) {}
452 template<typename Target>
453 class LinuxTargetInfo : public OSTargetInfo<Target> {
455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
456 MacroBuilder &Builder) const override {
457 // Linux defines; list based off of gcc output
458 DefineStd(Builder, "unix", Opts);
459 DefineStd(Builder, "linux", Opts);
460 Builder.defineMacro("__gnu_linux__");
461 Builder.defineMacro("__ELF__");
462 if (Triple.isAndroid()) {
463 Builder.defineMacro("__ANDROID__", "1");
464 unsigned Maj, Min, Rev;
465 Triple.getEnvironmentVersion(Maj, Min, Rev);
466 this->PlatformName = "android";
467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
469 Builder.defineMacro("__ANDROID_API__", Twine(Maj));
471 if (Opts.POSIXThreads)
472 Builder.defineMacro("_REENTRANT");
474 Builder.defineMacro("_GNU_SOURCE");
475 if (this->HasFloat128)
476 Builder.defineMacro("__FLOAT128__");
479 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
480 : OSTargetInfo<Target>(Triple, Opts) {
481 this->WIntType = TargetInfo::UnsignedInt;
483 switch (Triple.getArch()) {
486 case llvm::Triple::ppc:
487 case llvm::Triple::ppc64:
488 case llvm::Triple::ppc64le:
489 this->MCountName = "_mcount";
491 case llvm::Triple::x86:
492 case llvm::Triple::x86_64:
493 case llvm::Triple::systemz:
494 this->HasFloat128 = true;
499 const char *getStaticInitSectionSpecifier() const override {
500 return ".text.startup";
505 template<typename Target>
506 class NetBSDTargetInfo : public OSTargetInfo<Target> {
508 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
509 MacroBuilder &Builder) const override {
510 // NetBSD defines; list based off of gcc output
511 Builder.defineMacro("__NetBSD__");
512 Builder.defineMacro("__unix__");
513 Builder.defineMacro("__ELF__");
514 if (Opts.POSIXThreads)
515 Builder.defineMacro("_POSIX_THREADS");
517 switch (Triple.getArch()) {
520 case llvm::Triple::arm:
521 case llvm::Triple::armeb:
522 case llvm::Triple::thumb:
523 case llvm::Triple::thumbeb:
524 Builder.defineMacro("__ARM_DWARF_EH__");
529 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
530 : OSTargetInfo<Target>(Triple, Opts) {
531 this->MCountName = "_mcount";
536 template<typename Target>
537 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
539 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
540 MacroBuilder &Builder) const override {
541 // OpenBSD defines; list based off of gcc output
543 Builder.defineMacro("__OpenBSD__");
544 DefineStd(Builder, "unix", Opts);
545 Builder.defineMacro("__ELF__");
546 if (Opts.POSIXThreads)
547 Builder.defineMacro("_REENTRANT");
550 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
551 : OSTargetInfo<Target>(Triple, Opts) {
552 this->TLSSupported = false;
554 switch (Triple.getArch()) {
556 case llvm::Triple::x86:
557 case llvm::Triple::x86_64:
558 case llvm::Triple::arm:
559 case llvm::Triple::sparc:
560 this->MCountName = "__mcount";
562 case llvm::Triple::mips64:
563 case llvm::Triple::mips64el:
564 case llvm::Triple::ppc:
565 case llvm::Triple::sparcv9:
566 this->MCountName = "_mcount";
573 template<typename Target>
574 class BitrigTargetInfo : public OSTargetInfo<Target> {
576 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
577 MacroBuilder &Builder) const override {
578 // Bitrig defines; list based off of gcc output
580 Builder.defineMacro("__Bitrig__");
581 DefineStd(Builder, "unix", Opts);
582 Builder.defineMacro("__ELF__");
583 if (Opts.POSIXThreads)
584 Builder.defineMacro("_REENTRANT");
586 switch (Triple.getArch()) {
589 case llvm::Triple::arm:
590 case llvm::Triple::armeb:
591 case llvm::Triple::thumb:
592 case llvm::Triple::thumbeb:
593 Builder.defineMacro("__ARM_DWARF_EH__");
598 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
599 : OSTargetInfo<Target>(Triple, Opts) {
600 this->MCountName = "__mcount";
605 template<typename Target>
606 class PSPTargetInfo : public OSTargetInfo<Target> {
608 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
609 MacroBuilder &Builder) const override {
610 // PSP defines; list based on the output of the pspdev gcc toolchain.
611 Builder.defineMacro("PSP");
612 Builder.defineMacro("_PSP");
613 Builder.defineMacro("__psp__");
614 Builder.defineMacro("__ELF__");
617 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {}
621 template<typename Target>
622 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
624 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
625 MacroBuilder &Builder) const override {
627 Builder.defineMacro("__PPC__");
628 Builder.defineMacro("__PPU__");
629 Builder.defineMacro("__CELLOS_LV2__");
630 Builder.defineMacro("__ELF__");
631 Builder.defineMacro("__LP32__");
632 Builder.defineMacro("_ARCH_PPC64");
633 Builder.defineMacro("__powerpc64__");
636 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
637 : OSTargetInfo<Target>(Triple, Opts) {
638 this->LongWidth = this->LongAlign = 32;
639 this->PointerWidth = this->PointerAlign = 32;
640 this->IntMaxType = TargetInfo::SignedLongLong;
641 this->Int64Type = TargetInfo::SignedLongLong;
642 this->SizeType = TargetInfo::UnsignedInt;
643 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64");
647 template <typename Target>
648 class PS4OSTargetInfo : public OSTargetInfo<Target> {
650 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
651 MacroBuilder &Builder) const override {
652 Builder.defineMacro("__FreeBSD__", "9");
653 Builder.defineMacro("__FreeBSD_cc_version", "900001");
654 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
655 DefineStd(Builder, "unix", Opts);
656 Builder.defineMacro("__ELF__");
657 Builder.defineMacro("__ORBIS__");
660 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
661 : OSTargetInfo<Target>(Triple, Opts) {
662 this->WCharType = this->UnsignedShort;
664 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits).
665 this->MaxTLSAlign = 256;
667 // On PS4, do not honor explicit bit field alignment,
668 // as in "__attribute__((aligned(2))) int b : 1;".
669 this->UseExplicitBitFieldAlignment = false;
671 switch (Triple.getArch()) {
673 case llvm::Triple::x86_64:
674 this->MCountName = ".mcount";
681 template<typename Target>
682 class SolarisTargetInfo : public OSTargetInfo<Target> {
684 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
685 MacroBuilder &Builder) const override {
686 DefineStd(Builder, "sun", Opts);
687 DefineStd(Builder, "unix", Opts);
688 Builder.defineMacro("__ELF__");
689 Builder.defineMacro("__svr4__");
690 Builder.defineMacro("__SVR4");
691 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
692 // newer, but to 500 for everything else. feature_test.h has a check to
693 // ensure that you are not using C99 with an old version of X/Open or C89
694 // with a new version.
696 Builder.defineMacro("_XOPEN_SOURCE", "600");
698 Builder.defineMacro("_XOPEN_SOURCE", "500");
700 Builder.defineMacro("__C99FEATURES__");
701 Builder.defineMacro("_LARGEFILE_SOURCE");
702 Builder.defineMacro("_LARGEFILE64_SOURCE");
703 Builder.defineMacro("__EXTENSIONS__");
704 Builder.defineMacro("_REENTRANT");
707 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
708 : OSTargetInfo<Target>(Triple, Opts) {
709 this->WCharType = this->SignedInt;
710 // FIXME: WIntType should be SignedLong
715 template<typename Target>
716 class WindowsTargetInfo : public OSTargetInfo<Target> {
718 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
719 MacroBuilder &Builder) const override {
720 Builder.defineMacro("_WIN32");
722 void getVisualStudioDefines(const LangOptions &Opts,
723 MacroBuilder &Builder) const {
724 if (Opts.CPlusPlus) {
726 Builder.defineMacro("_CPPRTTI");
728 if (Opts.CXXExceptions)
729 Builder.defineMacro("_CPPUNWIND");
733 Builder.defineMacro("__BOOL_DEFINED");
735 if (!Opts.CharIsSigned)
736 Builder.defineMacro("_CHAR_UNSIGNED");
738 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
739 // but it works for now.
740 if (Opts.POSIXThreads)
741 Builder.defineMacro("_MT");
743 if (Opts.MSCompatibilityVersion) {
744 Builder.defineMacro("_MSC_VER",
745 Twine(Opts.MSCompatibilityVersion / 100000));
746 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
747 // FIXME We cannot encode the revision information into 32-bits
748 Builder.defineMacro("_MSC_BUILD", Twine(1));
750 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
751 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
753 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) {
754 if (Opts.CPlusPlus1z)
755 Builder.defineMacro("_MSVC_LANG", "201403L");
756 else if (Opts.CPlusPlus14)
757 Builder.defineMacro("_MSVC_LANG", "201402L");
761 if (Opts.MicrosoftExt) {
762 Builder.defineMacro("_MSC_EXTENSIONS");
764 if (Opts.CPlusPlus11) {
765 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
766 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
767 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
771 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
775 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
776 : OSTargetInfo<Target>(Triple, Opts) {}
779 template <typename Target>
780 class NaClTargetInfo : public OSTargetInfo<Target> {
782 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
783 MacroBuilder &Builder) const override {
784 if (Opts.POSIXThreads)
785 Builder.defineMacro("_REENTRANT");
787 Builder.defineMacro("_GNU_SOURCE");
789 DefineStd(Builder, "unix", Opts);
790 Builder.defineMacro("__ELF__");
791 Builder.defineMacro("__native_client__");
795 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
796 : OSTargetInfo<Target>(Triple, Opts) {
797 this->LongAlign = 32;
798 this->LongWidth = 32;
799 this->PointerAlign = 32;
800 this->PointerWidth = 32;
801 this->IntMaxType = TargetInfo::SignedLongLong;
802 this->Int64Type = TargetInfo::SignedLongLong;
803 this->DoubleAlign = 64;
804 this->LongDoubleWidth = 64;
805 this->LongDoubleAlign = 64;
806 this->LongLongWidth = 64;
807 this->LongLongAlign = 64;
808 this->SizeType = TargetInfo::UnsignedInt;
809 this->PtrDiffType = TargetInfo::SignedInt;
810 this->IntPtrType = TargetInfo::SignedInt;
811 // RegParmMax is inherited from the underlying architecture.
812 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble();
813 if (Triple.getArch() == llvm::Triple::arm) {
814 // Handled in ARM's setABI().
815 } else if (Triple.getArch() == llvm::Triple::x86) {
816 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128");
817 } else if (Triple.getArch() == llvm::Triple::x86_64) {
818 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128");
819 } else if (Triple.getArch() == llvm::Triple::mipsel) {
820 // Handled on mips' setDataLayout.
822 assert(Triple.getArch() == llvm::Triple::le32);
823 this->resetDataLayout("e-p:32:32-i64:64");
829 template<typename Target>
830 class FuchsiaTargetInfo : public OSTargetInfo<Target> {
832 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
833 MacroBuilder &Builder) const override {
834 Builder.defineMacro("__Fuchsia__");
835 Builder.defineMacro("__ELF__");
836 if (Opts.POSIXThreads)
837 Builder.defineMacro("_REENTRANT");
838 // Required by the libc++ locale support.
840 Builder.defineMacro("_GNU_SOURCE");
843 FuchsiaTargetInfo(const llvm::Triple &Triple,
844 const TargetOptions &Opts)
845 : OSTargetInfo<Target>(Triple, Opts) {
846 this->MCountName = "__mcount";
850 // WebAssembly target
851 template <typename Target>
852 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> {
853 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
854 MacroBuilder &Builder) const final {
855 // A common platform macro.
856 if (Opts.POSIXThreads)
857 Builder.defineMacro("_REENTRANT");
858 // Follow g++ convention and predefine _GNU_SOURCE for C++.
860 Builder.defineMacro("_GNU_SOURCE");
863 // As an optimization, group static init code together in a section.
864 const char *getStaticInitSectionSpecifier() const final {
865 return ".text.__startup";
869 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple,
870 const TargetOptions &Opts)
871 : OSTargetInfo<Target>(Triple, Opts) {
872 this->MCountName = "__mcount";
873 this->TheCXXABI.set(TargetCXXABI::WebAssembly);
877 //===----------------------------------------------------------------------===//
878 // Specific target implementations.
879 //===----------------------------------------------------------------------===//
881 // PPC abstract base class
882 class PPCTargetInfo : public TargetInfo {
883 static const Builtin::Info BuiltinInfo[];
884 static const char * const GCCRegNames[];
885 static const TargetInfo::GCCRegAlias GCCRegAliases[];
888 // Target cpu features.
903 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
904 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
905 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
906 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) {
907 SimdDefaultAlign = 128;
908 LongDoubleWidth = LongDoubleAlign = 128;
909 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
912 /// \brief Flags for architecture specific defines.
915 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
916 ArchDefinePpcgr = 1 << 1,
917 ArchDefinePpcsq = 1 << 2,
918 ArchDefine440 = 1 << 3,
919 ArchDefine603 = 1 << 4,
920 ArchDefine604 = 1 << 5,
921 ArchDefinePwr4 = 1 << 6,
922 ArchDefinePwr5 = 1 << 7,
923 ArchDefinePwr5x = 1 << 8,
924 ArchDefinePwr6 = 1 << 9,
925 ArchDefinePwr6x = 1 << 10,
926 ArchDefinePwr7 = 1 << 11,
927 ArchDefinePwr8 = 1 << 12,
928 ArchDefinePwr9 = 1 << 13,
929 ArchDefineA2 = 1 << 14,
930 ArchDefineA2q = 1 << 15
933 // Note: GCC recognizes the following additional cpus:
934 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
935 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
937 bool setCPU(const std::string &Name) override {
938 bool CPUKnown = llvm::StringSwitch<bool>(Name)
939 .Case("generic", true)
961 .Case("e500mc", true)
963 .Case("power3", true)
965 .Case("power4", true)
967 .Case("power5", true)
969 .Case("power5x", true)
971 .Case("power6", true)
973 .Case("power6x", true)
975 .Case("power7", true)
977 .Case("power8", true)
979 .Case("power9", true)
981 .Case("powerpc", true)
983 .Case("powerpc64", true)
985 .Case("powerpc64le", true)
986 .Case("ppc64le", true)
996 StringRef getABI() const override { return ABI; }
998 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
999 return llvm::makeArrayRef(BuiltinInfo,
1000 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin);
1003 bool isCLZForZeroUndef() const override { return false; }
1005 void getTargetDefines(const LangOptions &Opts,
1006 MacroBuilder &Builder) const override;
1009 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
1011 const std::vector<std::string> &FeaturesVec) const override;
1013 bool handleTargetFeatures(std::vector<std::string> &Features,
1014 DiagnosticsEngine &Diags) override;
1015 bool hasFeature(StringRef Feature) const override;
1016 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
1017 bool Enabled) const override;
1019 ArrayRef<const char *> getGCCRegNames() const override;
1020 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
1021 bool validateAsmConstraint(const char *&Name,
1022 TargetInfo::ConstraintInfo &Info) const override {
1024 default: return false;
1027 case 'b': // Base register
1028 case 'f': // Floating point register
1029 Info.setAllowsRegister();
1031 // FIXME: The following are added to allow parsing.
1032 // I just took a guess at what the actions should be.
1033 // Also, is more specific checking needed? I.e. specific registers?
1034 case 'd': // Floating point register (containing 64-bit value)
1035 case 'v': // Altivec vector register
1036 Info.setAllowsRegister();
1040 case 'd':// VSX vector register to hold vector double data
1041 case 'f':// VSX vector register to hold vector float data
1042 case 's':// VSX vector register to hold scalar float data
1043 case 'a':// Any VSX register
1044 case 'c':// An individual CR bit
1049 Info.setAllowsRegister();
1050 Name++; // Skip over 'w'.
1052 case 'h': // `MQ', `CTR', or `LINK' register
1053 case 'q': // `MQ' register
1054 case 'c': // `CTR' register
1055 case 'l': // `LINK' register
1056 case 'x': // `CR' register (condition register) number 0
1057 case 'y': // `CR' register (condition register)
1058 case 'z': // `XER[CA]' carry bit (part of the XER register)
1059 Info.setAllowsRegister();
1061 case 'I': // Signed 16-bit constant
1062 case 'J': // Unsigned 16-bit constant shifted left 16 bits
1063 // (use `L' instead for SImode constants)
1064 case 'K': // Unsigned 16-bit constant
1065 case 'L': // Signed 16-bit constant shifted left 16 bits
1066 case 'M': // Constant larger than 31
1067 case 'N': // Exact power of 2
1068 case 'P': // Constant whose negation is a signed 16-bit constant
1069 case 'G': // Floating point constant that can be loaded into a
1070 // register with one instruction per word
1071 case 'H': // Integer/Floating point constant that can be loaded
1072 // into a register using three instructions
1074 case 'm': // Memory operand. Note that on PowerPC targets, m can
1075 // include addresses that update the base register. It
1076 // is therefore only safe to use `m' in an asm statement
1077 // if that asm statement accesses the operand exactly once.
1078 // The asm statement must also use `%U<opno>' as a
1079 // placeholder for the "update" flag in the corresponding
1080 // load or store instruction. For example:
1081 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
1083 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
1084 // is not. Use es rather than m if you don't want the base
1085 // register to be updated.
1089 // es: A "stable" memory operand; that is, one which does not
1090 // include any automodification of the base register. Unlike
1091 // `m', this constraint can be used in asm statements that
1092 // might access the operand several times, or that might not
1093 // access it at all.
1094 Info.setAllowsMemory();
1095 Name++; // Skip over 'e'.
1097 case 'Q': // Memory operand that is an offset from a register (it is
1098 // usually better to use `m' or `es' in asm statements)
1099 case 'Z': // Memory operand that is an indexed or indirect from a
1100 // register (it is usually better to use `m' or `es' in
1102 Info.setAllowsMemory();
1103 Info.setAllowsRegister();
1105 case 'R': // AIX TOC entry
1106 case 'a': // Address operand that is an indexed or indirect from a
1107 // register (`p' is preferable for asm statements)
1108 case 'S': // Constant suitable as a 64-bit mask operand
1109 case 'T': // Constant suitable as a 32-bit mask operand
1110 case 'U': // System V Release 4 small data area reference
1111 case 't': // AND masks that can be performed by two rldic{l, r}
1113 case 'W': // Vector constant that does not require memory
1114 case 'j': // Vector constant that is all zeros.
1120 std::string convertConstraint(const char *&Constraint) const override {
1122 switch (*Constraint) {
1125 // Two-character constraint; add "^" hint for later parsing.
1126 R = std::string("^") + std::string(Constraint, 2);
1130 return TargetInfo::convertConstraint(Constraint);
1134 const char *getClobbers() const override {
1137 int getEHDataRegisterNumber(unsigned RegNo) const override {
1138 if (RegNo == 0) return 3;
1139 if (RegNo == 1) return 4;
1143 bool hasSjLjLowering() const override {
1147 bool useFloat128ManglingForLongDouble() const override {
1148 return LongDoubleWidth == 128 &&
1149 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() &&
1150 getTriple().isOSBinFormatELF();
1154 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
1155 #define BUILTIN(ID, TYPE, ATTRS) \
1156 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1157 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1158 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1159 #include "clang/Basic/BuiltinsPPC.def"
1162 /// handleTargetFeatures - Perform initialization based on the user
1163 /// configured set of features.
1164 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1165 DiagnosticsEngine &Diags) {
1166 for (const auto &Feature : Features) {
1167 if (Feature == "+vsx") {
1169 } else if (Feature == "+bpermd") {
1171 } else if (Feature == "+extdiv") {
1173 } else if (Feature == "+power8-vector") {
1175 } else if (Feature == "+crypto") {
1177 } else if (Feature == "+direct-move") {
1178 HasDirectMove = true;
1179 } else if (Feature == "+qpx") {
1181 } else if (Feature == "+htm") {
1183 } else if (Feature == "+float128") {
1185 } else if (Feature == "+power9-vector") {
1188 // TODO: Finish this list and add an assert that we've handled them
1195 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1196 /// #defines that are not tied to a specific subtarget.
1197 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1198 MacroBuilder &Builder) const {
1199 // Target identification.
1200 Builder.defineMacro("__ppc__");
1201 Builder.defineMacro("__PPC__");
1202 Builder.defineMacro("_ARCH_PPC");
1203 Builder.defineMacro("__powerpc__");
1204 Builder.defineMacro("__POWERPC__");
1205 if (PointerWidth == 64) {
1206 Builder.defineMacro("_ARCH_PPC64");
1207 Builder.defineMacro("__powerpc64__");
1208 Builder.defineMacro("__ppc64__");
1209 Builder.defineMacro("__PPC64__");
1212 // Target properties.
1213 if (getTriple().getArch() == llvm::Triple::ppc64le) {
1214 Builder.defineMacro("_LITTLE_ENDIAN");
1216 if (getTriple().getOS() != llvm::Triple::NetBSD &&
1217 getTriple().getOS() != llvm::Triple::OpenBSD)
1218 Builder.defineMacro("_BIG_ENDIAN");
1222 if (ABI == "elfv1" || ABI == "elfv1-qpx")
1223 Builder.defineMacro("_CALL_ELF", "1");
1225 Builder.defineMacro("_CALL_ELF", "2");
1227 // Subtarget options.
1228 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1229 Builder.defineMacro("__REGISTER_PREFIX__", "");
1231 // FIXME: Should be controlled by command line option.
1232 if (LongDoubleWidth == 128)
1233 Builder.defineMacro("__LONG_DOUBLE_128__");
1236 Builder.defineMacro("__VEC__", "10206");
1237 Builder.defineMacro("__ALTIVEC__");
1240 // CPU identification.
1241 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1242 .Case("440", ArchDefineName)
1243 .Case("450", ArchDefineName | ArchDefine440)
1244 .Case("601", ArchDefineName)
1245 .Case("602", ArchDefineName | ArchDefinePpcgr)
1246 .Case("603", ArchDefineName | ArchDefinePpcgr)
1247 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1248 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1249 .Case("604", ArchDefineName | ArchDefinePpcgr)
1250 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1251 .Case("620", ArchDefineName | ArchDefinePpcgr)
1252 .Case("630", ArchDefineName | ArchDefinePpcgr)
1253 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1254 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1255 .Case("750", ArchDefineName | ArchDefinePpcgr)
1256 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1258 .Case("a2", ArchDefineA2)
1259 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1260 .Case("pwr3", ArchDefinePpcgr)
1261 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1262 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1264 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1265 | ArchDefinePpcgr | ArchDefinePpcsq)
1266 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1267 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1268 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1269 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1271 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1272 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1273 | ArchDefinePpcgr | ArchDefinePpcsq)
1274 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1275 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1276 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1277 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7
1278 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1279 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1281 .Case("power3", ArchDefinePpcgr)
1282 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1283 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1285 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1286 | ArchDefinePpcgr | ArchDefinePpcsq)
1287 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1288 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1289 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1290 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1292 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1293 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1294 | ArchDefinePpcgr | ArchDefinePpcsq)
1295 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1296 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1297 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1298 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7
1299 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1300 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1302 .Default(ArchDefineNone);
1304 if (defs & ArchDefineName)
1305 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1306 if (defs & ArchDefinePpcgr)
1307 Builder.defineMacro("_ARCH_PPCGR");
1308 if (defs & ArchDefinePpcsq)
1309 Builder.defineMacro("_ARCH_PPCSQ");
1310 if (defs & ArchDefine440)
1311 Builder.defineMacro("_ARCH_440");
1312 if (defs & ArchDefine603)
1313 Builder.defineMacro("_ARCH_603");
1314 if (defs & ArchDefine604)
1315 Builder.defineMacro("_ARCH_604");
1316 if (defs & ArchDefinePwr4)
1317 Builder.defineMacro("_ARCH_PWR4");
1318 if (defs & ArchDefinePwr5)
1319 Builder.defineMacro("_ARCH_PWR5");
1320 if (defs & ArchDefinePwr5x)
1321 Builder.defineMacro("_ARCH_PWR5X");
1322 if (defs & ArchDefinePwr6)
1323 Builder.defineMacro("_ARCH_PWR6");
1324 if (defs & ArchDefinePwr6x)
1325 Builder.defineMacro("_ARCH_PWR6X");
1326 if (defs & ArchDefinePwr7)
1327 Builder.defineMacro("_ARCH_PWR7");
1328 if (defs & ArchDefinePwr8)
1329 Builder.defineMacro("_ARCH_PWR8");
1330 if (defs & ArchDefinePwr9)
1331 Builder.defineMacro("_ARCH_PWR9");
1332 if (defs & ArchDefineA2)
1333 Builder.defineMacro("_ARCH_A2");
1334 if (defs & ArchDefineA2q) {
1335 Builder.defineMacro("_ARCH_A2Q");
1336 Builder.defineMacro("_ARCH_QP");
1339 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1340 Builder.defineMacro("__bg__");
1341 Builder.defineMacro("__THW_BLUEGENE__");
1342 Builder.defineMacro("__bgq__");
1343 Builder.defineMacro("__TOS_BGQ__");
1347 Builder.defineMacro("__VSX__");
1349 Builder.defineMacro("__POWER8_VECTOR__");
1351 Builder.defineMacro("__CRYPTO__");
1353 Builder.defineMacro("__HTM__");
1355 Builder.defineMacro("__FLOAT128__");
1357 Builder.defineMacro("__POWER9_VECTOR__");
1359 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1360 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1361 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1362 if (PointerWidth == 64)
1363 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1365 // FIXME: The following are not yet generated here by Clang, but are
1366 // generated by GCC:
1369 // __RECIP_PRECISION__
1370 // __APPLE_ALTIVEC__
1379 // __CMODEL_MEDIUM__
1386 // Handle explicit options being passed to the compiler here: if we've
1387 // explicitly turned off vsx and turned on any of:
1392 // then go ahead and error since the customer has expressed an incompatible
1394 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
1395 const std::vector<std::string> &FeaturesVec) {
1397 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") !=
1398 FeaturesVec.end()) {
1399 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") !=
1400 FeaturesVec.end()) {
1401 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
1406 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") !=
1407 FeaturesVec.end()) {
1408 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
1413 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") !=
1414 FeaturesVec.end()) {
1415 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
1420 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") !=
1421 FeaturesVec.end()) {
1422 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector"
1431 bool PPCTargetInfo::initFeatureMap(
1432 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
1433 const std::vector<std::string> &FeaturesVec) const {
1434 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1445 .Case("ppc64", true)
1446 .Case("ppc64le", true)
1449 Features["qpx"] = (CPU == "a2q");
1450 Features["power9-vector"] = (CPU == "pwr9");
1451 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1452 .Case("ppc64le", true)
1456 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1457 .Case("ppc64le", true)
1461 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1462 .Case("ppc64le", true)
1467 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1468 .Case("ppc64le", true)
1473 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1474 .Case("ppc64le", true)
1478 Features["vsx"] = llvm::StringSwitch<bool>(CPU)
1479 .Case("ppc64le", true)
1485 if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
1488 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1491 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1492 return llvm::StringSwitch<bool>(Feature)
1493 .Case("powerpc", true)
1494 .Case("vsx", HasVSX)
1495 .Case("power8-vector", HasP8Vector)
1496 .Case("crypto", HasP8Crypto)
1497 .Case("direct-move", HasDirectMove)
1498 .Case("qpx", HasQPX)
1499 .Case("htm", HasHTM)
1500 .Case("bpermd", HasBPERMD)
1501 .Case("extdiv", HasExtDiv)
1502 .Case("float128", HasFloat128)
1503 .Case("power9-vector", HasP9Vector)
1507 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1508 StringRef Name, bool Enabled) const {
1509 // If we're enabling direct-move or power8-vector go ahead and enable vsx
1510 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user
1511 // incompatible options.
1513 if (Name == "direct-move" ||
1514 Name == "power8-vector" ||
1515 Name == "float128" ||
1516 Name == "power9-vector") {
1517 // power9-vector is really a superset of power8-vector so encode that.
1518 Features[Name] = Features["vsx"] = true;
1519 if (Name == "power9-vector")
1520 Features["power8-vector"] = true;
1522 Features[Name] = true;
1525 if (Name == "vsx") {
1526 Features[Name] = Features["direct-move"] = Features["power8-vector"] =
1527 Features["float128"] = Features["power9-vector"] = false;
1529 Features[Name] = false;
1534 const char * const PPCTargetInfo::GCCRegNames[] = {
1535 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1536 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1537 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1538 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1539 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1540 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1541 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1542 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1543 "mq", "lr", "ctr", "ap",
1544 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1546 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1547 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1548 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1549 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1551 "spe_acc", "spefscr",
1555 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const {
1556 return llvm::makeArrayRef(GCCRegNames);
1559 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1560 // While some of these aliases do map to different registers
1561 // they still share the same register name.
1572 { { "10" }, "r10" },
1573 { { "11" }, "r11" },
1574 { { "12" }, "r12" },
1575 { { "13" }, "r13" },
1576 { { "14" }, "r14" },
1577 { { "15" }, "r15" },
1578 { { "16" }, "r16" },
1579 { { "17" }, "r17" },
1580 { { "18" }, "r18" },
1581 { { "19" }, "r19" },
1582 { { "20" }, "r20" },
1583 { { "21" }, "r21" },
1584 { { "22" }, "r22" },
1585 { { "23" }, "r23" },
1586 { { "24" }, "r24" },
1587 { { "25" }, "r25" },
1588 { { "26" }, "r26" },
1589 { { "27" }, "r27" },
1590 { { "28" }, "r28" },
1591 { { "29" }, "r29" },
1592 { { "30" }, "r30" },
1593 { { "31" }, "r31" },
1594 { { "fr0" }, "f0" },
1595 { { "fr1" }, "f1" },
1596 { { "fr2" }, "f2" },
1597 { { "fr3" }, "f3" },
1598 { { "fr4" }, "f4" },
1599 { { "fr5" }, "f5" },
1600 { { "fr6" }, "f6" },
1601 { { "fr7" }, "f7" },
1602 { { "fr8" }, "f8" },
1603 { { "fr9" }, "f9" },
1604 { { "fr10" }, "f10" },
1605 { { "fr11" }, "f11" },
1606 { { "fr12" }, "f12" },
1607 { { "fr13" }, "f13" },
1608 { { "fr14" }, "f14" },
1609 { { "fr15" }, "f15" },
1610 { { "fr16" }, "f16" },
1611 { { "fr17" }, "f17" },
1612 { { "fr18" }, "f18" },
1613 { { "fr19" }, "f19" },
1614 { { "fr20" }, "f20" },
1615 { { "fr21" }, "f21" },
1616 { { "fr22" }, "f22" },
1617 { { "fr23" }, "f23" },
1618 { { "fr24" }, "f24" },
1619 { { "fr25" }, "f25" },
1620 { { "fr26" }, "f26" },
1621 { { "fr27" }, "f27" },
1622 { { "fr28" }, "f28" },
1623 { { "fr29" }, "f29" },
1624 { { "fr30" }, "f30" },
1625 { { "fr31" }, "f31" },
1626 { { "cc" }, "cr0" },
1629 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
1630 return llvm::makeArrayRef(GCCRegAliases);
1633 class PPC32TargetInfo : public PPCTargetInfo {
1635 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1636 : PPCTargetInfo(Triple, Opts) {
1637 resetDataLayout("E-m:e-p:32:32-i64:64-n32");
1639 switch (getTriple().getOS()) {
1640 case llvm::Triple::Linux:
1641 case llvm::Triple::FreeBSD:
1642 case llvm::Triple::NetBSD:
1643 SizeType = UnsignedInt;
1644 PtrDiffType = SignedInt;
1645 IntPtrType = SignedInt;
1651 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1652 LongDoubleWidth = LongDoubleAlign = 64;
1653 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1656 // PPC32 supports atomics up to 4 bytes.
1657 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1660 BuiltinVaListKind getBuiltinVaListKind() const override {
1661 // This is the ELF definition, and is overridden by the Darwin sub-target
1662 return TargetInfo::PowerABIBuiltinVaList;
1666 // Note: ABI differences may eventually require us to have a separate
1667 // TargetInfo for little endian.
1668 class PPC64TargetInfo : public PPCTargetInfo {
1670 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1671 : PPCTargetInfo(Triple, Opts) {
1672 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1673 IntMaxType = SignedLong;
1674 Int64Type = SignedLong;
1676 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1677 resetDataLayout("e-m:e-i64:64-n32:64");
1680 resetDataLayout("E-m:e-i64:64-n32:64");
1684 switch (getTriple().getOS()) {
1685 case llvm::Triple::FreeBSD:
1686 LongDoubleWidth = LongDoubleAlign = 64;
1687 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1689 case llvm::Triple::NetBSD:
1690 IntMaxType = SignedLongLong;
1691 Int64Type = SignedLongLong;
1697 // PPC64 supports atomics up to 8 bytes.
1698 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1700 BuiltinVaListKind getBuiltinVaListKind() const override {
1701 return TargetInfo::CharPtrBuiltinVaList;
1703 // PPC64 Linux-specific ABI options.
1704 bool setABI(const std::string &Name) override {
1705 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1713 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> {
1715 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1716 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
1717 HasAlignMac68kSupport = true;
1718 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1719 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1721 SuitableAlign = 128;
1722 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
1724 BuiltinVaListKind getBuiltinVaListKind() const override {
1725 return TargetInfo::CharPtrBuiltinVaList;
1729 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> {
1731 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1732 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
1733 HasAlignMac68kSupport = true;
1734 SuitableAlign = 128;
1735 resetDataLayout("E-m:o-i64:64-n32:64");
1739 static const unsigned NVPTXAddrSpaceMap[] = {
1742 4, // opencl_constant
1743 // FIXME: generic has to be added to the target
1744 0, // opencl_generic
1750 class NVPTXTargetInfo : public TargetInfo {
1751 static const char *const GCCRegNames[];
1752 static const Builtin::Info BuiltinInfo[];
1756 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1757 : TargetInfo(Triple) {
1758 TLSSupported = false;
1759 LongWidth = LongAlign = 64;
1760 AddrSpaceMap = &NVPTXAddrSpaceMap;
1761 UseAddrSpaceMapMangling = true;
1762 // Define available target features
1763 // These must be defined in sorted order!
1764 NoAsmVariants = true;
1765 GPU = CudaArch::SM_20;
1767 // If possible, get a TargetInfo for our host triple, so we can match its
1769 llvm::Triple HostTriple(Opts.HostTriple);
1770 if (HostTriple.isNVPTX())
1772 std::unique_ptr<TargetInfo> HostTarget(
1773 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts));
1778 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0);
1779 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0);
1780 BoolWidth = HostTarget->getBoolWidth();
1781 BoolAlign = HostTarget->getBoolAlign();
1782 IntWidth = HostTarget->getIntWidth();
1783 IntAlign = HostTarget->getIntAlign();
1784 HalfWidth = HostTarget->getHalfWidth();
1785 HalfAlign = HostTarget->getHalfAlign();
1786 FloatWidth = HostTarget->getFloatWidth();
1787 FloatAlign = HostTarget->getFloatAlign();
1788 DoubleWidth = HostTarget->getDoubleWidth();
1789 DoubleAlign = HostTarget->getDoubleAlign();
1790 LongWidth = HostTarget->getLongWidth();
1791 LongAlign = HostTarget->getLongAlign();
1792 LongLongWidth = HostTarget->getLongLongWidth();
1793 LongLongAlign = HostTarget->getLongLongAlign();
1794 MinGlobalAlign = HostTarget->getMinGlobalAlign();
1795 NewAlign = HostTarget->getNewAlign();
1796 DefaultAlignForAttributeAligned =
1797 HostTarget->getDefaultAlignForAttributeAligned();
1798 SizeType = HostTarget->getSizeType();
1799 IntMaxType = HostTarget->getIntMaxType();
1800 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0);
1801 IntPtrType = HostTarget->getIntPtrType();
1802 WCharType = HostTarget->getWCharType();
1803 WIntType = HostTarget->getWIntType();
1804 Char16Type = HostTarget->getChar16Type();
1805 Char32Type = HostTarget->getChar32Type();
1806 Int64Type = HostTarget->getInt64Type();
1807 SigAtomicType = HostTarget->getSigAtomicType();
1808 ProcessIDType = HostTarget->getProcessIDType();
1810 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
1811 UseZeroLengthBitfieldAlignment =
1812 HostTarget->useZeroLengthBitfieldAlignment();
1813 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
1814 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
1816 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
1817 // we need those macros to be identical on host and device, because (among
1818 // other things) they affect which standard library classes are defined, and
1819 // we need all classes to be defined on both the host and device.
1820 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
1822 // Properties intentionally not copied from host:
1823 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the
1824 // host/device boundary.
1825 // - SuitableAlign: Not visible across the host/device boundary, and may
1826 // correctly be different on host/device, e.g. if host has wider vector
1827 // types than device.
1828 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same
1829 // as its double type, but that's not necessarily true on the host.
1830 // TODO: nvcc emits a warning when using long double on device; we should
1833 void getTargetDefines(const LangOptions &Opts,
1834 MacroBuilder &Builder) const override {
1835 Builder.defineMacro("__PTX__");
1836 Builder.defineMacro("__NVPTX__");
1837 if (Opts.CUDAIsDevice) {
1838 // Set __CUDA_ARCH__ for the GPU specified.
1839 std::string CUDAArchCode = [this] {
1841 case CudaArch::UNKNOWN:
1842 assert(false && "No GPU arch when compiling CUDA device code.");
1844 case CudaArch::SM_20:
1846 case CudaArch::SM_21:
1848 case CudaArch::SM_30:
1850 case CudaArch::SM_32:
1852 case CudaArch::SM_35:
1854 case CudaArch::SM_37:
1856 case CudaArch::SM_50:
1858 case CudaArch::SM_52:
1860 case CudaArch::SM_53:
1862 case CudaArch::SM_60:
1864 case CudaArch::SM_61:
1866 case CudaArch::SM_62:
1869 llvm_unreachable("unhandled CudaArch");
1871 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1874 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1875 return llvm::makeArrayRef(BuiltinInfo,
1876 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin);
1879 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
1881 const std::vector<std::string> &FeaturesVec) const override {
1882 Features["satom"] = GPU >= CudaArch::SM_60;
1883 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1886 bool hasFeature(StringRef Feature) const override {
1887 return llvm::StringSwitch<bool>(Feature)
1888 .Cases("ptx", "nvptx", true)
1889 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope.
1893 ArrayRef<const char *> getGCCRegNames() const override;
1894 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1898 bool validateAsmConstraint(const char *&Name,
1899 TargetInfo::ConstraintInfo &Info) const override {
1909 Info.setAllowsRegister();
1913 const char *getClobbers() const override {
1914 // FIXME: Is this really right?
1917 BuiltinVaListKind getBuiltinVaListKind() const override {
1919 return TargetInfo::CharPtrBuiltinVaList;
1921 bool setCPU(const std::string &Name) override {
1922 GPU = StringToCudaArch(Name);
1923 return GPU != CudaArch::UNKNOWN;
1925 void setSupportedOpenCLOpts() override {
1926 auto &Opts = getSupportedOpenCLOpts();
1927 Opts.support("cl_clang_storage_class_specifiers");
1928 Opts.support("cl_khr_gl_sharing");
1929 Opts.support("cl_khr_icd");
1931 Opts.support("cl_khr_fp64");
1932 Opts.support("cl_khr_byte_addressable_store");
1933 Opts.support("cl_khr_global_int32_base_atomics");
1934 Opts.support("cl_khr_global_int32_extended_atomics");
1935 Opts.support("cl_khr_local_int32_base_atomics");
1936 Opts.support("cl_khr_local_int32_extended_atomics");
1940 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1941 #define BUILTIN(ID, TYPE, ATTRS) \
1942 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1943 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1944 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1945 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
1946 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
1947 #include "clang/Basic/BuiltinsNVPTX.def"
1950 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
1952 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
1953 return llvm::makeArrayRef(GCCRegNames);
1956 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1958 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1959 : NVPTXTargetInfo(Triple, Opts) {
1960 LongWidth = LongAlign = 32;
1961 PointerWidth = PointerAlign = 32;
1962 SizeType = TargetInfo::UnsignedInt;
1963 PtrDiffType = TargetInfo::SignedInt;
1964 IntPtrType = TargetInfo::SignedInt;
1965 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64");
1969 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1971 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1972 : NVPTXTargetInfo(Triple, Opts) {
1973 PointerWidth = PointerAlign = 64;
1974 SizeType = TargetInfo::UnsignedLong;
1975 PtrDiffType = TargetInfo::SignedLong;
1976 IntPtrType = TargetInfo::SignedLong;
1977 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64");
1981 static const unsigned AMDGPUAddrSpaceMap[] = {
1984 2, // opencl_constant
1985 4, // opencl_generic
1991 // If you edit the description strings, make sure you update
1992 // getPointerWidthV().
1994 static const char *const DataLayoutStringR600 =
1995 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1996 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1998 static const char *const DataLayoutStringSI =
1999 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
2000 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2001 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
2003 class AMDGPUTargetInfo final : public TargetInfo {
2004 static const Builtin::Info BuiltinInfo[];
2005 static const char * const GCCRegNames[];
2007 /// \brief The GPU profiles supported by the AMDGPU target.
2015 GK_EVERGREEN_DOUBLE_OPS,
2016 GK_NORTHERN_ISLANDS,
2026 bool hasFullSpeedFP32Denorms:1;
2028 static bool isAMDGCN(const llvm::Triple &TT) {
2029 return TT.getArch() == llvm::Triple::amdgcn;
2033 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
2034 : TargetInfo(Triple) ,
2035 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600),
2039 hasFullSpeedFP32Denorms(false){
2040 if (getTriple().getArch() == llvm::Triple::amdgcn) {
2046 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ?
2047 DataLayoutStringSI : DataLayoutStringR600);
2049 AddrSpaceMap = &AMDGPUAddrSpaceMap;
2050 UseAddrSpaceMapMangling = true;
2053 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
2054 if (GPU <= GK_CAYMAN)
2067 uint64_t getMaxPointerWidth() const override {
2068 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32;
2071 const char * getClobbers() const override {
2075 ArrayRef<const char *> getGCCRegNames() const override;
2077 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2081 bool validateAsmConstraint(const char *&Name,
2082 TargetInfo::ConstraintInfo &Info) const override {
2087 Info.setAllowsRegister();
2093 bool initFeatureMap(llvm::StringMap<bool> &Features,
2094 DiagnosticsEngine &Diags, StringRef CPU,
2095 const std::vector<std::string> &FeatureVec) const override;
2097 void adjustTargetOptions(const CodeGenOptions &CGOpts,
2098 TargetOptions &TargetOpts) const override {
2099 bool hasFP32Denormals = false;
2100 bool hasFP64Denormals = false;
2101 for (auto &I : TargetOpts.FeaturesAsWritten) {
2102 if (I == "+fp32-denormals" || I == "-fp32-denormals")
2103 hasFP32Denormals = true;
2104 if (I == "+fp64-denormals" || I == "-fp64-denormals")
2105 hasFP64Denormals = true;
2107 if (!hasFP32Denormals)
2108 TargetOpts.Features.push_back((Twine(hasFullSpeedFP32Denorms &&
2109 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str());
2110 // Always do not flush fp64 denorms.
2111 if (!hasFP64Denormals && hasFP64)
2112 TargetOpts.Features.push_back("+fp64-denormals");
2115 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
2116 return llvm::makeArrayRef(BuiltinInfo,
2117 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin);
2120 void getTargetDefines(const LangOptions &Opts,
2121 MacroBuilder &Builder) const override {
2122 if (getTriple().getArch() == llvm::Triple::amdgcn)
2123 Builder.defineMacro("__AMDGCN__");
2125 Builder.defineMacro("__R600__");
2128 Builder.defineMacro("__HAS_FMAF__");
2130 Builder.defineMacro("__HAS_LDEXPF__");
2132 Builder.defineMacro("__HAS_FP64__");
2135 BuiltinVaListKind getBuiltinVaListKind() const override {
2136 return TargetInfo::CharPtrBuiltinVaList;
2139 static GPUKind parseR600Name(StringRef Name) {
2140 return llvm::StringSwitch<GPUKind>(Name)
2141 .Case("r600" , GK_R600)
2142 .Case("rv610", GK_R600)
2143 .Case("rv620", GK_R600)
2144 .Case("rv630", GK_R600)
2145 .Case("rv635", GK_R600)
2146 .Case("rs780", GK_R600)
2147 .Case("rs880", GK_R600)
2148 .Case("rv670", GK_R600_DOUBLE_OPS)
2149 .Case("rv710", GK_R700)
2150 .Case("rv730", GK_R700)
2151 .Case("rv740", GK_R700_DOUBLE_OPS)
2152 .Case("rv770", GK_R700_DOUBLE_OPS)
2153 .Case("palm", GK_EVERGREEN)
2154 .Case("cedar", GK_EVERGREEN)
2155 .Case("sumo", GK_EVERGREEN)
2156 .Case("sumo2", GK_EVERGREEN)
2157 .Case("redwood", GK_EVERGREEN)
2158 .Case("juniper", GK_EVERGREEN)
2159 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
2160 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
2161 .Case("barts", GK_NORTHERN_ISLANDS)
2162 .Case("turks", GK_NORTHERN_ISLANDS)
2163 .Case("caicos", GK_NORTHERN_ISLANDS)
2164 .Case("cayman", GK_CAYMAN)
2165 .Case("aruba", GK_CAYMAN)
2169 static GPUKind parseAMDGCNName(StringRef Name) {
2170 return llvm::StringSwitch<GPUKind>(Name)
2171 .Case("tahiti", GK_GFX6)
2172 .Case("pitcairn", GK_GFX6)
2173 .Case("verde", GK_GFX6)
2174 .Case("oland", GK_GFX6)
2175 .Case("hainan", GK_GFX6)
2176 .Case("bonaire", GK_GFX7)
2177 .Case("kabini", GK_GFX7)
2178 .Case("kaveri", GK_GFX7)
2179 .Case("hawaii", GK_GFX7)
2180 .Case("mullins", GK_GFX7)
2181 .Case("gfx700", GK_GFX7)
2182 .Case("gfx701", GK_GFX7)
2183 .Case("gfx702", GK_GFX7)
2184 .Case("tonga", GK_GFX8)
2185 .Case("iceland", GK_GFX8)
2186 .Case("carrizo", GK_GFX8)
2187 .Case("fiji", GK_GFX8)
2188 .Case("stoney", GK_GFX8)
2189 .Case("polaris10", GK_GFX8)
2190 .Case("polaris11", GK_GFX8)
2191 .Case("gfx800", GK_GFX8)
2192 .Case("gfx801", GK_GFX8)
2193 .Case("gfx802", GK_GFX8)
2194 .Case("gfx803", GK_GFX8)
2195 .Case("gfx804", GK_GFX8)
2196 .Case("gfx810", GK_GFX8)
2200 bool setCPU(const std::string &Name) override {
2201 if (getTriple().getArch() == llvm::Triple::amdgcn)
2202 GPU = parseAMDGCNName(Name);
2204 GPU = parseR600Name(Name);
2206 return GPU != GK_NONE;
2209 void setSupportedOpenCLOpts() override {
2210 auto &Opts = getSupportedOpenCLOpts();
2211 Opts.support("cl_clang_storage_class_specifiers");
2212 Opts.support("cl_khr_icd");
2215 Opts.support("cl_khr_fp64");
2216 if (GPU >= GK_EVERGREEN) {
2217 Opts.support("cl_khr_byte_addressable_store");
2218 Opts.support("cl_khr_global_int32_base_atomics");
2219 Opts.support("cl_khr_global_int32_extended_atomics");
2220 Opts.support("cl_khr_local_int32_base_atomics");
2221 Opts.support("cl_khr_local_int32_extended_atomics");
2223 if (GPU >= GK_GFX6) {
2224 Opts.support("cl_khr_fp16");
2225 Opts.support("cl_khr_int64_base_atomics");
2226 Opts.support("cl_khr_int64_extended_atomics");
2227 Opts.support("cl_khr_mipmap_image");
2228 Opts.support("cl_khr_subgroups");
2229 Opts.support("cl_khr_3d_image_writes");
2230 Opts.support("cl_amd_media_ops");
2231 Opts.support("cl_amd_media_ops2");
2235 LangAS::ID getOpenCLImageAddrSpace() const override {
2236 return LangAS::opencl_constant;
2239 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2242 return CCCR_Warning;
2244 case CC_OpenCLKernel:
2249 // In amdgcn target the null pointer in global, constant, and generic
2250 // address space has value 0 but in private and local address space has
2252 uint64_t getNullPointerValue(unsigned AS) const override {
2253 return AS != LangAS::opencl_local && AS != 0 ? 0 : ~0;
2257 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
2258 #define BUILTIN(ID, TYPE, ATTRS) \
2259 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2260 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2261 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2262 #include "clang/Basic/BuiltinsAMDGPU.def"
2264 const char * const AMDGPUTargetInfo::GCCRegNames[] = {
2265 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2266 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2267 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2268 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
2269 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
2270 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
2271 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
2272 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
2273 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
2274 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
2275 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
2276 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
2277 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
2278 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
2279 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
2280 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
2281 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
2282 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
2283 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
2284 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
2285 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
2286 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
2287 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
2288 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
2289 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
2290 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
2291 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
2292 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
2293 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
2294 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
2295 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
2296 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
2297 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2298 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
2299 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
2300 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
2301 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
2302 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
2303 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
2304 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
2305 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
2306 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
2307 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
2308 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
2309 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
2310 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
2311 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
2312 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127",
2313 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi",
2314 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi"
2317 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const {
2318 return llvm::makeArrayRef(GCCRegNames);
2321 bool AMDGPUTargetInfo::initFeatureMap(
2322 llvm::StringMap<bool> &Features,
2323 DiagnosticsEngine &Diags, StringRef CPU,
2324 const std::vector<std::string> &FeatureVec) const {
2326 // XXX - What does the member GPU mean if device name string passed here?
2327 if (getTriple().getArch() == llvm::Triple::amdgcn) {
2331 switch (parseAMDGCNName(CPU)) {
2337 Features["s-memrealtime"] = true;
2338 Features["16-bit-insts"] = true;
2344 llvm_unreachable("unhandled subtarget");
2350 switch (parseR600Name(CPU)) {
2354 case GK_NORTHERN_ISLANDS:
2356 case GK_R600_DOUBLE_OPS:
2357 case GK_R700_DOUBLE_OPS:
2358 case GK_EVERGREEN_DOUBLE_OPS:
2360 Features["fp64"] = true;
2365 llvm_unreachable("unhandled subtarget");
2369 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec);
2372 const Builtin::Info BuiltinInfoX86[] = {
2373 #define BUILTIN(ID, TYPE, ATTRS) \
2374 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2375 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2376 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2377 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
2378 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
2379 #include "clang/Basic/BuiltinsX86.def"
2381 #define BUILTIN(ID, TYPE, ATTRS) \
2382 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2383 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2384 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2385 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
2386 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
2387 #include "clang/Basic/BuiltinsX86_64.def"
2391 static const char* const GCCRegNames[] = {
2392 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
2393 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
2394 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
2395 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
2396 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
2397 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2398 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
2399 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
2400 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
2401 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23",
2402 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31",
2403 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23",
2404 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31",
2405 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7",
2406 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15",
2407 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23",
2408 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31",
2409 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7",
2412 const TargetInfo::AddlRegName AddlRegNames[] = {
2413 { { "al", "ah", "eax", "rax" }, 0 },
2414 { { "bl", "bh", "ebx", "rbx" }, 3 },
2415 { { "cl", "ch", "ecx", "rcx" }, 2 },
2416 { { "dl", "dh", "edx", "rdx" }, 1 },
2417 { { "esi", "rsi" }, 4 },
2418 { { "edi", "rdi" }, 5 },
2419 { { "esp", "rsp" }, 7 },
2420 { { "ebp", "rbp" }, 6 },
2421 { { "r8d", "r8w", "r8b" }, 38 },
2422 { { "r9d", "r9w", "r9b" }, 39 },
2423 { { "r10d", "r10w", "r10b" }, 40 },
2424 { { "r11d", "r11w", "r11b" }, 41 },
2425 { { "r12d", "r12w", "r12b" }, 42 },
2426 { { "r13d", "r13w", "r13b" }, 43 },
2427 { { "r14d", "r14w", "r14b" }, 44 },
2428 { { "r15d", "r15w", "r15b" }, 45 },
2431 // X86 target abstract base class; x86-32 and x86-64 are very close, so
2432 // most of the implementation can be shared.
2433 class X86TargetInfo : public TargetInfo {
2435 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
2438 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
2439 } MMX3DNowLevel = NoMMX3DNow;
2447 bool HasAES = false;
2448 bool HasPCLMUL = false;
2449 bool HasLZCNT = false;
2450 bool HasRDRND = false;
2451 bool HasFSGSBASE = false;
2452 bool HasBMI = false;
2453 bool HasBMI2 = false;
2454 bool HasPOPCNT = false;
2455 bool HasRTM = false;
2456 bool HasPRFCHW = false;
2457 bool HasRDSEED = false;
2458 bool HasADX = false;
2459 bool HasTBM = false;
2460 bool HasFMA = false;
2461 bool HasF16C = false;
2462 bool HasAVX512CD = false;
2463 bool HasAVX512ER = false;
2464 bool HasAVX512PF = false;
2465 bool HasAVX512DQ = false;
2466 bool HasAVX512BW = false;
2467 bool HasAVX512VL = false;
2468 bool HasAVX512VBMI = false;
2469 bool HasAVX512IFMA = false;
2470 bool HasSHA = false;
2471 bool HasMPX = false;
2472 bool HasSGX = false;
2473 bool HasCX16 = false;
2474 bool HasFXSR = false;
2475 bool HasXSAVE = false;
2476 bool HasXSAVEOPT = false;
2477 bool HasXSAVEC = false;
2478 bool HasXSAVES = false;
2479 bool HasMWAITX = false;
2480 bool HasPKU = false;
2481 bool HasCLFLUSHOPT = false;
2482 bool HasPCOMMIT = false;
2483 bool HasCLWB = false;
2484 bool HasUMIP = false;
2485 bool HasMOVBE = false;
2486 bool HasPREFETCHWT1 = false;
2488 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2490 /// Each enumeration represents a particular CPU supported by Clang. These
2491 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2496 /// i386-generation processors.
2502 /// i486-generation processors.
2511 /// i586-generation processors, P5 microarchitecture based.
2519 /// i686-generation processors, P6 / Pentium M microarchitecture based.
2529 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2530 /// Clang however has some logic to suport this.
2531 // FIXME: Warn, deprecate, and potentially remove this.
2536 /// Netburst microarchitecture based processors.
2545 /// Core microarchitecture based processors.
2549 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2550 /// codename which GCC no longer accepts as an option to -march, but Clang
2551 /// has some logic for recognizing it.
2552 // FIXME: Warn, deprecate, and potentially remove this.
2564 /// Nehalem microarchitecture based processors.
2568 /// Westmere microarchitecture based processors.
2571 /// \name Sandy Bridge
2572 /// Sandy Bridge microarchitecture based processors.
2575 /// \name Ivy Bridge
2576 /// Ivy Bridge microarchitecture based processors.
2580 /// Haswell microarchitecture based processors.
2584 /// Broadwell microarchitecture based processors.
2587 /// \name Skylake Client
2588 /// Skylake client microarchitecture based processors.
2591 /// \name Skylake Server
2592 /// Skylake server microarchitecture based processors.
2595 /// \name Cannonlake Client
2596 /// Cannonlake client microarchitecture based processors.
2599 /// \name Knights Landing
2600 /// Knights Landing processor.
2604 /// Lakemont microarchitecture based processors.
2608 /// K6 architecture processors.
2616 /// K7 architecture processors.
2619 CK_AthlonThunderbird,
2626 /// K8 architecture processors.
2639 /// Bobcat architecture processors.
2646 /// Bulldozer architecture processors.
2654 /// This specification is deprecated and will be removed in the future.
2655 /// Users should prefer \see CK_K8.
2656 // FIXME: Warn on this when the CPU is set to it.
2662 /// Geode processors.
2668 CPUKind getCPUKind(StringRef CPU) const {
2669 return llvm::StringSwitch<CPUKind>(CPU)
2670 .Case("i386", CK_i386)
2671 .Case("i486", CK_i486)
2672 .Case("winchip-c6", CK_WinChipC6)
2673 .Case("winchip2", CK_WinChip2)
2675 .Case("i586", CK_i586)
2676 .Case("pentium", CK_Pentium)
2677 .Case("pentium-mmx", CK_PentiumMMX)
2678 .Case("i686", CK_i686)
2679 .Case("pentiumpro", CK_PentiumPro)
2680 .Case("pentium2", CK_Pentium2)
2681 .Case("pentium3", CK_Pentium3)
2682 .Case("pentium3m", CK_Pentium3M)
2683 .Case("pentium-m", CK_PentiumM)
2684 .Case("c3-2", CK_C3_2)
2685 .Case("yonah", CK_Yonah)
2686 .Case("pentium4", CK_Pentium4)
2687 .Case("pentium4m", CK_Pentium4M)
2688 .Case("prescott", CK_Prescott)
2689 .Case("nocona", CK_Nocona)
2690 .Case("core2", CK_Core2)
2691 .Case("penryn", CK_Penryn)
2692 .Case("bonnell", CK_Bonnell)
2693 .Case("atom", CK_Bonnell) // Legacy name.
2694 .Case("silvermont", CK_Silvermont)
2695 .Case("slm", CK_Silvermont) // Legacy name.
2696 .Case("nehalem", CK_Nehalem)
2697 .Case("corei7", CK_Nehalem) // Legacy name.
2698 .Case("westmere", CK_Westmere)
2699 .Case("sandybridge", CK_SandyBridge)
2700 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2701 .Case("ivybridge", CK_IvyBridge)
2702 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2703 .Case("haswell", CK_Haswell)
2704 .Case("core-avx2", CK_Haswell) // Legacy name.
2705 .Case("broadwell", CK_Broadwell)
2706 .Case("skylake", CK_SkylakeClient)
2707 .Case("skylake-avx512", CK_SkylakeServer)
2708 .Case("skx", CK_SkylakeServer) // Legacy name.
2709 .Case("cannonlake", CK_Cannonlake)
2710 .Case("knl", CK_KNL)
2711 .Case("lakemont", CK_Lakemont)
2713 .Case("k6-2", CK_K6_2)
2714 .Case("k6-3", CK_K6_3)
2715 .Case("athlon", CK_Athlon)
2716 .Case("athlon-tbird", CK_AthlonThunderbird)
2717 .Case("athlon-4", CK_Athlon4)
2718 .Case("athlon-xp", CK_AthlonXP)
2719 .Case("athlon-mp", CK_AthlonMP)
2720 .Case("athlon64", CK_Athlon64)
2721 .Case("athlon64-sse3", CK_Athlon64SSE3)
2722 .Case("athlon-fx", CK_AthlonFX)
2724 .Case("k8-sse3", CK_K8SSE3)
2725 .Case("opteron", CK_Opteron)
2726 .Case("opteron-sse3", CK_OpteronSSE3)
2727 .Case("barcelona", CK_AMDFAM10)
2728 .Case("amdfam10", CK_AMDFAM10)
2729 .Case("btver1", CK_BTVER1)
2730 .Case("btver2", CK_BTVER2)
2731 .Case("bdver1", CK_BDVER1)
2732 .Case("bdver2", CK_BDVER2)
2733 .Case("bdver3", CK_BDVER3)
2734 .Case("bdver4", CK_BDVER4)
2735 .Case("x86-64", CK_x86_64)
2736 .Case("geode", CK_Geode)
2737 .Default(CK_Generic);
2744 } FPMath = FP_Default;
2747 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
2748 : TargetInfo(Triple) {
2749 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
2751 unsigned getFloatEvalMethod() const override {
2752 // X87 evaluates with 80 bits "long double" precision.
2753 return SSELevel == NoSSE ? 2 : 0;
2755 ArrayRef<const char *> getGCCRegNames() const override {
2756 return llvm::makeArrayRef(GCCRegNames);
2758 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2761 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
2762 return llvm::makeArrayRef(AddlRegNames);
2764 bool validateCpuSupports(StringRef Name) const override;
2765 bool validateAsmConstraint(const char *&Name,
2766 TargetInfo::ConstraintInfo &info) const override;
2768 bool validateGlobalRegisterVariable(StringRef RegName,
2770 bool &HasSizeMismatch) const override {
2771 // esp and ebp are the only 32-bit registers the x86 backend can currently
2773 if (RegName.equals("esp") || RegName.equals("ebp")) {
2774 // Check that the register size is 32-bit.
2775 HasSizeMismatch = RegSize != 32;
2782 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2784 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2786 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2788 std::string convertConstraint(const char *&Constraint) const override;
2789 const char *getClobbers() const override {
2790 return "~{dirflag},~{fpsr},~{flags}";
2793 StringRef getConstraintRegister(const StringRef &Constraint,
2794 const StringRef &Expression) const override {
2795 StringRef::iterator I, E;
2796 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) {
2803 // For the register constraints, return the matching register name
2816 // In case the constraint is 'r' we need to return Expression
2820 // Default value if there is no constraint for the register
2826 void getTargetDefines(const LangOptions &Opts,
2827 MacroBuilder &Builder) const override;
2828 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2830 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2832 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2834 void setFeatureEnabled(llvm::StringMap<bool> &Features,
2835 StringRef Name, bool Enabled) const override {
2836 setFeatureEnabledImpl(Features, Name, Enabled);
2838 // This exists purely to cut down on the number of virtual calls in
2839 // initFeatureMap which calls this repeatedly.
2840 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2841 StringRef Name, bool Enabled);
2843 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
2845 const std::vector<std::string> &FeaturesVec) const override;
2846 bool hasFeature(StringRef Feature) const override;
2847 bool handleTargetFeatures(std::vector<std::string> &Features,
2848 DiagnosticsEngine &Diags) override;
2849 StringRef getABI() const override {
2850 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
2852 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2854 if (getTriple().getArch() == llvm::Triple::x86 &&
2855 MMX3DNowLevel == NoMMX3DNow)
2859 bool setCPU(const std::string &Name) override {
2860 CPU = getCPUKind(Name);
2862 // Perform any per-CPU checks necessary to determine if this CPU is
2864 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2865 // invalid without explaining *why*.
2868 // No processor selected!
2895 case CK_AthlonThunderbird:
2900 // Only accept certain architectures when compiling in 32-bit mode.
2901 if (getTriple().getArch() != llvm::Triple::x86)
2912 case CK_SandyBridge:
2916 case CK_SkylakeClient:
2917 case CK_SkylakeServer:
2921 case CK_Athlon64SSE3:
2926 case CK_OpteronSSE3:
2937 llvm_unreachable("Unhandled CPU kind");
2940 bool setFPMath(StringRef Name) override;
2942 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2943 // Most of the non-ARM calling conventions are i386 conventions.
2945 case CC_X86ThisCall:
2946 case CC_X86FastCall:
2948 case CC_X86VectorCall:
2953 case CC_IntelOclBicc:
2956 return CCCR_Warning;
2960 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2961 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2964 bool hasSjLjLowering() const override {
2968 void setSupportedOpenCLOpts() override {
2969 getSupportedOpenCLOpts().supportAll();
2973 bool X86TargetInfo::setFPMath(StringRef Name) {
2974 if (Name == "387") {
2978 if (Name == "sse") {
2985 bool X86TargetInfo::initFeatureMap(
2986 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
2987 const std::vector<std::string> &FeaturesVec) const {
2988 // FIXME: This *really* should not be here.
2989 // X86_64 always has SSE2.
2990 if (getTriple().getArch() == llvm::Triple::x86_64)
2991 setFeatureEnabledImpl(Features, "sse2", true);
2993 const CPUKind Kind = getCPUKind(CPU);
2995 // Enable X87 for all X86 processors but Lakemont.
2996 if (Kind != CK_Lakemont)
2997 setFeatureEnabledImpl(Features, "x87", true);
3013 setFeatureEnabledImpl(Features, "mmx", true);
3018 setFeatureEnabledImpl(Features, "sse", true);
3019 setFeatureEnabledImpl(Features, "fxsr", true);
3025 setFeatureEnabledImpl(Features, "sse2", true);
3026 setFeatureEnabledImpl(Features, "fxsr", true);
3031 setFeatureEnabledImpl(Features, "sse3", true);
3032 setFeatureEnabledImpl(Features, "fxsr", true);
3033 setFeatureEnabledImpl(Features, "cx16", true);
3037 setFeatureEnabledImpl(Features, "ssse3", true);
3038 setFeatureEnabledImpl(Features, "fxsr", true);
3039 setFeatureEnabledImpl(Features, "cx16", true);
3042 setFeatureEnabledImpl(Features, "sse4.1", true);
3043 setFeatureEnabledImpl(Features, "fxsr", true);
3044 setFeatureEnabledImpl(Features, "cx16", true);
3047 setFeatureEnabledImpl(Features, "avx512ifma", true);
3048 setFeatureEnabledImpl(Features, "avx512vbmi", true);
3049 setFeatureEnabledImpl(Features, "sha", true);
3050 setFeatureEnabledImpl(Features, "umip", true);
3052 case CK_SkylakeServer:
3053 setFeatureEnabledImpl(Features, "avx512f", true);
3054 setFeatureEnabledImpl(Features, "avx512cd", true);
3055 setFeatureEnabledImpl(Features, "avx512dq", true);
3056 setFeatureEnabledImpl(Features, "avx512bw", true);
3057 setFeatureEnabledImpl(Features, "avx512vl", true);
3058 setFeatureEnabledImpl(Features, "pku", true);
3059 setFeatureEnabledImpl(Features, "pcommit", true);
3060 setFeatureEnabledImpl(Features, "clwb", true);
3062 case CK_SkylakeClient:
3063 setFeatureEnabledImpl(Features, "xsavec", true);
3064 setFeatureEnabledImpl(Features, "xsaves", true);
3065 setFeatureEnabledImpl(Features, "mpx", true);
3066 setFeatureEnabledImpl(Features, "sgx", true);
3067 setFeatureEnabledImpl(Features, "clflushopt", true);
3070 setFeatureEnabledImpl(Features, "rdseed", true);
3071 setFeatureEnabledImpl(Features, "adx", true);
3074 setFeatureEnabledImpl(Features, "avx2", true);
3075 setFeatureEnabledImpl(Features, "lzcnt", true);
3076 setFeatureEnabledImpl(Features, "bmi", true);
3077 setFeatureEnabledImpl(Features, "bmi2", true);
3078 setFeatureEnabledImpl(Features, "rtm", true);
3079 setFeatureEnabledImpl(Features, "fma", true);
3080 setFeatureEnabledImpl(Features, "movbe", true);
3083 setFeatureEnabledImpl(Features, "rdrnd", true);
3084 setFeatureEnabledImpl(Features, "f16c", true);
3085 setFeatureEnabledImpl(Features, "fsgsbase", true);
3087 case CK_SandyBridge:
3088 setFeatureEnabledImpl(Features, "avx", true);
3089 setFeatureEnabledImpl(Features, "xsave", true);
3090 setFeatureEnabledImpl(Features, "xsaveopt", true);
3094 setFeatureEnabledImpl(Features, "aes", true);
3095 setFeatureEnabledImpl(Features, "pclmul", true);
3098 setFeatureEnabledImpl(Features, "sse4.2", true);
3099 setFeatureEnabledImpl(Features, "fxsr", true);
3100 setFeatureEnabledImpl(Features, "cx16", true);
3103 setFeatureEnabledImpl(Features, "avx512f", true);
3104 setFeatureEnabledImpl(Features, "avx512cd", true);
3105 setFeatureEnabledImpl(Features, "avx512er", true);
3106 setFeatureEnabledImpl(Features, "avx512pf", true);
3107 setFeatureEnabledImpl(Features, "prefetchwt1", true);
3108 setFeatureEnabledImpl(Features, "fxsr", true);
3109 setFeatureEnabledImpl(Features, "rdseed", true);
3110 setFeatureEnabledImpl(Features, "adx", true);
3111 setFeatureEnabledImpl(Features, "lzcnt", true);
3112 setFeatureEnabledImpl(Features, "bmi", true);
3113 setFeatureEnabledImpl(Features, "bmi2", true);
3114 setFeatureEnabledImpl(Features, "rtm", true);
3115 setFeatureEnabledImpl(Features, "fma", true);
3116 setFeatureEnabledImpl(Features, "rdrnd", true);
3117 setFeatureEnabledImpl(Features, "f16c", true);
3118 setFeatureEnabledImpl(Features, "fsgsbase", true);
3119 setFeatureEnabledImpl(Features, "aes", true);
3120 setFeatureEnabledImpl(Features, "pclmul", true);
3121 setFeatureEnabledImpl(Features, "cx16", true);
3122 setFeatureEnabledImpl(Features, "xsaveopt", true);
3123 setFeatureEnabledImpl(Features, "xsave", true);
3124 setFeatureEnabledImpl(Features, "movbe", true);
3130 setFeatureEnabledImpl(Features, "3dnow", true);
3133 case CK_AthlonThunderbird:
3135 setFeatureEnabledImpl(Features, "3dnowa", true);
3140 setFeatureEnabledImpl(Features, "sse", true);
3141 setFeatureEnabledImpl(Features, "3dnowa", true);
3142 setFeatureEnabledImpl(Features, "fxsr", true);
3148 setFeatureEnabledImpl(Features, "sse2", true);
3149 setFeatureEnabledImpl(Features, "3dnowa", true);
3150 setFeatureEnabledImpl(Features, "fxsr", true);
3153 setFeatureEnabledImpl(Features, "sse4a", true);
3154 setFeatureEnabledImpl(Features, "lzcnt", true);
3155 setFeatureEnabledImpl(Features, "popcnt", true);
3158 case CK_OpteronSSE3:
3159 case CK_Athlon64SSE3:
3160 setFeatureEnabledImpl(Features, "sse3", true);
3161 setFeatureEnabledImpl(Features, "3dnowa", true);
3162 setFeatureEnabledImpl(Features, "fxsr", true);
3165 setFeatureEnabledImpl(Features, "avx", true);
3166 setFeatureEnabledImpl(Features, "aes", true);
3167 setFeatureEnabledImpl(Features, "pclmul", true);
3168 setFeatureEnabledImpl(Features, "bmi", true);
3169 setFeatureEnabledImpl(Features, "f16c", true);
3170 setFeatureEnabledImpl(Features, "xsaveopt", true);
3173 setFeatureEnabledImpl(Features, "ssse3", true);
3174 setFeatureEnabledImpl(Features, "sse4a", true);
3175 setFeatureEnabledImpl(Features, "lzcnt", true);
3176 setFeatureEnabledImpl(Features, "popcnt", true);
3177 setFeatureEnabledImpl(Features, "prfchw", true);
3178 setFeatureEnabledImpl(Features, "cx16", true);
3179 setFeatureEnabledImpl(Features, "fxsr", true);
3182 setFeatureEnabledImpl(Features, "avx2", true);
3183 setFeatureEnabledImpl(Features, "bmi2", true);
3184 setFeatureEnabledImpl(Features, "mwaitx", true);
3187 setFeatureEnabledImpl(Features, "fsgsbase", true);
3188 setFeatureEnabledImpl(Features, "xsaveopt", true);
3191 setFeatureEnabledImpl(Features, "bmi", true);
3192 setFeatureEnabledImpl(Features, "fma", true);
3193 setFeatureEnabledImpl(Features, "f16c", true);
3194 setFeatureEnabledImpl(Features, "tbm", true);
3197 // xop implies avx, sse4a and fma4.
3198 setFeatureEnabledImpl(Features, "xop", true);
3199 setFeatureEnabledImpl(Features, "lzcnt", true);
3200 setFeatureEnabledImpl(Features, "aes", true);
3201 setFeatureEnabledImpl(Features, "pclmul", true);
3202 setFeatureEnabledImpl(Features, "prfchw", true);
3203 setFeatureEnabledImpl(Features, "cx16", true);
3204 setFeatureEnabledImpl(Features, "fxsr", true);
3205 setFeatureEnabledImpl(Features, "xsave", true);
3208 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
3211 // Can't do this earlier because we need to be able to explicitly enable
3212 // or disable these features and the things that they depend upon.
3214 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
3215 auto I = Features.find("sse4.2");
3216 if (I != Features.end() && I->getValue() &&
3217 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
3219 Features["popcnt"] = true;
3221 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
3222 I = Features.find("3dnow");
3223 if (I != Features.end() && I->getValue() &&
3224 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
3226 Features["prfchw"] = true;
3228 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
3230 I = Features.find("sse");
3231 if (I != Features.end() && I->getValue() &&
3232 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
3234 Features["mmx"] = true;
3239 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
3240 X86SSEEnum Level, bool Enabled) {
3244 Features["avx512f"] = true;
3246 Features["avx2"] = true;
3248 Features["avx"] = true;
3249 Features["xsave"] = true;
3251 Features["sse4.2"] = true;
3253 Features["sse4.1"] = true;
3255 Features["ssse3"] = true;
3257 Features["sse3"] = true;
3259 Features["sse2"] = true;
3261 Features["sse"] = true;
3271 Features["sse"] = false;
3273 Features["sse2"] = Features["pclmul"] = Features["aes"] =
3274 Features["sha"] = false;
3276 Features["sse3"] = false;
3277 setXOPLevel(Features, NoXOP, false);
3279 Features["ssse3"] = false;
3281 Features["sse4.1"] = false;
3283 Features["sse4.2"] = false;
3285 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
3286 Features["xsaveopt"] = false;
3287 setXOPLevel(Features, FMA4, false);
3289 Features["avx2"] = false;
3291 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
3292 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
3293 Features["avx512vl"] = Features["avx512vbmi"] =
3294 Features["avx512ifma"] = false;
3298 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
3299 MMX3DNowEnum Level, bool Enabled) {
3302 case AMD3DNowAthlon:
3303 Features["3dnowa"] = true;
3305 Features["3dnow"] = true;
3307 Features["mmx"] = true;
3317 Features["mmx"] = false;
3319 Features["3dnow"] = false;
3320 case AMD3DNowAthlon:
3321 Features["3dnowa"] = false;
3325 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
3330 Features["xop"] = true;
3332 Features["fma4"] = true;
3333 setSSELevel(Features, AVX, true);
3335 Features["sse4a"] = true;
3336 setSSELevel(Features, SSE3, true);
3346 Features["sse4a"] = false;
3348 Features["fma4"] = false;
3350 Features["xop"] = false;
3354 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
3355 StringRef Name, bool Enabled) {
3356 // This is a bit of a hack to deal with the sse4 target feature when used
3357 // as part of the target attribute. We handle sse4 correctly everywhere
3358 // else. See below for more information on how we handle the sse4 options.
3360 Features[Name] = Enabled;
3362 if (Name == "mmx") {
3363 setMMXLevel(Features, MMX, Enabled);
3364 } else if (Name == "sse") {
3365 setSSELevel(Features, SSE1, Enabled);
3366 } else if (Name == "sse2") {
3367 setSSELevel(Features, SSE2, Enabled);
3368 } else if (Name == "sse3") {
3369 setSSELevel(Features, SSE3, Enabled);
3370 } else if (Name == "ssse3") {
3371 setSSELevel(Features, SSSE3, Enabled);
3372 } else if (Name == "sse4.2") {
3373 setSSELevel(Features, SSE42, Enabled);
3374 } else if (Name == "sse4.1") {
3375 setSSELevel(Features, SSE41, Enabled);
3376 } else if (Name == "3dnow") {
3377 setMMXLevel(Features, AMD3DNow, Enabled);
3378 } else if (Name == "3dnowa") {
3379 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
3380 } else if (Name == "aes") {
3382 setSSELevel(Features, SSE2, Enabled);
3383 } else if (Name == "pclmul") {
3385 setSSELevel(Features, SSE2, Enabled);
3386 } else if (Name == "avx") {
3387 setSSELevel(Features, AVX, Enabled);
3388 } else if (Name == "avx2") {
3389 setSSELevel(Features, AVX2, Enabled);
3390 } else if (Name == "avx512f") {
3391 setSSELevel(Features, AVX512F, Enabled);
3392 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
3393 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
3394 Name == "avx512vbmi" || Name == "avx512ifma") {
3396 setSSELevel(Features, AVX512F, Enabled);
3397 // Enable BWI instruction if VBMI is being enabled.
3398 if (Name == "avx512vbmi" && Enabled)
3399 Features["avx512bw"] = true;
3400 // Also disable VBMI if BWI is being disabled.
3401 if (Name == "avx512bw" && !Enabled)
3402 Features["avx512vbmi"] = false;
3403 } else if (Name == "fma") {
3405 setSSELevel(Features, AVX, Enabled);
3406 } else if (Name == "fma4") {
3407 setXOPLevel(Features, FMA4, Enabled);
3408 } else if (Name == "xop") {
3409 setXOPLevel(Features, XOP, Enabled);
3410 } else if (Name == "sse4a") {
3411 setXOPLevel(Features, SSE4A, Enabled);
3412 } else if (Name == "f16c") {
3414 setSSELevel(Features, AVX, Enabled);
3415 } else if (Name == "sha") {
3417 setSSELevel(Features, SSE2, Enabled);
3418 } else if (Name == "sse4") {
3419 // We can get here via the __target__ attribute since that's not controlled
3420 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
3421 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
3424 setSSELevel(Features, SSE42, Enabled);
3426 setSSELevel(Features, SSE41, Enabled);
3427 } else if (Name == "xsave") {
3429 Features["xsaveopt"] = false;
3430 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
3432 Features["xsave"] = true;
3436 /// handleTargetFeatures - Perform initialization based on the user
3437 /// configured set of features.
3438 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
3439 DiagnosticsEngine &Diags) {
3440 for (const auto &Feature : Features) {
3441 if (Feature[0] != '+')
3444 if (Feature == "+aes") {
3446 } else if (Feature == "+pclmul") {
3448 } else if (Feature == "+lzcnt") {
3450 } else if (Feature == "+rdrnd") {
3452 } else if (Feature == "+fsgsbase") {
3454 } else if (Feature == "+bmi") {
3456 } else if (Feature == "+bmi2") {
3458 } else if (Feature == "+popcnt") {
3460 } else if (Feature == "+rtm") {
3462 } else if (Feature == "+prfchw") {
3464 } else if (Feature == "+rdseed") {
3466 } else if (Feature == "+adx") {
3468 } else if (Feature == "+tbm") {
3470 } else if (Feature == "+fma") {
3472 } else if (Feature == "+f16c") {
3474 } else if (Feature == "+avx512cd") {
3476 } else if (Feature == "+avx512er") {
3478 } else if (Feature == "+avx512pf") {
3480 } else if (Feature == "+avx512dq") {
3482 } else if (Feature == "+avx512bw") {
3484 } else if (Feature == "+avx512vl") {
3486 } else if (Feature == "+avx512vbmi") {
3487 HasAVX512VBMI = true;
3488 } else if (Feature == "+avx512ifma") {
3489 HasAVX512IFMA = true;
3490 } else if (Feature == "+sha") {
3492 } else if (Feature == "+mpx") {
3494 } else if (Feature == "+movbe") {
3496 } else if (Feature == "+sgx") {
3498 } else if (Feature == "+cx16") {
3500 } else if (Feature == "+fxsr") {
3502 } else if (Feature == "+xsave") {
3504 } else if (Feature == "+xsaveopt") {
3506 } else if (Feature == "+xsavec") {
3508 } else if (Feature == "+xsaves") {
3510 } else if (Feature == "+mwaitx") {
3512 } else if (Feature == "+pku") {
3514 } else if (Feature == "+clflushopt") {
3515 HasCLFLUSHOPT = true;
3516 } else if (Feature == "+pcommit") {
3518 } else if (Feature == "+clwb") {
3520 } else if (Feature == "+umip") {
3522 } else if (Feature == "+prefetchwt1") {
3523 HasPREFETCHWT1 = true;
3526 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
3527 .Case("+avx512f", AVX512F)
3528 .Case("+avx2", AVX2)
3530 .Case("+sse4.2", SSE42)
3531 .Case("+sse4.1", SSE41)
3532 .Case("+ssse3", SSSE3)
3533 .Case("+sse3", SSE3)
3534 .Case("+sse2", SSE2)
3537 SSELevel = std::max(SSELevel, Level);
3539 MMX3DNowEnum ThreeDNowLevel =
3540 llvm::StringSwitch<MMX3DNowEnum>(Feature)
3541 .Case("+3dnowa", AMD3DNowAthlon)
3542 .Case("+3dnow", AMD3DNow)
3544 .Default(NoMMX3DNow);
3545 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
3547 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
3549 .Case("+fma4", FMA4)
3550 .Case("+sse4a", SSE4A)
3552 XOPLevel = std::max(XOPLevel, XLevel);
3555 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
3556 // matches the selected sse level.
3557 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
3558 (FPMath == FP_387 && SSELevel >= SSE1)) {
3559 Diags.Report(diag::err_target_unsupported_fpmath) <<
3560 (FPMath == FP_SSE ? "sse" : "387");
3565 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3569 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
3570 /// definitions for this particular subtarget.
3571 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
3572 MacroBuilder &Builder) const {
3573 // Target identification.
3574 if (getTriple().getArch() == llvm::Triple::x86_64) {
3575 Builder.defineMacro("__amd64__");
3576 Builder.defineMacro("__amd64");
3577 Builder.defineMacro("__x86_64");
3578 Builder.defineMacro("__x86_64__");
3579 if (getTriple().getArchName() == "x86_64h") {
3580 Builder.defineMacro("__x86_64h");
3581 Builder.defineMacro("__x86_64h__");
3584 DefineStd(Builder, "i386", Opts);
3587 // Subtarget options.
3588 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
3589 // truly should be based on -mtune options.
3594 // The rest are coming from the i386 define above.
3595 Builder.defineMacro("__tune_i386__");
3601 defineCPUMacros(Builder, "i486");
3604 Builder.defineMacro("__pentium_mmx__");
3605 Builder.defineMacro("__tune_pentium_mmx__");
3609 defineCPUMacros(Builder, "i586");
3610 defineCPUMacros(Builder, "pentium");
3615 Builder.defineMacro("__tune_pentium3__");
3619 Builder.defineMacro("__tune_pentium2__");
3622 Builder.defineMacro("__tune_i686__");
3623 Builder.defineMacro("__tune_pentiumpro__");
3626 Builder.defineMacro("__i686");
3627 Builder.defineMacro("__i686__");
3628 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3629 Builder.defineMacro("__pentiumpro");
3630 Builder.defineMacro("__pentiumpro__");
3634 defineCPUMacros(Builder, "pentium4");
3639 defineCPUMacros(Builder, "nocona");
3643 defineCPUMacros(Builder, "core2");
3646 defineCPUMacros(Builder, "atom");
3649 defineCPUMacros(Builder, "slm");
3653 case CK_SandyBridge:
3657 case CK_SkylakeClient:
3658 // FIXME: Historically, we defined this legacy name, it would be nice to
3659 // remove it at some point. We've never exposed fine-grained names for
3660 // recent primary x86 CPUs, and we should keep it that way.
3661 defineCPUMacros(Builder, "corei7");
3663 case CK_SkylakeServer:
3664 defineCPUMacros(Builder, "skx");
3669 defineCPUMacros(Builder, "knl");
3672 Builder.defineMacro("__tune_lakemont__");
3675 Builder.defineMacro("__k6_2__");
3676 Builder.defineMacro("__tune_k6_2__");
3679 if (CPU != CK_K6_2) { // In case of fallthrough
3680 // FIXME: GCC may be enabling these in cases where some other k6
3681 // architecture is specified but -m3dnow is explicitly provided. The
3682 // exact semantics need to be determined and emulated here.
3683 Builder.defineMacro("__k6_3__");
3684 Builder.defineMacro("__tune_k6_3__");
3688 defineCPUMacros(Builder, "k6");
3691 case CK_AthlonThunderbird:
3695 defineCPUMacros(Builder, "athlon");
3696 if (SSELevel != NoSSE) {
3697 Builder.defineMacro("__athlon_sse__");
3698 Builder.defineMacro("__tune_athlon_sse__");
3705 case CK_OpteronSSE3:
3707 case CK_Athlon64SSE3:
3709 defineCPUMacros(Builder, "k8");
3712 defineCPUMacros(Builder, "amdfam10");
3715 defineCPUMacros(Builder, "btver1");
3718 defineCPUMacros(Builder, "btver2");
3721 defineCPUMacros(Builder, "bdver1");
3724 defineCPUMacros(Builder, "bdver2");
3727 defineCPUMacros(Builder, "bdver3");
3730 defineCPUMacros(Builder, "bdver4");
3733 defineCPUMacros(Builder, "geode");
3737 // Target properties.
3738 Builder.defineMacro("__REGISTER_PREFIX__", "");
3740 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3741 // functions in glibc header files that use FP Stack inline asm which the
3742 // backend can't deal with (PR879).
3743 Builder.defineMacro("__NO_MATH_INLINES");
3746 Builder.defineMacro("__AES__");
3749 Builder.defineMacro("__PCLMUL__");
3752 Builder.defineMacro("__LZCNT__");
3755 Builder.defineMacro("__RDRND__");
3758 Builder.defineMacro("__FSGSBASE__");
3761 Builder.defineMacro("__BMI__");
3764 Builder.defineMacro("__BMI2__");
3767 Builder.defineMacro("__POPCNT__");
3770 Builder.defineMacro("__RTM__");
3773 Builder.defineMacro("__PRFCHW__");
3776 Builder.defineMacro("__RDSEED__");
3779 Builder.defineMacro("__ADX__");
3782 Builder.defineMacro("__TBM__");
3785 Builder.defineMacro("__MWAITX__");
3789 Builder.defineMacro("__XOP__");
3791 Builder.defineMacro("__FMA4__");
3793 Builder.defineMacro("__SSE4A__");
3799 Builder.defineMacro("__FMA__");
3802 Builder.defineMacro("__F16C__");
3805 Builder.defineMacro("__AVX512CD__");
3807 Builder.defineMacro("__AVX512ER__");
3809 Builder.defineMacro("__AVX512PF__");
3811 Builder.defineMacro("__AVX512DQ__");
3813 Builder.defineMacro("__AVX512BW__");
3815 Builder.defineMacro("__AVX512VL__");
3817 Builder.defineMacro("__AVX512VBMI__");
3819 Builder.defineMacro("__AVX512IFMA__");
3822 Builder.defineMacro("__SHA__");
3825 Builder.defineMacro("__FXSR__");
3827 Builder.defineMacro("__XSAVE__");
3829 Builder.defineMacro("__XSAVEOPT__");
3831 Builder.defineMacro("__XSAVEC__");
3833 Builder.defineMacro("__XSAVES__");
3835 Builder.defineMacro("__PKU__");
3837 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3839 // Each case falls through to the previous one here.
3842 Builder.defineMacro("__AVX512F__");
3844 Builder.defineMacro("__AVX2__");
3846 Builder.defineMacro("__AVX__");
3848 Builder.defineMacro("__SSE4_2__");
3850 Builder.defineMacro("__SSE4_1__");
3852 Builder.defineMacro("__SSSE3__");
3854 Builder.defineMacro("__SSE3__");
3856 Builder.defineMacro("__SSE2__");
3857 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
3859 Builder.defineMacro("__SSE__");
3860 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
3865 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3875 Builder.defineMacro("_M_IX86_FP", Twine(2));
3878 Builder.defineMacro("_M_IX86_FP", Twine(1));
3881 Builder.defineMacro("_M_IX86_FP", Twine(0));
3885 // Each case falls through to the previous one here.
3886 switch (MMX3DNowLevel) {
3887 case AMD3DNowAthlon:
3888 Builder.defineMacro("__3dNOW_A__");
3890 Builder.defineMacro("__3dNOW__");
3892 Builder.defineMacro("__MMX__");
3897 if (CPU >= CK_i486) {
3898 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3899 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3900 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3903 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3906 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3907 return llvm::StringSwitch<bool>(Feature)
3908 .Case("aes", HasAES)
3909 .Case("avx", SSELevel >= AVX)
3910 .Case("avx2", SSELevel >= AVX2)
3911 .Case("avx512f", SSELevel >= AVX512F)
3912 .Case("avx512cd", HasAVX512CD)
3913 .Case("avx512er", HasAVX512ER)
3914 .Case("avx512pf", HasAVX512PF)
3915 .Case("avx512dq", HasAVX512DQ)
3916 .Case("avx512bw", HasAVX512BW)
3917 .Case("avx512vl", HasAVX512VL)
3918 .Case("avx512vbmi", HasAVX512VBMI)
3919 .Case("avx512ifma", HasAVX512IFMA)
3920 .Case("bmi", HasBMI)
3921 .Case("bmi2", HasBMI2)
3922 .Case("clflushopt", HasCLFLUSHOPT)
3923 .Case("clwb", HasCLWB)
3924 .Case("cx16", HasCX16)
3925 .Case("f16c", HasF16C)
3926 .Case("fma", HasFMA)
3927 .Case("fma4", XOPLevel >= FMA4)
3928 .Case("fsgsbase", HasFSGSBASE)
3929 .Case("fxsr", HasFXSR)
3930 .Case("lzcnt", HasLZCNT)
3931 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3932 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3933 .Case("mmx", MMX3DNowLevel >= MMX)
3934 .Case("movbe", HasMOVBE)
3935 .Case("mpx", HasMPX)
3936 .Case("pclmul", HasPCLMUL)
3937 .Case("pcommit", HasPCOMMIT)
3938 .Case("pku", HasPKU)
3939 .Case("popcnt", HasPOPCNT)
3940 .Case("prefetchwt1", HasPREFETCHWT1)
3941 .Case("prfchw", HasPRFCHW)
3942 .Case("rdrnd", HasRDRND)
3943 .Case("rdseed", HasRDSEED)
3944 .Case("rtm", HasRTM)
3945 .Case("sgx", HasSGX)
3946 .Case("sha", HasSHA)
3947 .Case("sse", SSELevel >= SSE1)
3948 .Case("sse2", SSELevel >= SSE2)
3949 .Case("sse3", SSELevel >= SSE3)
3950 .Case("ssse3", SSELevel >= SSSE3)
3951 .Case("sse4.1", SSELevel >= SSE41)
3952 .Case("sse4.2", SSELevel >= SSE42)
3953 .Case("sse4a", XOPLevel >= SSE4A)
3954 .Case("tbm", HasTBM)
3955 .Case("umip", HasUMIP)
3957 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3958 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3959 .Case("xop", XOPLevel >= XOP)
3960 .Case("xsave", HasXSAVE)
3961 .Case("xsavec", HasXSAVEC)
3962 .Case("xsaves", HasXSAVES)
3963 .Case("xsaveopt", HasXSAVEOPT)
3967 // We can't use a generic validation scheme for the features accepted here
3968 // versus subtarget features accepted in the target attribute because the
3969 // bitfield structure that's initialized in the runtime only supports the
3970 // below currently rather than the full range of subtarget features. (See
3971 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
3972 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
3973 return llvm::StringSwitch<bool>(FeatureStr)
3976 .Case("popcnt", true)
3980 .Case("ssse3", true)
3981 .Case("sse4.1", true)
3982 .Case("sse4.2", true)
3985 .Case("sse4a", true)
3989 .Case("avx512f", true)
3993 .Case("pclmul", true)
3994 .Case("avx512vl", true)
3995 .Case("avx512bw", true)
3996 .Case("avx512dq", true)
3997 .Case("avx512cd", true)
3998 .Case("avx512er", true)
3999 .Case("avx512pf", true)
4000 .Case("avx512vbmi", true)
4001 .Case("avx512ifma", true)
4006 X86TargetInfo::validateAsmConstraint(const char *&Name,
4007 TargetInfo::ConstraintInfo &Info) const {
4009 default: return false;
4010 // Constant constraints.
4011 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
4013 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
4014 // x86_64 instructions.
4016 Info.setRequiresImmediate();
4019 Info.setRequiresImmediate(0, 31);
4022 Info.setRequiresImmediate(0, 63);
4025 Info.setRequiresImmediate(-128, 127);
4028 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) });
4031 Info.setRequiresImmediate(0, 3);
4034 Info.setRequiresImmediate(0, 255);
4037 Info.setRequiresImmediate(0, 127);
4039 // Register constraints.
4040 case 'Y': // 'Y' is the first character for several 2-character constraints.
4041 // Shift the pointer to the second character of the constraint.
4046 case '0': // First SSE register.
4047 case 't': // Any SSE register, when SSE2 is enabled.
4048 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
4049 case 'm': // Any MMX register, when inter-unit moves enabled.
4050 case 'k': // AVX512 arch mask registers: k1-k7.
4051 Info.setAllowsRegister();
4054 case 'f': // Any x87 floating point stack register.
4055 // Constraint 'f' cannot be used for output operands.
4056 if (Info.ConstraintStr[0] == '=')
4058 Info.setAllowsRegister();
4066 case 'A': // edx:eax.
4067 case 't': // Top of floating point stack.
4068 case 'u': // Second from top of floating point stack.
4069 case 'q': // Any register accessible as [r]l: a, b, c, and d.
4070 case 'y': // Any MMX register.
4071 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
4072 case 'x': // Any SSE register.
4073 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0
4074 // for intermideate k reg operations).
4075 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
4076 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
4077 case 'l': // "Index" registers: any general register that can be used as an
4078 // index in a base+index memory access.
4079 Info.setAllowsRegister();
4081 // Floating point constant constraints.
4082 case 'C': // SSE floating point constant.
4083 case 'G': // x87 floating point constant.
4088 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
4089 unsigned Size) const {
4090 // Strip off constraint modifiers.
4091 while (Constraint[0] == '=' ||
4092 Constraint[0] == '+' ||
4093 Constraint[0] == '&')
4094 Constraint = Constraint.substr(1);
4096 return validateOperandSize(Constraint, Size);
4099 bool X86TargetInfo::validateInputSize(StringRef Constraint,
4100 unsigned Size) const {
4101 return validateOperandSize(Constraint, Size);
4104 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
4105 unsigned Size) const {
4106 switch (Constraint[0]) {
4109 // Registers k0-k7 (AVX512) size limit is 64 bit.
4118 if (SSELevel >= AVX512F)
4119 // 512-bit zmm registers can be used if target supports AVX512F.
4120 return Size <= 512U;
4121 else if (SSELevel >= AVX)
4122 // 256-bit ymm registers can be used if target supports AVX.
4123 return Size <= 256U;
4124 return Size <= 128U;
4126 // 'Y' is the first character for several 2-character constraints.
4127 switch (Constraint[1]) {
4130 // 'Ym' is synonymous with 'y'.
4135 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
4136 if (SSELevel >= AVX512F)
4137 return Size <= 512U;
4138 else if (SSELevel >= AVX)
4139 return Size <= 256U;
4140 return SSELevel >= SSE2 && Size <= 128U;
4149 X86TargetInfo::convertConstraint(const char *&Constraint) const {
4150 switch (*Constraint) {
4151 case 'a': return std::string("{ax}");
4152 case 'b': return std::string("{bx}");
4153 case 'c': return std::string("{cx}");
4154 case 'd': return std::string("{dx}");
4155 case 'S': return std::string("{si}");
4156 case 'D': return std::string("{di}");
4157 case 'p': // address
4158 return std::string("im");
4159 case 't': // top of floating point stack.
4160 return std::string("{st}");
4161 case 'u': // second from top of floating point stack.
4162 return std::string("{st(1)}"); // second from top of floating point stack.
4164 switch (Constraint[1]) {
4166 // Break from inner switch and fall through (copy single char),
4167 // continue parsing after copying the current constraint into
4168 // the return string.
4171 // "^" hints llvm that this is a 2 letter constraint.
4172 // "Constraint++" is used to promote the string iterator
4173 // to the next constraint.
4174 return std::string("^") + std::string(Constraint++, 2);
4178 return std::string(1, *Constraint);
4182 // X86-32 generic target
4183 class X86_32TargetInfo : public X86TargetInfo {
4185 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4186 : X86TargetInfo(Triple, Opts) {
4187 DoubleAlign = LongLongAlign = 32;
4188 LongDoubleWidth = 96;
4189 LongDoubleAlign = 32;
4190 SuitableAlign = 128;
4191 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128");
4192 SizeType = UnsignedInt;
4193 PtrDiffType = SignedInt;
4194 IntPtrType = SignedInt;
4197 // Use fpret for all types.
4198 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
4199 (1 << TargetInfo::Double) |
4200 (1 << TargetInfo::LongDouble));
4202 // x86-32 has atomics up to 8 bytes
4203 // FIXME: Check that we actually have cmpxchg8b before setting
4204 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
4205 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4207 BuiltinVaListKind getBuiltinVaListKind() const override {
4208 return TargetInfo::CharPtrBuiltinVaList;
4211 int getEHDataRegisterNumber(unsigned RegNo) const override {
4212 if (RegNo == 0) return 0;
4213 if (RegNo == 1) return 2;
4216 bool validateOperandSize(StringRef Constraint,
4217 unsigned Size) const override {
4218 switch (Constraint[0]) {
4234 return X86TargetInfo::validateOperandSize(Constraint, Size);
4236 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4237 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
4238 Builtin::FirstTSBuiltin + 1);
4242 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
4244 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4245 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {}
4247 unsigned getFloatEvalMethod() const override {
4248 unsigned Major, Minor, Micro;
4249 getTriple().getOSVersion(Major, Minor, Micro);
4250 // New NetBSD uses the default rounding mode.
4251 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
4252 return X86_32TargetInfo::getFloatEvalMethod();
4253 // NetBSD before 6.99.26 defaults to "double" rounding.
4258 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
4260 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4261 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4262 SizeType = UnsignedLong;
4263 IntPtrType = SignedLong;
4264 PtrDiffType = SignedLong;
4268 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
4270 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4271 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4272 SizeType = UnsignedLong;
4273 IntPtrType = SignedLong;
4274 PtrDiffType = SignedLong;
4278 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
4280 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4281 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4282 LongDoubleWidth = 128;
4283 LongDoubleAlign = 128;
4284 SuitableAlign = 128;
4285 MaxVectorAlign = 256;
4286 // The watchOS simulator uses the builtin bool type for Objective-C.
4287 llvm::Triple T = llvm::Triple(Triple);
4289 UseSignedCharForObjCBool = false;
4290 SizeType = UnsignedLong;
4291 IntPtrType = SignedLong;
4292 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128");
4293 HasAlignMac68kSupport = true;
4296 bool handleTargetFeatures(std::vector<std::string> &Features,
4297 DiagnosticsEngine &Diags) override {
4298 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features,
4301 // We now know the features we have: we can decide how to align vectors.
4303 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4308 // x86-32 Windows target
4309 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
4311 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4312 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4313 WCharType = UnsignedShort;
4314 DoubleAlign = LongLongAlign = 64;
4316 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4317 resetDataLayout(IsWinCOFF
4318 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
4319 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4321 void getTargetDefines(const LangOptions &Opts,
4322 MacroBuilder &Builder) const override {
4323 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4327 // x86-32 Windows Visual Studio target
4328 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
4330 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple,
4331 const TargetOptions &Opts)
4332 : WindowsX86_32TargetInfo(Triple, Opts) {
4333 LongDoubleWidth = LongDoubleAlign = 64;
4334 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4336 void getTargetDefines(const LangOptions &Opts,
4337 MacroBuilder &Builder) const override {
4338 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4339 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
4340 // The value of the following reflects processor type.
4341 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
4342 // We lost the original triple, so we use the default.
4343 Builder.defineMacro("_M_IX86", "600");
4347 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4348 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang
4349 // supports __declspec natively under -fms-extensions, but we define a no-op
4350 // __declspec macro anyway for pre-processor compatibility.
4351 if (Opts.MicrosoftExt)
4352 Builder.defineMacro("__declspec", "__declspec");
4354 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
4356 if (!Opts.MicrosoftExt) {
4357 // Provide macros for all the calling convention keywords. Provide both
4358 // single and double underscore prefixed variants. These are available on
4359 // x64 as well as x86, even though they have no effect.
4360 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
4361 for (const char *CC : CCs) {
4362 std::string GCCSpelling = "__attribute__((__";
4364 GCCSpelling += "__))";
4365 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
4366 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
4371 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4372 Builder.defineMacro("__MSVCRT__");
4373 Builder.defineMacro("__MINGW32__");
4374 addCygMingDefines(Opts, Builder);
4377 // x86-32 MinGW target
4378 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
4380 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4381 : WindowsX86_32TargetInfo(Triple, Opts) {}
4382 void getTargetDefines(const LangOptions &Opts,
4383 MacroBuilder &Builder) const override {
4384 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4385 DefineStd(Builder, "WIN32", Opts);
4386 DefineStd(Builder, "WINNT", Opts);
4387 Builder.defineMacro("_X86_");
4388 addMinGWDefines(Opts, Builder);
4392 // x86-32 Cygwin target
4393 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
4395 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4396 : X86_32TargetInfo(Triple, Opts) {
4397 WCharType = UnsignedShort;
4398 DoubleAlign = LongLongAlign = 64;
4399 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4401 void getTargetDefines(const LangOptions &Opts,
4402 MacroBuilder &Builder) const override {
4403 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4404 Builder.defineMacro("_X86_");
4405 Builder.defineMacro("__CYGWIN__");
4406 Builder.defineMacro("__CYGWIN32__");
4407 addCygMingDefines(Opts, Builder);
4408 DefineStd(Builder, "unix", Opts);
4410 Builder.defineMacro("_GNU_SOURCE");
4414 // x86-32 Haiku target
4415 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> {
4417 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4418 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4420 void getTargetDefines(const LangOptions &Opts,
4421 MacroBuilder &Builder) const override {
4422 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4423 Builder.defineMacro("__INTEL__");
4427 // X86-32 MCU target
4428 class MCUX86_32TargetInfo : public X86_32TargetInfo {
4430 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4431 : X86_32TargetInfo(Triple, Opts) {
4432 LongDoubleWidth = 64;
4433 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4434 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32");
4435 WIntType = UnsignedInt;
4438 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4439 // On MCU we support only C calling convention.
4440 return CC == CC_C ? CCCR_OK : CCCR_Warning;
4443 void getTargetDefines(const LangOptions &Opts,
4444 MacroBuilder &Builder) const override {
4445 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4446 Builder.defineMacro("__iamcu");
4447 Builder.defineMacro("__iamcu__");
4450 bool allowsLargerPreferedTypeAlignment() const override {
4456 template<typename Target>
4457 class RTEMSTargetInfo : public OSTargetInfo<Target> {
4459 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4460 MacroBuilder &Builder) const override {
4461 // RTEMS defines; list based off of gcc output
4463 Builder.defineMacro("__rtems__");
4464 Builder.defineMacro("__ELF__");
4468 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4469 : OSTargetInfo<Target>(Triple, Opts) {
4470 switch (Triple.getArch()) {
4472 case llvm::Triple::x86:
4473 // this->MCountName = ".mcount";
4475 case llvm::Triple::mips:
4476 case llvm::Triple::mipsel:
4477 case llvm::Triple::ppc:
4478 case llvm::Triple::ppc64:
4479 case llvm::Triple::ppc64le:
4480 // this->MCountName = "_mcount";
4482 case llvm::Triple::arm:
4483 // this->MCountName = "__mcount";
4489 // x86-32 RTEMS target
4490 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
4492 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4493 : X86_32TargetInfo(Triple, Opts) {
4494 SizeType = UnsignedLong;
4495 IntPtrType = SignedLong;
4496 PtrDiffType = SignedLong;
4498 void getTargetDefines(const LangOptions &Opts,
4499 MacroBuilder &Builder) const override {
4500 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4501 Builder.defineMacro("__INTEL__");
4502 Builder.defineMacro("__rtems__");
4506 // x86-64 generic target
4507 class X86_64TargetInfo : public X86TargetInfo {
4509 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4510 : X86TargetInfo(Triple, Opts) {
4511 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
4513 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4514 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
4515 LongDoubleWidth = 128;
4516 LongDoubleAlign = 128;
4517 LargeArrayMinWidth = 128;
4518 LargeArrayAlign = 128;
4519 SuitableAlign = 128;
4520 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
4521 PtrDiffType = IsX32 ? SignedInt : SignedLong;
4522 IntPtrType = IsX32 ? SignedInt : SignedLong;
4523 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
4524 Int64Type = IsX32 ? SignedLongLong : SignedLong;
4527 // Pointers are 32-bit in x32.
4528 resetDataLayout(IsX32
4529 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
4530 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
4531 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128");
4533 // Use fpret only for long double.
4534 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
4536 // Use fp2ret for _Complex long double.
4537 ComplexLongDoubleUsesFP2Ret = true;
4539 // Make __builtin_ms_va_list available.
4540 HasBuiltinMSVaList = true;
4542 // x86-64 has atomics up to 16 bytes.
4543 MaxAtomicPromoteWidth = 128;
4544 MaxAtomicInlineWidth = 128;
4546 BuiltinVaListKind getBuiltinVaListKind() const override {
4547 return TargetInfo::X86_64ABIBuiltinVaList;
4550 int getEHDataRegisterNumber(unsigned RegNo) const override {
4551 if (RegNo == 0) return 0;
4552 if (RegNo == 1) return 1;
4556 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4560 case CC_X86VectorCall:
4561 case CC_IntelOclBicc:
4562 case CC_X86_64Win64:
4563 case CC_PreserveMost:
4564 case CC_PreserveAll:
4568 return CCCR_Warning;
4572 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
4576 // for x32 we need it here explicitly
4577 bool hasInt128Type() const override { return true; }
4578 unsigned getUnwindWordWidth() const override { return 64; }
4579 unsigned getRegisterWidth() const override { return 64; }
4581 bool validateGlobalRegisterVariable(StringRef RegName,
4583 bool &HasSizeMismatch) const override {
4584 // rsp and rbp are the only 64-bit registers the x86 backend can currently
4586 if (RegName.equals("rsp") || RegName.equals("rbp")) {
4587 // Check that the register size is 64-bit.
4588 HasSizeMismatch = RegSize != 64;
4592 // Check if the register is a 32-bit register the backend can handle.
4593 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize,
4596 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4597 return llvm::makeArrayRef(BuiltinInfoX86,
4598 X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
4602 // x86-64 Windows target
4603 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
4605 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4606 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4607 WCharType = UnsignedShort;
4608 LongWidth = LongAlign = 32;
4609 DoubleAlign = LongLongAlign = 64;
4610 IntMaxType = SignedLongLong;
4611 Int64Type = SignedLongLong;
4612 SizeType = UnsignedLongLong;
4613 PtrDiffType = SignedLongLong;
4614 IntPtrType = SignedLongLong;
4617 void getTargetDefines(const LangOptions &Opts,
4618 MacroBuilder &Builder) const override {
4619 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
4620 Builder.defineMacro("_WIN64");
4623 BuiltinVaListKind getBuiltinVaListKind() const override {
4624 return TargetInfo::CharPtrBuiltinVaList;
4627 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4630 case CC_X86ThisCall:
4631 case CC_X86FastCall:
4634 case CC_X86VectorCall:
4635 case CC_IntelOclBicc:
4641 return CCCR_Warning;
4646 // x86-64 Windows Visual Studio target
4647 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
4649 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple,
4650 const TargetOptions &Opts)
4651 : WindowsX86_64TargetInfo(Triple, Opts) {
4652 LongDoubleWidth = LongDoubleAlign = 64;
4653 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4655 void getTargetDefines(const LangOptions &Opts,
4656 MacroBuilder &Builder) const override {
4657 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4658 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
4659 Builder.defineMacro("_M_X64", "100");
4660 Builder.defineMacro("_M_AMD64", "100");
4664 // x86-64 MinGW target
4665 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
4667 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4668 : WindowsX86_64TargetInfo(Triple, Opts) {
4669 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
4670 // with x86 FP ops. Weird.
4671 LongDoubleWidth = LongDoubleAlign = 128;
4672 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
4675 void getTargetDefines(const LangOptions &Opts,
4676 MacroBuilder &Builder) const override {
4677 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4678 DefineStd(Builder, "WIN64", Opts);
4679 Builder.defineMacro("__MINGW64__");
4680 addMinGWDefines(Opts, Builder);
4682 // GCC defines this macro when it is using __gxx_personality_seh0.
4683 if (!Opts.SjLjExceptions)
4684 Builder.defineMacro("__SEH__");
4688 // x86-64 Cygwin target
4689 class CygwinX86_64TargetInfo : public X86_64TargetInfo {
4691 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4692 : X86_64TargetInfo(Triple, Opts) {
4693 TLSSupported = false;
4694 WCharType = UnsignedShort;
4696 void getTargetDefines(const LangOptions &Opts,
4697 MacroBuilder &Builder) const override {
4698 X86_64TargetInfo::getTargetDefines(Opts, Builder);
4699 Builder.defineMacro("__x86_64__");
4700 Builder.defineMacro("__CYGWIN__");
4701 Builder.defineMacro("__CYGWIN64__");
4702 addCygMingDefines(Opts, Builder);
4703 DefineStd(Builder, "unix", Opts);
4705 Builder.defineMacro("_GNU_SOURCE");
4707 // GCC defines this macro when it is using __gxx_personality_seh0.
4708 if (!Opts.SjLjExceptions)
4709 Builder.defineMacro("__SEH__");
4713 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
4715 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4716 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4717 Int64Type = SignedLongLong;
4718 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
4719 llvm::Triple T = llvm::Triple(Triple);
4721 UseSignedCharForObjCBool = false;
4722 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128");
4725 bool handleTargetFeatures(std::vector<std::string> &Features,
4726 DiagnosticsEngine &Diags) override {
4727 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features,
4730 // We now know the features we have: we can decide how to align vectors.
4732 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4737 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
4739 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4740 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4741 IntMaxType = SignedLongLong;
4742 Int64Type = SignedLongLong;
4746 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
4748 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4749 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4750 IntMaxType = SignedLongLong;
4751 Int64Type = SignedLongLong;
4755 class ARMTargetInfo : public TargetInfo {
4756 // Possible FPU choices.
4765 // Possible HWDiv features.
4767 HWDivThumb = (1 << 0),
4771 static bool FPUModeIsVFP(FPUMode Mode) {
4772 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
4775 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4776 static const char * const GCCRegNames[];
4778 std::string ABI, CPU;
4780 StringRef CPUProfile;
4790 unsigned ArchKind = llvm::ARM::AK_ARMV4T;
4791 unsigned ArchProfile;
4792 unsigned ArchVersion;
4796 unsigned IsAAPCS : 1;
4799 // Initialized via features.
4800 unsigned SoftFloat : 1;
4801 unsigned SoftFloatABI : 1;
4804 unsigned Crypto : 1;
4806 unsigned Unaligned : 1;
4809 LDREX_B = (1 << 0), /// byte (8-bit)
4810 LDREX_H = (1 << 1), /// half (16-bit)
4811 LDREX_W = (1 << 2), /// word (32-bit)
4812 LDREX_D = (1 << 3), /// double (64-bit)
4817 // ACLE 6.5.1 Hardware floating point
4819 HW_FP_HP = (1 << 1), /// half (16-bit)
4820 HW_FP_SP = (1 << 2), /// single (32-bit)
4821 HW_FP_DP = (1 << 3), /// double (64-bit)
4825 static const Builtin::Info BuiltinInfo[];
4827 void setABIAAPCS() {
4830 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4831 const llvm::Triple &T = getTriple();
4833 // size_t is unsigned long on MachO-derived environments, NetBSD,
4834 // OpenBSD and Bitrig.
4835 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
4836 T.getOS() == llvm::Triple::OpenBSD ||
4837 T.getOS() == llvm::Triple::Bitrig)
4838 SizeType = UnsignedLong;
4840 SizeType = UnsignedInt;
4842 switch (T.getOS()) {
4843 case llvm::Triple::NetBSD:
4844 case llvm::Triple::OpenBSD:
4845 WCharType = SignedInt;
4847 case llvm::Triple::Win32:
4848 WCharType = UnsignedShort;
4850 case llvm::Triple::Linux:
4852 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
4853 WCharType = UnsignedInt;
4857 UseBitFieldTypeAlignment = true;
4859 ZeroLengthBitfieldBoundary = 0;
4861 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
4862 // so set preferred for small types to 32.
4863 if (T.isOSBinFormatMachO()) {
4864 resetDataLayout(BigEndian
4865 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4866 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
4867 } else if (T.isOSWindows()) {
4868 assert(!BigEndian && "Windows on ARM does not support big endian");
4877 } else if (T.isOSNaCl()) {
4878 assert(!BigEndian && "NaCl on ARM does not support big endian");
4879 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128");
4881 resetDataLayout(BigEndian
4882 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4883 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
4886 // FIXME: Enumerated types are variable width in straight AAPCS.
4889 void setABIAPCS(bool IsAAPCS16) {
4890 const llvm::Triple &T = getTriple();
4895 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4897 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
4899 // size_t is unsigned int on FreeBSD.
4900 if (T.getOS() == llvm::Triple::FreeBSD)
4901 SizeType = UnsignedInt;
4903 SizeType = UnsignedLong;
4905 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
4906 WCharType = SignedInt;
4908 // Do not respect the alignment of bit-field types when laying out
4909 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
4910 UseBitFieldTypeAlignment = false;
4912 /// gcc forces the alignment to 4 bytes, regardless of the type of the
4913 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
4915 ZeroLengthBitfieldBoundary = 32;
4917 if (T.isOSBinFormatMachO() && IsAAPCS16) {
4918 assert(!BigEndian && "AAPCS16 does not support big-endian");
4919 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128");
4920 } else if (T.isOSBinFormatMachO())
4923 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4924 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
4928 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4929 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
4931 // FIXME: Override "preferred align" for double and long long.
4934 void setArchInfo() {
4935 StringRef ArchName = getTriple().getArchName();
4937 ArchISA = llvm::ARM::parseArchISA(ArchName);
4938 CPU = llvm::ARM::getDefaultCPU(ArchName);
4939 unsigned AK = llvm::ARM::parseArch(ArchName);
4940 if (AK != llvm::ARM::AK_INVALID)
4942 setArchInfo(ArchKind);
4945 void setArchInfo(unsigned Kind) {
4948 // cache TargetParser info
4950 SubArch = llvm::ARM::getSubArch(ArchKind);
4951 ArchProfile = llvm::ARM::parseArchProfile(SubArch);
4952 ArchVersion = llvm::ARM::parseArchVersion(SubArch);
4954 // cache CPU related strings
4955 CPUAttr = getCPUAttr();
4956 CPUProfile = getCPUProfile();
4960 // when triple does not specify a sub arch,
4961 // then we are not using inline atomics
4962 bool ShouldUseInlineAtomic =
4963 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) ||
4964 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
4965 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4966 if (ArchProfile == llvm::ARM::PK_M) {
4967 MaxAtomicPromoteWidth = 32;
4968 if (ShouldUseInlineAtomic)
4969 MaxAtomicInlineWidth = 32;
4972 MaxAtomicPromoteWidth = 64;
4973 if (ShouldUseInlineAtomic)
4974 MaxAtomicInlineWidth = 64;
4978 bool isThumb() const {
4979 return (ArchISA == llvm::ARM::IK_THUMB);
4982 bool supportsThumb() const {
4983 return CPUAttr.count('T') || ArchVersion >= 6;
4986 bool supportsThumb2() const {
4987 return CPUAttr.equals("6T2") ||
4988 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE"));
4991 StringRef getCPUAttr() const {
4992 // For most sub-arches, the build attribute CPU name is enough.
4993 // For Cortex variants, it's slightly different.
4996 return llvm::ARM::getCPUAttr(ArchKind);
4997 case llvm::ARM::AK_ARMV6M:
4999 case llvm::ARM::AK_ARMV7S:
5001 case llvm::ARM::AK_ARMV7A:
5003 case llvm::ARM::AK_ARMV7R:
5005 case llvm::ARM::AK_ARMV7M:
5007 case llvm::ARM::AK_ARMV7EM:
5009 case llvm::ARM::AK_ARMV8A:
5011 case llvm::ARM::AK_ARMV8_1A:
5013 case llvm::ARM::AK_ARMV8_2A:
5015 case llvm::ARM::AK_ARMV8MBaseline:
5017 case llvm::ARM::AK_ARMV8MMainline:
5019 case llvm::ARM::AK_ARMV8R:
5024 StringRef getCPUProfile() const {
5025 switch(ArchProfile) {
5026 case llvm::ARM::PK_A:
5028 case llvm::ARM::PK_R:
5030 case llvm::ARM::PK_M:
5038 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5039 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0),
5042 switch (getTriple().getOS()) {
5043 case llvm::Triple::NetBSD:
5044 case llvm::Triple::OpenBSD:
5045 PtrDiffType = SignedLong;
5048 PtrDiffType = SignedInt;
5052 // Cache arch related info.
5055 // {} in inline assembly are neon specifiers, not assembly variant
5057 NoAsmVariants = true;
5059 // FIXME: This duplicates code from the driver that sets the -target-abi
5060 // option - this code is used if -target-abi isn't passed and should
5061 // be unified in some way.
5062 if (Triple.isOSBinFormatMachO()) {
5063 // The backend is hardwired to assume AAPCS for M-class processors, ensure
5064 // the frontend matches that.
5065 if (Triple.getEnvironment() == llvm::Triple::EABI ||
5066 Triple.getOS() == llvm::Triple::UnknownOS ||
5067 ArchProfile == llvm::ARM::PK_M) {
5069 } else if (Triple.isWatchABI()) {
5074 } else if (Triple.isOSWindows()) {
5075 // FIXME: this is invalid for WindowsCE
5078 // Select the default based on the platform.
5079 switch (Triple.getEnvironment()) {
5080 case llvm::Triple::Android:
5081 case llvm::Triple::GNUEABI:
5082 case llvm::Triple::GNUEABIHF:
5083 case llvm::Triple::MuslEABI:
5084 case llvm::Triple::MuslEABIHF:
5085 setABI("aapcs-linux");
5087 case llvm::Triple::EABIHF:
5088 case llvm::Triple::EABI:
5091 case llvm::Triple::GNU:
5095 if (Triple.getOS() == llvm::Triple::NetBSD)
5103 // ARM targets default to using the ARM C++ ABI.
5104 TheCXXABI.set(TargetCXXABI::GenericARM);
5106 // ARM has atomics up to 8 bytes
5109 // Do force alignment of members that follow zero length bitfields. If
5110 // the alignment of the zero-length bitfield is greater than the member
5111 // that follows it, `bar', `bar' will be aligned as the type of the
5112 // zero length bitfield.
5113 UseZeroLengthBitfieldAlignment = true;
5115 if (Triple.getOS() == llvm::Triple::Linux ||
5116 Triple.getOS() == llvm::Triple::UnknownOS)
5118 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount";
5121 StringRef getABI() const override { return ABI; }
5123 bool setABI(const std::string &Name) override {
5126 // The defaults (above) are for AAPCS, check if we need to change them.
5128 // FIXME: We need support for -meabi... we could just mangle it into the
5130 if (Name == "apcs-gnu" || Name == "aapcs16") {
5131 setABIAPCS(Name == "aapcs16");
5134 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
5141 // FIXME: This should be based on Arch attributes, not CPU names.
5143 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
5145 const std::vector<std::string> &FeaturesVec) const override {
5147 std::vector<StringRef> TargetFeatures;
5148 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName());
5150 // get default FPU features
5151 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
5152 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
5154 // get default Extension features
5155 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
5156 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
5158 for (auto Feature : TargetFeatures)
5159 if (Feature[0] == '+')
5160 Features[Feature.drop_front(1)] = true;
5162 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
5165 bool handleTargetFeatures(std::vector<std::string> &Features,
5166 DiagnosticsEngine &Diags) override {
5172 SoftFloat = SoftFloatABI = false;
5175 // This does not diagnose illegal cases like having both
5176 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
5177 uint32_t HW_FP_remove = 0;
5178 for (const auto &Feature : Features) {
5179 if (Feature == "+soft-float") {
5181 } else if (Feature == "+soft-float-abi") {
5182 SoftFloatABI = true;
5183 } else if (Feature == "+vfp2") {
5185 HW_FP |= HW_FP_SP | HW_FP_DP;
5186 } else if (Feature == "+vfp3") {
5188 HW_FP |= HW_FP_SP | HW_FP_DP;
5189 } else if (Feature == "+vfp4") {
5191 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
5192 } else if (Feature == "+fp-armv8") {
5194 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
5195 } else if (Feature == "+neon") {
5197 HW_FP |= HW_FP_SP | HW_FP_DP;
5198 } else if (Feature == "+hwdiv") {
5199 HWDiv |= HWDivThumb;
5200 } else if (Feature == "+hwdiv-arm") {
5202 } else if (Feature == "+crc") {
5204 } else if (Feature == "+crypto") {
5206 } else if (Feature == "+dsp") {
5208 } else if (Feature == "+fp-only-sp") {
5209 HW_FP_remove |= HW_FP_DP;
5210 } else if (Feature == "+strict-align") {
5212 } else if (Feature == "+fp16") {
5216 HW_FP &= ~HW_FP_remove;
5218 switch (ArchVersion) {
5220 if (ArchProfile == llvm::ARM::PK_M)
5222 else if (ArchKind == llvm::ARM::AK_ARMV6K)
5223 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5228 if (ArchProfile == llvm::ARM::PK_M)
5229 LDREX = LDREX_W | LDREX_H | LDREX_B ;
5231 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5234 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5237 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
5238 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
5242 if (FPMath == FP_Neon)
5243 Features.push_back("+neonfp");
5244 else if (FPMath == FP_VFP)
5245 Features.push_back("-neonfp");
5247 // Remove front-end specific options which the backend handles differently.
5249 std::find(Features.begin(), Features.end(), "+soft-float-abi");
5250 if (Feature != Features.end())
5251 Features.erase(Feature);
5256 bool hasFeature(StringRef Feature) const override {
5257 return llvm::StringSwitch<bool>(Feature)
5259 .Case("aarch32", true)
5260 .Case("softfloat", SoftFloat)
5261 .Case("thumb", isThumb())
5262 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
5263 .Case("hwdiv", HWDiv & HWDivThumb)
5264 .Case("hwdiv-arm", HWDiv & HWDivARM)
5268 bool setCPU(const std::string &Name) override {
5269 if (Name != "generic")
5270 setArchInfo(llvm::ARM::parseCPUArch(Name));
5272 if (ArchKind == llvm::ARM::AK_INVALID)
5279 bool setFPMath(StringRef Name) override;
5281 void getTargetDefines(const LangOptions &Opts,
5282 MacroBuilder &Builder) const override {
5283 // Target identification.
5284 Builder.defineMacro("__arm");
5285 Builder.defineMacro("__arm__");
5286 // For bare-metal none-eabi.
5287 if (getTriple().getOS() == llvm::Triple::UnknownOS &&
5288 getTriple().getEnvironment() == llvm::Triple::EABI)
5289 Builder.defineMacro("__ELF__");
5291 // Target properties.
5292 Builder.defineMacro("__REGISTER_PREFIX__", "");
5294 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
5295 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
5296 if (getTriple().isWatchABI())
5297 Builder.defineMacro("__ARM_ARCH_7K__", "2");
5299 if (!CPUAttr.empty())
5300 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
5302 // ACLE 6.4.1 ARM/Thumb instruction set architecture
5303 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
5304 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
5306 if (ArchVersion >= 8) {
5307 // ACLE 6.5.7 Crypto Extension
5309 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
5310 // ACLE 6.5.8 CRC32 Extension
5312 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
5313 // ACLE 6.5.10 Numeric Maximum and Minimum
5314 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
5315 // ACLE 6.5.9 Directed Rounding
5316 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
5319 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
5320 // is not defined for the M-profile.
5321 // NOTE that the default profile is assumed to be 'A'
5322 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M)
5323 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
5325 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original
5326 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the
5327 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all
5328 // v7 and v8 architectures excluding v8-M Baseline.
5329 if (supportsThumb2())
5330 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
5331 else if (supportsThumb())
5332 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
5334 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
5335 // instruction set such as ARM or Thumb.
5336 Builder.defineMacro("__ARM_32BIT_STATE", "1");
5338 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
5340 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
5341 if (!CPUProfile.empty())
5342 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
5344 // ACLE 6.4.3 Unaligned access supported in hardware
5346 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
5348 // ACLE 6.4.4 LDREX/STREX
5350 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX));
5353 if (ArchVersion == 5 ||
5354 (ArchVersion == 6 && CPUProfile != "M") ||
5356 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
5358 // ACLE 6.5.1 Hardware Floating Point
5360 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
5363 Builder.defineMacro("__ARM_ACLE", "200");
5365 // FP16 support (we currently only support IEEE format).
5366 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
5367 Builder.defineMacro("__ARM_FP16_ARGS", "1");
5369 // ACLE 6.5.3 Fused multiply-accumulate (FMA)
5370 if (ArchVersion >= 7 && (FPU & VFP4FPU))
5371 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
5373 // Subtarget options.
5375 // FIXME: It's more complicated than this and we don't really support
5377 // Windows on ARM does not "support" interworking
5378 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows())
5379 Builder.defineMacro("__THUMB_INTERWORK__");
5381 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
5382 // Embedded targets on Darwin follow AAPCS, but not EABI.
5383 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
5384 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows())
5385 Builder.defineMacro("__ARM_EABI__");
5386 Builder.defineMacro("__ARM_PCS", "1");
5389 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" ||
5391 Builder.defineMacro("__ARM_PCS_VFP", "1");
5394 Builder.defineMacro("__SOFTFP__");
5396 if (ArchKind == llvm::ARM::AK_XSCALE)
5397 Builder.defineMacro("__XSCALE__");
5400 Builder.defineMacro("__THUMBEL__");
5401 Builder.defineMacro("__thumb__");
5402 if (supportsThumb2())
5403 Builder.defineMacro("__thumb2__");
5406 // ACLE 6.4.9 32-bit SIMD instructions
5407 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
5408 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
5410 // ACLE 6.4.10 Hardware Integer Divide
5411 if (((HWDiv & HWDivThumb) && isThumb()) ||
5412 ((HWDiv & HWDivARM) && !isThumb())) {
5413 Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
5414 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
5417 // Note, this is always on in gcc, even though it doesn't make sense.
5418 Builder.defineMacro("__APCS_32__");
5420 if (FPUModeIsVFP((FPUMode) FPU)) {
5421 Builder.defineMacro("__VFP_FP__");
5423 Builder.defineMacro("__ARM_VFPV2__");
5425 Builder.defineMacro("__ARM_VFPV3__");
5427 Builder.defineMacro("__ARM_VFPV4__");
5429 Builder.defineMacro("__ARM_FPV5__");
5432 // This only gets set when Neon instructions are actually available, unlike
5433 // the VFP define, hence the soft float and arch check. This is subtly
5434 // different from gcc, we follow the intent which was that it should be set
5435 // when Neon instructions are actually available.
5436 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
5437 Builder.defineMacro("__ARM_NEON", "1");
5438 Builder.defineMacro("__ARM_NEON__");
5439 // current AArch32 NEON implementations do not support double-precision
5440 // floating-point even when it is present in VFP.
5441 Builder.defineMacro("__ARM_NEON_FP",
5442 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP));
5445 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
5446 Opts.ShortWChar ? "2" : "4");
5448 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5449 Opts.ShortEnums ? "1" : "4");
5451 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") {
5452 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
5453 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
5454 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
5455 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
5458 // ACLE 6.4.7 DSP instructions
5460 Builder.defineMacro("__ARM_FEATURE_DSP", "1");
5463 // ACLE 6.4.8 Saturation instructions
5465 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) {
5466 Builder.defineMacro("__ARM_FEATURE_SAT", "1");
5470 // ACLE 6.4.6 Q (saturation) flag
5472 Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
5474 if (Opts.UnsafeFPMath)
5475 Builder.defineMacro("__ARM_FP_FAST", "1");
5477 if (ArchKind == llvm::ARM::AK_ARMV8_1A)
5478 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
5481 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5482 return llvm::makeArrayRef(BuiltinInfo,
5483 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin);
5485 bool isCLZForZeroUndef() const override { return false; }
5486 BuiltinVaListKind getBuiltinVaListKind() const override {
5488 ? AAPCSABIBuiltinVaList
5489 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList
5490 : TargetInfo::VoidPtrBuiltinVaList);
5492 ArrayRef<const char *> getGCCRegNames() const override;
5493 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5494 bool validateAsmConstraint(const char *&Name,
5495 TargetInfo::ConstraintInfo &Info) const override {
5500 case 't': // VFP Floating point register single precision
5501 case 'w': // VFP Floating point register double precision
5502 Info.setAllowsRegister();
5511 case 'Q': // A memory address that is a single base register.
5512 Info.setAllowsMemory();
5514 case 'U': // a memory reference...
5516 case 'q': // ...ARMV4 ldrsb
5517 case 'v': // ...VFP load/store (reg+constant offset)
5518 case 'y': // ...iWMMXt load/store
5519 case 't': // address valid for load/store opaque types wider
5521 case 'n': // valid address for Neon doubleword vector load/store
5522 case 'm': // valid address for Neon element and structure load/store
5523 case 's': // valid address for non-offset loads/stores of quad-word
5524 // values in four ARM registers
5525 Info.setAllowsMemory();
5532 std::string convertConstraint(const char *&Constraint) const override {
5534 switch (*Constraint) {
5535 case 'U': // Two-character constraint; add "^" hint for later parsing.
5536 R = std::string("^") + std::string(Constraint, 2);
5539 case 'p': // 'p' should be translated to 'r' by default.
5540 R = std::string("r");
5543 return std::string(1, *Constraint);
5548 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5549 std::string &SuggestedModifier) const override {
5550 bool isOutput = (Constraint[0] == '=');
5551 bool isInOut = (Constraint[0] == '+');
5553 // Strip off constraint modifiers.
5554 while (Constraint[0] == '=' ||
5555 Constraint[0] == '+' ||
5556 Constraint[0] == '&')
5557 Constraint = Constraint.substr(1);
5559 switch (Constraint[0]) {
5564 return (isInOut || isOutput || Size <= 64);
5566 // A register of size 32 cannot fit a vector type.
5574 const char *getClobbers() const override {
5575 // FIXME: Is this really right?
5579 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5586 return CCCR_Warning;
5590 int getEHDataRegisterNumber(unsigned RegNo) const override {
5591 if (RegNo == 0) return 0;
5592 if (RegNo == 1) return 1;
5596 bool hasSjLjLowering() const override {
5601 bool ARMTargetInfo::setFPMath(StringRef Name) {
5602 if (Name == "neon") {
5605 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
5613 const char * const ARMTargetInfo::GCCRegNames[] = {
5614 // Integer registers
5615 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5616 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
5619 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
5620 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
5621 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
5622 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5625 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
5626 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
5627 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
5628 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5631 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
5632 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
5635 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
5636 return llvm::makeArrayRef(GCCRegNames);
5639 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
5649 { { "v6", "rfp" }, "r9" },
5650 { { "sl" }, "r10" },
5651 { { "fp" }, "r11" },
5652 { { "ip" }, "r12" },
5653 { { "r13" }, "sp" },
5654 { { "r14" }, "lr" },
5655 { { "r15" }, "pc" },
5656 // The S, D and Q registers overlap, but aren't really aliases; we
5657 // don't want to substitute one of these for a different-sized one.
5660 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
5661 return llvm::makeArrayRef(GCCRegAliases);
5664 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
5665 #define BUILTIN(ID, TYPE, ATTRS) \
5666 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5667 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5668 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5669 #include "clang/Basic/BuiltinsNEON.def"
5671 #define BUILTIN(ID, TYPE, ATTRS) \
5672 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5673 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \
5674 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr },
5675 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5676 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5677 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
5678 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
5679 #include "clang/Basic/BuiltinsARM.def"
5682 class ARMleTargetInfo : public ARMTargetInfo {
5684 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5685 : ARMTargetInfo(Triple, Opts) {}
5686 void getTargetDefines(const LangOptions &Opts,
5687 MacroBuilder &Builder) const override {
5688 Builder.defineMacro("__ARMEL__");
5689 ARMTargetInfo::getTargetDefines(Opts, Builder);
5693 class ARMbeTargetInfo : public ARMTargetInfo {
5695 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5696 : ARMTargetInfo(Triple, Opts) {}
5697 void getTargetDefines(const LangOptions &Opts,
5698 MacroBuilder &Builder) const override {
5699 Builder.defineMacro("__ARMEB__");
5700 Builder.defineMacro("__ARM_BIG_ENDIAN");
5701 ARMTargetInfo::getTargetDefines(Opts, Builder);
5705 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
5706 const llvm::Triple Triple;
5708 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5709 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
5710 WCharType = UnsignedShort;
5711 SizeType = UnsignedInt;
5713 void getVisualStudioDefines(const LangOptions &Opts,
5714 MacroBuilder &Builder) const {
5715 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
5717 // FIXME: this is invalid for WindowsCE
5718 Builder.defineMacro("_M_ARM_NT", "1");
5719 Builder.defineMacro("_M_ARMT", "_M_ARM");
5720 Builder.defineMacro("_M_THUMB", "_M_ARM");
5722 assert((Triple.getArch() == llvm::Triple::arm ||
5723 Triple.getArch() == llvm::Triple::thumb) &&
5724 "invalid architecture for Windows ARM target info");
5725 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
5726 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
5728 // TODO map the complete set of values
5729 // 31: VFPv3 40: VFPv4
5730 Builder.defineMacro("_M_ARM_FP", "31");
5732 BuiltinVaListKind getBuiltinVaListKind() const override {
5733 return TargetInfo::CharPtrBuiltinVaList;
5735 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5738 case CC_X86ThisCall:
5739 case CC_X86FastCall:
5740 case CC_X86VectorCall:
5745 return CCCR_Warning;
5750 // Windows ARM + Itanium C++ ABI Target
5751 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
5753 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple,
5754 const TargetOptions &Opts)
5755 : WindowsARMTargetInfo(Triple, Opts) {
5756 TheCXXABI.set(TargetCXXABI::GenericARM);
5759 void getTargetDefines(const LangOptions &Opts,
5760 MacroBuilder &Builder) const override {
5761 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5763 if (Opts.MSVCCompat)
5764 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5768 // Windows ARM, MS (C++) ABI
5769 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
5771 MicrosoftARMleTargetInfo(const llvm::Triple &Triple,
5772 const TargetOptions &Opts)
5773 : WindowsARMTargetInfo(Triple, Opts) {
5774 TheCXXABI.set(TargetCXXABI::Microsoft);
5777 void getTargetDefines(const LangOptions &Opts,
5778 MacroBuilder &Builder) const override {
5779 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5780 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5785 class MinGWARMTargetInfo : public WindowsARMTargetInfo {
5787 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5788 : WindowsARMTargetInfo(Triple, Opts) {
5789 TheCXXABI.set(TargetCXXABI::GenericARM);
5792 void getTargetDefines(const LangOptions &Opts,
5793 MacroBuilder &Builder) const override {
5794 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5795 DefineStd(Builder, "WIN32", Opts);
5796 DefineStd(Builder, "WINNT", Opts);
5797 Builder.defineMacro("_ARM_");
5798 addMinGWDefines(Opts, Builder);
5802 // ARM Cygwin target
5803 class CygwinARMTargetInfo : public ARMleTargetInfo {
5805 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5806 : ARMleTargetInfo(Triple, Opts) {
5807 TLSSupported = false;
5808 WCharType = UnsignedShort;
5809 DoubleAlign = LongLongAlign = 64;
5810 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
5812 void getTargetDefines(const LangOptions &Opts,
5813 MacroBuilder &Builder) const override {
5814 ARMleTargetInfo::getTargetDefines(Opts, Builder);
5815 Builder.defineMacro("_ARM_");
5816 Builder.defineMacro("__CYGWIN__");
5817 Builder.defineMacro("__CYGWIN32__");
5818 DefineStd(Builder, "unix", Opts);
5820 Builder.defineMacro("_GNU_SOURCE");
5824 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> {
5826 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5827 MacroBuilder &Builder) const override {
5828 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5832 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5833 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
5834 HasAlignMac68kSupport = true;
5835 // iOS always has 64-bit atomic instructions.
5836 // FIXME: This should be based off of the target features in
5838 MaxAtomicInlineWidth = 64;
5840 if (Triple.isWatchABI()) {
5841 // Darwin on iOS uses a variant of the ARM C++ ABI.
5842 TheCXXABI.set(TargetCXXABI::WatchOS);
5844 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that
5845 // size_t is long, it's a bit weird for it to be int.
5846 PtrDiffType = SignedLong;
5848 // BOOL should be a real boolean on the new ABI
5849 UseSignedCharForObjCBool = false;
5851 TheCXXABI.set(TargetCXXABI::iOS);
5855 class AArch64TargetInfo : public TargetInfo {
5856 virtual void setDataLayout() = 0;
5857 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5858 static const char *const GCCRegNames[];
5871 static const Builtin::Info BuiltinInfo[];
5876 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5877 : TargetInfo(Triple), ABI("aapcs") {
5878 if (getTriple().getOS() == llvm::Triple::NetBSD) {
5879 WCharType = SignedInt;
5881 // NetBSD apparently prefers consistency across ARM targets to consistency
5882 // across 64-bit targets.
5883 Int64Type = SignedLongLong;
5884 IntMaxType = SignedLongLong;
5886 WCharType = UnsignedInt;
5887 Int64Type = SignedLong;
5888 IntMaxType = SignedLong;
5891 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5892 MaxVectorAlign = 128;
5893 MaxAtomicInlineWidth = 128;
5894 MaxAtomicPromoteWidth = 128;
5896 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
5897 LongDoubleFormat = &llvm::APFloat::IEEEquad();
5899 // {} in inline assembly are neon specifiers, not assembly variant
5901 NoAsmVariants = true;
5903 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
5904 // contributes to the alignment of the containing aggregate in the same way
5905 // a plain (non bit-field) member of that type would, without exception for
5906 // zero-sized or anonymous bit-fields."
5907 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
5908 UseZeroLengthBitfieldAlignment = true;
5910 // AArch64 targets default to using the ARM C++ ABI.
5911 TheCXXABI.set(TargetCXXABI::GenericAArch64);
5913 if (Triple.getOS() == llvm::Triple::Linux ||
5914 Triple.getOS() == llvm::Triple::UnknownOS)
5915 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount";
5918 StringRef getABI() const override { return ABI; }
5919 bool setABI(const std::string &Name) override {
5920 if (Name != "aapcs" && Name != "darwinpcs")
5927 bool setCPU(const std::string &Name) override {
5928 return Name == "generic" ||
5929 llvm::AArch64::parseCPUArch(Name) !=
5930 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID);
5933 void getTargetDefines(const LangOptions &Opts,
5934 MacroBuilder &Builder) const override {
5935 // Target identification.
5936 Builder.defineMacro("__aarch64__");
5938 // Target properties.
5939 Builder.defineMacro("_LP64");
5940 Builder.defineMacro("__LP64__");
5942 // ACLE predefines. Many can only have one possible value on v8 AArch64.
5943 Builder.defineMacro("__ARM_ACLE", "200");
5944 Builder.defineMacro("__ARM_ARCH", "8");
5945 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
5947 Builder.defineMacro("__ARM_64BIT_STATE", "1");
5948 Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
5949 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
5951 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
5952 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
5953 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
5954 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
5955 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
5956 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
5957 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
5959 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
5961 // 0xe implies support for half, single and double precision operations.
5962 Builder.defineMacro("__ARM_FP", "0xE");
5964 // PCS specifies this for SysV variants, which is all we support. Other ABIs
5965 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
5966 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
5967 Builder.defineMacro("__ARM_FP16_ARGS", "1");
5969 if (Opts.UnsafeFPMath)
5970 Builder.defineMacro("__ARM_FP_FAST", "1");
5972 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
5974 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5975 Opts.ShortEnums ? "1" : "4");
5977 if (FPU == NeonMode) {
5978 Builder.defineMacro("__ARM_NEON", "1");
5979 // 64-bit NEON supports half, single and double precision operations.
5980 Builder.defineMacro("__ARM_NEON_FP", "0xE");
5984 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
5987 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
5990 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
5993 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
5995 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
5996 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
5997 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
5998 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
5999 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
6002 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6003 return llvm::makeArrayRef(BuiltinInfo,
6004 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin);
6007 bool hasFeature(StringRef Feature) const override {
6008 return Feature == "aarch64" ||
6009 Feature == "arm64" ||
6011 (Feature == "neon" && FPU == NeonMode);
6014 bool handleTargetFeatures(std::vector<std::string> &Features,
6015 DiagnosticsEngine &Diags) override {
6022 for (const auto &Feature : Features) {
6023 if (Feature == "+neon")
6025 if (Feature == "+crc")
6027 if (Feature == "+crypto")
6029 if (Feature == "+strict-align")
6031 if (Feature == "+v8.1a")
6040 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6044 case CC_PreserveMost:
6045 case CC_PreserveAll:
6048 return CCCR_Warning;
6052 bool isCLZForZeroUndef() const override { return false; }
6054 BuiltinVaListKind getBuiltinVaListKind() const override {
6055 return TargetInfo::AArch64ABIBuiltinVaList;
6058 ArrayRef<const char *> getGCCRegNames() const override;
6059 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6061 bool validateAsmConstraint(const char *&Name,
6062 TargetInfo::ConstraintInfo &Info) const override {
6066 case 'w': // Floating point and SIMD registers (V0-V31)
6067 Info.setAllowsRegister();
6069 case 'I': // Constant that can be used with an ADD instruction
6070 case 'J': // Constant that can be used with a SUB instruction
6071 case 'K': // Constant that can be used with a 32-bit logical instruction
6072 case 'L': // Constant that can be used with a 64-bit logical instruction
6073 case 'M': // Constant that can be used as a 32-bit MOV immediate
6074 case 'N': // Constant that can be used as a 64-bit MOV immediate
6075 case 'Y': // Floating point constant zero
6076 case 'Z': // Integer constant zero
6078 case 'Q': // A memory reference with base register and no offset
6079 Info.setAllowsMemory();
6081 case 'S': // A symbolic address
6082 Info.setAllowsRegister();
6085 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
6086 // Utf: A memory address suitable for ldp/stp in TF mode.
6087 // Usa: An absolute symbolic address.
6088 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
6089 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
6090 case 'z': // Zero register, wzr or xzr
6091 Info.setAllowsRegister();
6093 case 'x': // Floating point and SIMD registers (V0-V15)
6094 Info.setAllowsRegister();
6101 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
6102 std::string &SuggestedModifier) const override {
6103 // Strip off constraint modifiers.
6104 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
6105 Constraint = Constraint.substr(1);
6107 switch (Constraint[0]) {
6115 // For now assume that the person knows what they're
6116 // doing with the modifier.
6119 // By default an 'r' constraint will be in the 'x'
6124 SuggestedModifier = "w";
6131 const char *getClobbers() const override { return ""; }
6133 int getEHDataRegisterNumber(unsigned RegNo) const override {
6142 const char *const AArch64TargetInfo::GCCRegNames[] = {
6143 // 32-bit Integer registers
6144 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
6145 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
6146 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
6148 // 64-bit Integer registers
6149 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
6150 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
6151 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
6153 // 32-bit floating point regsisters
6154 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
6155 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
6156 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
6158 // 64-bit floating point regsisters
6159 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
6160 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
6161 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
6164 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
6165 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
6166 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
6169 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
6170 return llvm::makeArrayRef(GCCRegNames);
6173 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
6174 { { "w31" }, "wsp" },
6175 { { "x29" }, "fp" },
6176 { { "x30" }, "lr" },
6177 { { "x31" }, "sp" },
6178 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
6179 // don't want to substitute one of these for a different-sized one.
6182 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
6183 return llvm::makeArrayRef(GCCRegAliases);
6186 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
6187 #define BUILTIN(ID, TYPE, ATTRS) \
6188 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6189 #include "clang/Basic/BuiltinsNEON.def"
6191 #define BUILTIN(ID, TYPE, ATTRS) \
6192 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6193 #include "clang/Basic/BuiltinsAArch64.def"
6196 class AArch64leTargetInfo : public AArch64TargetInfo {
6197 void setDataLayout() override {
6198 if (getTriple().isOSBinFormatMachO())
6199 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128");
6201 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6205 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6206 : AArch64TargetInfo(Triple, Opts) {
6208 void getTargetDefines(const LangOptions &Opts,
6209 MacroBuilder &Builder) const override {
6210 Builder.defineMacro("__AARCH64EL__");
6211 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6215 class AArch64beTargetInfo : public AArch64TargetInfo {
6216 void setDataLayout() override {
6217 assert(!getTriple().isOSBinFormatMachO());
6218 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6222 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6223 : AArch64TargetInfo(Triple, Opts) {}
6224 void getTargetDefines(const LangOptions &Opts,
6225 MacroBuilder &Builder) const override {
6226 Builder.defineMacro("__AARCH64EB__");
6227 Builder.defineMacro("__AARCH_BIG_ENDIAN");
6228 Builder.defineMacro("__ARM_BIG_ENDIAN");
6229 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6233 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
6235 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
6236 MacroBuilder &Builder) const override {
6237 Builder.defineMacro("__AARCH64_SIMD__");
6238 Builder.defineMacro("__ARM64_ARCH_8__");
6239 Builder.defineMacro("__ARM_NEON__");
6240 Builder.defineMacro("__LITTLE_ENDIAN__");
6241 Builder.defineMacro("__REGISTER_PREFIX__", "");
6242 Builder.defineMacro("__arm64", "1");
6243 Builder.defineMacro("__arm64__", "1");
6245 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
6249 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6250 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
6251 Int64Type = SignedLongLong;
6252 WCharType = SignedInt;
6253 UseSignedCharForObjCBool = false;
6255 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
6256 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
6258 TheCXXABI.set(TargetCXXABI::iOS64);
6261 BuiltinVaListKind getBuiltinVaListKind() const override {
6262 return TargetInfo::CharPtrBuiltinVaList;
6266 // Hexagon abstract base class
6267 class HexagonTargetInfo : public TargetInfo {
6268 static const Builtin::Info BuiltinInfo[];
6269 static const char * const GCCRegNames[];
6270 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6272 bool HasHVX, HasHVXDouble;
6276 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6277 : TargetInfo(Triple) {
6278 // Specify the vector alignment explicitly. For v512x1, the calculated
6279 // alignment would be 512*alignment(i1), which is 512 bytes, instead of
6280 // the required minimum of 64 bytes.
6281 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-"
6282 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
6283 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048");
6284 SizeType = UnsignedInt;
6285 PtrDiffType = SignedInt;
6286 IntPtrType = SignedInt;
6288 // {} in inline assembly are packet specifiers, not assembly variant
6290 NoAsmVariants = true;
6292 LargeArrayMinWidth = 64;
6293 LargeArrayAlign = 64;
6294 UseBitFieldTypeAlignment = true;
6295 ZeroLengthBitfieldBoundary = 32;
6296 HasHVX = HasHVXDouble = false;
6297 UseLongCalls = false;
6300 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6301 return llvm::makeArrayRef(BuiltinInfo,
6302 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin);
6305 bool validateAsmConstraint(const char *&Name,
6306 TargetInfo::ConstraintInfo &Info) const override {
6311 Info.setAllowsRegister();
6316 // Relocatable constant.
6322 void getTargetDefines(const LangOptions &Opts,
6323 MacroBuilder &Builder) const override;
6325 bool isCLZForZeroUndef() const override { return false; }
6327 bool hasFeature(StringRef Feature) const override {
6328 return llvm::StringSwitch<bool>(Feature)
6329 .Case("hexagon", true)
6330 .Case("hvx", HasHVX)
6331 .Case("hvx-double", HasHVXDouble)
6332 .Case("long-calls", UseLongCalls)
6336 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6337 StringRef CPU, const std::vector<std::string> &FeaturesVec)
6340 bool handleTargetFeatures(std::vector<std::string> &Features,
6341 DiagnosticsEngine &Diags) override;
6343 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
6344 bool Enabled) const override;
6346 BuiltinVaListKind getBuiltinVaListKind() const override {
6347 return TargetInfo::CharPtrBuiltinVaList;
6349 ArrayRef<const char *> getGCCRegNames() const override;
6350 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6351 const char *getClobbers() const override {
6355 static const char *getHexagonCPUSuffix(StringRef Name) {
6356 return llvm::StringSwitch<const char*>(Name)
6357 .Case("hexagonv4", "4")
6358 .Case("hexagonv5", "5")
6359 .Case("hexagonv55", "55")
6360 .Case("hexagonv60", "60")
6364 bool setCPU(const std::string &Name) override {
6365 if (!getHexagonCPUSuffix(Name))
6371 int getEHDataRegisterNumber(unsigned RegNo) const override {
6372 return RegNo < 2 ? RegNo : -1;
6376 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
6377 MacroBuilder &Builder) const {
6378 Builder.defineMacro("__qdsp6__", "1");
6379 Builder.defineMacro("__hexagon__", "1");
6381 if (CPU == "hexagonv4") {
6382 Builder.defineMacro("__HEXAGON_V4__");
6383 Builder.defineMacro("__HEXAGON_ARCH__", "4");
6384 if (Opts.HexagonQdsp6Compat) {
6385 Builder.defineMacro("__QDSP6_V4__");
6386 Builder.defineMacro("__QDSP6_ARCH__", "4");
6388 } else if (CPU == "hexagonv5") {
6389 Builder.defineMacro("__HEXAGON_V5__");
6390 Builder.defineMacro("__HEXAGON_ARCH__", "5");
6391 if(Opts.HexagonQdsp6Compat) {
6392 Builder.defineMacro("__QDSP6_V5__");
6393 Builder.defineMacro("__QDSP6_ARCH__", "5");
6395 } else if (CPU == "hexagonv55") {
6396 Builder.defineMacro("__HEXAGON_V55__");
6397 Builder.defineMacro("__HEXAGON_ARCH__", "55");
6398 Builder.defineMacro("__QDSP6_V55__");
6399 Builder.defineMacro("__QDSP6_ARCH__", "55");
6400 } else if (CPU == "hexagonv60") {
6401 Builder.defineMacro("__HEXAGON_V60__");
6402 Builder.defineMacro("__HEXAGON_ARCH__", "60");
6403 Builder.defineMacro("__QDSP6_V60__");
6404 Builder.defineMacro("__QDSP6_ARCH__", "60");
6407 if (hasFeature("hvx")) {
6408 Builder.defineMacro("__HVX__");
6409 if (hasFeature("hvx-double"))
6410 Builder.defineMacro("__HVXDBL__");
6414 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features,
6415 DiagnosticsEngine &Diags, StringRef CPU,
6416 const std::vector<std::string> &FeaturesVec) const {
6417 // Default for v60: -hvx, -hvx-double.
6418 Features["hvx"] = false;
6419 Features["hvx-double"] = false;
6420 Features["long-calls"] = false;
6422 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6425 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
6426 DiagnosticsEngine &Diags) {
6427 for (auto &F : Features) {
6430 else if (F == "-hvx")
6431 HasHVX = HasHVXDouble = false;
6432 else if (F == "+hvx-double")
6433 HasHVX = HasHVXDouble = true;
6434 else if (F == "-hvx-double")
6435 HasHVXDouble = false;
6437 if (F == "+long-calls")
6438 UseLongCalls = true;
6439 else if (F == "-long-calls")
6440 UseLongCalls = false;
6445 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
6446 StringRef Name, bool Enabled) const {
6448 if (Name == "hvx-double")
6449 Features["hvx"] = true;
6452 Features["hvx-double"] = false;
6454 Features[Name] = Enabled;
6457 const char *const HexagonTargetInfo::GCCRegNames[] = {
6458 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6459 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6460 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6461 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
6462 "p0", "p1", "p2", "p3",
6463 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
6466 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const {
6467 return llvm::makeArrayRef(GCCRegNames);
6470 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
6471 { { "sp" }, "r29" },
6472 { { "fp" }, "r30" },
6473 { { "lr" }, "r31" },
6476 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const {
6477 return llvm::makeArrayRef(GCCRegAliases);
6481 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
6482 #define BUILTIN(ID, TYPE, ATTRS) \
6483 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6484 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6485 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6486 #include "clang/Basic/BuiltinsHexagon.def"
6489 class LanaiTargetInfo : public TargetInfo {
6490 // Class for Lanai (32-bit).
6491 // The CPU profiles supported by the Lanai backend
6497 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6498 static const char *const GCCRegNames[];
6501 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6502 : TargetInfo(Triple) {
6503 // Description string has to be kept in sync with backend.
6504 resetDataLayout("E" // Big endian
6505 "-m:e" // ELF name manging
6506 "-p:32:32" // 32 bit pointers, 32 bit aligned
6507 "-i64:64" // 64 bit integers, 64 bit aligned
6508 "-a:0:32" // 32 bit alignment of objects of aggregate type
6509 "-n32" // 32 bit native integer width
6510 "-S64" // 64 bit natural stack alignment
6513 // Setting RegParmMax equal to what mregparm was set to in the old
6517 // Set the default CPU to V11
6520 // Temporary approach to make everything at least word-aligned and allow for
6521 // safely casting between pointers with different alignment requirements.
6522 // TODO: Remove this when there are no more cast align warnings on the
6524 MinGlobalAlign = 32;
6527 void getTargetDefines(const LangOptions &Opts,
6528 MacroBuilder &Builder) const override {
6529 // Define __lanai__ when building for target lanai.
6530 Builder.defineMacro("__lanai__");
6532 // Set define for the CPU specified.
6535 Builder.defineMacro("__LANAI_V11__");
6538 llvm_unreachable("Unhandled target CPU");
6542 bool setCPU(const std::string &Name) override {
6543 CPU = llvm::StringSwitch<CPUKind>(Name)
6544 .Case("v11", CK_V11)
6547 return CPU != CK_NONE;
6550 bool hasFeature(StringRef Feature) const override {
6551 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false);
6554 ArrayRef<const char *> getGCCRegNames() const override;
6556 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6558 BuiltinVaListKind getBuiltinVaListKind() const override {
6559 return TargetInfo::VoidPtrBuiltinVaList;
6562 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
6564 bool validateAsmConstraint(const char *&Name,
6565 TargetInfo::ConstraintInfo &info) const override {
6569 const char *getClobbers() const override { return ""; }
6572 const char *const LanaiTargetInfo::GCCRegNames[] = {
6573 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
6574 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
6575 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
6577 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const {
6578 return llvm::makeArrayRef(GCCRegNames);
6581 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = {
6591 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const {
6592 return llvm::makeArrayRef(GCCRegAliases);
6595 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
6596 class SparcTargetInfo : public TargetInfo {
6597 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6598 static const char * const GCCRegNames[];
6601 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6602 : TargetInfo(Triple), SoftFloat(false) {}
6604 int getEHDataRegisterNumber(unsigned RegNo) const override {
6605 if (RegNo == 0) return 24;
6606 if (RegNo == 1) return 25;
6610 bool handleTargetFeatures(std::vector<std::string> &Features,
6611 DiagnosticsEngine &Diags) override {
6612 // Check if software floating point is enabled
6613 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
6614 if (Feature != Features.end()) {
6619 void getTargetDefines(const LangOptions &Opts,
6620 MacroBuilder &Builder) const override {
6621 DefineStd(Builder, "sparc", Opts);
6622 Builder.defineMacro("__REGISTER_PREFIX__", "");
6625 Builder.defineMacro("SOFT_FLOAT", "1");
6628 bool hasFeature(StringRef Feature) const override {
6629 return llvm::StringSwitch<bool>(Feature)
6630 .Case("softfloat", SoftFloat)
6631 .Case("sparc", true)
6635 bool hasSjLjLowering() const override {
6639 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6640 // FIXME: Implement!
6643 BuiltinVaListKind getBuiltinVaListKind() const override {
6644 return TargetInfo::VoidPtrBuiltinVaList;
6646 ArrayRef<const char *> getGCCRegNames() const override;
6647 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6648 bool validateAsmConstraint(const char *&Name,
6649 TargetInfo::ConstraintInfo &info) const override {
6650 // FIXME: Implement!
6652 case 'I': // Signed 13-bit constant
6654 case 'K': // 32-bit constant with the low 12 bits clear
6655 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
6656 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
6657 case 'N': // Same as 'K' but zext (required for SIMode)
6658 case 'O': // The constant 4096
6663 const char *getClobbers() const override {
6664 // FIXME: Implement!
6668 // No Sparc V7 for now, the backend doesn't support it anyway.
6699 enum CPUGeneration {
6704 CPUGeneration getCPUGeneration(CPUKind Kind) const {
6712 case CK_SPARCLITE86X:
6719 case CK_LEON2_AT697E:
6720 case CK_LEON2_AT697F:
6722 case CK_LEON3_UT699:
6723 case CK_LEON3_GR712RC:
6725 case CK_LEON4_GR740:
6729 case CK_ULTRASPARC3:
6736 llvm_unreachable("Unexpected CPU kind");
6739 CPUKind getCPUKind(StringRef Name) const {
6740 return llvm::StringSwitch<CPUKind>(Name)
6742 .Case("supersparc", CK_SUPERSPARC)
6743 .Case("sparclite", CK_SPARCLITE)
6744 .Case("f934", CK_F934)
6745 .Case("hypersparc", CK_HYPERSPARC)
6746 .Case("sparclite86x", CK_SPARCLITE86X)
6747 .Case("sparclet", CK_SPARCLET)
6748 .Case("tsc701", CK_TSC701)
6750 .Case("ultrasparc", CK_ULTRASPARC)
6751 .Case("ultrasparc3", CK_ULTRASPARC3)
6752 .Case("niagara", CK_NIAGARA)
6753 .Case("niagara2", CK_NIAGARA2)
6754 .Case("niagara3", CK_NIAGARA3)
6755 .Case("niagara4", CK_NIAGARA4)
6756 .Case("ma2100", CK_MYRIAD2100)
6757 .Case("ma2150", CK_MYRIAD2150)
6758 .Case("ma2450", CK_MYRIAD2450)
6759 // FIXME: the myriad2[.n] spellings are obsolete,
6760 // but a grace period is needed to allow updating dependent builds.
6761 .Case("myriad2", CK_MYRIAD2100)
6762 .Case("myriad2.1", CK_MYRIAD2100)
6763 .Case("myriad2.2", CK_MYRIAD2150)
6764 .Case("leon2", CK_LEON2)
6765 .Case("at697e", CK_LEON2_AT697E)
6766 .Case("at697f", CK_LEON2_AT697F)
6767 .Case("leon3", CK_LEON3)
6768 .Case("ut699", CK_LEON3_UT699)
6769 .Case("gr712rc", CK_LEON3_GR712RC)
6770 .Case("leon4", CK_LEON4)
6771 .Case("gr740", CK_LEON4_GR740)
6772 .Default(CK_GENERIC);
6775 bool setCPU(const std::string &Name) override {
6776 CPU = getCPUKind(Name);
6777 return CPU != CK_GENERIC;
6781 const char * const SparcTargetInfo::GCCRegNames[] = {
6782 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6783 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6784 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6785 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6788 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
6789 return llvm::makeArrayRef(GCCRegNames);
6792 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
6803 { { "o2" }, "r10" },
6804 { { "o3" }, "r11" },
6805 { { "o4" }, "r12" },
6806 { { "o5" }, "r13" },
6807 { { "o6", "sp" }, "r14" },
6808 { { "o7" }, "r15" },
6809 { { "l0" }, "r16" },
6810 { { "l1" }, "r17" },
6811 { { "l2" }, "r18" },
6812 { { "l3" }, "r19" },
6813 { { "l4" }, "r20" },
6814 { { "l5" }, "r21" },
6815 { { "l6" }, "r22" },
6816 { { "l7" }, "r23" },
6817 { { "i0" }, "r24" },
6818 { { "i1" }, "r25" },
6819 { { "i2" }, "r26" },
6820 { { "i3" }, "r27" },
6821 { { "i4" }, "r28" },
6822 { { "i5" }, "r29" },
6823 { { "i6", "fp" }, "r30" },
6824 { { "i7" }, "r31" },
6827 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
6828 return llvm::makeArrayRef(GCCRegAliases);
6831 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
6832 class SparcV8TargetInfo : public SparcTargetInfo {
6834 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6835 : SparcTargetInfo(Triple, Opts) {
6836 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64");
6837 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
6838 switch (getTriple().getOS()) {
6840 SizeType = UnsignedInt;
6841 IntPtrType = SignedInt;
6842 PtrDiffType = SignedInt;
6844 case llvm::Triple::NetBSD:
6845 case llvm::Triple::OpenBSD:
6846 SizeType = UnsignedLong;
6847 IntPtrType = SignedLong;
6848 PtrDiffType = SignedLong;
6851 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops
6852 // on up to 64 bits.
6853 MaxAtomicPromoteWidth = 64;
6854 MaxAtomicInlineWidth = 32;
6857 void getTargetDefines(const LangOptions &Opts,
6858 MacroBuilder &Builder) const override {
6859 SparcTargetInfo::getTargetDefines(Opts, Builder);
6860 switch (getCPUGeneration(CPU)) {
6862 Builder.defineMacro("__sparcv8");
6863 if (getTriple().getOS() != llvm::Triple::Solaris)
6864 Builder.defineMacro("__sparcv8__");
6867 Builder.defineMacro("__sparcv9");
6868 if (getTriple().getOS() != llvm::Triple::Solaris) {
6869 Builder.defineMacro("__sparcv9__");
6870 Builder.defineMacro("__sparc_v9__");
6874 if (getTriple().getVendor() == llvm::Triple::Myriad) {
6875 std::string MyriadArchValue, Myriad2Value;
6876 Builder.defineMacro("__sparc_v8__");
6877 Builder.defineMacro("__leon__");
6880 MyriadArchValue = "__ma2150";
6884 MyriadArchValue = "__ma2450";
6888 MyriadArchValue = "__ma2100";
6892 Builder.defineMacro(MyriadArchValue, "1");
6893 Builder.defineMacro(MyriadArchValue+"__", "1");
6894 Builder.defineMacro("__myriad2__", Myriad2Value);
6895 Builder.defineMacro("__myriad2", Myriad2Value);
6899 bool hasSjLjLowering() const override {
6904 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
6905 class SparcV8elTargetInfo : public SparcV8TargetInfo {
6907 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6908 : SparcV8TargetInfo(Triple, Opts) {
6909 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64");
6913 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
6914 class SparcV9TargetInfo : public SparcTargetInfo {
6916 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6917 : SparcTargetInfo(Triple, Opts) {
6918 // FIXME: Support Sparc quad-precision long double?
6919 resetDataLayout("E-m:e-i64:64-n32:64-S128");
6920 // This is an LP64 platform.
6921 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6923 // OpenBSD uses long long for int64_t and intmax_t.
6924 if (getTriple().getOS() == llvm::Triple::OpenBSD)
6925 IntMaxType = SignedLongLong;
6927 IntMaxType = SignedLong;
6928 Int64Type = IntMaxType;
6930 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
6931 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
6932 LongDoubleWidth = 128;
6933 LongDoubleAlign = 128;
6934 LongDoubleFormat = &llvm::APFloat::IEEEquad();
6935 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6938 void getTargetDefines(const LangOptions &Opts,
6939 MacroBuilder &Builder) const override {
6940 SparcTargetInfo::getTargetDefines(Opts, Builder);
6941 Builder.defineMacro("__sparcv9");
6942 Builder.defineMacro("__arch64__");
6943 // Solaris doesn't need these variants, but the BSDs do.
6944 if (getTriple().getOS() != llvm::Triple::Solaris) {
6945 Builder.defineMacro("__sparc64__");
6946 Builder.defineMacro("__sparc_v9__");
6947 Builder.defineMacro("__sparcv9__");
6951 bool setCPU(const std::string &Name) override {
6952 if (!SparcTargetInfo::setCPU(Name))
6954 return getCPUGeneration(CPU) == CG_V9;
6958 class SystemZTargetInfo : public TargetInfo {
6959 static const Builtin::Info BuiltinInfo[];
6960 static const char *const GCCRegNames[];
6962 bool HasTransactionalExecution;
6966 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6967 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false),
6969 IntMaxType = SignedLong;
6970 Int64Type = SignedLong;
6971 TLSSupported = true;
6972 IntWidth = IntAlign = 32;
6973 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
6974 PointerWidth = PointerAlign = 64;
6975 LongDoubleWidth = 128;
6976 LongDoubleAlign = 64;
6977 LongDoubleFormat = &llvm::APFloat::IEEEquad();
6978 DefaultAlignForAttributeAligned = 64;
6979 MinGlobalAlign = 16;
6980 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64");
6981 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6983 void getTargetDefines(const LangOptions &Opts,
6984 MacroBuilder &Builder) const override {
6985 Builder.defineMacro("__s390__");
6986 Builder.defineMacro("__s390x__");
6987 Builder.defineMacro("__zarch__");
6988 Builder.defineMacro("__LONG_DOUBLE_128__");
6990 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
6991 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
6992 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
6993 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
6995 if (HasTransactionalExecution)
6996 Builder.defineMacro("__HTM__");
6998 Builder.defineMacro("__VEC__", "10301");
7000 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7001 return llvm::makeArrayRef(BuiltinInfo,
7002 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin);
7005 ArrayRef<const char *> getGCCRegNames() const override;
7006 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7010 bool validateAsmConstraint(const char *&Name,
7011 TargetInfo::ConstraintInfo &info) const override;
7012 const char *getClobbers() const override {
7013 // FIXME: Is this really right?
7016 BuiltinVaListKind getBuiltinVaListKind() const override {
7017 return TargetInfo::SystemZBuiltinVaList;
7019 bool setCPU(const std::string &Name) override {
7021 bool CPUKnown = llvm::StringSwitch<bool>(Name)
7023 .Case("arch8", true)
7025 .Case("arch9", true)
7026 .Case("zEC12", true)
7027 .Case("arch10", true)
7029 .Case("arch11", true)
7035 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7037 const std::vector<std::string> &FeaturesVec) const override {
7038 if (CPU == "zEC12" || CPU == "arch10")
7039 Features["transactional-execution"] = true;
7040 if (CPU == "z13" || CPU == "arch11") {
7041 Features["transactional-execution"] = true;
7042 Features["vector"] = true;
7044 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7047 bool handleTargetFeatures(std::vector<std::string> &Features,
7048 DiagnosticsEngine &Diags) override {
7049 HasTransactionalExecution = false;
7050 for (const auto &Feature : Features) {
7051 if (Feature == "+transactional-execution")
7052 HasTransactionalExecution = true;
7053 else if (Feature == "+vector")
7056 // If we use the vector ABI, vector types are 64-bit aligned.
7058 MaxVectorAlign = 64;
7059 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
7060 "-v128:64-a:8:16-n32:64");
7065 bool hasFeature(StringRef Feature) const override {
7066 return llvm::StringSwitch<bool>(Feature)
7067 .Case("systemz", true)
7068 .Case("htm", HasTransactionalExecution)
7069 .Case("vx", HasVector)
7073 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
7079 return CCCR_Warning;
7083 StringRef getABI() const override {
7089 bool useFloat128ManglingForLongDouble() const override {
7094 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
7095 #define BUILTIN(ID, TYPE, ATTRS) \
7096 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7097 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
7098 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
7099 #include "clang/Basic/BuiltinsSystemZ.def"
7102 const char *const SystemZTargetInfo::GCCRegNames[] = {
7103 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7104 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7105 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
7106 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
7109 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
7110 return llvm::makeArrayRef(GCCRegNames);
7113 bool SystemZTargetInfo::
7114 validateAsmConstraint(const char *&Name,
7115 TargetInfo::ConstraintInfo &Info) const {
7120 case 'a': // Address register
7121 case 'd': // Data register (equivalent to 'r')
7122 case 'f': // Floating-point register
7123 Info.setAllowsRegister();
7126 case 'I': // Unsigned 8-bit constant
7127 case 'J': // Unsigned 12-bit constant
7128 case 'K': // Signed 16-bit constant
7129 case 'L': // Signed 20-bit displacement (on all targets we support)
7130 case 'M': // 0x7fffffff
7133 case 'Q': // Memory with base and unsigned 12-bit displacement
7134 case 'R': // Likewise, plus an index
7135 case 'S': // Memory with base and signed 20-bit displacement
7136 case 'T': // Likewise, plus an index
7137 Info.setAllowsMemory();
7142 class MSP430TargetInfo : public TargetInfo {
7143 static const char *const GCCRegNames[];
7146 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7147 : TargetInfo(Triple) {
7148 TLSSupported = false;
7153 LongAlign = LongLongAlign = 16;
7157 SizeType = UnsignedInt;
7158 IntMaxType = SignedLongLong;
7159 IntPtrType = SignedInt;
7160 PtrDiffType = SignedInt;
7161 SigAtomicType = SignedLong;
7162 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16");
7164 void getTargetDefines(const LangOptions &Opts,
7165 MacroBuilder &Builder) const override {
7166 Builder.defineMacro("MSP430");
7167 Builder.defineMacro("__MSP430__");
7168 // FIXME: defines for different 'flavours' of MCU
7170 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7171 // FIXME: Implement.
7174 bool hasFeature(StringRef Feature) const override {
7175 return Feature == "msp430";
7177 ArrayRef<const char *> getGCCRegNames() const override;
7178 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7182 bool validateAsmConstraint(const char *&Name,
7183 TargetInfo::ConstraintInfo &info) const override {
7186 case 'K': // the constant 1
7187 case 'L': // constant -1^20 .. 1^19
7188 case 'M': // constant 1-4:
7191 // No target constraints for now.
7194 const char *getClobbers() const override {
7195 // FIXME: Is this really right?
7198 BuiltinVaListKind getBuiltinVaListKind() const override {
7200 return TargetInfo::CharPtrBuiltinVaList;
7204 const char *const MSP430TargetInfo::GCCRegNames[] = {
7205 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7206 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
7208 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const {
7209 return llvm::makeArrayRef(GCCRegNames);
7212 // LLVM and Clang cannot be used directly to output native binaries for
7213 // target, but is used to compile C code to llvm bitcode with correct
7214 // type and alignment information.
7216 // TCE uses the llvm bitcode as input and uses it for generating customized
7217 // target processor and program binary. TCE co-design environment is
7218 // publicly available in http://tce.cs.tut.fi
7220 static const unsigned TCEOpenCLAddrSpaceMap[] = {
7223 5, // opencl_constant
7224 // FIXME: generic has to be added to the target
7225 0, // opencl_generic
7231 class TCETargetInfo : public TargetInfo {
7233 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7234 : TargetInfo(Triple) {
7235 TLSSupported = false;
7237 LongWidth = LongLongWidth = 32;
7240 LongAlign = LongLongAlign = 32;
7243 SizeType = UnsignedInt;
7244 IntMaxType = SignedLong;
7245 IntPtrType = SignedInt;
7246 PtrDiffType = SignedInt;
7251 LongDoubleWidth = 32;
7252 LongDoubleAlign = 32;
7253 FloatFormat = &llvm::APFloat::IEEEsingle();
7254 DoubleFormat = &llvm::APFloat::IEEEsingle();
7255 LongDoubleFormat = &llvm::APFloat::IEEEsingle();
7256 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-"
7257 "i16:16:32-i32:32:32-i64:32:32-"
7258 "f32:32:32-f64:32:32-v64:32:32-"
7259 "v128:32:32-v256:32:32-v512:32:32-"
7260 "v1024:32:32-a0:0:32-n32");
7261 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
7262 UseAddrSpaceMapMangling = true;
7265 void getTargetDefines(const LangOptions &Opts,
7266 MacroBuilder &Builder) const override {
7267 DefineStd(Builder, "tce", Opts);
7268 Builder.defineMacro("__TCE__");
7269 Builder.defineMacro("__TCE_V1__");
7271 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; }
7273 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7274 const char *getClobbers() const override { return ""; }
7275 BuiltinVaListKind getBuiltinVaListKind() const override {
7276 return TargetInfo::VoidPtrBuiltinVaList;
7278 ArrayRef<const char *> getGCCRegNames() const override { return None; }
7279 bool validateAsmConstraint(const char *&Name,
7280 TargetInfo::ConstraintInfo &info) const override {
7283 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7288 class TCELETargetInfo : public TCETargetInfo {
7290 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7291 : TCETargetInfo(Triple, Opts) {
7294 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-"
7295 "i16:16:32-i32:32:32-i64:32:32-"
7296 "f32:32:32-f64:32:32-v64:32:32-"
7297 "v128:32:32-v256:32:32-v512:32:32-"
7298 "v1024:32:32-a0:0:32-n32");
7302 virtual void getTargetDefines(const LangOptions &Opts,
7303 MacroBuilder &Builder) const {
7304 DefineStd(Builder, "tcele", Opts);
7305 Builder.defineMacro("__TCE__");
7306 Builder.defineMacro("__TCE_V1__");
7307 Builder.defineMacro("__TCELE__");
7308 Builder.defineMacro("__TCELE_V1__");
7313 class BPFTargetInfo : public TargetInfo {
7315 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7316 : TargetInfo(Triple) {
7317 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7318 SizeType = UnsignedLong;
7319 PtrDiffType = SignedLong;
7320 IntPtrType = SignedLong;
7321 IntMaxType = SignedLong;
7322 Int64Type = SignedLong;
7324 if (Triple.getArch() == llvm::Triple::bpfeb) {
7325 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128");
7327 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
7329 MaxAtomicPromoteWidth = 64;
7330 MaxAtomicInlineWidth = 64;
7331 TLSSupported = false;
7333 void getTargetDefines(const LangOptions &Opts,
7334 MacroBuilder &Builder) const override {
7335 DefineStd(Builder, "bpf", Opts);
7336 Builder.defineMacro("__BPF__");
7338 bool hasFeature(StringRef Feature) const override {
7339 return Feature == "bpf";
7342 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7343 const char *getClobbers() const override {
7346 BuiltinVaListKind getBuiltinVaListKind() const override {
7347 return TargetInfo::VoidPtrBuiltinVaList;
7349 ArrayRef<const char *> getGCCRegNames() const override {
7352 bool validateAsmConstraint(const char *&Name,
7353 TargetInfo::ConstraintInfo &info) const override {
7356 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7361 class MipsTargetInfo : public TargetInfo {
7362 void setDataLayout() {
7366 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
7367 else if (ABI == "n32")
7368 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7369 else if (ABI == "n64")
7370 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7372 llvm_unreachable("Invalid ABI");
7375 resetDataLayout(("E-" + Layout).str());
7377 resetDataLayout(("e-" + Layout).str());
7381 static const Builtin::Info BuiltinInfo[];
7388 HardFloat, SoftFloat
7400 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7401 : TargetInfo(Triple), IsMips16(false), IsMicromips(false),
7402 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
7403 DspRev(NoDSP), HasMSA(false), HasFP64(false) {
7404 TheCXXABI.set(TargetCXXABI::GenericMIPS);
7406 setABI((getTriple().getArch() == llvm::Triple::mips ||
7407 getTriple().getArch() == llvm::Triple::mipsel)
7411 CPU = ABI == "o32" ? "mips32r2" : "mips64r2";
7414 bool isNaN2008Default() const {
7415 return CPU == "mips32r6" || CPU == "mips64r6";
7418 bool isFP64Default() const {
7419 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
7422 bool isNan2008() const override {
7426 bool processorSupportsGPR64() const {
7427 return llvm::StringSwitch<bool>(CPU)
7428 .Case("mips3", true)
7429 .Case("mips4", true)
7430 .Case("mips5", true)
7431 .Case("mips64", true)
7432 .Case("mips64r2", true)
7433 .Case("mips64r3", true)
7434 .Case("mips64r5", true)
7435 .Case("mips64r6", true)
7436 .Case("octeon", true)
7441 StringRef getABI() const override { return ABI; }
7442 bool setABI(const std::string &Name) override {
7443 if (Name == "o32") {
7449 if (Name == "n32") {
7454 if (Name == "n64") {
7462 void setO32ABITypes() {
7463 Int64Type = SignedLongLong;
7464 IntMaxType = Int64Type;
7465 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
7466 LongDoubleWidth = LongDoubleAlign = 64;
7467 LongWidth = LongAlign = 32;
7468 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
7469 PointerWidth = PointerAlign = 32;
7470 PtrDiffType = SignedInt;
7471 SizeType = UnsignedInt;
7475 void setN32N64ABITypes() {
7476 LongDoubleWidth = LongDoubleAlign = 128;
7477 LongDoubleFormat = &llvm::APFloat::IEEEquad();
7478 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
7479 LongDoubleWidth = LongDoubleAlign = 64;
7480 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
7482 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7483 SuitableAlign = 128;
7486 void setN64ABITypes() {
7487 setN32N64ABITypes();
7488 Int64Type = SignedLong;
7489 IntMaxType = Int64Type;
7490 LongWidth = LongAlign = 64;
7491 PointerWidth = PointerAlign = 64;
7492 PtrDiffType = SignedLong;
7493 SizeType = UnsignedLong;
7496 void setN32ABITypes() {
7497 setN32N64ABITypes();
7498 Int64Type = SignedLongLong;
7499 IntMaxType = Int64Type;
7500 LongWidth = LongAlign = 32;
7501 PointerWidth = PointerAlign = 32;
7502 PtrDiffType = SignedInt;
7503 SizeType = UnsignedInt;
7506 bool setCPU(const std::string &Name) override {
7508 return llvm::StringSwitch<bool>(Name)
7509 .Case("mips1", true)
7510 .Case("mips2", true)
7511 .Case("mips3", true)
7512 .Case("mips4", true)
7513 .Case("mips5", true)
7514 .Case("mips32", true)
7515 .Case("mips32r2", true)
7516 .Case("mips32r3", true)
7517 .Case("mips32r5", true)
7518 .Case("mips32r6", true)
7519 .Case("mips64", true)
7520 .Case("mips64r2", true)
7521 .Case("mips64r3", true)
7522 .Case("mips64r5", true)
7523 .Case("mips64r6", true)
7524 .Case("octeon", true)
7525 .Case("p5600", true)
7528 const std::string& getCPU() const { return CPU; }
7530 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7532 const std::vector<std::string> &FeaturesVec) const override {
7535 if (CPU == "octeon")
7536 Features["mips64r2"] = Features["cnmips"] = true;
7538 Features[CPU] = true;
7539 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7542 void getTargetDefines(const LangOptions &Opts,
7543 MacroBuilder &Builder) const override {
7545 DefineStd(Builder, "MIPSEB", Opts);
7546 Builder.defineMacro("_MIPSEB");
7548 DefineStd(Builder, "MIPSEL", Opts);
7549 Builder.defineMacro("_MIPSEL");
7552 Builder.defineMacro("__mips__");
7553 Builder.defineMacro("_mips");
7555 Builder.defineMacro("mips");
7558 Builder.defineMacro("__mips", "32");
7559 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
7561 Builder.defineMacro("__mips", "64");
7562 Builder.defineMacro("__mips64");
7563 Builder.defineMacro("__mips64__");
7564 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
7567 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU())
7568 .Cases("mips32", "mips64", "1")
7569 .Cases("mips32r2", "mips64r2", "2")
7570 .Cases("mips32r3", "mips64r3", "3")
7571 .Cases("mips32r5", "mips64r5", "5")
7572 .Cases("mips32r6", "mips64r6", "6")
7574 if (!ISARev.empty())
7575 Builder.defineMacro("__mips_isa_rev", ISARev);
7578 Builder.defineMacro("__mips_o32");
7579 Builder.defineMacro("_ABIO32", "1");
7580 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
7581 } else if (ABI == "n32") {
7582 Builder.defineMacro("__mips_n32");
7583 Builder.defineMacro("_ABIN32", "2");
7584 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
7585 } else if (ABI == "n64") {
7586 Builder.defineMacro("__mips_n64");
7587 Builder.defineMacro("_ABI64", "3");
7588 Builder.defineMacro("_MIPS_SIM", "_ABI64");
7590 llvm_unreachable("Invalid ABI.");
7592 Builder.defineMacro("__REGISTER_PREFIX__", "");
7596 Builder.defineMacro("__mips_hard_float", Twine(1));
7599 Builder.defineMacro("__mips_soft_float", Twine(1));
7604 Builder.defineMacro("__mips_single_float", Twine(1));
7606 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
7607 Builder.defineMacro("_MIPS_FPSET",
7608 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
7611 Builder.defineMacro("__mips16", Twine(1));
7614 Builder.defineMacro("__mips_micromips", Twine(1));
7617 Builder.defineMacro("__mips_nan2008", Twine(1));
7623 Builder.defineMacro("__mips_dsp_rev", Twine(1));
7624 Builder.defineMacro("__mips_dsp", Twine(1));
7627 Builder.defineMacro("__mips_dsp_rev", Twine(2));
7628 Builder.defineMacro("__mips_dspr2", Twine(1));
7629 Builder.defineMacro("__mips_dsp", Twine(1));
7634 Builder.defineMacro("__mips_msa", Twine(1));
7636 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
7637 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
7638 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
7640 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
7641 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
7643 // These shouldn't be defined for MIPS-I but there's no need to check
7644 // for that since MIPS-I isn't supported.
7645 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
7646 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
7647 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
7649 // 32-bit MIPS processors don't have the necessary lld/scd instructions
7650 // found in 64-bit processors. In the case of O32 on a 64-bit processor,
7651 // the instructions exist but using them violates the ABI since they
7652 // require 64-bit GPRs and O32 only supports 32-bit GPRs.
7653 if (ABI == "n32" || ABI == "n64")
7654 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
7657 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7658 return llvm::makeArrayRef(BuiltinInfo,
7659 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin);
7661 bool hasFeature(StringRef Feature) const override {
7662 return llvm::StringSwitch<bool>(Feature)
7664 .Case("fp64", HasFP64)
7667 BuiltinVaListKind getBuiltinVaListKind() const override {
7668 return TargetInfo::VoidPtrBuiltinVaList;
7670 ArrayRef<const char *> getGCCRegNames() const override {
7671 static const char *const GCCRegNames[] = {
7672 // CPU register names
7673 // Must match second column of GCCRegAliases
7674 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
7675 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
7676 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
7677 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
7678 // Floating point register names
7679 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
7680 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
7681 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
7682 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
7683 // Hi/lo and condition register names
7684 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
7685 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo",
7687 // MSA register names
7688 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
7689 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
7690 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
7691 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
7692 // MSA control register names
7693 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
7694 "$msarequest", "$msamap", "$msaunmap"
7696 return llvm::makeArrayRef(GCCRegNames);
7698 bool validateAsmConstraint(const char *&Name,
7699 TargetInfo::ConstraintInfo &Info) const override {
7703 case 'r': // CPU registers.
7704 case 'd': // Equivalent to "r" unless generating MIPS16 code.
7705 case 'y': // Equivalent to "r", backward compatibility only.
7706 case 'f': // floating-point registers.
7707 case 'c': // $25 for indirect jumps
7708 case 'l': // lo register
7709 case 'x': // hilo register pair
7710 Info.setAllowsRegister();
7712 case 'I': // Signed 16-bit constant
7713 case 'J': // Integer 0
7714 case 'K': // Unsigned 16-bit constant
7715 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
7716 case 'M': // Constants not loadable via lui, addiu, or ori
7717 case 'N': // Constant -1 to -65535
7718 case 'O': // A signed 15-bit constant
7719 case 'P': // A constant between 1 go 65535
7721 case 'R': // An address that can be used in a non-macro load or store
7722 Info.setAllowsMemory();
7725 if (Name[1] == 'C') { // An address usable by ll, and sc.
7726 Info.setAllowsMemory();
7727 Name++; // Skip over 'Z'.
7734 std::string convertConstraint(const char *&Constraint) const override {
7736 switch (*Constraint) {
7737 case 'Z': // Two-character constraint; add "^" hint for later parsing.
7738 if (Constraint[1] == 'C') {
7739 R = std::string("^") + std::string(Constraint, 2);
7745 return TargetInfo::convertConstraint(Constraint);
7748 const char *getClobbers() const override {
7749 // In GCC, $1 is not widely used in generated code (it's used only in a few
7750 // specific situations), so there is no real need for users to add it to
7751 // the clobbers list if they want to use it in their inline assembly code.
7753 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
7754 // code generation, so using it in inline assembly without adding it to the
7755 // clobbers list can cause conflicts between the inline assembly code and
7756 // the surrounding generated code.
7758 // Another problem is that LLVM is allowed to choose $1 for inline assembly
7759 // operands, which will conflict with the ".set at" assembler option (which
7760 // we use only for inline assembly, in order to maintain compatibility with
7761 // GCC) and will also conflict with the user's usage of $1.
7763 // The easiest way to avoid these conflicts and keep $1 as an allocatable
7764 // register for generated code is to automatically clobber $1 for all inline
7767 // FIXME: We should automatically clobber $1 only for inline assembly code
7768 // which actually uses it. This would allow LLVM to use $1 for inline
7769 // assembly operands if the user's assembly code doesn't use it.
7773 bool handleTargetFeatures(std::vector<std::string> &Features,
7774 DiagnosticsEngine &Diags) override {
7776 IsMicromips = false;
7777 IsNan2008 = isNaN2008Default();
7778 IsSingleFloat = false;
7779 FloatABI = HardFloat;
7781 HasFP64 = isFP64Default();
7783 for (const auto &Feature : Features) {
7784 if (Feature == "+single-float")
7785 IsSingleFloat = true;
7786 else if (Feature == "+soft-float")
7787 FloatABI = SoftFloat;
7788 else if (Feature == "+mips16")
7790 else if (Feature == "+micromips")
7792 else if (Feature == "+dsp")
7793 DspRev = std::max(DspRev, DSP1);
7794 else if (Feature == "+dspr2")
7795 DspRev = std::max(DspRev, DSP2);
7796 else if (Feature == "+msa")
7798 else if (Feature == "+fp64")
7800 else if (Feature == "-fp64")
7802 else if (Feature == "+nan2008")
7804 else if (Feature == "-nan2008")
7813 int getEHDataRegisterNumber(unsigned RegNo) const override {
7814 if (RegNo == 0) return 4;
7815 if (RegNo == 1) return 5;
7819 bool isCLZForZeroUndef() const override { return false; }
7821 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7822 static const TargetInfo::GCCRegAlias O32RegAliases[] = {
7823 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
7824 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
7825 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"},
7826 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"},
7827 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"},
7828 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
7829 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
7830 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
7831 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
7832 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
7834 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = {
7835 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
7836 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
7837 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"},
7838 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"},
7839 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"},
7840 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
7841 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
7842 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
7843 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
7844 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
7847 return llvm::makeArrayRef(O32RegAliases);
7848 return llvm::makeArrayRef(NewABIRegAliases);
7851 bool hasInt128Type() const override {
7852 return ABI == "n32" || ABI == "n64";
7855 bool validateTarget(DiagnosticsEngine &Diags) const override {
7856 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle
7857 // this yet. It's better to fail here than on the backend assertion.
7858 if (processorSupportsGPR64() && ABI == "o32") {
7859 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
7863 // 64-bit ABI's require 64-bit CPU's.
7864 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) {
7865 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
7869 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend
7870 // can't handle this yet. It's better to fail here than on the
7871 // backend assertion.
7872 if ((getTriple().getArch() == llvm::Triple::mips64 ||
7873 getTriple().getArch() == llvm::Triple::mips64el) &&
7875 Diags.Report(diag::err_target_unsupported_abi_for_triple)
7876 << ABI << getTriple().str();
7880 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend
7881 // can't handle this yet. It's better to fail here than on the
7882 // backend assertion.
7883 if ((getTriple().getArch() == llvm::Triple::mips ||
7884 getTriple().getArch() == llvm::Triple::mipsel) &&
7885 (ABI == "n32" || ABI == "n64")) {
7886 Diags.Report(diag::err_target_unsupported_abi_for_triple)
7887 << ABI << getTriple().str();
7895 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = {
7896 #define BUILTIN(ID, TYPE, ATTRS) \
7897 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7898 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
7899 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
7900 #include "clang/Basic/BuiltinsMips.def"
7903 class PNaClTargetInfo : public TargetInfo {
7905 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7906 : TargetInfo(Triple) {
7907 this->LongAlign = 32;
7908 this->LongWidth = 32;
7909 this->PointerAlign = 32;
7910 this->PointerWidth = 32;
7911 this->IntMaxType = TargetInfo::SignedLongLong;
7912 this->Int64Type = TargetInfo::SignedLongLong;
7913 this->DoubleAlign = 64;
7914 this->LongDoubleWidth = 64;
7915 this->LongDoubleAlign = 64;
7916 this->SizeType = TargetInfo::UnsignedInt;
7917 this->PtrDiffType = TargetInfo::SignedInt;
7918 this->IntPtrType = TargetInfo::SignedInt;
7919 this->RegParmMax = 0; // Disallow regparm
7922 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
7923 Builder.defineMacro("__le32__");
7924 Builder.defineMacro("__pnacl__");
7926 void getTargetDefines(const LangOptions &Opts,
7927 MacroBuilder &Builder) const override {
7928 getArchDefines(Opts, Builder);
7930 bool hasFeature(StringRef Feature) const override {
7931 return Feature == "pnacl";
7933 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7934 BuiltinVaListKind getBuiltinVaListKind() const override {
7935 return TargetInfo::PNaClABIBuiltinVaList;
7937 ArrayRef<const char *> getGCCRegNames() const override;
7938 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
7939 bool validateAsmConstraint(const char *&Name,
7940 TargetInfo::ConstraintInfo &Info) const override {
7944 const char *getClobbers() const override {
7949 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const {
7953 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const {
7957 // We attempt to use PNaCl (le32) frontend and Mips32EL backend.
7958 class NaClMips32TargetInfo : public MipsTargetInfo {
7960 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7961 : MipsTargetInfo(Triple, Opts) {}
7963 BuiltinVaListKind getBuiltinVaListKind() const override {
7964 return TargetInfo::PNaClABIBuiltinVaList;
7968 class Le64TargetInfo : public TargetInfo {
7969 static const Builtin::Info BuiltinInfo[];
7972 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7973 : TargetInfo(Triple) {
7974 NoAsmVariants = true;
7975 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7976 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7977 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128");
7980 void getTargetDefines(const LangOptions &Opts,
7981 MacroBuilder &Builder) const override {
7982 DefineStd(Builder, "unix", Opts);
7983 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
7984 Builder.defineMacro("__ELF__");
7986 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7987 return llvm::makeArrayRef(BuiltinInfo,
7988 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin);
7990 BuiltinVaListKind getBuiltinVaListKind() const override {
7991 return TargetInfo::PNaClABIBuiltinVaList;
7993 const char *getClobbers() const override { return ""; }
7994 ArrayRef<const char *> getGCCRegNames() const override {
7997 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8000 bool validateAsmConstraint(const char *&Name,
8001 TargetInfo::ConstraintInfo &Info) const override {
8005 bool hasProtectedVisibility() const override { return false; }
8008 class WebAssemblyTargetInfo : public TargetInfo {
8009 static const Builtin::Info BuiltinInfo[];
8017 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &)
8018 : TargetInfo(T), SIMDLevel(NoSIMD) {
8019 NoAsmVariants = true;
8020 SuitableAlign = 128;
8021 LargeArrayMinWidth = 128;
8022 LargeArrayAlign = 128;
8023 SimdDefaultAlign = 128;
8024 SigAtomicType = SignedLong;
8025 LongDoubleWidth = LongDoubleAlign = 128;
8026 LongDoubleFormat = &llvm::APFloat::IEEEquad();
8027 SizeType = UnsignedInt;
8028 PtrDiffType = SignedInt;
8029 IntPtrType = SignedInt;
8033 void getTargetDefines(const LangOptions &Opts,
8034 MacroBuilder &Builder) const override {
8035 defineCPUMacros(Builder, "wasm", /*Tuning=*/false);
8036 if (SIMDLevel >= SIMD128)
8037 Builder.defineMacro("__wasm_simd128__");
8042 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
8044 const std::vector<std::string> &FeaturesVec) const override {
8045 if (CPU == "bleeding-edge")
8046 Features["simd128"] = true;
8047 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
8049 bool hasFeature(StringRef Feature) const final {
8050 return llvm::StringSwitch<bool>(Feature)
8051 .Case("simd128", SIMDLevel >= SIMD128)
8054 bool handleTargetFeatures(std::vector<std::string> &Features,
8055 DiagnosticsEngine &Diags) final {
8056 for (const auto &Feature : Features) {
8057 if (Feature == "+simd128") {
8058 SIMDLevel = std::max(SIMDLevel, SIMD128);
8061 if (Feature == "-simd128") {
8062 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1));
8066 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature
8067 << "-target-feature";
8072 bool setCPU(const std::string &Name) final {
8073 return llvm::StringSwitch<bool>(Name)
8075 .Case("bleeding-edge", true)
8076 .Case("generic", true)
8079 ArrayRef<Builtin::Info> getTargetBuiltins() const final {
8080 return llvm::makeArrayRef(BuiltinInfo,
8081 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin);
8083 BuiltinVaListKind getBuiltinVaListKind() const final {
8084 return VoidPtrBuiltinVaList;
8086 ArrayRef<const char *> getGCCRegNames() const final {
8089 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final {
8093 validateAsmConstraint(const char *&Name,
8094 TargetInfo::ConstraintInfo &Info) const final {
8097 const char *getClobbers() const final { return ""; }
8098 bool isCLZForZeroUndef() const final { return false; }
8099 bool hasInt128Type() const final { return true; }
8100 IntType getIntTypeByWidth(unsigned BitWidth,
8101 bool IsSigned) const final {
8102 // WebAssembly prefers long long for explicitly 64-bit integers.
8103 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
8104 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
8106 IntType getLeastIntTypeByWidth(unsigned BitWidth,
8107 bool IsSigned) const final {
8108 // WebAssembly uses long long for int_least64_t and int_fast64_t.
8109 return BitWidth == 64
8110 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
8111 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
8115 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = {
8116 #define BUILTIN(ID, TYPE, ATTRS) \
8117 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8118 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8119 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8120 #include "clang/Basic/BuiltinsWebAssembly.def"
8123 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo {
8125 explicit WebAssembly32TargetInfo(const llvm::Triple &T,
8126 const TargetOptions &Opts)
8127 : WebAssemblyTargetInfo(T, Opts) {
8128 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
8129 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128");
8133 void getTargetDefines(const LangOptions &Opts,
8134 MacroBuilder &Builder) const override {
8135 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
8136 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false);
8140 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo {
8142 explicit WebAssembly64TargetInfo(const llvm::Triple &T,
8143 const TargetOptions &Opts)
8144 : WebAssemblyTargetInfo(T, Opts) {
8145 LongAlign = LongWidth = 64;
8146 PointerAlign = PointerWidth = 64;
8147 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8148 SizeType = UnsignedLong;
8149 PtrDiffType = SignedLong;
8150 IntPtrType = SignedLong;
8151 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
8155 void getTargetDefines(const LangOptions &Opts,
8156 MacroBuilder &Builder) const override {
8157 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
8158 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false);
8162 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
8163 #define BUILTIN(ID, TYPE, ATTRS) \
8164 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8165 #include "clang/Basic/BuiltinsLe64.def"
8168 static const unsigned SPIRAddrSpaceMap[] = {
8171 2, // opencl_constant
8172 4, // opencl_generic
8177 class SPIRTargetInfo : public TargetInfo {
8179 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8180 : TargetInfo(Triple) {
8181 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
8182 "SPIR target must use unknown OS");
8183 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
8184 "SPIR target must use unknown environment type");
8185 TLSSupported = false;
8186 LongWidth = LongAlign = 64;
8187 AddrSpaceMap = &SPIRAddrSpaceMap;
8188 UseAddrSpaceMapMangling = true;
8189 // Define available target features
8190 // These must be defined in sorted order!
8191 NoAsmVariants = true;
8193 void getTargetDefines(const LangOptions &Opts,
8194 MacroBuilder &Builder) const override {
8195 DefineStd(Builder, "SPIR", Opts);
8197 bool hasFeature(StringRef Feature) const override {
8198 return Feature == "spir";
8201 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
8202 const char *getClobbers() const override { return ""; }
8203 ArrayRef<const char *> getGCCRegNames() const override { return None; }
8204 bool validateAsmConstraint(const char *&Name,
8205 TargetInfo::ConstraintInfo &info) const override {
8208 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8211 BuiltinVaListKind getBuiltinVaListKind() const override {
8212 return TargetInfo::VoidPtrBuiltinVaList;
8215 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
8216 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK
8220 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
8221 return CC_SpirFunction;
8224 void setSupportedOpenCLOpts() override {
8225 // Assume all OpenCL extensions and optional core features are supported
8226 // for SPIR since it is a generic target.
8227 getSupportedOpenCLOpts().supportAll();
8231 class SPIR32TargetInfo : public SPIRTargetInfo {
8233 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8234 : SPIRTargetInfo(Triple, Opts) {
8235 PointerWidth = PointerAlign = 32;
8236 SizeType = TargetInfo::UnsignedInt;
8237 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
8238 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
8239 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
8241 void getTargetDefines(const LangOptions &Opts,
8242 MacroBuilder &Builder) const override {
8243 DefineStd(Builder, "SPIR32", Opts);
8247 class SPIR64TargetInfo : public SPIRTargetInfo {
8249 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8250 : SPIRTargetInfo(Triple, Opts) {
8251 PointerWidth = PointerAlign = 64;
8252 SizeType = TargetInfo::UnsignedLong;
8253 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
8254 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
8255 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
8257 void getTargetDefines(const LangOptions &Opts,
8258 MacroBuilder &Builder) const override {
8259 DefineStd(Builder, "SPIR64", Opts);
8263 class XCoreTargetInfo : public TargetInfo {
8264 static const Builtin::Info BuiltinInfo[];
8266 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8267 : TargetInfo(Triple) {
8268 NoAsmVariants = true;
8271 DoubleAlign = LongDoubleAlign = 32;
8272 SizeType = UnsignedInt;
8273 PtrDiffType = SignedInt;
8274 IntPtrType = SignedInt;
8275 WCharType = UnsignedChar;
8276 WIntType = UnsignedInt;
8277 UseZeroLengthBitfieldAlignment = true;
8278 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
8279 "-f64:32-a:0:32-n32");
8281 void getTargetDefines(const LangOptions &Opts,
8282 MacroBuilder &Builder) const override {
8283 Builder.defineMacro("__XS1B__");
8285 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8286 return llvm::makeArrayRef(BuiltinInfo,
8287 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin);
8289 BuiltinVaListKind getBuiltinVaListKind() const override {
8290 return TargetInfo::VoidPtrBuiltinVaList;
8292 const char *getClobbers() const override {
8295 ArrayRef<const char *> getGCCRegNames() const override {
8296 static const char * const GCCRegNames[] = {
8297 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8298 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
8300 return llvm::makeArrayRef(GCCRegNames);
8302 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8305 bool validateAsmConstraint(const char *&Name,
8306 TargetInfo::ConstraintInfo &Info) const override {
8309 int getEHDataRegisterNumber(unsigned RegNo) const override {
8310 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
8311 return (RegNo < 2)? RegNo : -1;
8313 bool allowsLargerPreferedTypeAlignment() const override {
8318 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
8319 #define BUILTIN(ID, TYPE, ATTRS) \
8320 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8321 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8322 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8323 #include "clang/Basic/BuiltinsXCore.def"
8326 // x86_32 Android target
8327 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
8329 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8330 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) {
8332 LongDoubleWidth = 64;
8333 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
8337 // x86_64 Android target
8338 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
8340 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8341 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) {
8342 LongDoubleFormat = &llvm::APFloat::IEEEquad();
8345 bool useFloat128ManglingForLongDouble() const override {
8350 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes
8351 class RenderScript32TargetInfo : public ARMleTargetInfo {
8353 RenderScript32TargetInfo(const llvm::Triple &Triple,
8354 const TargetOptions &Opts)
8355 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(),
8357 Triple.getEnvironmentName()),
8359 IsRenderScriptTarget = true;
8360 LongWidth = LongAlign = 64;
8362 void getTargetDefines(const LangOptions &Opts,
8363 MacroBuilder &Builder) const override {
8364 Builder.defineMacro("__RENDERSCRIPT__");
8365 ARMleTargetInfo::getTargetDefines(Opts, Builder);
8369 // 64-bit RenderScript is aarch64
8370 class RenderScript64TargetInfo : public AArch64leTargetInfo {
8372 RenderScript64TargetInfo(const llvm::Triple &Triple,
8373 const TargetOptions &Opts)
8374 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(),
8376 Triple.getEnvironmentName()),
8378 IsRenderScriptTarget = true;
8381 void getTargetDefines(const LangOptions &Opts,
8382 MacroBuilder &Builder) const override {
8383 Builder.defineMacro("__RENDERSCRIPT__");
8384 AArch64leTargetInfo::getTargetDefines(Opts, Builder);
8388 } // end anonymous namespace
8390 //===----------------------------------------------------------------------===//
8392 //===----------------------------------------------------------------------===//
8394 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
8395 const TargetOptions &Opts) {
8396 llvm::Triple::OSType os = Triple.getOS();
8398 switch (Triple.getArch()) {
8402 case llvm::Triple::xcore:
8403 return new XCoreTargetInfo(Triple, Opts);
8405 case llvm::Triple::hexagon:
8406 return new HexagonTargetInfo(Triple, Opts);
8408 case llvm::Triple::lanai:
8409 return new LanaiTargetInfo(Triple, Opts);
8411 case llvm::Triple::aarch64:
8412 if (Triple.isOSDarwin())
8413 return new DarwinAArch64TargetInfo(Triple, Opts);
8416 case llvm::Triple::CloudABI:
8417 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts);
8418 case llvm::Triple::FreeBSD:
8419 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
8420 case llvm::Triple::Fuchsia:
8421 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts);
8422 case llvm::Triple::Linux:
8423 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts);
8424 case llvm::Triple::NetBSD:
8425 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
8427 return new AArch64leTargetInfo(Triple, Opts);
8430 case llvm::Triple::aarch64_be:
8432 case llvm::Triple::FreeBSD:
8433 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
8434 case llvm::Triple::Fuchsia:
8435 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts);
8436 case llvm::Triple::Linux:
8437 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts);
8438 case llvm::Triple::NetBSD:
8439 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
8441 return new AArch64beTargetInfo(Triple, Opts);
8444 case llvm::Triple::arm:
8445 case llvm::Triple::thumb:
8446 if (Triple.isOSBinFormatMachO())
8447 return new DarwinARMTargetInfo(Triple, Opts);
8450 case llvm::Triple::CloudABI:
8451 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts);
8452 case llvm::Triple::Linux:
8453 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts);
8454 case llvm::Triple::FreeBSD:
8455 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
8456 case llvm::Triple::Fuchsia:
8457 return new FuchsiaTargetInfo<ARMleTargetInfo>(Triple, Opts);
8458 case llvm::Triple::NetBSD:
8459 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
8460 case llvm::Triple::OpenBSD:
8461 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
8462 case llvm::Triple::Bitrig:
8463 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts);
8464 case llvm::Triple::RTEMS:
8465 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts);
8466 case llvm::Triple::NaCl:
8467 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts);
8468 case llvm::Triple::Win32:
8469 switch (Triple.getEnvironment()) {
8470 case llvm::Triple::Cygnus:
8471 return new CygwinARMTargetInfo(Triple, Opts);
8472 case llvm::Triple::GNU:
8473 return new MinGWARMTargetInfo(Triple, Opts);
8474 case llvm::Triple::Itanium:
8475 return new ItaniumWindowsARMleTargetInfo(Triple, Opts);
8476 case llvm::Triple::MSVC:
8477 default: // Assume MSVC for unknown environments
8478 return new MicrosoftARMleTargetInfo(Triple, Opts);
8481 return new ARMleTargetInfo(Triple, Opts);
8484 case llvm::Triple::armeb:
8485 case llvm::Triple::thumbeb:
8486 if (Triple.isOSDarwin())
8487 return new DarwinARMTargetInfo(Triple, Opts);
8490 case llvm::Triple::Linux:
8491 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8492 case llvm::Triple::FreeBSD:
8493 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8494 case llvm::Triple::Fuchsia:
8495 return new FuchsiaTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8496 case llvm::Triple::NetBSD:
8497 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8498 case llvm::Triple::OpenBSD:
8499 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8500 case llvm::Triple::Bitrig:
8501 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8502 case llvm::Triple::RTEMS:
8503 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8504 case llvm::Triple::NaCl:
8505 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8507 return new ARMbeTargetInfo(Triple, Opts);
8510 case llvm::Triple::bpfeb:
8511 case llvm::Triple::bpfel:
8512 return new BPFTargetInfo(Triple, Opts);
8514 case llvm::Triple::msp430:
8515 return new MSP430TargetInfo(Triple, Opts);
8517 case llvm::Triple::mips:
8519 case llvm::Triple::Linux:
8520 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
8521 case llvm::Triple::RTEMS:
8522 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
8523 case llvm::Triple::FreeBSD:
8524 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8525 case llvm::Triple::NetBSD:
8526 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8528 return new MipsTargetInfo(Triple, Opts);
8531 case llvm::Triple::mipsel:
8533 case llvm::Triple::Linux:
8534 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
8535 case llvm::Triple::RTEMS:
8536 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
8537 case llvm::Triple::FreeBSD:
8538 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8539 case llvm::Triple::NetBSD:
8540 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8541 case llvm::Triple::NaCl:
8542 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts);
8544 return new MipsTargetInfo(Triple, Opts);
8547 case llvm::Triple::mips64:
8549 case llvm::Triple::Linux:
8550 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
8551 case llvm::Triple::RTEMS:
8552 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
8553 case llvm::Triple::FreeBSD:
8554 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8555 case llvm::Triple::NetBSD:
8556 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8557 case llvm::Triple::OpenBSD:
8558 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8560 return new MipsTargetInfo(Triple, Opts);
8563 case llvm::Triple::mips64el:
8565 case llvm::Triple::Linux:
8566 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
8567 case llvm::Triple::RTEMS:
8568 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
8569 case llvm::Triple::FreeBSD:
8570 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8571 case llvm::Triple::NetBSD:
8572 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8573 case llvm::Triple::OpenBSD:
8574 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8576 return new MipsTargetInfo(Triple, Opts);
8579 case llvm::Triple::le32:
8581 case llvm::Triple::NaCl:
8582 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts);
8587 case llvm::Triple::le64:
8588 return new Le64TargetInfo(Triple, Opts);
8590 case llvm::Triple::ppc:
8591 if (Triple.isOSDarwin())
8592 return new DarwinPPC32TargetInfo(Triple, Opts);
8594 case llvm::Triple::Linux:
8595 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts);
8596 case llvm::Triple::FreeBSD:
8597 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
8598 case llvm::Triple::NetBSD:
8599 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
8600 case llvm::Triple::OpenBSD:
8601 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
8602 case llvm::Triple::RTEMS:
8603 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts);
8605 return new PPC32TargetInfo(Triple, Opts);
8608 case llvm::Triple::ppc64:
8609 if (Triple.isOSDarwin())
8610 return new DarwinPPC64TargetInfo(Triple, Opts);
8612 case llvm::Triple::Linux:
8613 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
8614 case llvm::Triple::Lv2:
8615 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts);
8616 case llvm::Triple::FreeBSD:
8617 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
8618 case llvm::Triple::NetBSD:
8619 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
8621 return new PPC64TargetInfo(Triple, Opts);
8624 case llvm::Triple::ppc64le:
8626 case llvm::Triple::Linux:
8627 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
8628 case llvm::Triple::NetBSD:
8629 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
8631 return new PPC64TargetInfo(Triple, Opts);
8634 case llvm::Triple::nvptx:
8635 return new NVPTX32TargetInfo(Triple, Opts);
8636 case llvm::Triple::nvptx64:
8637 return new NVPTX64TargetInfo(Triple, Opts);
8639 case llvm::Triple::amdgcn:
8640 case llvm::Triple::r600:
8641 return new AMDGPUTargetInfo(Triple, Opts);
8643 case llvm::Triple::sparc:
8645 case llvm::Triple::Linux:
8646 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8647 case llvm::Triple::Solaris:
8648 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8649 case llvm::Triple::NetBSD:
8650 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8651 case llvm::Triple::OpenBSD:
8652 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8653 case llvm::Triple::RTEMS:
8654 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8656 return new SparcV8TargetInfo(Triple, Opts);
8659 // The 'sparcel' architecture copies all the above cases except for Solaris.
8660 case llvm::Triple::sparcel:
8662 case llvm::Triple::Linux:
8663 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
8664 case llvm::Triple::NetBSD:
8665 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
8666 case llvm::Triple::OpenBSD:
8667 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
8668 case llvm::Triple::RTEMS:
8669 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
8671 return new SparcV8elTargetInfo(Triple, Opts);
8674 case llvm::Triple::sparcv9:
8676 case llvm::Triple::Linux:
8677 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8678 case llvm::Triple::Solaris:
8679 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8680 case llvm::Triple::NetBSD:
8681 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8682 case llvm::Triple::OpenBSD:
8683 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8684 case llvm::Triple::FreeBSD:
8685 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8687 return new SparcV9TargetInfo(Triple, Opts);
8690 case llvm::Triple::systemz:
8692 case llvm::Triple::Linux:
8693 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts);
8695 return new SystemZTargetInfo(Triple, Opts);
8698 case llvm::Triple::tce:
8699 return new TCETargetInfo(Triple, Opts);
8701 case llvm::Triple::tcele:
8702 return new TCELETargetInfo(Triple, Opts);
8704 case llvm::Triple::x86:
8705 if (Triple.isOSDarwin())
8706 return new DarwinI386TargetInfo(Triple, Opts);
8709 case llvm::Triple::CloudABI:
8710 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts);
8711 case llvm::Triple::Linux: {
8712 switch (Triple.getEnvironment()) {
8714 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts);
8715 case llvm::Triple::Android:
8716 return new AndroidX86_32TargetInfo(Triple, Opts);
8719 case llvm::Triple::DragonFly:
8720 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
8721 case llvm::Triple::NetBSD:
8722 return new NetBSDI386TargetInfo(Triple, Opts);
8723 case llvm::Triple::OpenBSD:
8724 return new OpenBSDI386TargetInfo(Triple, Opts);
8725 case llvm::Triple::Bitrig:
8726 return new BitrigI386TargetInfo(Triple, Opts);
8727 case llvm::Triple::FreeBSD:
8728 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
8729 case llvm::Triple::Fuchsia:
8730 return new FuchsiaTargetInfo<X86_32TargetInfo>(Triple, Opts);
8731 case llvm::Triple::KFreeBSD:
8732 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
8733 case llvm::Triple::Minix:
8734 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts);
8735 case llvm::Triple::Solaris:
8736 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts);
8737 case llvm::Triple::Win32: {
8738 switch (Triple.getEnvironment()) {
8739 case llvm::Triple::Cygnus:
8740 return new CygwinX86_32TargetInfo(Triple, Opts);
8741 case llvm::Triple::GNU:
8742 return new MinGWX86_32TargetInfo(Triple, Opts);
8743 case llvm::Triple::Itanium:
8744 case llvm::Triple::MSVC:
8745 default: // Assume MSVC for unknown environments
8746 return new MicrosoftX86_32TargetInfo(Triple, Opts);
8749 case llvm::Triple::Haiku:
8750 return new HaikuX86_32TargetInfo(Triple, Opts);
8751 case llvm::Triple::RTEMS:
8752 return new RTEMSX86_32TargetInfo(Triple, Opts);
8753 case llvm::Triple::NaCl:
8754 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts);
8755 case llvm::Triple::ELFIAMCU:
8756 return new MCUX86_32TargetInfo(Triple, Opts);
8758 return new X86_32TargetInfo(Triple, Opts);
8761 case llvm::Triple::x86_64:
8762 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
8763 return new DarwinX86_64TargetInfo(Triple, Opts);
8766 case llvm::Triple::CloudABI:
8767 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts);
8768 case llvm::Triple::Linux: {
8769 switch (Triple.getEnvironment()) {
8771 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts);
8772 case llvm::Triple::Android:
8773 return new AndroidX86_64TargetInfo(Triple, Opts);
8776 case llvm::Triple::DragonFly:
8777 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
8778 case llvm::Triple::NetBSD:
8779 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
8780 case llvm::Triple::OpenBSD:
8781 return new OpenBSDX86_64TargetInfo(Triple, Opts);
8782 case llvm::Triple::Bitrig:
8783 return new BitrigX86_64TargetInfo(Triple, Opts);
8784 case llvm::Triple::FreeBSD:
8785 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
8786 case llvm::Triple::Fuchsia:
8787 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts);
8788 case llvm::Triple::KFreeBSD:
8789 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
8790 case llvm::Triple::Solaris:
8791 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts);
8792 case llvm::Triple::Win32: {
8793 switch (Triple.getEnvironment()) {
8794 case llvm::Triple::Cygnus:
8795 return new CygwinX86_64TargetInfo(Triple, Opts);
8796 case llvm::Triple::GNU:
8797 return new MinGWX86_64TargetInfo(Triple, Opts);
8798 case llvm::Triple::MSVC:
8799 default: // Assume MSVC for unknown environments
8800 return new MicrosoftX86_64TargetInfo(Triple, Opts);
8803 case llvm::Triple::Haiku:
8804 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts);
8805 case llvm::Triple::NaCl:
8806 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts);
8807 case llvm::Triple::PS4:
8808 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts);
8810 return new X86_64TargetInfo(Triple, Opts);
8813 case llvm::Triple::spir: {
8814 if (Triple.getOS() != llvm::Triple::UnknownOS ||
8815 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
8817 return new SPIR32TargetInfo(Triple, Opts);
8819 case llvm::Triple::spir64: {
8820 if (Triple.getOS() != llvm::Triple::UnknownOS ||
8821 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
8823 return new SPIR64TargetInfo(Triple, Opts);
8825 case llvm::Triple::wasm32:
8826 if (!(Triple == llvm::Triple("wasm32-unknown-unknown")))
8828 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts);
8829 case llvm::Triple::wasm64:
8830 if (!(Triple == llvm::Triple("wasm64-unknown-unknown")))
8832 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts);
8834 case llvm::Triple::renderscript32:
8835 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts);
8836 case llvm::Triple::renderscript64:
8837 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts);
8841 /// CreateTargetInfo - Return the target info object for the specified target
8844 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
8845 const std::shared_ptr<TargetOptions> &Opts) {
8846 llvm::Triple Triple(Opts->Triple);
8848 // Construct the target
8849 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts));
8851 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
8854 Target->TargetOpts = Opts;
8856 // Set the target CPU if specified.
8857 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
8858 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
8862 // Set the target ABI if specified.
8863 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
8864 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
8868 // Set the fp math unit.
8869 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
8870 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
8874 // Compute the default target features, we need the target to handle this
8875 // because features may have dependencies on one another.
8876 llvm::StringMap<bool> Features;
8877 if (!Target->initFeatureMap(Features, Diags, Opts->CPU,
8878 Opts->FeaturesAsWritten))
8881 // Add the features to the compile options.
8882 Opts->Features.clear();
8883 for (const auto &F : Features)
8884 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str());
8886 if (!Target->handleTargetFeatures(Opts->Features, Diags))
8889 Target->setSupportedOpenCLOpts();
8890 Target->setOpenCLExtensionOpts();
8892 if (!Target->validateTarget(Diags))
8895 return Target.release();