1 //===--- Targets.cpp - Implement target feature support -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "clang/Basic/Version.h"
23 #include "llvm/ADT/APFloat.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/ADT/Triple.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/TargetParser.h"
35 using namespace clang;
37 //===----------------------------------------------------------------------===//
38 // Common code shared among targets.
39 //===----------------------------------------------------------------------===//
41 /// DefineStd - Define a macro name and standard variants. For example if
42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
45 const LangOptions &Opts) {
46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
49 // in the user's namespace.
51 Builder.defineMacro(MacroName);
54 Builder.defineMacro("__" + MacroName);
57 Builder.defineMacro("__" + MacroName + "__");
60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
62 Builder.defineMacro("__" + CPUName);
63 Builder.defineMacro("__" + CPUName + "__");
65 Builder.defineMacro("__tune_" + CPUName + "__");
68 //===----------------------------------------------------------------------===//
69 // Defines specific to certain operating systems.
70 //===----------------------------------------------------------------------===//
73 template<typename TgtInfo>
74 class OSTargetInfo : public TgtInfo {
76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
77 MacroBuilder &Builder) const=0;
79 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
80 void getTargetDefines(const LangOptions &Opts,
81 MacroBuilder &Builder) const override {
82 TgtInfo::getTargetDefines(Opts, Builder);
83 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
89 template <typename Target>
90 class CloudABITargetInfo : public OSTargetInfo<Target> {
92 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
93 MacroBuilder &Builder) const override {
94 Builder.defineMacro("__CloudABI__");
95 Builder.defineMacro("__ELF__");
97 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
98 Builder.defineMacro("__STDC_ISO_10646__", "201206L");
99 Builder.defineMacro("__STDC_UTF_16__");
100 Builder.defineMacro("__STDC_UTF_32__");
104 CloudABITargetInfo(const llvm::Triple &Triple)
105 : OSTargetInfo<Target>(Triple) {
106 this->UserLabelPrefix = "";
110 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
111 const llvm::Triple &Triple,
112 StringRef &PlatformName,
113 VersionTuple &PlatformMinVersion) {
114 Builder.defineMacro("__APPLE_CC__", "6000");
115 Builder.defineMacro("__APPLE__");
116 Builder.defineMacro("OBJC_NEW_PROPERTIES");
117 // AddressSanitizer doesn't play well with source fortification, which is on
118 // by default on Darwin.
119 if (Opts.Sanitize.has(SanitizerKind::Address))
120 Builder.defineMacro("_FORTIFY_SOURCE", "0");
122 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode.
124 // __weak is always defined, for use in blocks and with objc pointers.
125 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
126 Builder.defineMacro("__strong", "");
127 Builder.defineMacro("__unsafe_unretained", "");
131 Builder.defineMacro("__STATIC__");
133 Builder.defineMacro("__DYNAMIC__");
135 if (Opts.POSIXThreads)
136 Builder.defineMacro("_REENTRANT");
138 // Get the platform type and version number from the triple.
139 unsigned Maj, Min, Rev;
140 if (Triple.isMacOSX()) {
141 Triple.getMacOSXVersion(Maj, Min, Rev);
142 PlatformName = "macosx";
144 Triple.getOSVersion(Maj, Min, Rev);
145 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
148 // If -target arch-pc-win32-macho option specified, we're
149 // generating code for Win32 ABI. No need to emit
150 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
151 if (PlatformName == "win32") {
152 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
156 // Set the appropriate OS version define.
157 if (Triple.isiOS()) {
158 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
161 Str[1] = '0' + (Min / 10);
162 Str[2] = '0' + (Min % 10);
163 Str[3] = '0' + (Rev / 10);
164 Str[4] = '0' + (Rev % 10);
167 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str);
169 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
172 } else if (Triple.isWatchOS()) {
173 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
176 Str[1] = '0' + (Min / 10);
177 Str[2] = '0' + (Min % 10);
178 Str[3] = '0' + (Rev / 10);
179 Str[4] = '0' + (Rev % 10);
181 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str);
182 } else if (Triple.isMacOSX()) {
183 // Note that the Driver allows versions which aren't representable in the
184 // define (because we only get a single digit for the minor and micro
185 // revision numbers). So, we limit them to the maximum representable
187 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
189 if (Maj < 10 || (Maj == 10 && Min < 10)) {
190 Str[0] = '0' + (Maj / 10);
191 Str[1] = '0' + (Maj % 10);
192 Str[2] = '0' + std::min(Min, 9U);
193 Str[3] = '0' + std::min(Rev, 9U);
196 // Handle versions > 10.9.
197 Str[0] = '0' + (Maj / 10);
198 Str[1] = '0' + (Maj % 10);
199 Str[2] = '0' + (Min / 10);
200 Str[3] = '0' + (Min % 10);
201 Str[4] = '0' + (Rev / 10);
202 Str[5] = '0' + (Rev % 10);
205 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
208 // Tell users about the kernel if there is one.
209 if (Triple.isOSDarwin())
210 Builder.defineMacro("__MACH__");
212 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
215 template<typename Target>
216 class DarwinTargetInfo : public OSTargetInfo<Target> {
218 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
219 MacroBuilder &Builder) const override {
220 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
221 this->PlatformMinVersion);
225 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
226 // By default, no TLS, and we whitelist permitted architecture/OS
228 this->TLSSupported = false;
230 if (Triple.isMacOSX())
231 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7);
232 else if (Triple.isiOS()) {
233 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards.
234 if (Triple.getArch() == llvm::Triple::x86_64 ||
235 Triple.getArch() == llvm::Triple::aarch64)
236 this->TLSSupported = !Triple.isOSVersionLT(8);
237 else if (Triple.getArch() == llvm::Triple::x86 ||
238 Triple.getArch() == llvm::Triple::arm ||
239 Triple.getArch() == llvm::Triple::thumb)
240 this->TLSSupported = !Triple.isOSVersionLT(9);
241 } else if (Triple.isWatchOS())
242 this->TLSSupported = !Triple.isOSVersionLT(2);
244 this->MCountName = "\01mcount";
247 std::string isValidSectionSpecifier(StringRef SR) const override {
248 // Let MCSectionMachO validate this.
249 StringRef Segment, Section;
250 unsigned TAA, StubSize;
252 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
253 TAA, HasTAA, StubSize);
256 const char *getStaticInitSectionSpecifier() const override {
257 // FIXME: We should return 0 when building kexts.
258 return "__TEXT,__StaticInit,regular,pure_instructions";
261 /// Darwin does not support protected visibility. Darwin's "default"
262 /// is very similar to ELF's "protected"; Darwin requires a "weak"
263 /// attribute on declarations that can be dynamically replaced.
264 bool hasProtectedVisibility() const override {
270 // DragonFlyBSD Target
271 template<typename Target>
272 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
274 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
275 MacroBuilder &Builder) const override {
276 // DragonFly defines; list based off of gcc output
277 Builder.defineMacro("__DragonFly__");
278 Builder.defineMacro("__DragonFly_cc_version", "100001");
279 Builder.defineMacro("__ELF__");
280 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
281 Builder.defineMacro("__tune_i386__");
282 DefineStd(Builder, "unix", Opts);
285 DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
286 : OSTargetInfo<Target>(Triple) {
287 this->UserLabelPrefix = "";
289 switch (Triple.getArch()) {
291 case llvm::Triple::x86:
292 case llvm::Triple::x86_64:
293 this->MCountName = ".mcount";
300 template<typename Target>
301 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
303 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
304 MacroBuilder &Builder) const override {
305 // FreeBSD defines; list based off of gcc output
307 unsigned Release = Triple.getOSMajorVersion();
311 Builder.defineMacro("__FreeBSD__", Twine(Release));
312 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
313 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
314 DefineStd(Builder, "unix", Opts);
315 Builder.defineMacro("__ELF__");
317 // On FreeBSD, wchar_t contains the number of the code point as
318 // used by the character set of the locale. These character sets are
319 // not necessarily a superset of ASCII.
321 // FIXME: This is wrong; the macro refers to the numerical values
322 // of wchar_t *literals*, which are not locale-dependent. However,
323 // FreeBSD systems apparently depend on us getting this wrong, and
324 // setting this to 1 is conforming even if all the basic source
325 // character literals have the same encoding as char and wchar_t.
326 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
329 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
330 this->UserLabelPrefix = "";
332 switch (Triple.getArch()) {
334 case llvm::Triple::x86:
335 case llvm::Triple::x86_64:
336 this->MCountName = ".mcount";
338 case llvm::Triple::mips:
339 case llvm::Triple::mipsel:
340 case llvm::Triple::ppc:
341 case llvm::Triple::ppc64:
342 case llvm::Triple::ppc64le:
343 this->MCountName = "_mcount";
345 case llvm::Triple::arm:
346 this->MCountName = "__mcount";
352 // GNU/kFreeBSD Target
353 template<typename Target>
354 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
356 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
357 MacroBuilder &Builder) const override {
358 // GNU/kFreeBSD defines; list based off of gcc output
360 DefineStd(Builder, "unix", Opts);
361 Builder.defineMacro("__FreeBSD_kernel__");
362 Builder.defineMacro("__GLIBC__");
363 Builder.defineMacro("__ELF__");
364 if (Opts.POSIXThreads)
365 Builder.defineMacro("_REENTRANT");
367 Builder.defineMacro("_GNU_SOURCE");
370 KFreeBSDTargetInfo(const llvm::Triple &Triple)
371 : OSTargetInfo<Target>(Triple) {
372 this->UserLabelPrefix = "";
377 template<typename Target>
378 class MinixTargetInfo : public OSTargetInfo<Target> {
380 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
381 MacroBuilder &Builder) const override {
384 Builder.defineMacro("__minix", "3");
385 Builder.defineMacro("_EM_WSIZE", "4");
386 Builder.defineMacro("_EM_PSIZE", "4");
387 Builder.defineMacro("_EM_SSIZE", "2");
388 Builder.defineMacro("_EM_LSIZE", "4");
389 Builder.defineMacro("_EM_FSIZE", "4");
390 Builder.defineMacro("_EM_DSIZE", "8");
391 Builder.defineMacro("__ELF__");
392 DefineStd(Builder, "unix", Opts);
395 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
396 this->UserLabelPrefix = "";
401 template<typename Target>
402 class LinuxTargetInfo : public OSTargetInfo<Target> {
404 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
405 MacroBuilder &Builder) const override {
406 // Linux defines; list based off of gcc output
407 DefineStd(Builder, "unix", Opts);
408 DefineStd(Builder, "linux", Opts);
409 Builder.defineMacro("__gnu_linux__");
410 Builder.defineMacro("__ELF__");
411 if (Triple.isAndroid()) {
412 Builder.defineMacro("__ANDROID__", "1");
413 unsigned Maj, Min, Rev;
414 Triple.getEnvironmentVersion(Maj, Min, Rev);
415 this->PlatformName = "android";
416 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
418 if (Opts.POSIXThreads)
419 Builder.defineMacro("_REENTRANT");
421 Builder.defineMacro("_GNU_SOURCE");
424 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
425 this->UserLabelPrefix = "";
426 this->WIntType = TargetInfo::UnsignedInt;
428 switch (Triple.getArch()) {
431 case llvm::Triple::ppc:
432 case llvm::Triple::ppc64:
433 case llvm::Triple::ppc64le:
434 this->MCountName = "_mcount";
439 const char *getStaticInitSectionSpecifier() const override {
440 return ".text.startup";
445 template<typename Target>
446 class NetBSDTargetInfo : public OSTargetInfo<Target> {
448 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
449 MacroBuilder &Builder) const override {
450 // NetBSD defines; list based off of gcc output
451 Builder.defineMacro("__NetBSD__");
452 Builder.defineMacro("__unix__");
453 Builder.defineMacro("__ELF__");
454 if (Opts.POSIXThreads)
455 Builder.defineMacro("_POSIX_THREADS");
457 switch (Triple.getArch()) {
460 case llvm::Triple::arm:
461 case llvm::Triple::armeb:
462 case llvm::Triple::thumb:
463 case llvm::Triple::thumbeb:
464 Builder.defineMacro("__ARM_DWARF_EH__");
469 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
470 this->UserLabelPrefix = "";
471 this->MCountName = "_mcount";
476 template<typename Target>
477 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
479 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
480 MacroBuilder &Builder) const override {
481 // OpenBSD defines; list based off of gcc output
483 Builder.defineMacro("__OpenBSD__");
484 DefineStd(Builder, "unix", Opts);
485 Builder.defineMacro("__ELF__");
486 if (Opts.POSIXThreads)
487 Builder.defineMacro("_REENTRANT");
490 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
491 this->UserLabelPrefix = "";
492 this->TLSSupported = false;
494 switch (Triple.getArch()) {
496 case llvm::Triple::x86:
497 case llvm::Triple::x86_64:
498 case llvm::Triple::arm:
499 case llvm::Triple::sparc:
500 this->MCountName = "__mcount";
502 case llvm::Triple::mips64:
503 case llvm::Triple::mips64el:
504 case llvm::Triple::ppc:
505 case llvm::Triple::sparcv9:
506 this->MCountName = "_mcount";
513 template<typename Target>
514 class BitrigTargetInfo : public OSTargetInfo<Target> {
516 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
517 MacroBuilder &Builder) const override {
518 // Bitrig defines; list based off of gcc output
520 Builder.defineMacro("__Bitrig__");
521 DefineStd(Builder, "unix", Opts);
522 Builder.defineMacro("__ELF__");
523 if (Opts.POSIXThreads)
524 Builder.defineMacro("_REENTRANT");
526 switch (Triple.getArch()) {
529 case llvm::Triple::arm:
530 case llvm::Triple::armeb:
531 case llvm::Triple::thumb:
532 case llvm::Triple::thumbeb:
533 Builder.defineMacro("__ARM_DWARF_EH__");
538 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
539 this->UserLabelPrefix = "";
540 this->MCountName = "__mcount";
545 template<typename Target>
546 class PSPTargetInfo : public OSTargetInfo<Target> {
548 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
549 MacroBuilder &Builder) const override {
550 // PSP defines; list based on the output of the pspdev gcc toolchain.
551 Builder.defineMacro("PSP");
552 Builder.defineMacro("_PSP");
553 Builder.defineMacro("__psp__");
554 Builder.defineMacro("__ELF__");
557 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
558 this->UserLabelPrefix = "";
563 template<typename Target>
564 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
566 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
567 MacroBuilder &Builder) const override {
569 Builder.defineMacro("__PPC__");
570 Builder.defineMacro("__PPU__");
571 Builder.defineMacro("__CELLOS_LV2__");
572 Builder.defineMacro("__ELF__");
573 Builder.defineMacro("__LP32__");
574 Builder.defineMacro("_ARCH_PPC64");
575 Builder.defineMacro("__powerpc64__");
578 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
579 this->UserLabelPrefix = "";
580 this->LongWidth = this->LongAlign = 32;
581 this->PointerWidth = this->PointerAlign = 32;
582 this->IntMaxType = TargetInfo::SignedLongLong;
583 this->Int64Type = TargetInfo::SignedLongLong;
584 this->SizeType = TargetInfo::UnsignedInt;
585 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64";
589 template <typename Target>
590 class PS4OSTargetInfo : public OSTargetInfo<Target> {
592 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
593 MacroBuilder &Builder) const override {
594 Builder.defineMacro("__FreeBSD__", "9");
595 Builder.defineMacro("__FreeBSD_cc_version", "900001");
596 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
597 DefineStd(Builder, "unix", Opts);
598 Builder.defineMacro("__ELF__");
599 Builder.defineMacro("__PS4__");
602 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
603 this->WCharType = this->UnsignedShort;
605 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits).
606 this->MaxTLSAlign = 256;
607 this->UserLabelPrefix = "";
609 switch (Triple.getArch()) {
611 case llvm::Triple::x86_64:
612 this->MCountName = ".mcount";
619 template<typename Target>
620 class SolarisTargetInfo : public OSTargetInfo<Target> {
622 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
623 MacroBuilder &Builder) const override {
624 DefineStd(Builder, "sun", Opts);
625 DefineStd(Builder, "unix", Opts);
626 Builder.defineMacro("__ELF__");
627 Builder.defineMacro("__svr4__");
628 Builder.defineMacro("__SVR4");
629 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
630 // newer, but to 500 for everything else. feature_test.h has a check to
631 // ensure that you are not using C99 with an old version of X/Open or C89
632 // with a new version.
634 Builder.defineMacro("_XOPEN_SOURCE", "600");
636 Builder.defineMacro("_XOPEN_SOURCE", "500");
638 Builder.defineMacro("__C99FEATURES__");
639 Builder.defineMacro("_LARGEFILE_SOURCE");
640 Builder.defineMacro("_LARGEFILE64_SOURCE");
641 Builder.defineMacro("__EXTENSIONS__");
642 Builder.defineMacro("_REENTRANT");
645 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
646 this->UserLabelPrefix = "";
647 this->WCharType = this->SignedInt;
648 // FIXME: WIntType should be SignedLong
653 template<typename Target>
654 class WindowsTargetInfo : public OSTargetInfo<Target> {
656 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
657 MacroBuilder &Builder) const override {
658 Builder.defineMacro("_WIN32");
660 void getVisualStudioDefines(const LangOptions &Opts,
661 MacroBuilder &Builder) const {
662 if (Opts.CPlusPlus) {
664 Builder.defineMacro("_CPPRTTI");
666 if (Opts.CXXExceptions)
667 Builder.defineMacro("_CPPUNWIND");
671 Builder.defineMacro("__BOOL_DEFINED");
673 if (!Opts.CharIsSigned)
674 Builder.defineMacro("_CHAR_UNSIGNED");
676 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
677 // but it works for now.
678 if (Opts.POSIXThreads)
679 Builder.defineMacro("_MT");
681 if (Opts.MSCompatibilityVersion) {
682 Builder.defineMacro("_MSC_VER",
683 Twine(Opts.MSCompatibilityVersion / 100000));
684 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
685 // FIXME We cannot encode the revision information into 32-bits
686 Builder.defineMacro("_MSC_BUILD", Twine(1));
688 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
689 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
692 if (Opts.MicrosoftExt) {
693 Builder.defineMacro("_MSC_EXTENSIONS");
695 if (Opts.CPlusPlus11) {
696 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
697 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
698 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
702 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
706 WindowsTargetInfo(const llvm::Triple &Triple)
707 : OSTargetInfo<Target>(Triple) {}
710 template <typename Target>
711 class NaClTargetInfo : public OSTargetInfo<Target> {
713 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
714 MacroBuilder &Builder) const override {
715 if (Opts.POSIXThreads)
716 Builder.defineMacro("_REENTRANT");
718 Builder.defineMacro("_GNU_SOURCE");
720 DefineStd(Builder, "unix", Opts);
721 Builder.defineMacro("__ELF__");
722 Builder.defineMacro("__native_client__");
726 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
727 this->UserLabelPrefix = "";
728 this->LongAlign = 32;
729 this->LongWidth = 32;
730 this->PointerAlign = 32;
731 this->PointerWidth = 32;
732 this->IntMaxType = TargetInfo::SignedLongLong;
733 this->Int64Type = TargetInfo::SignedLongLong;
734 this->DoubleAlign = 64;
735 this->LongDoubleWidth = 64;
736 this->LongDoubleAlign = 64;
737 this->LongLongWidth = 64;
738 this->LongLongAlign = 64;
739 this->SizeType = TargetInfo::UnsignedInt;
740 this->PtrDiffType = TargetInfo::SignedInt;
741 this->IntPtrType = TargetInfo::SignedInt;
742 // RegParmMax is inherited from the underlying architecture
743 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
744 if (Triple.getArch() == llvm::Triple::arm) {
745 // Handled in ARM's setABI().
746 } else if (Triple.getArch() == llvm::Triple::x86) {
747 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
748 } else if (Triple.getArch() == llvm::Triple::x86_64) {
749 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
750 } else if (Triple.getArch() == llvm::Triple::mipsel) {
751 // Handled on mips' setDataLayoutString.
753 assert(Triple.getArch() == llvm::Triple::le32);
754 this->DataLayoutString = "e-p:32:32-i64:64";
759 // WebAssembly target
760 template <typename Target>
761 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> {
762 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
763 MacroBuilder &Builder) const final {
764 // A common platform macro.
765 if (Opts.POSIXThreads)
766 Builder.defineMacro("_REENTRANT");
767 // Follow g++ convention and predefine _GNU_SOURCE for C++.
769 Builder.defineMacro("_GNU_SOURCE");
772 // As an optimization, group static init code together in a section.
773 const char *getStaticInitSectionSpecifier() const final {
774 return ".text.__startup";
778 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple)
779 : OSTargetInfo<Target>(Triple) {
780 this->MCountName = "__mcount";
781 this->UserLabelPrefix = "";
782 this->TheCXXABI.set(TargetCXXABI::WebAssembly);
786 //===----------------------------------------------------------------------===//
787 // Specific target implementations.
788 //===----------------------------------------------------------------------===//
790 // PPC abstract base class
791 class PPCTargetInfo : public TargetInfo {
792 static const Builtin::Info BuiltinInfo[];
793 static const char * const GCCRegNames[];
794 static const TargetInfo::GCCRegAlias GCCRegAliases[];
797 // Target cpu features.
811 PPCTargetInfo(const llvm::Triple &Triple)
812 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
813 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
814 HasBPERMD(false), HasExtDiv(false) {
815 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
816 SimdDefaultAlign = 128;
817 LongDoubleWidth = LongDoubleAlign = 128;
818 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
821 /// \brief Flags for architecture specific defines.
824 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
825 ArchDefinePpcgr = 1 << 1,
826 ArchDefinePpcsq = 1 << 2,
827 ArchDefine440 = 1 << 3,
828 ArchDefine603 = 1 << 4,
829 ArchDefine604 = 1 << 5,
830 ArchDefinePwr4 = 1 << 6,
831 ArchDefinePwr5 = 1 << 7,
832 ArchDefinePwr5x = 1 << 8,
833 ArchDefinePwr6 = 1 << 9,
834 ArchDefinePwr6x = 1 << 10,
835 ArchDefinePwr7 = 1 << 11,
836 ArchDefinePwr8 = 1 << 12,
837 ArchDefineA2 = 1 << 13,
838 ArchDefineA2q = 1 << 14
841 // Note: GCC recognizes the following additional cpus:
842 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
843 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
845 bool setCPU(const std::string &Name) override {
846 bool CPUKnown = llvm::StringSwitch<bool>(Name)
847 .Case("generic", true)
869 .Case("e500mc", true)
871 .Case("power3", true)
873 .Case("power4", true)
875 .Case("power5", true)
877 .Case("power5x", true)
879 .Case("power6", true)
881 .Case("power6x", true)
883 .Case("power7", true)
885 .Case("power8", true)
887 .Case("powerpc", true)
889 .Case("powerpc64", true)
891 .Case("powerpc64le", true)
892 .Case("ppc64le", true)
902 StringRef getABI() const override { return ABI; }
904 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
905 return llvm::makeArrayRef(BuiltinInfo,
906 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin);
909 bool isCLZForZeroUndef() const override { return false; }
911 void getTargetDefines(const LangOptions &Opts,
912 MacroBuilder &Builder) const override;
915 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
917 const std::vector<std::string> &FeaturesVec) const override;
919 bool handleTargetFeatures(std::vector<std::string> &Features,
920 DiagnosticsEngine &Diags) override;
921 bool hasFeature(StringRef Feature) const override;
922 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
923 bool Enabled) const override;
925 ArrayRef<const char *> getGCCRegNames() const override;
926 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
927 bool validateAsmConstraint(const char *&Name,
928 TargetInfo::ConstraintInfo &Info) const override {
930 default: return false;
933 case 'b': // Base register
934 case 'f': // Floating point register
935 Info.setAllowsRegister();
937 // FIXME: The following are added to allow parsing.
938 // I just took a guess at what the actions should be.
939 // Also, is more specific checking needed? I.e. specific registers?
940 case 'd': // Floating point register (containing 64-bit value)
941 case 'v': // Altivec vector register
942 Info.setAllowsRegister();
946 case 'd':// VSX vector register to hold vector double data
947 case 'f':// VSX vector register to hold vector float data
948 case 's':// VSX vector register to hold scalar float data
949 case 'a':// Any VSX register
950 case 'c':// An individual CR bit
955 Info.setAllowsRegister();
956 Name++; // Skip over 'w'.
958 case 'h': // `MQ', `CTR', or `LINK' register
959 case 'q': // `MQ' register
960 case 'c': // `CTR' register
961 case 'l': // `LINK' register
962 case 'x': // `CR' register (condition register) number 0
963 case 'y': // `CR' register (condition register)
964 case 'z': // `XER[CA]' carry bit (part of the XER register)
965 Info.setAllowsRegister();
967 case 'I': // Signed 16-bit constant
968 case 'J': // Unsigned 16-bit constant shifted left 16 bits
969 // (use `L' instead for SImode constants)
970 case 'K': // Unsigned 16-bit constant
971 case 'L': // Signed 16-bit constant shifted left 16 bits
972 case 'M': // Constant larger than 31
973 case 'N': // Exact power of 2
974 case 'P': // Constant whose negation is a signed 16-bit constant
975 case 'G': // Floating point constant that can be loaded into a
976 // register with one instruction per word
977 case 'H': // Integer/Floating point constant that can be loaded
978 // into a register using three instructions
980 case 'm': // Memory operand. Note that on PowerPC targets, m can
981 // include addresses that update the base register. It
982 // is therefore only safe to use `m' in an asm statement
983 // if that asm statement accesses the operand exactly once.
984 // The asm statement must also use `%U<opno>' as a
985 // placeholder for the "update" flag in the corresponding
986 // load or store instruction. For example:
987 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
989 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
990 // is not. Use es rather than m if you don't want the base
991 // register to be updated.
995 // es: A "stable" memory operand; that is, one which does not
996 // include any automodification of the base register. Unlike
997 // `m', this constraint can be used in asm statements that
998 // might access the operand several times, or that might not
1000 Info.setAllowsMemory();
1001 Name++; // Skip over 'e'.
1003 case 'Q': // Memory operand that is an offset from a register (it is
1004 // usually better to use `m' or `es' in asm statements)
1005 case 'Z': // Memory operand that is an indexed or indirect from a
1006 // register (it is usually better to use `m' or `es' in
1008 Info.setAllowsMemory();
1009 Info.setAllowsRegister();
1011 case 'R': // AIX TOC entry
1012 case 'a': // Address operand that is an indexed or indirect from a
1013 // register (`p' is preferable for asm statements)
1014 case 'S': // Constant suitable as a 64-bit mask operand
1015 case 'T': // Constant suitable as a 32-bit mask operand
1016 case 'U': // System V Release 4 small data area reference
1017 case 't': // AND masks that can be performed by two rldic{l, r}
1019 case 'W': // Vector constant that does not require memory
1020 case 'j': // Vector constant that is all zeros.
1026 std::string convertConstraint(const char *&Constraint) const override {
1028 switch (*Constraint) {
1031 // Two-character constraint; add "^" hint for later parsing.
1032 R = std::string("^") + std::string(Constraint, 2);
1036 return TargetInfo::convertConstraint(Constraint);
1040 const char *getClobbers() const override {
1043 int getEHDataRegisterNumber(unsigned RegNo) const override {
1044 if (RegNo == 0) return 3;
1045 if (RegNo == 1) return 4;
1049 bool hasSjLjLowering() const override {
1053 bool useFloat128ManglingForLongDouble() const override {
1054 return LongDoubleWidth == 128 &&
1055 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble &&
1056 getTriple().isOSBinFormatELF();
1060 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
1061 #define BUILTIN(ID, TYPE, ATTRS) \
1062 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1063 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1064 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1065 #include "clang/Basic/BuiltinsPPC.def"
1068 /// handleTargetFeatures - Perform initialization based on the user
1069 /// configured set of features.
1070 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1071 DiagnosticsEngine &Diags) {
1072 for (const auto &Feature : Features) {
1073 if (Feature == "+vsx") {
1075 } else if (Feature == "+bpermd") {
1077 } else if (Feature == "+extdiv") {
1079 } else if (Feature == "+power8-vector") {
1081 } else if (Feature == "+crypto") {
1083 } else if (Feature == "+direct-move") {
1084 HasDirectMove = true;
1085 } else if (Feature == "+qpx") {
1087 } else if (Feature == "+htm") {
1090 // TODO: Finish this list and add an assert that we've handled them
1097 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1098 /// #defines that are not tied to a specific subtarget.
1099 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1100 MacroBuilder &Builder) const {
1101 // Target identification.
1102 Builder.defineMacro("__ppc__");
1103 Builder.defineMacro("__PPC__");
1104 Builder.defineMacro("_ARCH_PPC");
1105 Builder.defineMacro("__powerpc__");
1106 Builder.defineMacro("__POWERPC__");
1107 if (PointerWidth == 64) {
1108 Builder.defineMacro("_ARCH_PPC64");
1109 Builder.defineMacro("__powerpc64__");
1110 Builder.defineMacro("__ppc64__");
1111 Builder.defineMacro("__PPC64__");
1114 // Target properties.
1115 if (getTriple().getArch() == llvm::Triple::ppc64le) {
1116 Builder.defineMacro("_LITTLE_ENDIAN");
1118 if (getTriple().getOS() != llvm::Triple::NetBSD &&
1119 getTriple().getOS() != llvm::Triple::OpenBSD)
1120 Builder.defineMacro("_BIG_ENDIAN");
1124 if (ABI == "elfv1" || ABI == "elfv1-qpx")
1125 Builder.defineMacro("_CALL_ELF", "1");
1127 Builder.defineMacro("_CALL_ELF", "2");
1129 // Subtarget options.
1130 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1131 Builder.defineMacro("__REGISTER_PREFIX__", "");
1133 // FIXME: Should be controlled by command line option.
1134 if (LongDoubleWidth == 128)
1135 Builder.defineMacro("__LONG_DOUBLE_128__");
1138 Builder.defineMacro("__VEC__", "10206");
1139 Builder.defineMacro("__ALTIVEC__");
1142 // CPU identification.
1143 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1144 .Case("440", ArchDefineName)
1145 .Case("450", ArchDefineName | ArchDefine440)
1146 .Case("601", ArchDefineName)
1147 .Case("602", ArchDefineName | ArchDefinePpcgr)
1148 .Case("603", ArchDefineName | ArchDefinePpcgr)
1149 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1150 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1151 .Case("604", ArchDefineName | ArchDefinePpcgr)
1152 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1153 .Case("620", ArchDefineName | ArchDefinePpcgr)
1154 .Case("630", ArchDefineName | ArchDefinePpcgr)
1155 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1156 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1157 .Case("750", ArchDefineName | ArchDefinePpcgr)
1158 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1160 .Case("a2", ArchDefineA2)
1161 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1162 .Case("pwr3", ArchDefinePpcgr)
1163 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1164 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1166 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1167 | ArchDefinePpcgr | ArchDefinePpcsq)
1168 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1169 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1170 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1171 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1173 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1174 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1175 | ArchDefinePpcgr | ArchDefinePpcsq)
1176 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1177 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1178 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1179 .Case("power3", ArchDefinePpcgr)
1180 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1181 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1183 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1184 | ArchDefinePpcgr | ArchDefinePpcsq)
1185 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1186 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1187 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1188 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1190 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1191 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1192 | ArchDefinePpcgr | ArchDefinePpcsq)
1193 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1194 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1195 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1196 .Default(ArchDefineNone);
1198 if (defs & ArchDefineName)
1199 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1200 if (defs & ArchDefinePpcgr)
1201 Builder.defineMacro("_ARCH_PPCGR");
1202 if (defs & ArchDefinePpcsq)
1203 Builder.defineMacro("_ARCH_PPCSQ");
1204 if (defs & ArchDefine440)
1205 Builder.defineMacro("_ARCH_440");
1206 if (defs & ArchDefine603)
1207 Builder.defineMacro("_ARCH_603");
1208 if (defs & ArchDefine604)
1209 Builder.defineMacro("_ARCH_604");
1210 if (defs & ArchDefinePwr4)
1211 Builder.defineMacro("_ARCH_PWR4");
1212 if (defs & ArchDefinePwr5)
1213 Builder.defineMacro("_ARCH_PWR5");
1214 if (defs & ArchDefinePwr5x)
1215 Builder.defineMacro("_ARCH_PWR5X");
1216 if (defs & ArchDefinePwr6)
1217 Builder.defineMacro("_ARCH_PWR6");
1218 if (defs & ArchDefinePwr6x)
1219 Builder.defineMacro("_ARCH_PWR6X");
1220 if (defs & ArchDefinePwr7)
1221 Builder.defineMacro("_ARCH_PWR7");
1222 if (defs & ArchDefinePwr8)
1223 Builder.defineMacro("_ARCH_PWR8");
1224 if (defs & ArchDefineA2)
1225 Builder.defineMacro("_ARCH_A2");
1226 if (defs & ArchDefineA2q) {
1227 Builder.defineMacro("_ARCH_A2Q");
1228 Builder.defineMacro("_ARCH_QP");
1231 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1232 Builder.defineMacro("__bg__");
1233 Builder.defineMacro("__THW_BLUEGENE__");
1234 Builder.defineMacro("__bgq__");
1235 Builder.defineMacro("__TOS_BGQ__");
1239 Builder.defineMacro("__VSX__");
1241 Builder.defineMacro("__POWER8_VECTOR__");
1243 Builder.defineMacro("__CRYPTO__");
1245 Builder.defineMacro("__HTM__");
1247 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1248 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1249 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1250 if (PointerWidth == 64)
1251 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1253 // FIXME: The following are not yet generated here by Clang, but are
1254 // generated by GCC:
1257 // __RECIP_PRECISION__
1258 // __APPLE_ALTIVEC__
1267 // __CMODEL_MEDIUM__
1274 // Handle explicit options being passed to the compiler here: if we've
1275 // explicitly turned off vsx and turned on power8-vector or direct-move then
1276 // go ahead and error since the customer has expressed a somewhat incompatible
1278 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
1279 const std::vector<std::string> &FeaturesVec) {
1281 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") !=
1282 FeaturesVec.end()) {
1283 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") !=
1284 FeaturesVec.end()) {
1285 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
1290 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") !=
1291 FeaturesVec.end()) {
1292 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
1301 bool PPCTargetInfo::initFeatureMap(
1302 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
1303 const std::vector<std::string> &FeaturesVec) const {
1304 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1314 .Case("ppc64", true)
1315 .Case("ppc64le", true)
1318 Features["qpx"] = (CPU == "a2q");
1319 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1320 .Case("ppc64le", true)
1323 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1324 .Case("ppc64le", true)
1327 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1328 .Case("ppc64le", true)
1332 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1333 .Case("ppc64le", true)
1337 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1338 .Case("ppc64le", true)
1341 Features["vsx"] = llvm::StringSwitch<bool>(CPU)
1342 .Case("ppc64le", true)
1347 if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
1350 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1353 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1354 return llvm::StringSwitch<bool>(Feature)
1355 .Case("powerpc", true)
1356 .Case("vsx", HasVSX)
1357 .Case("power8-vector", HasP8Vector)
1358 .Case("crypto", HasP8Crypto)
1359 .Case("direct-move", HasDirectMove)
1360 .Case("qpx", HasQPX)
1361 .Case("htm", HasHTM)
1362 .Case("bpermd", HasBPERMD)
1363 .Case("extdiv", HasExtDiv)
1367 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1368 StringRef Name, bool Enabled) const {
1369 // If we're enabling direct-move or power8-vector go ahead and enable vsx
1370 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user
1371 // incompatible options.
1373 if (Name == "vsx") {
1374 Features[Name] = true;
1375 } else if (Name == "direct-move") {
1376 Features[Name] = Features["vsx"] = true;
1377 } else if (Name == "power8-vector") {
1378 Features[Name] = Features["vsx"] = true;
1380 Features[Name] = true;
1383 if (Name == "vsx") {
1384 Features[Name] = Features["direct-move"] = Features["power8-vector"] =
1387 Features[Name] = false;
1392 const char * const PPCTargetInfo::GCCRegNames[] = {
1393 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1394 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1395 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1396 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1397 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1398 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1399 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1400 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1401 "mq", "lr", "ctr", "ap",
1402 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1404 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1405 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1406 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1407 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1409 "spe_acc", "spefscr",
1413 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const {
1414 return llvm::makeArrayRef(GCCRegNames);
1417 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1418 // While some of these aliases do map to different registers
1419 // they still share the same register name.
1430 { { "10" }, "r10" },
1431 { { "11" }, "r11" },
1432 { { "12" }, "r12" },
1433 { { "13" }, "r13" },
1434 { { "14" }, "r14" },
1435 { { "15" }, "r15" },
1436 { { "16" }, "r16" },
1437 { { "17" }, "r17" },
1438 { { "18" }, "r18" },
1439 { { "19" }, "r19" },
1440 { { "20" }, "r20" },
1441 { { "21" }, "r21" },
1442 { { "22" }, "r22" },
1443 { { "23" }, "r23" },
1444 { { "24" }, "r24" },
1445 { { "25" }, "r25" },
1446 { { "26" }, "r26" },
1447 { { "27" }, "r27" },
1448 { { "28" }, "r28" },
1449 { { "29" }, "r29" },
1450 { { "30" }, "r30" },
1451 { { "31" }, "r31" },
1452 { { "fr0" }, "f0" },
1453 { { "fr1" }, "f1" },
1454 { { "fr2" }, "f2" },
1455 { { "fr3" }, "f3" },
1456 { { "fr4" }, "f4" },
1457 { { "fr5" }, "f5" },
1458 { { "fr6" }, "f6" },
1459 { { "fr7" }, "f7" },
1460 { { "fr8" }, "f8" },
1461 { { "fr9" }, "f9" },
1462 { { "fr10" }, "f10" },
1463 { { "fr11" }, "f11" },
1464 { { "fr12" }, "f12" },
1465 { { "fr13" }, "f13" },
1466 { { "fr14" }, "f14" },
1467 { { "fr15" }, "f15" },
1468 { { "fr16" }, "f16" },
1469 { { "fr17" }, "f17" },
1470 { { "fr18" }, "f18" },
1471 { { "fr19" }, "f19" },
1472 { { "fr20" }, "f20" },
1473 { { "fr21" }, "f21" },
1474 { { "fr22" }, "f22" },
1475 { { "fr23" }, "f23" },
1476 { { "fr24" }, "f24" },
1477 { { "fr25" }, "f25" },
1478 { { "fr26" }, "f26" },
1479 { { "fr27" }, "f27" },
1480 { { "fr28" }, "f28" },
1481 { { "fr29" }, "f29" },
1482 { { "fr30" }, "f30" },
1483 { { "fr31" }, "f31" },
1484 { { "cc" }, "cr0" },
1487 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
1488 return llvm::makeArrayRef(GCCRegAliases);
1491 class PPC32TargetInfo : public PPCTargetInfo {
1493 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1494 DataLayoutString = "E-m:e-p:32:32-i64:64-n32";
1496 switch (getTriple().getOS()) {
1497 case llvm::Triple::Linux:
1498 case llvm::Triple::FreeBSD:
1499 case llvm::Triple::NetBSD:
1500 SizeType = UnsignedInt;
1501 PtrDiffType = SignedInt;
1502 IntPtrType = SignedInt;
1508 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1509 LongDoubleWidth = LongDoubleAlign = 64;
1510 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1513 // PPC32 supports atomics up to 4 bytes.
1514 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1517 BuiltinVaListKind getBuiltinVaListKind() const override {
1518 // This is the ELF definition, and is overridden by the Darwin sub-target
1519 return TargetInfo::PowerABIBuiltinVaList;
1523 // Note: ABI differences may eventually require us to have a separate
1524 // TargetInfo for little endian.
1525 class PPC64TargetInfo : public PPCTargetInfo {
1527 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1528 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1529 IntMaxType = SignedLong;
1530 Int64Type = SignedLong;
1532 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1533 DataLayoutString = "e-m:e-i64:64-n32:64";
1536 DataLayoutString = "E-m:e-i64:64-n32:64";
1540 switch (getTriple().getOS()) {
1541 case llvm::Triple::FreeBSD:
1542 LongDoubleWidth = LongDoubleAlign = 64;
1543 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1545 case llvm::Triple::NetBSD:
1546 IntMaxType = SignedLongLong;
1547 Int64Type = SignedLongLong;
1553 // PPC64 supports atomics up to 8 bytes.
1554 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1556 BuiltinVaListKind getBuiltinVaListKind() const override {
1557 return TargetInfo::CharPtrBuiltinVaList;
1559 // PPC64 Linux-specific ABI options.
1560 bool setABI(const std::string &Name) override {
1561 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1569 class DarwinPPC32TargetInfo :
1570 public DarwinTargetInfo<PPC32TargetInfo> {
1572 DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1573 : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1574 HasAlignMac68kSupport = true;
1575 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1576 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1578 SuitableAlign = 128;
1579 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32";
1581 BuiltinVaListKind getBuiltinVaListKind() const override {
1582 return TargetInfo::CharPtrBuiltinVaList;
1586 class DarwinPPC64TargetInfo :
1587 public DarwinTargetInfo<PPC64TargetInfo> {
1589 DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1590 : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1591 HasAlignMac68kSupport = true;
1592 SuitableAlign = 128;
1593 DataLayoutString = "E-m:o-i64:64-n32:64";
1597 static const unsigned NVPTXAddrSpaceMap[] = {
1600 4, // opencl_constant
1601 // FIXME: generic has to be added to the target
1602 0, // opencl_generic
1608 class NVPTXTargetInfo : public TargetInfo {
1609 static const char *const GCCRegNames[];
1610 static const Builtin::Info BuiltinInfo[];
1612 // The GPU profiles supported by the NVPTX backend
1623 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1625 TLSSupported = false;
1626 LongWidth = LongAlign = 64;
1627 AddrSpaceMap = &NVPTXAddrSpaceMap;
1628 UseAddrSpaceMapMangling = true;
1629 // Define available target features
1630 // These must be defined in sorted order!
1631 NoAsmVariants = true;
1632 // Set the default GPU to sm20
1635 void getTargetDefines(const LangOptions &Opts,
1636 MacroBuilder &Builder) const override {
1637 Builder.defineMacro("__PTX__");
1638 Builder.defineMacro("__NVPTX__");
1639 if (Opts.CUDAIsDevice) {
1640 // Set __CUDA_ARCH__ for the GPU specified.
1641 std::string CUDAArchCode;
1644 CUDAArchCode = "200";
1647 CUDAArchCode = "210";
1650 CUDAArchCode = "300";
1653 CUDAArchCode = "350";
1656 CUDAArchCode = "370";
1659 llvm_unreachable("Unhandled target CPU");
1661 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1664 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1665 return llvm::makeArrayRef(BuiltinInfo,
1666 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin);
1668 bool hasFeature(StringRef Feature) const override {
1669 return Feature == "ptx" || Feature == "nvptx";
1672 ArrayRef<const char *> getGCCRegNames() const override;
1673 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1677 bool validateAsmConstraint(const char *&Name,
1678 TargetInfo::ConstraintInfo &Info) const override {
1688 Info.setAllowsRegister();
1692 const char *getClobbers() const override {
1693 // FIXME: Is this really right?
1696 BuiltinVaListKind getBuiltinVaListKind() const override {
1698 return TargetInfo::CharPtrBuiltinVaList;
1700 bool setCPU(const std::string &Name) override {
1701 GPU = llvm::StringSwitch<GPUKind>(Name)
1702 .Case("sm_20", GK_SM20)
1703 .Case("sm_21", GK_SM21)
1704 .Case("sm_30", GK_SM30)
1705 .Case("sm_35", GK_SM35)
1706 .Case("sm_37", GK_SM37)
1709 return GPU != GK_NONE;
1713 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1714 #define BUILTIN(ID, TYPE, ATTRS) \
1715 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1716 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1717 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1718 #include "clang/Basic/BuiltinsNVPTX.def"
1721 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
1723 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
1724 return llvm::makeArrayRef(GCCRegNames);
1727 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1729 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1730 LongWidth = LongAlign = 32;
1731 PointerWidth = PointerAlign = 32;
1732 SizeType = TargetInfo::UnsignedInt;
1733 PtrDiffType = TargetInfo::SignedInt;
1734 IntPtrType = TargetInfo::SignedInt;
1735 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1739 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1741 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1742 PointerWidth = PointerAlign = 64;
1743 SizeType = TargetInfo::UnsignedLong;
1744 PtrDiffType = TargetInfo::SignedLong;
1745 IntPtrType = TargetInfo::SignedLong;
1746 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64";
1750 static const unsigned AMDGPUAddrSpaceMap[] = {
1753 2, // opencl_constant
1754 4, // opencl_generic
1760 // If you edit the description strings, make sure you update
1761 // getPointerWidthV().
1763 static const char *const DataLayoutStringR600 =
1764 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1765 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1767 static const char *const DataLayoutStringR600DoubleOps =
1768 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1769 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1771 static const char *const DataLayoutStringSI =
1772 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1773 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1774 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1776 class AMDGPUTargetInfo : public TargetInfo {
1777 static const Builtin::Info BuiltinInfo[];
1778 static const char * const GCCRegNames[];
1780 /// \brief The GPU profiles supported by the AMDGPU target.
1788 GK_EVERGREEN_DOUBLE_OPS,
1789 GK_NORTHERN_ISLANDS,
1791 GK_SOUTHERN_ISLANDS,
1801 AMDGPUTargetInfo(const llvm::Triple &Triple)
1802 : TargetInfo(Triple) {
1804 if (Triple.getArch() == llvm::Triple::amdgcn) {
1805 DataLayoutString = DataLayoutStringSI;
1806 GPU = GK_SOUTHERN_ISLANDS;
1811 DataLayoutString = DataLayoutStringR600;
1817 AddrSpaceMap = &AMDGPUAddrSpaceMap;
1818 UseAddrSpaceMapMangling = true;
1821 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1822 if (GPU <= GK_CAYMAN)
1835 const char * getClobbers() const override {
1839 ArrayRef<const char *> getGCCRegNames() const override;
1841 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1845 bool validateAsmConstraint(const char *&Name,
1846 TargetInfo::ConstraintInfo &Info) const override {
1851 Info.setAllowsRegister();
1857 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1858 return llvm::makeArrayRef(BuiltinInfo,
1859 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin);
1862 void getTargetDefines(const LangOptions &Opts,
1863 MacroBuilder &Builder) const override {
1864 Builder.defineMacro("__R600__");
1866 Builder.defineMacro("__HAS_FMAF__");
1868 Builder.defineMacro("__HAS_LDEXPF__");
1869 if (hasFP64 && Opts.OpenCL)
1870 Builder.defineMacro("cl_khr_fp64");
1872 if (GPU >= GK_NORTHERN_ISLANDS) {
1873 Builder.defineMacro("cl_khr_byte_addressable_store");
1874 Builder.defineMacro("cl_khr_global_int32_base_atomics");
1875 Builder.defineMacro("cl_khr_global_int32_extended_atomics");
1876 Builder.defineMacro("cl_khr_local_int32_base_atomics");
1877 Builder.defineMacro("cl_khr_local_int32_extended_atomics");
1882 BuiltinVaListKind getBuiltinVaListKind() const override {
1883 return TargetInfo::CharPtrBuiltinVaList;
1886 bool setCPU(const std::string &Name) override {
1887 GPU = llvm::StringSwitch<GPUKind>(Name)
1888 .Case("r600" , GK_R600)
1889 .Case("rv610", GK_R600)
1890 .Case("rv620", GK_R600)
1891 .Case("rv630", GK_R600)
1892 .Case("rv635", GK_R600)
1893 .Case("rs780", GK_R600)
1894 .Case("rs880", GK_R600)
1895 .Case("rv670", GK_R600_DOUBLE_OPS)
1896 .Case("rv710", GK_R700)
1897 .Case("rv730", GK_R700)
1898 .Case("rv740", GK_R700_DOUBLE_OPS)
1899 .Case("rv770", GK_R700_DOUBLE_OPS)
1900 .Case("palm", GK_EVERGREEN)
1901 .Case("cedar", GK_EVERGREEN)
1902 .Case("sumo", GK_EVERGREEN)
1903 .Case("sumo2", GK_EVERGREEN)
1904 .Case("redwood", GK_EVERGREEN)
1905 .Case("juniper", GK_EVERGREEN)
1906 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
1907 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
1908 .Case("barts", GK_NORTHERN_ISLANDS)
1909 .Case("turks", GK_NORTHERN_ISLANDS)
1910 .Case("caicos", GK_NORTHERN_ISLANDS)
1911 .Case("cayman", GK_CAYMAN)
1912 .Case("aruba", GK_CAYMAN)
1913 .Case("tahiti", GK_SOUTHERN_ISLANDS)
1914 .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1915 .Case("verde", GK_SOUTHERN_ISLANDS)
1916 .Case("oland", GK_SOUTHERN_ISLANDS)
1917 .Case("hainan", GK_SOUTHERN_ISLANDS)
1918 .Case("bonaire", GK_SEA_ISLANDS)
1919 .Case("kabini", GK_SEA_ISLANDS)
1920 .Case("kaveri", GK_SEA_ISLANDS)
1921 .Case("hawaii", GK_SEA_ISLANDS)
1922 .Case("mullins", GK_SEA_ISLANDS)
1923 .Case("tonga", GK_VOLCANIC_ISLANDS)
1924 .Case("iceland", GK_VOLCANIC_ISLANDS)
1925 .Case("carrizo", GK_VOLCANIC_ISLANDS)
1928 if (GPU == GK_NONE) {
1932 // Set the correct data layout
1938 case GK_NORTHERN_ISLANDS:
1939 DataLayoutString = DataLayoutStringR600;
1944 case GK_R600_DOUBLE_OPS:
1945 case GK_R700_DOUBLE_OPS:
1946 case GK_EVERGREEN_DOUBLE_OPS:
1948 DataLayoutString = DataLayoutStringR600DoubleOps;
1953 case GK_SOUTHERN_ISLANDS:
1954 case GK_SEA_ISLANDS:
1955 case GK_VOLCANIC_ISLANDS:
1956 DataLayoutString = DataLayoutStringSI;
1967 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
1968 #define BUILTIN(ID, TYPE, ATTRS) \
1969 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1970 #include "clang/Basic/BuiltinsAMDGPU.def"
1972 const char * const AMDGPUTargetInfo::GCCRegNames[] = {
1973 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1974 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1975 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1976 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1977 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
1978 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
1979 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
1980 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
1981 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
1982 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
1983 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
1984 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
1985 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
1986 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
1987 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
1988 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
1989 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
1990 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
1991 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
1992 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
1993 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
1994 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
1995 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
1996 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
1997 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
1998 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
1999 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
2000 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
2001 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
2002 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
2003 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
2004 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
2005 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2006 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
2007 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
2008 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
2009 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
2010 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
2011 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
2012 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
2013 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
2014 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
2015 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
2016 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
2017 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
2018 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
2019 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
2020 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127"
2021 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi",
2022 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi"
2025 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const {
2026 return llvm::makeArrayRef(GCCRegNames);
2029 // Namespace for x86 abstract base class
2030 const Builtin::Info BuiltinInfo[] = {
2031 #define BUILTIN(ID, TYPE, ATTRS) \
2032 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2033 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
2034 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
2035 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2036 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2037 #include "clang/Basic/BuiltinsX86.def"
2040 static const char* const GCCRegNames[] = {
2041 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
2042 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
2043 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
2044 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
2045 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
2046 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2047 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
2048 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
2049 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
2052 const TargetInfo::AddlRegName AddlRegNames[] = {
2053 { { "al", "ah", "eax", "rax" }, 0 },
2054 { { "bl", "bh", "ebx", "rbx" }, 3 },
2055 { { "cl", "ch", "ecx", "rcx" }, 2 },
2056 { { "dl", "dh", "edx", "rdx" }, 1 },
2057 { { "esi", "rsi" }, 4 },
2058 { { "edi", "rdi" }, 5 },
2059 { { "esp", "rsp" }, 7 },
2060 { { "ebp", "rbp" }, 6 },
2061 { { "r8d", "r8w", "r8b" }, 38 },
2062 { { "r9d", "r9w", "r9b" }, 39 },
2063 { { "r10d", "r10w", "r10b" }, 40 },
2064 { { "r11d", "r11w", "r11b" }, 41 },
2065 { { "r12d", "r12w", "r12b" }, 42 },
2066 { { "r13d", "r13w", "r13b" }, 43 },
2067 { { "r14d", "r14w", "r14b" }, 44 },
2068 { { "r15d", "r15w", "r15b" }, 45 },
2071 // X86 target abstract base class; x86-32 and x86-64 are very close, so
2072 // most of the implementation can be shared.
2073 class X86TargetInfo : public TargetInfo {
2075 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
2078 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
2079 } MMX3DNowLevel = NoMMX3DNow;
2087 bool HasAES = false;
2088 bool HasPCLMUL = false;
2089 bool HasLZCNT = false;
2090 bool HasRDRND = false;
2091 bool HasFSGSBASE = false;
2092 bool HasBMI = false;
2093 bool HasBMI2 = false;
2094 bool HasPOPCNT = false;
2095 bool HasRTM = false;
2096 bool HasPRFCHW = false;
2097 bool HasRDSEED = false;
2098 bool HasADX = false;
2099 bool HasTBM = false;
2100 bool HasFMA = false;
2101 bool HasF16C = false;
2102 bool HasAVX512CD = false;
2103 bool HasAVX512ER = false;
2104 bool HasAVX512PF = false;
2105 bool HasAVX512DQ = false;
2106 bool HasAVX512BW = false;
2107 bool HasAVX512VL = false;
2108 bool HasSHA = false;
2109 bool HasCX16 = false;
2110 bool HasFXSR = false;
2111 bool HasXSAVE = false;
2112 bool HasXSAVEOPT = false;
2113 bool HasXSAVEC = false;
2114 bool HasXSAVES = false;
2115 bool HasPKU = false;
2117 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2119 /// Each enumeration represents a particular CPU supported by Clang. These
2120 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2125 /// i386-generation processors.
2131 /// i486-generation processors.
2140 /// i586-generation processors, P5 microarchitecture based.
2148 /// i686-generation processors, P6 / Pentium M microarchitecture based.
2158 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2159 /// Clang however has some logic to suport this.
2160 // FIXME: Warn, deprecate, and potentially remove this.
2165 /// Netburst microarchitecture based processors.
2174 /// Core microarchitecture based processors.
2178 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2179 /// codename which GCC no longer accepts as an option to -march, but Clang
2180 /// has some logic for recognizing it.
2181 // FIXME: Warn, deprecate, and potentially remove this.
2193 /// Nehalem microarchitecture based processors.
2197 /// Westmere microarchitecture based processors.
2200 /// \name Sandy Bridge
2201 /// Sandy Bridge microarchitecture based processors.
2204 /// \name Ivy Bridge
2205 /// Ivy Bridge microarchitecture based processors.
2209 /// Haswell microarchitecture based processors.
2213 /// Broadwell microarchitecture based processors.
2217 /// Skylake microarchitecture based processors.
2220 /// \name Knights Landing
2221 /// Knights Landing processor.
2225 /// K6 architecture processors.
2233 /// K7 architecture processors.
2236 CK_AthlonThunderbird,
2243 /// K8 architecture processors.
2256 /// Bobcat architecture processors.
2263 /// Bulldozer architecture processors.
2271 /// This specification is deprecated and will be removed in the future.
2272 /// Users should prefer \see CK_K8.
2273 // FIXME: Warn on this when the CPU is set to it.
2279 /// Geode processors.
2285 CPUKind getCPUKind(StringRef CPU) const {
2286 return llvm::StringSwitch<CPUKind>(CPU)
2287 .Case("i386", CK_i386)
2288 .Case("i486", CK_i486)
2289 .Case("winchip-c6", CK_WinChipC6)
2290 .Case("winchip2", CK_WinChip2)
2292 .Case("i586", CK_i586)
2293 .Case("pentium", CK_Pentium)
2294 .Case("pentium-mmx", CK_PentiumMMX)
2295 .Case("i686", CK_i686)
2296 .Case("pentiumpro", CK_PentiumPro)
2297 .Case("pentium2", CK_Pentium2)
2298 .Case("pentium3", CK_Pentium3)
2299 .Case("pentium3m", CK_Pentium3M)
2300 .Case("pentium-m", CK_PentiumM)
2301 .Case("c3-2", CK_C3_2)
2302 .Case("yonah", CK_Yonah)
2303 .Case("pentium4", CK_Pentium4)
2304 .Case("pentium4m", CK_Pentium4M)
2305 .Case("prescott", CK_Prescott)
2306 .Case("nocona", CK_Nocona)
2307 .Case("core2", CK_Core2)
2308 .Case("penryn", CK_Penryn)
2309 .Case("bonnell", CK_Bonnell)
2310 .Case("atom", CK_Bonnell) // Legacy name.
2311 .Case("silvermont", CK_Silvermont)
2312 .Case("slm", CK_Silvermont) // Legacy name.
2313 .Case("nehalem", CK_Nehalem)
2314 .Case("corei7", CK_Nehalem) // Legacy name.
2315 .Case("westmere", CK_Westmere)
2316 .Case("sandybridge", CK_SandyBridge)
2317 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2318 .Case("ivybridge", CK_IvyBridge)
2319 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2320 .Case("haswell", CK_Haswell)
2321 .Case("core-avx2", CK_Haswell) // Legacy name.
2322 .Case("broadwell", CK_Broadwell)
2323 .Case("skylake", CK_Skylake)
2324 .Case("skx", CK_Skylake) // Legacy name.
2325 .Case("knl", CK_KNL)
2327 .Case("k6-2", CK_K6_2)
2328 .Case("k6-3", CK_K6_3)
2329 .Case("athlon", CK_Athlon)
2330 .Case("athlon-tbird", CK_AthlonThunderbird)
2331 .Case("athlon-4", CK_Athlon4)
2332 .Case("athlon-xp", CK_AthlonXP)
2333 .Case("athlon-mp", CK_AthlonMP)
2334 .Case("athlon64", CK_Athlon64)
2335 .Case("athlon64-sse3", CK_Athlon64SSE3)
2336 .Case("athlon-fx", CK_AthlonFX)
2338 .Case("k8-sse3", CK_K8SSE3)
2339 .Case("opteron", CK_Opteron)
2340 .Case("opteron-sse3", CK_OpteronSSE3)
2341 .Case("barcelona", CK_AMDFAM10)
2342 .Case("amdfam10", CK_AMDFAM10)
2343 .Case("btver1", CK_BTVER1)
2344 .Case("btver2", CK_BTVER2)
2345 .Case("bdver1", CK_BDVER1)
2346 .Case("bdver2", CK_BDVER2)
2347 .Case("bdver3", CK_BDVER3)
2348 .Case("bdver4", CK_BDVER4)
2349 .Case("x86-64", CK_x86_64)
2350 .Case("geode", CK_Geode)
2351 .Default(CK_Generic);
2358 } FPMath = FP_Default;
2361 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
2363 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
2365 unsigned getFloatEvalMethod() const override {
2366 // X87 evaluates with 80 bits "long double" precision.
2367 return SSELevel == NoSSE ? 2 : 0;
2369 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
2370 return llvm::makeArrayRef(BuiltinInfo,
2371 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin);
2373 ArrayRef<const char *> getGCCRegNames() const override {
2374 return llvm::makeArrayRef(GCCRegNames);
2376 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2379 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
2380 return llvm::makeArrayRef(AddlRegNames);
2382 bool validateCpuSupports(StringRef Name) const override;
2383 bool validateAsmConstraint(const char *&Name,
2384 TargetInfo::ConstraintInfo &info) const override;
2386 bool validateGlobalRegisterVariable(StringRef RegName,
2388 bool &HasSizeMismatch) const override {
2389 // esp and ebp are the only 32-bit registers the x86 backend can currently
2391 if (RegName.equals("esp") || RegName.equals("ebp")) {
2392 // Check that the register size is 32-bit.
2393 HasSizeMismatch = RegSize != 32;
2400 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2402 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2404 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2406 std::string convertConstraint(const char *&Constraint) const override;
2407 const char *getClobbers() const override {
2408 return "~{dirflag},~{fpsr},~{flags}";
2410 void getTargetDefines(const LangOptions &Opts,
2411 MacroBuilder &Builder) const override;
2412 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2414 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2416 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2418 void setFeatureEnabled(llvm::StringMap<bool> &Features,
2419 StringRef Name, bool Enabled) const override {
2420 setFeatureEnabledImpl(Features, Name, Enabled);
2422 // This exists purely to cut down on the number of virtual calls in
2423 // initFeatureMap which calls this repeatedly.
2424 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2425 StringRef Name, bool Enabled);
2427 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
2429 const std::vector<std::string> &FeaturesVec) const override;
2430 bool hasFeature(StringRef Feature) const override;
2431 bool handleTargetFeatures(std::vector<std::string> &Features,
2432 DiagnosticsEngine &Diags) override;
2433 StringRef getABI() const override {
2434 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
2436 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2438 if (getTriple().getArch() == llvm::Triple::x86 &&
2439 MMX3DNowLevel == NoMMX3DNow)
2443 bool setCPU(const std::string &Name) override {
2444 CPU = getCPUKind(Name);
2446 // Perform any per-CPU checks necessary to determine if this CPU is
2448 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2449 // invalid without explaining *why*.
2452 // No processor selected!
2478 case CK_AthlonThunderbird:
2483 // Only accept certain architectures when compiling in 32-bit mode.
2484 if (getTriple().getArch() != llvm::Triple::x86)
2495 case CK_SandyBridge:
2502 case CK_Athlon64SSE3:
2507 case CK_OpteronSSE3:
2518 llvm_unreachable("Unhandled CPU kind");
2521 bool setFPMath(StringRef Name) override;
2523 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2524 // We accept all non-ARM calling conventions
2525 return (CC == CC_X86ThisCall ||
2526 CC == CC_X86FastCall ||
2527 CC == CC_X86StdCall ||
2528 CC == CC_X86VectorCall ||
2530 CC == CC_X86Pascal ||
2531 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2534 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2535 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2538 bool hasSjLjLowering() const override {
2543 bool X86TargetInfo::setFPMath(StringRef Name) {
2544 if (Name == "387") {
2548 if (Name == "sse") {
2555 bool X86TargetInfo::initFeatureMap(
2556 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
2557 const std::vector<std::string> &FeaturesVec) const {
2558 // FIXME: This *really* should not be here.
2559 // X86_64 always has SSE2.
2560 if (getTriple().getArch() == llvm::Triple::x86_64)
2561 setFeatureEnabledImpl(Features, "sse2", true);
2563 switch (getCPUKind(CPU)) {
2576 setFeatureEnabledImpl(Features, "mmx", true);
2581 setFeatureEnabledImpl(Features, "sse", true);
2582 setFeatureEnabledImpl(Features, "fxsr", true);
2588 setFeatureEnabledImpl(Features, "sse2", true);
2589 setFeatureEnabledImpl(Features, "fxsr", true);
2594 setFeatureEnabledImpl(Features, "sse3", true);
2595 setFeatureEnabledImpl(Features, "fxsr", true);
2596 setFeatureEnabledImpl(Features, "cx16", true);
2600 setFeatureEnabledImpl(Features, "ssse3", true);
2601 setFeatureEnabledImpl(Features, "fxsr", true);
2602 setFeatureEnabledImpl(Features, "cx16", true);
2605 setFeatureEnabledImpl(Features, "sse4.1", true);
2606 setFeatureEnabledImpl(Features, "fxsr", true);
2607 setFeatureEnabledImpl(Features, "cx16", true);
2610 setFeatureEnabledImpl(Features, "avx512f", true);
2611 setFeatureEnabledImpl(Features, "avx512cd", true);
2612 setFeatureEnabledImpl(Features, "avx512dq", true);
2613 setFeatureEnabledImpl(Features, "avx512bw", true);
2614 setFeatureEnabledImpl(Features, "avx512vl", true);
2615 setFeatureEnabledImpl(Features, "xsavec", true);
2616 setFeatureEnabledImpl(Features, "xsaves", true);
2617 setFeatureEnabledImpl(Features, "pku", true);
2620 setFeatureEnabledImpl(Features, "rdseed", true);
2621 setFeatureEnabledImpl(Features, "adx", true);
2624 setFeatureEnabledImpl(Features, "avx2", true);
2625 setFeatureEnabledImpl(Features, "lzcnt", true);
2626 setFeatureEnabledImpl(Features, "bmi", true);
2627 setFeatureEnabledImpl(Features, "bmi2", true);
2628 setFeatureEnabledImpl(Features, "rtm", true);
2629 setFeatureEnabledImpl(Features, "fma", true);
2632 setFeatureEnabledImpl(Features, "rdrnd", true);
2633 setFeatureEnabledImpl(Features, "f16c", true);
2634 setFeatureEnabledImpl(Features, "fsgsbase", true);
2636 case CK_SandyBridge:
2637 setFeatureEnabledImpl(Features, "avx", true);
2638 setFeatureEnabledImpl(Features, "xsave", true);
2639 setFeatureEnabledImpl(Features, "xsaveopt", true);
2643 setFeatureEnabledImpl(Features, "aes", true);
2644 setFeatureEnabledImpl(Features, "pclmul", true);
2647 setFeatureEnabledImpl(Features, "sse4.2", true);
2648 setFeatureEnabledImpl(Features, "fxsr", true);
2649 setFeatureEnabledImpl(Features, "cx16", true);
2652 setFeatureEnabledImpl(Features, "avx512f", true);
2653 setFeatureEnabledImpl(Features, "avx512cd", true);
2654 setFeatureEnabledImpl(Features, "avx512er", true);
2655 setFeatureEnabledImpl(Features, "avx512pf", true);
2656 setFeatureEnabledImpl(Features, "fxsr", true);
2657 setFeatureEnabledImpl(Features, "rdseed", true);
2658 setFeatureEnabledImpl(Features, "adx", true);
2659 setFeatureEnabledImpl(Features, "lzcnt", true);
2660 setFeatureEnabledImpl(Features, "bmi", true);
2661 setFeatureEnabledImpl(Features, "bmi2", true);
2662 setFeatureEnabledImpl(Features, "rtm", true);
2663 setFeatureEnabledImpl(Features, "fma", true);
2664 setFeatureEnabledImpl(Features, "rdrnd", true);
2665 setFeatureEnabledImpl(Features, "f16c", true);
2666 setFeatureEnabledImpl(Features, "fsgsbase", true);
2667 setFeatureEnabledImpl(Features, "aes", true);
2668 setFeatureEnabledImpl(Features, "pclmul", true);
2669 setFeatureEnabledImpl(Features, "cx16", true);
2670 setFeatureEnabledImpl(Features, "xsaveopt", true);
2671 setFeatureEnabledImpl(Features, "xsave", true);
2677 setFeatureEnabledImpl(Features, "3dnow", true);
2680 case CK_AthlonThunderbird:
2682 setFeatureEnabledImpl(Features, "3dnowa", true);
2687 setFeatureEnabledImpl(Features, "sse", true);
2688 setFeatureEnabledImpl(Features, "3dnowa", true);
2689 setFeatureEnabledImpl(Features, "fxsr", true);
2695 setFeatureEnabledImpl(Features, "sse2", true);
2696 setFeatureEnabledImpl(Features, "3dnowa", true);
2697 setFeatureEnabledImpl(Features, "fxsr", true);
2700 setFeatureEnabledImpl(Features, "sse4a", true);
2701 setFeatureEnabledImpl(Features, "lzcnt", true);
2702 setFeatureEnabledImpl(Features, "popcnt", true);
2705 case CK_OpteronSSE3:
2706 case CK_Athlon64SSE3:
2707 setFeatureEnabledImpl(Features, "sse3", true);
2708 setFeatureEnabledImpl(Features, "3dnowa", true);
2709 setFeatureEnabledImpl(Features, "fxsr", true);
2712 setFeatureEnabledImpl(Features, "avx", true);
2713 setFeatureEnabledImpl(Features, "aes", true);
2714 setFeatureEnabledImpl(Features, "pclmul", true);
2715 setFeatureEnabledImpl(Features, "bmi", true);
2716 setFeatureEnabledImpl(Features, "f16c", true);
2717 setFeatureEnabledImpl(Features, "xsaveopt", true);
2720 setFeatureEnabledImpl(Features, "ssse3", true);
2721 setFeatureEnabledImpl(Features, "sse4a", true);
2722 setFeatureEnabledImpl(Features, "lzcnt", true);
2723 setFeatureEnabledImpl(Features, "popcnt", true);
2724 setFeatureEnabledImpl(Features, "prfchw", true);
2725 setFeatureEnabledImpl(Features, "cx16", true);
2726 setFeatureEnabledImpl(Features, "fxsr", true);
2727 setFeatureEnabledImpl(Features, "xsave", true);
2730 setFeatureEnabledImpl(Features, "avx2", true);
2731 setFeatureEnabledImpl(Features, "bmi2", true);
2734 setFeatureEnabledImpl(Features, "fsgsbase", true);
2735 setFeatureEnabledImpl(Features, "xsaveopt", true);
2738 setFeatureEnabledImpl(Features, "bmi", true);
2739 setFeatureEnabledImpl(Features, "fma", true);
2740 setFeatureEnabledImpl(Features, "f16c", true);
2741 setFeatureEnabledImpl(Features, "tbm", true);
2744 // xop implies avx, sse4a and fma4.
2745 setFeatureEnabledImpl(Features, "xop", true);
2746 setFeatureEnabledImpl(Features, "lzcnt", true);
2747 setFeatureEnabledImpl(Features, "aes", true);
2748 setFeatureEnabledImpl(Features, "pclmul", true);
2749 setFeatureEnabledImpl(Features, "prfchw", true);
2750 setFeatureEnabledImpl(Features, "cx16", true);
2751 setFeatureEnabledImpl(Features, "fxsr", true);
2752 setFeatureEnabledImpl(Features, "xsave", true);
2755 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
2758 // Can't do this earlier because we need to be able to explicitly enable
2759 // or disable these features and the things that they depend upon.
2761 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2762 auto I = Features.find("sse4.2");
2763 if (I != Features.end() && I->getValue() &&
2764 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
2766 Features["popcnt"] = true;
2768 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2769 I = Features.find("3dnow");
2770 if (I != Features.end() && I->getValue() &&
2771 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
2773 Features["prfchw"] = true;
2775 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2777 I = Features.find("sse");
2778 if (I != Features.end() && I->getValue() &&
2779 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
2781 Features["mmx"] = true;
2786 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2787 X86SSEEnum Level, bool Enabled) {
2791 Features["avx512f"] = true;
2793 Features["avx2"] = true;
2795 Features["avx"] = true;
2796 Features["xsave"] = true;
2798 Features["sse4.2"] = true;
2800 Features["sse4.1"] = true;
2802 Features["ssse3"] = true;
2804 Features["sse3"] = true;
2806 Features["sse2"] = true;
2808 Features["sse"] = true;
2818 Features["sse"] = false;
2820 Features["sse2"] = Features["pclmul"] = Features["aes"] =
2821 Features["sha"] = false;
2823 Features["sse3"] = false;
2824 setXOPLevel(Features, NoXOP, false);
2826 Features["ssse3"] = false;
2828 Features["sse4.1"] = false;
2830 Features["sse4.2"] = false;
2832 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
2833 Features["xsaveopt"] = false;
2834 setXOPLevel(Features, FMA4, false);
2836 Features["avx2"] = false;
2838 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2839 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2840 Features["avx512vl"] = false;
2844 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2845 MMX3DNowEnum Level, bool Enabled) {
2848 case AMD3DNowAthlon:
2849 Features["3dnowa"] = true;
2851 Features["3dnow"] = true;
2853 Features["mmx"] = true;
2863 Features["mmx"] = false;
2865 Features["3dnow"] = false;
2866 case AMD3DNowAthlon:
2867 Features["3dnowa"] = false;
2871 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2876 Features["xop"] = true;
2878 Features["fma4"] = true;
2879 setSSELevel(Features, AVX, true);
2881 Features["sse4a"] = true;
2882 setSSELevel(Features, SSE3, true);
2892 Features["sse4a"] = false;
2894 Features["fma4"] = false;
2896 Features["xop"] = false;
2900 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2901 StringRef Name, bool Enabled) {
2902 // This is a bit of a hack to deal with the sse4 target feature when used
2903 // as part of the target attribute. We handle sse4 correctly everywhere
2904 // else. See below for more information on how we handle the sse4 options.
2906 Features[Name] = Enabled;
2908 if (Name == "mmx") {
2909 setMMXLevel(Features, MMX, Enabled);
2910 } else if (Name == "sse") {
2911 setSSELevel(Features, SSE1, Enabled);
2912 } else if (Name == "sse2") {
2913 setSSELevel(Features, SSE2, Enabled);
2914 } else if (Name == "sse3") {
2915 setSSELevel(Features, SSE3, Enabled);
2916 } else if (Name == "ssse3") {
2917 setSSELevel(Features, SSSE3, Enabled);
2918 } else if (Name == "sse4.2") {
2919 setSSELevel(Features, SSE42, Enabled);
2920 } else if (Name == "sse4.1") {
2921 setSSELevel(Features, SSE41, Enabled);
2922 } else if (Name == "3dnow") {
2923 setMMXLevel(Features, AMD3DNow, Enabled);
2924 } else if (Name == "3dnowa") {
2925 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2926 } else if (Name == "aes") {
2928 setSSELevel(Features, SSE2, Enabled);
2929 } else if (Name == "pclmul") {
2931 setSSELevel(Features, SSE2, Enabled);
2932 } else if (Name == "avx") {
2933 setSSELevel(Features, AVX, Enabled);
2934 } else if (Name == "avx2") {
2935 setSSELevel(Features, AVX2, Enabled);
2936 } else if (Name == "avx512f") {
2937 setSSELevel(Features, AVX512F, Enabled);
2938 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2939 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2941 setSSELevel(Features, AVX512F, Enabled);
2942 } else if (Name == "fma") {
2944 setSSELevel(Features, AVX, Enabled);
2945 } else if (Name == "fma4") {
2946 setXOPLevel(Features, FMA4, Enabled);
2947 } else if (Name == "xop") {
2948 setXOPLevel(Features, XOP, Enabled);
2949 } else if (Name == "sse4a") {
2950 setXOPLevel(Features, SSE4A, Enabled);
2951 } else if (Name == "f16c") {
2953 setSSELevel(Features, AVX, Enabled);
2954 } else if (Name == "sha") {
2956 setSSELevel(Features, SSE2, Enabled);
2957 } else if (Name == "sse4") {
2958 // We can get here via the __target__ attribute since that's not controlled
2959 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
2960 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
2963 setSSELevel(Features, SSE42, Enabled);
2965 setSSELevel(Features, SSE41, Enabled);
2966 } else if (Name == "xsave") {
2968 setSSELevel(Features, AVX, Enabled);
2970 Features["xsaveopt"] = false;
2971 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
2973 Features["xsave"] = true;
2974 setSSELevel(Features, AVX, Enabled);
2979 /// handleTargetFeatures - Perform initialization based on the user
2980 /// configured set of features.
2981 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2982 DiagnosticsEngine &Diags) {
2983 for (const auto &Feature : Features) {
2984 if (Feature[0] != '+')
2987 if (Feature == "+aes") {
2989 } else if (Feature == "+pclmul") {
2991 } else if (Feature == "+lzcnt") {
2993 } else if (Feature == "+rdrnd") {
2995 } else if (Feature == "+fsgsbase") {
2997 } else if (Feature == "+bmi") {
2999 } else if (Feature == "+bmi2") {
3001 } else if (Feature == "+popcnt") {
3003 } else if (Feature == "+rtm") {
3005 } else if (Feature == "+prfchw") {
3007 } else if (Feature == "+rdseed") {
3009 } else if (Feature == "+adx") {
3011 } else if (Feature == "+tbm") {
3013 } else if (Feature == "+fma") {
3015 } else if (Feature == "+f16c") {
3017 } else if (Feature == "+avx512cd") {
3019 } else if (Feature == "+avx512er") {
3021 } else if (Feature == "+avx512pf") {
3023 } else if (Feature == "+avx512dq") {
3025 } else if (Feature == "+avx512bw") {
3027 } else if (Feature == "+avx512vl") {
3029 } else if (Feature == "+sha") {
3031 } else if (Feature == "+cx16") {
3033 } else if (Feature == "+fxsr") {
3035 } else if (Feature == "+xsave") {
3037 } else if (Feature == "+xsaveopt") {
3039 } else if (Feature == "+xsavec") {
3041 } else if (Feature == "+xsaves") {
3043 } else if (Feature == "+pku") {
3047 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
3048 .Case("+avx512f", AVX512F)
3049 .Case("+avx2", AVX2)
3051 .Case("+sse4.2", SSE42)
3052 .Case("+sse4.1", SSE41)
3053 .Case("+ssse3", SSSE3)
3054 .Case("+sse3", SSE3)
3055 .Case("+sse2", SSE2)
3058 SSELevel = std::max(SSELevel, Level);
3060 MMX3DNowEnum ThreeDNowLevel =
3061 llvm::StringSwitch<MMX3DNowEnum>(Feature)
3062 .Case("+3dnowa", AMD3DNowAthlon)
3063 .Case("+3dnow", AMD3DNow)
3065 .Default(NoMMX3DNow);
3066 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
3068 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
3070 .Case("+fma4", FMA4)
3071 .Case("+sse4a", SSE4A)
3073 XOPLevel = std::max(XOPLevel, XLevel);
3076 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
3077 // matches the selected sse level.
3078 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
3079 (FPMath == FP_387 && SSELevel >= SSE1)) {
3080 Diags.Report(diag::err_target_unsupported_fpmath) <<
3081 (FPMath == FP_SSE ? "sse" : "387");
3086 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3090 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
3091 /// definitions for this particular subtarget.
3092 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
3093 MacroBuilder &Builder) const {
3094 // Target identification.
3095 if (getTriple().getArch() == llvm::Triple::x86_64) {
3096 Builder.defineMacro("__amd64__");
3097 Builder.defineMacro("__amd64");
3098 Builder.defineMacro("__x86_64");
3099 Builder.defineMacro("__x86_64__");
3100 if (getTriple().getArchName() == "x86_64h") {
3101 Builder.defineMacro("__x86_64h");
3102 Builder.defineMacro("__x86_64h__");
3105 DefineStd(Builder, "i386", Opts);
3108 // Subtarget options.
3109 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
3110 // truly should be based on -mtune options.
3115 // The rest are coming from the i386 define above.
3116 Builder.defineMacro("__tune_i386__");
3122 defineCPUMacros(Builder, "i486");
3125 Builder.defineMacro("__pentium_mmx__");
3126 Builder.defineMacro("__tune_pentium_mmx__");
3130 defineCPUMacros(Builder, "i586");
3131 defineCPUMacros(Builder, "pentium");
3136 Builder.defineMacro("__tune_pentium3__");
3140 Builder.defineMacro("__tune_pentium2__");
3143 Builder.defineMacro("__tune_i686__");
3144 Builder.defineMacro("__tune_pentiumpro__");
3147 Builder.defineMacro("__i686");
3148 Builder.defineMacro("__i686__");
3149 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3150 Builder.defineMacro("__pentiumpro");
3151 Builder.defineMacro("__pentiumpro__");
3155 defineCPUMacros(Builder, "pentium4");
3160 defineCPUMacros(Builder, "nocona");
3164 defineCPUMacros(Builder, "core2");
3167 defineCPUMacros(Builder, "atom");
3170 defineCPUMacros(Builder, "slm");
3174 case CK_SandyBridge:
3178 // FIXME: Historically, we defined this legacy name, it would be nice to
3179 // remove it at some point. We've never exposed fine-grained names for
3180 // recent primary x86 CPUs, and we should keep it that way.
3181 defineCPUMacros(Builder, "corei7");
3184 // FIXME: Historically, we defined this legacy name, it would be nice to
3185 // remove it at some point. This is the only fine-grained CPU macro in the
3186 // main intel CPU line, and it would be better to not have these and force
3187 // people to use ISA macros.
3188 defineCPUMacros(Builder, "skx");
3191 defineCPUMacros(Builder, "knl");
3194 Builder.defineMacro("__k6_2__");
3195 Builder.defineMacro("__tune_k6_2__");
3198 if (CPU != CK_K6_2) { // In case of fallthrough
3199 // FIXME: GCC may be enabling these in cases where some other k6
3200 // architecture is specified but -m3dnow is explicitly provided. The
3201 // exact semantics need to be determined and emulated here.
3202 Builder.defineMacro("__k6_3__");
3203 Builder.defineMacro("__tune_k6_3__");
3207 defineCPUMacros(Builder, "k6");
3210 case CK_AthlonThunderbird:
3214 defineCPUMacros(Builder, "athlon");
3215 if (SSELevel != NoSSE) {
3216 Builder.defineMacro("__athlon_sse__");
3217 Builder.defineMacro("__tune_athlon_sse__");
3224 case CK_OpteronSSE3:
3226 case CK_Athlon64SSE3:
3228 defineCPUMacros(Builder, "k8");
3231 defineCPUMacros(Builder, "amdfam10");
3234 defineCPUMacros(Builder, "btver1");
3237 defineCPUMacros(Builder, "btver2");
3240 defineCPUMacros(Builder, "bdver1");
3243 defineCPUMacros(Builder, "bdver2");
3246 defineCPUMacros(Builder, "bdver3");
3249 defineCPUMacros(Builder, "bdver4");
3252 defineCPUMacros(Builder, "geode");
3256 // Target properties.
3257 Builder.defineMacro("__REGISTER_PREFIX__", "");
3259 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3260 // functions in glibc header files that use FP Stack inline asm which the
3261 // backend can't deal with (PR879).
3262 Builder.defineMacro("__NO_MATH_INLINES");
3265 Builder.defineMacro("__AES__");
3268 Builder.defineMacro("__PCLMUL__");
3271 Builder.defineMacro("__LZCNT__");
3274 Builder.defineMacro("__RDRND__");
3277 Builder.defineMacro("__FSGSBASE__");
3280 Builder.defineMacro("__BMI__");
3283 Builder.defineMacro("__BMI2__");
3286 Builder.defineMacro("__POPCNT__");
3289 Builder.defineMacro("__RTM__");
3292 Builder.defineMacro("__PRFCHW__");
3295 Builder.defineMacro("__RDSEED__");
3298 Builder.defineMacro("__ADX__");
3301 Builder.defineMacro("__TBM__");
3305 Builder.defineMacro("__XOP__");
3307 Builder.defineMacro("__FMA4__");
3309 Builder.defineMacro("__SSE4A__");
3315 Builder.defineMacro("__FMA__");
3318 Builder.defineMacro("__F16C__");
3321 Builder.defineMacro("__AVX512CD__");
3323 Builder.defineMacro("__AVX512ER__");
3325 Builder.defineMacro("__AVX512PF__");
3327 Builder.defineMacro("__AVX512DQ__");
3329 Builder.defineMacro("__AVX512BW__");
3331 Builder.defineMacro("__AVX512VL__");
3334 Builder.defineMacro("__SHA__");
3337 Builder.defineMacro("__FXSR__");
3339 Builder.defineMacro("__XSAVE__");
3341 Builder.defineMacro("__XSAVEOPT__");
3343 Builder.defineMacro("__XSAVEC__");
3345 Builder.defineMacro("__XSAVES__");
3347 Builder.defineMacro("__PKU__");
3349 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3351 // Each case falls through to the previous one here.
3354 Builder.defineMacro("__AVX512F__");
3356 Builder.defineMacro("__AVX2__");
3358 Builder.defineMacro("__AVX__");
3360 Builder.defineMacro("__SSE4_2__");
3362 Builder.defineMacro("__SSE4_1__");
3364 Builder.defineMacro("__SSSE3__");
3366 Builder.defineMacro("__SSE3__");
3368 Builder.defineMacro("__SSE2__");
3369 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
3371 Builder.defineMacro("__SSE__");
3372 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
3377 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3387 Builder.defineMacro("_M_IX86_FP", Twine(2));
3390 Builder.defineMacro("_M_IX86_FP", Twine(1));
3393 Builder.defineMacro("_M_IX86_FP", Twine(0));
3397 // Each case falls through to the previous one here.
3398 switch (MMX3DNowLevel) {
3399 case AMD3DNowAthlon:
3400 Builder.defineMacro("__3dNOW_A__");
3402 Builder.defineMacro("__3dNOW__");
3404 Builder.defineMacro("__MMX__");
3409 if (CPU >= CK_i486) {
3410 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3411 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3412 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3415 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3418 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3419 return llvm::StringSwitch<bool>(Feature)
3420 .Case("aes", HasAES)
3421 .Case("avx", SSELevel >= AVX)
3422 .Case("avx2", SSELevel >= AVX2)
3423 .Case("avx512f", SSELevel >= AVX512F)
3424 .Case("avx512cd", HasAVX512CD)
3425 .Case("avx512er", HasAVX512ER)
3426 .Case("avx512pf", HasAVX512PF)
3427 .Case("avx512dq", HasAVX512DQ)
3428 .Case("avx512bw", HasAVX512BW)
3429 .Case("avx512vl", HasAVX512VL)
3430 .Case("bmi", HasBMI)
3431 .Case("bmi2", HasBMI2)
3432 .Case("cx16", HasCX16)
3433 .Case("f16c", HasF16C)
3434 .Case("fma", HasFMA)
3435 .Case("fma4", XOPLevel >= FMA4)
3436 .Case("fsgsbase", HasFSGSBASE)
3437 .Case("fxsr", HasFXSR)
3438 .Case("lzcnt", HasLZCNT)
3439 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3440 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3441 .Case("mmx", MMX3DNowLevel >= MMX)
3442 .Case("pclmul", HasPCLMUL)
3443 .Case("popcnt", HasPOPCNT)
3444 .Case("prfchw", HasPRFCHW)
3445 .Case("rdrnd", HasRDRND)
3446 .Case("rdseed", HasRDSEED)
3447 .Case("rtm", HasRTM)
3448 .Case("sha", HasSHA)
3449 .Case("sse", SSELevel >= SSE1)
3450 .Case("sse2", SSELevel >= SSE2)
3451 .Case("sse3", SSELevel >= SSE3)
3452 .Case("ssse3", SSELevel >= SSSE3)
3453 .Case("sse4.1", SSELevel >= SSE41)
3454 .Case("sse4.2", SSELevel >= SSE42)
3455 .Case("sse4a", XOPLevel >= SSE4A)
3456 .Case("tbm", HasTBM)
3458 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3459 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3460 .Case("xop", XOPLevel >= XOP)
3461 .Case("xsave", HasXSAVE)
3462 .Case("xsavec", HasXSAVEC)
3463 .Case("xsaves", HasXSAVES)
3464 .Case("xsaveopt", HasXSAVEOPT)
3465 .Case("pku", HasPKU)
3469 // We can't use a generic validation scheme for the features accepted here
3470 // versus subtarget features accepted in the target attribute because the
3471 // bitfield structure that's initialized in the runtime only supports the
3472 // below currently rather than the full range of subtarget features. (See
3473 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
3474 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
3475 return llvm::StringSwitch<bool>(FeatureStr)
3478 .Case("popcnt", true)
3482 .Case("sse4.1", true)
3483 .Case("sse4.2", true)
3486 .Case("sse4a", true)
3490 .Case("avx512f", true)
3497 X86TargetInfo::validateAsmConstraint(const char *&Name,
3498 TargetInfo::ConstraintInfo &Info) const {
3500 default: return false;
3501 // Constant constraints.
3502 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
3504 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3505 // x86_64 instructions.
3507 Info.setRequiresImmediate();
3510 Info.setRequiresImmediate(0, 31);
3513 Info.setRequiresImmediate(0, 63);
3516 Info.setRequiresImmediate(-128, 127);
3519 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) });
3522 Info.setRequiresImmediate(0, 3);
3525 Info.setRequiresImmediate(0, 255);
3528 Info.setRequiresImmediate(0, 127);
3530 // Register constraints.
3531 case 'Y': // 'Y' is the first character for several 2-character constraints.
3532 // Shift the pointer to the second character of the constraint.
3537 case '0': // First SSE register.
3538 case 't': // Any SSE register, when SSE2 is enabled.
3539 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
3540 case 'm': // Any MMX register, when inter-unit moves enabled.
3541 Info.setAllowsRegister();
3544 case 'f': // Any x87 floating point stack register.
3545 // Constraint 'f' cannot be used for output operands.
3546 if (Info.ConstraintStr[0] == '=')
3548 Info.setAllowsRegister();
3556 case 'A': // edx:eax.
3557 case 't': // Top of floating point stack.
3558 case 'u': // Second from top of floating point stack.
3559 case 'q': // Any register accessible as [r]l: a, b, c, and d.
3560 case 'y': // Any MMX register.
3561 case 'x': // Any SSE register.
3562 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3563 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3564 case 'l': // "Index" registers: any general register that can be used as an
3565 // index in a base+index memory access.
3566 Info.setAllowsRegister();
3568 // Floating point constant constraints.
3569 case 'C': // SSE floating point constant.
3570 case 'G': // x87 floating point constant.
3575 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3576 unsigned Size) const {
3577 // Strip off constraint modifiers.
3578 while (Constraint[0] == '=' ||
3579 Constraint[0] == '+' ||
3580 Constraint[0] == '&')
3581 Constraint = Constraint.substr(1);
3583 return validateOperandSize(Constraint, Size);
3586 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3587 unsigned Size) const {
3588 return validateOperandSize(Constraint, Size);
3591 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3592 unsigned Size) const {
3593 switch (Constraint[0]) {
3602 if (SSELevel >= AVX512F)
3603 // 512-bit zmm registers can be used if target supports AVX512F.
3604 return Size <= 512U;
3605 else if (SSELevel >= AVX)
3606 // 256-bit ymm registers can be used if target supports AVX.
3607 return Size <= 256U;
3608 return Size <= 128U;
3610 // 'Y' is the first character for several 2-character constraints.
3611 switch (Constraint[1]) {
3614 // 'Ym' is synonymous with 'y'.
3618 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
3619 if (SSELevel >= AVX512F)
3620 return Size <= 512U;
3621 else if (SSELevel >= AVX)
3622 return Size <= 256U;
3623 return SSELevel >= SSE2 && Size <= 128U;
3632 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3633 switch (*Constraint) {
3634 case 'a': return std::string("{ax}");
3635 case 'b': return std::string("{bx}");
3636 case 'c': return std::string("{cx}");
3637 case 'd': return std::string("{dx}");
3638 case 'S': return std::string("{si}");
3639 case 'D': return std::string("{di}");
3640 case 'p': // address
3641 return std::string("im");
3642 case 't': // top of floating point stack.
3643 return std::string("{st}");
3644 case 'u': // second from top of floating point stack.
3645 return std::string("{st(1)}"); // second from top of floating point stack.
3647 return std::string(1, *Constraint);
3651 // X86-32 generic target
3652 class X86_32TargetInfo : public X86TargetInfo {
3654 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3655 DoubleAlign = LongLongAlign = 32;
3656 LongDoubleWidth = 96;
3657 LongDoubleAlign = 32;
3658 SuitableAlign = 128;
3659 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3660 SizeType = UnsignedInt;
3661 PtrDiffType = SignedInt;
3662 IntPtrType = SignedInt;
3665 // Use fpret for all types.
3666 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3667 (1 << TargetInfo::Double) |
3668 (1 << TargetInfo::LongDouble));
3670 // x86-32 has atomics up to 8 bytes
3671 // FIXME: Check that we actually have cmpxchg8b before setting
3672 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3673 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3675 BuiltinVaListKind getBuiltinVaListKind() const override {
3676 return TargetInfo::CharPtrBuiltinVaList;
3679 int getEHDataRegisterNumber(unsigned RegNo) const override {
3680 if (RegNo == 0) return 0;
3681 if (RegNo == 1) return 2;
3684 bool validateOperandSize(StringRef Constraint,
3685 unsigned Size) const override {
3686 switch (Constraint[0]) {
3702 return X86TargetInfo::validateOperandSize(Constraint, Size);
3706 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3708 NetBSDI386TargetInfo(const llvm::Triple &Triple)
3709 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3711 unsigned getFloatEvalMethod() const override {
3712 unsigned Major, Minor, Micro;
3713 getTriple().getOSVersion(Major, Minor, Micro);
3714 // New NetBSD uses the default rounding mode.
3715 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3716 return X86_32TargetInfo::getFloatEvalMethod();
3717 // NetBSD before 6.99.26 defaults to "double" rounding.
3722 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3724 OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3725 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3726 SizeType = UnsignedLong;
3727 IntPtrType = SignedLong;
3728 PtrDiffType = SignedLong;
3732 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3734 BitrigI386TargetInfo(const llvm::Triple &Triple)
3735 : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3736 SizeType = UnsignedLong;
3737 IntPtrType = SignedLong;
3738 PtrDiffType = SignedLong;
3742 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3744 DarwinI386TargetInfo(const llvm::Triple &Triple)
3745 : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3746 LongDoubleWidth = 128;
3747 LongDoubleAlign = 128;
3748 SuitableAlign = 128;
3749 MaxVectorAlign = 256;
3750 // The watchOS simulator uses the builtin bool type for Objective-C.
3751 llvm::Triple T = llvm::Triple(Triple);
3753 UseSignedCharForObjCBool = false;
3754 SizeType = UnsignedLong;
3755 IntPtrType = SignedLong;
3756 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3757 HasAlignMac68kSupport = true;
3760 bool handleTargetFeatures(std::vector<std::string> &Features,
3761 DiagnosticsEngine &Diags) override {
3762 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features,
3765 // We now know the features we have: we can decide how to align vectors.
3767 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3772 // x86-32 Windows target
3773 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3775 WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3776 : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3777 WCharType = UnsignedShort;
3778 DoubleAlign = LongLongAlign = 64;
3780 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3781 DataLayoutString = IsWinCOFF
3782 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
3783 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3785 void getTargetDefines(const LangOptions &Opts,
3786 MacroBuilder &Builder) const override {
3787 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3791 // x86-32 Windows Visual Studio target
3792 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3794 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3795 : WindowsX86_32TargetInfo(Triple) {
3796 LongDoubleWidth = LongDoubleAlign = 64;
3797 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3799 void getTargetDefines(const LangOptions &Opts,
3800 MacroBuilder &Builder) const override {
3801 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3802 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3803 // The value of the following reflects processor type.
3804 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3805 // We lost the original triple, so we use the default.
3806 Builder.defineMacro("_M_IX86", "600");
3810 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3811 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang
3812 // supports __declspec natively under -fms-extensions, but we define a no-op
3813 // __declspec macro anyway for pre-processor compatibility.
3814 if (Opts.MicrosoftExt)
3815 Builder.defineMacro("__declspec", "__declspec");
3817 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3819 if (!Opts.MicrosoftExt) {
3820 // Provide macros for all the calling convention keywords. Provide both
3821 // single and double underscore prefixed variants. These are available on
3822 // x64 as well as x86, even though they have no effect.
3823 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3824 for (const char *CC : CCs) {
3825 std::string GCCSpelling = "__attribute__((__";
3827 GCCSpelling += "__))";
3828 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3829 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3834 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3835 Builder.defineMacro("__MSVCRT__");
3836 Builder.defineMacro("__MINGW32__");
3837 addCygMingDefines(Opts, Builder);
3840 // x86-32 MinGW target
3841 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3843 MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3844 : WindowsX86_32TargetInfo(Triple) {}
3845 void getTargetDefines(const LangOptions &Opts,
3846 MacroBuilder &Builder) const override {
3847 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3848 DefineStd(Builder, "WIN32", Opts);
3849 DefineStd(Builder, "WINNT", Opts);
3850 Builder.defineMacro("_X86_");
3851 addMinGWDefines(Opts, Builder);
3855 // x86-32 Cygwin target
3856 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3858 CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3859 : X86_32TargetInfo(Triple) {
3860 WCharType = UnsignedShort;
3861 DoubleAlign = LongLongAlign = 64;
3862 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3864 void getTargetDefines(const LangOptions &Opts,
3865 MacroBuilder &Builder) const override {
3866 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3867 Builder.defineMacro("_X86_");
3868 Builder.defineMacro("__CYGWIN__");
3869 Builder.defineMacro("__CYGWIN32__");
3870 addCygMingDefines(Opts, Builder);
3871 DefineStd(Builder, "unix", Opts);
3873 Builder.defineMacro("_GNU_SOURCE");
3877 // x86-32 Haiku target
3878 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3880 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3881 SizeType = UnsignedLong;
3882 IntPtrType = SignedLong;
3883 PtrDiffType = SignedLong;
3884 ProcessIDType = SignedLong;
3885 this->UserLabelPrefix = "";
3886 this->TLSSupported = false;
3888 void getTargetDefines(const LangOptions &Opts,
3889 MacroBuilder &Builder) const override {
3890 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3891 Builder.defineMacro("__INTEL__");
3892 Builder.defineMacro("__HAIKU__");
3896 // X86-32 MCU target
3897 class MCUX86_32TargetInfo : public X86_32TargetInfo {
3899 MCUX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3900 LongDoubleWidth = 64;
3901 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3904 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3905 // On MCU we support only C calling convention.
3906 return CC == CC_C ? CCCR_OK : CCCR_Warning;
3909 void getTargetDefines(const LangOptions &Opts,
3910 MacroBuilder &Builder) const override {
3911 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3912 Builder.defineMacro("__iamcu");
3913 Builder.defineMacro("__iamcu__");
3918 template<typename Target>
3919 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3921 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3922 MacroBuilder &Builder) const override {
3923 // RTEMS defines; list based off of gcc output
3925 Builder.defineMacro("__rtems__");
3926 Builder.defineMacro("__ELF__");
3930 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3931 this->UserLabelPrefix = "";
3933 switch (Triple.getArch()) {
3935 case llvm::Triple::x86:
3936 // this->MCountName = ".mcount";
3938 case llvm::Triple::mips:
3939 case llvm::Triple::mipsel:
3940 case llvm::Triple::ppc:
3941 case llvm::Triple::ppc64:
3942 case llvm::Triple::ppc64le:
3943 // this->MCountName = "_mcount";
3945 case llvm::Triple::arm:
3946 // this->MCountName = "__mcount";
3952 // x86-32 RTEMS target
3953 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3955 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3956 SizeType = UnsignedLong;
3957 IntPtrType = SignedLong;
3958 PtrDiffType = SignedLong;
3959 this->UserLabelPrefix = "";
3961 void getTargetDefines(const LangOptions &Opts,
3962 MacroBuilder &Builder) const override {
3963 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3964 Builder.defineMacro("__INTEL__");
3965 Builder.defineMacro("__rtems__");
3969 // x86-64 generic target
3970 class X86_64TargetInfo : public X86TargetInfo {
3972 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3973 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3975 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3976 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3977 LongDoubleWidth = 128;
3978 LongDoubleAlign = 128;
3979 LargeArrayMinWidth = 128;
3980 LargeArrayAlign = 128;
3981 SuitableAlign = 128;
3982 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
3983 PtrDiffType = IsX32 ? SignedInt : SignedLong;
3984 IntPtrType = IsX32 ? SignedInt : SignedLong;
3985 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
3986 Int64Type = IsX32 ? SignedLongLong : SignedLong;
3989 // Pointers are 32-bit in x32.
3990 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3992 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
3993 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3995 // Use fpret only for long double.
3996 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3998 // Use fp2ret for _Complex long double.
3999 ComplexLongDoubleUsesFP2Ret = true;
4001 // Make __builtin_ms_va_list available.
4002 HasBuiltinMSVaList = true;
4004 // x86-64 has atomics up to 16 bytes.
4005 MaxAtomicPromoteWidth = 128;
4006 MaxAtomicInlineWidth = 128;
4008 BuiltinVaListKind getBuiltinVaListKind() const override {
4009 return TargetInfo::X86_64ABIBuiltinVaList;
4012 int getEHDataRegisterNumber(unsigned RegNo) const override {
4013 if (RegNo == 0) return 0;
4014 if (RegNo == 1) return 1;
4018 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4019 return (CC == CC_C ||
4020 CC == CC_X86VectorCall ||
4021 CC == CC_IntelOclBicc ||
4022 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
4025 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
4029 // for x32 we need it here explicitly
4030 bool hasInt128Type() const override { return true; }
4032 bool validateGlobalRegisterVariable(StringRef RegName,
4034 bool &HasSizeMismatch) const override {
4035 // rsp and rbp are the only 64-bit registers the x86 backend can currently
4037 if (RegName.equals("rsp") || RegName.equals("rbp")) {
4038 // Check that the register size is 64-bit.
4039 HasSizeMismatch = RegSize != 64;
4043 // Check if the register is a 32-bit register the backend can handle.
4044 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize,
4049 // x86-64 Windows target
4050 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
4052 WindowsX86_64TargetInfo(const llvm::Triple &Triple)
4053 : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
4054 WCharType = UnsignedShort;
4055 LongWidth = LongAlign = 32;
4056 DoubleAlign = LongLongAlign = 64;
4057 IntMaxType = SignedLongLong;
4058 Int64Type = SignedLongLong;
4059 SizeType = UnsignedLongLong;
4060 PtrDiffType = SignedLongLong;
4061 IntPtrType = SignedLongLong;
4062 this->UserLabelPrefix = "";
4065 void getTargetDefines(const LangOptions &Opts,
4066 MacroBuilder &Builder) const override {
4067 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
4068 Builder.defineMacro("_WIN64");
4071 BuiltinVaListKind getBuiltinVaListKind() const override {
4072 return TargetInfo::CharPtrBuiltinVaList;
4075 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4078 case CC_X86ThisCall:
4079 case CC_X86FastCall:
4082 case CC_X86VectorCall:
4083 case CC_IntelOclBicc:
4087 return CCCR_Warning;
4092 // x86-64 Windows Visual Studio target
4093 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
4095 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
4096 : WindowsX86_64TargetInfo(Triple) {
4097 LongDoubleWidth = LongDoubleAlign = 64;
4098 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4100 void getTargetDefines(const LangOptions &Opts,
4101 MacroBuilder &Builder) const override {
4102 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4103 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
4104 Builder.defineMacro("_M_X64", "100");
4105 Builder.defineMacro("_M_AMD64", "100");
4109 // x86-64 MinGW target
4110 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
4112 MinGWX86_64TargetInfo(const llvm::Triple &Triple)
4113 : WindowsX86_64TargetInfo(Triple) {
4114 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
4115 // with x86 FP ops. Weird.
4116 LongDoubleWidth = LongDoubleAlign = 128;
4117 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
4120 void getTargetDefines(const LangOptions &Opts,
4121 MacroBuilder &Builder) const override {
4122 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4123 DefineStd(Builder, "WIN64", Opts);
4124 Builder.defineMacro("__MINGW64__");
4125 addMinGWDefines(Opts, Builder);
4127 // GCC defines this macro when it is using __gxx_personality_seh0.
4128 if (!Opts.SjLjExceptions)
4129 Builder.defineMacro("__SEH__");
4133 // x86-64 Cygwin target
4134 class CygwinX86_64TargetInfo : public X86_64TargetInfo {
4136 CygwinX86_64TargetInfo(const llvm::Triple &Triple)
4137 : X86_64TargetInfo(Triple) {
4138 TLSSupported = false;
4139 WCharType = UnsignedShort;
4141 void getTargetDefines(const LangOptions &Opts,
4142 MacroBuilder &Builder) const override {
4143 X86_64TargetInfo::getTargetDefines(Opts, Builder);
4144 Builder.defineMacro("__x86_64__");
4145 Builder.defineMacro("__CYGWIN__");
4146 Builder.defineMacro("__CYGWIN64__");
4147 addCygMingDefines(Opts, Builder);
4148 DefineStd(Builder, "unix", Opts);
4150 Builder.defineMacro("_GNU_SOURCE");
4152 // GCC defines this macro when it is using __gxx_personality_seh0.
4153 if (!Opts.SjLjExceptions)
4154 Builder.defineMacro("__SEH__");
4158 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
4160 DarwinX86_64TargetInfo(const llvm::Triple &Triple)
4161 : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
4162 Int64Type = SignedLongLong;
4163 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
4164 llvm::Triple T = llvm::Triple(Triple);
4166 UseSignedCharForObjCBool = false;
4167 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
4170 bool handleTargetFeatures(std::vector<std::string> &Features,
4171 DiagnosticsEngine &Diags) override {
4172 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features,
4175 // We now know the features we have: we can decide how to align vectors.
4177 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4182 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
4184 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
4185 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
4186 IntMaxType = SignedLongLong;
4187 Int64Type = SignedLongLong;
4191 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
4193 BitrigX86_64TargetInfo(const llvm::Triple &Triple)
4194 : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
4195 IntMaxType = SignedLongLong;
4196 Int64Type = SignedLongLong;
4200 class ARMTargetInfo : public TargetInfo {
4201 // Possible FPU choices.
4210 // Possible HWDiv features.
4212 HWDivThumb = (1 << 0),
4216 static bool FPUModeIsVFP(FPUMode Mode) {
4217 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
4220 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4221 static const char * const GCCRegNames[];
4223 std::string ABI, CPU;
4225 StringRef CPUProfile;
4235 unsigned ArchKind = llvm::ARM::AK_ARMV4T;
4236 unsigned ArchProfile;
4237 unsigned ArchVersion;
4241 unsigned IsAAPCS : 1;
4244 // Initialized via features.
4245 unsigned SoftFloat : 1;
4246 unsigned SoftFloatABI : 1;
4249 unsigned Crypto : 1;
4251 unsigned Unaligned : 1;
4254 LDREX_B = (1 << 0), /// byte (8-bit)
4255 LDREX_H = (1 << 1), /// half (16-bit)
4256 LDREX_W = (1 << 2), /// word (32-bit)
4257 LDREX_D = (1 << 3), /// double (64-bit)
4262 // ACLE 6.5.1 Hardware floating point
4264 HW_FP_HP = (1 << 1), /// half (16-bit)
4265 HW_FP_SP = (1 << 2), /// single (32-bit)
4266 HW_FP_DP = (1 << 3), /// double (64-bit)
4270 static const Builtin::Info BuiltinInfo[];
4272 void setABIAAPCS() {
4275 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4276 const llvm::Triple &T = getTriple();
4278 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig.
4279 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
4280 T.getOS() == llvm::Triple::Bitrig)
4281 SizeType = UnsignedLong;
4283 SizeType = UnsignedInt;
4285 switch (T.getOS()) {
4286 case llvm::Triple::NetBSD:
4287 WCharType = SignedInt;
4289 case llvm::Triple::Win32:
4290 WCharType = UnsignedShort;
4292 case llvm::Triple::Linux:
4294 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
4295 WCharType = UnsignedInt;
4299 UseBitFieldTypeAlignment = true;
4301 ZeroLengthBitfieldBoundary = 0;
4303 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
4304 // so set preferred for small types to 32.
4305 if (T.isOSBinFormatMachO()) {
4307 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4308 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4309 } else if (T.isOSWindows()) {
4310 assert(!BigEndian && "Windows on ARM does not support big endian");
4311 DataLayoutString = "e"
4319 } else if (T.isOSNaCl()) {
4320 assert(!BigEndian && "NaCl on ARM does not support big endian");
4321 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
4324 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4325 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4328 // FIXME: Enumerated types are variable width in straight AAPCS.
4331 void setABIAPCS(bool IsAAPCS16) {
4332 const llvm::Triple &T = getTriple();
4337 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4339 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
4341 // size_t is unsigned int on FreeBSD.
4342 if (T.getOS() == llvm::Triple::FreeBSD)
4343 SizeType = UnsignedInt;
4345 SizeType = UnsignedLong;
4347 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
4348 WCharType = SignedInt;
4350 // Do not respect the alignment of bit-field types when laying out
4351 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
4352 UseBitFieldTypeAlignment = false;
4354 /// gcc forces the alignment to 4 bytes, regardless of the type of the
4355 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
4357 ZeroLengthBitfieldBoundary = 32;
4359 if (T.isOSBinFormatMachO() && IsAAPCS16) {
4360 assert(!BigEndian && "AAPCS16 does not support big-endian");
4361 DataLayoutString = "e-m:o-p:32:32-i64:64-a:0:32-n32-S128";
4362 } else if (T.isOSBinFormatMachO())
4365 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4366 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4370 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4371 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4373 // FIXME: Override "preferred align" for double and long long.
4376 void setArchInfo() {
4377 StringRef ArchName = getTriple().getArchName();
4379 ArchISA = llvm::ARM::parseArchISA(ArchName);
4380 CPU = llvm::ARM::getDefaultCPU(ArchName);
4381 unsigned AK = llvm::ARM::parseArch(ArchName);
4382 if (AK != llvm::ARM::AK_INVALID)
4384 setArchInfo(ArchKind);
4387 void setArchInfo(unsigned Kind) {
4390 // cache TargetParser info
4392 SubArch = llvm::ARM::getSubArch(ArchKind);
4393 ArchProfile = llvm::ARM::parseArchProfile(SubArch);
4394 ArchVersion = llvm::ARM::parseArchVersion(SubArch);
4396 // cache CPU related strings
4397 CPUAttr = getCPUAttr();
4398 CPUProfile = getCPUProfile();
4402 // when triple does not specify a sub arch,
4403 // then we are not using inline atomics
4404 bool ShouldUseInlineAtomic =
4405 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) ||
4406 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
4407 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4408 if (ArchProfile == llvm::ARM::PK_M) {
4409 MaxAtomicPromoteWidth = 32;
4410 if (ShouldUseInlineAtomic)
4411 MaxAtomicInlineWidth = 32;
4414 MaxAtomicPromoteWidth = 64;
4415 if (ShouldUseInlineAtomic)
4416 MaxAtomicInlineWidth = 64;
4420 bool isThumb() const {
4421 return (ArchISA == llvm::ARM::IK_THUMB);
4424 bool supportsThumb() const {
4425 return CPUAttr.count('T') || ArchVersion >= 6;
4428 bool supportsThumb2() const {
4429 return CPUAttr.equals("6T2") || ArchVersion >= 7;
4432 StringRef getCPUAttr() const {
4433 // For most sub-arches, the build attribute CPU name is enough.
4434 // For Cortex variants, it's slightly different.
4437 return llvm::ARM::getCPUAttr(ArchKind);
4438 case llvm::ARM::AK_ARMV6M:
4440 case llvm::ARM::AK_ARMV7S:
4442 case llvm::ARM::AK_ARMV7A:
4444 case llvm::ARM::AK_ARMV7R:
4446 case llvm::ARM::AK_ARMV7M:
4448 case llvm::ARM::AK_ARMV7EM:
4450 case llvm::ARM::AK_ARMV8A:
4452 case llvm::ARM::AK_ARMV8_1A:
4457 StringRef getCPUProfile() const {
4458 switch(ArchProfile) {
4459 case llvm::ARM::PK_A:
4461 case llvm::ARM::PK_R:
4463 case llvm::ARM::PK_M:
4471 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
4472 : TargetInfo(Triple), FPMath(FP_Default),
4473 IsAAPCS(true), LDREX(0), HW_FP(0) {
4474 BigEndian = IsBigEndian;
4476 switch (getTriple().getOS()) {
4477 case llvm::Triple::NetBSD:
4478 PtrDiffType = SignedLong;
4481 PtrDiffType = SignedInt;
4485 // Cache arch related info.
4488 // {} in inline assembly are neon specifiers, not assembly variant
4490 NoAsmVariants = true;
4492 // FIXME: This duplicates code from the driver that sets the -target-abi
4493 // option - this code is used if -target-abi isn't passed and should
4494 // be unified in some way.
4495 if (Triple.isOSBinFormatMachO()) {
4496 // The backend is hardwired to assume AAPCS for M-class processors, ensure
4497 // the frontend matches that.
4498 if (Triple.getEnvironment() == llvm::Triple::EABI ||
4499 Triple.getOS() == llvm::Triple::UnknownOS ||
4500 StringRef(CPU).startswith("cortex-m")) {
4502 } else if (Triple.isWatchOS()) {
4507 } else if (Triple.isOSWindows()) {
4508 // FIXME: this is invalid for WindowsCE
4511 // Select the default based on the platform.
4512 switch (Triple.getEnvironment()) {
4513 case llvm::Triple::Android:
4514 case llvm::Triple::GNUEABI:
4515 case llvm::Triple::GNUEABIHF:
4516 setABI("aapcs-linux");
4518 case llvm::Triple::EABIHF:
4519 case llvm::Triple::EABI:
4522 case llvm::Triple::GNU:
4526 if (Triple.getOS() == llvm::Triple::NetBSD)
4534 // ARM targets default to using the ARM C++ ABI.
4535 TheCXXABI.set(TargetCXXABI::GenericARM);
4537 // ARM has atomics up to 8 bytes
4540 // Do force alignment of members that follow zero length bitfields. If
4541 // the alignment of the zero-length bitfield is greater than the member
4542 // that follows it, `bar', `bar' will be aligned as the type of the
4543 // zero length bitfield.
4544 UseZeroLengthBitfieldAlignment = true;
4547 StringRef getABI() const override { return ABI; }
4549 bool setABI(const std::string &Name) override {
4552 // The defaults (above) are for AAPCS, check if we need to change them.
4554 // FIXME: We need support for -meabi... we could just mangle it into the
4556 if (Name == "apcs-gnu" || Name == "aapcs16") {
4557 setABIAPCS(Name == "aapcs16");
4560 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
4567 // FIXME: This should be based on Arch attributes, not CPU names.
4569 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
4571 const std::vector<std::string> &FeaturesVec) const override {
4573 std::vector<const char*> TargetFeatures;
4574 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName());
4576 // get default FPU features
4577 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
4578 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
4580 // get default Extension features
4581 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
4582 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
4584 for (const char *Feature : TargetFeatures)
4585 if (Feature[0] == '+')
4586 Features[Feature+1] = true;
4588 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
4591 bool handleTargetFeatures(std::vector<std::string> &Features,
4592 DiagnosticsEngine &Diags) override {
4598 SoftFloat = SoftFloatABI = false;
4601 // This does not diagnose illegal cases like having both
4602 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
4603 uint32_t HW_FP_remove = 0;
4604 for (const auto &Feature : Features) {
4605 if (Feature == "+soft-float") {
4607 } else if (Feature == "+soft-float-abi") {
4608 SoftFloatABI = true;
4609 } else if (Feature == "+vfp2") {
4611 HW_FP |= HW_FP_SP | HW_FP_DP;
4612 } else if (Feature == "+vfp3") {
4614 HW_FP |= HW_FP_SP | HW_FP_DP;
4615 } else if (Feature == "+vfp4") {
4617 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
4618 } else if (Feature == "+fp-armv8") {
4620 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
4621 } else if (Feature == "+neon") {
4623 HW_FP |= HW_FP_SP | HW_FP_DP;
4624 } else if (Feature == "+hwdiv") {
4625 HWDiv |= HWDivThumb;
4626 } else if (Feature == "+hwdiv-arm") {
4628 } else if (Feature == "+crc") {
4630 } else if (Feature == "+crypto") {
4632 } else if (Feature == "+dsp") {
4634 } else if (Feature == "+fp-only-sp") {
4635 HW_FP_remove |= HW_FP_DP;
4636 } else if (Feature == "+strict-align") {
4638 } else if (Feature == "+fp16") {
4642 HW_FP &= ~HW_FP_remove;
4644 switch (ArchVersion) {
4646 if (ArchProfile == llvm::ARM::PK_M)
4648 else if (ArchKind == llvm::ARM::AK_ARMV6K)
4649 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
4654 if (ArchProfile == llvm::ARM::PK_M)
4655 LDREX = LDREX_W | LDREX_H | LDREX_B ;
4657 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
4660 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
4663 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4664 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4668 if (FPMath == FP_Neon)
4669 Features.push_back("+neonfp");
4670 else if (FPMath == FP_VFP)
4671 Features.push_back("-neonfp");
4673 // Remove front-end specific options which the backend handles differently.
4675 std::find(Features.begin(), Features.end(), "+soft-float-abi");
4676 if (Feature != Features.end())
4677 Features.erase(Feature);
4682 bool hasFeature(StringRef Feature) const override {
4683 return llvm::StringSwitch<bool>(Feature)
4685 .Case("aarch32", true)
4686 .Case("softfloat", SoftFloat)
4687 .Case("thumb", isThumb())
4688 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4689 .Case("hwdiv", HWDiv & HWDivThumb)
4690 .Case("hwdiv-arm", HWDiv & HWDivARM)
4694 bool setCPU(const std::string &Name) override {
4695 if (Name != "generic")
4696 setArchInfo(llvm::ARM::parseCPUArch(Name));
4698 if (ArchKind == llvm::ARM::AK_INVALID)
4705 bool setFPMath(StringRef Name) override;
4707 void getTargetDefines(const LangOptions &Opts,
4708 MacroBuilder &Builder) const override {
4709 // Target identification.
4710 Builder.defineMacro("__arm");
4711 Builder.defineMacro("__arm__");
4713 // Target properties.
4714 Builder.defineMacro("__REGISTER_PREFIX__", "");
4716 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
4717 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
4718 if (getTriple().isWatchOS())
4719 Builder.defineMacro("__ARM_ARCH_7K__", "2");
4721 if (!CPUAttr.empty())
4722 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
4724 // ACLE 6.4.1 ARM/Thumb instruction set architecture
4725 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4726 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
4728 if (ArchVersion >= 8) {
4729 // ACLE 6.5.7 Crypto Extension
4731 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
4732 // ACLE 6.5.8 CRC32 Extension
4734 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
4735 // ACLE 6.5.10 Numeric Maximum and Minimum
4736 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
4737 // ACLE 6.5.9 Directed Rounding
4738 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
4741 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
4742 // is not defined for the M-profile.
4743 // NOTE that the deffault profile is assumed to be 'A'
4744 if (CPUProfile.empty() || CPUProfile != "M")
4745 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4747 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4748 // Thumb ISA (including v6-M). It is set to 2 if the core supports the
4749 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4750 if (supportsThumb2())
4751 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4752 else if (supportsThumb())
4753 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4755 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4756 // instruction set such as ARM or Thumb.
4757 Builder.defineMacro("__ARM_32BIT_STATE", "1");
4759 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4761 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4762 if (!CPUProfile.empty())
4763 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4765 // ACLE 6.4.3 Unaligned access supported in hardware
4767 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
4769 // ACLE 6.4.4 LDREX/STREX
4771 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX));
4774 if (ArchVersion == 5 ||
4775 (ArchVersion == 6 && CPUProfile != "M") ||
4777 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
4779 // ACLE 6.5.1 Hardware Floating Point
4781 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4784 Builder.defineMacro("__ARM_ACLE", "200");
4786 // FP16 support (we currently only support IEEE format).
4787 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
4788 Builder.defineMacro("__ARM_FP16_ARGS", "1");
4790 // ACLE 6.5.3 Fused multiply-accumulate (FMA)
4791 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM"))
4792 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
4794 // Subtarget options.
4796 // FIXME: It's more complicated than this and we don't really support
4798 // Windows on ARM does not "support" interworking
4799 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows())
4800 Builder.defineMacro("__THUMB_INTERWORK__");
4802 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4803 // Embedded targets on Darwin follow AAPCS, but not EABI.
4804 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4805 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4806 Builder.defineMacro("__ARM_EABI__");
4807 Builder.defineMacro("__ARM_PCS", "1");
4809 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4810 Builder.defineMacro("__ARM_PCS_VFP", "1");
4814 Builder.defineMacro("__SOFTFP__");
4816 if (CPU == "xscale")
4817 Builder.defineMacro("__XSCALE__");
4820 Builder.defineMacro("__THUMBEL__");
4821 Builder.defineMacro("__thumb__");
4822 if (supportsThumb2())
4823 Builder.defineMacro("__thumb2__");
4826 // ACLE 6.4.9 32-bit SIMD instructions
4827 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
4828 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
4830 // ACLE 6.4.10 Hardware Integer Divide
4831 if (((HWDiv & HWDivThumb) && isThumb()) ||
4832 ((HWDiv & HWDivARM) && !isThumb())) {
4833 Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
4834 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4837 // Note, this is always on in gcc, even though it doesn't make sense.
4838 Builder.defineMacro("__APCS_32__");
4840 if (FPUModeIsVFP((FPUMode) FPU)) {
4841 Builder.defineMacro("__VFP_FP__");
4843 Builder.defineMacro("__ARM_VFPV2__");
4845 Builder.defineMacro("__ARM_VFPV3__");
4847 Builder.defineMacro("__ARM_VFPV4__");
4850 // This only gets set when Neon instructions are actually available, unlike
4851 // the VFP define, hence the soft float and arch check. This is subtly
4852 // different from gcc, we follow the intent which was that it should be set
4853 // when Neon instructions are actually available.
4854 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
4855 Builder.defineMacro("__ARM_NEON", "1");
4856 Builder.defineMacro("__ARM_NEON__");
4857 // current AArch32 NEON implementations do not support double-precision
4858 // floating-point even when it is present in VFP.
4859 Builder.defineMacro("__ARM_NEON_FP",
4860 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP));
4863 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4864 Opts.ShortWChar ? "2" : "4");
4866 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4867 Opts.ShortEnums ? "1" : "4");
4869 if (ArchVersion >= 6 && CPUAttr != "6M") {
4870 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4871 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4872 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4873 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4876 // ACLE 6.4.7 DSP instructions
4878 Builder.defineMacro("__ARM_FEATURE_DSP", "1");
4881 // ACLE 6.4.8 Saturation instructions
4883 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) {
4884 Builder.defineMacro("__ARM_FEATURE_SAT", "1");
4888 // ACLE 6.4.6 Q (saturation) flag
4890 Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
4892 if (Opts.UnsafeFPMath)
4893 Builder.defineMacro("__ARM_FP_FAST", "1");
4895 if (ArchKind == llvm::ARM::AK_ARMV8_1A)
4896 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
4899 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4900 return llvm::makeArrayRef(BuiltinInfo,
4901 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin);
4903 bool isCLZForZeroUndef() const override { return false; }
4904 BuiltinVaListKind getBuiltinVaListKind() const override {
4906 ? AAPCSABIBuiltinVaList
4907 : (getTriple().isWatchOS() ? TargetInfo::CharPtrBuiltinVaList
4908 : TargetInfo::VoidPtrBuiltinVaList);
4910 ArrayRef<const char *> getGCCRegNames() const override;
4911 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
4912 bool validateAsmConstraint(const char *&Name,
4913 TargetInfo::ConstraintInfo &Info) const override {
4918 case 'w': // VFP Floating point register single precision
4919 case 'P': // VFP Floating point register double precision
4920 Info.setAllowsRegister();
4929 case 'Q': // A memory address that is a single base register.
4930 Info.setAllowsMemory();
4932 case 'U': // a memory reference...
4934 case 'q': // ...ARMV4 ldrsb
4935 case 'v': // ...VFP load/store (reg+constant offset)
4936 case 'y': // ...iWMMXt load/store
4937 case 't': // address valid for load/store opaque types wider
4939 case 'n': // valid address for Neon doubleword vector load/store
4940 case 'm': // valid address for Neon element and structure load/store
4941 case 's': // valid address for non-offset loads/stores of quad-word
4942 // values in four ARM registers
4943 Info.setAllowsMemory();
4950 std::string convertConstraint(const char *&Constraint) const override {
4952 switch (*Constraint) {
4953 case 'U': // Two-character constraint; add "^" hint for later parsing.
4954 R = std::string("^") + std::string(Constraint, 2);
4957 case 'p': // 'p' should be translated to 'r' by default.
4958 R = std::string("r");
4961 return std::string(1, *Constraint);
4966 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4967 std::string &SuggestedModifier) const override {
4968 bool isOutput = (Constraint[0] == '=');
4969 bool isInOut = (Constraint[0] == '+');
4971 // Strip off constraint modifiers.
4972 while (Constraint[0] == '=' ||
4973 Constraint[0] == '+' ||
4974 Constraint[0] == '&')
4975 Constraint = Constraint.substr(1);
4977 switch (Constraint[0]) {
4982 return (isInOut || isOutput || Size <= 64);
4984 // A register of size 32 cannot fit a vector type.
4992 const char *getClobbers() const override {
4993 // FIXME: Is this really right?
4997 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4998 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
5001 int getEHDataRegisterNumber(unsigned RegNo) const override {
5002 if (RegNo == 0) return 0;
5003 if (RegNo == 1) return 1;
5007 bool hasSjLjLowering() const override {
5012 bool ARMTargetInfo::setFPMath(StringRef Name) {
5013 if (Name == "neon") {
5016 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
5024 const char * const ARMTargetInfo::GCCRegNames[] = {
5025 // Integer registers
5026 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5027 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
5030 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
5031 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
5032 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
5033 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5036 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
5037 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
5038 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
5039 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5042 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
5043 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
5046 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
5047 return llvm::makeArrayRef(GCCRegNames);
5050 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
5060 { { "v6", "rfp" }, "r9" },
5061 { { "sl" }, "r10" },
5062 { { "fp" }, "r11" },
5063 { { "ip" }, "r12" },
5064 { { "r13" }, "sp" },
5065 { { "r14" }, "lr" },
5066 { { "r15" }, "pc" },
5067 // The S, D and Q registers overlap, but aren't really aliases; we
5068 // don't want to substitute one of these for a different-sized one.
5071 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
5072 return llvm::makeArrayRef(GCCRegAliases);
5075 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
5076 #define BUILTIN(ID, TYPE, ATTRS) \
5077 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5078 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5079 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5080 #include "clang/Basic/BuiltinsNEON.def"
5082 #define BUILTIN(ID, TYPE, ATTRS) \
5083 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5084 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \
5085 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr },
5086 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5087 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5088 #include "clang/Basic/BuiltinsARM.def"
5091 class ARMleTargetInfo : public ARMTargetInfo {
5093 ARMleTargetInfo(const llvm::Triple &Triple)
5094 : ARMTargetInfo(Triple, false) { }
5095 void getTargetDefines(const LangOptions &Opts,
5096 MacroBuilder &Builder) const override {
5097 Builder.defineMacro("__ARMEL__");
5098 ARMTargetInfo::getTargetDefines(Opts, Builder);
5102 class ARMbeTargetInfo : public ARMTargetInfo {
5104 ARMbeTargetInfo(const llvm::Triple &Triple)
5105 : ARMTargetInfo(Triple, true) { }
5106 void getTargetDefines(const LangOptions &Opts,
5107 MacroBuilder &Builder) const override {
5108 Builder.defineMacro("__ARMEB__");
5109 Builder.defineMacro("__ARM_BIG_ENDIAN");
5110 ARMTargetInfo::getTargetDefines(Opts, Builder);
5114 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
5115 const llvm::Triple Triple;
5117 WindowsARMTargetInfo(const llvm::Triple &Triple)
5118 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
5119 TLSSupported = false;
5120 WCharType = UnsignedShort;
5121 SizeType = UnsignedInt;
5122 UserLabelPrefix = "";
5124 void getVisualStudioDefines(const LangOptions &Opts,
5125 MacroBuilder &Builder) const {
5126 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
5128 // FIXME: this is invalid for WindowsCE
5129 Builder.defineMacro("_M_ARM_NT", "1");
5130 Builder.defineMacro("_M_ARMT", "_M_ARM");
5131 Builder.defineMacro("_M_THUMB", "_M_ARM");
5133 assert((Triple.getArch() == llvm::Triple::arm ||
5134 Triple.getArch() == llvm::Triple::thumb) &&
5135 "invalid architecture for Windows ARM target info");
5136 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
5137 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
5139 // TODO map the complete set of values
5140 // 31: VFPv3 40: VFPv4
5141 Builder.defineMacro("_M_ARM_FP", "31");
5143 BuiltinVaListKind getBuiltinVaListKind() const override {
5144 return TargetInfo::CharPtrBuiltinVaList;
5146 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5149 case CC_X86ThisCall:
5150 case CC_X86FastCall:
5151 case CC_X86VectorCall:
5156 return CCCR_Warning;
5161 // Windows ARM + Itanium C++ ABI Target
5162 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
5164 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
5165 : WindowsARMTargetInfo(Triple) {
5166 TheCXXABI.set(TargetCXXABI::GenericARM);
5169 void getTargetDefines(const LangOptions &Opts,
5170 MacroBuilder &Builder) const override {
5171 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5173 if (Opts.MSVCCompat)
5174 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5178 // Windows ARM, MS (C++) ABI
5179 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
5181 MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
5182 : WindowsARMTargetInfo(Triple) {
5183 TheCXXABI.set(TargetCXXABI::Microsoft);
5186 void getTargetDefines(const LangOptions &Opts,
5187 MacroBuilder &Builder) const override {
5188 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5189 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5194 class MinGWARMTargetInfo : public WindowsARMTargetInfo {
5196 MinGWARMTargetInfo(const llvm::Triple &Triple)
5197 : WindowsARMTargetInfo(Triple) {
5198 TheCXXABI.set(TargetCXXABI::GenericARM);
5201 void getTargetDefines(const LangOptions &Opts,
5202 MacroBuilder &Builder) const override {
5203 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5204 DefineStd(Builder, "WIN32", Opts);
5205 DefineStd(Builder, "WINNT", Opts);
5206 Builder.defineMacro("_ARM_");
5207 addMinGWDefines(Opts, Builder);
5211 // ARM Cygwin target
5212 class CygwinARMTargetInfo : public ARMleTargetInfo {
5214 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) {
5215 TLSSupported = false;
5216 WCharType = UnsignedShort;
5217 DoubleAlign = LongLongAlign = 64;
5218 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
5220 void getTargetDefines(const LangOptions &Opts,
5221 MacroBuilder &Builder) const override {
5222 ARMleTargetInfo::getTargetDefines(Opts, Builder);
5223 Builder.defineMacro("_ARM_");
5224 Builder.defineMacro("__CYGWIN__");
5225 Builder.defineMacro("__CYGWIN32__");
5226 DefineStd(Builder, "unix", Opts);
5228 Builder.defineMacro("_GNU_SOURCE");
5232 class DarwinARMTargetInfo :
5233 public DarwinTargetInfo<ARMleTargetInfo> {
5235 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5236 MacroBuilder &Builder) const override {
5237 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5241 DarwinARMTargetInfo(const llvm::Triple &Triple)
5242 : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
5243 HasAlignMac68kSupport = true;
5244 // iOS always has 64-bit atomic instructions.
5245 // FIXME: This should be based off of the target features in
5247 MaxAtomicInlineWidth = 64;
5249 if (Triple.isWatchOS()) {
5250 // Darwin on iOS uses a variant of the ARM C++ ABI.
5251 TheCXXABI.set(TargetCXXABI::WatchOS);
5253 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that
5254 // size_t is long, it's a bit weird for it to be int.
5255 PtrDiffType = SignedLong;
5257 // BOOL should be a real boolean on the new ABI
5258 UseSignedCharForObjCBool = false;
5260 TheCXXABI.set(TargetCXXABI::iOS);
5264 class AArch64TargetInfo : public TargetInfo {
5265 virtual void setDataLayoutString() = 0;
5266 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5267 static const char *const GCCRegNames[];
5280 static const Builtin::Info BuiltinInfo[];
5285 AArch64TargetInfo(const llvm::Triple &Triple)
5286 : TargetInfo(Triple), ABI("aapcs") {
5288 if (getTriple().getOS() == llvm::Triple::NetBSD) {
5289 WCharType = SignedInt;
5291 // NetBSD apparently prefers consistency across ARM targets to consistency
5292 // across 64-bit targets.
5293 Int64Type = SignedLongLong;
5294 IntMaxType = SignedLongLong;
5296 WCharType = UnsignedInt;
5297 Int64Type = SignedLong;
5298 IntMaxType = SignedLong;
5301 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5302 MaxVectorAlign = 128;
5303 MaxAtomicInlineWidth = 128;
5304 MaxAtomicPromoteWidth = 128;
5306 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
5307 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5309 // {} in inline assembly are neon specifiers, not assembly variant
5311 NoAsmVariants = true;
5313 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
5314 // contributes to the alignment of the containing aggregate in the same way
5315 // a plain (non bit-field) member of that type would, without exception for
5316 // zero-sized or anonymous bit-fields."
5317 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
5318 UseZeroLengthBitfieldAlignment = true;
5320 // AArch64 targets default to using the ARM C++ ABI.
5321 TheCXXABI.set(TargetCXXABI::GenericAArch64);
5324 StringRef getABI() const override { return ABI; }
5325 bool setABI(const std::string &Name) override {
5326 if (Name != "aapcs" && Name != "darwinpcs")
5333 bool setCPU(const std::string &Name) override {
5334 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5335 .Case("generic", true)
5336 .Cases("cortex-a53", "cortex-a57", "cortex-a72",
5337 "cortex-a35", "exynos-m1", true)
5338 .Case("cyclone", true)
5343 void getTargetDefines(const LangOptions &Opts,
5344 MacroBuilder &Builder) const override {
5345 // Target identification.
5346 Builder.defineMacro("__aarch64__");
5348 // Target properties.
5349 Builder.defineMacro("_LP64");
5350 Builder.defineMacro("__LP64__");
5352 // ACLE predefines. Many can only have one possible value on v8 AArch64.
5353 Builder.defineMacro("__ARM_ACLE", "200");
5354 Builder.defineMacro("__ARM_ARCH", "8");
5355 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
5357 Builder.defineMacro("__ARM_64BIT_STATE", "1");
5358 Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
5359 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
5361 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
5362 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
5363 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
5364 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
5365 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
5366 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
5367 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
5369 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
5371 // 0xe implies support for half, single and double precision operations.
5372 Builder.defineMacro("__ARM_FP", "0xE");
5374 // PCS specifies this for SysV variants, which is all we support. Other ABIs
5375 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
5376 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
5377 Builder.defineMacro("__ARM_FP16_ARGS", "1");
5379 if (Opts.UnsafeFPMath)
5380 Builder.defineMacro("__ARM_FP_FAST", "1");
5382 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
5384 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5385 Opts.ShortEnums ? "1" : "4");
5387 if (FPU == NeonMode) {
5388 Builder.defineMacro("__ARM_NEON", "1");
5389 // 64-bit NEON supports half, single and double precision operations.
5390 Builder.defineMacro("__ARM_NEON_FP", "0xE");
5394 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
5397 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
5400 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
5403 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
5405 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
5406 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
5407 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
5408 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
5409 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
5412 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5413 return llvm::makeArrayRef(BuiltinInfo,
5414 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin);
5417 bool hasFeature(StringRef Feature) const override {
5418 return Feature == "aarch64" ||
5419 Feature == "arm64" ||
5421 (Feature == "neon" && FPU == NeonMode);
5424 bool handleTargetFeatures(std::vector<std::string> &Features,
5425 DiagnosticsEngine &Diags) override {
5432 for (const auto &Feature : Features) {
5433 if (Feature == "+neon")
5435 if (Feature == "+crc")
5437 if (Feature == "+crypto")
5439 if (Feature == "+strict-align")
5441 if (Feature == "+v8.1a")
5445 setDataLayoutString();
5450 bool isCLZForZeroUndef() const override { return false; }
5452 BuiltinVaListKind getBuiltinVaListKind() const override {
5453 return TargetInfo::AArch64ABIBuiltinVaList;
5456 ArrayRef<const char *> getGCCRegNames() const override;
5457 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5459 bool validateAsmConstraint(const char *&Name,
5460 TargetInfo::ConstraintInfo &Info) const override {
5464 case 'w': // Floating point and SIMD registers (V0-V31)
5465 Info.setAllowsRegister();
5467 case 'I': // Constant that can be used with an ADD instruction
5468 case 'J': // Constant that can be used with a SUB instruction
5469 case 'K': // Constant that can be used with a 32-bit logical instruction
5470 case 'L': // Constant that can be used with a 64-bit logical instruction
5471 case 'M': // Constant that can be used as a 32-bit MOV immediate
5472 case 'N': // Constant that can be used as a 64-bit MOV immediate
5473 case 'Y': // Floating point constant zero
5474 case 'Z': // Integer constant zero
5476 case 'Q': // A memory reference with base register and no offset
5477 Info.setAllowsMemory();
5479 case 'S': // A symbolic address
5480 Info.setAllowsRegister();
5483 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
5484 // Utf: A memory address suitable for ldp/stp in TF mode.
5485 // Usa: An absolute symbolic address.
5486 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
5487 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
5488 case 'z': // Zero register, wzr or xzr
5489 Info.setAllowsRegister();
5491 case 'x': // Floating point and SIMD registers (V0-V15)
5492 Info.setAllowsRegister();
5499 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5500 std::string &SuggestedModifier) const override {
5501 // Strip off constraint modifiers.
5502 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
5503 Constraint = Constraint.substr(1);
5505 switch (Constraint[0]) {
5513 // For now assume that the person knows what they're
5514 // doing with the modifier.
5517 // By default an 'r' constraint will be in the 'x'
5522 SuggestedModifier = "w";
5529 const char *getClobbers() const override { return ""; }
5531 int getEHDataRegisterNumber(unsigned RegNo) const override {
5540 const char *const AArch64TargetInfo::GCCRegNames[] = {
5541 // 32-bit Integer registers
5542 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
5543 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
5544 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
5546 // 64-bit Integer registers
5547 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
5548 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
5549 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
5551 // 32-bit floating point regsisters
5552 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
5553 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
5554 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5556 // 64-bit floating point regsisters
5557 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
5558 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
5559 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5562 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
5563 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
5564 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
5567 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
5568 return llvm::makeArrayRef(GCCRegNames);
5571 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
5572 { { "w31" }, "wsp" },
5573 { { "x29" }, "fp" },
5574 { { "x30" }, "lr" },
5575 { { "x31" }, "sp" },
5576 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
5577 // don't want to substitute one of these for a different-sized one.
5580 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
5581 return llvm::makeArrayRef(GCCRegAliases);
5584 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
5585 #define BUILTIN(ID, TYPE, ATTRS) \
5586 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5587 #include "clang/Basic/BuiltinsNEON.def"
5589 #define BUILTIN(ID, TYPE, ATTRS) \
5590 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5591 #include "clang/Basic/BuiltinsAArch64.def"
5594 class AArch64leTargetInfo : public AArch64TargetInfo {
5595 void setDataLayoutString() override {
5596 if (getTriple().isOSBinFormatMachO())
5597 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128";
5599 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128";
5603 AArch64leTargetInfo(const llvm::Triple &Triple)
5604 : AArch64TargetInfo(Triple) {
5607 void getTargetDefines(const LangOptions &Opts,
5608 MacroBuilder &Builder) const override {
5609 Builder.defineMacro("__AARCH64EL__");
5610 AArch64TargetInfo::getTargetDefines(Opts, Builder);
5614 class AArch64beTargetInfo : public AArch64TargetInfo {
5615 void setDataLayoutString() override {
5616 assert(!getTriple().isOSBinFormatMachO());
5617 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128";
5621 AArch64beTargetInfo(const llvm::Triple &Triple)
5622 : AArch64TargetInfo(Triple) { }
5623 void getTargetDefines(const LangOptions &Opts,
5624 MacroBuilder &Builder) const override {
5625 Builder.defineMacro("__AARCH64EB__");
5626 Builder.defineMacro("__AARCH_BIG_ENDIAN");
5627 Builder.defineMacro("__ARM_BIG_ENDIAN");
5628 AArch64TargetInfo::getTargetDefines(Opts, Builder);
5632 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
5634 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5635 MacroBuilder &Builder) const override {
5636 Builder.defineMacro("__AARCH64_SIMD__");
5637 Builder.defineMacro("__ARM64_ARCH_8__");
5638 Builder.defineMacro("__ARM_NEON__");
5639 Builder.defineMacro("__LITTLE_ENDIAN__");
5640 Builder.defineMacro("__REGISTER_PREFIX__", "");
5641 Builder.defineMacro("__arm64", "1");
5642 Builder.defineMacro("__arm64__", "1");
5644 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5648 DarwinAArch64TargetInfo(const llvm::Triple &Triple)
5649 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
5650 Int64Type = SignedLongLong;
5651 WCharType = SignedInt;
5652 UseSignedCharForObjCBool = false;
5654 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
5655 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5657 TheCXXABI.set(TargetCXXABI::iOS64);
5660 BuiltinVaListKind getBuiltinVaListKind() const override {
5661 return TargetInfo::CharPtrBuiltinVaList;
5665 // Hexagon abstract base class
5666 class HexagonTargetInfo : public TargetInfo {
5667 static const Builtin::Info BuiltinInfo[];
5668 static const char * const GCCRegNames[];
5669 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5671 bool HasHVX, HasHVXDouble;
5674 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5676 DataLayoutString = "e-m:e-p:32:32:32-"
5677 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-"
5678 "f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32";
5679 SizeType = UnsignedInt;
5680 PtrDiffType = SignedInt;
5681 IntPtrType = SignedInt;
5683 // {} in inline assembly are packet specifiers, not assembly variant
5685 NoAsmVariants = true;
5687 LargeArrayMinWidth = 64;
5688 LargeArrayAlign = 64;
5689 UseBitFieldTypeAlignment = true;
5690 ZeroLengthBitfieldBoundary = 32;
5691 HasHVX = HasHVXDouble = false;
5694 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5695 return llvm::makeArrayRef(BuiltinInfo,
5696 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin);
5699 bool validateAsmConstraint(const char *&Name,
5700 TargetInfo::ConstraintInfo &Info) const override {
5704 void getTargetDefines(const LangOptions &Opts,
5705 MacroBuilder &Builder) const override;
5707 bool isCLZForZeroUndef() const override { return false; }
5709 bool hasFeature(StringRef Feature) const override {
5710 return llvm::StringSwitch<bool>(Feature)
5711 .Case("hexagon", true)
5712 .Case("hvx", HasHVX)
5713 .Case("hvx-double", HasHVXDouble)
5717 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
5718 StringRef CPU, const std::vector<std::string> &FeaturesVec)
5721 bool handleTargetFeatures(std::vector<std::string> &Features,
5722 DiagnosticsEngine &Diags) override;
5724 BuiltinVaListKind getBuiltinVaListKind() const override {
5725 return TargetInfo::CharPtrBuiltinVaList;
5727 ArrayRef<const char *> getGCCRegNames() const override;
5728 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5729 const char *getClobbers() const override {
5733 static const char *getHexagonCPUSuffix(StringRef Name) {
5734 return llvm::StringSwitch<const char*>(Name)
5735 .Case("hexagonv4", "4")
5736 .Case("hexagonv5", "5")
5737 .Case("hexagonv55", "55")
5738 .Case("hexagonv60", "60")
5742 bool setCPU(const std::string &Name) override {
5743 if (!getHexagonCPUSuffix(Name))
5749 int getEHDataRegisterNumber(unsigned RegNo) const override {
5750 return RegNo < 2 ? RegNo : -1;
5754 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5755 MacroBuilder &Builder) const {
5756 Builder.defineMacro("__qdsp6__", "1");
5757 Builder.defineMacro("__hexagon__", "1");
5759 if (CPU == "hexagonv4") {
5760 Builder.defineMacro("__HEXAGON_V4__");
5761 Builder.defineMacro("__HEXAGON_ARCH__", "4");
5762 if (Opts.HexagonQdsp6Compat) {
5763 Builder.defineMacro("__QDSP6_V4__");
5764 Builder.defineMacro("__QDSP6_ARCH__", "4");
5766 } else if (CPU == "hexagonv5") {
5767 Builder.defineMacro("__HEXAGON_V5__");
5768 Builder.defineMacro("__HEXAGON_ARCH__", "5");
5769 if(Opts.HexagonQdsp6Compat) {
5770 Builder.defineMacro("__QDSP6_V5__");
5771 Builder.defineMacro("__QDSP6_ARCH__", "5");
5773 } else if (CPU == "hexagonv60") {
5774 Builder.defineMacro("__HEXAGON_V60__");
5775 Builder.defineMacro("__HEXAGON_ARCH__", "60");
5776 Builder.defineMacro("__QDSP6_V60__");
5777 Builder.defineMacro("__QDSP6_ARCH__", "60");
5781 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
5782 DiagnosticsEngine &Diags) {
5783 for (auto &F : Features) {
5786 else if (F == "-hvx")
5787 HasHVX = HasHVXDouble = false;
5788 else if (F == "+hvx-double")
5789 HasHVX = HasHVXDouble = true;
5790 else if (F == "-hvx-double")
5791 HasHVXDouble = false;
5796 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features,
5797 DiagnosticsEngine &Diags, StringRef CPU,
5798 const std::vector<std::string> &FeaturesVec) const {
5799 // Default for v60: -hvx, -hvx-double.
5800 Features["hvx"] = false;
5801 Features["hvx-double"] = false;
5803 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
5807 const char *const HexagonTargetInfo::GCCRegNames[] = {
5808 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5809 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5810 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5811 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5812 "p0", "p1", "p2", "p3",
5813 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5816 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const {
5817 return llvm::makeArrayRef(GCCRegNames);
5820 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5821 { { "sp" }, "r29" },
5822 { { "fp" }, "r30" },
5823 { { "lr" }, "r31" },
5826 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const {
5827 return llvm::makeArrayRef(GCCRegAliases);
5831 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5832 #define BUILTIN(ID, TYPE, ATTRS) \
5833 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5834 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5835 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5836 #include "clang/Basic/BuiltinsHexagon.def"
5839 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5840 class SparcTargetInfo : public TargetInfo {
5841 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5842 static const char * const GCCRegNames[];
5845 SparcTargetInfo(const llvm::Triple &Triple)
5846 : TargetInfo(Triple), SoftFloat(false) {}
5848 bool handleTargetFeatures(std::vector<std::string> &Features,
5849 DiagnosticsEngine &Diags) override {
5850 // The backend doesn't actually handle soft float yet, but in case someone
5851 // is using the support for the front end continue to support it.
5852 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
5853 if (Feature != Features.end()) {
5855 Features.erase(Feature);
5859 void getTargetDefines(const LangOptions &Opts,
5860 MacroBuilder &Builder) const override {
5861 DefineStd(Builder, "sparc", Opts);
5862 Builder.defineMacro("__REGISTER_PREFIX__", "");
5865 Builder.defineMacro("SOFT_FLOAT", "1");
5868 bool hasFeature(StringRef Feature) const override {
5869 return llvm::StringSwitch<bool>(Feature)
5870 .Case("softfloat", SoftFloat)
5871 .Case("sparc", true)
5875 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5876 // FIXME: Implement!
5879 BuiltinVaListKind getBuiltinVaListKind() const override {
5880 return TargetInfo::VoidPtrBuiltinVaList;
5882 ArrayRef<const char *> getGCCRegNames() const override;
5883 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5884 bool validateAsmConstraint(const char *&Name,
5885 TargetInfo::ConstraintInfo &info) const override {
5886 // FIXME: Implement!
5888 case 'I': // Signed 13-bit constant
5890 case 'K': // 32-bit constant with the low 12 bits clear
5891 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5892 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5893 case 'N': // Same as 'K' but zext (required for SIMode)
5894 case 'O': // The constant 4096
5899 const char *getClobbers() const override {
5900 // FIXME: Implement!
5904 // No Sparc V7 for now, the backend doesn't support it anyway.
5924 enum CPUGeneration {
5929 CPUGeneration getCPUGeneration(CPUKind Kind) const {
5937 case CK_SPARCLITE86X:
5943 case CK_ULTRASPARC3:
5950 llvm_unreachable("Unexpected CPU kind");
5953 CPUKind getCPUKind(StringRef Name) const {
5954 return llvm::StringSwitch<CPUKind>(Name)
5956 .Case("supersparc", CK_SUPERSPARC)
5957 .Case("sparclite", CK_SPARCLITE)
5958 .Case("f934", CK_F934)
5959 .Case("hypersparc", CK_HYPERSPARC)
5960 .Case("sparclite86x", CK_SPARCLITE86X)
5961 .Case("sparclet", CK_SPARCLET)
5962 .Case("tsc701", CK_TSC701)
5964 .Case("ultrasparc", CK_ULTRASPARC)
5965 .Case("ultrasparc3", CK_ULTRASPARC3)
5966 .Case("niagara", CK_NIAGARA)
5967 .Case("niagara2", CK_NIAGARA2)
5968 .Case("niagara3", CK_NIAGARA3)
5969 .Case("niagara4", CK_NIAGARA4)
5970 .Default(CK_GENERIC);
5973 bool setCPU(const std::string &Name) override {
5974 CPU = getCPUKind(Name);
5975 return CPU != CK_GENERIC;
5979 const char * const SparcTargetInfo::GCCRegNames[] = {
5980 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5981 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5982 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5983 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5986 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
5987 return llvm::makeArrayRef(GCCRegNames);
5990 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
6001 { { "o2" }, "r10" },
6002 { { "o3" }, "r11" },
6003 { { "o4" }, "r12" },
6004 { { "o5" }, "r13" },
6005 { { "o6", "sp" }, "r14" },
6006 { { "o7" }, "r15" },
6007 { { "l0" }, "r16" },
6008 { { "l1" }, "r17" },
6009 { { "l2" }, "r18" },
6010 { { "l3" }, "r19" },
6011 { { "l4" }, "r20" },
6012 { { "l5" }, "r21" },
6013 { { "l6" }, "r22" },
6014 { { "l7" }, "r23" },
6015 { { "i0" }, "r24" },
6016 { { "i1" }, "r25" },
6017 { { "i2" }, "r26" },
6018 { { "i3" }, "r27" },
6019 { { "i4" }, "r28" },
6020 { { "i5" }, "r29" },
6021 { { "i6", "fp" }, "r30" },
6022 { { "i7" }, "r31" },
6025 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
6026 return llvm::makeArrayRef(GCCRegAliases);
6029 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
6030 class SparcV8TargetInfo : public SparcTargetInfo {
6032 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
6033 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
6034 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
6035 switch (getTriple().getOS()) {
6037 SizeType = UnsignedInt;
6038 IntPtrType = SignedInt;
6039 PtrDiffType = SignedInt;
6041 case llvm::Triple::NetBSD:
6042 case llvm::Triple::OpenBSD:
6043 SizeType = UnsignedLong;
6044 IntPtrType = SignedLong;
6045 PtrDiffType = SignedLong;
6050 void getTargetDefines(const LangOptions &Opts,
6051 MacroBuilder &Builder) const override {
6052 SparcTargetInfo::getTargetDefines(Opts, Builder);
6053 switch (getCPUGeneration(CPU)) {
6055 Builder.defineMacro("__sparcv8");
6056 if (getTriple().getOS() != llvm::Triple::Solaris)
6057 Builder.defineMacro("__sparcv8__");
6060 Builder.defineMacro("__sparcv9");
6061 if (getTriple().getOS() != llvm::Triple::Solaris) {
6062 Builder.defineMacro("__sparcv9__");
6063 Builder.defineMacro("__sparc_v9__");
6070 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
6071 class SparcV8elTargetInfo : public SparcV8TargetInfo {
6073 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) {
6074 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64";
6079 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
6080 class SparcV9TargetInfo : public SparcTargetInfo {
6082 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
6083 // FIXME: Support Sparc quad-precision long double?
6084 DataLayoutString = "E-m:e-i64:64-n32:64-S128";
6085 // This is an LP64 platform.
6086 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6088 // OpenBSD uses long long for int64_t and intmax_t.
6089 if (getTriple().getOS() == llvm::Triple::OpenBSD)
6090 IntMaxType = SignedLongLong;
6092 IntMaxType = SignedLong;
6093 Int64Type = IntMaxType;
6095 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
6096 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
6097 LongDoubleWidth = 128;
6098 LongDoubleAlign = 128;
6099 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6100 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6103 void getTargetDefines(const LangOptions &Opts,
6104 MacroBuilder &Builder) const override {
6105 SparcTargetInfo::getTargetDefines(Opts, Builder);
6106 Builder.defineMacro("__sparcv9");
6107 Builder.defineMacro("__arch64__");
6108 // Solaris doesn't need these variants, but the BSDs do.
6109 if (getTriple().getOS() != llvm::Triple::Solaris) {
6110 Builder.defineMacro("__sparc64__");
6111 Builder.defineMacro("__sparc_v9__");
6112 Builder.defineMacro("__sparcv9__");
6116 bool setCPU(const std::string &Name) override {
6117 if (!SparcTargetInfo::setCPU(Name))
6119 return getCPUGeneration(CPU) == CG_V9;
6123 class SystemZTargetInfo : public TargetInfo {
6124 static const Builtin::Info BuiltinInfo[];
6125 static const char *const GCCRegNames[];
6127 bool HasTransactionalExecution;
6131 SystemZTargetInfo(const llvm::Triple &Triple)
6132 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false),
6134 IntMaxType = SignedLong;
6135 Int64Type = SignedLong;
6136 TLSSupported = true;
6137 IntWidth = IntAlign = 32;
6138 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
6139 PointerWidth = PointerAlign = 64;
6140 LongDoubleWidth = 128;
6141 LongDoubleAlign = 64;
6142 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6143 DefaultAlignForAttributeAligned = 64;
6144 MinGlobalAlign = 16;
6145 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
6146 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6148 void getTargetDefines(const LangOptions &Opts,
6149 MacroBuilder &Builder) const override {
6150 Builder.defineMacro("__s390__");
6151 Builder.defineMacro("__s390x__");
6152 Builder.defineMacro("__zarch__");
6153 Builder.defineMacro("__LONG_DOUBLE_128__");
6154 if (HasTransactionalExecution)
6155 Builder.defineMacro("__HTM__");
6157 Builder.defineMacro("__VEC__", "10301");
6159 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6160 return llvm::makeArrayRef(BuiltinInfo,
6161 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin);
6164 ArrayRef<const char *> getGCCRegNames() const override;
6165 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6169 bool validateAsmConstraint(const char *&Name,
6170 TargetInfo::ConstraintInfo &info) const override;
6171 const char *getClobbers() const override {
6172 // FIXME: Is this really right?
6175 BuiltinVaListKind getBuiltinVaListKind() const override {
6176 return TargetInfo::SystemZBuiltinVaList;
6178 bool setCPU(const std::string &Name) override {
6180 bool CPUKnown = llvm::StringSwitch<bool>(Name)
6183 .Case("zEC12", true)
6190 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6192 const std::vector<std::string> &FeaturesVec) const override {
6194 Features["transactional-execution"] = true;
6196 Features["transactional-execution"] = true;
6197 Features["vector"] = true;
6199 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6202 bool handleTargetFeatures(std::vector<std::string> &Features,
6203 DiagnosticsEngine &Diags) override {
6204 HasTransactionalExecution = false;
6205 for (const auto &Feature : Features) {
6206 if (Feature == "+transactional-execution")
6207 HasTransactionalExecution = true;
6208 else if (Feature == "+vector")
6211 // If we use the vector ABI, vector types are 64-bit aligned.
6213 MaxVectorAlign = 64;
6214 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
6215 "-v128:64-a:8:16-n32:64";
6220 bool hasFeature(StringRef Feature) const override {
6221 return llvm::StringSwitch<bool>(Feature)
6222 .Case("systemz", true)
6223 .Case("htm", HasTransactionalExecution)
6224 .Case("vx", HasVector)
6228 StringRef getABI() const override {
6234 bool useFloat128ManglingForLongDouble() const override {
6239 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
6240 #define BUILTIN(ID, TYPE, ATTRS) \
6241 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6242 #include "clang/Basic/BuiltinsSystemZ.def"
6245 const char *const SystemZTargetInfo::GCCRegNames[] = {
6246 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6247 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6248 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
6249 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
6252 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
6253 return llvm::makeArrayRef(GCCRegNames);
6256 bool SystemZTargetInfo::
6257 validateAsmConstraint(const char *&Name,
6258 TargetInfo::ConstraintInfo &Info) const {
6263 case 'a': // Address register
6264 case 'd': // Data register (equivalent to 'r')
6265 case 'f': // Floating-point register
6266 Info.setAllowsRegister();
6269 case 'I': // Unsigned 8-bit constant
6270 case 'J': // Unsigned 12-bit constant
6271 case 'K': // Signed 16-bit constant
6272 case 'L': // Signed 20-bit displacement (on all targets we support)
6273 case 'M': // 0x7fffffff
6276 case 'Q': // Memory with base and unsigned 12-bit displacement
6277 case 'R': // Likewise, plus an index
6278 case 'S': // Memory with base and signed 20-bit displacement
6279 case 'T': // Likewise, plus an index
6280 Info.setAllowsMemory();
6285 class MSP430TargetInfo : public TargetInfo {
6286 static const char *const GCCRegNames[];
6289 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6291 TLSSupported = false;
6296 LongAlign = LongLongAlign = 16;
6300 SizeType = UnsignedInt;
6301 IntMaxType = SignedLongLong;
6302 IntPtrType = SignedInt;
6303 PtrDiffType = SignedInt;
6304 SigAtomicType = SignedLong;
6305 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
6307 void getTargetDefines(const LangOptions &Opts,
6308 MacroBuilder &Builder) const override {
6309 Builder.defineMacro("MSP430");
6310 Builder.defineMacro("__MSP430__");
6311 // FIXME: defines for different 'flavours' of MCU
6313 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6314 // FIXME: Implement.
6317 bool hasFeature(StringRef Feature) const override {
6318 return Feature == "msp430";
6320 ArrayRef<const char *> getGCCRegNames() const override;
6321 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6325 bool validateAsmConstraint(const char *&Name,
6326 TargetInfo::ConstraintInfo &info) const override {
6329 case 'K': // the constant 1
6330 case 'L': // constant -1^20 .. 1^19
6331 case 'M': // constant 1-4:
6334 // No target constraints for now.
6337 const char *getClobbers() const override {
6338 // FIXME: Is this really right?
6341 BuiltinVaListKind getBuiltinVaListKind() const override {
6343 return TargetInfo::CharPtrBuiltinVaList;
6347 const char *const MSP430TargetInfo::GCCRegNames[] = {
6348 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6349 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
6351 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const {
6352 return llvm::makeArrayRef(GCCRegNames);
6355 // LLVM and Clang cannot be used directly to output native binaries for
6356 // target, but is used to compile C code to llvm bitcode with correct
6357 // type and alignment information.
6359 // TCE uses the llvm bitcode as input and uses it for generating customized
6360 // target processor and program binary. TCE co-design environment is
6361 // publicly available in http://tce.cs.tut.fi
6363 static const unsigned TCEOpenCLAddrSpaceMap[] = {
6366 5, // opencl_constant
6367 // FIXME: generic has to be added to the target
6368 0, // opencl_generic
6374 class TCETargetInfo : public TargetInfo {
6376 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6377 TLSSupported = false;
6379 LongWidth = LongLongWidth = 32;
6382 LongAlign = LongLongAlign = 32;
6385 SizeType = UnsignedInt;
6386 IntMaxType = SignedLong;
6387 IntPtrType = SignedInt;
6388 PtrDiffType = SignedInt;
6393 LongDoubleWidth = 32;
6394 LongDoubleAlign = 32;
6395 FloatFormat = &llvm::APFloat::IEEEsingle;
6396 DoubleFormat = &llvm::APFloat::IEEEsingle;
6397 LongDoubleFormat = &llvm::APFloat::IEEEsingle;
6398 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
6399 "-f64:32-v64:32-v128:32-a:0:32-n32";
6400 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
6401 UseAddrSpaceMapMangling = true;
6404 void getTargetDefines(const LangOptions &Opts,
6405 MacroBuilder &Builder) const override {
6406 DefineStd(Builder, "tce", Opts);
6407 Builder.defineMacro("__TCE__");
6408 Builder.defineMacro("__TCE_V1__");
6410 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; }
6412 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
6413 const char *getClobbers() const override { return ""; }
6414 BuiltinVaListKind getBuiltinVaListKind() const override {
6415 return TargetInfo::VoidPtrBuiltinVaList;
6417 ArrayRef<const char *> getGCCRegNames() const override { return None; }
6418 bool validateAsmConstraint(const char *&Name,
6419 TargetInfo::ConstraintInfo &info) const override {
6422 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6427 class BPFTargetInfo : public TargetInfo {
6429 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6430 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6431 SizeType = UnsignedLong;
6432 PtrDiffType = SignedLong;
6433 IntPtrType = SignedLong;
6434 IntMaxType = SignedLong;
6435 Int64Type = SignedLong;
6437 if (Triple.getArch() == llvm::Triple::bpfeb) {
6439 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128";
6442 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128";
6444 MaxAtomicPromoteWidth = 64;
6445 MaxAtomicInlineWidth = 64;
6446 TLSSupported = false;
6448 void getTargetDefines(const LangOptions &Opts,
6449 MacroBuilder &Builder) const override {
6450 DefineStd(Builder, "bpf", Opts);
6451 Builder.defineMacro("__BPF__");
6453 bool hasFeature(StringRef Feature) const override {
6454 return Feature == "bpf";
6457 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
6458 const char *getClobbers() const override {
6461 BuiltinVaListKind getBuiltinVaListKind() const override {
6462 return TargetInfo::VoidPtrBuiltinVaList;
6464 ArrayRef<const char *> getGCCRegNames() const override {
6467 bool validateAsmConstraint(const char *&Name,
6468 TargetInfo::ConstraintInfo &info) const override {
6471 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6476 class MipsTargetInfoBase : public TargetInfo {
6477 virtual void setDataLayoutString() = 0;
6479 static const Builtin::Info BuiltinInfo[];
6486 HardFloat, SoftFloat
6498 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
6499 const std::string &CPUStr)
6500 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
6501 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
6502 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
6503 TheCXXABI.set(TargetCXXABI::GenericMIPS);
6506 bool isNaN2008Default() const {
6507 return CPU == "mips32r6" || CPU == "mips64r6";
6510 bool isFP64Default() const {
6511 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
6514 bool isNan2008() const override {
6518 StringRef getABI() const override { return ABI; }
6519 bool setCPU(const std::string &Name) override {
6520 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
6521 getTriple().getArch() == llvm::Triple::mipsel;
6523 return llvm::StringSwitch<bool>(Name)
6524 .Case("mips1", IsMips32)
6525 .Case("mips2", IsMips32)
6526 .Case("mips3", true)
6527 .Case("mips4", true)
6528 .Case("mips5", true)
6529 .Case("mips32", IsMips32)
6530 .Case("mips32r2", IsMips32)
6531 .Case("mips32r3", IsMips32)
6532 .Case("mips32r5", IsMips32)
6533 .Case("mips32r6", IsMips32)
6534 .Case("mips64", true)
6535 .Case("mips64r2", true)
6536 .Case("mips64r3", true)
6537 .Case("mips64r5", true)
6538 .Case("mips64r6", true)
6539 .Case("octeon", true)
6540 .Case("p5600", true)
6543 const std::string& getCPU() const { return CPU; }
6545 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6547 const std::vector<std::string> &FeaturesVec) const override {
6548 if (CPU == "octeon")
6549 Features["mips64r2"] = Features["cnmips"] = true;
6551 Features[CPU] = true;
6552 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6555 void getTargetDefines(const LangOptions &Opts,
6556 MacroBuilder &Builder) const override {
6557 Builder.defineMacro("__mips__");
6558 Builder.defineMacro("_mips");
6560 Builder.defineMacro("mips");
6562 Builder.defineMacro("__REGISTER_PREFIX__", "");
6566 Builder.defineMacro("__mips_hard_float", Twine(1));
6569 Builder.defineMacro("__mips_soft_float", Twine(1));
6574 Builder.defineMacro("__mips_single_float", Twine(1));
6576 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
6577 Builder.defineMacro("_MIPS_FPSET",
6578 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
6581 Builder.defineMacro("__mips16", Twine(1));
6584 Builder.defineMacro("__mips_micromips", Twine(1));
6587 Builder.defineMacro("__mips_nan2008", Twine(1));
6593 Builder.defineMacro("__mips_dsp_rev", Twine(1));
6594 Builder.defineMacro("__mips_dsp", Twine(1));
6597 Builder.defineMacro("__mips_dsp_rev", Twine(2));
6598 Builder.defineMacro("__mips_dspr2", Twine(1));
6599 Builder.defineMacro("__mips_dsp", Twine(1));
6604 Builder.defineMacro("__mips_msa", Twine(1));
6606 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
6607 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
6608 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
6610 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
6611 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
6613 // These shouldn't be defined for MIPS-I but there's no need to check
6614 // for that since MIPS-I isn't supported.
6615 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
6616 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
6617 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
6620 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6621 return llvm::makeArrayRef(BuiltinInfo,
6622 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin);
6624 bool hasFeature(StringRef Feature) const override {
6625 return llvm::StringSwitch<bool>(Feature)
6627 .Case("fp64", HasFP64)
6630 BuiltinVaListKind getBuiltinVaListKind() const override {
6631 return TargetInfo::VoidPtrBuiltinVaList;
6633 ArrayRef<const char *> getGCCRegNames() const override {
6634 static const char *const GCCRegNames[] = {
6635 // CPU register names
6636 // Must match second column of GCCRegAliases
6637 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
6638 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
6639 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
6640 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
6641 // Floating point register names
6642 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
6643 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
6644 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
6645 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
6646 // Hi/lo and condition register names
6647 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
6648 "$fcc5","$fcc6","$fcc7",
6649 // MSA register names
6650 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
6651 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
6652 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
6653 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
6654 // MSA control register names
6655 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
6656 "$msarequest", "$msamap", "$msaunmap"
6658 return llvm::makeArrayRef(GCCRegNames);
6660 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0;
6661 bool validateAsmConstraint(const char *&Name,
6662 TargetInfo::ConstraintInfo &Info) const override {
6666 case 'r': // CPU registers.
6667 case 'd': // Equivalent to "r" unless generating MIPS16 code.
6668 case 'y': // Equivalent to "r", backward compatibility only.
6669 case 'f': // floating-point registers.
6670 case 'c': // $25 for indirect jumps
6671 case 'l': // lo register
6672 case 'x': // hilo register pair
6673 Info.setAllowsRegister();
6675 case 'I': // Signed 16-bit constant
6676 case 'J': // Integer 0
6677 case 'K': // Unsigned 16-bit constant
6678 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
6679 case 'M': // Constants not loadable via lui, addiu, or ori
6680 case 'N': // Constant -1 to -65535
6681 case 'O': // A signed 15-bit constant
6682 case 'P': // A constant between 1 go 65535
6684 case 'R': // An address that can be used in a non-macro load or store
6685 Info.setAllowsMemory();
6688 if (Name[1] == 'C') { // An address usable by ll, and sc.
6689 Info.setAllowsMemory();
6690 Name++; // Skip over 'Z'.
6697 std::string convertConstraint(const char *&Constraint) const override {
6699 switch (*Constraint) {
6700 case 'Z': // Two-character constraint; add "^" hint for later parsing.
6701 if (Constraint[1] == 'C') {
6702 R = std::string("^") + std::string(Constraint, 2);
6708 return TargetInfo::convertConstraint(Constraint);
6711 const char *getClobbers() const override {
6712 // In GCC, $1 is not widely used in generated code (it's used only in a few
6713 // specific situations), so there is no real need for users to add it to
6714 // the clobbers list if they want to use it in their inline assembly code.
6716 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
6717 // code generation, so using it in inline assembly without adding it to the
6718 // clobbers list can cause conflicts between the inline assembly code and
6719 // the surrounding generated code.
6721 // Another problem is that LLVM is allowed to choose $1 for inline assembly
6722 // operands, which will conflict with the ".set at" assembler option (which
6723 // we use only for inline assembly, in order to maintain compatibility with
6724 // GCC) and will also conflict with the user's usage of $1.
6726 // The easiest way to avoid these conflicts and keep $1 as an allocatable
6727 // register for generated code is to automatically clobber $1 for all inline
6730 // FIXME: We should automatically clobber $1 only for inline assembly code
6731 // which actually uses it. This would allow LLVM to use $1 for inline
6732 // assembly operands if the user's assembly code doesn't use it.
6736 bool handleTargetFeatures(std::vector<std::string> &Features,
6737 DiagnosticsEngine &Diags) override {
6739 IsMicromips = false;
6740 IsNan2008 = isNaN2008Default();
6741 IsSingleFloat = false;
6742 FloatABI = HardFloat;
6744 HasFP64 = isFP64Default();
6746 for (const auto &Feature : Features) {
6747 if (Feature == "+single-float")
6748 IsSingleFloat = true;
6749 else if (Feature == "+soft-float")
6750 FloatABI = SoftFloat;
6751 else if (Feature == "+mips16")
6753 else if (Feature == "+micromips")
6755 else if (Feature == "+dsp")
6756 DspRev = std::max(DspRev, DSP1);
6757 else if (Feature == "+dspr2")
6758 DspRev = std::max(DspRev, DSP2);
6759 else if (Feature == "+msa")
6761 else if (Feature == "+fp64")
6763 else if (Feature == "-fp64")
6765 else if (Feature == "+nan2008")
6767 else if (Feature == "-nan2008")
6771 setDataLayoutString();
6776 int getEHDataRegisterNumber(unsigned RegNo) const override {
6777 if (RegNo == 0) return 4;
6778 if (RegNo == 1) return 5;
6782 bool isCLZForZeroUndef() const override { return false; }
6785 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
6786 #define BUILTIN(ID, TYPE, ATTRS) \
6787 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6788 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6789 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6790 #include "clang/Basic/BuiltinsMips.def"
6793 class Mips32TargetInfoBase : public MipsTargetInfoBase {
6795 Mips32TargetInfoBase(const llvm::Triple &Triple)
6796 : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
6797 SizeType = UnsignedInt;
6798 PtrDiffType = SignedInt;
6799 Int64Type = SignedLongLong;
6800 IntMaxType = Int64Type;
6801 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
6803 bool setABI(const std::string &Name) override {
6804 if (Name == "o32" || Name == "eabi") {
6810 void getTargetDefines(const LangOptions &Opts,
6811 MacroBuilder &Builder) const override {
6812 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6814 Builder.defineMacro("__mips", "32");
6815 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
6817 const std::string& CPUStr = getCPU();
6818 if (CPUStr == "mips32")
6819 Builder.defineMacro("__mips_isa_rev", "1");
6820 else if (CPUStr == "mips32r2")
6821 Builder.defineMacro("__mips_isa_rev", "2");
6822 else if (CPUStr == "mips32r3")
6823 Builder.defineMacro("__mips_isa_rev", "3");
6824 else if (CPUStr == "mips32r5")
6825 Builder.defineMacro("__mips_isa_rev", "5");
6826 else if (CPUStr == "mips32r6")
6827 Builder.defineMacro("__mips_isa_rev", "6");
6830 Builder.defineMacro("__mips_o32");
6831 Builder.defineMacro("_ABIO32", "1");
6832 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
6834 else if (ABI == "eabi")
6835 Builder.defineMacro("__mips_eabi");
6837 llvm_unreachable("Invalid ABI for Mips32.");
6839 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6840 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6850 { { "t2" }, "$10" },
6851 { { "t3" }, "$11" },
6852 { { "t4" }, "$12" },
6853 { { "t5" }, "$13" },
6854 { { "t6" }, "$14" },
6855 { { "t7" }, "$15" },
6856 { { "s0" }, "$16" },
6857 { { "s1" }, "$17" },
6858 { { "s2" }, "$18" },
6859 { { "s3" }, "$19" },
6860 { { "s4" }, "$20" },
6861 { { "s5" }, "$21" },
6862 { { "s6" }, "$22" },
6863 { { "s7" }, "$23" },
6864 { { "t8" }, "$24" },
6865 { { "t9" }, "$25" },
6866 { { "k0" }, "$26" },
6867 { { "k1" }, "$27" },
6868 { { "gp" }, "$28" },
6869 { { "sp","$sp" }, "$29" },
6870 { { "fp","$fp" }, "$30" },
6873 return llvm::makeArrayRef(GCCRegAliases);
6877 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
6878 void setDataLayoutString() override {
6879 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6883 Mips32EBTargetInfo(const llvm::Triple &Triple)
6884 : Mips32TargetInfoBase(Triple) {
6886 void getTargetDefines(const LangOptions &Opts,
6887 MacroBuilder &Builder) const override {
6888 DefineStd(Builder, "MIPSEB", Opts);
6889 Builder.defineMacro("_MIPSEB");
6890 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6894 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
6895 void setDataLayoutString() override {
6896 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6900 Mips32ELTargetInfo(const llvm::Triple &Triple)
6901 : Mips32TargetInfoBase(Triple) {
6904 void getTargetDefines(const LangOptions &Opts,
6905 MacroBuilder &Builder) const override {
6906 DefineStd(Builder, "MIPSEL", Opts);
6907 Builder.defineMacro("_MIPSEL");
6908 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6912 class Mips64TargetInfoBase : public MipsTargetInfoBase {
6914 Mips64TargetInfoBase(const llvm::Triple &Triple)
6915 : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6916 LongDoubleWidth = LongDoubleAlign = 128;
6917 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6918 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6919 LongDoubleWidth = LongDoubleAlign = 64;
6920 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6923 SuitableAlign = 128;
6924 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6927 void setN64ABITypes() {
6928 LongWidth = LongAlign = 64;
6929 PointerWidth = PointerAlign = 64;
6930 SizeType = UnsignedLong;
6931 PtrDiffType = SignedLong;
6932 Int64Type = SignedLong;
6933 IntMaxType = Int64Type;
6936 void setN32ABITypes() {
6937 LongWidth = LongAlign = 32;
6938 PointerWidth = PointerAlign = 32;
6939 SizeType = UnsignedInt;
6940 PtrDiffType = SignedInt;
6941 Int64Type = SignedLongLong;
6942 IntMaxType = Int64Type;
6945 bool setABI(const std::string &Name) override {
6946 if (Name == "n32") {
6951 if (Name == "n64") {
6959 void getTargetDefines(const LangOptions &Opts,
6960 MacroBuilder &Builder) const override {
6961 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6963 Builder.defineMacro("__mips", "64");
6964 Builder.defineMacro("__mips64");
6965 Builder.defineMacro("__mips64__");
6966 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6968 const std::string& CPUStr = getCPU();
6969 if (CPUStr == "mips64")
6970 Builder.defineMacro("__mips_isa_rev", "1");
6971 else if (CPUStr == "mips64r2")
6972 Builder.defineMacro("__mips_isa_rev", "2");
6973 else if (CPUStr == "mips64r3")
6974 Builder.defineMacro("__mips_isa_rev", "3");
6975 else if (CPUStr == "mips64r5")
6976 Builder.defineMacro("__mips_isa_rev", "5");
6977 else if (CPUStr == "mips64r6")
6978 Builder.defineMacro("__mips_isa_rev", "6");
6981 Builder.defineMacro("__mips_n32");
6982 Builder.defineMacro("_ABIN32", "2");
6983 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6985 else if (ABI == "n64") {
6986 Builder.defineMacro("__mips_n64");
6987 Builder.defineMacro("_ABI64", "3");
6988 Builder.defineMacro("_MIPS_SIM", "_ABI64");
6991 llvm_unreachable("Invalid ABI for Mips64.");
6993 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
6995 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6996 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
7006 { { "a6" }, "$10" },
7007 { { "a7" }, "$11" },
7008 { { "t0" }, "$12" },
7009 { { "t1" }, "$13" },
7010 { { "t2" }, "$14" },
7011 { { "t3" }, "$15" },
7012 { { "s0" }, "$16" },
7013 { { "s1" }, "$17" },
7014 { { "s2" }, "$18" },
7015 { { "s3" }, "$19" },
7016 { { "s4" }, "$20" },
7017 { { "s5" }, "$21" },
7018 { { "s6" }, "$22" },
7019 { { "s7" }, "$23" },
7020 { { "t8" }, "$24" },
7021 { { "t9" }, "$25" },
7022 { { "k0" }, "$26" },
7023 { { "k1" }, "$27" },
7024 { { "gp" }, "$28" },
7025 { { "sp","$sp" }, "$29" },
7026 { { "fp","$fp" }, "$30" },
7029 return llvm::makeArrayRef(GCCRegAliases);
7032 bool hasInt128Type() const override { return true; }
7035 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
7036 void setDataLayoutString() override {
7038 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7040 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7045 Mips64EBTargetInfo(const llvm::Triple &Triple)
7046 : Mips64TargetInfoBase(Triple) {}
7047 void getTargetDefines(const LangOptions &Opts,
7048 MacroBuilder &Builder) const override {
7049 DefineStd(Builder, "MIPSEB", Opts);
7050 Builder.defineMacro("_MIPSEB");
7051 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
7055 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
7056 void setDataLayoutString() override {
7058 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7060 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7063 Mips64ELTargetInfo(const llvm::Triple &Triple)
7064 : Mips64TargetInfoBase(Triple) {
7065 // Default ABI is n64.
7068 void getTargetDefines(const LangOptions &Opts,
7069 MacroBuilder &Builder) const override {
7070 DefineStd(Builder, "MIPSEL", Opts);
7071 Builder.defineMacro("_MIPSEL");
7072 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
7076 class PNaClTargetInfo : public TargetInfo {
7078 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
7080 this->UserLabelPrefix = "";
7081 this->LongAlign = 32;
7082 this->LongWidth = 32;
7083 this->PointerAlign = 32;
7084 this->PointerWidth = 32;
7085 this->IntMaxType = TargetInfo::SignedLongLong;
7086 this->Int64Type = TargetInfo::SignedLongLong;
7087 this->DoubleAlign = 64;
7088 this->LongDoubleWidth = 64;
7089 this->LongDoubleAlign = 64;
7090 this->SizeType = TargetInfo::UnsignedInt;
7091 this->PtrDiffType = TargetInfo::SignedInt;
7092 this->IntPtrType = TargetInfo::SignedInt;
7093 this->RegParmMax = 0; // Disallow regparm
7096 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
7097 Builder.defineMacro("__le32__");
7098 Builder.defineMacro("__pnacl__");
7100 void getTargetDefines(const LangOptions &Opts,
7101 MacroBuilder &Builder) const override {
7102 getArchDefines(Opts, Builder);
7104 bool hasFeature(StringRef Feature) const override {
7105 return Feature == "pnacl";
7107 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7108 BuiltinVaListKind getBuiltinVaListKind() const override {
7109 return TargetInfo::PNaClABIBuiltinVaList;
7111 ArrayRef<const char *> getGCCRegNames() const override;
7112 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
7113 bool validateAsmConstraint(const char *&Name,
7114 TargetInfo::ConstraintInfo &Info) const override {
7118 const char *getClobbers() const override {
7123 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const {
7127 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const {
7131 // We attempt to use PNaCl (le32) frontend and Mips32EL backend.
7132 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo {
7134 NaClMips32ELTargetInfo(const llvm::Triple &Triple) :
7135 Mips32ELTargetInfo(Triple) {
7138 BuiltinVaListKind getBuiltinVaListKind() const override {
7139 return TargetInfo::PNaClABIBuiltinVaList;
7143 class Le64TargetInfo : public TargetInfo {
7144 static const Builtin::Info BuiltinInfo[];
7147 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
7149 NoAsmVariants = true;
7150 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7151 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7152 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
7155 void getTargetDefines(const LangOptions &Opts,
7156 MacroBuilder &Builder) const override {
7157 DefineStd(Builder, "unix", Opts);
7158 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
7159 Builder.defineMacro("__ELF__");
7161 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7162 return llvm::makeArrayRef(BuiltinInfo,
7163 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin);
7165 BuiltinVaListKind getBuiltinVaListKind() const override {
7166 return TargetInfo::PNaClABIBuiltinVaList;
7168 const char *getClobbers() const override { return ""; }
7169 ArrayRef<const char *> getGCCRegNames() const override {
7172 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7175 bool validateAsmConstraint(const char *&Name,
7176 TargetInfo::ConstraintInfo &Info) const override {
7180 bool hasProtectedVisibility() const override { return false; }
7183 class WebAssemblyTargetInfo : public TargetInfo {
7184 static const Builtin::Info BuiltinInfo[];
7192 explicit WebAssemblyTargetInfo(const llvm::Triple &T)
7193 : TargetInfo(T), SIMDLevel(NoSIMD) {
7195 NoAsmVariants = true;
7196 SuitableAlign = 128;
7197 LargeArrayMinWidth = 128;
7198 LargeArrayAlign = 128;
7199 SimdDefaultAlign = 128;
7200 SigAtomicType = SignedLong;
7201 LongDoubleWidth = LongDoubleAlign = 128;
7202 LongDoubleFormat = &llvm::APFloat::IEEEquad;
7206 void getTargetDefines(const LangOptions &Opts,
7207 MacroBuilder &Builder) const override {
7208 defineCPUMacros(Builder, "wasm", /*Tuning=*/false);
7209 if (SIMDLevel >= SIMD128)
7210 Builder.defineMacro("__wasm_simd128__");
7215 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7217 const std::vector<std::string> &FeaturesVec) const override {
7218 if (CPU == "bleeding-edge")
7219 Features["simd128"] = true;
7220 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7222 bool hasFeature(StringRef Feature) const final {
7223 return llvm::StringSwitch<bool>(Feature)
7224 .Case("simd128", SIMDLevel >= SIMD128)
7227 bool handleTargetFeatures(std::vector<std::string> &Features,
7228 DiagnosticsEngine &Diags) final {
7229 for (const auto &Feature : Features) {
7230 if (Feature == "+simd128") {
7231 SIMDLevel = std::max(SIMDLevel, SIMD128);
7234 if (Feature == "-simd128") {
7235 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1));
7239 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature
7240 << "-target-feature";
7245 bool setCPU(const std::string &Name) final {
7246 return llvm::StringSwitch<bool>(Name)
7248 .Case("bleeding-edge", true)
7249 .Case("generic", true)
7252 ArrayRef<Builtin::Info> getTargetBuiltins() const final {
7253 return llvm::makeArrayRef(BuiltinInfo,
7254 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin);
7256 BuiltinVaListKind getBuiltinVaListKind() const final {
7257 return VoidPtrBuiltinVaList;
7259 ArrayRef<const char *> getGCCRegNames() const final {
7262 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final {
7266 validateAsmConstraint(const char *&Name,
7267 TargetInfo::ConstraintInfo &Info) const final {
7270 const char *getClobbers() const final { return ""; }
7271 bool isCLZForZeroUndef() const final { return false; }
7272 bool hasInt128Type() const final { return true; }
7273 IntType getIntTypeByWidth(unsigned BitWidth,
7274 bool IsSigned) const final {
7275 // WebAssembly prefers long long for explicitly 64-bit integers.
7276 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
7277 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
7279 IntType getLeastIntTypeByWidth(unsigned BitWidth,
7280 bool IsSigned) const final {
7281 // WebAssembly uses long long for int_least64_t and int_fast64_t.
7282 return BitWidth == 64
7283 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
7284 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
7288 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = {
7289 #define BUILTIN(ID, TYPE, ATTRS) \
7290 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7291 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
7292 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
7293 #include "clang/Basic/BuiltinsWebAssembly.def"
7296 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo {
7298 explicit WebAssembly32TargetInfo(const llvm::Triple &T)
7299 : WebAssemblyTargetInfo(T) {
7300 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
7301 DataLayoutString = "e-m:e-p:32:32-i64:64-n32:64-S128";
7305 void getTargetDefines(const LangOptions &Opts,
7306 MacroBuilder &Builder) const override {
7307 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
7308 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false);
7312 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo {
7314 explicit WebAssembly64TargetInfo(const llvm::Triple &T)
7315 : WebAssemblyTargetInfo(T) {
7316 LongAlign = LongWidth = 64;
7317 PointerAlign = PointerWidth = 64;
7318 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7319 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128";
7323 void getTargetDefines(const LangOptions &Opts,
7324 MacroBuilder &Builder) const override {
7325 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
7326 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false);
7330 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
7331 #define BUILTIN(ID, TYPE, ATTRS) \
7332 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7333 #include "clang/Basic/BuiltinsLe64.def"
7336 static const unsigned SPIRAddrSpaceMap[] = {
7339 2, // opencl_constant
7340 4, // opencl_generic
7345 class SPIRTargetInfo : public TargetInfo {
7347 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
7348 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
7349 "SPIR target must use unknown OS");
7350 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
7351 "SPIR target must use unknown environment type");
7353 TLSSupported = false;
7354 LongWidth = LongAlign = 64;
7355 AddrSpaceMap = &SPIRAddrSpaceMap;
7356 UseAddrSpaceMapMangling = true;
7357 // Define available target features
7358 // These must be defined in sorted order!
7359 NoAsmVariants = true;
7361 void getTargetDefines(const LangOptions &Opts,
7362 MacroBuilder &Builder) const override {
7363 DefineStd(Builder, "SPIR", Opts);
7365 bool hasFeature(StringRef Feature) const override {
7366 return Feature == "spir";
7369 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7370 const char *getClobbers() const override { return ""; }
7371 ArrayRef<const char *> getGCCRegNames() const override { return None; }
7372 bool validateAsmConstraint(const char *&Name,
7373 TargetInfo::ConstraintInfo &info) const override {
7376 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7379 BuiltinVaListKind getBuiltinVaListKind() const override {
7380 return TargetInfo::VoidPtrBuiltinVaList;
7383 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
7384 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK
7388 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
7389 return CC_SpirFunction;
7393 class SPIR32TargetInfo : public SPIRTargetInfo {
7395 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
7396 PointerWidth = PointerAlign = 32;
7397 SizeType = TargetInfo::UnsignedInt;
7398 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
7399 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
7400 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
7402 void getTargetDefines(const LangOptions &Opts,
7403 MacroBuilder &Builder) const override {
7404 DefineStd(Builder, "SPIR32", Opts);
7408 class SPIR64TargetInfo : public SPIRTargetInfo {
7410 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
7411 PointerWidth = PointerAlign = 64;
7412 SizeType = TargetInfo::UnsignedLong;
7413 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
7414 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
7415 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
7417 void getTargetDefines(const LangOptions &Opts,
7418 MacroBuilder &Builder) const override {
7419 DefineStd(Builder, "SPIR64", Opts);
7423 class XCoreTargetInfo : public TargetInfo {
7424 static const Builtin::Info BuiltinInfo[];
7426 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
7428 NoAsmVariants = true;
7431 DoubleAlign = LongDoubleAlign = 32;
7432 SizeType = UnsignedInt;
7433 PtrDiffType = SignedInt;
7434 IntPtrType = SignedInt;
7435 WCharType = UnsignedChar;
7436 WIntType = UnsignedInt;
7437 UseZeroLengthBitfieldAlignment = true;
7438 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
7439 "-f64:32-a:0:32-n32";
7441 void getTargetDefines(const LangOptions &Opts,
7442 MacroBuilder &Builder) const override {
7443 Builder.defineMacro("__XS1B__");
7445 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7446 return llvm::makeArrayRef(BuiltinInfo,
7447 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin);
7449 BuiltinVaListKind getBuiltinVaListKind() const override {
7450 return TargetInfo::VoidPtrBuiltinVaList;
7452 const char *getClobbers() const override {
7455 ArrayRef<const char *> getGCCRegNames() const override {
7456 static const char * const GCCRegNames[] = {
7457 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7458 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
7460 return llvm::makeArrayRef(GCCRegNames);
7462 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7465 bool validateAsmConstraint(const char *&Name,
7466 TargetInfo::ConstraintInfo &Info) const override {
7469 int getEHDataRegisterNumber(unsigned RegNo) const override {
7470 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
7471 return (RegNo < 2)? RegNo : -1;
7475 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
7476 #define BUILTIN(ID, TYPE, ATTRS) \
7477 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7478 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
7479 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
7480 #include "clang/Basic/BuiltinsXCore.def"
7483 // x86_32 Android target
7484 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
7486 AndroidX86_32TargetInfo(const llvm::Triple &Triple)
7487 : LinuxTargetInfo<X86_32TargetInfo>(Triple) {
7489 LongDoubleWidth = 64;
7490 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
7494 // x86_64 Android target
7495 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
7497 AndroidX86_64TargetInfo(const llvm::Triple &Triple)
7498 : LinuxTargetInfo<X86_64TargetInfo>(Triple) {
7499 LongDoubleFormat = &llvm::APFloat::IEEEquad;
7502 bool useFloat128ManglingForLongDouble() const override {
7506 } // end anonymous namespace
7508 //===----------------------------------------------------------------------===//
7510 //===----------------------------------------------------------------------===//
7512 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
7513 llvm::Triple::OSType os = Triple.getOS();
7515 switch (Triple.getArch()) {
7519 case llvm::Triple::xcore:
7520 return new XCoreTargetInfo(Triple);
7522 case llvm::Triple::hexagon:
7523 return new HexagonTargetInfo(Triple);
7525 case llvm::Triple::aarch64:
7526 if (Triple.isOSDarwin())
7527 return new DarwinAArch64TargetInfo(Triple);
7530 case llvm::Triple::CloudABI:
7531 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple);
7532 case llvm::Triple::FreeBSD:
7533 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
7534 case llvm::Triple::Linux:
7535 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
7536 case llvm::Triple::NetBSD:
7537 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
7539 return new AArch64leTargetInfo(Triple);
7542 case llvm::Triple::aarch64_be:
7544 case llvm::Triple::FreeBSD:
7545 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
7546 case llvm::Triple::Linux:
7547 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
7548 case llvm::Triple::NetBSD:
7549 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
7551 return new AArch64beTargetInfo(Triple);
7554 case llvm::Triple::arm:
7555 case llvm::Triple::thumb:
7556 if (Triple.isOSBinFormatMachO())
7557 return new DarwinARMTargetInfo(Triple);
7560 case llvm::Triple::Linux:
7561 return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
7562 case llvm::Triple::FreeBSD:
7563 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
7564 case llvm::Triple::NetBSD:
7565 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
7566 case llvm::Triple::OpenBSD:
7567 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
7568 case llvm::Triple::Bitrig:
7569 return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
7570 case llvm::Triple::RTEMS:
7571 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
7572 case llvm::Triple::NaCl:
7573 return new NaClTargetInfo<ARMleTargetInfo>(Triple);
7574 case llvm::Triple::Win32:
7575 switch (Triple.getEnvironment()) {
7576 case llvm::Triple::Cygnus:
7577 return new CygwinARMTargetInfo(Triple);
7578 case llvm::Triple::GNU:
7579 return new MinGWARMTargetInfo(Triple);
7580 case llvm::Triple::Itanium:
7581 return new ItaniumWindowsARMleTargetInfo(Triple);
7582 case llvm::Triple::MSVC:
7583 default: // Assume MSVC for unknown environments
7584 return new MicrosoftARMleTargetInfo(Triple);
7587 return new ARMleTargetInfo(Triple);
7590 case llvm::Triple::armeb:
7591 case llvm::Triple::thumbeb:
7592 if (Triple.isOSDarwin())
7593 return new DarwinARMTargetInfo(Triple);
7596 case llvm::Triple::Linux:
7597 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
7598 case llvm::Triple::FreeBSD:
7599 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
7600 case llvm::Triple::NetBSD:
7601 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
7602 case llvm::Triple::OpenBSD:
7603 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
7604 case llvm::Triple::Bitrig:
7605 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
7606 case llvm::Triple::RTEMS:
7607 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
7608 case llvm::Triple::NaCl:
7609 return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
7611 return new ARMbeTargetInfo(Triple);
7614 case llvm::Triple::bpfeb:
7615 case llvm::Triple::bpfel:
7616 return new BPFTargetInfo(Triple);
7618 case llvm::Triple::msp430:
7619 return new MSP430TargetInfo(Triple);
7621 case llvm::Triple::mips:
7623 case llvm::Triple::Linux:
7624 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
7625 case llvm::Triple::RTEMS:
7626 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
7627 case llvm::Triple::FreeBSD:
7628 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
7629 case llvm::Triple::NetBSD:
7630 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
7632 return new Mips32EBTargetInfo(Triple);
7635 case llvm::Triple::mipsel:
7637 case llvm::Triple::Linux:
7638 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
7639 case llvm::Triple::RTEMS:
7640 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
7641 case llvm::Triple::FreeBSD:
7642 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
7643 case llvm::Triple::NetBSD:
7644 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
7645 case llvm::Triple::NaCl:
7646 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple);
7648 return new Mips32ELTargetInfo(Triple);
7651 case llvm::Triple::mips64:
7653 case llvm::Triple::Linux:
7654 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
7655 case llvm::Triple::RTEMS:
7656 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
7657 case llvm::Triple::FreeBSD:
7658 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7659 case llvm::Triple::NetBSD:
7660 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7661 case llvm::Triple::OpenBSD:
7662 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7664 return new Mips64EBTargetInfo(Triple);
7667 case llvm::Triple::mips64el:
7669 case llvm::Triple::Linux:
7670 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
7671 case llvm::Triple::RTEMS:
7672 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
7673 case llvm::Triple::FreeBSD:
7674 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7675 case llvm::Triple::NetBSD:
7676 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7677 case llvm::Triple::OpenBSD:
7678 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7680 return new Mips64ELTargetInfo(Triple);
7683 case llvm::Triple::le32:
7685 case llvm::Triple::NaCl:
7686 return new NaClTargetInfo<PNaClTargetInfo>(Triple);
7691 case llvm::Triple::le64:
7692 return new Le64TargetInfo(Triple);
7694 case llvm::Triple::ppc:
7695 if (Triple.isOSDarwin())
7696 return new DarwinPPC32TargetInfo(Triple);
7698 case llvm::Triple::Linux:
7699 return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
7700 case llvm::Triple::FreeBSD:
7701 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
7702 case llvm::Triple::NetBSD:
7703 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
7704 case llvm::Triple::OpenBSD:
7705 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
7706 case llvm::Triple::RTEMS:
7707 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
7709 return new PPC32TargetInfo(Triple);
7712 case llvm::Triple::ppc64:
7713 if (Triple.isOSDarwin())
7714 return new DarwinPPC64TargetInfo(Triple);
7716 case llvm::Triple::Linux:
7717 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7718 case llvm::Triple::Lv2:
7719 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
7720 case llvm::Triple::FreeBSD:
7721 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
7722 case llvm::Triple::NetBSD:
7723 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7725 return new PPC64TargetInfo(Triple);
7728 case llvm::Triple::ppc64le:
7730 case llvm::Triple::Linux:
7731 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7732 case llvm::Triple::NetBSD:
7733 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7735 return new PPC64TargetInfo(Triple);
7738 case llvm::Triple::nvptx:
7739 return new NVPTX32TargetInfo(Triple);
7740 case llvm::Triple::nvptx64:
7741 return new NVPTX64TargetInfo(Triple);
7743 case llvm::Triple::amdgcn:
7744 case llvm::Triple::r600:
7745 return new AMDGPUTargetInfo(Triple);
7747 case llvm::Triple::sparc:
7749 case llvm::Triple::Linux:
7750 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
7751 case llvm::Triple::Solaris:
7752 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple);
7753 case llvm::Triple::NetBSD:
7754 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
7755 case llvm::Triple::OpenBSD:
7756 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
7757 case llvm::Triple::RTEMS:
7758 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
7760 return new SparcV8TargetInfo(Triple);
7763 // The 'sparcel' architecture copies all the above cases except for Solaris.
7764 case llvm::Triple::sparcel:
7766 case llvm::Triple::Linux:
7767 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple);
7768 case llvm::Triple::NetBSD:
7769 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7770 case llvm::Triple::OpenBSD:
7771 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7772 case llvm::Triple::RTEMS:
7773 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple);
7775 return new SparcV8elTargetInfo(Triple);
7778 case llvm::Triple::sparcv9:
7780 case llvm::Triple::Linux:
7781 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
7782 case llvm::Triple::Solaris:
7783 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
7784 case llvm::Triple::NetBSD:
7785 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
7786 case llvm::Triple::OpenBSD:
7787 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
7788 case llvm::Triple::FreeBSD:
7789 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
7791 return new SparcV9TargetInfo(Triple);
7794 case llvm::Triple::systemz:
7796 case llvm::Triple::Linux:
7797 return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
7799 return new SystemZTargetInfo(Triple);
7802 case llvm::Triple::tce:
7803 return new TCETargetInfo(Triple);
7805 case llvm::Triple::x86:
7806 if (Triple.isOSDarwin())
7807 return new DarwinI386TargetInfo(Triple);
7810 case llvm::Triple::CloudABI:
7811 return new CloudABITargetInfo<X86_32TargetInfo>(Triple);
7812 case llvm::Triple::Linux: {
7813 switch (Triple.getEnvironment()) {
7815 return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
7816 case llvm::Triple::Android:
7817 return new AndroidX86_32TargetInfo(Triple);
7820 case llvm::Triple::DragonFly:
7821 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
7822 case llvm::Triple::NetBSD:
7823 return new NetBSDI386TargetInfo(Triple);
7824 case llvm::Triple::OpenBSD:
7825 return new OpenBSDI386TargetInfo(Triple);
7826 case llvm::Triple::Bitrig:
7827 return new BitrigI386TargetInfo(Triple);
7828 case llvm::Triple::FreeBSD:
7829 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7830 case llvm::Triple::KFreeBSD:
7831 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7832 case llvm::Triple::Minix:
7833 return new MinixTargetInfo<X86_32TargetInfo>(Triple);
7834 case llvm::Triple::Solaris:
7835 return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
7836 case llvm::Triple::Win32: {
7837 switch (Triple.getEnvironment()) {
7838 case llvm::Triple::Cygnus:
7839 return new CygwinX86_32TargetInfo(Triple);
7840 case llvm::Triple::GNU:
7841 return new MinGWX86_32TargetInfo(Triple);
7842 case llvm::Triple::Itanium:
7843 case llvm::Triple::MSVC:
7844 default: // Assume MSVC for unknown environments
7845 return new MicrosoftX86_32TargetInfo(Triple);
7848 case llvm::Triple::Haiku:
7849 return new HaikuX86_32TargetInfo(Triple);
7850 case llvm::Triple::RTEMS:
7851 return new RTEMSX86_32TargetInfo(Triple);
7852 case llvm::Triple::NaCl:
7853 return new NaClTargetInfo<X86_32TargetInfo>(Triple);
7854 case llvm::Triple::ELFIAMCU:
7855 return new MCUX86_32TargetInfo(Triple);
7857 return new X86_32TargetInfo(Triple);
7860 case llvm::Triple::x86_64:
7861 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
7862 return new DarwinX86_64TargetInfo(Triple);
7865 case llvm::Triple::CloudABI:
7866 return new CloudABITargetInfo<X86_64TargetInfo>(Triple);
7867 case llvm::Triple::Linux: {
7868 switch (Triple.getEnvironment()) {
7870 return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
7871 case llvm::Triple::Android:
7872 return new AndroidX86_64TargetInfo(Triple);
7875 case llvm::Triple::DragonFly:
7876 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
7877 case llvm::Triple::NetBSD:
7878 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
7879 case llvm::Triple::OpenBSD:
7880 return new OpenBSDX86_64TargetInfo(Triple);
7881 case llvm::Triple::Bitrig:
7882 return new BitrigX86_64TargetInfo(Triple);
7883 case llvm::Triple::FreeBSD:
7884 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7885 case llvm::Triple::KFreeBSD:
7886 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7887 case llvm::Triple::Solaris:
7888 return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
7889 case llvm::Triple::Win32: {
7890 switch (Triple.getEnvironment()) {
7891 case llvm::Triple::Cygnus:
7892 return new CygwinX86_64TargetInfo(Triple);
7893 case llvm::Triple::GNU:
7894 return new MinGWX86_64TargetInfo(Triple);
7895 case llvm::Triple::MSVC:
7896 default: // Assume MSVC for unknown environments
7897 return new MicrosoftX86_64TargetInfo(Triple);
7900 case llvm::Triple::NaCl:
7901 return new NaClTargetInfo<X86_64TargetInfo>(Triple);
7902 case llvm::Triple::PS4:
7903 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple);
7905 return new X86_64TargetInfo(Triple);
7908 case llvm::Triple::spir: {
7909 if (Triple.getOS() != llvm::Triple::UnknownOS ||
7910 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7912 return new SPIR32TargetInfo(Triple);
7914 case llvm::Triple::spir64: {
7915 if (Triple.getOS() != llvm::Triple::UnknownOS ||
7916 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7918 return new SPIR64TargetInfo(Triple);
7920 case llvm::Triple::wasm32:
7921 if (!(Triple == llvm::Triple("wasm32-unknown-unknown")))
7923 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple);
7924 case llvm::Triple::wasm64:
7925 if (!(Triple == llvm::Triple("wasm64-unknown-unknown")))
7927 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple);
7931 /// CreateTargetInfo - Return the target info object for the specified target
7934 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
7935 const std::shared_ptr<TargetOptions> &Opts) {
7936 llvm::Triple Triple(Opts->Triple);
7938 // Construct the target
7939 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
7941 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
7944 Target->TargetOpts = Opts;
7946 // Set the target CPU if specified.
7947 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
7948 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
7952 // Set the target ABI if specified.
7953 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
7954 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
7958 // Set the fp math unit.
7959 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
7960 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
7964 // Compute the default target features, we need the target to handle this
7965 // because features may have dependencies on one another.
7966 llvm::StringMap<bool> Features;
7967 if (!Target->initFeatureMap(Features, Diags, Opts->CPU,
7968 Opts->FeaturesAsWritten))
7971 // Add the features to the compile options.
7972 Opts->Features.clear();
7973 for (const auto &F : Features)
7974 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str());
7976 if (!Target->handleTargetFeatures(Opts->Features, Diags))
7979 return Target.release();