1 //===--- Targets.cpp - Implement target feature support -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/Builtins.h"
16 #include "clang/Basic/Cuda.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetInfo.h"
22 #include "clang/Basic/TargetOptions.h"
23 #include "clang/Basic/Version.h"
24 #include "clang/Frontend/CodeGenOptions.h"
25 #include "llvm/ADT/APFloat.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/StringSwitch.h"
30 #include "llvm/ADT/Triple.h"
31 #include "llvm/MC/MCSectionMachO.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/TargetParser.h"
37 using namespace clang;
39 //===----------------------------------------------------------------------===//
40 // Common code shared among targets.
41 //===----------------------------------------------------------------------===//
43 /// DefineStd - Define a macro name and standard variants. For example if
44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
47 const LangOptions &Opts) {
48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
51 // in the user's namespace.
53 Builder.defineMacro(MacroName);
56 Builder.defineMacro("__" + MacroName);
59 Builder.defineMacro("__" + MacroName + "__");
62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
64 Builder.defineMacro("__" + CPUName);
65 Builder.defineMacro("__" + CPUName + "__");
67 Builder.defineMacro("__tune_" + CPUName + "__");
70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
71 const TargetOptions &Opts);
73 //===----------------------------------------------------------------------===//
74 // Defines specific to certain operating systems.
75 //===----------------------------------------------------------------------===//
78 template<typename TgtInfo>
79 class OSTargetInfo : public TgtInfo {
81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
82 MacroBuilder &Builder) const=0;
84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
85 : TgtInfo(Triple, Opts) {}
86 void getTargetDefines(const LangOptions &Opts,
87 MacroBuilder &Builder) const override {
88 TgtInfo::getTargetDefines(Opts, Builder);
89 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
95 template <typename Target>
96 class CloudABITargetInfo : public OSTargetInfo<Target> {
98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
99 MacroBuilder &Builder) const override {
100 Builder.defineMacro("__CloudABI__");
101 Builder.defineMacro("__ELF__");
103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
104 Builder.defineMacro("__STDC_ISO_10646__", "201206L");
105 Builder.defineMacro("__STDC_UTF_16__");
106 Builder.defineMacro("__STDC_UTF_32__");
110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
111 : OSTargetInfo<Target>(Triple, Opts) {}
115 template<typename Target>
116 class AnanasTargetInfo : public OSTargetInfo<Target> {
118 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
119 MacroBuilder &Builder) const override {
121 Builder.defineMacro("__Ananas__");
122 Builder.defineMacro("__ELF__");
125 AnanasTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
126 : OSTargetInfo<Target>(Triple, Opts) {}
129 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
130 const llvm::Triple &Triple,
131 StringRef &PlatformName,
132 VersionTuple &PlatformMinVersion) {
133 Builder.defineMacro("__APPLE_CC__", "6000");
134 Builder.defineMacro("__APPLE__");
135 Builder.defineMacro("__STDC_NO_THREADS__");
136 Builder.defineMacro("OBJC_NEW_PROPERTIES");
137 // AddressSanitizer doesn't play well with source fortification, which is on
138 // by default on Darwin.
139 if (Opts.Sanitize.has(SanitizerKind::Address))
140 Builder.defineMacro("_FORTIFY_SOURCE", "0");
142 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode.
144 // __weak is always defined, for use in blocks and with objc pointers.
145 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
146 Builder.defineMacro("__strong", "");
147 Builder.defineMacro("__unsafe_unretained", "");
151 Builder.defineMacro("__STATIC__");
153 Builder.defineMacro("__DYNAMIC__");
155 if (Opts.POSIXThreads)
156 Builder.defineMacro("_REENTRANT");
158 // Get the platform type and version number from the triple.
159 unsigned Maj, Min, Rev;
160 if (Triple.isMacOSX()) {
161 Triple.getMacOSXVersion(Maj, Min, Rev);
162 PlatformName = "macos";
164 Triple.getOSVersion(Maj, Min, Rev);
165 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
168 // If -target arch-pc-win32-macho option specified, we're
169 // generating code for Win32 ABI. No need to emit
170 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
171 if (PlatformName == "win32") {
172 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
176 // Set the appropriate OS version define.
177 if (Triple.isiOS()) {
178 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
182 Str[1] = '0' + (Min / 10);
183 Str[2] = '0' + (Min % 10);
184 Str[3] = '0' + (Rev / 10);
185 Str[4] = '0' + (Rev % 10);
188 // Handle versions >= 10.
189 Str[0] = '0' + (Maj / 10);
190 Str[1] = '0' + (Maj % 10);
191 Str[2] = '0' + (Min / 10);
192 Str[3] = '0' + (Min % 10);
193 Str[4] = '0' + (Rev / 10);
194 Str[5] = '0' + (Rev % 10);
198 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str);
200 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
203 } else if (Triple.isWatchOS()) {
204 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
207 Str[1] = '0' + (Min / 10);
208 Str[2] = '0' + (Min % 10);
209 Str[3] = '0' + (Rev / 10);
210 Str[4] = '0' + (Rev % 10);
212 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str);
213 } else if (Triple.isMacOSX()) {
214 // Note that the Driver allows versions which aren't representable in the
215 // define (because we only get a single digit for the minor and micro
216 // revision numbers). So, we limit them to the maximum representable
218 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
220 if (Maj < 10 || (Maj == 10 && Min < 10)) {
221 Str[0] = '0' + (Maj / 10);
222 Str[1] = '0' + (Maj % 10);
223 Str[2] = '0' + std::min(Min, 9U);
224 Str[3] = '0' + std::min(Rev, 9U);
227 // Handle versions > 10.9.
228 Str[0] = '0' + (Maj / 10);
229 Str[1] = '0' + (Maj % 10);
230 Str[2] = '0' + (Min / 10);
231 Str[3] = '0' + (Min % 10);
232 Str[4] = '0' + (Rev / 10);
233 Str[5] = '0' + (Rev % 10);
236 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
239 // Tell users about the kernel if there is one.
240 if (Triple.isOSDarwin())
241 Builder.defineMacro("__MACH__");
243 // The Watch ABI uses Dwarf EH.
244 if(Triple.isWatchABI())
245 Builder.defineMacro("__ARM_DWARF_EH__");
247 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
250 template<typename Target>
251 class DarwinTargetInfo : public OSTargetInfo<Target> {
253 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
254 MacroBuilder &Builder) const override {
255 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
256 this->PlatformMinVersion);
260 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
261 : OSTargetInfo<Target>(Triple, Opts) {
262 // By default, no TLS, and we whitelist permitted architecture/OS
264 this->TLSSupported = false;
266 if (Triple.isMacOSX())
267 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7);
268 else if (Triple.isiOS()) {
269 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards.
270 if (Triple.getArch() == llvm::Triple::x86_64 ||
271 Triple.getArch() == llvm::Triple::aarch64)
272 this->TLSSupported = !Triple.isOSVersionLT(8);
273 else if (Triple.getArch() == llvm::Triple::x86 ||
274 Triple.getArch() == llvm::Triple::arm ||
275 Triple.getArch() == llvm::Triple::thumb)
276 this->TLSSupported = !Triple.isOSVersionLT(9);
277 } else if (Triple.isWatchOS())
278 this->TLSSupported = !Triple.isOSVersionLT(2);
280 this->MCountName = "\01mcount";
283 std::string isValidSectionSpecifier(StringRef SR) const override {
284 // Let MCSectionMachO validate this.
285 StringRef Segment, Section;
286 unsigned TAA, StubSize;
288 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
289 TAA, HasTAA, StubSize);
292 const char *getStaticInitSectionSpecifier() const override {
293 // FIXME: We should return 0 when building kexts.
294 return "__TEXT,__StaticInit,regular,pure_instructions";
297 /// Darwin does not support protected visibility. Darwin's "default"
298 /// is very similar to ELF's "protected"; Darwin requires a "weak"
299 /// attribute on declarations that can be dynamically replaced.
300 bool hasProtectedVisibility() const override {
304 unsigned getExnObjectAlignment() const override {
305 // The alignment of an exception object is 8-bytes for darwin since
306 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned))
307 // and therefore doesn't guarantee 16-byte alignment.
313 // DragonFlyBSD Target
314 template<typename Target>
315 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
317 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
318 MacroBuilder &Builder) const override {
319 // DragonFly defines; list based off of gcc output
320 Builder.defineMacro("__DragonFly__");
321 Builder.defineMacro("__DragonFly_cc_version", "100001");
322 Builder.defineMacro("__ELF__");
323 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
324 Builder.defineMacro("__tune_i386__");
325 DefineStd(Builder, "unix", Opts);
328 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
329 : OSTargetInfo<Target>(Triple, Opts) {
330 switch (Triple.getArch()) {
332 case llvm::Triple::x86:
333 case llvm::Triple::x86_64:
334 this->MCountName = ".mcount";
340 #ifndef FREEBSD_CC_VERSION
341 #define FREEBSD_CC_VERSION 0U
345 template<typename Target>
346 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
348 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
349 MacroBuilder &Builder) const override {
350 // FreeBSD defines; list based off of gcc output
352 unsigned Release = Triple.getOSMajorVersion();
355 unsigned CCVersion = FREEBSD_CC_VERSION;
357 CCVersion = Release * 100000U + 1U;
359 Builder.defineMacro("__FreeBSD__", Twine(Release));
360 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion));
361 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
362 DefineStd(Builder, "unix", Opts);
363 Builder.defineMacro("__ELF__");
365 // On FreeBSD, wchar_t contains the number of the code point as
366 // used by the character set of the locale. These character sets are
367 // not necessarily a superset of ASCII.
369 // FIXME: This is wrong; the macro refers to the numerical values
370 // of wchar_t *literals*, which are not locale-dependent. However,
371 // FreeBSD systems apparently depend on us getting this wrong, and
372 // setting this to 1 is conforming even if all the basic source
373 // character literals have the same encoding as char and wchar_t.
374 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
377 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
378 : OSTargetInfo<Target>(Triple, Opts) {
379 switch (Triple.getArch()) {
381 case llvm::Triple::x86:
382 case llvm::Triple::x86_64:
383 this->MCountName = ".mcount";
385 case llvm::Triple::mips:
386 case llvm::Triple::mipsel:
387 case llvm::Triple::ppc:
388 case llvm::Triple::ppc64:
389 case llvm::Triple::ppc64le:
390 this->MCountName = "_mcount";
392 case llvm::Triple::arm:
393 this->MCountName = "__mcount";
399 // GNU/kFreeBSD Target
400 template<typename Target>
401 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
403 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
404 MacroBuilder &Builder) const override {
405 // GNU/kFreeBSD defines; list based off of gcc output
407 DefineStd(Builder, "unix", Opts);
408 Builder.defineMacro("__FreeBSD_kernel__");
409 Builder.defineMacro("__GLIBC__");
410 Builder.defineMacro("__ELF__");
411 if (Opts.POSIXThreads)
412 Builder.defineMacro("_REENTRANT");
414 Builder.defineMacro("_GNU_SOURCE");
417 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
418 : OSTargetInfo<Target>(Triple, Opts) {}
422 template<typename Target>
423 class HaikuTargetInfo : public OSTargetInfo<Target> {
425 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
426 MacroBuilder &Builder) const override {
427 // Haiku defines; list based off of gcc output
428 Builder.defineMacro("__HAIKU__");
429 Builder.defineMacro("__ELF__");
430 DefineStd(Builder, "unix", Opts);
433 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
434 : OSTargetInfo<Target>(Triple, Opts) {
435 this->SizeType = TargetInfo::UnsignedLong;
436 this->IntPtrType = TargetInfo::SignedLong;
437 this->PtrDiffType = TargetInfo::SignedLong;
438 this->ProcessIDType = TargetInfo::SignedLong;
439 this->TLSSupported = false;
445 template<typename Target>
446 class MinixTargetInfo : public OSTargetInfo<Target> {
448 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
449 MacroBuilder &Builder) const override {
452 Builder.defineMacro("__minix", "3");
453 Builder.defineMacro("_EM_WSIZE", "4");
454 Builder.defineMacro("_EM_PSIZE", "4");
455 Builder.defineMacro("_EM_SSIZE", "2");
456 Builder.defineMacro("_EM_LSIZE", "4");
457 Builder.defineMacro("_EM_FSIZE", "4");
458 Builder.defineMacro("_EM_DSIZE", "8");
459 Builder.defineMacro("__ELF__");
460 DefineStd(Builder, "unix", Opts);
463 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
464 : OSTargetInfo<Target>(Triple, Opts) {}
468 template<typename Target>
469 class LinuxTargetInfo : public OSTargetInfo<Target> {
471 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
472 MacroBuilder &Builder) const override {
473 // Linux defines; list based off of gcc output
474 DefineStd(Builder, "unix", Opts);
475 DefineStd(Builder, "linux", Opts);
476 Builder.defineMacro("__gnu_linux__");
477 Builder.defineMacro("__ELF__");
478 if (Triple.isAndroid()) {
479 Builder.defineMacro("__ANDROID__", "1");
480 unsigned Maj, Min, Rev;
481 Triple.getEnvironmentVersion(Maj, Min, Rev);
482 this->PlatformName = "android";
483 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
485 Builder.defineMacro("__ANDROID_API__", Twine(Maj));
487 if (Opts.POSIXThreads)
488 Builder.defineMacro("_REENTRANT");
490 Builder.defineMacro("_GNU_SOURCE");
491 if (this->HasFloat128)
492 Builder.defineMacro("__FLOAT128__");
495 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
496 : OSTargetInfo<Target>(Triple, Opts) {
497 this->WIntType = TargetInfo::UnsignedInt;
499 switch (Triple.getArch()) {
502 case llvm::Triple::mips:
503 case llvm::Triple::mipsel:
504 case llvm::Triple::mips64:
505 case llvm::Triple::mips64el:
506 case llvm::Triple::ppc:
507 case llvm::Triple::ppc64:
508 case llvm::Triple::ppc64le:
509 this->MCountName = "_mcount";
511 case llvm::Triple::x86:
512 case llvm::Triple::x86_64:
513 case llvm::Triple::systemz:
514 this->HasFloat128 = true;
519 const char *getStaticInitSectionSpecifier() const override {
520 return ".text.startup";
525 template<typename Target>
526 class NetBSDTargetInfo : public OSTargetInfo<Target> {
528 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
529 MacroBuilder &Builder) const override {
530 // NetBSD defines; list based off of gcc output
531 Builder.defineMacro("__NetBSD__");
532 Builder.defineMacro("__unix__");
533 Builder.defineMacro("__ELF__");
534 if (Opts.POSIXThreads)
535 Builder.defineMacro("_REENTRANT");
537 switch (Triple.getArch()) {
540 case llvm::Triple::arm:
541 case llvm::Triple::armeb:
542 case llvm::Triple::thumb:
543 case llvm::Triple::thumbeb:
544 Builder.defineMacro("__ARM_DWARF_EH__");
549 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
550 : OSTargetInfo<Target>(Triple, Opts) {
551 this->MCountName = "_mcount";
556 template<typename Target>
557 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
559 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
560 MacroBuilder &Builder) const override {
561 // OpenBSD defines; list based off of gcc output
563 Builder.defineMacro("__OpenBSD__");
564 DefineStd(Builder, "unix", Opts);
565 Builder.defineMacro("__ELF__");
566 if (Opts.POSIXThreads)
567 Builder.defineMacro("_REENTRANT");
568 if (this->HasFloat128)
569 Builder.defineMacro("__FLOAT128__");
572 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
573 : OSTargetInfo<Target>(Triple, Opts) {
574 this->TLSSupported = false;
576 switch (Triple.getArch()) {
577 case llvm::Triple::x86:
578 case llvm::Triple::x86_64:
579 this->HasFloat128 = true;
582 this->MCountName = "__mcount";
584 case llvm::Triple::mips64:
585 case llvm::Triple::mips64el:
586 case llvm::Triple::ppc:
587 case llvm::Triple::sparcv9:
588 this->MCountName = "_mcount";
595 template<typename Target>
596 class BitrigTargetInfo : public OSTargetInfo<Target> {
598 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
599 MacroBuilder &Builder) const override {
600 // Bitrig defines; list based off of gcc output
602 Builder.defineMacro("__Bitrig__");
603 DefineStd(Builder, "unix", Opts);
604 Builder.defineMacro("__ELF__");
605 if (Opts.POSIXThreads)
606 Builder.defineMacro("_REENTRANT");
608 switch (Triple.getArch()) {
611 case llvm::Triple::arm:
612 case llvm::Triple::armeb:
613 case llvm::Triple::thumb:
614 case llvm::Triple::thumbeb:
615 Builder.defineMacro("__ARM_DWARF_EH__");
620 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
621 : OSTargetInfo<Target>(Triple, Opts) {
622 this->MCountName = "__mcount";
627 template<typename Target>
628 class PSPTargetInfo : public OSTargetInfo<Target> {
630 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
631 MacroBuilder &Builder) const override {
632 // PSP defines; list based on the output of the pspdev gcc toolchain.
633 Builder.defineMacro("PSP");
634 Builder.defineMacro("_PSP");
635 Builder.defineMacro("__psp__");
636 Builder.defineMacro("__ELF__");
639 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {}
643 template<typename Target>
644 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
646 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
647 MacroBuilder &Builder) const override {
649 Builder.defineMacro("__PPC__");
650 Builder.defineMacro("__PPU__");
651 Builder.defineMacro("__CELLOS_LV2__");
652 Builder.defineMacro("__ELF__");
653 Builder.defineMacro("__LP32__");
654 Builder.defineMacro("_ARCH_PPC64");
655 Builder.defineMacro("__powerpc64__");
658 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
659 : OSTargetInfo<Target>(Triple, Opts) {
660 this->LongWidth = this->LongAlign = 32;
661 this->PointerWidth = this->PointerAlign = 32;
662 this->IntMaxType = TargetInfo::SignedLongLong;
663 this->Int64Type = TargetInfo::SignedLongLong;
664 this->SizeType = TargetInfo::UnsignedInt;
665 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64");
669 template <typename Target>
670 class PS4OSTargetInfo : public OSTargetInfo<Target> {
672 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
673 MacroBuilder &Builder) const override {
674 Builder.defineMacro("__FreeBSD__", "9");
675 Builder.defineMacro("__FreeBSD_cc_version", "900001");
676 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
677 DefineStd(Builder, "unix", Opts);
678 Builder.defineMacro("__ELF__");
679 Builder.defineMacro("__ORBIS__");
682 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
683 : OSTargetInfo<Target>(Triple, Opts) {
684 this->WCharType = this->UnsignedShort;
686 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits).
687 this->MaxTLSAlign = 256;
689 // On PS4, do not honor explicit bit field alignment,
690 // as in "__attribute__((aligned(2))) int b : 1;".
691 this->UseExplicitBitFieldAlignment = false;
693 switch (Triple.getArch()) {
695 case llvm::Triple::x86_64:
696 this->MCountName = ".mcount";
703 template<typename Target>
704 class SolarisTargetInfo : public OSTargetInfo<Target> {
706 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
707 MacroBuilder &Builder) const override {
708 DefineStd(Builder, "sun", Opts);
709 DefineStd(Builder, "unix", Opts);
710 Builder.defineMacro("__ELF__");
711 Builder.defineMacro("__svr4__");
712 Builder.defineMacro("__SVR4");
713 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
714 // newer, but to 500 for everything else. feature_test.h has a check to
715 // ensure that you are not using C99 with an old version of X/Open or C89
716 // with a new version.
718 Builder.defineMacro("_XOPEN_SOURCE", "600");
720 Builder.defineMacro("_XOPEN_SOURCE", "500");
722 Builder.defineMacro("__C99FEATURES__");
723 Builder.defineMacro("_LARGEFILE_SOURCE");
724 Builder.defineMacro("_LARGEFILE64_SOURCE");
725 Builder.defineMacro("__EXTENSIONS__");
726 Builder.defineMacro("_REENTRANT");
729 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
730 : OSTargetInfo<Target>(Triple, Opts) {
731 this->WCharType = this->SignedInt;
732 // FIXME: WIntType should be SignedLong
737 template<typename Target>
738 class WindowsTargetInfo : public OSTargetInfo<Target> {
740 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
741 MacroBuilder &Builder) const override {
742 Builder.defineMacro("_WIN32");
744 void getVisualStudioDefines(const LangOptions &Opts,
745 MacroBuilder &Builder) const {
746 if (Opts.CPlusPlus) {
748 Builder.defineMacro("_CPPRTTI");
750 if (Opts.CXXExceptions)
751 Builder.defineMacro("_CPPUNWIND");
755 Builder.defineMacro("__BOOL_DEFINED");
757 if (!Opts.CharIsSigned)
758 Builder.defineMacro("_CHAR_UNSIGNED");
760 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
761 // but it works for now.
762 if (Opts.POSIXThreads)
763 Builder.defineMacro("_MT");
765 if (Opts.MSCompatibilityVersion) {
766 Builder.defineMacro("_MSC_VER",
767 Twine(Opts.MSCompatibilityVersion / 100000));
768 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
769 // FIXME We cannot encode the revision information into 32-bits
770 Builder.defineMacro("_MSC_BUILD", Twine(1));
772 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
773 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
775 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) {
776 if (Opts.CPlusPlus1z)
777 Builder.defineMacro("_MSVC_LANG", "201403L");
778 else if (Opts.CPlusPlus14)
779 Builder.defineMacro("_MSVC_LANG", "201402L");
783 if (Opts.MicrosoftExt) {
784 Builder.defineMacro("_MSC_EXTENSIONS");
786 if (Opts.CPlusPlus11) {
787 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
788 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
789 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
793 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
797 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
798 : OSTargetInfo<Target>(Triple, Opts) {}
801 template <typename Target>
802 class NaClTargetInfo : public OSTargetInfo<Target> {
804 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
805 MacroBuilder &Builder) const override {
806 if (Opts.POSIXThreads)
807 Builder.defineMacro("_REENTRANT");
809 Builder.defineMacro("_GNU_SOURCE");
811 DefineStd(Builder, "unix", Opts);
812 Builder.defineMacro("__ELF__");
813 Builder.defineMacro("__native_client__");
817 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
818 : OSTargetInfo<Target>(Triple, Opts) {
819 this->LongAlign = 32;
820 this->LongWidth = 32;
821 this->PointerAlign = 32;
822 this->PointerWidth = 32;
823 this->IntMaxType = TargetInfo::SignedLongLong;
824 this->Int64Type = TargetInfo::SignedLongLong;
825 this->DoubleAlign = 64;
826 this->LongDoubleWidth = 64;
827 this->LongDoubleAlign = 64;
828 this->LongLongWidth = 64;
829 this->LongLongAlign = 64;
830 this->SizeType = TargetInfo::UnsignedInt;
831 this->PtrDiffType = TargetInfo::SignedInt;
832 this->IntPtrType = TargetInfo::SignedInt;
833 // RegParmMax is inherited from the underlying architecture.
834 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble();
835 if (Triple.getArch() == llvm::Triple::arm) {
836 // Handled in ARM's setABI().
837 } else if (Triple.getArch() == llvm::Triple::x86) {
838 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128");
839 } else if (Triple.getArch() == llvm::Triple::x86_64) {
840 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128");
841 } else if (Triple.getArch() == llvm::Triple::mipsel) {
842 // Handled on mips' setDataLayout.
844 assert(Triple.getArch() == llvm::Triple::le32);
845 this->resetDataLayout("e-p:32:32-i64:64");
851 template<typename Target>
852 class FuchsiaTargetInfo : public OSTargetInfo<Target> {
854 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
855 MacroBuilder &Builder) const override {
856 Builder.defineMacro("__Fuchsia__");
857 Builder.defineMacro("__ELF__");
858 if (Opts.POSIXThreads)
859 Builder.defineMacro("_REENTRANT");
860 // Required by the libc++ locale support.
862 Builder.defineMacro("_GNU_SOURCE");
865 FuchsiaTargetInfo(const llvm::Triple &Triple,
866 const TargetOptions &Opts)
867 : OSTargetInfo<Target>(Triple, Opts) {
868 this->MCountName = "__mcount";
872 // WebAssembly target
873 template <typename Target>
874 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> {
875 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
876 MacroBuilder &Builder) const final {
877 // A common platform macro.
878 if (Opts.POSIXThreads)
879 Builder.defineMacro("_REENTRANT");
880 // Follow g++ convention and predefine _GNU_SOURCE for C++.
882 Builder.defineMacro("_GNU_SOURCE");
885 // As an optimization, group static init code together in a section.
886 const char *getStaticInitSectionSpecifier() const final {
887 return ".text.__startup";
891 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple,
892 const TargetOptions &Opts)
893 : OSTargetInfo<Target>(Triple, Opts) {
894 this->MCountName = "__mcount";
895 this->TheCXXABI.set(TargetCXXABI::WebAssembly);
899 //===----------------------------------------------------------------------===//
900 // Specific target implementations.
901 //===----------------------------------------------------------------------===//
903 // PPC abstract base class
904 class PPCTargetInfo : public TargetInfo {
905 static const Builtin::Info BuiltinInfo[];
906 static const char * const GCCRegNames[];
907 static const TargetInfo::GCCRegAlias GCCRegAliases[];
910 // Target cpu features.
926 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
927 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false),
928 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
929 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) {
931 SimdDefaultAlign = 128;
932 LongDoubleWidth = LongDoubleAlign = 128;
933 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
936 /// \brief Flags for architecture specific defines.
939 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
940 ArchDefinePpcgr = 1 << 1,
941 ArchDefinePpcsq = 1 << 2,
942 ArchDefine440 = 1 << 3,
943 ArchDefine603 = 1 << 4,
944 ArchDefine604 = 1 << 5,
945 ArchDefinePwr4 = 1 << 6,
946 ArchDefinePwr5 = 1 << 7,
947 ArchDefinePwr5x = 1 << 8,
948 ArchDefinePwr6 = 1 << 9,
949 ArchDefinePwr6x = 1 << 10,
950 ArchDefinePwr7 = 1 << 11,
951 ArchDefinePwr8 = 1 << 12,
952 ArchDefinePwr9 = 1 << 13,
953 ArchDefineA2 = 1 << 14,
954 ArchDefineA2q = 1 << 15
957 // Set the language option for altivec based on our value.
958 void adjust(LangOptions &Opts) override {
961 TargetInfo::adjust(Opts);
964 // Note: GCC recognizes the following additional cpus:
965 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
966 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
968 bool setCPU(const std::string &Name) override {
969 bool CPUKnown = llvm::StringSwitch<bool>(Name)
970 .Case("generic", true)
992 .Case("e500mc", true)
994 .Case("power3", true)
996 .Case("power4", true)
998 .Case("power5", true)
1000 .Case("power5x", true)
1001 .Case("pwr5x", true)
1002 .Case("power6", true)
1004 .Case("power6x", true)
1005 .Case("pwr6x", true)
1006 .Case("power7", true)
1008 .Case("power8", true)
1010 .Case("power9", true)
1012 .Case("powerpc", true)
1014 .Case("powerpc64", true)
1015 .Case("ppc64", true)
1016 .Case("powerpc64le", true)
1017 .Case("ppc64le", true)
1027 StringRef getABI() const override { return ABI; }
1029 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1030 return llvm::makeArrayRef(BuiltinInfo,
1031 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin);
1034 bool isCLZForZeroUndef() const override { return false; }
1036 void getTargetDefines(const LangOptions &Opts,
1037 MacroBuilder &Builder) const override;
1040 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
1042 const std::vector<std::string> &FeaturesVec) const override;
1044 bool handleTargetFeatures(std::vector<std::string> &Features,
1045 DiagnosticsEngine &Diags) override;
1046 bool hasFeature(StringRef Feature) const override;
1047 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
1048 bool Enabled) const override;
1050 ArrayRef<const char *> getGCCRegNames() const override;
1051 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
1052 bool validateAsmConstraint(const char *&Name,
1053 TargetInfo::ConstraintInfo &Info) const override {
1055 default: return false;
1058 case 'b': // Base register
1059 case 'f': // Floating point register
1060 Info.setAllowsRegister();
1062 // FIXME: The following are added to allow parsing.
1063 // I just took a guess at what the actions should be.
1064 // Also, is more specific checking needed? I.e. specific registers?
1065 case 'd': // Floating point register (containing 64-bit value)
1066 case 'v': // Altivec vector register
1067 Info.setAllowsRegister();
1071 case 'd':// VSX vector register to hold vector double data
1072 case 'f':// VSX vector register to hold vector float data
1073 case 's':// VSX vector register to hold scalar float data
1074 case 'a':// Any VSX register
1075 case 'c':// An individual CR bit
1080 Info.setAllowsRegister();
1081 Name++; // Skip over 'w'.
1083 case 'h': // `MQ', `CTR', or `LINK' register
1084 case 'q': // `MQ' register
1085 case 'c': // `CTR' register
1086 case 'l': // `LINK' register
1087 case 'x': // `CR' register (condition register) number 0
1088 case 'y': // `CR' register (condition register)
1089 case 'z': // `XER[CA]' carry bit (part of the XER register)
1090 Info.setAllowsRegister();
1092 case 'I': // Signed 16-bit constant
1093 case 'J': // Unsigned 16-bit constant shifted left 16 bits
1094 // (use `L' instead for SImode constants)
1095 case 'K': // Unsigned 16-bit constant
1096 case 'L': // Signed 16-bit constant shifted left 16 bits
1097 case 'M': // Constant larger than 31
1098 case 'N': // Exact power of 2
1099 case 'P': // Constant whose negation is a signed 16-bit constant
1100 case 'G': // Floating point constant that can be loaded into a
1101 // register with one instruction per word
1102 case 'H': // Integer/Floating point constant that can be loaded
1103 // into a register using three instructions
1105 case 'm': // Memory operand. Note that on PowerPC targets, m can
1106 // include addresses that update the base register. It
1107 // is therefore only safe to use `m' in an asm statement
1108 // if that asm statement accesses the operand exactly once.
1109 // The asm statement must also use `%U<opno>' as a
1110 // placeholder for the "update" flag in the corresponding
1111 // load or store instruction. For example:
1112 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
1114 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
1115 // is not. Use es rather than m if you don't want the base
1116 // register to be updated.
1120 // es: A "stable" memory operand; that is, one which does not
1121 // include any automodification of the base register. Unlike
1122 // `m', this constraint can be used in asm statements that
1123 // might access the operand several times, or that might not
1124 // access it at all.
1125 Info.setAllowsMemory();
1126 Name++; // Skip over 'e'.
1128 case 'Q': // Memory operand that is an offset from a register (it is
1129 // usually better to use `m' or `es' in asm statements)
1130 case 'Z': // Memory operand that is an indexed or indirect from a
1131 // register (it is usually better to use `m' or `es' in
1133 Info.setAllowsMemory();
1134 Info.setAllowsRegister();
1136 case 'R': // AIX TOC entry
1137 case 'a': // Address operand that is an indexed or indirect from a
1138 // register (`p' is preferable for asm statements)
1139 case 'S': // Constant suitable as a 64-bit mask operand
1140 case 'T': // Constant suitable as a 32-bit mask operand
1141 case 'U': // System V Release 4 small data area reference
1142 case 't': // AND masks that can be performed by two rldic{l, r}
1144 case 'W': // Vector constant that does not require memory
1145 case 'j': // Vector constant that is all zeros.
1151 std::string convertConstraint(const char *&Constraint) const override {
1153 switch (*Constraint) {
1156 // Two-character constraint; add "^" hint for later parsing.
1157 R = std::string("^") + std::string(Constraint, 2);
1161 return TargetInfo::convertConstraint(Constraint);
1165 const char *getClobbers() const override {
1168 int getEHDataRegisterNumber(unsigned RegNo) const override {
1169 if (RegNo == 0) return 3;
1170 if (RegNo == 1) return 4;
1174 bool hasSjLjLowering() const override {
1178 bool useFloat128ManglingForLongDouble() const override {
1179 return LongDoubleWidth == 128 &&
1180 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() &&
1181 getTriple().isOSBinFormatELF();
1185 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
1186 #define BUILTIN(ID, TYPE, ATTRS) \
1187 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1188 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1189 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1190 #include "clang/Basic/BuiltinsPPC.def"
1193 /// handleTargetFeatures - Perform initialization based on the user
1194 /// configured set of features.
1195 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1196 DiagnosticsEngine &Diags) {
1197 for (const auto &Feature : Features) {
1198 if (Feature == "+altivec") {
1200 } else if (Feature == "+vsx") {
1202 } else if (Feature == "+bpermd") {
1204 } else if (Feature == "+extdiv") {
1206 } else if (Feature == "+power8-vector") {
1208 } else if (Feature == "+crypto") {
1210 } else if (Feature == "+direct-move") {
1211 HasDirectMove = true;
1212 } else if (Feature == "+qpx") {
1214 } else if (Feature == "+htm") {
1216 } else if (Feature == "+float128") {
1218 } else if (Feature == "+power9-vector") {
1221 // TODO: Finish this list and add an assert that we've handled them
1228 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1229 /// #defines that are not tied to a specific subtarget.
1230 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1231 MacroBuilder &Builder) const {
1232 // Target identification.
1233 Builder.defineMacro("__ppc__");
1234 Builder.defineMacro("__PPC__");
1235 Builder.defineMacro("_ARCH_PPC");
1236 Builder.defineMacro("__powerpc__");
1237 Builder.defineMacro("__POWERPC__");
1238 if (PointerWidth == 64) {
1239 Builder.defineMacro("_ARCH_PPC64");
1240 Builder.defineMacro("__powerpc64__");
1241 Builder.defineMacro("__ppc64__");
1242 Builder.defineMacro("__PPC64__");
1245 // Target properties.
1246 if (getTriple().getArch() == llvm::Triple::ppc64le) {
1247 Builder.defineMacro("_LITTLE_ENDIAN");
1249 if (getTriple().getOS() != llvm::Triple::NetBSD &&
1250 getTriple().getOS() != llvm::Triple::OpenBSD)
1251 Builder.defineMacro("_BIG_ENDIAN");
1255 if (ABI == "elfv1" || ABI == "elfv1-qpx")
1256 Builder.defineMacro("_CALL_ELF", "1");
1258 Builder.defineMacro("_CALL_ELF", "2");
1260 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but
1261 // our suppport post-dates this and it should work on all 64-bit ppc linux
1262 // platforms. It is guaranteed to work on all elfv2 platforms.
1263 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64)
1264 Builder.defineMacro("_CALL_LINUX", "1");
1266 // Subtarget options.
1267 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1268 Builder.defineMacro("__REGISTER_PREFIX__", "");
1270 // FIXME: Should be controlled by command line option.
1271 if (LongDoubleWidth == 128) {
1272 Builder.defineMacro("__LONG_DOUBLE_128__");
1273 Builder.defineMacro("__LONGDOUBLE128");
1276 // Define this for elfv2 (64-bit only) or 64-bit darwin.
1277 if (ABI == "elfv2" ||
1278 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64))
1279 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16");
1281 // CPU identification.
1282 ArchDefineTypes defs =
1283 (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1284 .Case("440", ArchDefineName)
1285 .Case("450", ArchDefineName | ArchDefine440)
1286 .Case("601", ArchDefineName)
1287 .Case("602", ArchDefineName | ArchDefinePpcgr)
1288 .Case("603", ArchDefineName | ArchDefinePpcgr)
1289 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1290 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1291 .Case("604", ArchDefineName | ArchDefinePpcgr)
1292 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1293 .Case("620", ArchDefineName | ArchDefinePpcgr)
1294 .Case("630", ArchDefineName | ArchDefinePpcgr)
1295 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1296 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1297 .Case("750", ArchDefineName | ArchDefinePpcgr)
1298 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
1300 .Case("a2", ArchDefineA2)
1301 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1302 .Case("pwr3", ArchDefinePpcgr)
1303 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1304 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
1306 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 |
1307 ArchDefinePpcgr | ArchDefinePpcsq)
1308 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 |
1309 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1310 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x |
1311 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
1313 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 |
1314 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
1315 ArchDefinePpcgr | ArchDefinePpcsq)
1316 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x |
1317 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
1318 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1319 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 |
1320 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
1321 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
1323 .Case("power3", ArchDefinePpcgr)
1324 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1325 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
1327 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
1328 ArchDefinePpcgr | ArchDefinePpcsq)
1329 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
1330 ArchDefinePwr4 | ArchDefinePpcgr |
1332 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
1333 ArchDefinePwr5 | ArchDefinePwr4 |
1334 ArchDefinePpcgr | ArchDefinePpcsq)
1335 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 |
1336 ArchDefinePwr5x | ArchDefinePwr5 |
1337 ArchDefinePwr4 | ArchDefinePpcgr |
1339 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x |
1340 ArchDefinePwr6 | ArchDefinePwr5x |
1341 ArchDefinePwr5 | ArchDefinePwr4 |
1342 ArchDefinePpcgr | ArchDefinePpcsq)
1343 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
1344 ArchDefinePwr6x | ArchDefinePwr6 |
1345 ArchDefinePwr5x | ArchDefinePwr5 |
1346 ArchDefinePwr4 | ArchDefinePpcgr |
1348 // powerpc64le automatically defaults to at least power8.
1349 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x |
1350 ArchDefinePwr6 | ArchDefinePwr5x |
1351 ArchDefinePwr5 | ArchDefinePwr4 |
1352 ArchDefinePpcgr | ArchDefinePpcsq)
1353 .Default(ArchDefineNone);
1355 if (defs & ArchDefineName)
1356 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1357 if (defs & ArchDefinePpcgr)
1358 Builder.defineMacro("_ARCH_PPCGR");
1359 if (defs & ArchDefinePpcsq)
1360 Builder.defineMacro("_ARCH_PPCSQ");
1361 if (defs & ArchDefine440)
1362 Builder.defineMacro("_ARCH_440");
1363 if (defs & ArchDefine603)
1364 Builder.defineMacro("_ARCH_603");
1365 if (defs & ArchDefine604)
1366 Builder.defineMacro("_ARCH_604");
1367 if (defs & ArchDefinePwr4)
1368 Builder.defineMacro("_ARCH_PWR4");
1369 if (defs & ArchDefinePwr5)
1370 Builder.defineMacro("_ARCH_PWR5");
1371 if (defs & ArchDefinePwr5x)
1372 Builder.defineMacro("_ARCH_PWR5X");
1373 if (defs & ArchDefinePwr6)
1374 Builder.defineMacro("_ARCH_PWR6");
1375 if (defs & ArchDefinePwr6x)
1376 Builder.defineMacro("_ARCH_PWR6X");
1377 if (defs & ArchDefinePwr7)
1378 Builder.defineMacro("_ARCH_PWR7");
1379 if (defs & ArchDefinePwr8)
1380 Builder.defineMacro("_ARCH_PWR8");
1381 if (defs & ArchDefinePwr9)
1382 Builder.defineMacro("_ARCH_PWR9");
1383 if (defs & ArchDefineA2)
1384 Builder.defineMacro("_ARCH_A2");
1385 if (defs & ArchDefineA2q) {
1386 Builder.defineMacro("_ARCH_A2Q");
1387 Builder.defineMacro("_ARCH_QP");
1390 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1391 Builder.defineMacro("__bg__");
1392 Builder.defineMacro("__THW_BLUEGENE__");
1393 Builder.defineMacro("__bgq__");
1394 Builder.defineMacro("__TOS_BGQ__");
1398 Builder.defineMacro("__VEC__", "10206");
1399 Builder.defineMacro("__ALTIVEC__");
1402 Builder.defineMacro("__VSX__");
1404 Builder.defineMacro("__POWER8_VECTOR__");
1406 Builder.defineMacro("__CRYPTO__");
1408 Builder.defineMacro("__HTM__");
1410 Builder.defineMacro("__FLOAT128__");
1412 Builder.defineMacro("__POWER9_VECTOR__");
1414 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1415 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1416 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1417 if (PointerWidth == 64)
1418 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1420 // We have support for the bswap intrinsics so we can define this.
1421 Builder.defineMacro("__HAVE_BSWAP__", "1");
1423 // FIXME: The following are not yet generated here by Clang, but are
1424 // generated by GCC:
1427 // __RECIP_PRECISION__
1428 // __APPLE_ALTIVEC__
1435 // __CMODEL_MEDIUM__
1442 // Handle explicit options being passed to the compiler here: if we've
1443 // explicitly turned off vsx and turned on any of:
1448 // then go ahead and error since the customer has expressed an incompatible
1450 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
1451 const std::vector<std::string> &FeaturesVec) {
1453 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") !=
1454 FeaturesVec.end()) {
1455 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") !=
1456 FeaturesVec.end()) {
1457 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
1462 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") !=
1463 FeaturesVec.end()) {
1464 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
1469 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") !=
1470 FeaturesVec.end()) {
1471 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
1476 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") !=
1477 FeaturesVec.end()) {
1478 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector"
1487 bool PPCTargetInfo::initFeatureMap(
1488 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
1489 const std::vector<std::string> &FeaturesVec) const {
1490 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1501 .Case("ppc64", true)
1502 .Case("ppc64le", true)
1505 Features["qpx"] = (CPU == "a2q");
1506 Features["power9-vector"] = (CPU == "pwr9");
1507 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1508 .Case("ppc64le", true)
1512 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1513 .Case("ppc64le", true)
1517 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1518 .Case("ppc64le", true)
1523 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1524 .Case("ppc64le", true)
1529 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1530 .Case("ppc64le", true)
1534 Features["vsx"] = llvm::StringSwitch<bool>(CPU)
1535 .Case("ppc64le", true)
1540 Features["htm"] = llvm::StringSwitch<bool>(CPU)
1541 .Case("ppc64le", true)
1546 if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
1549 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1552 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1553 return llvm::StringSwitch<bool>(Feature)
1554 .Case("powerpc", true)
1555 .Case("altivec", HasAltivec)
1556 .Case("vsx", HasVSX)
1557 .Case("power8-vector", HasP8Vector)
1558 .Case("crypto", HasP8Crypto)
1559 .Case("direct-move", HasDirectMove)
1560 .Case("qpx", HasQPX)
1561 .Case("htm", HasHTM)
1562 .Case("bpermd", HasBPERMD)
1563 .Case("extdiv", HasExtDiv)
1564 .Case("float128", HasFloat128)
1565 .Case("power9-vector", HasP9Vector)
1569 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1570 StringRef Name, bool Enabled) const {
1572 // If we're enabling any of the vsx based features then enable vsx and
1573 // altivec. We'll diagnose any problems later.
1574 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name)
1576 .Case("direct-move", true)
1577 .Case("power8-vector", true)
1578 .Case("power9-vector", true)
1579 .Case("float128", true)
1582 Features["vsx"] = Features["altivec"] = true;
1583 if (Name == "power9-vector")
1584 Features["power8-vector"] = true;
1585 Features[Name] = true;
1587 // If we're disabling altivec or vsx go ahead and disable all of the vsx
1589 if ((Name == "altivec") || (Name == "vsx"))
1590 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] =
1591 Features["float128"] = Features["power9-vector"] = false;
1592 if (Name == "power8-vector")
1593 Features["power9-vector"] = false;
1594 Features[Name] = false;
1598 const char * const PPCTargetInfo::GCCRegNames[] = {
1599 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1600 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1601 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1602 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1603 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1604 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1605 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1606 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1607 "mq", "lr", "ctr", "ap",
1608 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1610 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1611 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1612 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1613 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1615 "spe_acc", "spefscr",
1619 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const {
1620 return llvm::makeArrayRef(GCCRegNames);
1623 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1624 // While some of these aliases do map to different registers
1625 // they still share the same register name.
1636 { { "10" }, "r10" },
1637 { { "11" }, "r11" },
1638 { { "12" }, "r12" },
1639 { { "13" }, "r13" },
1640 { { "14" }, "r14" },
1641 { { "15" }, "r15" },
1642 { { "16" }, "r16" },
1643 { { "17" }, "r17" },
1644 { { "18" }, "r18" },
1645 { { "19" }, "r19" },
1646 { { "20" }, "r20" },
1647 { { "21" }, "r21" },
1648 { { "22" }, "r22" },
1649 { { "23" }, "r23" },
1650 { { "24" }, "r24" },
1651 { { "25" }, "r25" },
1652 { { "26" }, "r26" },
1653 { { "27" }, "r27" },
1654 { { "28" }, "r28" },
1655 { { "29" }, "r29" },
1656 { { "30" }, "r30" },
1657 { { "31" }, "r31" },
1658 { { "fr0" }, "f0" },
1659 { { "fr1" }, "f1" },
1660 { { "fr2" }, "f2" },
1661 { { "fr3" }, "f3" },
1662 { { "fr4" }, "f4" },
1663 { { "fr5" }, "f5" },
1664 { { "fr6" }, "f6" },
1665 { { "fr7" }, "f7" },
1666 { { "fr8" }, "f8" },
1667 { { "fr9" }, "f9" },
1668 { { "fr10" }, "f10" },
1669 { { "fr11" }, "f11" },
1670 { { "fr12" }, "f12" },
1671 { { "fr13" }, "f13" },
1672 { { "fr14" }, "f14" },
1673 { { "fr15" }, "f15" },
1674 { { "fr16" }, "f16" },
1675 { { "fr17" }, "f17" },
1676 { { "fr18" }, "f18" },
1677 { { "fr19" }, "f19" },
1678 { { "fr20" }, "f20" },
1679 { { "fr21" }, "f21" },
1680 { { "fr22" }, "f22" },
1681 { { "fr23" }, "f23" },
1682 { { "fr24" }, "f24" },
1683 { { "fr25" }, "f25" },
1684 { { "fr26" }, "f26" },
1685 { { "fr27" }, "f27" },
1686 { { "fr28" }, "f28" },
1687 { { "fr29" }, "f29" },
1688 { { "fr30" }, "f30" },
1689 { { "fr31" }, "f31" },
1690 { { "cc" }, "cr0" },
1693 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
1694 return llvm::makeArrayRef(GCCRegAliases);
1697 class PPC32TargetInfo : public PPCTargetInfo {
1699 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1700 : PPCTargetInfo(Triple, Opts) {
1701 resetDataLayout("E-m:e-p:32:32-i64:64-n32");
1703 switch (getTriple().getOS()) {
1704 case llvm::Triple::Linux:
1705 case llvm::Triple::FreeBSD:
1706 case llvm::Triple::NetBSD:
1707 SizeType = UnsignedInt;
1708 PtrDiffType = SignedInt;
1709 IntPtrType = SignedInt;
1715 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1716 LongDoubleWidth = LongDoubleAlign = 64;
1717 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1720 // PPC32 supports atomics up to 4 bytes.
1721 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1724 BuiltinVaListKind getBuiltinVaListKind() const override {
1725 // This is the ELF definition, and is overridden by the Darwin sub-target
1726 return TargetInfo::PowerABIBuiltinVaList;
1730 // Note: ABI differences may eventually require us to have a separate
1731 // TargetInfo for little endian.
1732 class PPC64TargetInfo : public PPCTargetInfo {
1734 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1735 : PPCTargetInfo(Triple, Opts) {
1736 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1737 IntMaxType = SignedLong;
1738 Int64Type = SignedLong;
1740 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1741 resetDataLayout("e-m:e-i64:64-n32:64");
1744 resetDataLayout("E-m:e-i64:64-n32:64");
1748 switch (getTriple().getOS()) {
1749 case llvm::Triple::FreeBSD:
1750 LongDoubleWidth = LongDoubleAlign = 64;
1751 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1753 case llvm::Triple::NetBSD:
1754 IntMaxType = SignedLongLong;
1755 Int64Type = SignedLongLong;
1761 // PPC64 supports atomics up to 8 bytes.
1762 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1764 BuiltinVaListKind getBuiltinVaListKind() const override {
1765 return TargetInfo::CharPtrBuiltinVaList;
1767 // PPC64 Linux-specific ABI options.
1768 bool setABI(const std::string &Name) override {
1769 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1777 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> {
1779 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1780 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
1781 HasAlignMac68kSupport = true;
1782 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1783 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1785 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
1787 BuiltinVaListKind getBuiltinVaListKind() const override {
1788 return TargetInfo::CharPtrBuiltinVaList;
1792 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> {
1794 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1795 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
1796 HasAlignMac68kSupport = true;
1797 resetDataLayout("E-m:o-i64:64-n32:64");
1801 static const unsigned NVPTXAddrSpaceMap[] = {
1805 4, // opencl_constant
1806 // FIXME: generic has to be added to the target
1807 0, // opencl_generic
1813 class NVPTXTargetInfo : public TargetInfo {
1814 static const char *const GCCRegNames[];
1815 static const Builtin::Info BuiltinInfo[];
1817 std::unique_ptr<TargetInfo> HostTarget;
1820 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts,
1821 unsigned TargetPointerWidth)
1822 : TargetInfo(Triple) {
1823 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) &&
1824 "NVPTX only supports 32- and 64-bit modes.");
1826 TLSSupported = false;
1827 AddrSpaceMap = &NVPTXAddrSpaceMap;
1828 UseAddrSpaceMapMangling = true;
1830 // Define available target features
1831 // These must be defined in sorted order!
1832 NoAsmVariants = true;
1833 GPU = CudaArch::SM_20;
1835 if (TargetPointerWidth == 32)
1836 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64");
1838 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64");
1840 // If possible, get a TargetInfo for our host triple, so we can match its
1842 llvm::Triple HostTriple(Opts.HostTriple);
1843 if (!HostTriple.isNVPTX())
1844 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts));
1846 // If no host target, make some guesses about the data layout and return.
1848 LongWidth = LongAlign = TargetPointerWidth;
1849 PointerWidth = PointerAlign = TargetPointerWidth;
1850 switch (TargetPointerWidth) {
1852 SizeType = TargetInfo::UnsignedInt;
1853 PtrDiffType = TargetInfo::SignedInt;
1854 IntPtrType = TargetInfo::SignedInt;
1857 SizeType = TargetInfo::UnsignedLong;
1858 PtrDiffType = TargetInfo::SignedLong;
1859 IntPtrType = TargetInfo::SignedLong;
1862 llvm_unreachable("TargetPointerWidth must be 32 or 64");
1867 // Copy properties from host target.
1868 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0);
1869 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0);
1870 BoolWidth = HostTarget->getBoolWidth();
1871 BoolAlign = HostTarget->getBoolAlign();
1872 IntWidth = HostTarget->getIntWidth();
1873 IntAlign = HostTarget->getIntAlign();
1874 HalfWidth = HostTarget->getHalfWidth();
1875 HalfAlign = HostTarget->getHalfAlign();
1876 FloatWidth = HostTarget->getFloatWidth();
1877 FloatAlign = HostTarget->getFloatAlign();
1878 DoubleWidth = HostTarget->getDoubleWidth();
1879 DoubleAlign = HostTarget->getDoubleAlign();
1880 LongWidth = HostTarget->getLongWidth();
1881 LongAlign = HostTarget->getLongAlign();
1882 LongLongWidth = HostTarget->getLongLongWidth();
1883 LongLongAlign = HostTarget->getLongLongAlign();
1884 MinGlobalAlign = HostTarget->getMinGlobalAlign();
1885 NewAlign = HostTarget->getNewAlign();
1886 DefaultAlignForAttributeAligned =
1887 HostTarget->getDefaultAlignForAttributeAligned();
1888 SizeType = HostTarget->getSizeType();
1889 IntMaxType = HostTarget->getIntMaxType();
1890 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0);
1891 IntPtrType = HostTarget->getIntPtrType();
1892 WCharType = HostTarget->getWCharType();
1893 WIntType = HostTarget->getWIntType();
1894 Char16Type = HostTarget->getChar16Type();
1895 Char32Type = HostTarget->getChar32Type();
1896 Int64Type = HostTarget->getInt64Type();
1897 SigAtomicType = HostTarget->getSigAtomicType();
1898 ProcessIDType = HostTarget->getProcessIDType();
1900 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
1901 UseZeroLengthBitfieldAlignment =
1902 HostTarget->useZeroLengthBitfieldAlignment();
1903 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
1904 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
1906 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
1907 // we need those macros to be identical on host and device, because (among
1908 // other things) they affect which standard library classes are defined, and
1909 // we need all classes to be defined on both the host and device.
1910 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
1912 // Properties intentionally not copied from host:
1913 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the
1914 // host/device boundary.
1915 // - SuitableAlign: Not visible across the host/device boundary, and may
1916 // correctly be different on host/device, e.g. if host has wider vector
1917 // types than device.
1918 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same
1919 // as its double type, but that's not necessarily true on the host.
1920 // TODO: nvcc emits a warning when using long double on device; we should
1923 void getTargetDefines(const LangOptions &Opts,
1924 MacroBuilder &Builder) const override {
1925 Builder.defineMacro("__PTX__");
1926 Builder.defineMacro("__NVPTX__");
1927 if (Opts.CUDAIsDevice) {
1928 // Set __CUDA_ARCH__ for the GPU specified.
1929 std::string CUDAArchCode = [this] {
1931 case CudaArch::UNKNOWN:
1932 assert(false && "No GPU arch when compiling CUDA device code.");
1934 case CudaArch::SM_20:
1936 case CudaArch::SM_21:
1938 case CudaArch::SM_30:
1940 case CudaArch::SM_32:
1942 case CudaArch::SM_35:
1944 case CudaArch::SM_37:
1946 case CudaArch::SM_50:
1948 case CudaArch::SM_52:
1950 case CudaArch::SM_53:
1952 case CudaArch::SM_60:
1954 case CudaArch::SM_61:
1956 case CudaArch::SM_62:
1959 llvm_unreachable("unhandled CudaArch");
1961 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1964 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1965 return llvm::makeArrayRef(BuiltinInfo,
1966 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin);
1969 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
1971 const std::vector<std::string> &FeaturesVec) const override {
1972 Features["satom"] = GPU >= CudaArch::SM_60;
1973 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1976 bool hasFeature(StringRef Feature) const override {
1977 return llvm::StringSwitch<bool>(Feature)
1978 .Cases("ptx", "nvptx", true)
1979 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope.
1983 ArrayRef<const char *> getGCCRegNames() const override;
1984 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1988 bool validateAsmConstraint(const char *&Name,
1989 TargetInfo::ConstraintInfo &Info) const override {
1999 Info.setAllowsRegister();
2003 const char *getClobbers() const override {
2004 // FIXME: Is this really right?
2007 BuiltinVaListKind getBuiltinVaListKind() const override {
2009 return TargetInfo::CharPtrBuiltinVaList;
2011 bool setCPU(const std::string &Name) override {
2012 GPU = StringToCudaArch(Name);
2013 return GPU != CudaArch::UNKNOWN;
2015 void setSupportedOpenCLOpts() override {
2016 auto &Opts = getSupportedOpenCLOpts();
2017 Opts.support("cl_clang_storage_class_specifiers");
2018 Opts.support("cl_khr_gl_sharing");
2019 Opts.support("cl_khr_icd");
2021 Opts.support("cl_khr_fp64");
2022 Opts.support("cl_khr_byte_addressable_store");
2023 Opts.support("cl_khr_global_int32_base_atomics");
2024 Opts.support("cl_khr_global_int32_extended_atomics");
2025 Opts.support("cl_khr_local_int32_base_atomics");
2026 Opts.support("cl_khr_local_int32_extended_atomics");
2029 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2030 // CUDA compilations support all of the host's calling conventions.
2032 // TODO: We should warn if you apply a non-default CC to anything other than
2035 return HostTarget->checkCallingConvention(CC);
2036 return CCCR_Warning;
2040 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
2041 #define BUILTIN(ID, TYPE, ATTRS) \
2042 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2043 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
2044 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
2045 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2046 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2047 #include "clang/Basic/BuiltinsNVPTX.def"
2050 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
2052 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
2053 return llvm::makeArrayRef(GCCRegNames);
2056 static const LangAS::Map AMDGPUPrivIsZeroDefIsGenMap = {
2060 2, // opencl_constant
2061 4, // opencl_generic
2066 static const LangAS::Map AMDGPUGenIsZeroDefIsGenMap = {
2070 2, // opencl_constant
2071 0, // opencl_generic
2076 static const LangAS::Map AMDGPUPrivIsZeroDefIsPrivMap = {
2080 2, // opencl_constant
2081 4, // opencl_generic
2086 static const LangAS::Map AMDGPUGenIsZeroDefIsPrivMap = {
2090 2, // opencl_constant
2091 0, // opencl_generic
2097 // If you edit the description strings, make sure you update
2098 // getPointerWidthV().
2100 static const char *const DataLayoutStringR600 =
2101 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2102 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
2104 static const char *const DataLayoutStringSIPrivateIsZero =
2105 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
2106 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2107 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
2109 static const char *const DataLayoutStringSIGenericIsZero =
2110 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
2111 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2112 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
2114 class AMDGPUTargetInfo final : public TargetInfo {
2115 static const Builtin::Info BuiltinInfo[];
2116 static const char * const GCCRegNames[];
2119 unsigned Generic, Global, Local, Constant, Private;
2120 AddrSpace(bool IsGenericZero_ = false){
2121 if (IsGenericZero_) {
2137 /// \brief The GPU profiles supported by the AMDGPU target.
2145 GK_EVERGREEN_DOUBLE_OPS,
2146 GK_NORTHERN_ISLANDS,
2159 static bool hasFullSpeedFMAF32(StringRef GPUName) {
2160 return parseAMDGCNName(GPUName) >= GK_GFX9;
2163 static bool isAMDGCN(const llvm::Triple &TT) {
2164 return TT.getArch() == llvm::Triple::amdgcn;
2167 static bool isGenericZero(const llvm::Triple &TT) {
2168 return TT.getEnvironmentName() == "amdgiz" ||
2169 TT.getEnvironmentName() == "amdgizcl";
2172 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
2173 : TargetInfo(Triple) ,
2174 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600),
2178 AS(isGenericZero(Triple)){
2179 if (getTriple().getArch() == llvm::Triple::amdgcn) {
2184 auto IsGenericZero = isGenericZero(Triple);
2185 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ?
2186 (IsGenericZero ? DataLayoutStringSIGenericIsZero :
2187 DataLayoutStringSIPrivateIsZero)
2188 : DataLayoutStringR600);
2189 assert(DataLayout->getAllocaAddrSpace() == AS.Private);
2191 setAddressSpaceMap(Triple.getOS() == llvm::Triple::Mesa3D ||
2192 Triple.getEnvironment() == llvm::Triple::OpenCL ||
2193 Triple.getEnvironmentName() == "amdgizcl" ||
2195 UseAddrSpaceMapMangling = true;
2197 // Set pointer width and alignment for target address space 0.
2198 PointerWidth = PointerAlign = DataLayout->getPointerSizeInBits();
2199 if (getMaxPointerWidth() == 64) {
2200 LongWidth = LongAlign = 64;
2201 SizeType = UnsignedLong;
2202 PtrDiffType = SignedLong;
2203 IntPtrType = SignedLong;
2207 void setAddressSpaceMap(bool DefaultIsPrivate) {
2208 if (isGenericZero(getTriple())) {
2209 AddrSpaceMap = DefaultIsPrivate ? &AMDGPUGenIsZeroDefIsPrivMap
2210 : &AMDGPUGenIsZeroDefIsGenMap;
2212 AddrSpaceMap = DefaultIsPrivate ? &AMDGPUPrivIsZeroDefIsPrivMap
2213 : &AMDGPUPrivIsZeroDefIsGenMap;
2217 void adjust(LangOptions &Opts) override {
2218 TargetInfo::adjust(Opts);
2219 setAddressSpaceMap(Opts.OpenCL || !isAMDGCN(getTriple()));
2222 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
2223 if (GPU <= GK_CAYMAN)
2226 if (AddrSpace == AS.Private || AddrSpace == AS.Local) {
2232 uint64_t getPointerAlignV(unsigned AddrSpace) const override {
2233 return getPointerWidthV(AddrSpace);
2236 uint64_t getMaxPointerWidth() const override {
2237 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32;
2240 const char * getClobbers() const override {
2244 ArrayRef<const char *> getGCCRegNames() const override;
2246 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2250 bool validateAsmConstraint(const char *&Name,
2251 TargetInfo::ConstraintInfo &Info) const override {
2256 Info.setAllowsRegister();
2262 bool initFeatureMap(llvm::StringMap<bool> &Features,
2263 DiagnosticsEngine &Diags, StringRef CPU,
2264 const std::vector<std::string> &FeatureVec) const override;
2266 void adjustTargetOptions(const CodeGenOptions &CGOpts,
2267 TargetOptions &TargetOpts) const override {
2268 bool hasFP32Denormals = false;
2269 bool hasFP64Denormals = false;
2270 for (auto &I : TargetOpts.FeaturesAsWritten) {
2271 if (I == "+fp32-denormals" || I == "-fp32-denormals")
2272 hasFP32Denormals = true;
2273 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals")
2274 hasFP64Denormals = true;
2276 if (!hasFP32Denormals)
2277 TargetOpts.Features.push_back(
2278 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) &&
2279 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str());
2280 // Always do not flush fp64 or fp16 denorms.
2281 if (!hasFP64Denormals && hasFP64)
2282 TargetOpts.Features.push_back("+fp64-fp16-denormals");
2285 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
2286 return llvm::makeArrayRef(BuiltinInfo,
2287 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin);
2290 void getTargetDefines(const LangOptions &Opts,
2291 MacroBuilder &Builder) const override {
2292 if (getTriple().getArch() == llvm::Triple::amdgcn)
2293 Builder.defineMacro("__AMDGCN__");
2295 Builder.defineMacro("__R600__");
2298 Builder.defineMacro("__HAS_FMAF__");
2300 Builder.defineMacro("__HAS_LDEXPF__");
2302 Builder.defineMacro("__HAS_FP64__");
2305 BuiltinVaListKind getBuiltinVaListKind() const override {
2306 return TargetInfo::CharPtrBuiltinVaList;
2309 static GPUKind parseR600Name(StringRef Name) {
2310 return llvm::StringSwitch<GPUKind>(Name)
2311 .Case("r600" , GK_R600)
2312 .Case("rv610", GK_R600)
2313 .Case("rv620", GK_R600)
2314 .Case("rv630", GK_R600)
2315 .Case("rv635", GK_R600)
2316 .Case("rs780", GK_R600)
2317 .Case("rs880", GK_R600)
2318 .Case("rv670", GK_R600_DOUBLE_OPS)
2319 .Case("rv710", GK_R700)
2320 .Case("rv730", GK_R700)
2321 .Case("rv740", GK_R700_DOUBLE_OPS)
2322 .Case("rv770", GK_R700_DOUBLE_OPS)
2323 .Case("palm", GK_EVERGREEN)
2324 .Case("cedar", GK_EVERGREEN)
2325 .Case("sumo", GK_EVERGREEN)
2326 .Case("sumo2", GK_EVERGREEN)
2327 .Case("redwood", GK_EVERGREEN)
2328 .Case("juniper", GK_EVERGREEN)
2329 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
2330 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
2331 .Case("barts", GK_NORTHERN_ISLANDS)
2332 .Case("turks", GK_NORTHERN_ISLANDS)
2333 .Case("caicos", GK_NORTHERN_ISLANDS)
2334 .Case("cayman", GK_CAYMAN)
2335 .Case("aruba", GK_CAYMAN)
2339 static GPUKind parseAMDGCNName(StringRef Name) {
2340 return llvm::StringSwitch<GPUKind>(Name)
2341 .Case("tahiti", GK_GFX6)
2342 .Case("pitcairn", GK_GFX6)
2343 .Case("verde", GK_GFX6)
2344 .Case("oland", GK_GFX6)
2345 .Case("hainan", GK_GFX6)
2346 .Case("bonaire", GK_GFX7)
2347 .Case("kabini", GK_GFX7)
2348 .Case("kaveri", GK_GFX7)
2349 .Case("hawaii", GK_GFX7)
2350 .Case("mullins", GK_GFX7)
2351 .Case("gfx700", GK_GFX7)
2352 .Case("gfx701", GK_GFX7)
2353 .Case("gfx702", GK_GFX7)
2354 .Case("tonga", GK_GFX8)
2355 .Case("iceland", GK_GFX8)
2356 .Case("carrizo", GK_GFX8)
2357 .Case("fiji", GK_GFX8)
2358 .Case("stoney", GK_GFX8)
2359 .Case("polaris10", GK_GFX8)
2360 .Case("polaris11", GK_GFX8)
2361 .Case("gfx800", GK_GFX8)
2362 .Case("gfx801", GK_GFX8)
2363 .Case("gfx802", GK_GFX8)
2364 .Case("gfx803", GK_GFX8)
2365 .Case("gfx804", GK_GFX8)
2366 .Case("gfx810", GK_GFX8)
2367 .Case("gfx900", GK_GFX9)
2368 .Case("gfx901", GK_GFX9)
2372 bool setCPU(const std::string &Name) override {
2373 if (getTriple().getArch() == llvm::Triple::amdgcn)
2374 GPU = parseAMDGCNName(Name);
2376 GPU = parseR600Name(Name);
2378 return GPU != GK_NONE;
2381 void setSupportedOpenCLOpts() override {
2382 auto &Opts = getSupportedOpenCLOpts();
2383 Opts.support("cl_clang_storage_class_specifiers");
2384 Opts.support("cl_khr_icd");
2387 Opts.support("cl_khr_fp64");
2388 if (GPU >= GK_EVERGREEN) {
2389 Opts.support("cl_khr_byte_addressable_store");
2390 Opts.support("cl_khr_global_int32_base_atomics");
2391 Opts.support("cl_khr_global_int32_extended_atomics");
2392 Opts.support("cl_khr_local_int32_base_atomics");
2393 Opts.support("cl_khr_local_int32_extended_atomics");
2395 if (GPU >= GK_GFX6) {
2396 Opts.support("cl_khr_fp16");
2397 Opts.support("cl_khr_int64_base_atomics");
2398 Opts.support("cl_khr_int64_extended_atomics");
2399 Opts.support("cl_khr_mipmap_image");
2400 Opts.support("cl_khr_subgroups");
2401 Opts.support("cl_khr_3d_image_writes");
2402 Opts.support("cl_amd_media_ops");
2403 Opts.support("cl_amd_media_ops2");
2407 LangAS::ID getOpenCLImageAddrSpace() const override {
2408 return LangAS::opencl_constant;
2411 llvm::Optional<unsigned> getConstantAddressSpace() const override {
2412 return LangAS::FirstTargetAddressSpace + AS.Constant;
2415 /// \returns Target specific vtbl ptr address space.
2416 unsigned getVtblPtrAddressSpace() const override { return AS.Constant; }
2418 /// \returns If a target requires an address within a target specific address
2419 /// space \p AddressSpace to be converted in order to be used, then return the
2420 /// corresponding target specific DWARF address space.
2422 /// \returns Otherwise return None and no conversion will be emitted in the
2424 Optional<unsigned> getDWARFAddressSpace(
2425 unsigned AddressSpace) const override {
2426 const unsigned DWARF_Private = 1;
2427 const unsigned DWARF_Local = 2;
2428 if (AddressSpace == AS.Private) {
2429 return DWARF_Private;
2430 } else if (AddressSpace == AS.Local) {
2437 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2440 return CCCR_Warning;
2442 case CC_OpenCLKernel:
2447 // In amdgcn target the null pointer in global, constant, and generic
2448 // address space has value 0 but in private and local address space has
2450 uint64_t getNullPointerValue(unsigned AS) const override {
2451 return AS == LangAS::opencl_local ? ~0 : 0;
2455 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
2456 #define BUILTIN(ID, TYPE, ATTRS) \
2457 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2458 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2459 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2460 #include "clang/Basic/BuiltinsAMDGPU.def"
2462 const char * const AMDGPUTargetInfo::GCCRegNames[] = {
2463 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2464 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2465 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2466 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
2467 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
2468 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
2469 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
2470 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
2471 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
2472 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
2473 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
2474 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
2475 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
2476 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
2477 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
2478 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
2479 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
2480 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
2481 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
2482 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
2483 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
2484 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
2485 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
2486 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
2487 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
2488 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
2489 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
2490 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
2491 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
2492 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
2493 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
2494 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
2495 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2496 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
2497 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
2498 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
2499 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
2500 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
2501 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
2502 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
2503 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
2504 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
2505 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
2506 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
2507 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
2508 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
2509 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
2510 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127",
2511 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi",
2512 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi"
2515 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const {
2516 return llvm::makeArrayRef(GCCRegNames);
2519 bool AMDGPUTargetInfo::initFeatureMap(
2520 llvm::StringMap<bool> &Features,
2521 DiagnosticsEngine &Diags, StringRef CPU,
2522 const std::vector<std::string> &FeatureVec) const {
2524 // XXX - What does the member GPU mean if device name string passed here?
2525 if (getTriple().getArch() == llvm::Triple::amdgcn) {
2529 switch (parseAMDGCNName(CPU)) {
2535 Features["gfx9-insts"] = true;
2538 Features["s-memrealtime"] = true;
2539 Features["16-bit-insts"] = true;
2540 Features["dpp"] = true;
2546 llvm_unreachable("unhandled subtarget");
2552 switch (parseR600Name(CPU)) {
2556 case GK_NORTHERN_ISLANDS:
2558 case GK_R600_DOUBLE_OPS:
2559 case GK_R700_DOUBLE_OPS:
2560 case GK_EVERGREEN_DOUBLE_OPS:
2562 Features["fp64"] = true;
2567 llvm_unreachable("unhandled subtarget");
2571 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec);
2574 const Builtin::Info BuiltinInfoX86[] = {
2575 #define BUILTIN(ID, TYPE, ATTRS) \
2576 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2577 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2578 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2579 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
2580 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
2581 #include "clang/Basic/BuiltinsX86.def"
2583 #define BUILTIN(ID, TYPE, ATTRS) \
2584 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2585 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2586 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2587 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
2588 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
2589 #include "clang/Basic/BuiltinsX86_64.def"
2593 static const char* const GCCRegNames[] = {
2594 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
2595 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
2596 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
2597 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
2598 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
2599 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2600 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
2601 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
2602 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
2603 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23",
2604 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31",
2605 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23",
2606 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31",
2607 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7",
2608 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15",
2609 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23",
2610 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31",
2611 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7",
2614 const TargetInfo::AddlRegName AddlRegNames[] = {
2615 { { "al", "ah", "eax", "rax" }, 0 },
2616 { { "bl", "bh", "ebx", "rbx" }, 3 },
2617 { { "cl", "ch", "ecx", "rcx" }, 2 },
2618 { { "dl", "dh", "edx", "rdx" }, 1 },
2619 { { "esi", "rsi" }, 4 },
2620 { { "edi", "rdi" }, 5 },
2621 { { "esp", "rsp" }, 7 },
2622 { { "ebp", "rbp" }, 6 },
2623 { { "r8d", "r8w", "r8b" }, 38 },
2624 { { "r9d", "r9w", "r9b" }, 39 },
2625 { { "r10d", "r10w", "r10b" }, 40 },
2626 { { "r11d", "r11w", "r11b" }, 41 },
2627 { { "r12d", "r12w", "r12b" }, 42 },
2628 { { "r13d", "r13w", "r13b" }, 43 },
2629 { { "r14d", "r14w", "r14b" }, 44 },
2630 { { "r15d", "r15w", "r15b" }, 45 },
2633 // X86 target abstract base class; x86-32 and x86-64 are very close, so
2634 // most of the implementation can be shared.
2635 class X86TargetInfo : public TargetInfo {
2637 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
2640 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
2641 } MMX3DNowLevel = NoMMX3DNow;
2649 bool HasAES = false;
2650 bool HasPCLMUL = false;
2651 bool HasLZCNT = false;
2652 bool HasRDRND = false;
2653 bool HasFSGSBASE = false;
2654 bool HasBMI = false;
2655 bool HasBMI2 = false;
2656 bool HasPOPCNT = false;
2657 bool HasRTM = false;
2658 bool HasPRFCHW = false;
2659 bool HasRDSEED = false;
2660 bool HasADX = false;
2661 bool HasTBM = false;
2662 bool HasLWP = false;
2663 bool HasFMA = false;
2664 bool HasF16C = false;
2665 bool HasAVX512CD = false;
2666 bool HasAVX512VPOPCNTDQ = false;
2667 bool HasAVX512ER = false;
2668 bool HasAVX512PF = false;
2669 bool HasAVX512DQ = false;
2670 bool HasAVX512BW = false;
2671 bool HasAVX512VL = false;
2672 bool HasAVX512VBMI = false;
2673 bool HasAVX512IFMA = false;
2674 bool HasSHA = false;
2675 bool HasMPX = false;
2676 bool HasSGX = false;
2677 bool HasCX16 = false;
2678 bool HasFXSR = false;
2679 bool HasXSAVE = false;
2680 bool HasXSAVEOPT = false;
2681 bool HasXSAVEC = false;
2682 bool HasXSAVES = false;
2683 bool HasMWAITX = false;
2684 bool HasCLZERO = false;
2685 bool HasPKU = false;
2686 bool HasCLFLUSHOPT = false;
2687 bool HasCLWB = false;
2688 bool HasMOVBE = false;
2689 bool HasPREFETCHWT1 = false;
2691 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2693 /// Each enumeration represents a particular CPU supported by Clang. These
2694 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2699 /// i386-generation processors.
2705 /// i486-generation processors.
2714 /// i586-generation processors, P5 microarchitecture based.
2722 /// i686-generation processors, P6 / Pentium M microarchitecture based.
2732 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2733 /// Clang however has some logic to support this.
2734 // FIXME: Warn, deprecate, and potentially remove this.
2739 /// Netburst microarchitecture based processors.
2748 /// Core microarchitecture based processors.
2752 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2753 /// codename which GCC no longer accepts as an option to -march, but Clang
2754 /// has some logic for recognizing it.
2755 // FIXME: Warn, deprecate, and potentially remove this.
2768 /// Nehalem microarchitecture based processors.
2772 /// Westmere microarchitecture based processors.
2775 /// \name Sandy Bridge
2776 /// Sandy Bridge microarchitecture based processors.
2779 /// \name Ivy Bridge
2780 /// Ivy Bridge microarchitecture based processors.
2784 /// Haswell microarchitecture based processors.
2788 /// Broadwell microarchitecture based processors.
2791 /// \name Skylake Client
2792 /// Skylake client microarchitecture based processors.
2795 /// \name Skylake Server
2796 /// Skylake server microarchitecture based processors.
2799 /// \name Cannonlake Client
2800 /// Cannonlake client microarchitecture based processors.
2803 /// \name Knights Landing
2804 /// Knights Landing processor.
2808 /// Lakemont microarchitecture based processors.
2812 /// K6 architecture processors.
2820 /// K7 architecture processors.
2823 CK_AthlonThunderbird,
2830 /// K8 architecture processors.
2843 /// Bobcat architecture processors.
2850 /// Bulldozer architecture processors.
2859 /// Zen architecture processors.
2864 /// This specification is deprecated and will be removed in the future.
2865 /// Users should prefer \see CK_K8.
2866 // FIXME: Warn on this when the CPU is set to it.
2872 /// Geode processors.
2878 CPUKind getCPUKind(StringRef CPU) const {
2879 return llvm::StringSwitch<CPUKind>(CPU)
2880 .Case("i386", CK_i386)
2881 .Case("i486", CK_i486)
2882 .Case("winchip-c6", CK_WinChipC6)
2883 .Case("winchip2", CK_WinChip2)
2885 .Case("i586", CK_i586)
2886 .Case("pentium", CK_Pentium)
2887 .Case("pentium-mmx", CK_PentiumMMX)
2888 .Case("i686", CK_i686)
2889 .Case("pentiumpro", CK_PentiumPro)
2890 .Case("pentium2", CK_Pentium2)
2891 .Case("pentium3", CK_Pentium3)
2892 .Case("pentium3m", CK_Pentium3M)
2893 .Case("pentium-m", CK_PentiumM)
2894 .Case("c3-2", CK_C3_2)
2895 .Case("yonah", CK_Yonah)
2896 .Case("pentium4", CK_Pentium4)
2897 .Case("pentium4m", CK_Pentium4M)
2898 .Case("prescott", CK_Prescott)
2899 .Case("nocona", CK_Nocona)
2900 .Case("core2", CK_Core2)
2901 .Case("penryn", CK_Penryn)
2902 .Case("bonnell", CK_Bonnell)
2903 .Case("atom", CK_Bonnell) // Legacy name.
2904 .Case("silvermont", CK_Silvermont)
2905 .Case("slm", CK_Silvermont) // Legacy name.
2906 .Case("goldmont", CK_Goldmont)
2907 .Case("nehalem", CK_Nehalem)
2908 .Case("corei7", CK_Nehalem) // Legacy name.
2909 .Case("westmere", CK_Westmere)
2910 .Case("sandybridge", CK_SandyBridge)
2911 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2912 .Case("ivybridge", CK_IvyBridge)
2913 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2914 .Case("haswell", CK_Haswell)
2915 .Case("core-avx2", CK_Haswell) // Legacy name.
2916 .Case("broadwell", CK_Broadwell)
2917 .Case("skylake", CK_SkylakeClient)
2918 .Case("skylake-avx512", CK_SkylakeServer)
2919 .Case("skx", CK_SkylakeServer) // Legacy name.
2920 .Case("cannonlake", CK_Cannonlake)
2921 .Case("knl", CK_KNL)
2922 .Case("lakemont", CK_Lakemont)
2924 .Case("k6-2", CK_K6_2)
2925 .Case("k6-3", CK_K6_3)
2926 .Case("athlon", CK_Athlon)
2927 .Case("athlon-tbird", CK_AthlonThunderbird)
2928 .Case("athlon-4", CK_Athlon4)
2929 .Case("athlon-xp", CK_AthlonXP)
2930 .Case("athlon-mp", CK_AthlonMP)
2931 .Case("athlon64", CK_Athlon64)
2932 .Case("athlon64-sse3", CK_Athlon64SSE3)
2933 .Case("athlon-fx", CK_AthlonFX)
2935 .Case("k8-sse3", CK_K8SSE3)
2936 .Case("opteron", CK_Opteron)
2937 .Case("opteron-sse3", CK_OpteronSSE3)
2938 .Case("barcelona", CK_AMDFAM10)
2939 .Case("amdfam10", CK_AMDFAM10)
2940 .Case("btver1", CK_BTVER1)
2941 .Case("btver2", CK_BTVER2)
2942 .Case("bdver1", CK_BDVER1)
2943 .Case("bdver2", CK_BDVER2)
2944 .Case("bdver3", CK_BDVER3)
2945 .Case("bdver4", CK_BDVER4)
2946 .Case("znver1", CK_ZNVER1)
2947 .Case("x86-64", CK_x86_64)
2948 .Case("geode", CK_Geode)
2949 .Default(CK_Generic);
2956 } FPMath = FP_Default;
2959 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
2960 : TargetInfo(Triple) {
2961 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
2963 unsigned getFloatEvalMethod() const override {
2964 // X87 evaluates with 80 bits "long double" precision.
2965 return SSELevel == NoSSE ? 2 : 0;
2967 ArrayRef<const char *> getGCCRegNames() const override {
2968 return llvm::makeArrayRef(GCCRegNames);
2970 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2973 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
2974 return llvm::makeArrayRef(AddlRegNames);
2976 bool validateCpuSupports(StringRef Name) const override;
2977 bool validateAsmConstraint(const char *&Name,
2978 TargetInfo::ConstraintInfo &info) const override;
2980 bool validateGlobalRegisterVariable(StringRef RegName,
2982 bool &HasSizeMismatch) const override {
2983 // esp and ebp are the only 32-bit registers the x86 backend can currently
2985 if (RegName.equals("esp") || RegName.equals("ebp")) {
2986 // Check that the register size is 32-bit.
2987 HasSizeMismatch = RegSize != 32;
2994 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2996 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2998 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
3000 std::string convertConstraint(const char *&Constraint) const override;
3001 const char *getClobbers() const override {
3002 return "~{dirflag},~{fpsr},~{flags}";
3005 StringRef getConstraintRegister(const StringRef &Constraint,
3006 const StringRef &Expression) const override {
3007 StringRef::iterator I, E;
3008 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) {
3015 // For the register constraints, return the matching register name
3028 // In case the constraint is 'r' we need to return Expression
3032 // Default value if there is no constraint for the register
3038 void getTargetDefines(const LangOptions &Opts,
3039 MacroBuilder &Builder) const override;
3040 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
3042 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
3044 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
3046 void setFeatureEnabled(llvm::StringMap<bool> &Features,
3047 StringRef Name, bool Enabled) const override {
3048 setFeatureEnabledImpl(Features, Name, Enabled);
3050 // This exists purely to cut down on the number of virtual calls in
3051 // initFeatureMap which calls this repeatedly.
3052 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
3053 StringRef Name, bool Enabled);
3055 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
3057 const std::vector<std::string> &FeaturesVec) const override;
3058 bool hasFeature(StringRef Feature) const override;
3059 bool handleTargetFeatures(std::vector<std::string> &Features,
3060 DiagnosticsEngine &Diags) override;
3061 StringRef getABI() const override {
3062 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
3064 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
3066 if (getTriple().getArch() == llvm::Triple::x86 &&
3067 MMX3DNowLevel == NoMMX3DNow)
3071 bool setCPU(const std::string &Name) override {
3072 CPU = getCPUKind(Name);
3074 // Perform any per-CPU checks necessary to determine if this CPU is
3076 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
3077 // invalid without explaining *why*.
3080 // No processor selected!
3107 case CK_AthlonThunderbird:
3112 // Only accept certain architectures when compiling in 32-bit mode.
3113 if (getTriple().getArch() != llvm::Triple::x86)
3125 case CK_SandyBridge:
3129 case CK_SkylakeClient:
3130 case CK_SkylakeServer:
3134 case CK_Athlon64SSE3:
3139 case CK_OpteronSSE3:
3151 llvm_unreachable("Unhandled CPU kind");
3154 bool setFPMath(StringRef Name) override;
3156 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3157 // Most of the non-ARM calling conventions are i386 conventions.
3159 case CC_X86ThisCall:
3160 case CC_X86FastCall:
3162 case CC_X86VectorCall:
3167 case CC_IntelOclBicc:
3168 case CC_OpenCLKernel:
3171 return CCCR_Warning;
3175 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3176 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
3179 bool hasSjLjLowering() const override {
3183 void setSupportedOpenCLOpts() override {
3184 getSupportedOpenCLOpts().supportAll();
3188 bool X86TargetInfo::setFPMath(StringRef Name) {
3189 if (Name == "387") {
3193 if (Name == "sse") {
3200 bool X86TargetInfo::initFeatureMap(
3201 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
3202 const std::vector<std::string> &FeaturesVec) const {
3203 // FIXME: This *really* should not be here.
3204 // X86_64 always has SSE2.
3205 if (getTriple().getArch() == llvm::Triple::x86_64)
3206 setFeatureEnabledImpl(Features, "sse2", true);
3208 const CPUKind Kind = getCPUKind(CPU);
3210 // Enable X87 for all X86 processors but Lakemont.
3211 if (Kind != CK_Lakemont)
3212 setFeatureEnabledImpl(Features, "x87", true);
3228 setFeatureEnabledImpl(Features, "mmx", true);
3233 setFeatureEnabledImpl(Features, "sse", true);
3234 setFeatureEnabledImpl(Features, "fxsr", true);
3240 setFeatureEnabledImpl(Features, "sse2", true);
3241 setFeatureEnabledImpl(Features, "fxsr", true);
3246 setFeatureEnabledImpl(Features, "sse3", true);
3247 setFeatureEnabledImpl(Features, "fxsr", true);
3248 setFeatureEnabledImpl(Features, "cx16", true);
3251 setFeatureEnabledImpl(Features, "ssse3", true);
3252 setFeatureEnabledImpl(Features, "fxsr", true);
3253 setFeatureEnabledImpl(Features, "cx16", true);
3256 setFeatureEnabledImpl(Features, "sse4.1", true);
3257 setFeatureEnabledImpl(Features, "fxsr", true);
3258 setFeatureEnabledImpl(Features, "cx16", true);
3261 setFeatureEnabledImpl(Features, "avx512ifma", true);
3262 setFeatureEnabledImpl(Features, "avx512vbmi", true);
3263 setFeatureEnabledImpl(Features, "sha", true);
3265 case CK_SkylakeServer:
3266 setFeatureEnabledImpl(Features, "avx512f", true);
3267 setFeatureEnabledImpl(Features, "avx512cd", true);
3268 setFeatureEnabledImpl(Features, "avx512dq", true);
3269 setFeatureEnabledImpl(Features, "avx512bw", true);
3270 setFeatureEnabledImpl(Features, "avx512vl", true);
3271 setFeatureEnabledImpl(Features, "pku", true);
3272 setFeatureEnabledImpl(Features, "clwb", true);
3274 case CK_SkylakeClient:
3275 setFeatureEnabledImpl(Features, "xsavec", true);
3276 setFeatureEnabledImpl(Features, "xsaves", true);
3277 setFeatureEnabledImpl(Features, "mpx", true);
3278 setFeatureEnabledImpl(Features, "sgx", true);
3279 setFeatureEnabledImpl(Features, "clflushopt", true);
3280 setFeatureEnabledImpl(Features, "rtm", true);
3283 setFeatureEnabledImpl(Features, "rdseed", true);
3284 setFeatureEnabledImpl(Features, "adx", true);
3287 setFeatureEnabledImpl(Features, "avx2", true);
3288 setFeatureEnabledImpl(Features, "lzcnt", true);
3289 setFeatureEnabledImpl(Features, "bmi", true);
3290 setFeatureEnabledImpl(Features, "bmi2", true);
3291 setFeatureEnabledImpl(Features, "fma", true);
3292 setFeatureEnabledImpl(Features, "movbe", true);
3295 setFeatureEnabledImpl(Features, "rdrnd", true);
3296 setFeatureEnabledImpl(Features, "f16c", true);
3297 setFeatureEnabledImpl(Features, "fsgsbase", true);
3299 case CK_SandyBridge:
3300 setFeatureEnabledImpl(Features, "avx", true);
3301 setFeatureEnabledImpl(Features, "xsave", true);
3302 setFeatureEnabledImpl(Features, "xsaveopt", true);
3305 setFeatureEnabledImpl(Features, "aes", true);
3306 setFeatureEnabledImpl(Features, "pclmul", true);
3309 setFeatureEnabledImpl(Features, "sse4.2", true);
3310 setFeatureEnabledImpl(Features, "fxsr", true);
3311 setFeatureEnabledImpl(Features, "cx16", true);
3314 setFeatureEnabledImpl(Features, "sha", true);
3315 setFeatureEnabledImpl(Features, "rdrnd", true);
3316 setFeatureEnabledImpl(Features, "rdseed", true);
3317 setFeatureEnabledImpl(Features, "xsave", true);
3318 setFeatureEnabledImpl(Features, "xsaveopt", true);
3319 setFeatureEnabledImpl(Features, "xsavec", true);
3320 setFeatureEnabledImpl(Features, "xsaves", true);
3321 setFeatureEnabledImpl(Features, "clflushopt", true);
3322 setFeatureEnabledImpl(Features, "mpx", true);
3325 setFeatureEnabledImpl(Features, "aes", true);
3326 setFeatureEnabledImpl(Features, "pclmul", true);
3327 setFeatureEnabledImpl(Features, "sse4.2", true);
3330 setFeatureEnabledImpl(Features, "movbe", true);
3331 setFeatureEnabledImpl(Features, "ssse3", true);
3332 setFeatureEnabledImpl(Features, "fxsr", true);
3333 setFeatureEnabledImpl(Features, "cx16", true);
3336 setFeatureEnabledImpl(Features, "avx512f", true);
3337 setFeatureEnabledImpl(Features, "avx512cd", true);
3338 setFeatureEnabledImpl(Features, "avx512er", true);
3339 setFeatureEnabledImpl(Features, "avx512pf", true);
3340 setFeatureEnabledImpl(Features, "prefetchwt1", true);
3341 setFeatureEnabledImpl(Features, "fxsr", true);
3342 setFeatureEnabledImpl(Features, "rdseed", true);
3343 setFeatureEnabledImpl(Features, "adx", true);
3344 setFeatureEnabledImpl(Features, "lzcnt", true);
3345 setFeatureEnabledImpl(Features, "bmi", true);
3346 setFeatureEnabledImpl(Features, "bmi2", true);
3347 setFeatureEnabledImpl(Features, "rtm", true);
3348 setFeatureEnabledImpl(Features, "fma", true);
3349 setFeatureEnabledImpl(Features, "rdrnd", true);
3350 setFeatureEnabledImpl(Features, "f16c", true);
3351 setFeatureEnabledImpl(Features, "fsgsbase", true);
3352 setFeatureEnabledImpl(Features, "aes", true);
3353 setFeatureEnabledImpl(Features, "pclmul", true);
3354 setFeatureEnabledImpl(Features, "cx16", true);
3355 setFeatureEnabledImpl(Features, "xsaveopt", true);
3356 setFeatureEnabledImpl(Features, "xsave", true);
3357 setFeatureEnabledImpl(Features, "movbe", true);
3363 setFeatureEnabledImpl(Features, "3dnow", true);
3366 case CK_AthlonThunderbird:
3368 setFeatureEnabledImpl(Features, "3dnowa", true);
3373 setFeatureEnabledImpl(Features, "sse", true);
3374 setFeatureEnabledImpl(Features, "3dnowa", true);
3375 setFeatureEnabledImpl(Features, "fxsr", true);
3381 setFeatureEnabledImpl(Features, "sse2", true);
3382 setFeatureEnabledImpl(Features, "3dnowa", true);
3383 setFeatureEnabledImpl(Features, "fxsr", true);
3386 setFeatureEnabledImpl(Features, "sse4a", true);
3387 setFeatureEnabledImpl(Features, "lzcnt", true);
3388 setFeatureEnabledImpl(Features, "popcnt", true);
3391 case CK_OpteronSSE3:
3392 case CK_Athlon64SSE3:
3393 setFeatureEnabledImpl(Features, "sse3", true);
3394 setFeatureEnabledImpl(Features, "3dnowa", true);
3395 setFeatureEnabledImpl(Features, "fxsr", true);
3398 setFeatureEnabledImpl(Features, "avx", true);
3399 setFeatureEnabledImpl(Features, "aes", true);
3400 setFeatureEnabledImpl(Features, "pclmul", true);
3401 setFeatureEnabledImpl(Features, "bmi", true);
3402 setFeatureEnabledImpl(Features, "f16c", true);
3403 setFeatureEnabledImpl(Features, "xsaveopt", true);
3406 setFeatureEnabledImpl(Features, "ssse3", true);
3407 setFeatureEnabledImpl(Features, "sse4a", true);
3408 setFeatureEnabledImpl(Features, "lzcnt", true);
3409 setFeatureEnabledImpl(Features, "popcnt", true);
3410 setFeatureEnabledImpl(Features, "prfchw", true);
3411 setFeatureEnabledImpl(Features, "cx16", true);
3412 setFeatureEnabledImpl(Features, "fxsr", true);
3415 setFeatureEnabledImpl(Features, "adx", true);
3416 setFeatureEnabledImpl(Features, "aes", true);
3417 setFeatureEnabledImpl(Features, "avx2", true);
3418 setFeatureEnabledImpl(Features, "bmi", true);
3419 setFeatureEnabledImpl(Features, "bmi2", true);
3420 setFeatureEnabledImpl(Features, "clflushopt", true);
3421 setFeatureEnabledImpl(Features, "clzero", true);
3422 setFeatureEnabledImpl(Features, "cx16", true);
3423 setFeatureEnabledImpl(Features, "f16c", true);
3424 setFeatureEnabledImpl(Features, "fma", true);
3425 setFeatureEnabledImpl(Features, "fsgsbase", true);
3426 setFeatureEnabledImpl(Features, "fxsr", true);
3427 setFeatureEnabledImpl(Features, "lzcnt", true);
3428 setFeatureEnabledImpl(Features, "mwaitx", true);
3429 setFeatureEnabledImpl(Features, "movbe", true);
3430 setFeatureEnabledImpl(Features, "pclmul", true);
3431 setFeatureEnabledImpl(Features, "popcnt", true);
3432 setFeatureEnabledImpl(Features, "prfchw", true);
3433 setFeatureEnabledImpl(Features, "rdrnd", true);
3434 setFeatureEnabledImpl(Features, "rdseed", true);
3435 setFeatureEnabledImpl(Features, "sha", true);
3436 setFeatureEnabledImpl(Features, "sse4a", true);
3437 setFeatureEnabledImpl(Features, "xsave", true);
3438 setFeatureEnabledImpl(Features, "xsavec", true);
3439 setFeatureEnabledImpl(Features, "xsaveopt", true);
3440 setFeatureEnabledImpl(Features, "xsaves", true);
3443 setFeatureEnabledImpl(Features, "avx2", true);
3444 setFeatureEnabledImpl(Features, "bmi2", true);
3445 setFeatureEnabledImpl(Features, "mwaitx", true);
3448 setFeatureEnabledImpl(Features, "fsgsbase", true);
3449 setFeatureEnabledImpl(Features, "xsaveopt", true);
3452 setFeatureEnabledImpl(Features, "bmi", true);
3453 setFeatureEnabledImpl(Features, "fma", true);
3454 setFeatureEnabledImpl(Features, "f16c", true);
3455 setFeatureEnabledImpl(Features, "tbm", true);
3458 // xop implies avx, sse4a and fma4.
3459 setFeatureEnabledImpl(Features, "xop", true);
3460 setFeatureEnabledImpl(Features, "lwp", true);
3461 setFeatureEnabledImpl(Features, "lzcnt", true);
3462 setFeatureEnabledImpl(Features, "aes", true);
3463 setFeatureEnabledImpl(Features, "pclmul", true);
3464 setFeatureEnabledImpl(Features, "prfchw", true);
3465 setFeatureEnabledImpl(Features, "cx16", true);
3466 setFeatureEnabledImpl(Features, "fxsr", true);
3467 setFeatureEnabledImpl(Features, "xsave", true);
3470 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
3473 // Can't do this earlier because we need to be able to explicitly enable
3474 // or disable these features and the things that they depend upon.
3476 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
3477 auto I = Features.find("sse4.2");
3478 if (I != Features.end() && I->getValue() &&
3479 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
3481 Features["popcnt"] = true;
3483 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
3484 I = Features.find("3dnow");
3485 if (I != Features.end() && I->getValue() &&
3486 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
3488 Features["prfchw"] = true;
3490 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
3492 I = Features.find("sse");
3493 if (I != Features.end() && I->getValue() &&
3494 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
3496 Features["mmx"] = true;
3501 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
3502 X86SSEEnum Level, bool Enabled) {
3506 Features["avx512f"] = true;
3509 Features["avx2"] = true;
3512 Features["avx"] = true;
3513 Features["xsave"] = true;
3516 Features["sse4.2"] = true;
3519 Features["sse4.1"] = true;
3522 Features["ssse3"] = true;
3525 Features["sse3"] = true;
3528 Features["sse2"] = true;
3531 Features["sse"] = true;
3542 Features["sse"] = false;
3545 Features["sse2"] = Features["pclmul"] = Features["aes"] =
3546 Features["sha"] = false;
3549 Features["sse3"] = false;
3550 setXOPLevel(Features, NoXOP, false);
3553 Features["ssse3"] = false;
3556 Features["sse4.1"] = false;
3559 Features["sse4.2"] = false;
3562 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
3563 Features["xsaveopt"] = false;
3564 setXOPLevel(Features, FMA4, false);
3567 Features["avx2"] = false;
3570 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
3571 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
3572 Features["avx512vl"] = Features["avx512vbmi"] =
3573 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false;
3578 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
3579 MMX3DNowEnum Level, bool Enabled) {
3582 case AMD3DNowAthlon:
3583 Features["3dnowa"] = true;
3586 Features["3dnow"] = true;
3589 Features["mmx"] = true;
3600 Features["mmx"] = false;
3603 Features["3dnow"] = false;
3605 case AMD3DNowAthlon:
3606 Features["3dnowa"] = false;
3611 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
3616 Features["xop"] = true;
3619 Features["fma4"] = true;
3620 setSSELevel(Features, AVX, true);
3623 Features["sse4a"] = true;
3624 setSSELevel(Features, SSE3, true);
3635 Features["sse4a"] = false;
3638 Features["fma4"] = false;
3641 Features["xop"] = false;
3646 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
3647 StringRef Name, bool Enabled) {
3648 // This is a bit of a hack to deal with the sse4 target feature when used
3649 // as part of the target attribute. We handle sse4 correctly everywhere
3650 // else. See below for more information on how we handle the sse4 options.
3652 Features[Name] = Enabled;
3654 if (Name == "mmx") {
3655 setMMXLevel(Features, MMX, Enabled);
3656 } else if (Name == "sse") {
3657 setSSELevel(Features, SSE1, Enabled);
3658 } else if (Name == "sse2") {
3659 setSSELevel(Features, SSE2, Enabled);
3660 } else if (Name == "sse3") {
3661 setSSELevel(Features, SSE3, Enabled);
3662 } else if (Name == "ssse3") {
3663 setSSELevel(Features, SSSE3, Enabled);
3664 } else if (Name == "sse4.2") {
3665 setSSELevel(Features, SSE42, Enabled);
3666 } else if (Name == "sse4.1") {
3667 setSSELevel(Features, SSE41, Enabled);
3668 } else if (Name == "3dnow") {
3669 setMMXLevel(Features, AMD3DNow, Enabled);
3670 } else if (Name == "3dnowa") {
3671 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
3672 } else if (Name == "aes") {
3674 setSSELevel(Features, SSE2, Enabled);
3675 } else if (Name == "pclmul") {
3677 setSSELevel(Features, SSE2, Enabled);
3678 } else if (Name == "avx") {
3679 setSSELevel(Features, AVX, Enabled);
3680 } else if (Name == "avx2") {
3681 setSSELevel(Features, AVX2, Enabled);
3682 } else if (Name == "avx512f") {
3683 setSSELevel(Features, AVX512F, Enabled);
3684 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
3685 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
3686 Name == "avx512vbmi" || Name == "avx512ifma" ||
3687 Name == "avx512vpopcntdq") {
3689 setSSELevel(Features, AVX512F, Enabled);
3690 // Enable BWI instruction if VBMI is being enabled.
3691 if (Name == "avx512vbmi" && Enabled)
3692 Features["avx512bw"] = true;
3693 // Also disable VBMI if BWI is being disabled.
3694 if (Name == "avx512bw" && !Enabled)
3695 Features["avx512vbmi"] = false;
3696 } else if (Name == "fma") {
3698 setSSELevel(Features, AVX, Enabled);
3699 } else if (Name == "fma4") {
3700 setXOPLevel(Features, FMA4, Enabled);
3701 } else if (Name == "xop") {
3702 setXOPLevel(Features, XOP, Enabled);
3703 } else if (Name == "sse4a") {
3704 setXOPLevel(Features, SSE4A, Enabled);
3705 } else if (Name == "f16c") {
3707 setSSELevel(Features, AVX, Enabled);
3708 } else if (Name == "sha") {
3710 setSSELevel(Features, SSE2, Enabled);
3711 } else if (Name == "sse4") {
3712 // We can get here via the __target__ attribute since that's not controlled
3713 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
3714 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
3717 setSSELevel(Features, SSE42, Enabled);
3719 setSSELevel(Features, SSE41, Enabled);
3720 } else if (Name == "xsave") {
3722 Features["xsaveopt"] = false;
3723 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
3725 Features["xsave"] = true;
3729 /// handleTargetFeatures - Perform initialization based on the user
3730 /// configured set of features.
3731 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
3732 DiagnosticsEngine &Diags) {
3733 for (const auto &Feature : Features) {
3734 if (Feature[0] != '+')
3737 if (Feature == "+aes") {
3739 } else if (Feature == "+pclmul") {
3741 } else if (Feature == "+lzcnt") {
3743 } else if (Feature == "+rdrnd") {
3745 } else if (Feature == "+fsgsbase") {
3747 } else if (Feature == "+bmi") {
3749 } else if (Feature == "+bmi2") {
3751 } else if (Feature == "+popcnt") {
3753 } else if (Feature == "+rtm") {
3755 } else if (Feature == "+prfchw") {
3757 } else if (Feature == "+rdseed") {
3759 } else if (Feature == "+adx") {
3761 } else if (Feature == "+tbm") {
3763 } else if (Feature == "+lwp") {
3765 } else if (Feature == "+fma") {
3767 } else if (Feature == "+f16c") {
3769 } else if (Feature == "+avx512cd") {
3771 } else if (Feature == "+avx512vpopcntdq") {
3772 HasAVX512VPOPCNTDQ = true;
3773 } else if (Feature == "+avx512er") {
3775 } else if (Feature == "+avx512pf") {
3777 } else if (Feature == "+avx512dq") {
3779 } else if (Feature == "+avx512bw") {
3781 } else if (Feature == "+avx512vl") {
3783 } else if (Feature == "+avx512vbmi") {
3784 HasAVX512VBMI = true;
3785 } else if (Feature == "+avx512ifma") {
3786 HasAVX512IFMA = true;
3787 } else if (Feature == "+sha") {
3789 } else if (Feature == "+mpx") {
3791 } else if (Feature == "+movbe") {
3793 } else if (Feature == "+sgx") {
3795 } else if (Feature == "+cx16") {
3797 } else if (Feature == "+fxsr") {
3799 } else if (Feature == "+xsave") {
3801 } else if (Feature == "+xsaveopt") {
3803 } else if (Feature == "+xsavec") {
3805 } else if (Feature == "+xsaves") {
3807 } else if (Feature == "+mwaitx") {
3809 } else if (Feature == "+pku") {
3811 } else if (Feature == "+clflushopt") {
3812 HasCLFLUSHOPT = true;
3813 } else if (Feature == "+clwb") {
3815 } else if (Feature == "+prefetchwt1") {
3816 HasPREFETCHWT1 = true;
3817 } else if (Feature == "+clzero") {
3821 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
3822 .Case("+avx512f", AVX512F)
3823 .Case("+avx2", AVX2)
3825 .Case("+sse4.2", SSE42)
3826 .Case("+sse4.1", SSE41)
3827 .Case("+ssse3", SSSE3)
3828 .Case("+sse3", SSE3)
3829 .Case("+sse2", SSE2)
3832 SSELevel = std::max(SSELevel, Level);
3834 MMX3DNowEnum ThreeDNowLevel =
3835 llvm::StringSwitch<MMX3DNowEnum>(Feature)
3836 .Case("+3dnowa", AMD3DNowAthlon)
3837 .Case("+3dnow", AMD3DNow)
3839 .Default(NoMMX3DNow);
3840 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
3842 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
3844 .Case("+fma4", FMA4)
3845 .Case("+sse4a", SSE4A)
3847 XOPLevel = std::max(XOPLevel, XLevel);
3850 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
3851 // matches the selected sse level.
3852 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
3853 (FPMath == FP_387 && SSELevel >= SSE1)) {
3854 Diags.Report(diag::err_target_unsupported_fpmath) <<
3855 (FPMath == FP_SSE ? "sse" : "387");
3860 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3864 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
3865 /// definitions for this particular subtarget.
3866 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
3867 MacroBuilder &Builder) const {
3868 // Target identification.
3869 if (getTriple().getArch() == llvm::Triple::x86_64) {
3870 Builder.defineMacro("__amd64__");
3871 Builder.defineMacro("__amd64");
3872 Builder.defineMacro("__x86_64");
3873 Builder.defineMacro("__x86_64__");
3874 if (getTriple().getArchName() == "x86_64h") {
3875 Builder.defineMacro("__x86_64h");
3876 Builder.defineMacro("__x86_64h__");
3879 DefineStd(Builder, "i386", Opts);
3882 // Subtarget options.
3883 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
3884 // truly should be based on -mtune options.
3889 // The rest are coming from the i386 define above.
3890 Builder.defineMacro("__tune_i386__");
3896 defineCPUMacros(Builder, "i486");
3899 Builder.defineMacro("__pentium_mmx__");
3900 Builder.defineMacro("__tune_pentium_mmx__");
3904 defineCPUMacros(Builder, "i586");
3905 defineCPUMacros(Builder, "pentium");
3910 Builder.defineMacro("__tune_pentium3__");
3914 Builder.defineMacro("__tune_pentium2__");
3917 Builder.defineMacro("__tune_i686__");
3918 Builder.defineMacro("__tune_pentiumpro__");
3921 Builder.defineMacro("__i686");
3922 Builder.defineMacro("__i686__");
3923 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3924 Builder.defineMacro("__pentiumpro");
3925 Builder.defineMacro("__pentiumpro__");
3929 defineCPUMacros(Builder, "pentium4");
3934 defineCPUMacros(Builder, "nocona");
3938 defineCPUMacros(Builder, "core2");
3941 defineCPUMacros(Builder, "atom");
3944 defineCPUMacros(Builder, "slm");
3947 defineCPUMacros(Builder, "goldmont");
3951 case CK_SandyBridge:
3955 case CK_SkylakeClient:
3956 // FIXME: Historically, we defined this legacy name, it would be nice to
3957 // remove it at some point. We've never exposed fine-grained names for
3958 // recent primary x86 CPUs, and we should keep it that way.
3959 defineCPUMacros(Builder, "corei7");
3961 case CK_SkylakeServer:
3962 defineCPUMacros(Builder, "skx");
3967 defineCPUMacros(Builder, "knl");
3970 Builder.defineMacro("__tune_lakemont__");
3973 Builder.defineMacro("__k6_2__");
3974 Builder.defineMacro("__tune_k6_2__");
3977 if (CPU != CK_K6_2) { // In case of fallthrough
3978 // FIXME: GCC may be enabling these in cases where some other k6
3979 // architecture is specified but -m3dnow is explicitly provided. The
3980 // exact semantics need to be determined and emulated here.
3981 Builder.defineMacro("__k6_3__");
3982 Builder.defineMacro("__tune_k6_3__");
3986 defineCPUMacros(Builder, "k6");
3989 case CK_AthlonThunderbird:
3993 defineCPUMacros(Builder, "athlon");
3994 if (SSELevel != NoSSE) {
3995 Builder.defineMacro("__athlon_sse__");
3996 Builder.defineMacro("__tune_athlon_sse__");
4003 case CK_OpteronSSE3:
4005 case CK_Athlon64SSE3:
4007 defineCPUMacros(Builder, "k8");
4010 defineCPUMacros(Builder, "amdfam10");
4013 defineCPUMacros(Builder, "btver1");
4016 defineCPUMacros(Builder, "btver2");
4019 defineCPUMacros(Builder, "bdver1");
4022 defineCPUMacros(Builder, "bdver2");
4025 defineCPUMacros(Builder, "bdver3");
4028 defineCPUMacros(Builder, "bdver4");
4031 defineCPUMacros(Builder, "znver1");
4034 defineCPUMacros(Builder, "geode");
4038 // Target properties.
4039 Builder.defineMacro("__REGISTER_PREFIX__", "");
4041 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
4042 // functions in glibc header files that use FP Stack inline asm which the
4043 // backend can't deal with (PR879).
4044 Builder.defineMacro("__NO_MATH_INLINES");
4047 Builder.defineMacro("__AES__");
4050 Builder.defineMacro("__PCLMUL__");
4053 Builder.defineMacro("__LZCNT__");
4056 Builder.defineMacro("__RDRND__");
4059 Builder.defineMacro("__FSGSBASE__");
4062 Builder.defineMacro("__BMI__");
4065 Builder.defineMacro("__BMI2__");
4068 Builder.defineMacro("__POPCNT__");
4071 Builder.defineMacro("__RTM__");
4074 Builder.defineMacro("__PRFCHW__");
4077 Builder.defineMacro("__RDSEED__");
4080 Builder.defineMacro("__ADX__");
4083 Builder.defineMacro("__TBM__");
4086 Builder.defineMacro("__LWP__");
4089 Builder.defineMacro("__MWAITX__");
4093 Builder.defineMacro("__XOP__");
4096 Builder.defineMacro("__FMA4__");
4099 Builder.defineMacro("__SSE4A__");
4106 Builder.defineMacro("__FMA__");
4109 Builder.defineMacro("__F16C__");
4112 Builder.defineMacro("__AVX512CD__");
4113 if (HasAVX512VPOPCNTDQ)
4114 Builder.defineMacro("__AVX512VPOPCNTDQ__");
4116 Builder.defineMacro("__AVX512ER__");
4118 Builder.defineMacro("__AVX512PF__");
4120 Builder.defineMacro("__AVX512DQ__");
4122 Builder.defineMacro("__AVX512BW__");
4124 Builder.defineMacro("__AVX512VL__");
4126 Builder.defineMacro("__AVX512VBMI__");
4128 Builder.defineMacro("__AVX512IFMA__");
4131 Builder.defineMacro("__SHA__");
4134 Builder.defineMacro("__FXSR__");
4136 Builder.defineMacro("__XSAVE__");
4138 Builder.defineMacro("__XSAVEOPT__");
4140 Builder.defineMacro("__XSAVEC__");
4142 Builder.defineMacro("__XSAVES__");
4144 Builder.defineMacro("__PKU__");
4146 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
4148 Builder.defineMacro("__CLFLUSHOPT__");
4150 Builder.defineMacro("__CLWB__");
4152 Builder.defineMacro("__MPX__");
4154 Builder.defineMacro("__SGX__");
4156 Builder.defineMacro("__PREFETCHWT1__");
4158 Builder.defineMacro("__CLZERO__");
4160 // Each case falls through to the previous one here.
4163 Builder.defineMacro("__AVX512F__");
4166 Builder.defineMacro("__AVX2__");
4169 Builder.defineMacro("__AVX__");
4172 Builder.defineMacro("__SSE4_2__");
4175 Builder.defineMacro("__SSE4_1__");
4178 Builder.defineMacro("__SSSE3__");
4181 Builder.defineMacro("__SSE3__");
4184 Builder.defineMacro("__SSE2__");
4185 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
4188 Builder.defineMacro("__SSE__");
4189 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
4195 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
4205 Builder.defineMacro("_M_IX86_FP", Twine(2));
4208 Builder.defineMacro("_M_IX86_FP", Twine(1));
4211 Builder.defineMacro("_M_IX86_FP", Twine(0));
4216 // Each case falls through to the previous one here.
4217 switch (MMX3DNowLevel) {
4218 case AMD3DNowAthlon:
4219 Builder.defineMacro("__3dNOW_A__");
4222 Builder.defineMacro("__3dNOW__");
4225 Builder.defineMacro("__MMX__");
4231 if (CPU >= CK_i486) {
4232 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4233 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4234 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4237 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4240 Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
4243 bool X86TargetInfo::hasFeature(StringRef Feature) const {
4244 return llvm::StringSwitch<bool>(Feature)
4245 .Case("aes", HasAES)
4246 .Case("avx", SSELevel >= AVX)
4247 .Case("avx2", SSELevel >= AVX2)
4248 .Case("avx512f", SSELevel >= AVX512F)
4249 .Case("avx512cd", HasAVX512CD)
4250 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
4251 .Case("avx512er", HasAVX512ER)
4252 .Case("avx512pf", HasAVX512PF)
4253 .Case("avx512dq", HasAVX512DQ)
4254 .Case("avx512bw", HasAVX512BW)
4255 .Case("avx512vl", HasAVX512VL)
4256 .Case("avx512vbmi", HasAVX512VBMI)
4257 .Case("avx512ifma", HasAVX512IFMA)
4258 .Case("bmi", HasBMI)
4259 .Case("bmi2", HasBMI2)
4260 .Case("clflushopt", HasCLFLUSHOPT)
4261 .Case("clwb", HasCLWB)
4262 .Case("clzero", HasCLZERO)
4263 .Case("cx16", HasCX16)
4264 .Case("f16c", HasF16C)
4265 .Case("fma", HasFMA)
4266 .Case("fma4", XOPLevel >= FMA4)
4267 .Case("fsgsbase", HasFSGSBASE)
4268 .Case("fxsr", HasFXSR)
4269 .Case("lzcnt", HasLZCNT)
4270 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
4271 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
4272 .Case("mmx", MMX3DNowLevel >= MMX)
4273 .Case("movbe", HasMOVBE)
4274 .Case("mpx", HasMPX)
4275 .Case("pclmul", HasPCLMUL)
4276 .Case("pku", HasPKU)
4277 .Case("popcnt", HasPOPCNT)
4278 .Case("prefetchwt1", HasPREFETCHWT1)
4279 .Case("prfchw", HasPRFCHW)
4280 .Case("rdrnd", HasRDRND)
4281 .Case("rdseed", HasRDSEED)
4282 .Case("rtm", HasRTM)
4283 .Case("sgx", HasSGX)
4284 .Case("sha", HasSHA)
4285 .Case("sse", SSELevel >= SSE1)
4286 .Case("sse2", SSELevel >= SSE2)
4287 .Case("sse3", SSELevel >= SSE3)
4288 .Case("ssse3", SSELevel >= SSSE3)
4289 .Case("sse4.1", SSELevel >= SSE41)
4290 .Case("sse4.2", SSELevel >= SSE42)
4291 .Case("sse4a", XOPLevel >= SSE4A)
4292 .Case("tbm", HasTBM)
4293 .Case("lwp", HasLWP)
4295 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
4296 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
4297 .Case("xop", XOPLevel >= XOP)
4298 .Case("xsave", HasXSAVE)
4299 .Case("xsavec", HasXSAVEC)
4300 .Case("xsaves", HasXSAVES)
4301 .Case("xsaveopt", HasXSAVEOPT)
4305 // We can't use a generic validation scheme for the features accepted here
4306 // versus subtarget features accepted in the target attribute because the
4307 // bitfield structure that's initialized in the runtime only supports the
4308 // below currently rather than the full range of subtarget features. (See
4309 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
4310 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
4311 return llvm::StringSwitch<bool>(FeatureStr)
4314 .Case("popcnt", true)
4318 .Case("ssse3", true)
4319 .Case("sse4.1", true)
4320 .Case("sse4.2", true)
4323 .Case("sse4a", true)
4327 .Case("avx512f", true)
4331 .Case("pclmul", true)
4332 .Case("avx512vl", true)
4333 .Case("avx512bw", true)
4334 .Case("avx512dq", true)
4335 .Case("avx512cd", true)
4336 .Case("avx512vpopcntdq", true)
4337 .Case("avx512er", true)
4338 .Case("avx512pf", true)
4339 .Case("avx512vbmi", true)
4340 .Case("avx512ifma", true)
4345 X86TargetInfo::validateAsmConstraint(const char *&Name,
4346 TargetInfo::ConstraintInfo &Info) const {
4348 default: return false;
4349 // Constant constraints.
4350 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
4352 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
4353 // x86_64 instructions.
4355 Info.setRequiresImmediate();
4358 Info.setRequiresImmediate(0, 31);
4361 Info.setRequiresImmediate(0, 63);
4364 Info.setRequiresImmediate(-128, 127);
4367 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) });
4370 Info.setRequiresImmediate(0, 3);
4373 Info.setRequiresImmediate(0, 255);
4376 Info.setRequiresImmediate(0, 127);
4378 // Register constraints.
4379 case 'Y': // 'Y' is the first character for several 2-character constraints.
4380 // Shift the pointer to the second character of the constraint.
4385 case '0': // First SSE register.
4386 case 't': // Any SSE register, when SSE2 is enabled.
4387 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
4388 case 'm': // Any MMX register, when inter-unit moves enabled.
4389 case 'k': // AVX512 arch mask registers: k1-k7.
4390 Info.setAllowsRegister();
4393 case 'f': // Any x87 floating point stack register.
4394 // Constraint 'f' cannot be used for output operands.
4395 if (Info.ConstraintStr[0] == '=')
4397 Info.setAllowsRegister();
4405 case 'A': // edx:eax.
4406 case 't': // Top of floating point stack.
4407 case 'u': // Second from top of floating point stack.
4408 case 'q': // Any register accessible as [r]l: a, b, c, and d.
4409 case 'y': // Any MMX register.
4410 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
4411 case 'x': // Any SSE register.
4412 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0
4413 // for intermideate k reg operations).
4414 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
4415 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
4416 case 'l': // "Index" registers: any general register that can be used as an
4417 // index in a base+index memory access.
4418 Info.setAllowsRegister();
4420 // Floating point constant constraints.
4421 case 'C': // SSE floating point constant.
4422 case 'G': // x87 floating point constant.
4427 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
4428 unsigned Size) const {
4429 // Strip off constraint modifiers.
4430 while (Constraint[0] == '=' ||
4431 Constraint[0] == '+' ||
4432 Constraint[0] == '&')
4433 Constraint = Constraint.substr(1);
4435 return validateOperandSize(Constraint, Size);
4438 bool X86TargetInfo::validateInputSize(StringRef Constraint,
4439 unsigned Size) const {
4440 return validateOperandSize(Constraint, Size);
4443 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
4444 unsigned Size) const {
4445 switch (Constraint[0]) {
4448 // Registers k0-k7 (AVX512) size limit is 64 bit.
4457 if (SSELevel >= AVX512F)
4458 // 512-bit zmm registers can be used if target supports AVX512F.
4459 return Size <= 512U;
4460 else if (SSELevel >= AVX)
4461 // 256-bit ymm registers can be used if target supports AVX.
4462 return Size <= 256U;
4463 return Size <= 128U;
4465 // 'Y' is the first character for several 2-character constraints.
4466 switch (Constraint[1]) {
4469 // 'Ym' is synonymous with 'y'.
4474 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
4475 if (SSELevel >= AVX512F)
4476 return Size <= 512U;
4477 else if (SSELevel >= AVX)
4478 return Size <= 256U;
4479 return SSELevel >= SSE2 && Size <= 128U;
4488 X86TargetInfo::convertConstraint(const char *&Constraint) const {
4489 switch (*Constraint) {
4490 case 'a': return std::string("{ax}");
4491 case 'b': return std::string("{bx}");
4492 case 'c': return std::string("{cx}");
4493 case 'd': return std::string("{dx}");
4494 case 'S': return std::string("{si}");
4495 case 'D': return std::string("{di}");
4496 case 'p': // address
4497 return std::string("im");
4498 case 't': // top of floating point stack.
4499 return std::string("{st}");
4500 case 'u': // second from top of floating point stack.
4501 return std::string("{st(1)}"); // second from top of floating point stack.
4503 switch (Constraint[1]) {
4505 // Break from inner switch and fall through (copy single char),
4506 // continue parsing after copying the current constraint into
4507 // the return string.
4510 // "^" hints llvm that this is a 2 letter constraint.
4511 // "Constraint++" is used to promote the string iterator
4512 // to the next constraint.
4513 return std::string("^") + std::string(Constraint++, 2);
4517 return std::string(1, *Constraint);
4521 // X86-32 generic target
4522 class X86_32TargetInfo : public X86TargetInfo {
4524 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4525 : X86TargetInfo(Triple, Opts) {
4526 DoubleAlign = LongLongAlign = 32;
4527 LongDoubleWidth = 96;
4528 LongDoubleAlign = 32;
4529 SuitableAlign = 128;
4530 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128");
4531 SizeType = UnsignedInt;
4532 PtrDiffType = SignedInt;
4533 IntPtrType = SignedInt;
4536 // Use fpret for all types.
4537 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
4538 (1 << TargetInfo::Double) |
4539 (1 << TargetInfo::LongDouble));
4541 // x86-32 has atomics up to 8 bytes
4542 // FIXME: Check that we actually have cmpxchg8b before setting
4543 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
4544 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4546 BuiltinVaListKind getBuiltinVaListKind() const override {
4547 return TargetInfo::CharPtrBuiltinVaList;
4550 int getEHDataRegisterNumber(unsigned RegNo) const override {
4551 if (RegNo == 0) return 0;
4552 if (RegNo == 1) return 2;
4555 bool validateOperandSize(StringRef Constraint,
4556 unsigned Size) const override {
4557 switch (Constraint[0]) {
4573 return X86TargetInfo::validateOperandSize(Constraint, Size);
4575 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4576 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
4577 Builtin::FirstTSBuiltin + 1);
4581 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
4583 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4584 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {}
4586 unsigned getFloatEvalMethod() const override {
4587 unsigned Major, Minor, Micro;
4588 getTriple().getOSVersion(Major, Minor, Micro);
4589 // New NetBSD uses the default rounding mode.
4590 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
4591 return X86_32TargetInfo::getFloatEvalMethod();
4592 // NetBSD before 6.99.26 defaults to "double" rounding.
4597 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
4599 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4600 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4601 SizeType = UnsignedLong;
4602 IntPtrType = SignedLong;
4603 PtrDiffType = SignedLong;
4607 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
4609 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4610 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4611 SizeType = UnsignedLong;
4612 IntPtrType = SignedLong;
4613 PtrDiffType = SignedLong;
4617 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
4619 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4620 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4621 LongDoubleWidth = 128;
4622 LongDoubleAlign = 128;
4623 SuitableAlign = 128;
4624 MaxVectorAlign = 256;
4625 // The watchOS simulator uses the builtin bool type for Objective-C.
4626 llvm::Triple T = llvm::Triple(Triple);
4628 UseSignedCharForObjCBool = false;
4629 SizeType = UnsignedLong;
4630 IntPtrType = SignedLong;
4631 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128");
4632 HasAlignMac68kSupport = true;
4635 bool handleTargetFeatures(std::vector<std::string> &Features,
4636 DiagnosticsEngine &Diags) override {
4637 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features,
4640 // We now know the features we have: we can decide how to align vectors.
4642 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4647 // x86-32 Windows target
4648 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
4650 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4651 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4652 WCharType = UnsignedShort;
4653 DoubleAlign = LongLongAlign = 64;
4655 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4656 resetDataLayout(IsWinCOFF
4657 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
4658 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4660 void getTargetDefines(const LangOptions &Opts,
4661 MacroBuilder &Builder) const override {
4662 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4666 // x86-32 Windows Visual Studio target
4667 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
4669 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple,
4670 const TargetOptions &Opts)
4671 : WindowsX86_32TargetInfo(Triple, Opts) {
4672 LongDoubleWidth = LongDoubleAlign = 64;
4673 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4675 void getTargetDefines(const LangOptions &Opts,
4676 MacroBuilder &Builder) const override {
4677 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4678 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
4679 // The value of the following reflects processor type.
4680 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
4681 // We lost the original triple, so we use the default.
4682 Builder.defineMacro("_M_IX86", "600");
4686 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4687 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang
4688 // supports __declspec natively under -fms-extensions, but we define a no-op
4689 // __declspec macro anyway for pre-processor compatibility.
4690 if (Opts.MicrosoftExt)
4691 Builder.defineMacro("__declspec", "__declspec");
4693 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
4695 if (!Opts.MicrosoftExt) {
4696 // Provide macros for all the calling convention keywords. Provide both
4697 // single and double underscore prefixed variants. These are available on
4698 // x64 as well as x86, even though they have no effect.
4699 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
4700 for (const char *CC : CCs) {
4701 std::string GCCSpelling = "__attribute__((__";
4703 GCCSpelling += "__))";
4704 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
4705 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
4710 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4711 Builder.defineMacro("__MSVCRT__");
4712 Builder.defineMacro("__MINGW32__");
4713 addCygMingDefines(Opts, Builder);
4716 // x86-32 MinGW target
4717 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
4719 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4720 : WindowsX86_32TargetInfo(Triple, Opts) {
4723 void getTargetDefines(const LangOptions &Opts,
4724 MacroBuilder &Builder) const override {
4725 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4726 DefineStd(Builder, "WIN32", Opts);
4727 DefineStd(Builder, "WINNT", Opts);
4728 Builder.defineMacro("_X86_");
4729 addMinGWDefines(Opts, Builder);
4733 // x86-32 Cygwin target
4734 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
4736 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4737 : X86_32TargetInfo(Triple, Opts) {
4738 WCharType = UnsignedShort;
4739 DoubleAlign = LongLongAlign = 64;
4740 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4742 void getTargetDefines(const LangOptions &Opts,
4743 MacroBuilder &Builder) const override {
4744 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4745 Builder.defineMacro("_X86_");
4746 Builder.defineMacro("__CYGWIN__");
4747 Builder.defineMacro("__CYGWIN32__");
4748 addCygMingDefines(Opts, Builder);
4749 DefineStd(Builder, "unix", Opts);
4751 Builder.defineMacro("_GNU_SOURCE");
4755 // x86-32 Haiku target
4756 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> {
4758 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4759 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4761 void getTargetDefines(const LangOptions &Opts,
4762 MacroBuilder &Builder) const override {
4763 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4764 Builder.defineMacro("__INTEL__");
4768 // X86-32 MCU target
4769 class MCUX86_32TargetInfo : public X86_32TargetInfo {
4771 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4772 : X86_32TargetInfo(Triple, Opts) {
4773 LongDoubleWidth = 64;
4774 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4775 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32");
4776 WIntType = UnsignedInt;
4779 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4780 // On MCU we support only C calling convention.
4781 return CC == CC_C ? CCCR_OK : CCCR_Warning;
4784 void getTargetDefines(const LangOptions &Opts,
4785 MacroBuilder &Builder) const override {
4786 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4787 Builder.defineMacro("__iamcu");
4788 Builder.defineMacro("__iamcu__");
4791 bool allowsLargerPreferedTypeAlignment() const override {
4797 template<typename Target>
4798 class RTEMSTargetInfo : public OSTargetInfo<Target> {
4800 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4801 MacroBuilder &Builder) const override {
4802 // RTEMS defines; list based off of gcc output
4804 Builder.defineMacro("__rtems__");
4805 Builder.defineMacro("__ELF__");
4809 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4810 : OSTargetInfo<Target>(Triple, Opts) {
4811 switch (Triple.getArch()) {
4813 case llvm::Triple::x86:
4814 // this->MCountName = ".mcount";
4816 case llvm::Triple::mips:
4817 case llvm::Triple::mipsel:
4818 case llvm::Triple::ppc:
4819 case llvm::Triple::ppc64:
4820 case llvm::Triple::ppc64le:
4821 // this->MCountName = "_mcount";
4823 case llvm::Triple::arm:
4824 // this->MCountName = "__mcount";
4830 // x86-32 RTEMS target
4831 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
4833 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4834 : X86_32TargetInfo(Triple, Opts) {
4835 SizeType = UnsignedLong;
4836 IntPtrType = SignedLong;
4837 PtrDiffType = SignedLong;
4839 void getTargetDefines(const LangOptions &Opts,
4840 MacroBuilder &Builder) const override {
4841 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4842 Builder.defineMacro("__INTEL__");
4843 Builder.defineMacro("__rtems__");
4847 // x86-64 generic target
4848 class X86_64TargetInfo : public X86TargetInfo {
4850 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4851 : X86TargetInfo(Triple, Opts) {
4852 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
4854 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4855 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
4856 LongDoubleWidth = 128;
4857 LongDoubleAlign = 128;
4858 LargeArrayMinWidth = 128;
4859 LargeArrayAlign = 128;
4860 SuitableAlign = 128;
4861 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
4862 PtrDiffType = IsX32 ? SignedInt : SignedLong;
4863 IntPtrType = IsX32 ? SignedInt : SignedLong;
4864 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
4865 Int64Type = IsX32 ? SignedLongLong : SignedLong;
4868 // Pointers are 32-bit in x32.
4869 resetDataLayout(IsX32
4870 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
4871 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
4872 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128");
4874 // Use fpret only for long double.
4875 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
4877 // Use fp2ret for _Complex long double.
4878 ComplexLongDoubleUsesFP2Ret = true;
4880 // Make __builtin_ms_va_list available.
4881 HasBuiltinMSVaList = true;
4883 // x86-64 has atomics up to 16 bytes.
4884 MaxAtomicPromoteWidth = 128;
4885 MaxAtomicInlineWidth = 128;
4887 BuiltinVaListKind getBuiltinVaListKind() const override {
4888 return TargetInfo::X86_64ABIBuiltinVaList;
4891 int getEHDataRegisterNumber(unsigned RegNo) const override {
4892 if (RegNo == 0) return 0;
4893 if (RegNo == 1) return 1;
4897 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4901 case CC_X86VectorCall:
4902 case CC_IntelOclBicc:
4903 case CC_X86_64Win64:
4904 case CC_PreserveMost:
4905 case CC_PreserveAll:
4907 case CC_OpenCLKernel:
4910 return CCCR_Warning;
4914 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
4918 // for x32 we need it here explicitly
4919 bool hasInt128Type() const override { return true; }
4920 unsigned getUnwindWordWidth() const override { return 64; }
4921 unsigned getRegisterWidth() const override { return 64; }
4923 bool validateGlobalRegisterVariable(StringRef RegName,
4925 bool &HasSizeMismatch) const override {
4926 // rsp and rbp are the only 64-bit registers the x86 backend can currently
4928 if (RegName.equals("rsp") || RegName.equals("rbp")) {
4929 // Check that the register size is 64-bit.
4930 HasSizeMismatch = RegSize != 64;
4934 // Check if the register is a 32-bit register the backend can handle.
4935 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize,
4938 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4939 return llvm::makeArrayRef(BuiltinInfoX86,
4940 X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
4944 // x86-64 Windows target
4945 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
4947 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4948 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4949 WCharType = UnsignedShort;
4950 LongWidth = LongAlign = 32;
4951 DoubleAlign = LongLongAlign = 64;
4952 IntMaxType = SignedLongLong;
4953 Int64Type = SignedLongLong;
4954 SizeType = UnsignedLongLong;
4955 PtrDiffType = SignedLongLong;
4956 IntPtrType = SignedLongLong;
4959 void getTargetDefines(const LangOptions &Opts,
4960 MacroBuilder &Builder) const override {
4961 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
4962 Builder.defineMacro("_WIN64");
4965 BuiltinVaListKind getBuiltinVaListKind() const override {
4966 return TargetInfo::CharPtrBuiltinVaList;
4969 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4972 case CC_X86ThisCall:
4973 case CC_X86FastCall:
4976 case CC_X86VectorCall:
4977 case CC_IntelOclBicc:
4981 case CC_OpenCLKernel:
4984 return CCCR_Warning;
4989 // x86-64 Windows Visual Studio target
4990 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
4992 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple,
4993 const TargetOptions &Opts)
4994 : WindowsX86_64TargetInfo(Triple, Opts) {
4995 LongDoubleWidth = LongDoubleAlign = 64;
4996 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4998 void getTargetDefines(const LangOptions &Opts,
4999 MacroBuilder &Builder) const override {
5000 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
5001 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
5002 Builder.defineMacro("_M_X64", "100");
5003 Builder.defineMacro("_M_AMD64", "100");
5007 // x86-64 MinGW target
5008 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
5010 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5011 : WindowsX86_64TargetInfo(Triple, Opts) {
5012 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
5013 // with x86 FP ops. Weird.
5014 LongDoubleWidth = LongDoubleAlign = 128;
5015 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
5019 void getTargetDefines(const LangOptions &Opts,
5020 MacroBuilder &Builder) const override {
5021 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
5022 DefineStd(Builder, "WIN64", Opts);
5023 Builder.defineMacro("__MINGW64__");
5024 addMinGWDefines(Opts, Builder);
5026 // GCC defines this macro when it is using __gxx_personality_seh0.
5027 if (!Opts.SjLjExceptions)
5028 Builder.defineMacro("__SEH__");
5032 // x86-64 Cygwin target
5033 class CygwinX86_64TargetInfo : public X86_64TargetInfo {
5035 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5036 : X86_64TargetInfo(Triple, Opts) {
5037 TLSSupported = false;
5038 WCharType = UnsignedShort;
5040 void getTargetDefines(const LangOptions &Opts,
5041 MacroBuilder &Builder) const override {
5042 X86_64TargetInfo::getTargetDefines(Opts, Builder);
5043 Builder.defineMacro("__x86_64__");
5044 Builder.defineMacro("__CYGWIN__");
5045 Builder.defineMacro("__CYGWIN64__");
5046 addCygMingDefines(Opts, Builder);
5047 DefineStd(Builder, "unix", Opts);
5049 Builder.defineMacro("_GNU_SOURCE");
5051 // GCC defines this macro when it is using __gxx_personality_seh0.
5052 if (!Opts.SjLjExceptions)
5053 Builder.defineMacro("__SEH__");
5057 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
5059 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5060 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) {
5061 Int64Type = SignedLongLong;
5062 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
5063 llvm::Triple T = llvm::Triple(Triple);
5065 UseSignedCharForObjCBool = false;
5066 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128");
5069 bool handleTargetFeatures(std::vector<std::string> &Features,
5070 DiagnosticsEngine &Diags) override {
5071 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features,
5074 // We now know the features we have: we can decide how to align vectors.
5076 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
5081 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
5083 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5084 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) {
5085 IntMaxType = SignedLongLong;
5086 Int64Type = SignedLongLong;
5090 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
5092 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5093 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) {
5094 IntMaxType = SignedLongLong;
5095 Int64Type = SignedLongLong;
5099 class ARMTargetInfo : public TargetInfo {
5100 // Possible FPU choices.
5109 // Possible HWDiv features.
5111 HWDivThumb = (1 << 0),
5115 static bool FPUModeIsVFP(FPUMode Mode) {
5116 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
5119 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5120 static const char * const GCCRegNames[];
5122 std::string ABI, CPU;
5124 StringRef CPUProfile;
5134 unsigned ArchKind = llvm::ARM::AK_ARMV4T;
5135 unsigned ArchProfile;
5136 unsigned ArchVersion;
5140 unsigned IsAAPCS : 1;
5143 // Initialized via features.
5144 unsigned SoftFloat : 1;
5145 unsigned SoftFloatABI : 1;
5148 unsigned Crypto : 1;
5150 unsigned Unaligned : 1;
5153 LDREX_B = (1 << 0), /// byte (8-bit)
5154 LDREX_H = (1 << 1), /// half (16-bit)
5155 LDREX_W = (1 << 2), /// word (32-bit)
5156 LDREX_D = (1 << 3), /// double (64-bit)
5161 // ACLE 6.5.1 Hardware floating point
5163 HW_FP_HP = (1 << 1), /// half (16-bit)
5164 HW_FP_SP = (1 << 2), /// single (32-bit)
5165 HW_FP_DP = (1 << 3), /// double (64-bit)
5169 static const Builtin::Info BuiltinInfo[];
5171 void setABIAAPCS() {
5174 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
5175 const llvm::Triple &T = getTriple();
5177 // size_t is unsigned long on MachO-derived environments, NetBSD,
5178 // OpenBSD and Bitrig.
5179 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
5180 T.getOS() == llvm::Triple::OpenBSD ||
5181 T.getOS() == llvm::Triple::Bitrig)
5182 SizeType = UnsignedLong;
5184 SizeType = UnsignedInt;
5186 switch (T.getOS()) {
5187 case llvm::Triple::NetBSD:
5188 case llvm::Triple::OpenBSD:
5189 WCharType = SignedInt;
5191 case llvm::Triple::Win32:
5192 WCharType = UnsignedShort;
5194 case llvm::Triple::Linux:
5196 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
5197 WCharType = UnsignedInt;
5201 UseBitFieldTypeAlignment = true;
5203 ZeroLengthBitfieldBoundary = 0;
5205 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
5206 // so set preferred for small types to 32.
5207 if (T.isOSBinFormatMachO()) {
5208 resetDataLayout(BigEndian
5209 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
5210 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
5211 } else if (T.isOSWindows()) {
5212 assert(!BigEndian && "Windows on ARM does not support big endian");
5221 } else if (T.isOSNaCl()) {
5222 assert(!BigEndian && "NaCl on ARM does not support big endian");
5223 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128");
5225 resetDataLayout(BigEndian
5226 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
5227 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
5230 // FIXME: Enumerated types are variable width in straight AAPCS.
5233 void setABIAPCS(bool IsAAPCS16) {
5234 const llvm::Triple &T = getTriple();
5239 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
5241 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
5243 // size_t is unsigned int on FreeBSD.
5244 if (T.getOS() == llvm::Triple::FreeBSD)
5245 SizeType = UnsignedInt;
5247 SizeType = UnsignedLong;
5249 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
5250 WCharType = SignedInt;
5252 // Do not respect the alignment of bit-field types when laying out
5253 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
5254 UseBitFieldTypeAlignment = false;
5256 /// gcc forces the alignment to 4 bytes, regardless of the type of the
5257 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
5259 ZeroLengthBitfieldBoundary = 32;
5261 if (T.isOSBinFormatMachO() && IsAAPCS16) {
5262 assert(!BigEndian && "AAPCS16 does not support big-endian");
5263 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128");
5264 } else if (T.isOSBinFormatMachO())
5267 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
5268 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
5272 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
5273 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
5275 // FIXME: Override "preferred align" for double and long long.
5278 void setArchInfo() {
5279 StringRef ArchName = getTriple().getArchName();
5281 ArchISA = llvm::ARM::parseArchISA(ArchName);
5282 CPU = llvm::ARM::getDefaultCPU(ArchName);
5283 unsigned AK = llvm::ARM::parseArch(ArchName);
5284 if (AK != llvm::ARM::AK_INVALID)
5286 setArchInfo(ArchKind);
5289 void setArchInfo(unsigned Kind) {
5292 // cache TargetParser info
5294 SubArch = llvm::ARM::getSubArch(ArchKind);
5295 ArchProfile = llvm::ARM::parseArchProfile(SubArch);
5296 ArchVersion = llvm::ARM::parseArchVersion(SubArch);
5298 // cache CPU related strings
5299 CPUAttr = getCPUAttr();
5300 CPUProfile = getCPUProfile();
5304 // when triple does not specify a sub arch,
5305 // then we are not using inline atomics
5306 bool ShouldUseInlineAtomic =
5307 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) ||
5308 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
5309 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
5310 if (ArchProfile == llvm::ARM::PK_M) {
5311 MaxAtomicPromoteWidth = 32;
5312 if (ShouldUseInlineAtomic)
5313 MaxAtomicInlineWidth = 32;
5316 MaxAtomicPromoteWidth = 64;
5317 if (ShouldUseInlineAtomic)
5318 MaxAtomicInlineWidth = 64;
5322 bool isThumb() const {
5323 return (ArchISA == llvm::ARM::IK_THUMB);
5326 bool supportsThumb() const {
5327 return CPUAttr.count('T') || ArchVersion >= 6;
5330 bool supportsThumb2() const {
5331 return CPUAttr.equals("6T2") ||
5332 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE"));
5335 StringRef getCPUAttr() const {
5336 // For most sub-arches, the build attribute CPU name is enough.
5337 // For Cortex variants, it's slightly different.
5340 return llvm::ARM::getCPUAttr(ArchKind);
5341 case llvm::ARM::AK_ARMV6M:
5343 case llvm::ARM::AK_ARMV7S:
5345 case llvm::ARM::AK_ARMV7A:
5347 case llvm::ARM::AK_ARMV7R:
5349 case llvm::ARM::AK_ARMV7M:
5351 case llvm::ARM::AK_ARMV7EM:
5353 case llvm::ARM::AK_ARMV7VE:
5355 case llvm::ARM::AK_ARMV8A:
5357 case llvm::ARM::AK_ARMV8_1A:
5359 case llvm::ARM::AK_ARMV8_2A:
5361 case llvm::ARM::AK_ARMV8MBaseline:
5363 case llvm::ARM::AK_ARMV8MMainline:
5365 case llvm::ARM::AK_ARMV8R:
5370 StringRef getCPUProfile() const {
5371 switch(ArchProfile) {
5372 case llvm::ARM::PK_A:
5374 case llvm::ARM::PK_R:
5376 case llvm::ARM::PK_M:
5384 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5385 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0),
5388 switch (getTriple().getOS()) {
5389 case llvm::Triple::NetBSD:
5390 case llvm::Triple::OpenBSD:
5391 PtrDiffType = SignedLong;
5394 PtrDiffType = SignedInt;
5398 // Cache arch related info.
5401 // {} in inline assembly are neon specifiers, not assembly variant
5403 NoAsmVariants = true;
5405 // FIXME: This duplicates code from the driver that sets the -target-abi
5406 // option - this code is used if -target-abi isn't passed and should
5407 // be unified in some way.
5408 if (Triple.isOSBinFormatMachO()) {
5409 // The backend is hardwired to assume AAPCS for M-class processors, ensure
5410 // the frontend matches that.
5411 if (Triple.getEnvironment() == llvm::Triple::EABI ||
5412 Triple.getOS() == llvm::Triple::UnknownOS ||
5413 ArchProfile == llvm::ARM::PK_M) {
5415 } else if (Triple.isWatchABI()) {
5420 } else if (Triple.isOSWindows()) {
5421 // FIXME: this is invalid for WindowsCE
5424 // Select the default based on the platform.
5425 switch (Triple.getEnvironment()) {
5426 case llvm::Triple::Android:
5427 case llvm::Triple::GNUEABI:
5428 case llvm::Triple::GNUEABIHF:
5429 case llvm::Triple::MuslEABI:
5430 case llvm::Triple::MuslEABIHF:
5431 setABI("aapcs-linux");
5433 case llvm::Triple::EABIHF:
5434 case llvm::Triple::EABI:
5437 case llvm::Triple::GNU:
5441 if (Triple.getOS() == llvm::Triple::NetBSD)
5443 else if (Triple.getOS() == llvm::Triple::OpenBSD)
5444 setABI("aapcs-linux");
5451 // ARM targets default to using the ARM C++ ABI.
5452 TheCXXABI.set(TargetCXXABI::GenericARM);
5454 // ARM has atomics up to 8 bytes
5457 // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS)
5458 if (IsAAPCS && (Triple.getEnvironment() != llvm::Triple::Android))
5459 MaxVectorAlign = 64;
5461 // Do force alignment of members that follow zero length bitfields. If
5462 // the alignment of the zero-length bitfield is greater than the member
5463 // that follows it, `bar', `bar' will be aligned as the type of the
5464 // zero length bitfield.
5465 UseZeroLengthBitfieldAlignment = true;
5467 if (Triple.getOS() == llvm::Triple::Linux ||
5468 Triple.getOS() == llvm::Triple::UnknownOS)
5470 Opts.EABIVersion == llvm::EABI::GNU ? "\01__gnu_mcount_nc" : "\01mcount";
5473 StringRef getABI() const override { return ABI; }
5475 bool setABI(const std::string &Name) override {
5478 // The defaults (above) are for AAPCS, check if we need to change them.
5480 // FIXME: We need support for -meabi... we could just mangle it into the
5482 if (Name == "apcs-gnu" || Name == "aapcs16") {
5483 setABIAPCS(Name == "aapcs16");
5486 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
5493 // FIXME: This should be based on Arch attributes, not CPU names.
5495 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
5497 const std::vector<std::string> &FeaturesVec) const override {
5499 std::vector<StringRef> TargetFeatures;
5500 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName());
5502 // get default FPU features
5503 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
5504 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
5506 // get default Extension features
5507 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
5508 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
5510 for (auto Feature : TargetFeatures)
5511 if (Feature[0] == '+')
5512 Features[Feature.drop_front(1)] = true;
5514 // Enable or disable thumb-mode explicitly per function to enable mixed
5515 // ARM and Thumb code generation.
5517 Features["thumb-mode"] = true;
5519 Features["thumb-mode"] = false;
5521 // Convert user-provided arm and thumb GNU target attributes to
5522 // [-|+]thumb-mode target features respectively.
5523 std::vector<std::string> UpdatedFeaturesVec(FeaturesVec);
5524 for (auto &Feature : UpdatedFeaturesVec) {
5525 if (Feature.compare("+arm") == 0)
5526 Feature = "-thumb-mode";
5527 else if (Feature.compare("+thumb") == 0)
5528 Feature = "+thumb-mode";
5531 return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec);
5534 bool handleTargetFeatures(std::vector<std::string> &Features,
5535 DiagnosticsEngine &Diags) override {
5541 SoftFloat = SoftFloatABI = false;
5544 // This does not diagnose illegal cases like having both
5545 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
5546 uint32_t HW_FP_remove = 0;
5547 for (const auto &Feature : Features) {
5548 if (Feature == "+soft-float") {
5550 } else if (Feature == "+soft-float-abi") {
5551 SoftFloatABI = true;
5552 } else if (Feature == "+vfp2") {
5554 HW_FP |= HW_FP_SP | HW_FP_DP;
5555 } else if (Feature == "+vfp3") {
5557 HW_FP |= HW_FP_SP | HW_FP_DP;
5558 } else if (Feature == "+vfp4") {
5560 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
5561 } else if (Feature == "+fp-armv8") {
5563 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
5564 } else if (Feature == "+neon") {
5566 HW_FP |= HW_FP_SP | HW_FP_DP;
5567 } else if (Feature == "+hwdiv") {
5568 HWDiv |= HWDivThumb;
5569 } else if (Feature == "+hwdiv-arm") {
5571 } else if (Feature == "+crc") {
5573 } else if (Feature == "+crypto") {
5575 } else if (Feature == "+dsp") {
5577 } else if (Feature == "+fp-only-sp") {
5578 HW_FP_remove |= HW_FP_DP;
5579 } else if (Feature == "+strict-align") {
5581 } else if (Feature == "+fp16") {
5585 HW_FP &= ~HW_FP_remove;
5587 switch (ArchVersion) {
5589 if (ArchProfile == llvm::ARM::PK_M)
5591 else if (ArchKind == llvm::ARM::AK_ARMV6K)
5592 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5597 if (ArchProfile == llvm::ARM::PK_M)
5598 LDREX = LDREX_W | LDREX_H | LDREX_B ;
5600 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5603 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5606 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
5607 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
5611 if (FPMath == FP_Neon)
5612 Features.push_back("+neonfp");
5613 else if (FPMath == FP_VFP)
5614 Features.push_back("-neonfp");
5616 // Remove front-end specific options which the backend handles differently.
5618 std::find(Features.begin(), Features.end(), "+soft-float-abi");
5619 if (Feature != Features.end())
5620 Features.erase(Feature);
5625 bool hasFeature(StringRef Feature) const override {
5626 return llvm::StringSwitch<bool>(Feature)
5628 .Case("aarch32", true)
5629 .Case("softfloat", SoftFloat)
5630 .Case("thumb", isThumb())
5631 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
5632 .Case("vfp", FPU && !SoftFloat)
5633 .Case("hwdiv", HWDiv & HWDivThumb)
5634 .Case("hwdiv-arm", HWDiv & HWDivARM)
5638 bool setCPU(const std::string &Name) override {
5639 if (Name != "generic")
5640 setArchInfo(llvm::ARM::parseCPUArch(Name));
5642 if (ArchKind == llvm::ARM::AK_INVALID)
5649 bool setFPMath(StringRef Name) override;
5651 void getTargetDefinesARMV81A(const LangOptions &Opts,
5652 MacroBuilder &Builder) const {
5653 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
5656 void getTargetDefinesARMV82A(const LangOptions &Opts,
5657 MacroBuilder &Builder) const {
5658 // Also include the ARMv8.1-A defines
5659 getTargetDefinesARMV81A(Opts, Builder);
5662 void getTargetDefines(const LangOptions &Opts,
5663 MacroBuilder &Builder) const override {
5664 // Target identification.
5665 Builder.defineMacro("__arm");
5666 Builder.defineMacro("__arm__");
5667 // For bare-metal none-eabi.
5668 if (getTriple().getOS() == llvm::Triple::UnknownOS &&
5669 (getTriple().getEnvironment() == llvm::Triple::EABI ||
5670 getTriple().getEnvironment() == llvm::Triple::EABIHF))
5671 Builder.defineMacro("__ELF__");
5674 // Target properties.
5675 Builder.defineMacro("__REGISTER_PREFIX__", "");
5677 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
5678 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
5679 if (getTriple().isWatchABI())
5680 Builder.defineMacro("__ARM_ARCH_7K__", "2");
5682 if (!CPUAttr.empty())
5683 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
5685 // ACLE 6.4.1 ARM/Thumb instruction set architecture
5686 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
5687 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
5689 if (ArchVersion >= 8) {
5690 // ACLE 6.5.7 Crypto Extension
5692 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
5693 // ACLE 6.5.8 CRC32 Extension
5695 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
5696 // ACLE 6.5.10 Numeric Maximum and Minimum
5697 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
5698 // ACLE 6.5.9 Directed Rounding
5699 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
5702 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
5703 // is not defined for the M-profile.
5704 // NOTE that the default profile is assumed to be 'A'
5705 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M)
5706 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
5708 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original
5709 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the
5710 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all
5711 // v7 and v8 architectures excluding v8-M Baseline.
5712 if (supportsThumb2())
5713 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
5714 else if (supportsThumb())
5715 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
5717 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
5718 // instruction set such as ARM or Thumb.
5719 Builder.defineMacro("__ARM_32BIT_STATE", "1");
5721 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
5723 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
5724 if (!CPUProfile.empty())
5725 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
5727 // ACLE 6.4.3 Unaligned access supported in hardware
5729 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
5731 // ACLE 6.4.4 LDREX/STREX
5733 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX));
5736 if (ArchVersion == 5 ||
5737 (ArchVersion == 6 && CPUProfile != "M") ||
5739 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
5741 // ACLE 6.5.1 Hardware Floating Point
5743 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
5746 Builder.defineMacro("__ARM_ACLE", "200");
5748 // FP16 support (we currently only support IEEE format).
5749 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
5750 Builder.defineMacro("__ARM_FP16_ARGS", "1");
5752 // ACLE 6.5.3 Fused multiply-accumulate (FMA)
5753 if (ArchVersion >= 7 && (FPU & VFP4FPU))
5754 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
5756 // Subtarget options.
5758 // FIXME: It's more complicated than this and we don't really support
5760 // Windows on ARM does not "support" interworking
5761 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows())
5762 Builder.defineMacro("__THUMB_INTERWORK__");
5764 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
5765 // Embedded targets on Darwin follow AAPCS, but not EABI.
5766 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
5767 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows())
5768 Builder.defineMacro("__ARM_EABI__");
5769 Builder.defineMacro("__ARM_PCS", "1");
5772 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" ||
5774 Builder.defineMacro("__ARM_PCS_VFP", "1");
5777 Builder.defineMacro("__SOFTFP__");
5779 if (ArchKind == llvm::ARM::AK_XSCALE)
5780 Builder.defineMacro("__XSCALE__");
5783 Builder.defineMacro("__THUMBEL__");
5784 Builder.defineMacro("__thumb__");
5785 if (supportsThumb2())
5786 Builder.defineMacro("__thumb2__");
5789 // ACLE 6.4.9 32-bit SIMD instructions
5790 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
5791 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
5793 // ACLE 6.4.10 Hardware Integer Divide
5794 if (((HWDiv & HWDivThumb) && isThumb()) ||
5795 ((HWDiv & HWDivARM) && !isThumb())) {
5796 Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
5797 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
5800 // Note, this is always on in gcc, even though it doesn't make sense.
5801 Builder.defineMacro("__APCS_32__");
5803 if (FPUModeIsVFP((FPUMode) FPU)) {
5804 Builder.defineMacro("__VFP_FP__");
5806 Builder.defineMacro("__ARM_VFPV2__");
5808 Builder.defineMacro("__ARM_VFPV3__");
5810 Builder.defineMacro("__ARM_VFPV4__");
5812 Builder.defineMacro("__ARM_FPV5__");
5815 // This only gets set when Neon instructions are actually available, unlike
5816 // the VFP define, hence the soft float and arch check. This is subtly
5817 // different from gcc, we follow the intent which was that it should be set
5818 // when Neon instructions are actually available.
5819 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
5820 Builder.defineMacro("__ARM_NEON", "1");
5821 Builder.defineMacro("__ARM_NEON__");
5822 // current AArch32 NEON implementations do not support double-precision
5823 // floating-point even when it is present in VFP.
5824 Builder.defineMacro("__ARM_NEON_FP",
5825 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP));
5828 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
5829 Opts.ShortWChar ? "2" : "4");
5831 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5832 Opts.ShortEnums ? "1" : "4");
5834 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") {
5835 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
5836 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
5837 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
5838 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
5841 // ACLE 6.4.7 DSP instructions
5843 Builder.defineMacro("__ARM_FEATURE_DSP", "1");
5846 // ACLE 6.4.8 Saturation instructions
5848 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) {
5849 Builder.defineMacro("__ARM_FEATURE_SAT", "1");
5853 // ACLE 6.4.6 Q (saturation) flag
5855 Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
5857 if (Opts.UnsafeFPMath)
5858 Builder.defineMacro("__ARM_FP_FAST", "1");
5862 case llvm::ARM::AK_ARMV8_1A:
5863 getTargetDefinesARMV81A(Opts, Builder);
5865 case llvm::ARM::AK_ARMV8_2A:
5866 getTargetDefinesARMV82A(Opts, Builder);
5871 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5872 return llvm::makeArrayRef(BuiltinInfo,
5873 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin);
5875 bool isCLZForZeroUndef() const override { return false; }
5876 BuiltinVaListKind getBuiltinVaListKind() const override {
5878 ? AAPCSABIBuiltinVaList
5879 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList
5880 : TargetInfo::VoidPtrBuiltinVaList);
5882 ArrayRef<const char *> getGCCRegNames() const override;
5883 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5884 bool validateAsmConstraint(const char *&Name,
5885 TargetInfo::ConstraintInfo &Info) const override {
5890 case 't': // VFP Floating point register single precision
5891 case 'w': // VFP Floating point register double precision
5892 Info.setAllowsRegister();
5901 case 'Q': // A memory address that is a single base register.
5902 Info.setAllowsMemory();
5904 case 'U': // a memory reference...
5906 case 'q': // ...ARMV4 ldrsb
5907 case 'v': // ...VFP load/store (reg+constant offset)
5908 case 'y': // ...iWMMXt load/store
5909 case 't': // address valid for load/store opaque types wider
5911 case 'n': // valid address for Neon doubleword vector load/store
5912 case 'm': // valid address for Neon element and structure load/store
5913 case 's': // valid address for non-offset loads/stores of quad-word
5914 // values in four ARM registers
5915 Info.setAllowsMemory();
5922 std::string convertConstraint(const char *&Constraint) const override {
5924 switch (*Constraint) {
5925 case 'U': // Two-character constraint; add "^" hint for later parsing.
5926 R = std::string("^") + std::string(Constraint, 2);
5929 case 'p': // 'p' should be translated to 'r' by default.
5930 R = std::string("r");
5933 return std::string(1, *Constraint);
5938 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5939 std::string &SuggestedModifier) const override {
5940 bool isOutput = (Constraint[0] == '=');
5941 bool isInOut = (Constraint[0] == '+');
5943 // Strip off constraint modifiers.
5944 while (Constraint[0] == '=' ||
5945 Constraint[0] == '+' ||
5946 Constraint[0] == '&')
5947 Constraint = Constraint.substr(1);
5949 switch (Constraint[0]) {
5954 return (isInOut || isOutput || Size <= 64);
5956 // A register of size 32 cannot fit a vector type.
5964 const char *getClobbers() const override {
5965 // FIXME: Is this really right?
5969 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5974 case CC_OpenCLKernel:
5977 return CCCR_Warning;
5981 int getEHDataRegisterNumber(unsigned RegNo) const override {
5982 if (RegNo == 0) return 0;
5983 if (RegNo == 1) return 1;
5987 bool hasSjLjLowering() const override {
5992 bool ARMTargetInfo::setFPMath(StringRef Name) {
5993 if (Name == "neon") {
5996 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
6004 const char * const ARMTargetInfo::GCCRegNames[] = {
6005 // Integer registers
6006 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6007 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
6010 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
6011 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
6012 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
6013 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
6016 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
6017 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
6018 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
6019 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
6022 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
6023 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
6026 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
6027 return llvm::makeArrayRef(GCCRegNames);
6030 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
6040 { { "v6", "rfp" }, "r9" },
6041 { { "sl" }, "r10" },
6042 { { "fp" }, "r11" },
6043 { { "ip" }, "r12" },
6044 { { "r13" }, "sp" },
6045 { { "r14" }, "lr" },
6046 { { "r15" }, "pc" },
6047 // The S, D and Q registers overlap, but aren't really aliases; we
6048 // don't want to substitute one of these for a different-sized one.
6051 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
6052 return llvm::makeArrayRef(GCCRegAliases);
6055 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
6056 #define BUILTIN(ID, TYPE, ATTRS) \
6057 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6058 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6059 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6060 #include "clang/Basic/BuiltinsNEON.def"
6062 #define BUILTIN(ID, TYPE, ATTRS) \
6063 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6064 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \
6065 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr },
6066 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6067 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6068 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
6069 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
6070 #include "clang/Basic/BuiltinsARM.def"
6073 class ARMleTargetInfo : public ARMTargetInfo {
6075 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6076 : ARMTargetInfo(Triple, Opts) {}
6077 void getTargetDefines(const LangOptions &Opts,
6078 MacroBuilder &Builder) const override {
6079 Builder.defineMacro("__ARMEL__");
6080 ARMTargetInfo::getTargetDefines(Opts, Builder);
6084 class ARMbeTargetInfo : public ARMTargetInfo {
6086 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6087 : ARMTargetInfo(Triple, Opts) {}
6088 void getTargetDefines(const LangOptions &Opts,
6089 MacroBuilder &Builder) const override {
6090 Builder.defineMacro("__ARMEB__");
6091 Builder.defineMacro("__ARM_BIG_ENDIAN");
6092 ARMTargetInfo::getTargetDefines(Opts, Builder);
6096 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
6097 const llvm::Triple Triple;
6099 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6100 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
6101 WCharType = UnsignedShort;
6102 SizeType = UnsignedInt;
6104 void getVisualStudioDefines(const LangOptions &Opts,
6105 MacroBuilder &Builder) const {
6106 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
6108 // FIXME: this is invalid for WindowsCE
6109 Builder.defineMacro("_M_ARM_NT", "1");
6110 Builder.defineMacro("_M_ARMT", "_M_ARM");
6111 Builder.defineMacro("_M_THUMB", "_M_ARM");
6113 assert((Triple.getArch() == llvm::Triple::arm ||
6114 Triple.getArch() == llvm::Triple::thumb) &&
6115 "invalid architecture for Windows ARM target info");
6116 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
6117 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
6119 // TODO map the complete set of values
6120 // 31: VFPv3 40: VFPv4
6121 Builder.defineMacro("_M_ARM_FP", "31");
6123 BuiltinVaListKind getBuiltinVaListKind() const override {
6124 return TargetInfo::CharPtrBuiltinVaList;
6126 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6129 case CC_X86ThisCall:
6130 case CC_X86FastCall:
6131 case CC_X86VectorCall:
6134 case CC_OpenCLKernel:
6137 return CCCR_Warning;
6142 // Windows ARM + Itanium C++ ABI Target
6143 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
6145 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple,
6146 const TargetOptions &Opts)
6147 : WindowsARMTargetInfo(Triple, Opts) {
6148 TheCXXABI.set(TargetCXXABI::GenericARM);
6151 void getTargetDefines(const LangOptions &Opts,
6152 MacroBuilder &Builder) const override {
6153 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
6155 if (Opts.MSVCCompat)
6156 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
6160 // Windows ARM, MS (C++) ABI
6161 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
6163 MicrosoftARMleTargetInfo(const llvm::Triple &Triple,
6164 const TargetOptions &Opts)
6165 : WindowsARMTargetInfo(Triple, Opts) {
6166 TheCXXABI.set(TargetCXXABI::Microsoft);
6169 void getTargetDefines(const LangOptions &Opts,
6170 MacroBuilder &Builder) const override {
6171 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
6172 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
6177 class MinGWARMTargetInfo : public WindowsARMTargetInfo {
6179 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6180 : WindowsARMTargetInfo(Triple, Opts) {
6181 TheCXXABI.set(TargetCXXABI::GenericARM);
6184 void getTargetDefines(const LangOptions &Opts,
6185 MacroBuilder &Builder) const override {
6186 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
6187 DefineStd(Builder, "WIN32", Opts);
6188 DefineStd(Builder, "WINNT", Opts);
6189 Builder.defineMacro("_ARM_");
6190 addMinGWDefines(Opts, Builder);
6194 // ARM Cygwin target
6195 class CygwinARMTargetInfo : public ARMleTargetInfo {
6197 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6198 : ARMleTargetInfo(Triple, Opts) {
6199 TLSSupported = false;
6200 WCharType = UnsignedShort;
6201 DoubleAlign = LongLongAlign = 64;
6202 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
6204 void getTargetDefines(const LangOptions &Opts,
6205 MacroBuilder &Builder) const override {
6206 ARMleTargetInfo::getTargetDefines(Opts, Builder);
6207 Builder.defineMacro("_ARM_");
6208 Builder.defineMacro("__CYGWIN__");
6209 Builder.defineMacro("__CYGWIN32__");
6210 DefineStd(Builder, "unix", Opts);
6212 Builder.defineMacro("_GNU_SOURCE");
6216 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> {
6218 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
6219 MacroBuilder &Builder) const override {
6220 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
6224 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6225 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
6226 HasAlignMac68kSupport = true;
6227 // iOS always has 64-bit atomic instructions.
6228 // FIXME: This should be based off of the target features in
6230 MaxAtomicInlineWidth = 64;
6232 if (Triple.isWatchABI()) {
6233 // Darwin on iOS uses a variant of the ARM C++ ABI.
6234 TheCXXABI.set(TargetCXXABI::WatchOS);
6236 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that
6237 // size_t is long, it's a bit weird for it to be int.
6238 PtrDiffType = SignedLong;
6240 // BOOL should be a real boolean on the new ABI
6241 UseSignedCharForObjCBool = false;
6243 TheCXXABI.set(TargetCXXABI::iOS);
6247 class AArch64TargetInfo : public TargetInfo {
6248 virtual void setDataLayout() = 0;
6249 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6250 static const char *const GCCRegNames[];
6261 unsigned HasFullFP16;
6262 llvm::AArch64::ArchKind ArchKind;
6264 static const Builtin::Info BuiltinInfo[];
6269 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6270 : TargetInfo(Triple), ABI("aapcs") {
6271 if (getTriple().getOS() == llvm::Triple::NetBSD ||
6272 getTriple().getOS() == llvm::Triple::OpenBSD) {
6273 WCharType = SignedInt;
6275 // NetBSD apparently prefers consistency across ARM targets to consistency
6276 // across 64-bit targets.
6277 Int64Type = SignedLongLong;
6278 IntMaxType = SignedLongLong;
6280 WCharType = UnsignedInt;
6281 Int64Type = SignedLong;
6282 IntMaxType = SignedLong;
6285 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6286 MaxVectorAlign = 128;
6287 MaxAtomicInlineWidth = 128;
6288 MaxAtomicPromoteWidth = 128;
6290 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
6291 LongDoubleFormat = &llvm::APFloat::IEEEquad();
6293 // {} in inline assembly are neon specifiers, not assembly variant
6295 NoAsmVariants = true;
6297 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
6298 // contributes to the alignment of the containing aggregate in the same way
6299 // a plain (non bit-field) member of that type would, without exception for
6300 // zero-sized or anonymous bit-fields."
6301 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
6302 UseZeroLengthBitfieldAlignment = true;
6304 // AArch64 targets default to using the ARM C++ ABI.
6305 TheCXXABI.set(TargetCXXABI::GenericAArch64);
6307 if (Triple.getOS() == llvm::Triple::Linux)
6308 this->MCountName = "\01_mcount";
6309 else if (Triple.getOS() == llvm::Triple::UnknownOS)
6310 this->MCountName = Opts.EABIVersion == llvm::EABI::GNU ? "\01_mcount" : "mcount";
6313 StringRef getABI() const override { return ABI; }
6314 bool setABI(const std::string &Name) override {
6315 if (Name != "aapcs" && Name != "darwinpcs")
6322 bool setCPU(const std::string &Name) override {
6323 return Name == "generic" ||
6324 llvm::AArch64::parseCPUArch(Name) !=
6325 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID);
6328 void getTargetDefinesARMV81A(const LangOptions &Opts,
6329 MacroBuilder &Builder) const {
6330 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
6333 void getTargetDefinesARMV82A(const LangOptions &Opts,
6334 MacroBuilder &Builder) const {
6335 // Also include the ARMv8.1 defines
6336 getTargetDefinesARMV81A(Opts, Builder);
6339 void getTargetDefines(const LangOptions &Opts,
6340 MacroBuilder &Builder) const override {
6341 // Target identification.
6342 Builder.defineMacro("__aarch64__");
6343 // For bare-metal none-eabi.
6344 if (getTriple().getOS() == llvm::Triple::UnknownOS &&
6345 (getTriple().getEnvironment() == llvm::Triple::EABI ||
6346 getTriple().getEnvironment() == llvm::Triple::EABIHF))
6347 Builder.defineMacro("__ELF__");
6349 // Target properties.
6350 Builder.defineMacro("_LP64");
6351 Builder.defineMacro("__LP64__");
6353 // ACLE predefines. Many can only have one possible value on v8 AArch64.
6354 Builder.defineMacro("__ARM_ACLE", "200");
6355 Builder.defineMacro("__ARM_ARCH", "8");
6356 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
6358 Builder.defineMacro("__ARM_64BIT_STATE", "1");
6359 Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
6360 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
6362 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
6363 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
6364 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
6365 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
6366 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
6367 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
6368 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
6370 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
6372 // 0xe implies support for half, single and double precision operations.
6373 Builder.defineMacro("__ARM_FP", "0xE");
6375 // PCS specifies this for SysV variants, which is all we support. Other ABIs
6376 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
6377 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
6378 Builder.defineMacro("__ARM_FP16_ARGS", "1");
6380 if (Opts.UnsafeFPMath)
6381 Builder.defineMacro("__ARM_FP_FAST", "1");
6383 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
6385 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
6386 Opts.ShortEnums ? "1" : "4");
6388 if (FPU == NeonMode) {
6389 Builder.defineMacro("__ARM_NEON", "1");
6390 // 64-bit NEON supports half, single and double precision operations.
6391 Builder.defineMacro("__ARM_NEON_FP", "0xE");
6395 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
6398 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
6401 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
6405 case llvm::AArch64::ArchKind::AK_ARMV8_1A:
6406 getTargetDefinesARMV81A(Opts, Builder);
6408 case llvm::AArch64::ArchKind::AK_ARMV8_2A:
6409 getTargetDefinesARMV82A(Opts, Builder);
6413 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
6414 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
6415 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
6416 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
6417 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
6420 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6421 return llvm::makeArrayRef(BuiltinInfo,
6422 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin);
6425 bool hasFeature(StringRef Feature) const override {
6426 return Feature == "aarch64" ||
6427 Feature == "arm64" ||
6429 (Feature == "neon" && FPU == NeonMode);
6432 bool handleTargetFeatures(std::vector<std::string> &Features,
6433 DiagnosticsEngine &Diags) override {
6439 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8A;
6441 for (const auto &Feature : Features) {
6442 if (Feature == "+neon")
6444 if (Feature == "+crc")
6446 if (Feature == "+crypto")
6448 if (Feature == "+strict-align")
6450 if (Feature == "+v8.1a")
6451 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_1A;
6452 if (Feature == "+v8.2a")
6453 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_2A;
6454 if (Feature == "+fullfp16")
6463 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6467 case CC_PreserveMost:
6468 case CC_PreserveAll:
6469 case CC_OpenCLKernel:
6472 return CCCR_Warning;
6476 bool isCLZForZeroUndef() const override { return false; }
6478 BuiltinVaListKind getBuiltinVaListKind() const override {
6479 return TargetInfo::AArch64ABIBuiltinVaList;
6482 ArrayRef<const char *> getGCCRegNames() const override;
6483 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6485 bool validateAsmConstraint(const char *&Name,
6486 TargetInfo::ConstraintInfo &Info) const override {
6490 case 'w': // Floating point and SIMD registers (V0-V31)
6491 Info.setAllowsRegister();
6493 case 'I': // Constant that can be used with an ADD instruction
6494 case 'J': // Constant that can be used with a SUB instruction
6495 case 'K': // Constant that can be used with a 32-bit logical instruction
6496 case 'L': // Constant that can be used with a 64-bit logical instruction
6497 case 'M': // Constant that can be used as a 32-bit MOV immediate
6498 case 'N': // Constant that can be used as a 64-bit MOV immediate
6499 case 'Y': // Floating point constant zero
6500 case 'Z': // Integer constant zero
6502 case 'Q': // A memory reference with base register and no offset
6503 Info.setAllowsMemory();
6505 case 'S': // A symbolic address
6506 Info.setAllowsRegister();
6509 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
6510 // Utf: A memory address suitable for ldp/stp in TF mode.
6511 // Usa: An absolute symbolic address.
6512 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
6513 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
6514 case 'z': // Zero register, wzr or xzr
6515 Info.setAllowsRegister();
6517 case 'x': // Floating point and SIMD registers (V0-V15)
6518 Info.setAllowsRegister();
6525 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
6526 std::string &SuggestedModifier) const override {
6527 // Strip off constraint modifiers.
6528 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
6529 Constraint = Constraint.substr(1);
6531 switch (Constraint[0]) {
6539 // For now assume that the person knows what they're
6540 // doing with the modifier.
6543 // By default an 'r' constraint will be in the 'x'
6548 SuggestedModifier = "w";
6555 const char *getClobbers() const override { return ""; }
6557 int getEHDataRegisterNumber(unsigned RegNo) const override {
6566 const char *const AArch64TargetInfo::GCCRegNames[] = {
6567 // 32-bit Integer registers
6568 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
6569 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
6570 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
6572 // 64-bit Integer registers
6573 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
6574 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
6575 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
6577 // 32-bit floating point regsisters
6578 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
6579 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
6580 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
6582 // 64-bit floating point regsisters
6583 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
6584 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
6585 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
6588 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
6589 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
6590 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
6593 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
6594 return llvm::makeArrayRef(GCCRegNames);
6597 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
6598 { { "w31" }, "wsp" },
6599 { { "x29" }, "fp" },
6600 { { "x30" }, "lr" },
6601 { { "x31" }, "sp" },
6602 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
6603 // don't want to substitute one of these for a different-sized one.
6606 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
6607 return llvm::makeArrayRef(GCCRegAliases);
6610 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
6611 #define BUILTIN(ID, TYPE, ATTRS) \
6612 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6613 #include "clang/Basic/BuiltinsNEON.def"
6615 #define BUILTIN(ID, TYPE, ATTRS) \
6616 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6617 #include "clang/Basic/BuiltinsAArch64.def"
6620 class AArch64leTargetInfo : public AArch64TargetInfo {
6621 void setDataLayout() override {
6622 if (getTriple().isOSBinFormatMachO())
6623 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128");
6625 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6629 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6630 : AArch64TargetInfo(Triple, Opts) {
6632 void getTargetDefines(const LangOptions &Opts,
6633 MacroBuilder &Builder) const override {
6634 Builder.defineMacro("__AARCH64EL__");
6635 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6639 class MicrosoftARM64TargetInfo
6640 : public WindowsTargetInfo<AArch64leTargetInfo> {
6641 const llvm::Triple Triple;
6644 MicrosoftARM64TargetInfo(const llvm::Triple &Triple,
6645 const TargetOptions &Opts)
6646 : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) {
6647 WCharType = UnsignedShort;
6648 SizeType = UnsignedLongLong;
6649 TheCXXABI.set(TargetCXXABI::Microsoft);
6652 void setDataLayout() override {
6653 resetDataLayout("e-m:w-i64:64-i128:128-n32:64-S128");
6656 void getVisualStudioDefines(const LangOptions &Opts,
6657 MacroBuilder &Builder) const {
6658 WindowsTargetInfo<AArch64leTargetInfo>::getVisualStudioDefines(Opts,
6660 Builder.defineMacro("_WIN32", "1");
6661 Builder.defineMacro("_WIN64", "1");
6662 Builder.defineMacro("_M_ARM64", "1");
6665 void getTargetDefines(const LangOptions &Opts,
6666 MacroBuilder &Builder) const override {
6667 WindowsTargetInfo::getTargetDefines(Opts, Builder);
6668 getVisualStudioDefines(Opts, Builder);
6671 BuiltinVaListKind getBuiltinVaListKind() const override {
6672 return TargetInfo::CharPtrBuiltinVaList;
6676 class AArch64beTargetInfo : public AArch64TargetInfo {
6677 void setDataLayout() override {
6678 assert(!getTriple().isOSBinFormatMachO());
6679 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6683 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6684 : AArch64TargetInfo(Triple, Opts) {}
6685 void getTargetDefines(const LangOptions &Opts,
6686 MacroBuilder &Builder) const override {
6687 Builder.defineMacro("__AARCH64EB__");
6688 Builder.defineMacro("__AARCH_BIG_ENDIAN");
6689 Builder.defineMacro("__ARM_BIG_ENDIAN");
6690 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6694 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
6696 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
6697 MacroBuilder &Builder) const override {
6698 Builder.defineMacro("__AARCH64_SIMD__");
6699 Builder.defineMacro("__ARM64_ARCH_8__");
6700 Builder.defineMacro("__ARM_NEON__");
6701 Builder.defineMacro("__LITTLE_ENDIAN__");
6702 Builder.defineMacro("__REGISTER_PREFIX__", "");
6703 Builder.defineMacro("__arm64", "1");
6704 Builder.defineMacro("__arm64__", "1");
6706 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
6710 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6711 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
6712 Int64Type = SignedLongLong;
6713 WCharType = SignedInt;
6714 UseSignedCharForObjCBool = false;
6716 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
6717 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
6719 TheCXXABI.set(TargetCXXABI::iOS64);
6722 BuiltinVaListKind getBuiltinVaListKind() const override {
6723 return TargetInfo::CharPtrBuiltinVaList;
6727 // Hexagon abstract base class
6728 class HexagonTargetInfo : public TargetInfo {
6729 static const Builtin::Info BuiltinInfo[];
6730 static const char * const GCCRegNames[];
6731 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6733 bool HasHVX, HasHVXDouble;
6737 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6738 : TargetInfo(Triple) {
6739 // Specify the vector alignment explicitly. For v512x1, the calculated
6740 // alignment would be 512*alignment(i1), which is 512 bytes, instead of
6741 // the required minimum of 64 bytes.
6742 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-"
6743 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
6744 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048");
6745 SizeType = UnsignedInt;
6746 PtrDiffType = SignedInt;
6747 IntPtrType = SignedInt;
6749 // {} in inline assembly are packet specifiers, not assembly variant
6751 NoAsmVariants = true;
6753 LargeArrayMinWidth = 64;
6754 LargeArrayAlign = 64;
6755 UseBitFieldTypeAlignment = true;
6756 ZeroLengthBitfieldBoundary = 32;
6757 HasHVX = HasHVXDouble = false;
6758 UseLongCalls = false;
6761 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6762 return llvm::makeArrayRef(BuiltinInfo,
6763 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin);
6766 bool validateAsmConstraint(const char *&Name,
6767 TargetInfo::ConstraintInfo &Info) const override {
6772 Info.setAllowsRegister();
6777 // Relocatable constant.
6783 void getTargetDefines(const LangOptions &Opts,
6784 MacroBuilder &Builder) const override;
6786 bool isCLZForZeroUndef() const override { return false; }
6788 bool hasFeature(StringRef Feature) const override {
6789 return llvm::StringSwitch<bool>(Feature)
6790 .Case("hexagon", true)
6791 .Case("hvx", HasHVX)
6792 .Case("hvx-double", HasHVXDouble)
6793 .Case("long-calls", UseLongCalls)
6797 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6798 StringRef CPU, const std::vector<std::string> &FeaturesVec)
6801 bool handleTargetFeatures(std::vector<std::string> &Features,
6802 DiagnosticsEngine &Diags) override;
6804 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
6805 bool Enabled) const override;
6807 BuiltinVaListKind getBuiltinVaListKind() const override {
6808 return TargetInfo::CharPtrBuiltinVaList;
6810 ArrayRef<const char *> getGCCRegNames() const override;
6811 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6812 const char *getClobbers() const override {
6816 static const char *getHexagonCPUSuffix(StringRef Name) {
6817 return llvm::StringSwitch<const char*>(Name)
6818 .Case("hexagonv4", "4")
6819 .Case("hexagonv5", "5")
6820 .Case("hexagonv55", "55")
6821 .Case("hexagonv60", "60")
6822 .Case("hexagonv62", "62")
6826 bool setCPU(const std::string &Name) override {
6827 if (!getHexagonCPUSuffix(Name))
6833 int getEHDataRegisterNumber(unsigned RegNo) const override {
6834 return RegNo < 2 ? RegNo : -1;
6838 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
6839 MacroBuilder &Builder) const {
6840 Builder.defineMacro("__qdsp6__", "1");
6841 Builder.defineMacro("__hexagon__", "1");
6843 if (CPU == "hexagonv4") {
6844 Builder.defineMacro("__HEXAGON_V4__");
6845 Builder.defineMacro("__HEXAGON_ARCH__", "4");
6846 if (Opts.HexagonQdsp6Compat) {
6847 Builder.defineMacro("__QDSP6_V4__");
6848 Builder.defineMacro("__QDSP6_ARCH__", "4");
6850 } else if (CPU == "hexagonv5") {
6851 Builder.defineMacro("__HEXAGON_V5__");
6852 Builder.defineMacro("__HEXAGON_ARCH__", "5");
6853 if(Opts.HexagonQdsp6Compat) {
6854 Builder.defineMacro("__QDSP6_V5__");
6855 Builder.defineMacro("__QDSP6_ARCH__", "5");
6857 } else if (CPU == "hexagonv55") {
6858 Builder.defineMacro("__HEXAGON_V55__");
6859 Builder.defineMacro("__HEXAGON_ARCH__", "55");
6860 Builder.defineMacro("__QDSP6_V55__");
6861 Builder.defineMacro("__QDSP6_ARCH__", "55");
6862 } else if (CPU == "hexagonv60") {
6863 Builder.defineMacro("__HEXAGON_V60__");
6864 Builder.defineMacro("__HEXAGON_ARCH__", "60");
6865 Builder.defineMacro("__QDSP6_V60__");
6866 Builder.defineMacro("__QDSP6_ARCH__", "60");
6867 } else if (CPU == "hexagonv62") {
6868 Builder.defineMacro("__HEXAGON_V62__");
6869 Builder.defineMacro("__HEXAGON_ARCH__", "62");
6872 if (hasFeature("hvx")) {
6873 Builder.defineMacro("__HVX__");
6874 if (hasFeature("hvx-double"))
6875 Builder.defineMacro("__HVXDBL__");
6879 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features,
6880 DiagnosticsEngine &Diags, StringRef CPU,
6881 const std::vector<std::string> &FeaturesVec) const {
6882 // Default for v60: -hvx, -hvx-double.
6883 Features["hvx"] = false;
6884 Features["hvx-double"] = false;
6885 Features["long-calls"] = false;
6887 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6890 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
6891 DiagnosticsEngine &Diags) {
6892 for (auto &F : Features) {
6895 else if (F == "-hvx")
6896 HasHVX = HasHVXDouble = false;
6897 else if (F == "+hvx-double")
6898 HasHVX = HasHVXDouble = true;
6899 else if (F == "-hvx-double")
6900 HasHVXDouble = false;
6902 if (F == "+long-calls")
6903 UseLongCalls = true;
6904 else if (F == "-long-calls")
6905 UseLongCalls = false;
6910 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
6911 StringRef Name, bool Enabled) const {
6913 if (Name == "hvx-double")
6914 Features["hvx"] = true;
6917 Features["hvx-double"] = false;
6919 Features[Name] = Enabled;
6922 const char *const HexagonTargetInfo::GCCRegNames[] = {
6923 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6924 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6925 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6926 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
6927 "p0", "p1", "p2", "p3",
6928 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
6931 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const {
6932 return llvm::makeArrayRef(GCCRegNames);
6935 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
6936 { { "sp" }, "r29" },
6937 { { "fp" }, "r30" },
6938 { { "lr" }, "r31" },
6941 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const {
6942 return llvm::makeArrayRef(GCCRegAliases);
6946 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
6947 #define BUILTIN(ID, TYPE, ATTRS) \
6948 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6949 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6950 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6951 #include "clang/Basic/BuiltinsHexagon.def"
6954 class LanaiTargetInfo : public TargetInfo {
6955 // Class for Lanai (32-bit).
6956 // The CPU profiles supported by the Lanai backend
6962 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6963 static const char *const GCCRegNames[];
6966 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6967 : TargetInfo(Triple) {
6968 // Description string has to be kept in sync with backend.
6969 resetDataLayout("E" // Big endian
6970 "-m:e" // ELF name manging
6971 "-p:32:32" // 32 bit pointers, 32 bit aligned
6972 "-i64:64" // 64 bit integers, 64 bit aligned
6973 "-a:0:32" // 32 bit alignment of objects of aggregate type
6974 "-n32" // 32 bit native integer width
6975 "-S64" // 64 bit natural stack alignment
6978 // Setting RegParmMax equal to what mregparm was set to in the old
6982 // Set the default CPU to V11
6985 // Temporary approach to make everything at least word-aligned and allow for
6986 // safely casting between pointers with different alignment requirements.
6987 // TODO: Remove this when there are no more cast align warnings on the
6989 MinGlobalAlign = 32;
6992 void getTargetDefines(const LangOptions &Opts,
6993 MacroBuilder &Builder) const override {
6994 // Define __lanai__ when building for target lanai.
6995 Builder.defineMacro("__lanai__");
6997 // Set define for the CPU specified.
7000 Builder.defineMacro("__LANAI_V11__");
7003 llvm_unreachable("Unhandled target CPU");
7007 bool setCPU(const std::string &Name) override {
7008 CPU = llvm::StringSwitch<CPUKind>(Name)
7009 .Case("v11", CK_V11)
7012 return CPU != CK_NONE;
7015 bool hasFeature(StringRef Feature) const override {
7016 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false);
7019 ArrayRef<const char *> getGCCRegNames() const override;
7021 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
7023 BuiltinVaListKind getBuiltinVaListKind() const override {
7024 return TargetInfo::VoidPtrBuiltinVaList;
7027 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7029 bool validateAsmConstraint(const char *&Name,
7030 TargetInfo::ConstraintInfo &info) const override {
7034 const char *getClobbers() const override { return ""; }
7037 const char *const LanaiTargetInfo::GCCRegNames[] = {
7038 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
7039 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
7040 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
7042 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const {
7043 return llvm::makeArrayRef(GCCRegNames);
7046 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = {
7056 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const {
7057 return llvm::makeArrayRef(GCCRegAliases);
7060 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
7061 class SparcTargetInfo : public TargetInfo {
7062 static const TargetInfo::GCCRegAlias GCCRegAliases[];
7063 static const char * const GCCRegNames[];
7066 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7067 : TargetInfo(Triple), SoftFloat(false) {}
7069 int getEHDataRegisterNumber(unsigned RegNo) const override {
7070 if (RegNo == 0) return 24;
7071 if (RegNo == 1) return 25;
7075 bool handleTargetFeatures(std::vector<std::string> &Features,
7076 DiagnosticsEngine &Diags) override {
7077 // Check if software floating point is enabled
7078 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
7079 if (Feature != Features.end()) {
7084 void getTargetDefines(const LangOptions &Opts,
7085 MacroBuilder &Builder) const override {
7086 DefineStd(Builder, "sparc", Opts);
7087 Builder.defineMacro("__REGISTER_PREFIX__", "");
7090 Builder.defineMacro("SOFT_FLOAT", "1");
7093 bool hasFeature(StringRef Feature) const override {
7094 return llvm::StringSwitch<bool>(Feature)
7095 .Case("softfloat", SoftFloat)
7096 .Case("sparc", true)
7100 bool hasSjLjLowering() const override {
7104 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7105 // FIXME: Implement!
7108 BuiltinVaListKind getBuiltinVaListKind() const override {
7109 return TargetInfo::VoidPtrBuiltinVaList;
7111 ArrayRef<const char *> getGCCRegNames() const override;
7112 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
7113 bool validateAsmConstraint(const char *&Name,
7114 TargetInfo::ConstraintInfo &info) const override {
7115 // FIXME: Implement!
7117 case 'I': // Signed 13-bit constant
7119 case 'K': // 32-bit constant with the low 12 bits clear
7120 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
7121 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
7122 case 'N': // Same as 'K' but zext (required for SIMode)
7123 case 'O': // The constant 4096
7128 info.setAllowsRegister();
7133 const char *getClobbers() const override {
7134 // FIXME: Implement!
7138 // No Sparc V7 for now, the backend doesn't support it anyway.
7169 enum CPUGeneration {
7174 CPUGeneration getCPUGeneration(CPUKind Kind) const {
7182 case CK_SPARCLITE86X:
7189 case CK_LEON2_AT697E:
7190 case CK_LEON2_AT697F:
7192 case CK_LEON3_UT699:
7193 case CK_LEON3_GR712RC:
7195 case CK_LEON4_GR740:
7199 case CK_ULTRASPARC3:
7206 llvm_unreachable("Unexpected CPU kind");
7209 CPUKind getCPUKind(StringRef Name) const {
7210 return llvm::StringSwitch<CPUKind>(Name)
7212 .Case("supersparc", CK_SUPERSPARC)
7213 .Case("sparclite", CK_SPARCLITE)
7214 .Case("f934", CK_F934)
7215 .Case("hypersparc", CK_HYPERSPARC)
7216 .Case("sparclite86x", CK_SPARCLITE86X)
7217 .Case("sparclet", CK_SPARCLET)
7218 .Case("tsc701", CK_TSC701)
7220 .Case("ultrasparc", CK_ULTRASPARC)
7221 .Case("ultrasparc3", CK_ULTRASPARC3)
7222 .Case("niagara", CK_NIAGARA)
7223 .Case("niagara2", CK_NIAGARA2)
7224 .Case("niagara3", CK_NIAGARA3)
7225 .Case("niagara4", CK_NIAGARA4)
7226 .Case("ma2100", CK_MYRIAD2100)
7227 .Case("ma2150", CK_MYRIAD2150)
7228 .Case("ma2450", CK_MYRIAD2450)
7229 // FIXME: the myriad2[.n] spellings are obsolete,
7230 // but a grace period is needed to allow updating dependent builds.
7231 .Case("myriad2", CK_MYRIAD2100)
7232 .Case("myriad2.1", CK_MYRIAD2100)
7233 .Case("myriad2.2", CK_MYRIAD2150)
7234 .Case("leon2", CK_LEON2)
7235 .Case("at697e", CK_LEON2_AT697E)
7236 .Case("at697f", CK_LEON2_AT697F)
7237 .Case("leon3", CK_LEON3)
7238 .Case("ut699", CK_LEON3_UT699)
7239 .Case("gr712rc", CK_LEON3_GR712RC)
7240 .Case("leon4", CK_LEON4)
7241 .Case("gr740", CK_LEON4_GR740)
7242 .Default(CK_GENERIC);
7245 bool setCPU(const std::string &Name) override {
7246 CPU = getCPUKind(Name);
7247 return CPU != CK_GENERIC;
7251 const char * const SparcTargetInfo::GCCRegNames[] = {
7252 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7253 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7254 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
7255 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
7258 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
7259 return llvm::makeArrayRef(GCCRegNames);
7262 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
7273 { { "o2" }, "r10" },
7274 { { "o3" }, "r11" },
7275 { { "o4" }, "r12" },
7276 { { "o5" }, "r13" },
7277 { { "o6", "sp" }, "r14" },
7278 { { "o7" }, "r15" },
7279 { { "l0" }, "r16" },
7280 { { "l1" }, "r17" },
7281 { { "l2" }, "r18" },
7282 { { "l3" }, "r19" },
7283 { { "l4" }, "r20" },
7284 { { "l5" }, "r21" },
7285 { { "l6" }, "r22" },
7286 { { "l7" }, "r23" },
7287 { { "i0" }, "r24" },
7288 { { "i1" }, "r25" },
7289 { { "i2" }, "r26" },
7290 { { "i3" }, "r27" },
7291 { { "i4" }, "r28" },
7292 { { "i5" }, "r29" },
7293 { { "i6", "fp" }, "r30" },
7294 { { "i7" }, "r31" },
7297 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
7298 return llvm::makeArrayRef(GCCRegAliases);
7301 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
7302 class SparcV8TargetInfo : public SparcTargetInfo {
7304 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7305 : SparcTargetInfo(Triple, Opts) {
7306 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64");
7307 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
7308 switch (getTriple().getOS()) {
7310 SizeType = UnsignedInt;
7311 IntPtrType = SignedInt;
7312 PtrDiffType = SignedInt;
7314 case llvm::Triple::NetBSD:
7315 case llvm::Triple::OpenBSD:
7316 SizeType = UnsignedLong;
7317 IntPtrType = SignedLong;
7318 PtrDiffType = SignedLong;
7321 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops
7322 // on up to 64 bits.
7323 MaxAtomicPromoteWidth = 64;
7324 MaxAtomicInlineWidth = 32;
7327 void getTargetDefines(const LangOptions &Opts,
7328 MacroBuilder &Builder) const override {
7329 SparcTargetInfo::getTargetDefines(Opts, Builder);
7330 switch (getCPUGeneration(CPU)) {
7332 Builder.defineMacro("__sparcv8");
7333 if (getTriple().getOS() != llvm::Triple::Solaris)
7334 Builder.defineMacro("__sparcv8__");
7337 Builder.defineMacro("__sparcv9");
7338 if (getTriple().getOS() != llvm::Triple::Solaris) {
7339 Builder.defineMacro("__sparcv9__");
7340 Builder.defineMacro("__sparc_v9__");
7344 if (getTriple().getVendor() == llvm::Triple::Myriad) {
7345 std::string MyriadArchValue, Myriad2Value;
7346 Builder.defineMacro("__sparc_v8__");
7347 Builder.defineMacro("__leon__");
7350 MyriadArchValue = "__ma2150";
7354 MyriadArchValue = "__ma2450";
7358 MyriadArchValue = "__ma2100";
7362 Builder.defineMacro(MyriadArchValue, "1");
7363 Builder.defineMacro(MyriadArchValue+"__", "1");
7364 Builder.defineMacro("__myriad2__", Myriad2Value);
7365 Builder.defineMacro("__myriad2", Myriad2Value);
7369 bool hasSjLjLowering() const override {
7374 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
7375 class SparcV8elTargetInfo : public SparcV8TargetInfo {
7377 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7378 : SparcV8TargetInfo(Triple, Opts) {
7379 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64");
7383 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
7384 class SparcV9TargetInfo : public SparcTargetInfo {
7386 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7387 : SparcTargetInfo(Triple, Opts) {
7388 // FIXME: Support Sparc quad-precision long double?
7389 resetDataLayout("E-m:e-i64:64-n32:64-S128");
7390 // This is an LP64 platform.
7391 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7393 // OpenBSD uses long long for int64_t and intmax_t.
7394 if (getTriple().getOS() == llvm::Triple::OpenBSD)
7395 IntMaxType = SignedLongLong;
7397 IntMaxType = SignedLong;
7398 Int64Type = IntMaxType;
7400 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
7401 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
7402 LongDoubleWidth = 128;
7403 LongDoubleAlign = 128;
7404 LongDoubleFormat = &llvm::APFloat::IEEEquad();
7405 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7408 void getTargetDefines(const LangOptions &Opts,
7409 MacroBuilder &Builder) const override {
7410 SparcTargetInfo::getTargetDefines(Opts, Builder);
7411 Builder.defineMacro("__sparcv9");
7412 Builder.defineMacro("__arch64__");
7413 // Solaris doesn't need these variants, but the BSDs do.
7414 if (getTriple().getOS() != llvm::Triple::Solaris) {
7415 Builder.defineMacro("__sparc64__");
7416 Builder.defineMacro("__sparc_v9__");
7417 Builder.defineMacro("__sparcv9__");
7421 bool setCPU(const std::string &Name) override {
7422 if (!SparcTargetInfo::setCPU(Name))
7424 return getCPUGeneration(CPU) == CG_V9;
7428 class SystemZTargetInfo : public TargetInfo {
7429 static const Builtin::Info BuiltinInfo[];
7430 static const char *const GCCRegNames[];
7433 bool HasTransactionalExecution;
7437 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7438 : TargetInfo(Triple), CPU("z10"), ISARevision(8),
7439 HasTransactionalExecution(false), HasVector(false) {
7440 IntMaxType = SignedLong;
7441 Int64Type = SignedLong;
7442 TLSSupported = true;
7443 IntWidth = IntAlign = 32;
7444 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
7445 PointerWidth = PointerAlign = 64;
7446 LongDoubleWidth = 128;
7447 LongDoubleAlign = 64;
7448 LongDoubleFormat = &llvm::APFloat::IEEEquad();
7449 DefaultAlignForAttributeAligned = 64;
7450 MinGlobalAlign = 16;
7451 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64");
7452 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7454 void getTargetDefines(const LangOptions &Opts,
7455 MacroBuilder &Builder) const override {
7456 Builder.defineMacro("__s390__");
7457 Builder.defineMacro("__s390x__");
7458 Builder.defineMacro("__zarch__");
7459 Builder.defineMacro("__LONG_DOUBLE_128__");
7461 Builder.defineMacro("__ARCH__", Twine(ISARevision));
7463 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
7464 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
7465 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
7466 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
7468 if (HasTransactionalExecution)
7469 Builder.defineMacro("__HTM__");
7471 Builder.defineMacro("__VX__");
7473 Builder.defineMacro("__VEC__", "10301");
7475 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7476 return llvm::makeArrayRef(BuiltinInfo,
7477 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin);
7480 ArrayRef<const char *> getGCCRegNames() const override;
7481 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7485 bool validateAsmConstraint(const char *&Name,
7486 TargetInfo::ConstraintInfo &info) const override;
7487 const char *getClobbers() const override {
7488 // FIXME: Is this really right?
7491 BuiltinVaListKind getBuiltinVaListKind() const override {
7492 return TargetInfo::SystemZBuiltinVaList;
7494 int getISARevision(const StringRef &Name) const {
7495 return llvm::StringSwitch<int>(Name)
7496 .Cases("arch8", "z10", 8)
7497 .Cases("arch9", "z196", 9)
7498 .Cases("arch10", "zEC12", 10)
7499 .Cases("arch11", "z13", 11)
7502 bool setCPU(const std::string &Name) override {
7504 ISARevision = getISARevision(CPU);
7505 return ISARevision != -1;
7508 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7510 const std::vector<std::string> &FeaturesVec) const override {
7511 int ISARevision = getISARevision(CPU);
7512 if (ISARevision >= 10)
7513 Features["transactional-execution"] = true;
7514 if (ISARevision >= 11)
7515 Features["vector"] = true;
7516 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7519 bool handleTargetFeatures(std::vector<std::string> &Features,
7520 DiagnosticsEngine &Diags) override {
7521 HasTransactionalExecution = false;
7523 for (const auto &Feature : Features) {
7524 if (Feature == "+transactional-execution")
7525 HasTransactionalExecution = true;
7526 else if (Feature == "+vector")
7529 // If we use the vector ABI, vector types are 64-bit aligned.
7531 MaxVectorAlign = 64;
7532 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
7533 "-v128:64-a:8:16-n32:64");
7538 bool hasFeature(StringRef Feature) const override {
7539 return llvm::StringSwitch<bool>(Feature)
7540 .Case("systemz", true)
7541 .Case("arch8", ISARevision >= 8)
7542 .Case("arch9", ISARevision >= 9)
7543 .Case("arch10", ISARevision >= 10)
7544 .Case("arch11", ISARevision >= 11)
7545 .Case("htm", HasTransactionalExecution)
7546 .Case("vx", HasVector)
7550 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
7554 case CC_OpenCLKernel:
7557 return CCCR_Warning;
7561 StringRef getABI() const override {
7567 bool useFloat128ManglingForLongDouble() const override {
7572 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
7573 #define BUILTIN(ID, TYPE, ATTRS) \
7574 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7575 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
7576 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
7577 #include "clang/Basic/BuiltinsSystemZ.def"
7580 const char *const SystemZTargetInfo::GCCRegNames[] = {
7581 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7582 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7583 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
7584 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
7587 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
7588 return llvm::makeArrayRef(GCCRegNames);
7591 bool SystemZTargetInfo::
7592 validateAsmConstraint(const char *&Name,
7593 TargetInfo::ConstraintInfo &Info) const {
7598 case 'a': // Address register
7599 case 'd': // Data register (equivalent to 'r')
7600 case 'f': // Floating-point register
7601 Info.setAllowsRegister();
7604 case 'I': // Unsigned 8-bit constant
7605 case 'J': // Unsigned 12-bit constant
7606 case 'K': // Signed 16-bit constant
7607 case 'L': // Signed 20-bit displacement (on all targets we support)
7608 case 'M': // 0x7fffffff
7611 case 'Q': // Memory with base and unsigned 12-bit displacement
7612 case 'R': // Likewise, plus an index
7613 case 'S': // Memory with base and signed 20-bit displacement
7614 case 'T': // Likewise, plus an index
7615 Info.setAllowsMemory();
7620 class MSP430TargetInfo : public TargetInfo {
7621 static const char *const GCCRegNames[];
7624 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7625 : TargetInfo(Triple) {
7626 TLSSupported = false;
7631 LongAlign = LongLongAlign = 16;
7635 SizeType = UnsignedInt;
7636 IntMaxType = SignedLongLong;
7637 IntPtrType = SignedInt;
7638 PtrDiffType = SignedInt;
7639 SigAtomicType = SignedLong;
7640 resetDataLayout("e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16");
7642 void getTargetDefines(const LangOptions &Opts,
7643 MacroBuilder &Builder) const override {
7644 Builder.defineMacro("MSP430");
7645 Builder.defineMacro("__MSP430__");
7646 // FIXME: defines for different 'flavours' of MCU
7648 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7649 // FIXME: Implement.
7652 bool hasFeature(StringRef Feature) const override {
7653 return Feature == "msp430";
7655 ArrayRef<const char *> getGCCRegNames() const override;
7656 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7660 bool validateAsmConstraint(const char *&Name,
7661 TargetInfo::ConstraintInfo &info) const override {
7664 case 'K': // the constant 1
7665 case 'L': // constant -1^20 .. 1^19
7666 case 'M': // constant 1-4:
7669 // No target constraints for now.
7672 const char *getClobbers() const override {
7673 // FIXME: Is this really right?
7676 BuiltinVaListKind getBuiltinVaListKind() const override {
7678 return TargetInfo::CharPtrBuiltinVaList;
7682 const char *const MSP430TargetInfo::GCCRegNames[] = {
7683 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7684 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
7686 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const {
7687 return llvm::makeArrayRef(GCCRegNames);
7690 // LLVM and Clang cannot be used directly to output native binaries for
7691 // target, but is used to compile C code to llvm bitcode with correct
7692 // type and alignment information.
7694 // TCE uses the llvm bitcode as input and uses it for generating customized
7695 // target processor and program binary. TCE co-design environment is
7696 // publicly available in http://tce.cs.tut.fi
7698 static const unsigned TCEOpenCLAddrSpaceMap[] = {
7702 5, // opencl_constant
7703 // FIXME: generic has to be added to the target
7704 0, // opencl_generic
7710 class TCETargetInfo : public TargetInfo {
7712 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7713 : TargetInfo(Triple) {
7714 TLSSupported = false;
7716 LongWidth = LongLongWidth = 32;
7719 LongAlign = LongLongAlign = 32;
7722 SizeType = UnsignedInt;
7723 IntMaxType = SignedLong;
7724 IntPtrType = SignedInt;
7725 PtrDiffType = SignedInt;
7730 LongDoubleWidth = 32;
7731 LongDoubleAlign = 32;
7732 FloatFormat = &llvm::APFloat::IEEEsingle();
7733 DoubleFormat = &llvm::APFloat::IEEEsingle();
7734 LongDoubleFormat = &llvm::APFloat::IEEEsingle();
7735 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-"
7736 "i16:16:32-i32:32:32-i64:32:32-"
7737 "f32:32:32-f64:32:32-v64:32:32-"
7738 "v128:32:32-v256:32:32-v512:32:32-"
7739 "v1024:32:32-a0:0:32-n32");
7740 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
7741 UseAddrSpaceMapMangling = true;
7744 void getTargetDefines(const LangOptions &Opts,
7745 MacroBuilder &Builder) const override {
7746 DefineStd(Builder, "tce", Opts);
7747 Builder.defineMacro("__TCE__");
7748 Builder.defineMacro("__TCE_V1__");
7750 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; }
7752 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7753 const char *getClobbers() const override { return ""; }
7754 BuiltinVaListKind getBuiltinVaListKind() const override {
7755 return TargetInfo::VoidPtrBuiltinVaList;
7757 ArrayRef<const char *> getGCCRegNames() const override { return None; }
7758 bool validateAsmConstraint(const char *&Name,
7759 TargetInfo::ConstraintInfo &info) const override {
7762 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7767 class TCELETargetInfo : public TCETargetInfo {
7769 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7770 : TCETargetInfo(Triple, Opts) {
7773 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-"
7774 "i16:16:32-i32:32:32-i64:32:32-"
7775 "f32:32:32-f64:32:32-v64:32:32-"
7776 "v128:32:32-v256:32:32-v512:32:32-"
7777 "v1024:32:32-a0:0:32-n32");
7781 virtual void getTargetDefines(const LangOptions &Opts,
7782 MacroBuilder &Builder) const {
7783 DefineStd(Builder, "tcele", Opts);
7784 Builder.defineMacro("__TCE__");
7785 Builder.defineMacro("__TCE_V1__");
7786 Builder.defineMacro("__TCELE__");
7787 Builder.defineMacro("__TCELE_V1__");
7792 class BPFTargetInfo : public TargetInfo {
7794 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7795 : TargetInfo(Triple) {
7796 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7797 SizeType = UnsignedLong;
7798 PtrDiffType = SignedLong;
7799 IntPtrType = SignedLong;
7800 IntMaxType = SignedLong;
7801 Int64Type = SignedLong;
7803 if (Triple.getArch() == llvm::Triple::bpfeb) {
7804 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128");
7806 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
7808 MaxAtomicPromoteWidth = 64;
7809 MaxAtomicInlineWidth = 64;
7810 TLSSupported = false;
7812 void getTargetDefines(const LangOptions &Opts,
7813 MacroBuilder &Builder) const override {
7814 DefineStd(Builder, "bpf", Opts);
7815 Builder.defineMacro("__BPF__");
7817 bool hasFeature(StringRef Feature) const override {
7818 return Feature == "bpf";
7821 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7822 const char *getClobbers() const override {
7825 BuiltinVaListKind getBuiltinVaListKind() const override {
7826 return TargetInfo::VoidPtrBuiltinVaList;
7828 ArrayRef<const char *> getGCCRegNames() const override {
7831 bool validateAsmConstraint(const char *&Name,
7832 TargetInfo::ConstraintInfo &info) const override {
7835 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7838 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
7841 return CCCR_Warning;
7843 case CC_OpenCLKernel:
7849 class Nios2TargetInfo : public TargetInfo {
7850 void setDataLayout() {
7852 resetDataLayout("E-p:32:32:32-i8:8:32-i16:16:32-n32");
7854 resetDataLayout("e-p:32:32:32-i8:8:32-i16:16:32-n32");
7857 static const Builtin::Info BuiltinInfo[];
7862 Nios2TargetInfo(const llvm::Triple &triple, const TargetOptions &opts)
7863 : TargetInfo(triple), CPU(opts.CPU), ABI(opts.ABI) {
7864 SizeType = UnsignedInt;
7865 PtrDiffType = SignedInt;
7866 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
7870 StringRef getABI() const override { return ABI; }
7871 bool setABI(const std::string &Name) override {
7872 if (Name == "o32" || Name == "eabi") {
7879 bool setCPU(const std::string &Name) override {
7880 if (Name == "nios2r1" || Name == "nios2r2") {
7887 void getTargetDefines(const LangOptions &Opts,
7888 MacroBuilder &Builder) const override {
7889 DefineStd(Builder, "nios2", Opts);
7890 DefineStd(Builder, "NIOS2", Opts);
7892 Builder.defineMacro("__nios2");
7893 Builder.defineMacro("__NIOS2");
7894 Builder.defineMacro("__nios2__");
7895 Builder.defineMacro("__NIOS2__");
7898 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7899 return llvm::makeArrayRef(BuiltinInfo, clang::Nios2::LastTSBuiltin -
7900 Builtin::FirstTSBuiltin);
7903 bool isFeatureSupportedByCPU(StringRef Feature, StringRef CPU) const {
7904 const bool isR2 = CPU == "nios2r2";
7905 return llvm::StringSwitch<bool>(Feature)
7906 .Case("nios2r2mandatory", isR2)
7907 .Case("nios2r2bmx", isR2)
7908 .Case("nios2r2mpx", isR2)
7909 .Case("nios2r2cdx", isR2)
7913 bool initFeatureMap(llvm::StringMap<bool> &Features,
7914 DiagnosticsEngine &Diags, StringRef CPU,
7915 const std::vector<std::string> &FeatureVec) const override {
7916 static const char *allFeatures[] = {
7917 "nios2r2mandatory", "nios2r2bmx", "nios2r2mpx", "nios2r2cdx"
7919 for (const char *feature : allFeatures) {
7920 Features[feature] = isFeatureSupportedByCPU(feature, CPU);
7925 bool hasFeature(StringRef Feature) const override {
7926 return isFeatureSupportedByCPU(Feature, CPU);
7929 BuiltinVaListKind getBuiltinVaListKind() const override {
7930 return TargetInfo::VoidPtrBuiltinVaList;
7933 ArrayRef<const char *> getGCCRegNames() const override {
7934 static const char *const GCCRegNames[] = {
7935 // CPU register names
7936 // Must match second column of GCCRegAliases
7937 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
7938 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20",
7939 "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30",
7941 // Floating point register names
7942 "ctl0", "ctl1", "ctl2", "ctl3", "ctl4", "ctl5", "ctl6", "ctl7", "ctl8",
7943 "ctl9", "ctl10", "ctl11", "ctl12", "ctl13", "ctl14", "ctl15"
7945 return llvm::makeArrayRef(GCCRegNames);
7948 bool validateAsmConstraint(const char *&Name,
7949 TargetInfo::ConstraintInfo &Info) const override {
7954 case 'r': // CPU registers.
7955 case 'd': // Equivalent to "r" unless generating MIPS16 code.
7956 case 'y': // Equivalent to "r", backwards compatibility only.
7957 case 'f': // floating-point registers.
7958 case 'c': // $25 for indirect jumps
7959 case 'l': // lo register
7960 case 'x': // hilo register pair
7961 Info.setAllowsRegister();
7966 const char *getClobbers() const override { return ""; }
7968 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7969 static const TargetInfo::GCCRegAlias aliases[] = {
7970 {{"zero"}, "r0"}, {{"at"}, "r1"}, {{"et"}, "r24"},
7971 {{"bt"}, "r25"}, {{"gp"}, "r26"}, {{"sp"}, "r27"},
7972 {{"fp"}, "r28"}, {{"ea"}, "r29"}, {{"ba"}, "r30"},
7973 {{"ra"}, "r31"}, {{"status"}, "ctl0"}, {{"estatus"}, "ctl1"},
7974 {{"bstatus"}, "ctl2"}, {{"ienable"}, "ctl3"}, {{"ipending"}, "ctl4"},
7975 {{"cpuid"}, "ctl5"}, {{"exception"}, "ctl7"}, {{"pteaddr"}, "ctl8"},
7976 {{"tlbacc"}, "ctl9"}, {{"tlbmisc"}, "ctl10"}, {{"badaddr"}, "ctl12"},
7977 {{"config"}, "ctl13"}, {{"mpubase"}, "ctl14"}, {{"mpuacc"}, "ctl15"},
7979 return llvm::makeArrayRef(aliases);
7983 const Builtin::Info Nios2TargetInfo::BuiltinInfo[] = {
7984 #define BUILTIN(ID, TYPE, ATTRS) \
7985 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
7986 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
7987 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
7988 #include "clang/Basic/BuiltinsNios2.def"
7991 class MipsTargetInfo : public TargetInfo {
7992 void setDataLayout() {
7996 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
7997 else if (ABI == "n32")
7998 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7999 else if (ABI == "n64")
8000 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128";
8002 llvm_unreachable("Invalid ABI");
8005 resetDataLayout(("E-" + Layout).str());
8007 resetDataLayout(("e-" + Layout).str());
8011 static const Builtin::Info BuiltinInfo[];
8018 bool CanUseBSDABICalls;
8020 HardFloat, SoftFloat
8033 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8034 : TargetInfo(Triple), IsMips16(false), IsMicromips(false),
8035 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false),
8036 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP),
8037 HasMSA(false), DisableMadd4(false), HasFP64(false) {
8038 TheCXXABI.set(TargetCXXABI::GenericMIPS);
8040 setABI((getTriple().getArch() == llvm::Triple::mips ||
8041 getTriple().getArch() == llvm::Triple::mipsel)
8045 CPU = ABI == "o32" ? "mips32r2" : "mips64r2";
8047 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD ||
8048 Triple.getOS() == llvm::Triple::OpenBSD;
8051 bool isNaN2008Default() const {
8052 return CPU == "mips32r6" || CPU == "mips64r6";
8055 bool isFP64Default() const {
8056 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
8059 bool isNan2008() const override {
8063 bool processorSupportsGPR64() const {
8064 return llvm::StringSwitch<bool>(CPU)
8065 .Case("mips3", true)
8066 .Case("mips4", true)
8067 .Case("mips5", true)
8068 .Case("mips64", true)
8069 .Case("mips64r2", true)
8070 .Case("mips64r3", true)
8071 .Case("mips64r5", true)
8072 .Case("mips64r6", true)
8073 .Case("octeon", true)
8078 StringRef getABI() const override { return ABI; }
8079 bool setABI(const std::string &Name) override {
8080 if (Name == "o32") {
8086 if (Name == "n32") {
8091 if (Name == "n64") {
8099 void setO32ABITypes() {
8100 Int64Type = SignedLongLong;
8101 IntMaxType = Int64Type;
8102 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
8103 LongDoubleWidth = LongDoubleAlign = 64;
8104 LongWidth = LongAlign = 32;
8105 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
8106 PointerWidth = PointerAlign = 32;
8107 PtrDiffType = SignedInt;
8108 SizeType = UnsignedInt;
8112 void setN32N64ABITypes() {
8113 LongDoubleWidth = LongDoubleAlign = 128;
8114 LongDoubleFormat = &llvm::APFloat::IEEEquad();
8115 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
8116 LongDoubleWidth = LongDoubleAlign = 64;
8117 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
8119 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8120 SuitableAlign = 128;
8123 void setN64ABITypes() {
8124 setN32N64ABITypes();
8125 if (getTriple().getOS() == llvm::Triple::OpenBSD) {
8126 Int64Type = SignedLongLong;
8128 Int64Type = SignedLong;
8130 IntMaxType = Int64Type;
8131 LongWidth = LongAlign = 64;
8132 PointerWidth = PointerAlign = 64;
8133 PtrDiffType = SignedLong;
8134 SizeType = UnsignedLong;
8137 void setN32ABITypes() {
8138 setN32N64ABITypes();
8139 Int64Type = SignedLongLong;
8140 IntMaxType = Int64Type;
8141 LongWidth = LongAlign = 32;
8142 PointerWidth = PointerAlign = 32;
8143 PtrDiffType = SignedInt;
8144 SizeType = UnsignedInt;
8147 bool setCPU(const std::string &Name) override {
8149 return llvm::StringSwitch<bool>(Name)
8150 .Case("mips1", true)
8151 .Case("mips2", true)
8152 .Case("mips3", true)
8153 .Case("mips4", true)
8154 .Case("mips5", true)
8155 .Case("mips32", true)
8156 .Case("mips32r2", true)
8157 .Case("mips32r3", true)
8158 .Case("mips32r5", true)
8159 .Case("mips32r6", true)
8160 .Case("mips64", true)
8161 .Case("mips64r2", true)
8162 .Case("mips64r3", true)
8163 .Case("mips64r5", true)
8164 .Case("mips64r6", true)
8165 .Case("octeon", true)
8166 .Case("p5600", true)
8169 const std::string& getCPU() const { return CPU; }
8171 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
8173 const std::vector<std::string> &FeaturesVec) const override {
8176 if (CPU == "octeon")
8177 Features["mips64r2"] = Features["cnmips"] = true;
8179 Features[CPU] = true;
8180 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
8183 void getTargetDefines(const LangOptions &Opts,
8184 MacroBuilder &Builder) const override {
8186 DefineStd(Builder, "MIPSEB", Opts);
8187 Builder.defineMacro("_MIPSEB");
8189 DefineStd(Builder, "MIPSEL", Opts);
8190 Builder.defineMacro("_MIPSEL");
8193 Builder.defineMacro("__mips__");
8194 Builder.defineMacro("_mips");
8196 Builder.defineMacro("mips");
8199 Builder.defineMacro("__mips", "32");
8200 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
8202 Builder.defineMacro("__mips", "64");
8203 Builder.defineMacro("__mips64");
8204 Builder.defineMacro("__mips64__");
8205 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
8208 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU())
8209 .Cases("mips32", "mips64", "1")
8210 .Cases("mips32r2", "mips64r2", "2")
8211 .Cases("mips32r3", "mips64r3", "3")
8212 .Cases("mips32r5", "mips64r5", "5")
8213 .Cases("mips32r6", "mips64r6", "6")
8215 if (!ISARev.empty())
8216 Builder.defineMacro("__mips_isa_rev", ISARev);
8219 Builder.defineMacro("__mips_o32");
8220 Builder.defineMacro("_ABIO32", "1");
8221 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
8222 } else if (ABI == "n32") {
8223 Builder.defineMacro("__mips_n32");
8224 Builder.defineMacro("_ABIN32", "2");
8225 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
8226 } else if (ABI == "n64") {
8227 Builder.defineMacro("__mips_n64");
8228 Builder.defineMacro("_ABI64", "3");
8229 Builder.defineMacro("_MIPS_SIM", "_ABI64");
8231 llvm_unreachable("Invalid ABI.");
8233 if (!IsNoABICalls) {
8234 Builder.defineMacro("__mips_abicalls");
8235 if (CanUseBSDABICalls)
8236 Builder.defineMacro("__ABICALLS__");
8239 Builder.defineMacro("__REGISTER_PREFIX__", "");
8243 Builder.defineMacro("__mips_hard_float", Twine(1));
8246 Builder.defineMacro("__mips_soft_float", Twine(1));
8251 Builder.defineMacro("__mips_single_float", Twine(1));
8253 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
8254 Builder.defineMacro("_MIPS_FPSET",
8255 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
8258 Builder.defineMacro("__mips16", Twine(1));
8261 Builder.defineMacro("__mips_micromips", Twine(1));
8264 Builder.defineMacro("__mips_nan2008", Twine(1));
8270 Builder.defineMacro("__mips_dsp_rev", Twine(1));
8271 Builder.defineMacro("__mips_dsp", Twine(1));
8274 Builder.defineMacro("__mips_dsp_rev", Twine(2));
8275 Builder.defineMacro("__mips_dspr2", Twine(1));
8276 Builder.defineMacro("__mips_dsp", Twine(1));
8281 Builder.defineMacro("__mips_msa", Twine(1));
8284 Builder.defineMacro("__mips_no_madd4", Twine(1));
8286 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
8287 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
8288 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
8290 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
8291 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
8293 // These shouldn't be defined for MIPS-I but there's no need to check
8294 // for that since MIPS-I isn't supported.
8295 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
8296 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
8297 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
8299 // 32-bit MIPS processors don't have the necessary lld/scd instructions
8300 // found in 64-bit processors. In the case of O32 on a 64-bit processor,
8301 // the instructions exist but using them violates the ABI since they
8302 // require 64-bit GPRs and O32 only supports 32-bit GPRs.
8303 if (ABI == "n32" || ABI == "n64")
8304 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
8307 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8308 return llvm::makeArrayRef(BuiltinInfo,
8309 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin);
8311 bool hasFeature(StringRef Feature) const override {
8312 return llvm::StringSwitch<bool>(Feature)
8314 .Case("fp64", HasFP64)
8317 BuiltinVaListKind getBuiltinVaListKind() const override {
8318 return TargetInfo::VoidPtrBuiltinVaList;
8320 ArrayRef<const char *> getGCCRegNames() const override {
8321 static const char *const GCCRegNames[] = {
8322 // CPU register names
8323 // Must match second column of GCCRegAliases
8324 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
8325 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
8326 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
8327 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
8328 // Floating point register names
8329 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
8330 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
8331 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
8332 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
8333 // Hi/lo and condition register names
8334 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
8335 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo",
8337 // MSA register names
8338 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
8339 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
8340 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
8341 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
8342 // MSA control register names
8343 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
8344 "$msarequest", "$msamap", "$msaunmap"
8346 return llvm::makeArrayRef(GCCRegNames);
8348 bool validateAsmConstraint(const char *&Name,
8349 TargetInfo::ConstraintInfo &Info) const override {
8353 case 'r': // CPU registers.
8354 case 'd': // Equivalent to "r" unless generating MIPS16 code.
8355 case 'y': // Equivalent to "r", backward compatibility only.
8356 case 'f': // floating-point registers.
8357 case 'c': // $25 for indirect jumps
8358 case 'l': // lo register
8359 case 'x': // hilo register pair
8360 Info.setAllowsRegister();
8362 case 'I': // Signed 16-bit constant
8363 case 'J': // Integer 0
8364 case 'K': // Unsigned 16-bit constant
8365 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
8366 case 'M': // Constants not loadable via lui, addiu, or ori
8367 case 'N': // Constant -1 to -65535
8368 case 'O': // A signed 15-bit constant
8369 case 'P': // A constant between 1 go 65535
8371 case 'R': // An address that can be used in a non-macro load or store
8372 Info.setAllowsMemory();
8375 if (Name[1] == 'C') { // An address usable by ll, and sc.
8376 Info.setAllowsMemory();
8377 Name++; // Skip over 'Z'.
8384 std::string convertConstraint(const char *&Constraint) const override {
8386 switch (*Constraint) {
8387 case 'Z': // Two-character constraint; add "^" hint for later parsing.
8388 if (Constraint[1] == 'C') {
8389 R = std::string("^") + std::string(Constraint, 2);
8395 return TargetInfo::convertConstraint(Constraint);
8398 const char *getClobbers() const override {
8399 // In GCC, $1 is not widely used in generated code (it's used only in a few
8400 // specific situations), so there is no real need for users to add it to
8401 // the clobbers list if they want to use it in their inline assembly code.
8403 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
8404 // code generation, so using it in inline assembly without adding it to the
8405 // clobbers list can cause conflicts between the inline assembly code and
8406 // the surrounding generated code.
8408 // Another problem is that LLVM is allowed to choose $1 for inline assembly
8409 // operands, which will conflict with the ".set at" assembler option (which
8410 // we use only for inline assembly, in order to maintain compatibility with
8411 // GCC) and will also conflict with the user's usage of $1.
8413 // The easiest way to avoid these conflicts and keep $1 as an allocatable
8414 // register for generated code is to automatically clobber $1 for all inline
8417 // FIXME: We should automatically clobber $1 only for inline assembly code
8418 // which actually uses it. This would allow LLVM to use $1 for inline
8419 // assembly operands if the user's assembly code doesn't use it.
8423 bool handleTargetFeatures(std::vector<std::string> &Features,
8424 DiagnosticsEngine &Diags) override {
8426 IsMicromips = false;
8427 IsNan2008 = isNaN2008Default();
8428 IsSingleFloat = false;
8429 FloatABI = HardFloat;
8431 HasFP64 = isFP64Default();
8433 for (const auto &Feature : Features) {
8434 if (Feature == "+single-float")
8435 IsSingleFloat = true;
8436 else if (Feature == "+soft-float")
8437 FloatABI = SoftFloat;
8438 else if (Feature == "+mips16")
8440 else if (Feature == "+micromips")
8442 else if (Feature == "+dsp")
8443 DspRev = std::max(DspRev, DSP1);
8444 else if (Feature == "+dspr2")
8445 DspRev = std::max(DspRev, DSP2);
8446 else if (Feature == "+msa")
8448 else if (Feature == "+nomadd4")
8449 DisableMadd4 = true;
8450 else if (Feature == "+fp64")
8452 else if (Feature == "-fp64")
8454 else if (Feature == "+nan2008")
8456 else if (Feature == "-nan2008")
8458 else if (Feature == "+noabicalls")
8459 IsNoABICalls = true;
8467 int getEHDataRegisterNumber(unsigned RegNo) const override {
8468 if (RegNo == 0) return 4;
8469 if (RegNo == 1) return 5;
8473 bool isCLZForZeroUndef() const override { return false; }
8475 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8476 static const TargetInfo::GCCRegAlias O32RegAliases[] = {
8477 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
8478 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
8479 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"},
8480 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"},
8481 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"},
8482 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
8483 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
8484 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
8485 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
8486 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
8488 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = {
8489 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
8490 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
8491 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"},
8492 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"},
8493 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"},
8494 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
8495 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
8496 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
8497 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
8498 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
8501 return llvm::makeArrayRef(O32RegAliases);
8502 return llvm::makeArrayRef(NewABIRegAliases);
8505 bool hasInt128Type() const override {
8506 return ABI == "n32" || ABI == "n64";
8509 bool validateTarget(DiagnosticsEngine &Diags) const override {
8510 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle
8511 // this yet. It's better to fail here than on the backend assertion.
8512 if (processorSupportsGPR64() && ABI == "o32") {
8513 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
8517 // 64-bit ABI's require 64-bit CPU's.
8518 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) {
8519 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
8523 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend
8524 // can't handle this yet. It's better to fail here than on the
8525 // backend assertion.
8526 if ((getTriple().getArch() == llvm::Triple::mips64 ||
8527 getTriple().getArch() == llvm::Triple::mips64el) &&
8529 Diags.Report(diag::err_target_unsupported_abi_for_triple)
8530 << ABI << getTriple().str();
8534 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend
8535 // can't handle this yet. It's better to fail here than on the
8536 // backend assertion.
8537 if ((getTriple().getArch() == llvm::Triple::mips ||
8538 getTriple().getArch() == llvm::Triple::mipsel) &&
8539 (ABI == "n32" || ABI == "n64")) {
8540 Diags.Report(diag::err_target_unsupported_abi_for_triple)
8541 << ABI << getTriple().str();
8549 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = {
8550 #define BUILTIN(ID, TYPE, ATTRS) \
8551 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8552 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8553 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8554 #include "clang/Basic/BuiltinsMips.def"
8557 class PNaClTargetInfo : public TargetInfo {
8559 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8560 : TargetInfo(Triple) {
8561 this->LongAlign = 32;
8562 this->LongWidth = 32;
8563 this->PointerAlign = 32;
8564 this->PointerWidth = 32;
8565 this->IntMaxType = TargetInfo::SignedLongLong;
8566 this->Int64Type = TargetInfo::SignedLongLong;
8567 this->DoubleAlign = 64;
8568 this->LongDoubleWidth = 64;
8569 this->LongDoubleAlign = 64;
8570 this->SizeType = TargetInfo::UnsignedInt;
8571 this->PtrDiffType = TargetInfo::SignedInt;
8572 this->IntPtrType = TargetInfo::SignedInt;
8573 this->RegParmMax = 0; // Disallow regparm
8576 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
8577 Builder.defineMacro("__le32__");
8578 Builder.defineMacro("__pnacl__");
8580 void getTargetDefines(const LangOptions &Opts,
8581 MacroBuilder &Builder) const override {
8582 getArchDefines(Opts, Builder);
8584 bool hasFeature(StringRef Feature) const override {
8585 return Feature == "pnacl";
8587 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
8588 BuiltinVaListKind getBuiltinVaListKind() const override {
8589 return TargetInfo::PNaClABIBuiltinVaList;
8591 ArrayRef<const char *> getGCCRegNames() const override;
8592 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
8593 bool validateAsmConstraint(const char *&Name,
8594 TargetInfo::ConstraintInfo &Info) const override {
8598 const char *getClobbers() const override {
8603 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const {
8607 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const {
8611 // We attempt to use PNaCl (le32) frontend and Mips32EL backend.
8612 class NaClMips32TargetInfo : public MipsTargetInfo {
8614 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8615 : MipsTargetInfo(Triple, Opts) {}
8617 BuiltinVaListKind getBuiltinVaListKind() const override {
8618 return TargetInfo::PNaClABIBuiltinVaList;
8622 class Le64TargetInfo : public TargetInfo {
8623 static const Builtin::Info BuiltinInfo[];
8626 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8627 : TargetInfo(Triple) {
8628 NoAsmVariants = true;
8629 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
8630 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8631 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128");
8634 void getTargetDefines(const LangOptions &Opts,
8635 MacroBuilder &Builder) const override {
8636 DefineStd(Builder, "unix", Opts);
8637 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
8638 Builder.defineMacro("__ELF__");
8640 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8641 return llvm::makeArrayRef(BuiltinInfo,
8642 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin);
8644 BuiltinVaListKind getBuiltinVaListKind() const override {
8645 return TargetInfo::PNaClABIBuiltinVaList;
8647 const char *getClobbers() const override { return ""; }
8648 ArrayRef<const char *> getGCCRegNames() const override {
8651 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8654 bool validateAsmConstraint(const char *&Name,
8655 TargetInfo::ConstraintInfo &Info) const override {
8659 bool hasProtectedVisibility() const override { return false; }
8662 class WebAssemblyTargetInfo : public TargetInfo {
8663 static const Builtin::Info BuiltinInfo[];
8671 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &)
8672 : TargetInfo(T), SIMDLevel(NoSIMD) {
8673 NoAsmVariants = true;
8674 SuitableAlign = 128;
8675 LargeArrayMinWidth = 128;
8676 LargeArrayAlign = 128;
8677 SimdDefaultAlign = 128;
8678 SigAtomicType = SignedLong;
8679 LongDoubleWidth = LongDoubleAlign = 128;
8680 LongDoubleFormat = &llvm::APFloat::IEEEquad();
8681 SizeType = UnsignedInt;
8682 PtrDiffType = SignedInt;
8683 IntPtrType = SignedInt;
8687 void getTargetDefines(const LangOptions &Opts,
8688 MacroBuilder &Builder) const override {
8689 defineCPUMacros(Builder, "wasm", /*Tuning=*/false);
8690 if (SIMDLevel >= SIMD128)
8691 Builder.defineMacro("__wasm_simd128__");
8696 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
8698 const std::vector<std::string> &FeaturesVec) const override {
8699 if (CPU == "bleeding-edge")
8700 Features["simd128"] = true;
8701 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
8703 bool hasFeature(StringRef Feature) const final {
8704 return llvm::StringSwitch<bool>(Feature)
8705 .Case("simd128", SIMDLevel >= SIMD128)
8708 bool handleTargetFeatures(std::vector<std::string> &Features,
8709 DiagnosticsEngine &Diags) final {
8710 for (const auto &Feature : Features) {
8711 if (Feature == "+simd128") {
8712 SIMDLevel = std::max(SIMDLevel, SIMD128);
8715 if (Feature == "-simd128") {
8716 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1));
8720 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature
8721 << "-target-feature";
8726 bool setCPU(const std::string &Name) final {
8727 return llvm::StringSwitch<bool>(Name)
8729 .Case("bleeding-edge", true)
8730 .Case("generic", true)
8733 ArrayRef<Builtin::Info> getTargetBuiltins() const final {
8734 return llvm::makeArrayRef(BuiltinInfo,
8735 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin);
8737 BuiltinVaListKind getBuiltinVaListKind() const final {
8738 return VoidPtrBuiltinVaList;
8740 ArrayRef<const char *> getGCCRegNames() const final {
8743 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final {
8747 validateAsmConstraint(const char *&Name,
8748 TargetInfo::ConstraintInfo &Info) const final {
8751 const char *getClobbers() const final { return ""; }
8752 bool isCLZForZeroUndef() const final { return false; }
8753 bool hasInt128Type() const final { return true; }
8754 IntType getIntTypeByWidth(unsigned BitWidth,
8755 bool IsSigned) const final {
8756 // WebAssembly prefers long long for explicitly 64-bit integers.
8757 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
8758 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
8760 IntType getLeastIntTypeByWidth(unsigned BitWidth,
8761 bool IsSigned) const final {
8762 // WebAssembly uses long long for int_least64_t and int_fast64_t.
8763 return BitWidth == 64
8764 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
8765 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
8769 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = {
8770 #define BUILTIN(ID, TYPE, ATTRS) \
8771 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8772 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8773 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8774 #include "clang/Basic/BuiltinsWebAssembly.def"
8777 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo {
8779 explicit WebAssembly32TargetInfo(const llvm::Triple &T,
8780 const TargetOptions &Opts)
8781 : WebAssemblyTargetInfo(T, Opts) {
8782 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8783 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128");
8787 void getTargetDefines(const LangOptions &Opts,
8788 MacroBuilder &Builder) const override {
8789 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
8790 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false);
8794 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo {
8796 explicit WebAssembly64TargetInfo(const llvm::Triple &T,
8797 const TargetOptions &Opts)
8798 : WebAssemblyTargetInfo(T, Opts) {
8799 LongAlign = LongWidth = 64;
8800 PointerAlign = PointerWidth = 64;
8801 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8802 SizeType = UnsignedLong;
8803 PtrDiffType = SignedLong;
8804 IntPtrType = SignedLong;
8805 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
8809 void getTargetDefines(const LangOptions &Opts,
8810 MacroBuilder &Builder) const override {
8811 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
8812 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false);
8816 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
8817 #define BUILTIN(ID, TYPE, ATTRS) \
8818 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8819 #include "clang/Basic/BuiltinsLe64.def"
8822 static const unsigned SPIRAddrSpaceMap[] = {
8826 2, // opencl_constant
8827 4, // opencl_generic
8832 class SPIRTargetInfo : public TargetInfo {
8834 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8835 : TargetInfo(Triple) {
8836 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
8837 "SPIR target must use unknown OS");
8838 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
8839 "SPIR target must use unknown environment type");
8840 TLSSupported = false;
8841 LongWidth = LongAlign = 64;
8842 AddrSpaceMap = &SPIRAddrSpaceMap;
8843 UseAddrSpaceMapMangling = true;
8844 // Define available target features
8845 // These must be defined in sorted order!
8846 NoAsmVariants = true;
8848 void getTargetDefines(const LangOptions &Opts,
8849 MacroBuilder &Builder) const override {
8850 DefineStd(Builder, "SPIR", Opts);
8852 bool hasFeature(StringRef Feature) const override {
8853 return Feature == "spir";
8856 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
8857 const char *getClobbers() const override { return ""; }
8858 ArrayRef<const char *> getGCCRegNames() const override { return None; }
8859 bool validateAsmConstraint(const char *&Name,
8860 TargetInfo::ConstraintInfo &info) const override {
8863 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8866 BuiltinVaListKind getBuiltinVaListKind() const override {
8867 return TargetInfo::VoidPtrBuiltinVaList;
8870 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
8871 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK
8875 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
8876 return CC_SpirFunction;
8879 void setSupportedOpenCLOpts() override {
8880 // Assume all OpenCL extensions and optional core features are supported
8881 // for SPIR since it is a generic target.
8882 getSupportedOpenCLOpts().supportAll();
8886 class SPIR32TargetInfo : public SPIRTargetInfo {
8888 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8889 : SPIRTargetInfo(Triple, Opts) {
8890 PointerWidth = PointerAlign = 32;
8891 SizeType = TargetInfo::UnsignedInt;
8892 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
8893 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
8894 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
8896 void getTargetDefines(const LangOptions &Opts,
8897 MacroBuilder &Builder) const override {
8898 DefineStd(Builder, "SPIR32", Opts);
8902 class SPIR64TargetInfo : public SPIRTargetInfo {
8904 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8905 : SPIRTargetInfo(Triple, Opts) {
8906 PointerWidth = PointerAlign = 64;
8907 SizeType = TargetInfo::UnsignedLong;
8908 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
8909 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
8910 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
8912 void getTargetDefines(const LangOptions &Opts,
8913 MacroBuilder &Builder) const override {
8914 DefineStd(Builder, "SPIR64", Opts);
8918 class XCoreTargetInfo : public TargetInfo {
8919 static const Builtin::Info BuiltinInfo[];
8921 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8922 : TargetInfo(Triple) {
8923 NoAsmVariants = true;
8926 DoubleAlign = LongDoubleAlign = 32;
8927 SizeType = UnsignedInt;
8928 PtrDiffType = SignedInt;
8929 IntPtrType = SignedInt;
8930 WCharType = UnsignedChar;
8931 WIntType = UnsignedInt;
8932 UseZeroLengthBitfieldAlignment = true;
8933 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
8934 "-f64:32-a:0:32-n32");
8936 void getTargetDefines(const LangOptions &Opts,
8937 MacroBuilder &Builder) const override {
8938 Builder.defineMacro("__XS1B__");
8940 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8941 return llvm::makeArrayRef(BuiltinInfo,
8942 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin);
8944 BuiltinVaListKind getBuiltinVaListKind() const override {
8945 return TargetInfo::VoidPtrBuiltinVaList;
8947 const char *getClobbers() const override {
8950 ArrayRef<const char *> getGCCRegNames() const override {
8951 static const char * const GCCRegNames[] = {
8952 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8953 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
8955 return llvm::makeArrayRef(GCCRegNames);
8957 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8960 bool validateAsmConstraint(const char *&Name,
8961 TargetInfo::ConstraintInfo &Info) const override {
8964 int getEHDataRegisterNumber(unsigned RegNo) const override {
8965 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
8966 return (RegNo < 2)? RegNo : -1;
8968 bool allowsLargerPreferedTypeAlignment() const override {
8973 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
8974 #define BUILTIN(ID, TYPE, ATTRS) \
8975 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8976 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8977 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8978 #include "clang/Basic/BuiltinsXCore.def"
8981 // x86_32 Android target
8982 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
8984 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8985 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) {
8987 LongDoubleWidth = 64;
8988 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
8992 // x86_64 Android target
8993 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
8995 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8996 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) {
8997 LongDoubleFormat = &llvm::APFloat::IEEEquad();
9000 bool useFloat128ManglingForLongDouble() const override {
9005 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes
9006 class RenderScript32TargetInfo : public ARMleTargetInfo {
9008 RenderScript32TargetInfo(const llvm::Triple &Triple,
9009 const TargetOptions &Opts)
9010 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(),
9012 Triple.getEnvironmentName()),
9014 IsRenderScriptTarget = true;
9015 LongWidth = LongAlign = 64;
9017 void getTargetDefines(const LangOptions &Opts,
9018 MacroBuilder &Builder) const override {
9019 Builder.defineMacro("__RENDERSCRIPT__");
9020 ARMleTargetInfo::getTargetDefines(Opts, Builder);
9024 // 64-bit RenderScript is aarch64
9025 class RenderScript64TargetInfo : public AArch64leTargetInfo {
9027 RenderScript64TargetInfo(const llvm::Triple &Triple,
9028 const TargetOptions &Opts)
9029 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(),
9031 Triple.getEnvironmentName()),
9033 IsRenderScriptTarget = true;
9036 void getTargetDefines(const LangOptions &Opts,
9037 MacroBuilder &Builder) const override {
9038 Builder.defineMacro("__RENDERSCRIPT__");
9039 AArch64leTargetInfo::getTargetDefines(Opts, Builder);
9043 /// Information about a specific microcontroller.
9046 const char *DefineName;
9049 // This list should be kept up-to-date with AVRDevices.td in LLVM.
9050 static ArrayRef<MCUInfo> AVRMcus = {
9051 { "at90s1200", "__AVR_AT90S1200__" },
9052 { "attiny11", "__AVR_ATtiny11__" },
9053 { "attiny12", "__AVR_ATtiny12__" },
9054 { "attiny15", "__AVR_ATtiny15__" },
9055 { "attiny28", "__AVR_ATtiny28__" },
9056 { "at90s2313", "__AVR_AT90S2313__" },
9057 { "at90s2323", "__AVR_AT90S2323__" },
9058 { "at90s2333", "__AVR_AT90S2333__" },
9059 { "at90s2343", "__AVR_AT90S2343__" },
9060 { "attiny22", "__AVR_ATtiny22__" },
9061 { "attiny26", "__AVR_ATtiny26__" },
9062 { "at86rf401", "__AVR_AT86RF401__" },
9063 { "at90s4414", "__AVR_AT90S4414__" },
9064 { "at90s4433", "__AVR_AT90S4433__" },
9065 { "at90s4434", "__AVR_AT90S4434__" },
9066 { "at90s8515", "__AVR_AT90S8515__" },
9067 { "at90c8534", "__AVR_AT90c8534__" },
9068 { "at90s8535", "__AVR_AT90S8535__" },
9069 { "ata5272", "__AVR_ATA5272__" },
9070 { "attiny13", "__AVR_ATtiny13__" },
9071 { "attiny13a", "__AVR_ATtiny13A__" },
9072 { "attiny2313", "__AVR_ATtiny2313__" },
9073 { "attiny2313a", "__AVR_ATtiny2313A__" },
9074 { "attiny24", "__AVR_ATtiny24__" },
9075 { "attiny24a", "__AVR_ATtiny24A__" },
9076 { "attiny4313", "__AVR_ATtiny4313__" },
9077 { "attiny44", "__AVR_ATtiny44__" },
9078 { "attiny44a", "__AVR_ATtiny44A__" },
9079 { "attiny84", "__AVR_ATtiny84__" },
9080 { "attiny84a", "__AVR_ATtiny84A__" },
9081 { "attiny25", "__AVR_ATtiny25__" },
9082 { "attiny45", "__AVR_ATtiny45__" },
9083 { "attiny85", "__AVR_ATtiny85__" },
9084 { "attiny261", "__AVR_ATtiny261__" },
9085 { "attiny261a", "__AVR_ATtiny261A__" },
9086 { "attiny461", "__AVR_ATtiny461__" },
9087 { "attiny461a", "__AVR_ATtiny461A__" },
9088 { "attiny861", "__AVR_ATtiny861__" },
9089 { "attiny861a", "__AVR_ATtiny861A__" },
9090 { "attiny87", "__AVR_ATtiny87__" },
9091 { "attiny43u", "__AVR_ATtiny43U__" },
9092 { "attiny48", "__AVR_ATtiny48__" },
9093 { "attiny88", "__AVR_ATtiny88__" },
9094 { "attiny828", "__AVR_ATtiny828__" },
9095 { "at43usb355", "__AVR_AT43USB355__" },
9096 { "at76c711", "__AVR_AT76C711__" },
9097 { "atmega103", "__AVR_ATmega103__" },
9098 { "at43usb320", "__AVR_AT43USB320__" },
9099 { "attiny167", "__AVR_ATtiny167__" },
9100 { "at90usb82", "__AVR_AT90USB82__" },
9101 { "at90usb162", "__AVR_AT90USB162__" },
9102 { "ata5505", "__AVR_ATA5505__" },
9103 { "atmega8u2", "__AVR_ATmega8U2__" },
9104 { "atmega16u2", "__AVR_ATmega16U2__" },
9105 { "atmega32u2", "__AVR_ATmega32U2__" },
9106 { "attiny1634", "__AVR_ATtiny1634__" },
9107 { "atmega8", "__AVR_ATmega8__" },
9108 { "ata6289", "__AVR_ATA6289__" },
9109 { "atmega8a", "__AVR_ATmega8A__" },
9110 { "ata6285", "__AVR_ATA6285__" },
9111 { "ata6286", "__AVR_ATA6286__" },
9112 { "atmega48", "__AVR_ATmega48__" },
9113 { "atmega48a", "__AVR_ATmega48A__" },
9114 { "atmega48pa", "__AVR_ATmega48PA__" },
9115 { "atmega48p", "__AVR_ATmega48P__" },
9116 { "atmega88", "__AVR_ATmega88__" },
9117 { "atmega88a", "__AVR_ATmega88A__" },
9118 { "atmega88p", "__AVR_ATmega88P__" },
9119 { "atmega88pa", "__AVR_ATmega88PA__" },
9120 { "atmega8515", "__AVR_ATmega8515__" },
9121 { "atmega8535", "__AVR_ATmega8535__" },
9122 { "atmega8hva", "__AVR_ATmega8HVA__" },
9123 { "at90pwm1", "__AVR_AT90PWM1__" },
9124 { "at90pwm2", "__AVR_AT90PWM2__" },
9125 { "at90pwm2b", "__AVR_AT90PWM2B__" },
9126 { "at90pwm3", "__AVR_AT90PWM3__" },
9127 { "at90pwm3b", "__AVR_AT90PWM3B__" },
9128 { "at90pwm81", "__AVR_AT90PWM81__" },
9129 { "ata5790", "__AVR_ATA5790__" },
9130 { "ata5795", "__AVR_ATA5795__" },
9131 { "atmega16", "__AVR_ATmega16__" },
9132 { "atmega16a", "__AVR_ATmega16A__" },
9133 { "atmega161", "__AVR_ATmega161__" },
9134 { "atmega162", "__AVR_ATmega162__" },
9135 { "atmega163", "__AVR_ATmega163__" },
9136 { "atmega164a", "__AVR_ATmega164A__" },
9137 { "atmega164p", "__AVR_ATmega164P__" },
9138 { "atmega164pa", "__AVR_ATmega164PA__" },
9139 { "atmega165", "__AVR_ATmega165__" },
9140 { "atmega165a", "__AVR_ATmega165A__" },
9141 { "atmega165p", "__AVR_ATmega165P__" },
9142 { "atmega165pa", "__AVR_ATmega165PA__" },
9143 { "atmega168", "__AVR_ATmega168__" },
9144 { "atmega168a", "__AVR_ATmega168A__" },
9145 { "atmega168p", "__AVR_ATmega168P__" },
9146 { "atmega168pa", "__AVR_ATmega168PA__" },
9147 { "atmega169", "__AVR_ATmega169__" },
9148 { "atmega169a", "__AVR_ATmega169A__" },
9149 { "atmega169p", "__AVR_ATmega169P__" },
9150 { "atmega169pa", "__AVR_ATmega169PA__" },
9151 { "atmega32", "__AVR_ATmega32__" },
9152 { "atmega32a", "__AVR_ATmega32A__" },
9153 { "atmega323", "__AVR_ATmega323__" },
9154 { "atmega324a", "__AVR_ATmega324A__" },
9155 { "atmega324p", "__AVR_ATmega324P__" },
9156 { "atmega324pa", "__AVR_ATmega324PA__" },
9157 { "atmega325", "__AVR_ATmega325__" },
9158 { "atmega325a", "__AVR_ATmega325A__" },
9159 { "atmega325p", "__AVR_ATmega325P__" },
9160 { "atmega325pa", "__AVR_ATmega325PA__" },
9161 { "atmega3250", "__AVR_ATmega3250__" },
9162 { "atmega3250a", "__AVR_ATmega3250A__" },
9163 { "atmega3250p", "__AVR_ATmega3250P__" },
9164 { "atmega3250pa", "__AVR_ATmega3250PA__" },
9165 { "atmega328", "__AVR_ATmega328__" },
9166 { "atmega328p", "__AVR_ATmega328P__" },
9167 { "atmega329", "__AVR_ATmega329__" },
9168 { "atmega329a", "__AVR_ATmega329A__" },
9169 { "atmega329p", "__AVR_ATmega329P__" },
9170 { "atmega329pa", "__AVR_ATmega329PA__" },
9171 { "atmega3290", "__AVR_ATmega3290__" },
9172 { "atmega3290a", "__AVR_ATmega3290A__" },
9173 { "atmega3290p", "__AVR_ATmega3290P__" },
9174 { "atmega3290pa", "__AVR_ATmega3290PA__" },
9175 { "atmega406", "__AVR_ATmega406__" },
9176 { "atmega64", "__AVR_ATmega64__" },
9177 { "atmega64a", "__AVR_ATmega64A__" },
9178 { "atmega640", "__AVR_ATmega640__" },
9179 { "atmega644", "__AVR_ATmega644__" },
9180 { "atmega644a", "__AVR_ATmega644A__" },
9181 { "atmega644p", "__AVR_ATmega644P__" },
9182 { "atmega644pa", "__AVR_ATmega644PA__" },
9183 { "atmega645", "__AVR_ATmega645__" },
9184 { "atmega645a", "__AVR_ATmega645A__" },
9185 { "atmega645p", "__AVR_ATmega645P__" },
9186 { "atmega649", "__AVR_ATmega649__" },
9187 { "atmega649a", "__AVR_ATmega649A__" },
9188 { "atmega649p", "__AVR_ATmega649P__" },
9189 { "atmega6450", "__AVR_ATmega6450__" },
9190 { "atmega6450a", "__AVR_ATmega6450A__" },
9191 { "atmega6450p", "__AVR_ATmega6450P__" },
9192 { "atmega6490", "__AVR_ATmega6490__" },
9193 { "atmega6490a", "__AVR_ATmega6490A__" },
9194 { "atmega6490p", "__AVR_ATmega6490P__" },
9195 { "atmega64rfr2", "__AVR_ATmega64RFR2__" },
9196 { "atmega644rfr2", "__AVR_ATmega644RFR2__" },
9197 { "atmega16hva", "__AVR_ATmega16HVA__" },
9198 { "atmega16hva2", "__AVR_ATmega16HVA2__" },
9199 { "atmega16hvb", "__AVR_ATmega16HVB__" },
9200 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" },
9201 { "atmega32hvb", "__AVR_ATmega32HVB__" },
9202 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" },
9203 { "atmega64hve", "__AVR_ATmega64HVE__" },
9204 { "at90can32", "__AVR_AT90CAN32__" },
9205 { "at90can64", "__AVR_AT90CAN64__" },
9206 { "at90pwm161", "__AVR_AT90PWM161__" },
9207 { "at90pwm216", "__AVR_AT90PWM216__" },
9208 { "at90pwm316", "__AVR_AT90PWM316__" },
9209 { "atmega32c1", "__AVR_ATmega32C1__" },
9210 { "atmega64c1", "__AVR_ATmega64C1__" },
9211 { "atmega16m1", "__AVR_ATmega16M1__" },
9212 { "atmega32m1", "__AVR_ATmega32M1__" },
9213 { "atmega64m1", "__AVR_ATmega64M1__" },
9214 { "atmega16u4", "__AVR_ATmega16U4__" },
9215 { "atmega32u4", "__AVR_ATmega32U4__" },
9216 { "atmega32u6", "__AVR_ATmega32U6__" },
9217 { "at90usb646", "__AVR_AT90USB646__" },
9218 { "at90usb647", "__AVR_AT90USB647__" },
9219 { "at90scr100", "__AVR_AT90SCR100__" },
9220 { "at94k", "__AVR_AT94K__" },
9221 { "m3000", "__AVR_AT000__" },
9222 { "atmega128", "__AVR_ATmega128__" },
9223 { "atmega128a", "__AVR_ATmega128A__" },
9224 { "atmega1280", "__AVR_ATmega1280__" },
9225 { "atmega1281", "__AVR_ATmega1281__" },
9226 { "atmega1284", "__AVR_ATmega1284__" },
9227 { "atmega1284p", "__AVR_ATmega1284P__" },
9228 { "atmega128rfa1", "__AVR_ATmega128RFA1__" },
9229 { "atmega128rfr2", "__AVR_ATmega128RFR2__" },
9230 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" },
9231 { "at90can128", "__AVR_AT90CAN128__" },
9232 { "at90usb1286", "__AVR_AT90USB1286__" },
9233 { "at90usb1287", "__AVR_AT90USB1287__" },
9234 { "atmega2560", "__AVR_ATmega2560__" },
9235 { "atmega2561", "__AVR_ATmega2561__" },
9236 { "atmega256rfr2", "__AVR_ATmega256RFR2__" },
9237 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" },
9238 { "atxmega16a4", "__AVR_ATxmega16A4__" },
9239 { "atxmega16a4u", "__AVR_ATxmega16a4U__" },
9240 { "atxmega16c4", "__AVR_ATxmega16C4__" },
9241 { "atxmega16d4", "__AVR_ATxmega16D4__" },
9242 { "atxmega32a4", "__AVR_ATxmega32A4__" },
9243 { "atxmega32a4u", "__AVR_ATxmega32A4U__" },
9244 { "atxmega32c4", "__AVR_ATxmega32C4__" },
9245 { "atxmega32d4", "__AVR_ATxmega32D4__" },
9246 { "atxmega32e5", "__AVR_ATxmega32E5__" },
9247 { "atxmega16e5", "__AVR_ATxmega16E5__" },
9248 { "atxmega8e5", "__AVR_ATxmega8E5__" },
9249 { "atxmega32x1", "__AVR_ATxmega32X1__" },
9250 { "atxmega64a3", "__AVR_ATxmega64A3__" },
9251 { "atxmega64a3u", "__AVR_ATxmega64A3U__" },
9252 { "atxmega64a4u", "__AVR_ATxmega64A4U__" },
9253 { "atxmega64b1", "__AVR_ATxmega64B1__" },
9254 { "atxmega64b3", "__AVR_ATxmega64B3__" },
9255 { "atxmega64c3", "__AVR_ATxmega64C3__" },
9256 { "atxmega64d3", "__AVR_ATxmega64D3__" },
9257 { "atxmega64d4", "__AVR_ATxmega64D4__" },
9258 { "atxmega64a1", "__AVR_ATxmega64A1__" },
9259 { "atxmega64a1u", "__AVR_ATxmega64A1U__" },
9260 { "atxmega128a3", "__AVR_ATxmega128A3__" },
9261 { "atxmega128a3u", "__AVR_ATxmega128A3U__" },
9262 { "atxmega128b1", "__AVR_ATxmega128B1__" },
9263 { "atxmega128b3", "__AVR_ATxmega128B3__" },
9264 { "atxmega128c3", "__AVR_ATxmega128C3__" },
9265 { "atxmega128d3", "__AVR_ATxmega128D3__" },
9266 { "atxmega128d4", "__AVR_ATxmega128D4__" },
9267 { "atxmega192a3", "__AVR_ATxmega192A3__" },
9268 { "atxmega192a3u", "__AVR_ATxmega192A3U__" },
9269 { "atxmega192c3", "__AVR_ATxmega192C3__" },
9270 { "atxmega192d3", "__AVR_ATxmega192D3__" },
9271 { "atxmega256a3", "__AVR_ATxmega256A3__" },
9272 { "atxmega256a3u", "__AVR_ATxmega256A3U__" },
9273 { "atxmega256a3b", "__AVR_ATxmega256A3B__" },
9274 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" },
9275 { "atxmega256c3", "__AVR_ATxmega256C3__" },
9276 { "atxmega256d3", "__AVR_ATxmega256D3__" },
9277 { "atxmega384c3", "__AVR_ATxmega384C3__" },
9278 { "atxmega384d3", "__AVR_ATxmega384D3__" },
9279 { "atxmega128a1", "__AVR_ATxmega128A1__" },
9280 { "atxmega128a1u", "__AVR_ATxmega128A1U__" },
9281 { "atxmega128a4u", "__AVR_ATxmega128a4U__" },
9282 { "attiny4", "__AVR_ATtiny4__" },
9283 { "attiny5", "__AVR_ATtiny5__" },
9284 { "attiny9", "__AVR_ATtiny9__" },
9285 { "attiny10", "__AVR_ATtiny10__" },
9286 { "attiny20", "__AVR_ATtiny20__" },
9287 { "attiny40", "__AVR_ATtiny40__" },
9288 { "attiny102", "__AVR_ATtiny102__" },
9289 { "attiny104", "__AVR_ATtiny104__" },
9293 class AVRTargetInfo : public TargetInfo {
9295 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
9296 : TargetInfo(Triple) {
9297 TLSSupported = false;
9307 DefaultAlignForAttributeAligned = 8;
9314 DoubleFormat = &llvm::APFloat::IEEEsingle();
9315 LongDoubleWidth = 32;
9316 LongDoubleAlign = 8;
9317 LongDoubleFormat = &llvm::APFloat::IEEEsingle();
9318 SizeType = UnsignedInt;
9319 PtrDiffType = SignedInt;
9320 IntPtrType = SignedInt;
9321 Char16Type = UnsignedInt;
9322 WCharType = SignedInt;
9323 WIntType = SignedInt;
9324 Char32Type = UnsignedLong;
9325 SigAtomicType = SignedChar;
9326 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64"
9327 "-f32:32:32-f64:64:64-n8");
9330 void getTargetDefines(const LangOptions &Opts,
9331 MacroBuilder &Builder) const override {
9332 Builder.defineMacro("AVR");
9333 Builder.defineMacro("__AVR");
9334 Builder.defineMacro("__AVR__");
9336 if (!this->CPU.empty()) {
9337 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(),
9338 [&](const MCUInfo &Info) { return Info.Name == this->CPU; });
9340 if (It != AVRMcus.end())
9341 Builder.defineMacro(It->DefineName);
9345 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
9349 BuiltinVaListKind getBuiltinVaListKind() const override {
9350 return TargetInfo::VoidPtrBuiltinVaList;
9353 const char *getClobbers() const override {
9357 ArrayRef<const char *> getGCCRegNames() const override {
9358 static const char * const GCCRegNames[] = {
9359 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
9360 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
9361 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
9362 "r24", "r25", "X", "Y", "Z", "SP"
9364 return llvm::makeArrayRef(GCCRegNames);
9367 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
9371 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
9372 static const TargetInfo::AddlRegName AddlRegNames[] = {
9373 { { "r26", "r27"}, 26 },
9374 { { "r28", "r29"}, 27 },
9375 { { "r30", "r31"}, 28 },
9376 { { "SPL", "SPH"}, 29 },
9378 return llvm::makeArrayRef(AddlRegNames);
9381 bool validateAsmConstraint(const char *&Name,
9382 TargetInfo::ConstraintInfo &Info) const override {
9383 // There aren't any multi-character AVR specific constraints.
9384 if (StringRef(Name).size() > 1) return false;
9387 default: return false;
9388 case 'a': // Simple upper registers
9389 case 'b': // Base pointer registers pairs
9390 case 'd': // Upper register
9391 case 'l': // Lower registers
9392 case 'e': // Pointer register pairs
9393 case 'q': // Stack pointer register
9394 case 'r': // Any register
9395 case 'w': // Special upper register pairs
9396 case 't': // Temporary register
9397 case 'x': case 'X': // Pointer register pair X
9398 case 'y': case 'Y': // Pointer register pair Y
9399 case 'z': case 'Z': // Pointer register pair Z
9400 Info.setAllowsRegister();
9402 case 'I': // 6-bit positive integer constant
9403 Info.setRequiresImmediate(0, 63);
9405 case 'J': // 6-bit negative integer constant
9406 Info.setRequiresImmediate(-63, 0);
9408 case 'K': // Integer constant (Range: 2)
9409 Info.setRequiresImmediate(2);
9411 case 'L': // Integer constant (Range: 0)
9412 Info.setRequiresImmediate(0);
9414 case 'M': // 8-bit integer constant
9415 Info.setRequiresImmediate(0, 0xff);
9417 case 'N': // Integer constant (Range: -1)
9418 Info.setRequiresImmediate(-1);
9420 case 'O': // Integer constant (Range: 8, 16, 24)
9421 Info.setRequiresImmediate({8, 16, 24});
9423 case 'P': // Integer constant (Range: 1)
9424 Info.setRequiresImmediate(1);
9426 case 'R': // Integer constant (Range: -6 to 5)
9427 Info.setRequiresImmediate(-6, 5);
9429 case 'G': // Floating point constant
9430 case 'Q': // A memory address based on Y or Z pointer with displacement.
9437 IntType getIntTypeByWidth(unsigned BitWidth,
9438 bool IsSigned) const final {
9439 // AVR prefers int for 16-bit integers.
9440 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt)
9441 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
9444 IntType getLeastIntTypeByWidth(unsigned BitWidth,
9445 bool IsSigned) const final {
9446 // AVR uses int for int_least16_t and int_fast16_t.
9447 return BitWidth == 16
9448 ? (IsSigned ? SignedInt : UnsignedInt)
9449 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
9452 bool setCPU(const std::string &Name) override {
9453 bool IsFamily = llvm::StringSwitch<bool>(Name)
9456 .Case("avr25", true)
9458 .Case("avr31", true)
9459 .Case("avr35", true)
9462 .Case("avr51", true)
9464 .Case("avrxmega1", true)
9465 .Case("avrxmega2", true)
9466 .Case("avrxmega3", true)
9467 .Case("avrxmega4", true)
9468 .Case("avrxmega5", true)
9469 .Case("avrxmega6", true)
9470 .Case("avrxmega7", true)
9471 .Case("avrtiny", true)
9474 if (IsFamily) this->CPU = Name;
9476 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(),
9477 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end();
9479 if (IsMCU) this->CPU = Name;
9481 return IsFamily || IsMCU;
9488 } // end anonymous namespace
9490 //===----------------------------------------------------------------------===//
9492 //===----------------------------------------------------------------------===//
9494 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
9495 const TargetOptions &Opts) {
9496 llvm::Triple::OSType os = Triple.getOS();
9498 switch (Triple.getArch()) {
9502 case llvm::Triple::xcore:
9503 return new XCoreTargetInfo(Triple, Opts);
9505 case llvm::Triple::hexagon:
9506 return new HexagonTargetInfo(Triple, Opts);
9508 case llvm::Triple::lanai:
9509 return new LanaiTargetInfo(Triple, Opts);
9511 case llvm::Triple::aarch64:
9512 if (Triple.isOSDarwin())
9513 return new DarwinAArch64TargetInfo(Triple, Opts);
9516 case llvm::Triple::CloudABI:
9517 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts);
9518 case llvm::Triple::FreeBSD:
9519 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9520 case llvm::Triple::Fuchsia:
9521 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9522 case llvm::Triple::Linux:
9523 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9524 case llvm::Triple::NetBSD:
9525 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9526 case llvm::Triple::OpenBSD:
9527 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9528 case llvm::Triple::Win32:
9529 return new MicrosoftARM64TargetInfo(Triple, Opts);
9531 return new AArch64leTargetInfo(Triple, Opts);
9534 case llvm::Triple::aarch64_be:
9536 case llvm::Triple::FreeBSD:
9537 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9538 case llvm::Triple::Fuchsia:
9539 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9540 case llvm::Triple::Linux:
9541 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9542 case llvm::Triple::NetBSD:
9543 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9545 return new AArch64beTargetInfo(Triple, Opts);
9548 case llvm::Triple::arm:
9549 case llvm::Triple::thumb:
9550 if (Triple.isOSBinFormatMachO())
9551 return new DarwinARMTargetInfo(Triple, Opts);
9554 case llvm::Triple::CloudABI:
9555 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts);
9556 case llvm::Triple::Linux:
9557 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts);
9558 case llvm::Triple::FreeBSD:
9559 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
9560 case llvm::Triple::NetBSD:
9561 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
9562 case llvm::Triple::OpenBSD:
9563 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
9564 case llvm::Triple::Bitrig:
9565 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts);
9566 case llvm::Triple::RTEMS:
9567 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts);
9568 case llvm::Triple::NaCl:
9569 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts);
9570 case llvm::Triple::Win32:
9571 switch (Triple.getEnvironment()) {
9572 case llvm::Triple::Cygnus:
9573 return new CygwinARMTargetInfo(Triple, Opts);
9574 case llvm::Triple::GNU:
9575 return new MinGWARMTargetInfo(Triple, Opts);
9576 case llvm::Triple::Itanium:
9577 return new ItaniumWindowsARMleTargetInfo(Triple, Opts);
9578 case llvm::Triple::MSVC:
9579 default: // Assume MSVC for unknown environments
9580 return new MicrosoftARMleTargetInfo(Triple, Opts);
9583 return new ARMleTargetInfo(Triple, Opts);
9586 case llvm::Triple::armeb:
9587 case llvm::Triple::thumbeb:
9588 if (Triple.isOSDarwin())
9589 return new DarwinARMTargetInfo(Triple, Opts);
9592 case llvm::Triple::Linux:
9593 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9594 case llvm::Triple::FreeBSD:
9595 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9596 case llvm::Triple::NetBSD:
9597 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9598 case llvm::Triple::OpenBSD:
9599 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9600 case llvm::Triple::Bitrig:
9601 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9602 case llvm::Triple::RTEMS:
9603 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9604 case llvm::Triple::NaCl:
9605 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9607 return new ARMbeTargetInfo(Triple, Opts);
9610 case llvm::Triple::avr:
9611 return new AVRTargetInfo(Triple, Opts);
9612 case llvm::Triple::bpfeb:
9613 case llvm::Triple::bpfel:
9614 return new BPFTargetInfo(Triple, Opts);
9616 case llvm::Triple::msp430:
9617 return new MSP430TargetInfo(Triple, Opts);
9619 case llvm::Triple::nios2:
9620 return new LinuxTargetInfo<Nios2TargetInfo>(Triple, Opts);
9622 case llvm::Triple::mips:
9624 case llvm::Triple::Linux:
9625 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9626 case llvm::Triple::RTEMS:
9627 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9628 case llvm::Triple::FreeBSD:
9629 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9630 case llvm::Triple::NetBSD:
9631 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9633 return new MipsTargetInfo(Triple, Opts);
9636 case llvm::Triple::mipsel:
9638 case llvm::Triple::Linux:
9639 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9640 case llvm::Triple::RTEMS:
9641 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9642 case llvm::Triple::FreeBSD:
9643 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9644 case llvm::Triple::NetBSD:
9645 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9646 case llvm::Triple::NaCl:
9647 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts);
9649 return new MipsTargetInfo(Triple, Opts);
9652 case llvm::Triple::mips64:
9654 case llvm::Triple::Linux:
9655 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9656 case llvm::Triple::RTEMS:
9657 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9658 case llvm::Triple::FreeBSD:
9659 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9660 case llvm::Triple::NetBSD:
9661 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9662 case llvm::Triple::OpenBSD:
9663 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9665 return new MipsTargetInfo(Triple, Opts);
9668 case llvm::Triple::mips64el:
9670 case llvm::Triple::Linux:
9671 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9672 case llvm::Triple::RTEMS:
9673 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9674 case llvm::Triple::FreeBSD:
9675 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9676 case llvm::Triple::NetBSD:
9677 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9678 case llvm::Triple::OpenBSD:
9679 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9681 return new MipsTargetInfo(Triple, Opts);
9684 case llvm::Triple::le32:
9686 case llvm::Triple::NaCl:
9687 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts);
9692 case llvm::Triple::le64:
9693 return new Le64TargetInfo(Triple, Opts);
9695 case llvm::Triple::ppc:
9696 if (Triple.isOSDarwin())
9697 return new DarwinPPC32TargetInfo(Triple, Opts);
9699 case llvm::Triple::Linux:
9700 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts);
9701 case llvm::Triple::FreeBSD:
9702 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
9703 case llvm::Triple::NetBSD:
9704 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
9705 case llvm::Triple::OpenBSD:
9706 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
9707 case llvm::Triple::RTEMS:
9708 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts);
9710 return new PPC32TargetInfo(Triple, Opts);
9713 case llvm::Triple::ppc64:
9714 if (Triple.isOSDarwin())
9715 return new DarwinPPC64TargetInfo(Triple, Opts);
9717 case llvm::Triple::Linux:
9718 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
9719 case llvm::Triple::Lv2:
9720 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts);
9721 case llvm::Triple::FreeBSD:
9722 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
9723 case llvm::Triple::NetBSD:
9724 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
9726 return new PPC64TargetInfo(Triple, Opts);
9729 case llvm::Triple::ppc64le:
9731 case llvm::Triple::Linux:
9732 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
9733 case llvm::Triple::NetBSD:
9734 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
9736 return new PPC64TargetInfo(Triple, Opts);
9739 case llvm::Triple::nvptx:
9740 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32);
9741 case llvm::Triple::nvptx64:
9742 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64);
9744 case llvm::Triple::amdgcn:
9745 case llvm::Triple::r600:
9746 return new AMDGPUTargetInfo(Triple, Opts);
9748 case llvm::Triple::sparc:
9750 case llvm::Triple::Linux:
9751 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9752 case llvm::Triple::Solaris:
9753 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9754 case llvm::Triple::NetBSD:
9755 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9756 case llvm::Triple::OpenBSD:
9757 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9758 case llvm::Triple::RTEMS:
9759 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9761 return new SparcV8TargetInfo(Triple, Opts);
9764 // The 'sparcel' architecture copies all the above cases except for Solaris.
9765 case llvm::Triple::sparcel:
9767 case llvm::Triple::Linux:
9768 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9769 case llvm::Triple::NetBSD:
9770 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9771 case llvm::Triple::OpenBSD:
9772 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9773 case llvm::Triple::RTEMS:
9774 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9776 return new SparcV8elTargetInfo(Triple, Opts);
9779 case llvm::Triple::sparcv9:
9781 case llvm::Triple::Linux:
9782 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9783 case llvm::Triple::Solaris:
9784 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9785 case llvm::Triple::NetBSD:
9786 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9787 case llvm::Triple::OpenBSD:
9788 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9789 case llvm::Triple::FreeBSD:
9790 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9792 return new SparcV9TargetInfo(Triple, Opts);
9795 case llvm::Triple::systemz:
9797 case llvm::Triple::Linux:
9798 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts);
9800 return new SystemZTargetInfo(Triple, Opts);
9803 case llvm::Triple::tce:
9804 return new TCETargetInfo(Triple, Opts);
9806 case llvm::Triple::tcele:
9807 return new TCELETargetInfo(Triple, Opts);
9809 case llvm::Triple::x86:
9810 if (Triple.isOSDarwin())
9811 return new DarwinI386TargetInfo(Triple, Opts);
9814 case llvm::Triple::Ananas:
9815 return new AnanasTargetInfo<X86_32TargetInfo>(Triple, Opts);
9816 case llvm::Triple::CloudABI:
9817 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts);
9818 case llvm::Triple::Linux: {
9819 switch (Triple.getEnvironment()) {
9821 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts);
9822 case llvm::Triple::Android:
9823 return new AndroidX86_32TargetInfo(Triple, Opts);
9826 case llvm::Triple::DragonFly:
9827 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
9828 case llvm::Triple::NetBSD:
9829 return new NetBSDI386TargetInfo(Triple, Opts);
9830 case llvm::Triple::OpenBSD:
9831 return new OpenBSDI386TargetInfo(Triple, Opts);
9832 case llvm::Triple::Bitrig:
9833 return new BitrigI386TargetInfo(Triple, Opts);
9834 case llvm::Triple::FreeBSD:
9835 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
9836 case llvm::Triple::KFreeBSD:
9837 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
9838 case llvm::Triple::Minix:
9839 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts);
9840 case llvm::Triple::Solaris:
9841 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts);
9842 case llvm::Triple::Win32: {
9843 switch (Triple.getEnvironment()) {
9844 case llvm::Triple::Cygnus:
9845 return new CygwinX86_32TargetInfo(Triple, Opts);
9846 case llvm::Triple::GNU:
9847 return new MinGWX86_32TargetInfo(Triple, Opts);
9848 case llvm::Triple::Itanium:
9849 case llvm::Triple::MSVC:
9850 default: // Assume MSVC for unknown environments
9851 return new MicrosoftX86_32TargetInfo(Triple, Opts);
9854 case llvm::Triple::Haiku:
9855 return new HaikuX86_32TargetInfo(Triple, Opts);
9856 case llvm::Triple::RTEMS:
9857 return new RTEMSX86_32TargetInfo(Triple, Opts);
9858 case llvm::Triple::NaCl:
9859 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts);
9860 case llvm::Triple::ELFIAMCU:
9861 return new MCUX86_32TargetInfo(Triple, Opts);
9863 return new X86_32TargetInfo(Triple, Opts);
9866 case llvm::Triple::x86_64:
9867 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
9868 return new DarwinX86_64TargetInfo(Triple, Opts);
9871 case llvm::Triple::Ananas:
9872 return new AnanasTargetInfo<X86_64TargetInfo>(Triple, Opts);
9873 case llvm::Triple::CloudABI:
9874 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts);
9875 case llvm::Triple::Linux: {
9876 switch (Triple.getEnvironment()) {
9878 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts);
9879 case llvm::Triple::Android:
9880 return new AndroidX86_64TargetInfo(Triple, Opts);
9883 case llvm::Triple::DragonFly:
9884 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9885 case llvm::Triple::NetBSD:
9886 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9887 case llvm::Triple::OpenBSD:
9888 return new OpenBSDX86_64TargetInfo(Triple, Opts);
9889 case llvm::Triple::Bitrig:
9890 return new BitrigX86_64TargetInfo(Triple, Opts);
9891 case llvm::Triple::FreeBSD:
9892 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9893 case llvm::Triple::Fuchsia:
9894 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts);
9895 case llvm::Triple::KFreeBSD:
9896 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9897 case llvm::Triple::Solaris:
9898 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts);
9899 case llvm::Triple::Win32: {
9900 switch (Triple.getEnvironment()) {
9901 case llvm::Triple::Cygnus:
9902 return new CygwinX86_64TargetInfo(Triple, Opts);
9903 case llvm::Triple::GNU:
9904 return new MinGWX86_64TargetInfo(Triple, Opts);
9905 case llvm::Triple::MSVC:
9906 default: // Assume MSVC for unknown environments
9907 return new MicrosoftX86_64TargetInfo(Triple, Opts);
9910 case llvm::Triple::Haiku:
9911 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts);
9912 case llvm::Triple::NaCl:
9913 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts);
9914 case llvm::Triple::PS4:
9915 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts);
9917 return new X86_64TargetInfo(Triple, Opts);
9920 case llvm::Triple::spir: {
9921 if (Triple.getOS() != llvm::Triple::UnknownOS ||
9922 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
9924 return new SPIR32TargetInfo(Triple, Opts);
9926 case llvm::Triple::spir64: {
9927 if (Triple.getOS() != llvm::Triple::UnknownOS ||
9928 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
9930 return new SPIR64TargetInfo(Triple, Opts);
9932 case llvm::Triple::wasm32:
9933 if (Triple.getSubArch() != llvm::Triple::NoSubArch ||
9934 Triple.getVendor() != llvm::Triple::UnknownVendor ||
9935 Triple.getOS() != llvm::Triple::UnknownOS ||
9936 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment ||
9937 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm()))
9939 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts);
9940 case llvm::Triple::wasm64:
9941 if (Triple.getSubArch() != llvm::Triple::NoSubArch ||
9942 Triple.getVendor() != llvm::Triple::UnknownVendor ||
9943 Triple.getOS() != llvm::Triple::UnknownOS ||
9944 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment ||
9945 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm()))
9947 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts);
9949 case llvm::Triple::renderscript32:
9950 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts);
9951 case llvm::Triple::renderscript64:
9952 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts);
9956 /// CreateTargetInfo - Return the target info object for the specified target
9959 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
9960 const std::shared_ptr<TargetOptions> &Opts) {
9961 llvm::Triple Triple(Opts->Triple);
9963 // Construct the target
9964 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts));
9966 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
9969 Target->TargetOpts = Opts;
9971 // Set the target CPU if specified.
9972 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
9973 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
9977 // Set the target ABI if specified.
9978 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
9979 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
9983 // Set the fp math unit.
9984 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
9985 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
9989 // Compute the default target features, we need the target to handle this
9990 // because features may have dependencies on one another.
9991 llvm::StringMap<bool> Features;
9992 if (!Target->initFeatureMap(Features, Diags, Opts->CPU,
9993 Opts->FeaturesAsWritten))
9996 // Add the features to the compile options.
9997 Opts->Features.clear();
9998 for (const auto &F : Features)
9999 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str());
10001 if (!Target->handleTargetFeatures(Opts->Features, Diags))
10004 Target->setSupportedOpenCLOpts();
10005 Target->setOpenCLExtensionOpts();
10007 if (!Target->validateTarget(Diags))
10010 return Target.release();