1 //===--- Targets.cpp - Implement target feature support -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "clang/Basic/Version.h"
23 #include "llvm/ADT/APFloat.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/ADT/Triple.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/TargetParser.h"
35 using namespace clang;
37 //===----------------------------------------------------------------------===//
38 // Common code shared among targets.
39 //===----------------------------------------------------------------------===//
41 /// DefineStd - Define a macro name and standard variants. For example if
42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
45 const LangOptions &Opts) {
46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
49 // in the user's namespace.
51 Builder.defineMacro(MacroName);
54 Builder.defineMacro("__" + MacroName);
57 Builder.defineMacro("__" + MacroName + "__");
60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
62 Builder.defineMacro("__" + CPUName);
63 Builder.defineMacro("__" + CPUName + "__");
65 Builder.defineMacro("__tune_" + CPUName + "__");
68 //===----------------------------------------------------------------------===//
69 // Defines specific to certain operating systems.
70 //===----------------------------------------------------------------------===//
73 template<typename TgtInfo>
74 class OSTargetInfo : public TgtInfo {
76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
77 MacroBuilder &Builder) const=0;
79 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
80 void getTargetDefines(const LangOptions &Opts,
81 MacroBuilder &Builder) const override {
82 TgtInfo::getTargetDefines(Opts, Builder);
83 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
89 template <typename Target>
90 class CloudABITargetInfo : public OSTargetInfo<Target> {
92 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
93 MacroBuilder &Builder) const override {
94 Builder.defineMacro("__CloudABI__");
95 Builder.defineMacro("__ELF__");
97 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
98 Builder.defineMacro("__STDC_ISO_10646__", "201206L");
99 Builder.defineMacro("__STDC_UTF_16__");
100 Builder.defineMacro("__STDC_UTF_32__");
104 CloudABITargetInfo(const llvm::Triple &Triple)
105 : OSTargetInfo<Target>(Triple) {
106 this->UserLabelPrefix = "";
110 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
111 const llvm::Triple &Triple,
112 StringRef &PlatformName,
113 VersionTuple &PlatformMinVersion) {
114 Builder.defineMacro("__APPLE_CC__", "6000");
115 Builder.defineMacro("__APPLE__");
116 Builder.defineMacro("OBJC_NEW_PROPERTIES");
117 // AddressSanitizer doesn't play well with source fortification, which is on
118 // by default on Darwin.
119 if (Opts.Sanitize.has(SanitizerKind::Address))
120 Builder.defineMacro("_FORTIFY_SOURCE", "0");
122 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode.
124 // __weak is always defined, for use in blocks and with objc pointers.
125 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
126 Builder.defineMacro("__strong", "");
127 Builder.defineMacro("__unsafe_unretained", "");
131 Builder.defineMacro("__STATIC__");
133 Builder.defineMacro("__DYNAMIC__");
135 if (Opts.POSIXThreads)
136 Builder.defineMacro("_REENTRANT");
138 // Get the platform type and version number from the triple.
139 unsigned Maj, Min, Rev;
140 if (Triple.isMacOSX()) {
141 Triple.getMacOSXVersion(Maj, Min, Rev);
142 PlatformName = "macosx";
144 Triple.getOSVersion(Maj, Min, Rev);
145 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
148 // If -target arch-pc-win32-macho option specified, we're
149 // generating code for Win32 ABI. No need to emit
150 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
151 if (PlatformName == "win32") {
152 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
156 // Set the appropriate OS version define.
157 if (Triple.isiOS()) {
158 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
161 Str[1] = '0' + (Min / 10);
162 Str[2] = '0' + (Min % 10);
163 Str[3] = '0' + (Rev / 10);
164 Str[4] = '0' + (Rev % 10);
167 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str);
169 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
172 } else if (Triple.isWatchOS()) {
173 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
176 Str[1] = '0' + (Min / 10);
177 Str[2] = '0' + (Min % 10);
178 Str[3] = '0' + (Rev / 10);
179 Str[4] = '0' + (Rev % 10);
181 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str);
182 } else if (Triple.isMacOSX()) {
183 // Note that the Driver allows versions which aren't representable in the
184 // define (because we only get a single digit for the minor and micro
185 // revision numbers). So, we limit them to the maximum representable
187 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
189 if (Maj < 10 || (Maj == 10 && Min < 10)) {
190 Str[0] = '0' + (Maj / 10);
191 Str[1] = '0' + (Maj % 10);
192 Str[2] = '0' + std::min(Min, 9U);
193 Str[3] = '0' + std::min(Rev, 9U);
196 // Handle versions > 10.9.
197 Str[0] = '0' + (Maj / 10);
198 Str[1] = '0' + (Maj % 10);
199 Str[2] = '0' + (Min / 10);
200 Str[3] = '0' + (Min % 10);
201 Str[4] = '0' + (Rev / 10);
202 Str[5] = '0' + (Rev % 10);
205 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
208 // Tell users about the kernel if there is one.
209 if (Triple.isOSDarwin())
210 Builder.defineMacro("__MACH__");
212 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
215 template<typename Target>
216 class DarwinTargetInfo : public OSTargetInfo<Target> {
218 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
219 MacroBuilder &Builder) const override {
220 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
221 this->PlatformMinVersion);
225 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
226 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
227 this->MCountName = "\01mcount";
230 std::string isValidSectionSpecifier(StringRef SR) const override {
231 // Let MCSectionMachO validate this.
232 StringRef Segment, Section;
233 unsigned TAA, StubSize;
235 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
236 TAA, HasTAA, StubSize);
239 const char *getStaticInitSectionSpecifier() const override {
240 // FIXME: We should return 0 when building kexts.
241 return "__TEXT,__StaticInit,regular,pure_instructions";
244 /// Darwin does not support protected visibility. Darwin's "default"
245 /// is very similar to ELF's "protected"; Darwin requires a "weak"
246 /// attribute on declarations that can be dynamically replaced.
247 bool hasProtectedVisibility() const override {
253 // DragonFlyBSD Target
254 template<typename Target>
255 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
257 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
258 MacroBuilder &Builder) const override {
259 // DragonFly defines; list based off of gcc output
260 Builder.defineMacro("__DragonFly__");
261 Builder.defineMacro("__DragonFly_cc_version", "100001");
262 Builder.defineMacro("__ELF__");
263 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
264 Builder.defineMacro("__tune_i386__");
265 DefineStd(Builder, "unix", Opts);
268 DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
269 : OSTargetInfo<Target>(Triple) {
270 this->UserLabelPrefix = "";
272 switch (Triple.getArch()) {
274 case llvm::Triple::x86:
275 case llvm::Triple::x86_64:
276 this->MCountName = ".mcount";
283 template<typename Target>
284 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
286 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
287 MacroBuilder &Builder) const override {
288 // FreeBSD defines; list based off of gcc output
290 unsigned Release = Triple.getOSMajorVersion();
294 Builder.defineMacro("__FreeBSD__", Twine(Release));
295 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
296 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
297 DefineStd(Builder, "unix", Opts);
298 Builder.defineMacro("__ELF__");
300 // On FreeBSD, wchar_t contains the number of the code point as
301 // used by the character set of the locale. These character sets are
302 // not necessarily a superset of ASCII.
304 // FIXME: This is wrong; the macro refers to the numerical values
305 // of wchar_t *literals*, which are not locale-dependent. However,
306 // FreeBSD systems apparently depend on us getting this wrong, and
307 // setting this to 1 is conforming even if all the basic source
308 // character literals have the same encoding as char and wchar_t.
309 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
312 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
313 this->UserLabelPrefix = "";
315 switch (Triple.getArch()) {
317 case llvm::Triple::x86:
318 case llvm::Triple::x86_64:
319 this->MCountName = ".mcount";
321 case llvm::Triple::mips:
322 case llvm::Triple::mipsel:
323 case llvm::Triple::ppc:
324 case llvm::Triple::ppc64:
325 case llvm::Triple::ppc64le:
326 this->MCountName = "_mcount";
328 case llvm::Triple::arm:
329 this->MCountName = "__mcount";
335 // GNU/kFreeBSD Target
336 template<typename Target>
337 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
339 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
340 MacroBuilder &Builder) const override {
341 // GNU/kFreeBSD defines; list based off of gcc output
343 DefineStd(Builder, "unix", Opts);
344 Builder.defineMacro("__FreeBSD_kernel__");
345 Builder.defineMacro("__GLIBC__");
346 Builder.defineMacro("__ELF__");
347 if (Opts.POSIXThreads)
348 Builder.defineMacro("_REENTRANT");
350 Builder.defineMacro("_GNU_SOURCE");
353 KFreeBSDTargetInfo(const llvm::Triple &Triple)
354 : OSTargetInfo<Target>(Triple) {
355 this->UserLabelPrefix = "";
360 template<typename Target>
361 class MinixTargetInfo : public OSTargetInfo<Target> {
363 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
364 MacroBuilder &Builder) const override {
367 Builder.defineMacro("__minix", "3");
368 Builder.defineMacro("_EM_WSIZE", "4");
369 Builder.defineMacro("_EM_PSIZE", "4");
370 Builder.defineMacro("_EM_SSIZE", "2");
371 Builder.defineMacro("_EM_LSIZE", "4");
372 Builder.defineMacro("_EM_FSIZE", "4");
373 Builder.defineMacro("_EM_DSIZE", "8");
374 Builder.defineMacro("__ELF__");
375 DefineStd(Builder, "unix", Opts);
378 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
379 this->UserLabelPrefix = "";
384 template<typename Target>
385 class LinuxTargetInfo : public OSTargetInfo<Target> {
387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
388 MacroBuilder &Builder) const override {
389 // Linux defines; list based off of gcc output
390 DefineStd(Builder, "unix", Opts);
391 DefineStd(Builder, "linux", Opts);
392 Builder.defineMacro("__gnu_linux__");
393 Builder.defineMacro("__ELF__");
394 if (Triple.isAndroid()) {
395 Builder.defineMacro("__ANDROID__", "1");
396 unsigned Maj, Min, Rev;
397 Triple.getEnvironmentVersion(Maj, Min, Rev);
398 this->PlatformName = "android";
399 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
401 if (Opts.POSIXThreads)
402 Builder.defineMacro("_REENTRANT");
404 Builder.defineMacro("_GNU_SOURCE");
407 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
408 this->UserLabelPrefix = "";
409 this->WIntType = TargetInfo::UnsignedInt;
411 switch (Triple.getArch()) {
414 case llvm::Triple::ppc:
415 case llvm::Triple::ppc64:
416 case llvm::Triple::ppc64le:
417 this->MCountName = "_mcount";
422 const char *getStaticInitSectionSpecifier() const override {
423 return ".text.startup";
428 template<typename Target>
429 class NetBSDTargetInfo : public OSTargetInfo<Target> {
431 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
432 MacroBuilder &Builder) const override {
433 // NetBSD defines; list based off of gcc output
434 Builder.defineMacro("__NetBSD__");
435 Builder.defineMacro("__unix__");
436 Builder.defineMacro("__ELF__");
437 if (Opts.POSIXThreads)
438 Builder.defineMacro("_POSIX_THREADS");
440 switch (Triple.getArch()) {
443 case llvm::Triple::arm:
444 case llvm::Triple::armeb:
445 case llvm::Triple::thumb:
446 case llvm::Triple::thumbeb:
447 Builder.defineMacro("__ARM_DWARF_EH__");
452 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
453 this->UserLabelPrefix = "";
454 this->MCountName = "_mcount";
459 template<typename Target>
460 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
462 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
463 MacroBuilder &Builder) const override {
464 // OpenBSD defines; list based off of gcc output
466 Builder.defineMacro("__OpenBSD__");
467 DefineStd(Builder, "unix", Opts);
468 Builder.defineMacro("__ELF__");
469 if (Opts.POSIXThreads)
470 Builder.defineMacro("_REENTRANT");
473 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
474 this->UserLabelPrefix = "";
475 this->TLSSupported = false;
477 switch (Triple.getArch()) {
479 case llvm::Triple::x86:
480 case llvm::Triple::x86_64:
481 case llvm::Triple::arm:
482 case llvm::Triple::sparc:
483 this->MCountName = "__mcount";
485 case llvm::Triple::mips64:
486 case llvm::Triple::mips64el:
487 case llvm::Triple::ppc:
488 case llvm::Triple::sparcv9:
489 this->MCountName = "_mcount";
496 template<typename Target>
497 class BitrigTargetInfo : public OSTargetInfo<Target> {
499 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
500 MacroBuilder &Builder) const override {
501 // Bitrig defines; list based off of gcc output
503 Builder.defineMacro("__Bitrig__");
504 DefineStd(Builder, "unix", Opts);
505 Builder.defineMacro("__ELF__");
506 if (Opts.POSIXThreads)
507 Builder.defineMacro("_REENTRANT");
509 switch (Triple.getArch()) {
512 case llvm::Triple::arm:
513 case llvm::Triple::armeb:
514 case llvm::Triple::thumb:
515 case llvm::Triple::thumbeb:
516 Builder.defineMacro("__ARM_DWARF_EH__");
521 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
522 this->UserLabelPrefix = "";
523 this->MCountName = "__mcount";
528 template<typename Target>
529 class PSPTargetInfo : public OSTargetInfo<Target> {
531 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
532 MacroBuilder &Builder) const override {
533 // PSP defines; list based on the output of the pspdev gcc toolchain.
534 Builder.defineMacro("PSP");
535 Builder.defineMacro("_PSP");
536 Builder.defineMacro("__psp__");
537 Builder.defineMacro("__ELF__");
540 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
541 this->UserLabelPrefix = "";
546 template<typename Target>
547 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
549 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
550 MacroBuilder &Builder) const override {
552 Builder.defineMacro("__PPC__");
553 Builder.defineMacro("__PPU__");
554 Builder.defineMacro("__CELLOS_LV2__");
555 Builder.defineMacro("__ELF__");
556 Builder.defineMacro("__LP32__");
557 Builder.defineMacro("_ARCH_PPC64");
558 Builder.defineMacro("__powerpc64__");
561 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
562 this->UserLabelPrefix = "";
563 this->LongWidth = this->LongAlign = 32;
564 this->PointerWidth = this->PointerAlign = 32;
565 this->IntMaxType = TargetInfo::SignedLongLong;
566 this->Int64Type = TargetInfo::SignedLongLong;
567 this->SizeType = TargetInfo::UnsignedInt;
568 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64";
572 template <typename Target>
573 class PS4OSTargetInfo : public OSTargetInfo<Target> {
575 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
576 MacroBuilder &Builder) const override {
577 Builder.defineMacro("__FreeBSD__", "9");
578 Builder.defineMacro("__FreeBSD_cc_version", "900001");
579 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
580 DefineStd(Builder, "unix", Opts);
581 Builder.defineMacro("__ELF__");
582 Builder.defineMacro("__PS4__");
585 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
586 this->WCharType = this->UnsignedShort;
588 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits).
589 this->MaxTLSAlign = 256;
590 this->UserLabelPrefix = "";
592 switch (Triple.getArch()) {
594 case llvm::Triple::x86_64:
595 this->MCountName = ".mcount";
602 template<typename Target>
603 class SolarisTargetInfo : public OSTargetInfo<Target> {
605 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
606 MacroBuilder &Builder) const override {
607 DefineStd(Builder, "sun", Opts);
608 DefineStd(Builder, "unix", Opts);
609 Builder.defineMacro("__ELF__");
610 Builder.defineMacro("__svr4__");
611 Builder.defineMacro("__SVR4");
612 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
613 // newer, but to 500 for everything else. feature_test.h has a check to
614 // ensure that you are not using C99 with an old version of X/Open or C89
615 // with a new version.
617 Builder.defineMacro("_XOPEN_SOURCE", "600");
619 Builder.defineMacro("_XOPEN_SOURCE", "500");
621 Builder.defineMacro("__C99FEATURES__");
622 Builder.defineMacro("_LARGEFILE_SOURCE");
623 Builder.defineMacro("_LARGEFILE64_SOURCE");
624 Builder.defineMacro("__EXTENSIONS__");
625 Builder.defineMacro("_REENTRANT");
628 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
629 this->UserLabelPrefix = "";
630 this->WCharType = this->SignedInt;
631 // FIXME: WIntType should be SignedLong
636 template<typename Target>
637 class WindowsTargetInfo : public OSTargetInfo<Target> {
639 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
640 MacroBuilder &Builder) const override {
641 Builder.defineMacro("_WIN32");
643 void getVisualStudioDefines(const LangOptions &Opts,
644 MacroBuilder &Builder) const {
645 if (Opts.CPlusPlus) {
647 Builder.defineMacro("_CPPRTTI");
649 if (Opts.CXXExceptions)
650 Builder.defineMacro("_CPPUNWIND");
654 Builder.defineMacro("__BOOL_DEFINED");
656 if (!Opts.CharIsSigned)
657 Builder.defineMacro("_CHAR_UNSIGNED");
659 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
660 // but it works for now.
661 if (Opts.POSIXThreads)
662 Builder.defineMacro("_MT");
664 if (Opts.MSCompatibilityVersion) {
665 Builder.defineMacro("_MSC_VER",
666 Twine(Opts.MSCompatibilityVersion / 100000));
667 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
668 // FIXME We cannot encode the revision information into 32-bits
669 Builder.defineMacro("_MSC_BUILD", Twine(1));
671 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
672 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
675 if (Opts.MicrosoftExt) {
676 Builder.defineMacro("_MSC_EXTENSIONS");
678 if (Opts.CPlusPlus11) {
679 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
680 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
681 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
685 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
689 WindowsTargetInfo(const llvm::Triple &Triple)
690 : OSTargetInfo<Target>(Triple) {}
693 template <typename Target>
694 class NaClTargetInfo : public OSTargetInfo<Target> {
696 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
697 MacroBuilder &Builder) const override {
698 if (Opts.POSIXThreads)
699 Builder.defineMacro("_REENTRANT");
701 Builder.defineMacro("_GNU_SOURCE");
703 DefineStd(Builder, "unix", Opts);
704 Builder.defineMacro("__ELF__");
705 Builder.defineMacro("__native_client__");
709 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
710 this->UserLabelPrefix = "";
711 this->LongAlign = 32;
712 this->LongWidth = 32;
713 this->PointerAlign = 32;
714 this->PointerWidth = 32;
715 this->IntMaxType = TargetInfo::SignedLongLong;
716 this->Int64Type = TargetInfo::SignedLongLong;
717 this->DoubleAlign = 64;
718 this->LongDoubleWidth = 64;
719 this->LongDoubleAlign = 64;
720 this->LongLongWidth = 64;
721 this->LongLongAlign = 64;
722 this->SizeType = TargetInfo::UnsignedInt;
723 this->PtrDiffType = TargetInfo::SignedInt;
724 this->IntPtrType = TargetInfo::SignedInt;
725 // RegParmMax is inherited from the underlying architecture
726 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
727 if (Triple.getArch() == llvm::Triple::arm) {
728 // Handled in ARM's setABI().
729 } else if (Triple.getArch() == llvm::Triple::x86) {
730 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
731 } else if (Triple.getArch() == llvm::Triple::x86_64) {
732 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
733 } else if (Triple.getArch() == llvm::Triple::mipsel) {
734 // Handled on mips' setDataLayoutString.
736 assert(Triple.getArch() == llvm::Triple::le32);
737 this->DataLayoutString = "e-p:32:32-i64:64";
742 // WebAssembly target
743 template <typename Target>
744 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> {
745 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
746 MacroBuilder &Builder) const final {
747 // A common platform macro.
748 if (Opts.POSIXThreads)
749 Builder.defineMacro("_REENTRANT");
750 // Follow g++ convention and predefine _GNU_SOURCE for C++.
752 Builder.defineMacro("_GNU_SOURCE");
755 // As an optimization, group static init code together in a section.
756 const char *getStaticInitSectionSpecifier() const final {
757 return ".text.__startup";
761 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple)
762 : OSTargetInfo<Target>(Triple) {
763 this->MCountName = "__mcount";
764 this->UserLabelPrefix = "";
765 this->TheCXXABI.set(TargetCXXABI::WebAssembly);
769 //===----------------------------------------------------------------------===//
770 // Specific target implementations.
771 //===----------------------------------------------------------------------===//
773 // PPC abstract base class
774 class PPCTargetInfo : public TargetInfo {
775 static const Builtin::Info BuiltinInfo[];
776 static const char * const GCCRegNames[];
777 static const TargetInfo::GCCRegAlias GCCRegAliases[];
780 // Target cpu features.
794 PPCTargetInfo(const llvm::Triple &Triple)
795 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
796 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
797 HasBPERMD(false), HasExtDiv(false) {
798 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
799 SimdDefaultAlign = 128;
800 LongDoubleWidth = LongDoubleAlign = 128;
801 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
804 /// \brief Flags for architecture specific defines.
807 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
808 ArchDefinePpcgr = 1 << 1,
809 ArchDefinePpcsq = 1 << 2,
810 ArchDefine440 = 1 << 3,
811 ArchDefine603 = 1 << 4,
812 ArchDefine604 = 1 << 5,
813 ArchDefinePwr4 = 1 << 6,
814 ArchDefinePwr5 = 1 << 7,
815 ArchDefinePwr5x = 1 << 8,
816 ArchDefinePwr6 = 1 << 9,
817 ArchDefinePwr6x = 1 << 10,
818 ArchDefinePwr7 = 1 << 11,
819 ArchDefinePwr8 = 1 << 12,
820 ArchDefineA2 = 1 << 13,
821 ArchDefineA2q = 1 << 14
824 // Note: GCC recognizes the following additional cpus:
825 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
826 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
828 bool setCPU(const std::string &Name) override {
829 bool CPUKnown = llvm::StringSwitch<bool>(Name)
830 .Case("generic", true)
852 .Case("e500mc", true)
854 .Case("power3", true)
856 .Case("power4", true)
858 .Case("power5", true)
860 .Case("power5x", true)
862 .Case("power6", true)
864 .Case("power6x", true)
866 .Case("power7", true)
868 .Case("power8", true)
870 .Case("powerpc", true)
872 .Case("powerpc64", true)
874 .Case("powerpc64le", true)
875 .Case("ppc64le", true)
885 StringRef getABI() const override { return ABI; }
887 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
888 return llvm::makeArrayRef(BuiltinInfo,
889 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin);
892 bool isCLZForZeroUndef() const override { return false; }
894 void getTargetDefines(const LangOptions &Opts,
895 MacroBuilder &Builder) const override;
898 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
900 const std::vector<std::string> &FeaturesVec) const override;
902 bool handleTargetFeatures(std::vector<std::string> &Features,
903 DiagnosticsEngine &Diags) override;
904 bool hasFeature(StringRef Feature) const override;
905 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
906 bool Enabled) const override;
908 ArrayRef<const char *> getGCCRegNames() const override;
909 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
910 bool validateAsmConstraint(const char *&Name,
911 TargetInfo::ConstraintInfo &Info) const override {
913 default: return false;
916 case 'b': // Base register
917 case 'f': // Floating point register
918 Info.setAllowsRegister();
920 // FIXME: The following are added to allow parsing.
921 // I just took a guess at what the actions should be.
922 // Also, is more specific checking needed? I.e. specific registers?
923 case 'd': // Floating point register (containing 64-bit value)
924 case 'v': // Altivec vector register
925 Info.setAllowsRegister();
929 case 'd':// VSX vector register to hold vector double data
930 case 'f':// VSX vector register to hold vector float data
931 case 's':// VSX vector register to hold scalar float data
932 case 'a':// Any VSX register
933 case 'c':// An individual CR bit
938 Info.setAllowsRegister();
939 Name++; // Skip over 'w'.
941 case 'h': // `MQ', `CTR', or `LINK' register
942 case 'q': // `MQ' register
943 case 'c': // `CTR' register
944 case 'l': // `LINK' register
945 case 'x': // `CR' register (condition register) number 0
946 case 'y': // `CR' register (condition register)
947 case 'z': // `XER[CA]' carry bit (part of the XER register)
948 Info.setAllowsRegister();
950 case 'I': // Signed 16-bit constant
951 case 'J': // Unsigned 16-bit constant shifted left 16 bits
952 // (use `L' instead for SImode constants)
953 case 'K': // Unsigned 16-bit constant
954 case 'L': // Signed 16-bit constant shifted left 16 bits
955 case 'M': // Constant larger than 31
956 case 'N': // Exact power of 2
957 case 'P': // Constant whose negation is a signed 16-bit constant
958 case 'G': // Floating point constant that can be loaded into a
959 // register with one instruction per word
960 case 'H': // Integer/Floating point constant that can be loaded
961 // into a register using three instructions
963 case 'm': // Memory operand. Note that on PowerPC targets, m can
964 // include addresses that update the base register. It
965 // is therefore only safe to use `m' in an asm statement
966 // if that asm statement accesses the operand exactly once.
967 // The asm statement must also use `%U<opno>' as a
968 // placeholder for the "update" flag in the corresponding
969 // load or store instruction. For example:
970 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
972 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
973 // is not. Use es rather than m if you don't want the base
974 // register to be updated.
978 // es: A "stable" memory operand; that is, one which does not
979 // include any automodification of the base register. Unlike
980 // `m', this constraint can be used in asm statements that
981 // might access the operand several times, or that might not
983 Info.setAllowsMemory();
984 Name++; // Skip over 'e'.
986 case 'Q': // Memory operand that is an offset from a register (it is
987 // usually better to use `m' or `es' in asm statements)
988 case 'Z': // Memory operand that is an indexed or indirect from a
989 // register (it is usually better to use `m' or `es' in
991 Info.setAllowsMemory();
992 Info.setAllowsRegister();
994 case 'R': // AIX TOC entry
995 case 'a': // Address operand that is an indexed or indirect from a
996 // register (`p' is preferable for asm statements)
997 case 'S': // Constant suitable as a 64-bit mask operand
998 case 'T': // Constant suitable as a 32-bit mask operand
999 case 'U': // System V Release 4 small data area reference
1000 case 't': // AND masks that can be performed by two rldic{l, r}
1002 case 'W': // Vector constant that does not require memory
1003 case 'j': // Vector constant that is all zeros.
1009 std::string convertConstraint(const char *&Constraint) const override {
1011 switch (*Constraint) {
1014 // Two-character constraint; add "^" hint for later parsing.
1015 R = std::string("^") + std::string(Constraint, 2);
1019 return TargetInfo::convertConstraint(Constraint);
1023 const char *getClobbers() const override {
1026 int getEHDataRegisterNumber(unsigned RegNo) const override {
1027 if (RegNo == 0) return 3;
1028 if (RegNo == 1) return 4;
1032 bool hasSjLjLowering() const override {
1036 bool useFloat128ManglingForLongDouble() const override {
1037 return LongDoubleWidth == 128 &&
1038 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble &&
1039 getTriple().isOSBinFormatELF();
1043 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
1044 #define BUILTIN(ID, TYPE, ATTRS) \
1045 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1046 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1047 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1048 #include "clang/Basic/BuiltinsPPC.def"
1051 /// handleTargetFeatures - Perform initialization based on the user
1052 /// configured set of features.
1053 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1054 DiagnosticsEngine &Diags) {
1055 for (const auto &Feature : Features) {
1056 if (Feature == "+vsx") {
1058 } else if (Feature == "+bpermd") {
1060 } else if (Feature == "+extdiv") {
1062 } else if (Feature == "+power8-vector") {
1064 } else if (Feature == "+crypto") {
1066 } else if (Feature == "+direct-move") {
1067 HasDirectMove = true;
1068 } else if (Feature == "+qpx") {
1070 } else if (Feature == "+htm") {
1073 // TODO: Finish this list and add an assert that we've handled them
1080 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1081 /// #defines that are not tied to a specific subtarget.
1082 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1083 MacroBuilder &Builder) const {
1084 // Target identification.
1085 Builder.defineMacro("__ppc__");
1086 Builder.defineMacro("__PPC__");
1087 Builder.defineMacro("_ARCH_PPC");
1088 Builder.defineMacro("__powerpc__");
1089 Builder.defineMacro("__POWERPC__");
1090 if (PointerWidth == 64) {
1091 Builder.defineMacro("_ARCH_PPC64");
1092 Builder.defineMacro("__powerpc64__");
1093 Builder.defineMacro("__ppc64__");
1094 Builder.defineMacro("__PPC64__");
1097 // Target properties.
1098 if (getTriple().getArch() == llvm::Triple::ppc64le) {
1099 Builder.defineMacro("_LITTLE_ENDIAN");
1101 if (getTriple().getOS() != llvm::Triple::NetBSD &&
1102 getTriple().getOS() != llvm::Triple::OpenBSD)
1103 Builder.defineMacro("_BIG_ENDIAN");
1107 if (ABI == "elfv1" || ABI == "elfv1-qpx")
1108 Builder.defineMacro("_CALL_ELF", "1");
1110 Builder.defineMacro("_CALL_ELF", "2");
1112 // Subtarget options.
1113 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1114 Builder.defineMacro("__REGISTER_PREFIX__", "");
1116 // FIXME: Should be controlled by command line option.
1117 if (LongDoubleWidth == 128)
1118 Builder.defineMacro("__LONG_DOUBLE_128__");
1121 Builder.defineMacro("__VEC__", "10206");
1122 Builder.defineMacro("__ALTIVEC__");
1125 // CPU identification.
1126 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1127 .Case("440", ArchDefineName)
1128 .Case("450", ArchDefineName | ArchDefine440)
1129 .Case("601", ArchDefineName)
1130 .Case("602", ArchDefineName | ArchDefinePpcgr)
1131 .Case("603", ArchDefineName | ArchDefinePpcgr)
1132 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1133 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1134 .Case("604", ArchDefineName | ArchDefinePpcgr)
1135 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1136 .Case("620", ArchDefineName | ArchDefinePpcgr)
1137 .Case("630", ArchDefineName | ArchDefinePpcgr)
1138 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1139 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1140 .Case("750", ArchDefineName | ArchDefinePpcgr)
1141 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1143 .Case("a2", ArchDefineA2)
1144 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1145 .Case("pwr3", ArchDefinePpcgr)
1146 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1147 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1149 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1150 | ArchDefinePpcgr | ArchDefinePpcsq)
1151 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1152 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1153 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1154 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1156 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1157 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1158 | ArchDefinePpcgr | ArchDefinePpcsq)
1159 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1160 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1161 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1162 .Case("power3", ArchDefinePpcgr)
1163 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1164 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1166 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1167 | ArchDefinePpcgr | ArchDefinePpcsq)
1168 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1169 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1170 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1171 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1173 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1174 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1175 | ArchDefinePpcgr | ArchDefinePpcsq)
1176 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1177 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1178 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1179 .Default(ArchDefineNone);
1181 if (defs & ArchDefineName)
1182 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1183 if (defs & ArchDefinePpcgr)
1184 Builder.defineMacro("_ARCH_PPCGR");
1185 if (defs & ArchDefinePpcsq)
1186 Builder.defineMacro("_ARCH_PPCSQ");
1187 if (defs & ArchDefine440)
1188 Builder.defineMacro("_ARCH_440");
1189 if (defs & ArchDefine603)
1190 Builder.defineMacro("_ARCH_603");
1191 if (defs & ArchDefine604)
1192 Builder.defineMacro("_ARCH_604");
1193 if (defs & ArchDefinePwr4)
1194 Builder.defineMacro("_ARCH_PWR4");
1195 if (defs & ArchDefinePwr5)
1196 Builder.defineMacro("_ARCH_PWR5");
1197 if (defs & ArchDefinePwr5x)
1198 Builder.defineMacro("_ARCH_PWR5X");
1199 if (defs & ArchDefinePwr6)
1200 Builder.defineMacro("_ARCH_PWR6");
1201 if (defs & ArchDefinePwr6x)
1202 Builder.defineMacro("_ARCH_PWR6X");
1203 if (defs & ArchDefinePwr7)
1204 Builder.defineMacro("_ARCH_PWR7");
1205 if (defs & ArchDefinePwr8)
1206 Builder.defineMacro("_ARCH_PWR8");
1207 if (defs & ArchDefineA2)
1208 Builder.defineMacro("_ARCH_A2");
1209 if (defs & ArchDefineA2q) {
1210 Builder.defineMacro("_ARCH_A2Q");
1211 Builder.defineMacro("_ARCH_QP");
1214 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1215 Builder.defineMacro("__bg__");
1216 Builder.defineMacro("__THW_BLUEGENE__");
1217 Builder.defineMacro("__bgq__");
1218 Builder.defineMacro("__TOS_BGQ__");
1222 Builder.defineMacro("__VSX__");
1224 Builder.defineMacro("__POWER8_VECTOR__");
1226 Builder.defineMacro("__CRYPTO__");
1228 Builder.defineMacro("__HTM__");
1230 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1231 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1232 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1233 if (PointerWidth == 64)
1234 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1236 // FIXME: The following are not yet generated here by Clang, but are
1237 // generated by GCC:
1240 // __RECIP_PRECISION__
1241 // __APPLE_ALTIVEC__
1250 // __CMODEL_MEDIUM__
1257 // Handle explicit options being passed to the compiler here: if we've
1258 // explicitly turned off vsx and turned on power8-vector or direct-move then
1259 // go ahead and error since the customer has expressed a somewhat incompatible
1261 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
1262 const std::vector<std::string> &FeaturesVec) {
1264 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") !=
1265 FeaturesVec.end()) {
1266 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") !=
1267 FeaturesVec.end()) {
1268 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
1273 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") !=
1274 FeaturesVec.end()) {
1275 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
1284 bool PPCTargetInfo::initFeatureMap(
1285 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
1286 const std::vector<std::string> &FeaturesVec) const {
1287 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1297 .Case("ppc64", true)
1298 .Case("ppc64le", true)
1301 Features["qpx"] = (CPU == "a2q");
1302 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1303 .Case("ppc64le", true)
1306 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1307 .Case("ppc64le", true)
1310 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1311 .Case("ppc64le", true)
1315 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1316 .Case("ppc64le", true)
1320 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1321 .Case("ppc64le", true)
1324 Features["vsx"] = llvm::StringSwitch<bool>(CPU)
1325 .Case("ppc64le", true)
1330 if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
1333 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1336 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1337 return llvm::StringSwitch<bool>(Feature)
1338 .Case("powerpc", true)
1339 .Case("vsx", HasVSX)
1340 .Case("power8-vector", HasP8Vector)
1341 .Case("crypto", HasP8Crypto)
1342 .Case("direct-move", HasDirectMove)
1343 .Case("qpx", HasQPX)
1344 .Case("htm", HasHTM)
1345 .Case("bpermd", HasBPERMD)
1346 .Case("extdiv", HasExtDiv)
1350 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1351 StringRef Name, bool Enabled) const {
1352 // If we're enabling direct-move or power8-vector go ahead and enable vsx
1353 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user
1354 // incompatible options.
1356 if (Name == "vsx") {
1357 Features[Name] = true;
1358 } else if (Name == "direct-move") {
1359 Features[Name] = Features["vsx"] = true;
1360 } else if (Name == "power8-vector") {
1361 Features[Name] = Features["vsx"] = true;
1363 Features[Name] = true;
1366 if (Name == "vsx") {
1367 Features[Name] = Features["direct-move"] = Features["power8-vector"] =
1370 Features[Name] = false;
1375 const char * const PPCTargetInfo::GCCRegNames[] = {
1376 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1377 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1378 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1379 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1380 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1381 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1382 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1383 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1384 "mq", "lr", "ctr", "ap",
1385 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1387 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1388 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1389 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1390 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1392 "spe_acc", "spefscr",
1396 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const {
1397 return llvm::makeArrayRef(GCCRegNames);
1400 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1401 // While some of these aliases do map to different registers
1402 // they still share the same register name.
1413 { { "10" }, "r10" },
1414 { { "11" }, "r11" },
1415 { { "12" }, "r12" },
1416 { { "13" }, "r13" },
1417 { { "14" }, "r14" },
1418 { { "15" }, "r15" },
1419 { { "16" }, "r16" },
1420 { { "17" }, "r17" },
1421 { { "18" }, "r18" },
1422 { { "19" }, "r19" },
1423 { { "20" }, "r20" },
1424 { { "21" }, "r21" },
1425 { { "22" }, "r22" },
1426 { { "23" }, "r23" },
1427 { { "24" }, "r24" },
1428 { { "25" }, "r25" },
1429 { { "26" }, "r26" },
1430 { { "27" }, "r27" },
1431 { { "28" }, "r28" },
1432 { { "29" }, "r29" },
1433 { { "30" }, "r30" },
1434 { { "31" }, "r31" },
1435 { { "fr0" }, "f0" },
1436 { { "fr1" }, "f1" },
1437 { { "fr2" }, "f2" },
1438 { { "fr3" }, "f3" },
1439 { { "fr4" }, "f4" },
1440 { { "fr5" }, "f5" },
1441 { { "fr6" }, "f6" },
1442 { { "fr7" }, "f7" },
1443 { { "fr8" }, "f8" },
1444 { { "fr9" }, "f9" },
1445 { { "fr10" }, "f10" },
1446 { { "fr11" }, "f11" },
1447 { { "fr12" }, "f12" },
1448 { { "fr13" }, "f13" },
1449 { { "fr14" }, "f14" },
1450 { { "fr15" }, "f15" },
1451 { { "fr16" }, "f16" },
1452 { { "fr17" }, "f17" },
1453 { { "fr18" }, "f18" },
1454 { { "fr19" }, "f19" },
1455 { { "fr20" }, "f20" },
1456 { { "fr21" }, "f21" },
1457 { { "fr22" }, "f22" },
1458 { { "fr23" }, "f23" },
1459 { { "fr24" }, "f24" },
1460 { { "fr25" }, "f25" },
1461 { { "fr26" }, "f26" },
1462 { { "fr27" }, "f27" },
1463 { { "fr28" }, "f28" },
1464 { { "fr29" }, "f29" },
1465 { { "fr30" }, "f30" },
1466 { { "fr31" }, "f31" },
1467 { { "cc" }, "cr0" },
1470 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
1471 return llvm::makeArrayRef(GCCRegAliases);
1474 class PPC32TargetInfo : public PPCTargetInfo {
1476 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1477 DataLayoutString = "E-m:e-p:32:32-i64:64-n32";
1479 switch (getTriple().getOS()) {
1480 case llvm::Triple::Linux:
1481 case llvm::Triple::FreeBSD:
1482 case llvm::Triple::NetBSD:
1483 SizeType = UnsignedInt;
1484 PtrDiffType = SignedInt;
1485 IntPtrType = SignedInt;
1491 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1492 LongDoubleWidth = LongDoubleAlign = 64;
1493 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1496 // PPC32 supports atomics up to 4 bytes.
1497 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1500 BuiltinVaListKind getBuiltinVaListKind() const override {
1501 // This is the ELF definition, and is overridden by the Darwin sub-target
1502 return TargetInfo::PowerABIBuiltinVaList;
1506 // Note: ABI differences may eventually require us to have a separate
1507 // TargetInfo for little endian.
1508 class PPC64TargetInfo : public PPCTargetInfo {
1510 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1511 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1512 IntMaxType = SignedLong;
1513 Int64Type = SignedLong;
1515 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1516 DataLayoutString = "e-m:e-i64:64-n32:64";
1519 DataLayoutString = "E-m:e-i64:64-n32:64";
1523 switch (getTriple().getOS()) {
1524 case llvm::Triple::FreeBSD:
1525 LongDoubleWidth = LongDoubleAlign = 64;
1526 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1528 case llvm::Triple::NetBSD:
1529 IntMaxType = SignedLongLong;
1530 Int64Type = SignedLongLong;
1536 // PPC64 supports atomics up to 8 bytes.
1537 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1539 BuiltinVaListKind getBuiltinVaListKind() const override {
1540 return TargetInfo::CharPtrBuiltinVaList;
1542 // PPC64 Linux-specific ABI options.
1543 bool setABI(const std::string &Name) override {
1544 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1552 class DarwinPPC32TargetInfo :
1553 public DarwinTargetInfo<PPC32TargetInfo> {
1555 DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1556 : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1557 HasAlignMac68kSupport = true;
1558 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1559 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1561 SuitableAlign = 128;
1562 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32";
1564 BuiltinVaListKind getBuiltinVaListKind() const override {
1565 return TargetInfo::CharPtrBuiltinVaList;
1569 class DarwinPPC64TargetInfo :
1570 public DarwinTargetInfo<PPC64TargetInfo> {
1572 DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1573 : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1574 HasAlignMac68kSupport = true;
1575 SuitableAlign = 128;
1576 DataLayoutString = "E-m:o-i64:64-n32:64";
1580 static const unsigned NVPTXAddrSpaceMap[] = {
1583 4, // opencl_constant
1584 // FIXME: generic has to be added to the target
1585 0, // opencl_generic
1591 class NVPTXTargetInfo : public TargetInfo {
1592 static const char *const GCCRegNames[];
1593 static const Builtin::Info BuiltinInfo[];
1595 // The GPU profiles supported by the NVPTX backend
1606 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1608 TLSSupported = false;
1609 LongWidth = LongAlign = 64;
1610 AddrSpaceMap = &NVPTXAddrSpaceMap;
1611 UseAddrSpaceMapMangling = true;
1612 // Define available target features
1613 // These must be defined in sorted order!
1614 NoAsmVariants = true;
1615 // Set the default GPU to sm20
1618 void getTargetDefines(const LangOptions &Opts,
1619 MacroBuilder &Builder) const override {
1620 Builder.defineMacro("__PTX__");
1621 Builder.defineMacro("__NVPTX__");
1622 if (Opts.CUDAIsDevice) {
1623 // Set __CUDA_ARCH__ for the GPU specified.
1624 std::string CUDAArchCode;
1627 CUDAArchCode = "200";
1630 CUDAArchCode = "210";
1633 CUDAArchCode = "300";
1636 CUDAArchCode = "350";
1639 CUDAArchCode = "370";
1642 llvm_unreachable("Unhandled target CPU");
1644 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1647 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1648 return llvm::makeArrayRef(BuiltinInfo,
1649 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin);
1651 bool hasFeature(StringRef Feature) const override {
1652 return Feature == "ptx" || Feature == "nvptx";
1655 ArrayRef<const char *> getGCCRegNames() const override;
1656 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1660 bool validateAsmConstraint(const char *&Name,
1661 TargetInfo::ConstraintInfo &Info) const override {
1671 Info.setAllowsRegister();
1675 const char *getClobbers() const override {
1676 // FIXME: Is this really right?
1679 BuiltinVaListKind getBuiltinVaListKind() const override {
1681 return TargetInfo::CharPtrBuiltinVaList;
1683 bool setCPU(const std::string &Name) override {
1684 GPU = llvm::StringSwitch<GPUKind>(Name)
1685 .Case("sm_20", GK_SM20)
1686 .Case("sm_21", GK_SM21)
1687 .Case("sm_30", GK_SM30)
1688 .Case("sm_35", GK_SM35)
1689 .Case("sm_37", GK_SM37)
1692 return GPU != GK_NONE;
1696 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1697 #define BUILTIN(ID, TYPE, ATTRS) \
1698 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1699 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1700 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1701 #include "clang/Basic/BuiltinsNVPTX.def"
1704 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
1706 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
1707 return llvm::makeArrayRef(GCCRegNames);
1710 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1712 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1713 LongWidth = LongAlign = 32;
1714 PointerWidth = PointerAlign = 32;
1715 SizeType = TargetInfo::UnsignedInt;
1716 PtrDiffType = TargetInfo::SignedInt;
1717 IntPtrType = TargetInfo::SignedInt;
1718 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1722 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1724 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1725 PointerWidth = PointerAlign = 64;
1726 SizeType = TargetInfo::UnsignedLong;
1727 PtrDiffType = TargetInfo::SignedLong;
1728 IntPtrType = TargetInfo::SignedLong;
1729 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64";
1733 static const unsigned AMDGPUAddrSpaceMap[] = {
1736 2, // opencl_constant
1737 4, // opencl_generic
1743 // If you edit the description strings, make sure you update
1744 // getPointerWidthV().
1746 static const char *const DataLayoutStringR600 =
1747 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1748 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1750 static const char *const DataLayoutStringR600DoubleOps =
1751 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1752 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1754 static const char *const DataLayoutStringSI =
1755 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1756 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1757 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1759 class AMDGPUTargetInfo : public TargetInfo {
1760 static const Builtin::Info BuiltinInfo[];
1761 static const char * const GCCRegNames[];
1763 /// \brief The GPU profiles supported by the AMDGPU target.
1771 GK_EVERGREEN_DOUBLE_OPS,
1772 GK_NORTHERN_ISLANDS,
1774 GK_SOUTHERN_ISLANDS,
1784 AMDGPUTargetInfo(const llvm::Triple &Triple)
1785 : TargetInfo(Triple) {
1787 if (Triple.getArch() == llvm::Triple::amdgcn) {
1788 DataLayoutString = DataLayoutStringSI;
1789 GPU = GK_SOUTHERN_ISLANDS;
1794 DataLayoutString = DataLayoutStringR600;
1800 AddrSpaceMap = &AMDGPUAddrSpaceMap;
1801 UseAddrSpaceMapMangling = true;
1804 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1805 if (GPU <= GK_CAYMAN)
1818 const char * getClobbers() const override {
1822 ArrayRef<const char *> getGCCRegNames() const override;
1824 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1828 bool validateAsmConstraint(const char *&Name,
1829 TargetInfo::ConstraintInfo &Info) const override {
1834 Info.setAllowsRegister();
1840 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1841 return llvm::makeArrayRef(BuiltinInfo,
1842 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin);
1845 void getTargetDefines(const LangOptions &Opts,
1846 MacroBuilder &Builder) const override {
1847 Builder.defineMacro("__R600__");
1849 Builder.defineMacro("__HAS_FMAF__");
1851 Builder.defineMacro("__HAS_LDEXPF__");
1852 if (hasFP64 && Opts.OpenCL)
1853 Builder.defineMacro("cl_khr_fp64");
1855 if (GPU >= GK_NORTHERN_ISLANDS) {
1856 Builder.defineMacro("cl_khr_byte_addressable_store");
1857 Builder.defineMacro("cl_khr_global_int32_base_atomics");
1858 Builder.defineMacro("cl_khr_global_int32_extended_atomics");
1859 Builder.defineMacro("cl_khr_local_int32_base_atomics");
1860 Builder.defineMacro("cl_khr_local_int32_extended_atomics");
1865 BuiltinVaListKind getBuiltinVaListKind() const override {
1866 return TargetInfo::CharPtrBuiltinVaList;
1869 bool setCPU(const std::string &Name) override {
1870 GPU = llvm::StringSwitch<GPUKind>(Name)
1871 .Case("r600" , GK_R600)
1872 .Case("rv610", GK_R600)
1873 .Case("rv620", GK_R600)
1874 .Case("rv630", GK_R600)
1875 .Case("rv635", GK_R600)
1876 .Case("rs780", GK_R600)
1877 .Case("rs880", GK_R600)
1878 .Case("rv670", GK_R600_DOUBLE_OPS)
1879 .Case("rv710", GK_R700)
1880 .Case("rv730", GK_R700)
1881 .Case("rv740", GK_R700_DOUBLE_OPS)
1882 .Case("rv770", GK_R700_DOUBLE_OPS)
1883 .Case("palm", GK_EVERGREEN)
1884 .Case("cedar", GK_EVERGREEN)
1885 .Case("sumo", GK_EVERGREEN)
1886 .Case("sumo2", GK_EVERGREEN)
1887 .Case("redwood", GK_EVERGREEN)
1888 .Case("juniper", GK_EVERGREEN)
1889 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
1890 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
1891 .Case("barts", GK_NORTHERN_ISLANDS)
1892 .Case("turks", GK_NORTHERN_ISLANDS)
1893 .Case("caicos", GK_NORTHERN_ISLANDS)
1894 .Case("cayman", GK_CAYMAN)
1895 .Case("aruba", GK_CAYMAN)
1896 .Case("tahiti", GK_SOUTHERN_ISLANDS)
1897 .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1898 .Case("verde", GK_SOUTHERN_ISLANDS)
1899 .Case("oland", GK_SOUTHERN_ISLANDS)
1900 .Case("hainan", GK_SOUTHERN_ISLANDS)
1901 .Case("bonaire", GK_SEA_ISLANDS)
1902 .Case("kabini", GK_SEA_ISLANDS)
1903 .Case("kaveri", GK_SEA_ISLANDS)
1904 .Case("hawaii", GK_SEA_ISLANDS)
1905 .Case("mullins", GK_SEA_ISLANDS)
1906 .Case("tonga", GK_VOLCANIC_ISLANDS)
1907 .Case("iceland", GK_VOLCANIC_ISLANDS)
1908 .Case("carrizo", GK_VOLCANIC_ISLANDS)
1911 if (GPU == GK_NONE) {
1915 // Set the correct data layout
1921 case GK_NORTHERN_ISLANDS:
1922 DataLayoutString = DataLayoutStringR600;
1927 case GK_R600_DOUBLE_OPS:
1928 case GK_R700_DOUBLE_OPS:
1929 case GK_EVERGREEN_DOUBLE_OPS:
1931 DataLayoutString = DataLayoutStringR600DoubleOps;
1936 case GK_SOUTHERN_ISLANDS:
1937 case GK_SEA_ISLANDS:
1938 case GK_VOLCANIC_ISLANDS:
1939 DataLayoutString = DataLayoutStringSI;
1950 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
1951 #define BUILTIN(ID, TYPE, ATTRS) \
1952 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1953 #include "clang/Basic/BuiltinsAMDGPU.def"
1955 const char * const AMDGPUTargetInfo::GCCRegNames[] = {
1956 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1957 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1958 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1959 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1960 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
1961 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
1962 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
1963 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
1964 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
1965 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
1966 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
1967 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
1968 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
1969 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
1970 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
1971 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
1972 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
1973 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
1974 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
1975 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
1976 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
1977 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
1978 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
1979 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
1980 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
1981 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
1982 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
1983 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
1984 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
1985 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
1986 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
1987 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
1988 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1989 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
1990 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
1991 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
1992 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
1993 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
1994 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
1995 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
1996 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
1997 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
1998 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
1999 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
2000 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
2001 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
2002 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
2003 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127"
2004 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi",
2005 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi"
2008 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const {
2009 return llvm::makeArrayRef(GCCRegNames);
2012 // Namespace for x86 abstract base class
2013 const Builtin::Info BuiltinInfo[] = {
2014 #define BUILTIN(ID, TYPE, ATTRS) \
2015 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2016 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
2017 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
2018 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2019 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2020 #include "clang/Basic/BuiltinsX86.def"
2023 static const char* const GCCRegNames[] = {
2024 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
2025 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
2026 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
2027 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
2028 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
2029 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2030 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
2031 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
2032 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
2035 const TargetInfo::AddlRegName AddlRegNames[] = {
2036 { { "al", "ah", "eax", "rax" }, 0 },
2037 { { "bl", "bh", "ebx", "rbx" }, 3 },
2038 { { "cl", "ch", "ecx", "rcx" }, 2 },
2039 { { "dl", "dh", "edx", "rdx" }, 1 },
2040 { { "esi", "rsi" }, 4 },
2041 { { "edi", "rdi" }, 5 },
2042 { { "esp", "rsp" }, 7 },
2043 { { "ebp", "rbp" }, 6 },
2044 { { "r8d", "r8w", "r8b" }, 38 },
2045 { { "r9d", "r9w", "r9b" }, 39 },
2046 { { "r10d", "r10w", "r10b" }, 40 },
2047 { { "r11d", "r11w", "r11b" }, 41 },
2048 { { "r12d", "r12w", "r12b" }, 42 },
2049 { { "r13d", "r13w", "r13b" }, 43 },
2050 { { "r14d", "r14w", "r14b" }, 44 },
2051 { { "r15d", "r15w", "r15b" }, 45 },
2054 // X86 target abstract base class; x86-32 and x86-64 are very close, so
2055 // most of the implementation can be shared.
2056 class X86TargetInfo : public TargetInfo {
2058 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
2061 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
2062 } MMX3DNowLevel = NoMMX3DNow;
2070 bool HasAES = false;
2071 bool HasPCLMUL = false;
2072 bool HasLZCNT = false;
2073 bool HasRDRND = false;
2074 bool HasFSGSBASE = false;
2075 bool HasBMI = false;
2076 bool HasBMI2 = false;
2077 bool HasPOPCNT = false;
2078 bool HasRTM = false;
2079 bool HasPRFCHW = false;
2080 bool HasRDSEED = false;
2081 bool HasADX = false;
2082 bool HasTBM = false;
2083 bool HasFMA = false;
2084 bool HasF16C = false;
2085 bool HasAVX512CD = false;
2086 bool HasAVX512ER = false;
2087 bool HasAVX512PF = false;
2088 bool HasAVX512DQ = false;
2089 bool HasAVX512BW = false;
2090 bool HasAVX512VL = false;
2091 bool HasSHA = false;
2092 bool HasCX16 = false;
2093 bool HasFXSR = false;
2094 bool HasXSAVE = false;
2095 bool HasXSAVEOPT = false;
2096 bool HasXSAVEC = false;
2097 bool HasXSAVES = false;
2099 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2101 /// Each enumeration represents a particular CPU supported by Clang. These
2102 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2107 /// i386-generation processors.
2113 /// i486-generation processors.
2122 /// i586-generation processors, P5 microarchitecture based.
2130 /// i686-generation processors, P6 / Pentium M microarchitecture based.
2140 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2141 /// Clang however has some logic to suport this.
2142 // FIXME: Warn, deprecate, and potentially remove this.
2147 /// Netburst microarchitecture based processors.
2156 /// Core microarchitecture based processors.
2160 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2161 /// codename which GCC no longer accepts as an option to -march, but Clang
2162 /// has some logic for recognizing it.
2163 // FIXME: Warn, deprecate, and potentially remove this.
2175 /// Nehalem microarchitecture based processors.
2179 /// Westmere microarchitecture based processors.
2182 /// \name Sandy Bridge
2183 /// Sandy Bridge microarchitecture based processors.
2186 /// \name Ivy Bridge
2187 /// Ivy Bridge microarchitecture based processors.
2191 /// Haswell microarchitecture based processors.
2195 /// Broadwell microarchitecture based processors.
2199 /// Skylake microarchitecture based processors.
2202 /// \name Knights Landing
2203 /// Knights Landing processor.
2207 /// K6 architecture processors.
2215 /// K7 architecture processors.
2218 CK_AthlonThunderbird,
2225 /// K8 architecture processors.
2238 /// Bobcat architecture processors.
2245 /// Bulldozer architecture processors.
2253 /// This specification is deprecated and will be removed in the future.
2254 /// Users should prefer \see CK_K8.
2255 // FIXME: Warn on this when the CPU is set to it.
2261 /// Geode processors.
2267 CPUKind getCPUKind(StringRef CPU) const {
2268 return llvm::StringSwitch<CPUKind>(CPU)
2269 .Case("i386", CK_i386)
2270 .Case("i486", CK_i486)
2271 .Case("winchip-c6", CK_WinChipC6)
2272 .Case("winchip2", CK_WinChip2)
2274 .Case("i586", CK_i586)
2275 .Case("pentium", CK_Pentium)
2276 .Case("pentium-mmx", CK_PentiumMMX)
2277 .Case("i686", CK_i686)
2278 .Case("pentiumpro", CK_PentiumPro)
2279 .Case("pentium2", CK_Pentium2)
2280 .Case("pentium3", CK_Pentium3)
2281 .Case("pentium3m", CK_Pentium3M)
2282 .Case("pentium-m", CK_PentiumM)
2283 .Case("c3-2", CK_C3_2)
2284 .Case("yonah", CK_Yonah)
2285 .Case("pentium4", CK_Pentium4)
2286 .Case("pentium4m", CK_Pentium4M)
2287 .Case("prescott", CK_Prescott)
2288 .Case("nocona", CK_Nocona)
2289 .Case("core2", CK_Core2)
2290 .Case("penryn", CK_Penryn)
2291 .Case("bonnell", CK_Bonnell)
2292 .Case("atom", CK_Bonnell) // Legacy name.
2293 .Case("silvermont", CK_Silvermont)
2294 .Case("slm", CK_Silvermont) // Legacy name.
2295 .Case("nehalem", CK_Nehalem)
2296 .Case("corei7", CK_Nehalem) // Legacy name.
2297 .Case("westmere", CK_Westmere)
2298 .Case("sandybridge", CK_SandyBridge)
2299 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2300 .Case("ivybridge", CK_IvyBridge)
2301 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2302 .Case("haswell", CK_Haswell)
2303 .Case("core-avx2", CK_Haswell) // Legacy name.
2304 .Case("broadwell", CK_Broadwell)
2305 .Case("skylake", CK_Skylake)
2306 .Case("skx", CK_Skylake) // Legacy name.
2307 .Case("knl", CK_KNL)
2309 .Case("k6-2", CK_K6_2)
2310 .Case("k6-3", CK_K6_3)
2311 .Case("athlon", CK_Athlon)
2312 .Case("athlon-tbird", CK_AthlonThunderbird)
2313 .Case("athlon-4", CK_Athlon4)
2314 .Case("athlon-xp", CK_AthlonXP)
2315 .Case("athlon-mp", CK_AthlonMP)
2316 .Case("athlon64", CK_Athlon64)
2317 .Case("athlon64-sse3", CK_Athlon64SSE3)
2318 .Case("athlon-fx", CK_AthlonFX)
2320 .Case("k8-sse3", CK_K8SSE3)
2321 .Case("opteron", CK_Opteron)
2322 .Case("opteron-sse3", CK_OpteronSSE3)
2323 .Case("barcelona", CK_AMDFAM10)
2324 .Case("amdfam10", CK_AMDFAM10)
2325 .Case("btver1", CK_BTVER1)
2326 .Case("btver2", CK_BTVER2)
2327 .Case("bdver1", CK_BDVER1)
2328 .Case("bdver2", CK_BDVER2)
2329 .Case("bdver3", CK_BDVER3)
2330 .Case("bdver4", CK_BDVER4)
2331 .Case("x86-64", CK_x86_64)
2332 .Case("geode", CK_Geode)
2333 .Default(CK_Generic);
2340 } FPMath = FP_Default;
2343 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
2345 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
2347 unsigned getFloatEvalMethod() const override {
2348 // X87 evaluates with 80 bits "long double" precision.
2349 return SSELevel == NoSSE ? 2 : 0;
2351 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
2352 return llvm::makeArrayRef(BuiltinInfo,
2353 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin);
2355 ArrayRef<const char *> getGCCRegNames() const override {
2356 return llvm::makeArrayRef(GCCRegNames);
2358 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2361 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
2362 return llvm::makeArrayRef(AddlRegNames);
2364 bool validateCpuSupports(StringRef Name) const override;
2365 bool validateAsmConstraint(const char *&Name,
2366 TargetInfo::ConstraintInfo &info) const override;
2368 bool validateGlobalRegisterVariable(StringRef RegName,
2370 bool &HasSizeMismatch) const override {
2371 // esp and ebp are the only 32-bit registers the x86 backend can currently
2373 if (RegName.equals("esp") || RegName.equals("ebp")) {
2374 // Check that the register size is 32-bit.
2375 HasSizeMismatch = RegSize != 32;
2382 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2384 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2386 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2388 std::string convertConstraint(const char *&Constraint) const override;
2389 const char *getClobbers() const override {
2390 return "~{dirflag},~{fpsr},~{flags}";
2392 void getTargetDefines(const LangOptions &Opts,
2393 MacroBuilder &Builder) const override;
2394 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2396 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2398 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2400 void setFeatureEnabled(llvm::StringMap<bool> &Features,
2401 StringRef Name, bool Enabled) const override {
2402 setFeatureEnabledImpl(Features, Name, Enabled);
2404 // This exists purely to cut down on the number of virtual calls in
2405 // initFeatureMap which calls this repeatedly.
2406 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2407 StringRef Name, bool Enabled);
2409 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
2411 const std::vector<std::string> &FeaturesVec) const override;
2412 bool hasFeature(StringRef Feature) const override;
2413 bool handleTargetFeatures(std::vector<std::string> &Features,
2414 DiagnosticsEngine &Diags) override;
2415 StringRef getABI() const override {
2416 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
2418 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2420 if (getTriple().getArch() == llvm::Triple::x86 &&
2421 MMX3DNowLevel == NoMMX3DNow)
2425 bool setCPU(const std::string &Name) override {
2426 CPU = getCPUKind(Name);
2428 // Perform any per-CPU checks necessary to determine if this CPU is
2430 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2431 // invalid without explaining *why*.
2434 // No processor selected!
2460 case CK_AthlonThunderbird:
2465 // Only accept certain architectures when compiling in 32-bit mode.
2466 if (getTriple().getArch() != llvm::Triple::x86)
2477 case CK_SandyBridge:
2484 case CK_Athlon64SSE3:
2489 case CK_OpteronSSE3:
2500 llvm_unreachable("Unhandled CPU kind");
2503 bool setFPMath(StringRef Name) override;
2505 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2506 // We accept all non-ARM calling conventions
2507 return (CC == CC_X86ThisCall ||
2508 CC == CC_X86FastCall ||
2509 CC == CC_X86StdCall ||
2510 CC == CC_X86VectorCall ||
2512 CC == CC_X86Pascal ||
2513 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2516 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2517 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2520 bool hasSjLjLowering() const override {
2525 bool X86TargetInfo::setFPMath(StringRef Name) {
2526 if (Name == "387") {
2530 if (Name == "sse") {
2537 bool X86TargetInfo::initFeatureMap(
2538 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
2539 const std::vector<std::string> &FeaturesVec) const {
2540 // FIXME: This *really* should not be here.
2541 // X86_64 always has SSE2.
2542 if (getTriple().getArch() == llvm::Triple::x86_64)
2543 setFeatureEnabledImpl(Features, "sse2", true);
2545 switch (getCPUKind(CPU)) {
2558 setFeatureEnabledImpl(Features, "mmx", true);
2563 setFeatureEnabledImpl(Features, "sse", true);
2564 setFeatureEnabledImpl(Features, "fxsr", true);
2570 setFeatureEnabledImpl(Features, "sse2", true);
2571 setFeatureEnabledImpl(Features, "fxsr", true);
2576 setFeatureEnabledImpl(Features, "sse3", true);
2577 setFeatureEnabledImpl(Features, "fxsr", true);
2578 setFeatureEnabledImpl(Features, "cx16", true);
2582 setFeatureEnabledImpl(Features, "ssse3", true);
2583 setFeatureEnabledImpl(Features, "fxsr", true);
2584 setFeatureEnabledImpl(Features, "cx16", true);
2587 setFeatureEnabledImpl(Features, "sse4.1", true);
2588 setFeatureEnabledImpl(Features, "fxsr", true);
2589 setFeatureEnabledImpl(Features, "cx16", true);
2592 setFeatureEnabledImpl(Features, "avx512f", true);
2593 setFeatureEnabledImpl(Features, "avx512cd", true);
2594 setFeatureEnabledImpl(Features, "avx512dq", true);
2595 setFeatureEnabledImpl(Features, "avx512bw", true);
2596 setFeatureEnabledImpl(Features, "avx512vl", true);
2597 setFeatureEnabledImpl(Features, "xsavec", true);
2598 setFeatureEnabledImpl(Features, "xsaves", true);
2601 setFeatureEnabledImpl(Features, "rdseed", true);
2602 setFeatureEnabledImpl(Features, "adx", true);
2605 setFeatureEnabledImpl(Features, "avx2", true);
2606 setFeatureEnabledImpl(Features, "lzcnt", true);
2607 setFeatureEnabledImpl(Features, "bmi", true);
2608 setFeatureEnabledImpl(Features, "bmi2", true);
2609 setFeatureEnabledImpl(Features, "rtm", true);
2610 setFeatureEnabledImpl(Features, "fma", true);
2613 setFeatureEnabledImpl(Features, "rdrnd", true);
2614 setFeatureEnabledImpl(Features, "f16c", true);
2615 setFeatureEnabledImpl(Features, "fsgsbase", true);
2617 case CK_SandyBridge:
2618 setFeatureEnabledImpl(Features, "avx", true);
2619 setFeatureEnabledImpl(Features, "xsave", true);
2620 setFeatureEnabledImpl(Features, "xsaveopt", true);
2624 setFeatureEnabledImpl(Features, "aes", true);
2625 setFeatureEnabledImpl(Features, "pclmul", true);
2628 setFeatureEnabledImpl(Features, "sse4.2", true);
2629 setFeatureEnabledImpl(Features, "fxsr", true);
2630 setFeatureEnabledImpl(Features, "cx16", true);
2633 setFeatureEnabledImpl(Features, "avx512f", true);
2634 setFeatureEnabledImpl(Features, "avx512cd", true);
2635 setFeatureEnabledImpl(Features, "avx512er", true);
2636 setFeatureEnabledImpl(Features, "avx512pf", true);
2637 setFeatureEnabledImpl(Features, "fxsr", true);
2638 setFeatureEnabledImpl(Features, "rdseed", true);
2639 setFeatureEnabledImpl(Features, "adx", true);
2640 setFeatureEnabledImpl(Features, "lzcnt", true);
2641 setFeatureEnabledImpl(Features, "bmi", true);
2642 setFeatureEnabledImpl(Features, "bmi2", true);
2643 setFeatureEnabledImpl(Features, "rtm", true);
2644 setFeatureEnabledImpl(Features, "fma", true);
2645 setFeatureEnabledImpl(Features, "rdrnd", true);
2646 setFeatureEnabledImpl(Features, "f16c", true);
2647 setFeatureEnabledImpl(Features, "fsgsbase", true);
2648 setFeatureEnabledImpl(Features, "aes", true);
2649 setFeatureEnabledImpl(Features, "pclmul", true);
2650 setFeatureEnabledImpl(Features, "cx16", true);
2651 setFeatureEnabledImpl(Features, "xsaveopt", true);
2652 setFeatureEnabledImpl(Features, "xsave", true);
2658 setFeatureEnabledImpl(Features, "3dnow", true);
2661 case CK_AthlonThunderbird:
2663 setFeatureEnabledImpl(Features, "3dnowa", true);
2668 setFeatureEnabledImpl(Features, "sse", true);
2669 setFeatureEnabledImpl(Features, "3dnowa", true);
2670 setFeatureEnabledImpl(Features, "fxsr", true);
2676 setFeatureEnabledImpl(Features, "sse2", true);
2677 setFeatureEnabledImpl(Features, "3dnowa", true);
2678 setFeatureEnabledImpl(Features, "fxsr", true);
2681 setFeatureEnabledImpl(Features, "sse4a", true);
2682 setFeatureEnabledImpl(Features, "lzcnt", true);
2683 setFeatureEnabledImpl(Features, "popcnt", true);
2686 case CK_OpteronSSE3:
2687 case CK_Athlon64SSE3:
2688 setFeatureEnabledImpl(Features, "sse3", true);
2689 setFeatureEnabledImpl(Features, "3dnowa", true);
2690 setFeatureEnabledImpl(Features, "fxsr", true);
2693 setFeatureEnabledImpl(Features, "avx", true);
2694 setFeatureEnabledImpl(Features, "aes", true);
2695 setFeatureEnabledImpl(Features, "pclmul", true);
2696 setFeatureEnabledImpl(Features, "bmi", true);
2697 setFeatureEnabledImpl(Features, "f16c", true);
2698 setFeatureEnabledImpl(Features, "xsaveopt", true);
2701 setFeatureEnabledImpl(Features, "ssse3", true);
2702 setFeatureEnabledImpl(Features, "sse4a", true);
2703 setFeatureEnabledImpl(Features, "lzcnt", true);
2704 setFeatureEnabledImpl(Features, "popcnt", true);
2705 setFeatureEnabledImpl(Features, "prfchw", true);
2706 setFeatureEnabledImpl(Features, "cx16", true);
2707 setFeatureEnabledImpl(Features, "fxsr", true);
2708 setFeatureEnabledImpl(Features, "xsave", true);
2711 setFeatureEnabledImpl(Features, "avx2", true);
2712 setFeatureEnabledImpl(Features, "bmi2", true);
2715 setFeatureEnabledImpl(Features, "fsgsbase", true);
2716 setFeatureEnabledImpl(Features, "xsaveopt", true);
2719 setFeatureEnabledImpl(Features, "bmi", true);
2720 setFeatureEnabledImpl(Features, "fma", true);
2721 setFeatureEnabledImpl(Features, "f16c", true);
2722 setFeatureEnabledImpl(Features, "tbm", true);
2725 // xop implies avx, sse4a and fma4.
2726 setFeatureEnabledImpl(Features, "xop", true);
2727 setFeatureEnabledImpl(Features, "lzcnt", true);
2728 setFeatureEnabledImpl(Features, "aes", true);
2729 setFeatureEnabledImpl(Features, "pclmul", true);
2730 setFeatureEnabledImpl(Features, "prfchw", true);
2731 setFeatureEnabledImpl(Features, "cx16", true);
2732 setFeatureEnabledImpl(Features, "fxsr", true);
2733 setFeatureEnabledImpl(Features, "xsave", true);
2736 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
2739 // Can't do this earlier because we need to be able to explicitly enable
2740 // or disable these features and the things that they depend upon.
2742 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2743 auto I = Features.find("sse4.2");
2744 if (I != Features.end() && I->getValue() &&
2745 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
2747 Features["popcnt"] = true;
2749 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2750 I = Features.find("3dnow");
2751 if (I != Features.end() && I->getValue() &&
2752 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
2754 Features["prfchw"] = true;
2756 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2758 I = Features.find("sse");
2759 if (I != Features.end() && I->getValue() &&
2760 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
2762 Features["mmx"] = true;
2767 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2768 X86SSEEnum Level, bool Enabled) {
2772 Features["avx512f"] = true;
2774 Features["avx2"] = true;
2776 Features["avx"] = true;
2777 Features["xsave"] = true;
2779 Features["sse4.2"] = true;
2781 Features["sse4.1"] = true;
2783 Features["ssse3"] = true;
2785 Features["sse3"] = true;
2787 Features["sse2"] = true;
2789 Features["sse"] = true;
2799 Features["sse"] = false;
2801 Features["sse2"] = Features["pclmul"] = Features["aes"] =
2802 Features["sha"] = false;
2804 Features["sse3"] = false;
2805 setXOPLevel(Features, NoXOP, false);
2807 Features["ssse3"] = false;
2809 Features["sse4.1"] = false;
2811 Features["sse4.2"] = false;
2813 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
2814 Features["xsaveopt"] = false;
2815 setXOPLevel(Features, FMA4, false);
2817 Features["avx2"] = false;
2819 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2820 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2821 Features["avx512vl"] = false;
2825 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2826 MMX3DNowEnum Level, bool Enabled) {
2829 case AMD3DNowAthlon:
2830 Features["3dnowa"] = true;
2832 Features["3dnow"] = true;
2834 Features["mmx"] = true;
2844 Features["mmx"] = false;
2846 Features["3dnow"] = false;
2847 case AMD3DNowAthlon:
2848 Features["3dnowa"] = false;
2852 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2857 Features["xop"] = true;
2859 Features["fma4"] = true;
2860 setSSELevel(Features, AVX, true);
2862 Features["sse4a"] = true;
2863 setSSELevel(Features, SSE3, true);
2873 Features["sse4a"] = false;
2875 Features["fma4"] = false;
2877 Features["xop"] = false;
2881 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2882 StringRef Name, bool Enabled) {
2883 // This is a bit of a hack to deal with the sse4 target feature when used
2884 // as part of the target attribute. We handle sse4 correctly everywhere
2885 // else. See below for more information on how we handle the sse4 options.
2887 Features[Name] = Enabled;
2889 if (Name == "mmx") {
2890 setMMXLevel(Features, MMX, Enabled);
2891 } else if (Name == "sse") {
2892 setSSELevel(Features, SSE1, Enabled);
2893 } else if (Name == "sse2") {
2894 setSSELevel(Features, SSE2, Enabled);
2895 } else if (Name == "sse3") {
2896 setSSELevel(Features, SSE3, Enabled);
2897 } else if (Name == "ssse3") {
2898 setSSELevel(Features, SSSE3, Enabled);
2899 } else if (Name == "sse4.2") {
2900 setSSELevel(Features, SSE42, Enabled);
2901 } else if (Name == "sse4.1") {
2902 setSSELevel(Features, SSE41, Enabled);
2903 } else if (Name == "3dnow") {
2904 setMMXLevel(Features, AMD3DNow, Enabled);
2905 } else if (Name == "3dnowa") {
2906 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2907 } else if (Name == "aes") {
2909 setSSELevel(Features, SSE2, Enabled);
2910 } else if (Name == "pclmul") {
2912 setSSELevel(Features, SSE2, Enabled);
2913 } else if (Name == "avx") {
2914 setSSELevel(Features, AVX, Enabled);
2915 } else if (Name == "avx2") {
2916 setSSELevel(Features, AVX2, Enabled);
2917 } else if (Name == "avx512f") {
2918 setSSELevel(Features, AVX512F, Enabled);
2919 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2920 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2922 setSSELevel(Features, AVX512F, Enabled);
2923 } else if (Name == "fma") {
2925 setSSELevel(Features, AVX, Enabled);
2926 } else if (Name == "fma4") {
2927 setXOPLevel(Features, FMA4, Enabled);
2928 } else if (Name == "xop") {
2929 setXOPLevel(Features, XOP, Enabled);
2930 } else if (Name == "sse4a") {
2931 setXOPLevel(Features, SSE4A, Enabled);
2932 } else if (Name == "f16c") {
2934 setSSELevel(Features, AVX, Enabled);
2935 } else if (Name == "sha") {
2937 setSSELevel(Features, SSE2, Enabled);
2938 } else if (Name == "sse4") {
2939 // We can get here via the __target__ attribute since that's not controlled
2940 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
2941 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
2944 setSSELevel(Features, SSE42, Enabled);
2946 setSSELevel(Features, SSE41, Enabled);
2947 } else if (Name == "xsave") {
2949 setSSELevel(Features, AVX, Enabled);
2951 Features["xsaveopt"] = false;
2952 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
2954 Features["xsave"] = true;
2955 setSSELevel(Features, AVX, Enabled);
2960 /// handleTargetFeatures - Perform initialization based on the user
2961 /// configured set of features.
2962 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2963 DiagnosticsEngine &Diags) {
2964 for (const auto &Feature : Features) {
2965 if (Feature[0] != '+')
2968 if (Feature == "+aes") {
2970 } else if (Feature == "+pclmul") {
2972 } else if (Feature == "+lzcnt") {
2974 } else if (Feature == "+rdrnd") {
2976 } else if (Feature == "+fsgsbase") {
2978 } else if (Feature == "+bmi") {
2980 } else if (Feature == "+bmi2") {
2982 } else if (Feature == "+popcnt") {
2984 } else if (Feature == "+rtm") {
2986 } else if (Feature == "+prfchw") {
2988 } else if (Feature == "+rdseed") {
2990 } else if (Feature == "+adx") {
2992 } else if (Feature == "+tbm") {
2994 } else if (Feature == "+fma") {
2996 } else if (Feature == "+f16c") {
2998 } else if (Feature == "+avx512cd") {
3000 } else if (Feature == "+avx512er") {
3002 } else if (Feature == "+avx512pf") {
3004 } else if (Feature == "+avx512dq") {
3006 } else if (Feature == "+avx512bw") {
3008 } else if (Feature == "+avx512vl") {
3010 } else if (Feature == "+sha") {
3012 } else if (Feature == "+cx16") {
3014 } else if (Feature == "+fxsr") {
3016 } else if (Feature == "+xsave") {
3018 } else if (Feature == "+xsaveopt") {
3020 } else if (Feature == "+xsavec") {
3022 } else if (Feature == "+xsaves") {
3026 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
3027 .Case("+avx512f", AVX512F)
3028 .Case("+avx2", AVX2)
3030 .Case("+sse4.2", SSE42)
3031 .Case("+sse4.1", SSE41)
3032 .Case("+ssse3", SSSE3)
3033 .Case("+sse3", SSE3)
3034 .Case("+sse2", SSE2)
3037 SSELevel = std::max(SSELevel, Level);
3039 MMX3DNowEnum ThreeDNowLevel =
3040 llvm::StringSwitch<MMX3DNowEnum>(Feature)
3041 .Case("+3dnowa", AMD3DNowAthlon)
3042 .Case("+3dnow", AMD3DNow)
3044 .Default(NoMMX3DNow);
3045 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
3047 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
3049 .Case("+fma4", FMA4)
3050 .Case("+sse4a", SSE4A)
3052 XOPLevel = std::max(XOPLevel, XLevel);
3055 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
3056 // matches the selected sse level.
3057 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
3058 (FPMath == FP_387 && SSELevel >= SSE1)) {
3059 Diags.Report(diag::err_target_unsupported_fpmath) <<
3060 (FPMath == FP_SSE ? "sse" : "387");
3065 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3069 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
3070 /// definitions for this particular subtarget.
3071 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
3072 MacroBuilder &Builder) const {
3073 // Target identification.
3074 if (getTriple().getArch() == llvm::Triple::x86_64) {
3075 Builder.defineMacro("__amd64__");
3076 Builder.defineMacro("__amd64");
3077 Builder.defineMacro("__x86_64");
3078 Builder.defineMacro("__x86_64__");
3079 if (getTriple().getArchName() == "x86_64h") {
3080 Builder.defineMacro("__x86_64h");
3081 Builder.defineMacro("__x86_64h__");
3084 DefineStd(Builder, "i386", Opts);
3087 // Subtarget options.
3088 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
3089 // truly should be based on -mtune options.
3094 // The rest are coming from the i386 define above.
3095 Builder.defineMacro("__tune_i386__");
3101 defineCPUMacros(Builder, "i486");
3104 Builder.defineMacro("__pentium_mmx__");
3105 Builder.defineMacro("__tune_pentium_mmx__");
3109 defineCPUMacros(Builder, "i586");
3110 defineCPUMacros(Builder, "pentium");
3115 Builder.defineMacro("__tune_pentium3__");
3119 Builder.defineMacro("__tune_pentium2__");
3122 Builder.defineMacro("__tune_i686__");
3123 Builder.defineMacro("__tune_pentiumpro__");
3126 Builder.defineMacro("__i686");
3127 Builder.defineMacro("__i686__");
3128 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3129 Builder.defineMacro("__pentiumpro");
3130 Builder.defineMacro("__pentiumpro__");
3134 defineCPUMacros(Builder, "pentium4");
3139 defineCPUMacros(Builder, "nocona");
3143 defineCPUMacros(Builder, "core2");
3146 defineCPUMacros(Builder, "atom");
3149 defineCPUMacros(Builder, "slm");
3153 case CK_SandyBridge:
3157 // FIXME: Historically, we defined this legacy name, it would be nice to
3158 // remove it at some point. We've never exposed fine-grained names for
3159 // recent primary x86 CPUs, and we should keep it that way.
3160 defineCPUMacros(Builder, "corei7");
3163 // FIXME: Historically, we defined this legacy name, it would be nice to
3164 // remove it at some point. This is the only fine-grained CPU macro in the
3165 // main intel CPU line, and it would be better to not have these and force
3166 // people to use ISA macros.
3167 defineCPUMacros(Builder, "skx");
3170 defineCPUMacros(Builder, "knl");
3173 Builder.defineMacro("__k6_2__");
3174 Builder.defineMacro("__tune_k6_2__");
3177 if (CPU != CK_K6_2) { // In case of fallthrough
3178 // FIXME: GCC may be enabling these in cases where some other k6
3179 // architecture is specified but -m3dnow is explicitly provided. The
3180 // exact semantics need to be determined and emulated here.
3181 Builder.defineMacro("__k6_3__");
3182 Builder.defineMacro("__tune_k6_3__");
3186 defineCPUMacros(Builder, "k6");
3189 case CK_AthlonThunderbird:
3193 defineCPUMacros(Builder, "athlon");
3194 if (SSELevel != NoSSE) {
3195 Builder.defineMacro("__athlon_sse__");
3196 Builder.defineMacro("__tune_athlon_sse__");
3203 case CK_OpteronSSE3:
3205 case CK_Athlon64SSE3:
3207 defineCPUMacros(Builder, "k8");
3210 defineCPUMacros(Builder, "amdfam10");
3213 defineCPUMacros(Builder, "btver1");
3216 defineCPUMacros(Builder, "btver2");
3219 defineCPUMacros(Builder, "bdver1");
3222 defineCPUMacros(Builder, "bdver2");
3225 defineCPUMacros(Builder, "bdver3");
3228 defineCPUMacros(Builder, "bdver4");
3231 defineCPUMacros(Builder, "geode");
3235 // Target properties.
3236 Builder.defineMacro("__REGISTER_PREFIX__", "");
3238 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3239 // functions in glibc header files that use FP Stack inline asm which the
3240 // backend can't deal with (PR879).
3241 Builder.defineMacro("__NO_MATH_INLINES");
3244 Builder.defineMacro("__AES__");
3247 Builder.defineMacro("__PCLMUL__");
3250 Builder.defineMacro("__LZCNT__");
3253 Builder.defineMacro("__RDRND__");
3256 Builder.defineMacro("__FSGSBASE__");
3259 Builder.defineMacro("__BMI__");
3262 Builder.defineMacro("__BMI2__");
3265 Builder.defineMacro("__POPCNT__");
3268 Builder.defineMacro("__RTM__");
3271 Builder.defineMacro("__PRFCHW__");
3274 Builder.defineMacro("__RDSEED__");
3277 Builder.defineMacro("__ADX__");
3280 Builder.defineMacro("__TBM__");
3284 Builder.defineMacro("__XOP__");
3286 Builder.defineMacro("__FMA4__");
3288 Builder.defineMacro("__SSE4A__");
3294 Builder.defineMacro("__FMA__");
3297 Builder.defineMacro("__F16C__");
3300 Builder.defineMacro("__AVX512CD__");
3302 Builder.defineMacro("__AVX512ER__");
3304 Builder.defineMacro("__AVX512PF__");
3306 Builder.defineMacro("__AVX512DQ__");
3308 Builder.defineMacro("__AVX512BW__");
3310 Builder.defineMacro("__AVX512VL__");
3313 Builder.defineMacro("__SHA__");
3316 Builder.defineMacro("__FXSR__");
3318 Builder.defineMacro("__XSAVE__");
3320 Builder.defineMacro("__XSAVEOPT__");
3322 Builder.defineMacro("__XSAVEC__");
3324 Builder.defineMacro("__XSAVES__");
3327 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3329 // Each case falls through to the previous one here.
3332 Builder.defineMacro("__AVX512F__");
3334 Builder.defineMacro("__AVX2__");
3336 Builder.defineMacro("__AVX__");
3338 Builder.defineMacro("__SSE4_2__");
3340 Builder.defineMacro("__SSE4_1__");
3342 Builder.defineMacro("__SSSE3__");
3344 Builder.defineMacro("__SSE3__");
3346 Builder.defineMacro("__SSE2__");
3347 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
3349 Builder.defineMacro("__SSE__");
3350 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
3355 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3365 Builder.defineMacro("_M_IX86_FP", Twine(2));
3368 Builder.defineMacro("_M_IX86_FP", Twine(1));
3371 Builder.defineMacro("_M_IX86_FP", Twine(0));
3375 // Each case falls through to the previous one here.
3376 switch (MMX3DNowLevel) {
3377 case AMD3DNowAthlon:
3378 Builder.defineMacro("__3dNOW_A__");
3380 Builder.defineMacro("__3dNOW__");
3382 Builder.defineMacro("__MMX__");
3387 if (CPU >= CK_i486) {
3388 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3389 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3390 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3393 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3396 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3397 return llvm::StringSwitch<bool>(Feature)
3398 .Case("aes", HasAES)
3399 .Case("avx", SSELevel >= AVX)
3400 .Case("avx2", SSELevel >= AVX2)
3401 .Case("avx512f", SSELevel >= AVX512F)
3402 .Case("avx512cd", HasAVX512CD)
3403 .Case("avx512er", HasAVX512ER)
3404 .Case("avx512pf", HasAVX512PF)
3405 .Case("avx512dq", HasAVX512DQ)
3406 .Case("avx512bw", HasAVX512BW)
3407 .Case("avx512vl", HasAVX512VL)
3408 .Case("bmi", HasBMI)
3409 .Case("bmi2", HasBMI2)
3410 .Case("cx16", HasCX16)
3411 .Case("f16c", HasF16C)
3412 .Case("fma", HasFMA)
3413 .Case("fma4", XOPLevel >= FMA4)
3414 .Case("fsgsbase", HasFSGSBASE)
3415 .Case("fxsr", HasFXSR)
3416 .Case("lzcnt", HasLZCNT)
3417 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3418 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3419 .Case("mmx", MMX3DNowLevel >= MMX)
3420 .Case("pclmul", HasPCLMUL)
3421 .Case("popcnt", HasPOPCNT)
3422 .Case("prfchw", HasPRFCHW)
3423 .Case("rdrnd", HasRDRND)
3424 .Case("rdseed", HasRDSEED)
3425 .Case("rtm", HasRTM)
3426 .Case("sha", HasSHA)
3427 .Case("sse", SSELevel >= SSE1)
3428 .Case("sse2", SSELevel >= SSE2)
3429 .Case("sse3", SSELevel >= SSE3)
3430 .Case("ssse3", SSELevel >= SSSE3)
3431 .Case("sse4.1", SSELevel >= SSE41)
3432 .Case("sse4.2", SSELevel >= SSE42)
3433 .Case("sse4a", XOPLevel >= SSE4A)
3434 .Case("tbm", HasTBM)
3436 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3437 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3438 .Case("xop", XOPLevel >= XOP)
3439 .Case("xsave", HasXSAVE)
3440 .Case("xsavec", HasXSAVEC)
3441 .Case("xsaves", HasXSAVES)
3442 .Case("xsaveopt", HasXSAVEOPT)
3446 // We can't use a generic validation scheme for the features accepted here
3447 // versus subtarget features accepted in the target attribute because the
3448 // bitfield structure that's initialized in the runtime only supports the
3449 // below currently rather than the full range of subtarget features. (See
3450 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
3451 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
3452 return llvm::StringSwitch<bool>(FeatureStr)
3455 .Case("popcnt", true)
3459 .Case("sse4.1", true)
3460 .Case("sse4.2", true)
3463 .Case("sse4a", true)
3467 .Case("avx512f", true)
3474 X86TargetInfo::validateAsmConstraint(const char *&Name,
3475 TargetInfo::ConstraintInfo &Info) const {
3477 default: return false;
3478 // Constant constraints.
3479 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
3481 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3482 // x86_64 instructions.
3484 Info.setRequiresImmediate();
3487 Info.setRequiresImmediate(0, 31);
3490 Info.setRequiresImmediate(0, 63);
3493 Info.setRequiresImmediate(-128, 127);
3496 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) });
3499 Info.setRequiresImmediate(0, 3);
3502 Info.setRequiresImmediate(0, 255);
3505 Info.setRequiresImmediate(0, 127);
3507 // Register constraints.
3508 case 'Y': // 'Y' is the first character for several 2-character constraints.
3509 // Shift the pointer to the second character of the constraint.
3514 case '0': // First SSE register.
3515 case 't': // Any SSE register, when SSE2 is enabled.
3516 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
3517 case 'm': // Any MMX register, when inter-unit moves enabled.
3518 Info.setAllowsRegister();
3521 case 'f': // Any x87 floating point stack register.
3522 // Constraint 'f' cannot be used for output operands.
3523 if (Info.ConstraintStr[0] == '=')
3525 Info.setAllowsRegister();
3533 case 'A': // edx:eax.
3534 case 't': // Top of floating point stack.
3535 case 'u': // Second from top of floating point stack.
3536 case 'q': // Any register accessible as [r]l: a, b, c, and d.
3537 case 'y': // Any MMX register.
3538 case 'x': // Any SSE register.
3539 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3540 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3541 case 'l': // "Index" registers: any general register that can be used as an
3542 // index in a base+index memory access.
3543 Info.setAllowsRegister();
3545 // Floating point constant constraints.
3546 case 'C': // SSE floating point constant.
3547 case 'G': // x87 floating point constant.
3552 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3553 unsigned Size) const {
3554 // Strip off constraint modifiers.
3555 while (Constraint[0] == '=' ||
3556 Constraint[0] == '+' ||
3557 Constraint[0] == '&')
3558 Constraint = Constraint.substr(1);
3560 return validateOperandSize(Constraint, Size);
3563 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3564 unsigned Size) const {
3565 return validateOperandSize(Constraint, Size);
3568 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3569 unsigned Size) const {
3570 switch (Constraint[0]) {
3579 if (SSELevel >= AVX512F)
3580 // 512-bit zmm registers can be used if target supports AVX512F.
3581 return Size <= 512U;
3582 else if (SSELevel >= AVX)
3583 // 256-bit ymm registers can be used if target supports AVX.
3584 return Size <= 256U;
3585 return Size <= 128U;
3587 // 'Y' is the first character for several 2-character constraints.
3588 switch (Constraint[1]) {
3591 // 'Ym' is synonymous with 'y'.
3595 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
3596 if (SSELevel >= AVX512F)
3597 return Size <= 512U;
3598 else if (SSELevel >= AVX)
3599 return Size <= 256U;
3600 return SSELevel >= SSE2 && Size <= 128U;
3609 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3610 switch (*Constraint) {
3611 case 'a': return std::string("{ax}");
3612 case 'b': return std::string("{bx}");
3613 case 'c': return std::string("{cx}");
3614 case 'd': return std::string("{dx}");
3615 case 'S': return std::string("{si}");
3616 case 'D': return std::string("{di}");
3617 case 'p': // address
3618 return std::string("im");
3619 case 't': // top of floating point stack.
3620 return std::string("{st}");
3621 case 'u': // second from top of floating point stack.
3622 return std::string("{st(1)}"); // second from top of floating point stack.
3624 return std::string(1, *Constraint);
3628 // X86-32 generic target
3629 class X86_32TargetInfo : public X86TargetInfo {
3631 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3632 DoubleAlign = LongLongAlign = 32;
3633 LongDoubleWidth = 96;
3634 LongDoubleAlign = 32;
3635 SuitableAlign = 128;
3636 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3637 SizeType = UnsignedInt;
3638 PtrDiffType = SignedInt;
3639 IntPtrType = SignedInt;
3642 // Use fpret for all types.
3643 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3644 (1 << TargetInfo::Double) |
3645 (1 << TargetInfo::LongDouble));
3647 // x86-32 has atomics up to 8 bytes
3648 // FIXME: Check that we actually have cmpxchg8b before setting
3649 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3650 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3652 BuiltinVaListKind getBuiltinVaListKind() const override {
3653 return TargetInfo::CharPtrBuiltinVaList;
3656 int getEHDataRegisterNumber(unsigned RegNo) const override {
3657 if (RegNo == 0) return 0;
3658 if (RegNo == 1) return 2;
3661 bool validateOperandSize(StringRef Constraint,
3662 unsigned Size) const override {
3663 switch (Constraint[0]) {
3679 return X86TargetInfo::validateOperandSize(Constraint, Size);
3683 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3685 NetBSDI386TargetInfo(const llvm::Triple &Triple)
3686 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3688 unsigned getFloatEvalMethod() const override {
3689 unsigned Major, Minor, Micro;
3690 getTriple().getOSVersion(Major, Minor, Micro);
3691 // New NetBSD uses the default rounding mode.
3692 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3693 return X86_32TargetInfo::getFloatEvalMethod();
3694 // NetBSD before 6.99.26 defaults to "double" rounding.
3699 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3701 OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3702 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3703 SizeType = UnsignedLong;
3704 IntPtrType = SignedLong;
3705 PtrDiffType = SignedLong;
3709 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3711 BitrigI386TargetInfo(const llvm::Triple &Triple)
3712 : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3713 SizeType = UnsignedLong;
3714 IntPtrType = SignedLong;
3715 PtrDiffType = SignedLong;
3719 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3721 DarwinI386TargetInfo(const llvm::Triple &Triple)
3722 : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3723 LongDoubleWidth = 128;
3724 LongDoubleAlign = 128;
3725 SuitableAlign = 128;
3726 MaxVectorAlign = 256;
3727 // The watchOS simulator uses the builtin bool type for Objective-C.
3728 llvm::Triple T = llvm::Triple(Triple);
3730 UseSignedCharForObjCBool = false;
3731 SizeType = UnsignedLong;
3732 IntPtrType = SignedLong;
3733 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3734 HasAlignMac68kSupport = true;
3737 bool handleTargetFeatures(std::vector<std::string> &Features,
3738 DiagnosticsEngine &Diags) override {
3739 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features,
3742 // We now know the features we have: we can decide how to align vectors.
3744 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3749 // x86-32 Windows target
3750 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3752 WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3753 : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3754 WCharType = UnsignedShort;
3755 DoubleAlign = LongLongAlign = 64;
3757 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3758 DataLayoutString = IsWinCOFF
3759 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
3760 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3762 void getTargetDefines(const LangOptions &Opts,
3763 MacroBuilder &Builder) const override {
3764 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3768 // x86-32 Windows Visual Studio target
3769 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3771 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3772 : WindowsX86_32TargetInfo(Triple) {
3773 LongDoubleWidth = LongDoubleAlign = 64;
3774 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3776 void getTargetDefines(const LangOptions &Opts,
3777 MacroBuilder &Builder) const override {
3778 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3779 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3780 // The value of the following reflects processor type.
3781 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3782 // We lost the original triple, so we use the default.
3783 Builder.defineMacro("_M_IX86", "600");
3787 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3788 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang
3789 // supports __declspec natively under -fms-extensions, but we define a no-op
3790 // __declspec macro anyway for pre-processor compatibility.
3791 if (Opts.MicrosoftExt)
3792 Builder.defineMacro("__declspec", "__declspec");
3794 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3796 if (!Opts.MicrosoftExt) {
3797 // Provide macros for all the calling convention keywords. Provide both
3798 // single and double underscore prefixed variants. These are available on
3799 // x64 as well as x86, even though they have no effect.
3800 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3801 for (const char *CC : CCs) {
3802 std::string GCCSpelling = "__attribute__((__";
3804 GCCSpelling += "__))";
3805 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3806 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3811 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3812 Builder.defineMacro("__MSVCRT__");
3813 Builder.defineMacro("__MINGW32__");
3814 addCygMingDefines(Opts, Builder);
3817 // x86-32 MinGW target
3818 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3820 MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3821 : WindowsX86_32TargetInfo(Triple) {}
3822 void getTargetDefines(const LangOptions &Opts,
3823 MacroBuilder &Builder) const override {
3824 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3825 DefineStd(Builder, "WIN32", Opts);
3826 DefineStd(Builder, "WINNT", Opts);
3827 Builder.defineMacro("_X86_");
3828 addMinGWDefines(Opts, Builder);
3832 // x86-32 Cygwin target
3833 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3835 CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3836 : X86_32TargetInfo(Triple) {
3837 WCharType = UnsignedShort;
3838 DoubleAlign = LongLongAlign = 64;
3839 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3841 void getTargetDefines(const LangOptions &Opts,
3842 MacroBuilder &Builder) const override {
3843 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3844 Builder.defineMacro("_X86_");
3845 Builder.defineMacro("__CYGWIN__");
3846 Builder.defineMacro("__CYGWIN32__");
3847 addCygMingDefines(Opts, Builder);
3848 DefineStd(Builder, "unix", Opts);
3850 Builder.defineMacro("_GNU_SOURCE");
3854 // x86-32 Haiku target
3855 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3857 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3858 SizeType = UnsignedLong;
3859 IntPtrType = SignedLong;
3860 PtrDiffType = SignedLong;
3861 ProcessIDType = SignedLong;
3862 this->UserLabelPrefix = "";
3863 this->TLSSupported = false;
3865 void getTargetDefines(const LangOptions &Opts,
3866 MacroBuilder &Builder) const override {
3867 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3868 Builder.defineMacro("__INTEL__");
3869 Builder.defineMacro("__HAIKU__");
3873 // X86-32 MCU target
3874 class MCUX86_32TargetInfo : public X86_32TargetInfo {
3876 MCUX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3877 LongDoubleWidth = 64;
3878 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3881 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3882 // On MCU we support only C calling convention.
3883 return CC == CC_C ? CCCR_OK : CCCR_Warning;
3886 void getTargetDefines(const LangOptions &Opts,
3887 MacroBuilder &Builder) const override {
3888 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3889 Builder.defineMacro("__iamcu");
3890 Builder.defineMacro("__iamcu__");
3895 template<typename Target>
3896 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3898 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3899 MacroBuilder &Builder) const override {
3900 // RTEMS defines; list based off of gcc output
3902 Builder.defineMacro("__rtems__");
3903 Builder.defineMacro("__ELF__");
3907 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3908 this->UserLabelPrefix = "";
3910 switch (Triple.getArch()) {
3912 case llvm::Triple::x86:
3913 // this->MCountName = ".mcount";
3915 case llvm::Triple::mips:
3916 case llvm::Triple::mipsel:
3917 case llvm::Triple::ppc:
3918 case llvm::Triple::ppc64:
3919 case llvm::Triple::ppc64le:
3920 // this->MCountName = "_mcount";
3922 case llvm::Triple::arm:
3923 // this->MCountName = "__mcount";
3929 // x86-32 RTEMS target
3930 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3932 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3933 SizeType = UnsignedLong;
3934 IntPtrType = SignedLong;
3935 PtrDiffType = SignedLong;
3936 this->UserLabelPrefix = "";
3938 void getTargetDefines(const LangOptions &Opts,
3939 MacroBuilder &Builder) const override {
3940 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3941 Builder.defineMacro("__INTEL__");
3942 Builder.defineMacro("__rtems__");
3946 // x86-64 generic target
3947 class X86_64TargetInfo : public X86TargetInfo {
3949 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3950 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3952 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3953 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3954 LongDoubleWidth = 128;
3955 LongDoubleAlign = 128;
3956 LargeArrayMinWidth = 128;
3957 LargeArrayAlign = 128;
3958 SuitableAlign = 128;
3959 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
3960 PtrDiffType = IsX32 ? SignedInt : SignedLong;
3961 IntPtrType = IsX32 ? SignedInt : SignedLong;
3962 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
3963 Int64Type = IsX32 ? SignedLongLong : SignedLong;
3966 // Pointers are 32-bit in x32.
3967 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3969 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
3970 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3972 // Use fpret only for long double.
3973 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3975 // Use fp2ret for _Complex long double.
3976 ComplexLongDoubleUsesFP2Ret = true;
3978 // Make __builtin_ms_va_list available.
3979 HasBuiltinMSVaList = true;
3981 // x86-64 has atomics up to 16 bytes.
3982 MaxAtomicPromoteWidth = 128;
3983 MaxAtomicInlineWidth = 128;
3985 BuiltinVaListKind getBuiltinVaListKind() const override {
3986 return TargetInfo::X86_64ABIBuiltinVaList;
3989 int getEHDataRegisterNumber(unsigned RegNo) const override {
3990 if (RegNo == 0) return 0;
3991 if (RegNo == 1) return 1;
3995 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3996 return (CC == CC_C ||
3997 CC == CC_X86VectorCall ||
3998 CC == CC_IntelOclBicc ||
3999 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
4002 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
4006 // for x32 we need it here explicitly
4007 bool hasInt128Type() const override { return true; }
4009 bool validateGlobalRegisterVariable(StringRef RegName,
4011 bool &HasSizeMismatch) const override {
4012 // rsp and rbp are the only 64-bit registers the x86 backend can currently
4014 if (RegName.equals("rsp") || RegName.equals("rbp")) {
4015 // Check that the register size is 64-bit.
4016 HasSizeMismatch = RegSize != 64;
4020 // Check if the register is a 32-bit register the backend can handle.
4021 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize,
4026 // x86-64 Windows target
4027 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
4029 WindowsX86_64TargetInfo(const llvm::Triple &Triple)
4030 : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
4031 WCharType = UnsignedShort;
4032 LongWidth = LongAlign = 32;
4033 DoubleAlign = LongLongAlign = 64;
4034 IntMaxType = SignedLongLong;
4035 Int64Type = SignedLongLong;
4036 SizeType = UnsignedLongLong;
4037 PtrDiffType = SignedLongLong;
4038 IntPtrType = SignedLongLong;
4039 this->UserLabelPrefix = "";
4042 void getTargetDefines(const LangOptions &Opts,
4043 MacroBuilder &Builder) const override {
4044 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
4045 Builder.defineMacro("_WIN64");
4048 BuiltinVaListKind getBuiltinVaListKind() const override {
4049 return TargetInfo::CharPtrBuiltinVaList;
4052 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4055 case CC_X86ThisCall:
4056 case CC_X86FastCall:
4059 case CC_X86VectorCall:
4060 case CC_IntelOclBicc:
4064 return CCCR_Warning;
4069 // x86-64 Windows Visual Studio target
4070 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
4072 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
4073 : WindowsX86_64TargetInfo(Triple) {
4074 LongDoubleWidth = LongDoubleAlign = 64;
4075 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4077 void getTargetDefines(const LangOptions &Opts,
4078 MacroBuilder &Builder) const override {
4079 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4080 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
4081 Builder.defineMacro("_M_X64", "100");
4082 Builder.defineMacro("_M_AMD64", "100");
4086 // x86-64 MinGW target
4087 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
4089 MinGWX86_64TargetInfo(const llvm::Triple &Triple)
4090 : WindowsX86_64TargetInfo(Triple) {
4091 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
4092 // with x86 FP ops. Weird.
4093 LongDoubleWidth = LongDoubleAlign = 128;
4094 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
4097 void getTargetDefines(const LangOptions &Opts,
4098 MacroBuilder &Builder) const override {
4099 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4100 DefineStd(Builder, "WIN64", Opts);
4101 Builder.defineMacro("__MINGW64__");
4102 addMinGWDefines(Opts, Builder);
4104 // GCC defines this macro when it is using __gxx_personality_seh0.
4105 if (!Opts.SjLjExceptions)
4106 Builder.defineMacro("__SEH__");
4110 // x86-64 Cygwin target
4111 class CygwinX86_64TargetInfo : public X86_64TargetInfo {
4113 CygwinX86_64TargetInfo(const llvm::Triple &Triple)
4114 : X86_64TargetInfo(Triple) {
4115 TLSSupported = false;
4116 WCharType = UnsignedShort;
4118 void getTargetDefines(const LangOptions &Opts,
4119 MacroBuilder &Builder) const override {
4120 X86_64TargetInfo::getTargetDefines(Opts, Builder);
4121 Builder.defineMacro("__x86_64__");
4122 Builder.defineMacro("__CYGWIN__");
4123 Builder.defineMacro("__CYGWIN64__");
4124 addCygMingDefines(Opts, Builder);
4125 DefineStd(Builder, "unix", Opts);
4127 Builder.defineMacro("_GNU_SOURCE");
4129 // GCC defines this macro when it is using __gxx_personality_seh0.
4130 if (!Opts.SjLjExceptions)
4131 Builder.defineMacro("__SEH__");
4135 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
4137 DarwinX86_64TargetInfo(const llvm::Triple &Triple)
4138 : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
4139 Int64Type = SignedLongLong;
4140 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
4141 llvm::Triple T = llvm::Triple(Triple);
4143 UseSignedCharForObjCBool = false;
4144 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
4147 bool handleTargetFeatures(std::vector<std::string> &Features,
4148 DiagnosticsEngine &Diags) override {
4149 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features,
4152 // We now know the features we have: we can decide how to align vectors.
4154 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4159 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
4161 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
4162 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
4163 IntMaxType = SignedLongLong;
4164 Int64Type = SignedLongLong;
4168 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
4170 BitrigX86_64TargetInfo(const llvm::Triple &Triple)
4171 : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
4172 IntMaxType = SignedLongLong;
4173 Int64Type = SignedLongLong;
4177 class ARMTargetInfo : public TargetInfo {
4178 // Possible FPU choices.
4187 // Possible HWDiv features.
4189 HWDivThumb = (1 << 0),
4193 static bool FPUModeIsVFP(FPUMode Mode) {
4194 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
4197 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4198 static const char * const GCCRegNames[];
4200 std::string ABI, CPU;
4202 StringRef CPUProfile;
4212 unsigned ArchKind = llvm::ARM::AK_ARMV4T;
4213 unsigned ArchProfile;
4214 unsigned ArchVersion;
4218 unsigned IsAAPCS : 1;
4221 // Initialized via features.
4222 unsigned SoftFloat : 1;
4223 unsigned SoftFloatABI : 1;
4226 unsigned Crypto : 1;
4228 unsigned Unaligned : 1;
4231 LDREX_B = (1 << 0), /// byte (8-bit)
4232 LDREX_H = (1 << 1), /// half (16-bit)
4233 LDREX_W = (1 << 2), /// word (32-bit)
4234 LDREX_D = (1 << 3), /// double (64-bit)
4239 // ACLE 6.5.1 Hardware floating point
4241 HW_FP_HP = (1 << 1), /// half (16-bit)
4242 HW_FP_SP = (1 << 2), /// single (32-bit)
4243 HW_FP_DP = (1 << 3), /// double (64-bit)
4247 static const Builtin::Info BuiltinInfo[];
4249 void setABIAAPCS() {
4252 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4253 const llvm::Triple &T = getTriple();
4255 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig.
4256 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
4257 T.getOS() == llvm::Triple::Bitrig)
4258 SizeType = UnsignedLong;
4260 SizeType = UnsignedInt;
4262 switch (T.getOS()) {
4263 case llvm::Triple::NetBSD:
4264 WCharType = SignedInt;
4266 case llvm::Triple::Win32:
4267 WCharType = UnsignedShort;
4269 case llvm::Triple::Linux:
4271 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
4272 WCharType = UnsignedInt;
4276 UseBitFieldTypeAlignment = true;
4278 ZeroLengthBitfieldBoundary = 0;
4280 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
4281 // so set preferred for small types to 32.
4282 if (T.isOSBinFormatMachO()) {
4284 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4285 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4286 } else if (T.isOSWindows()) {
4287 assert(!BigEndian && "Windows on ARM does not support big endian");
4288 DataLayoutString = "e"
4296 } else if (T.isOSNaCl()) {
4297 assert(!BigEndian && "NaCl on ARM does not support big endian");
4298 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
4301 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4302 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4305 // FIXME: Enumerated types are variable width in straight AAPCS.
4308 void setABIAPCS(bool IsAAPCS16) {
4309 const llvm::Triple &T = getTriple();
4314 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4316 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
4318 // size_t is unsigned int on FreeBSD.
4319 if (T.getOS() == llvm::Triple::FreeBSD)
4320 SizeType = UnsignedInt;
4322 SizeType = UnsignedLong;
4324 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
4325 WCharType = SignedInt;
4327 // Do not respect the alignment of bit-field types when laying out
4328 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
4329 UseBitFieldTypeAlignment = false;
4331 /// gcc forces the alignment to 4 bytes, regardless of the type of the
4332 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
4334 ZeroLengthBitfieldBoundary = 32;
4336 if (T.isOSBinFormatMachO() && IsAAPCS16) {
4337 assert(!BigEndian && "AAPCS16 does not support big-endian");
4338 DataLayoutString = "e-m:o-p:32:32-i64:64-a:0:32-n32-S128";
4339 } else if (T.isOSBinFormatMachO())
4342 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4343 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4347 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4348 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4350 // FIXME: Override "preferred align" for double and long long.
4353 void setArchInfo() {
4354 StringRef ArchName = getTriple().getArchName();
4356 ArchISA = llvm::ARM::parseArchISA(ArchName);
4357 CPU = llvm::ARM::getDefaultCPU(ArchName);
4358 unsigned AK = llvm::ARM::parseArch(ArchName);
4359 if (AK != llvm::ARM::AK_INVALID)
4361 setArchInfo(ArchKind);
4364 void setArchInfo(unsigned Kind) {
4367 // cache TargetParser info
4369 SubArch = llvm::ARM::getSubArch(ArchKind);
4370 ArchProfile = llvm::ARM::parseArchProfile(SubArch);
4371 ArchVersion = llvm::ARM::parseArchVersion(SubArch);
4373 // cache CPU related strings
4374 CPUAttr = getCPUAttr();
4375 CPUProfile = getCPUProfile();
4379 // when triple does not specify a sub arch,
4380 // then we are not using inline atomics
4381 bool ShouldUseInlineAtomic =
4382 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) ||
4383 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
4384 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4385 if (ArchProfile == llvm::ARM::PK_M) {
4386 MaxAtomicPromoteWidth = 32;
4387 if (ShouldUseInlineAtomic)
4388 MaxAtomicInlineWidth = 32;
4391 MaxAtomicPromoteWidth = 64;
4392 if (ShouldUseInlineAtomic)
4393 MaxAtomicInlineWidth = 64;
4397 bool isThumb() const {
4398 return (ArchISA == llvm::ARM::IK_THUMB);
4401 bool supportsThumb() const {
4402 return CPUAttr.count('T') || ArchVersion >= 6;
4405 bool supportsThumb2() const {
4406 return CPUAttr.equals("6T2") || ArchVersion >= 7;
4409 StringRef getCPUAttr() const {
4410 // For most sub-arches, the build attribute CPU name is enough.
4411 // For Cortex variants, it's slightly different.
4414 return llvm::ARM::getCPUAttr(ArchKind);
4415 case llvm::ARM::AK_ARMV6M:
4417 case llvm::ARM::AK_ARMV7S:
4419 case llvm::ARM::AK_ARMV7A:
4421 case llvm::ARM::AK_ARMV7R:
4423 case llvm::ARM::AK_ARMV7M:
4425 case llvm::ARM::AK_ARMV7EM:
4427 case llvm::ARM::AK_ARMV8A:
4429 case llvm::ARM::AK_ARMV8_1A:
4434 StringRef getCPUProfile() const {
4435 switch(ArchProfile) {
4436 case llvm::ARM::PK_A:
4438 case llvm::ARM::PK_R:
4440 case llvm::ARM::PK_M:
4448 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
4449 : TargetInfo(Triple), FPMath(FP_Default),
4450 IsAAPCS(true), LDREX(0), HW_FP(0) {
4451 BigEndian = IsBigEndian;
4453 switch (getTriple().getOS()) {
4454 case llvm::Triple::NetBSD:
4455 PtrDiffType = SignedLong;
4458 PtrDiffType = SignedInt;
4462 // Cache arch related info.
4465 // {} in inline assembly are neon specifiers, not assembly variant
4467 NoAsmVariants = true;
4469 // FIXME: This duplicates code from the driver that sets the -target-abi
4470 // option - this code is used if -target-abi isn't passed and should
4471 // be unified in some way.
4472 if (Triple.isOSBinFormatMachO()) {
4473 // The backend is hardwired to assume AAPCS for M-class processors, ensure
4474 // the frontend matches that.
4475 if (Triple.getEnvironment() == llvm::Triple::EABI ||
4476 Triple.getOS() == llvm::Triple::UnknownOS ||
4477 StringRef(CPU).startswith("cortex-m")) {
4479 } else if (Triple.isWatchOS()) {
4484 } else if (Triple.isOSWindows()) {
4485 // FIXME: this is invalid for WindowsCE
4488 // Select the default based on the platform.
4489 switch (Triple.getEnvironment()) {
4490 case llvm::Triple::Android:
4491 case llvm::Triple::GNUEABI:
4492 case llvm::Triple::GNUEABIHF:
4493 setABI("aapcs-linux");
4495 case llvm::Triple::EABIHF:
4496 case llvm::Triple::EABI:
4499 case llvm::Triple::GNU:
4503 if (Triple.getOS() == llvm::Triple::NetBSD)
4511 // ARM targets default to using the ARM C++ ABI.
4512 TheCXXABI.set(TargetCXXABI::GenericARM);
4514 // ARM has atomics up to 8 bytes
4517 // Do force alignment of members that follow zero length bitfields. If
4518 // the alignment of the zero-length bitfield is greater than the member
4519 // that follows it, `bar', `bar' will be aligned as the type of the
4520 // zero length bitfield.
4521 UseZeroLengthBitfieldAlignment = true;
4524 StringRef getABI() const override { return ABI; }
4526 bool setABI(const std::string &Name) override {
4529 // The defaults (above) are for AAPCS, check if we need to change them.
4531 // FIXME: We need support for -meabi... we could just mangle it into the
4533 if (Name == "apcs-gnu" || Name == "aapcs16") {
4534 setABIAPCS(Name == "aapcs16");
4537 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
4544 // FIXME: This should be based on Arch attributes, not CPU names.
4546 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
4548 const std::vector<std::string> &FeaturesVec) const override {
4550 std::vector<const char*> TargetFeatures;
4551 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName());
4553 // get default FPU features
4554 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
4555 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
4557 // get default Extension features
4558 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
4559 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
4561 for (const char *Feature : TargetFeatures)
4562 if (Feature[0] == '+')
4563 Features[Feature+1] = true;
4565 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
4568 bool handleTargetFeatures(std::vector<std::string> &Features,
4569 DiagnosticsEngine &Diags) override {
4575 SoftFloat = SoftFloatABI = false;
4578 // This does not diagnose illegal cases like having both
4579 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
4580 uint32_t HW_FP_remove = 0;
4581 for (const auto &Feature : Features) {
4582 if (Feature == "+soft-float") {
4584 } else if (Feature == "+soft-float-abi") {
4585 SoftFloatABI = true;
4586 } else if (Feature == "+vfp2") {
4588 HW_FP |= HW_FP_SP | HW_FP_DP;
4589 } else if (Feature == "+vfp3") {
4591 HW_FP |= HW_FP_SP | HW_FP_DP;
4592 } else if (Feature == "+vfp4") {
4594 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
4595 } else if (Feature == "+fp-armv8") {
4597 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
4598 } else if (Feature == "+neon") {
4600 HW_FP |= HW_FP_SP | HW_FP_DP;
4601 } else if (Feature == "+hwdiv") {
4602 HWDiv |= HWDivThumb;
4603 } else if (Feature == "+hwdiv-arm") {
4605 } else if (Feature == "+crc") {
4607 } else if (Feature == "+crypto") {
4609 } else if (Feature == "+dsp") {
4611 } else if (Feature == "+fp-only-sp") {
4612 HW_FP_remove |= HW_FP_DP;
4613 } else if (Feature == "+strict-align") {
4615 } else if (Feature == "+fp16") {
4619 HW_FP &= ~HW_FP_remove;
4621 switch (ArchVersion) {
4623 if (ArchProfile == llvm::ARM::PK_M)
4625 else if (ArchKind == llvm::ARM::AK_ARMV6K)
4626 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
4631 if (ArchProfile == llvm::ARM::PK_M)
4632 LDREX = LDREX_W | LDREX_H | LDREX_B ;
4634 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
4637 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
4640 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4641 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4645 if (FPMath == FP_Neon)
4646 Features.push_back("+neonfp");
4647 else if (FPMath == FP_VFP)
4648 Features.push_back("-neonfp");
4650 // Remove front-end specific options which the backend handles differently.
4652 std::find(Features.begin(), Features.end(), "+soft-float-abi");
4653 if (Feature != Features.end())
4654 Features.erase(Feature);
4659 bool hasFeature(StringRef Feature) const override {
4660 return llvm::StringSwitch<bool>(Feature)
4662 .Case("aarch32", true)
4663 .Case("softfloat", SoftFloat)
4664 .Case("thumb", isThumb())
4665 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4666 .Case("hwdiv", HWDiv & HWDivThumb)
4667 .Case("hwdiv-arm", HWDiv & HWDivARM)
4671 bool setCPU(const std::string &Name) override {
4672 if (Name != "generic")
4673 setArchInfo(llvm::ARM::parseCPUArch(Name));
4675 if (ArchKind == llvm::ARM::AK_INVALID)
4682 bool setFPMath(StringRef Name) override;
4684 void getTargetDefines(const LangOptions &Opts,
4685 MacroBuilder &Builder) const override {
4686 // Target identification.
4687 Builder.defineMacro("__arm");
4688 Builder.defineMacro("__arm__");
4690 // Target properties.
4691 Builder.defineMacro("__REGISTER_PREFIX__", "");
4693 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
4694 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
4695 if (getTriple().isWatchOS())
4696 Builder.defineMacro("__ARM_ARCH_7K__", "2");
4698 if (!CPUAttr.empty())
4699 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
4701 // ACLE 6.4.1 ARM/Thumb instruction set architecture
4702 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4703 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
4705 if (ArchVersion >= 8) {
4706 // ACLE 6.5.7 Crypto Extension
4708 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
4709 // ACLE 6.5.8 CRC32 Extension
4711 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
4712 // ACLE 6.5.10 Numeric Maximum and Minimum
4713 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
4714 // ACLE 6.5.9 Directed Rounding
4715 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
4718 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
4719 // is not defined for the M-profile.
4720 // NOTE that the deffault profile is assumed to be 'A'
4721 if (CPUProfile.empty() || CPUProfile != "M")
4722 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4724 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4725 // Thumb ISA (including v6-M). It is set to 2 if the core supports the
4726 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4727 if (supportsThumb2())
4728 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4729 else if (supportsThumb())
4730 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4732 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4733 // instruction set such as ARM or Thumb.
4734 Builder.defineMacro("__ARM_32BIT_STATE", "1");
4736 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4738 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4739 if (!CPUProfile.empty())
4740 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4742 // ACLE 6.4.3 Unaligned access supported in hardware
4744 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
4746 // ACLE 6.4.4 LDREX/STREX
4748 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX));
4751 if (ArchVersion == 5 ||
4752 (ArchVersion == 6 && CPUProfile != "M") ||
4754 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
4756 // ACLE 6.5.1 Hardware Floating Point
4758 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4761 Builder.defineMacro("__ARM_ACLE", "200");
4763 // FP16 support (we currently only support IEEE format).
4764 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
4765 Builder.defineMacro("__ARM_FP16_ARGS", "1");
4767 // ACLE 6.5.3 Fused multiply-accumulate (FMA)
4768 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM"))
4769 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
4771 // Subtarget options.
4773 // FIXME: It's more complicated than this and we don't really support
4775 // Windows on ARM does not "support" interworking
4776 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows())
4777 Builder.defineMacro("__THUMB_INTERWORK__");
4779 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4780 // Embedded targets on Darwin follow AAPCS, but not EABI.
4781 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4782 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4783 Builder.defineMacro("__ARM_EABI__");
4784 Builder.defineMacro("__ARM_PCS", "1");
4786 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4787 Builder.defineMacro("__ARM_PCS_VFP", "1");
4791 Builder.defineMacro("__SOFTFP__");
4793 if (CPU == "xscale")
4794 Builder.defineMacro("__XSCALE__");
4797 Builder.defineMacro("__THUMBEL__");
4798 Builder.defineMacro("__thumb__");
4799 if (supportsThumb2())
4800 Builder.defineMacro("__thumb2__");
4803 // ACLE 6.4.9 32-bit SIMD instructions
4804 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
4805 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
4807 // ACLE 6.4.10 Hardware Integer Divide
4808 if (((HWDiv & HWDivThumb) && isThumb()) ||
4809 ((HWDiv & HWDivARM) && !isThumb())) {
4810 Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
4811 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4814 // Note, this is always on in gcc, even though it doesn't make sense.
4815 Builder.defineMacro("__APCS_32__");
4817 if (FPUModeIsVFP((FPUMode) FPU)) {
4818 Builder.defineMacro("__VFP_FP__");
4820 Builder.defineMacro("__ARM_VFPV2__");
4822 Builder.defineMacro("__ARM_VFPV3__");
4824 Builder.defineMacro("__ARM_VFPV4__");
4827 // This only gets set when Neon instructions are actually available, unlike
4828 // the VFP define, hence the soft float and arch check. This is subtly
4829 // different from gcc, we follow the intent which was that it should be set
4830 // when Neon instructions are actually available.
4831 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
4832 Builder.defineMacro("__ARM_NEON", "1");
4833 Builder.defineMacro("__ARM_NEON__");
4834 // current AArch32 NEON implementations do not support double-precision
4835 // floating-point even when it is present in VFP.
4836 Builder.defineMacro("__ARM_NEON_FP",
4837 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP));
4840 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4841 Opts.ShortWChar ? "2" : "4");
4843 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4844 Opts.ShortEnums ? "1" : "4");
4846 if (ArchVersion >= 6 && CPUAttr != "6M") {
4847 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4848 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4849 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4850 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4853 // ACLE 6.4.7 DSP instructions
4855 Builder.defineMacro("__ARM_FEATURE_DSP", "1");
4858 // ACLE 6.4.8 Saturation instructions
4860 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) {
4861 Builder.defineMacro("__ARM_FEATURE_SAT", "1");
4865 // ACLE 6.4.6 Q (saturation) flag
4867 Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
4869 if (Opts.UnsafeFPMath)
4870 Builder.defineMacro("__ARM_FP_FAST", "1");
4872 if (ArchKind == llvm::ARM::AK_ARMV8_1A)
4873 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
4876 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4877 return llvm::makeArrayRef(BuiltinInfo,
4878 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin);
4880 bool isCLZForZeroUndef() const override { return false; }
4881 BuiltinVaListKind getBuiltinVaListKind() const override {
4883 ? AAPCSABIBuiltinVaList
4884 : (getTriple().isWatchOS() ? TargetInfo::CharPtrBuiltinVaList
4885 : TargetInfo::VoidPtrBuiltinVaList);
4887 ArrayRef<const char *> getGCCRegNames() const override;
4888 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
4889 bool validateAsmConstraint(const char *&Name,
4890 TargetInfo::ConstraintInfo &Info) const override {
4895 case 'w': // VFP Floating point register single precision
4896 case 'P': // VFP Floating point register double precision
4897 Info.setAllowsRegister();
4906 case 'Q': // A memory address that is a single base register.
4907 Info.setAllowsMemory();
4909 case 'U': // a memory reference...
4911 case 'q': // ...ARMV4 ldrsb
4912 case 'v': // ...VFP load/store (reg+constant offset)
4913 case 'y': // ...iWMMXt load/store
4914 case 't': // address valid for load/store opaque types wider
4916 case 'n': // valid address for Neon doubleword vector load/store
4917 case 'm': // valid address for Neon element and structure load/store
4918 case 's': // valid address for non-offset loads/stores of quad-word
4919 // values in four ARM registers
4920 Info.setAllowsMemory();
4927 std::string convertConstraint(const char *&Constraint) const override {
4929 switch (*Constraint) {
4930 case 'U': // Two-character constraint; add "^" hint for later parsing.
4931 R = std::string("^") + std::string(Constraint, 2);
4934 case 'p': // 'p' should be translated to 'r' by default.
4935 R = std::string("r");
4938 return std::string(1, *Constraint);
4943 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4944 std::string &SuggestedModifier) const override {
4945 bool isOutput = (Constraint[0] == '=');
4946 bool isInOut = (Constraint[0] == '+');
4948 // Strip off constraint modifiers.
4949 while (Constraint[0] == '=' ||
4950 Constraint[0] == '+' ||
4951 Constraint[0] == '&')
4952 Constraint = Constraint.substr(1);
4954 switch (Constraint[0]) {
4959 return (isInOut || isOutput || Size <= 64);
4961 // A register of size 32 cannot fit a vector type.
4969 const char *getClobbers() const override {
4970 // FIXME: Is this really right?
4974 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4975 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4978 int getEHDataRegisterNumber(unsigned RegNo) const override {
4979 if (RegNo == 0) return 0;
4980 if (RegNo == 1) return 1;
4984 bool hasSjLjLowering() const override {
4989 bool ARMTargetInfo::setFPMath(StringRef Name) {
4990 if (Name == "neon") {
4993 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
5001 const char * const ARMTargetInfo::GCCRegNames[] = {
5002 // Integer registers
5003 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5004 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
5007 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
5008 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
5009 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
5010 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5013 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
5014 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
5015 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
5016 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5019 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
5020 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
5023 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
5024 return llvm::makeArrayRef(GCCRegNames);
5027 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
5037 { { "v6", "rfp" }, "r9" },
5038 { { "sl" }, "r10" },
5039 { { "fp" }, "r11" },
5040 { { "ip" }, "r12" },
5041 { { "r13" }, "sp" },
5042 { { "r14" }, "lr" },
5043 { { "r15" }, "pc" },
5044 // The S, D and Q registers overlap, but aren't really aliases; we
5045 // don't want to substitute one of these for a different-sized one.
5048 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
5049 return llvm::makeArrayRef(GCCRegAliases);
5052 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
5053 #define BUILTIN(ID, TYPE, ATTRS) \
5054 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5055 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5056 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5057 #include "clang/Basic/BuiltinsNEON.def"
5059 #define BUILTIN(ID, TYPE, ATTRS) \
5060 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5061 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \
5062 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr },
5063 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5064 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5065 #include "clang/Basic/BuiltinsARM.def"
5068 class ARMleTargetInfo : public ARMTargetInfo {
5070 ARMleTargetInfo(const llvm::Triple &Triple)
5071 : ARMTargetInfo(Triple, false) { }
5072 void getTargetDefines(const LangOptions &Opts,
5073 MacroBuilder &Builder) const override {
5074 Builder.defineMacro("__ARMEL__");
5075 ARMTargetInfo::getTargetDefines(Opts, Builder);
5079 class ARMbeTargetInfo : public ARMTargetInfo {
5081 ARMbeTargetInfo(const llvm::Triple &Triple)
5082 : ARMTargetInfo(Triple, true) { }
5083 void getTargetDefines(const LangOptions &Opts,
5084 MacroBuilder &Builder) const override {
5085 Builder.defineMacro("__ARMEB__");
5086 Builder.defineMacro("__ARM_BIG_ENDIAN");
5087 ARMTargetInfo::getTargetDefines(Opts, Builder);
5091 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
5092 const llvm::Triple Triple;
5094 WindowsARMTargetInfo(const llvm::Triple &Triple)
5095 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
5096 TLSSupported = false;
5097 WCharType = UnsignedShort;
5098 SizeType = UnsignedInt;
5099 UserLabelPrefix = "";
5101 void getVisualStudioDefines(const LangOptions &Opts,
5102 MacroBuilder &Builder) const {
5103 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
5105 // FIXME: this is invalid for WindowsCE
5106 Builder.defineMacro("_M_ARM_NT", "1");
5107 Builder.defineMacro("_M_ARMT", "_M_ARM");
5108 Builder.defineMacro("_M_THUMB", "_M_ARM");
5110 assert((Triple.getArch() == llvm::Triple::arm ||
5111 Triple.getArch() == llvm::Triple::thumb) &&
5112 "invalid architecture for Windows ARM target info");
5113 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
5114 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
5116 // TODO map the complete set of values
5117 // 31: VFPv3 40: VFPv4
5118 Builder.defineMacro("_M_ARM_FP", "31");
5120 BuiltinVaListKind getBuiltinVaListKind() const override {
5121 return TargetInfo::CharPtrBuiltinVaList;
5123 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5126 case CC_X86ThisCall:
5127 case CC_X86FastCall:
5128 case CC_X86VectorCall:
5133 return CCCR_Warning;
5138 // Windows ARM + Itanium C++ ABI Target
5139 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
5141 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
5142 : WindowsARMTargetInfo(Triple) {
5143 TheCXXABI.set(TargetCXXABI::GenericARM);
5146 void getTargetDefines(const LangOptions &Opts,
5147 MacroBuilder &Builder) const override {
5148 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5150 if (Opts.MSVCCompat)
5151 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5155 // Windows ARM, MS (C++) ABI
5156 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
5158 MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
5159 : WindowsARMTargetInfo(Triple) {
5160 TheCXXABI.set(TargetCXXABI::Microsoft);
5163 void getTargetDefines(const LangOptions &Opts,
5164 MacroBuilder &Builder) const override {
5165 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5166 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5171 class MinGWARMTargetInfo : public WindowsARMTargetInfo {
5173 MinGWARMTargetInfo(const llvm::Triple &Triple)
5174 : WindowsARMTargetInfo(Triple) {
5175 TheCXXABI.set(TargetCXXABI::GenericARM);
5178 void getTargetDefines(const LangOptions &Opts,
5179 MacroBuilder &Builder) const override {
5180 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5181 DefineStd(Builder, "WIN32", Opts);
5182 DefineStd(Builder, "WINNT", Opts);
5183 Builder.defineMacro("_ARM_");
5184 addMinGWDefines(Opts, Builder);
5188 // ARM Cygwin target
5189 class CygwinARMTargetInfo : public ARMleTargetInfo {
5191 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) {
5192 TLSSupported = false;
5193 WCharType = UnsignedShort;
5194 DoubleAlign = LongLongAlign = 64;
5195 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
5197 void getTargetDefines(const LangOptions &Opts,
5198 MacroBuilder &Builder) const override {
5199 ARMleTargetInfo::getTargetDefines(Opts, Builder);
5200 Builder.defineMacro("_ARM_");
5201 Builder.defineMacro("__CYGWIN__");
5202 Builder.defineMacro("__CYGWIN32__");
5203 DefineStd(Builder, "unix", Opts);
5205 Builder.defineMacro("_GNU_SOURCE");
5209 class DarwinARMTargetInfo :
5210 public DarwinTargetInfo<ARMleTargetInfo> {
5212 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5213 MacroBuilder &Builder) const override {
5214 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5218 DarwinARMTargetInfo(const llvm::Triple &Triple)
5219 : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
5220 HasAlignMac68kSupport = true;
5221 // iOS always has 64-bit atomic instructions.
5222 // FIXME: This should be based off of the target features in
5224 MaxAtomicInlineWidth = 64;
5226 if (Triple.isWatchOS()) {
5227 // Darwin on iOS uses a variant of the ARM C++ ABI.
5228 TheCXXABI.set(TargetCXXABI::WatchOS);
5230 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that
5231 // size_t is long, it's a bit weird for it to be int.
5232 PtrDiffType = SignedLong;
5234 // BOOL should be a real boolean on the new ABI
5235 UseSignedCharForObjCBool = false;
5237 TheCXXABI.set(TargetCXXABI::iOS);
5241 class AArch64TargetInfo : public TargetInfo {
5242 virtual void setDataLayoutString() = 0;
5243 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5244 static const char *const GCCRegNames[];
5257 static const Builtin::Info BuiltinInfo[];
5262 AArch64TargetInfo(const llvm::Triple &Triple)
5263 : TargetInfo(Triple), ABI("aapcs") {
5265 if (getTriple().getOS() == llvm::Triple::NetBSD) {
5266 WCharType = SignedInt;
5268 // NetBSD apparently prefers consistency across ARM targets to consistency
5269 // across 64-bit targets.
5270 Int64Type = SignedLongLong;
5271 IntMaxType = SignedLongLong;
5273 WCharType = UnsignedInt;
5274 Int64Type = SignedLong;
5275 IntMaxType = SignedLong;
5278 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5279 MaxVectorAlign = 128;
5280 MaxAtomicInlineWidth = 128;
5281 MaxAtomicPromoteWidth = 128;
5283 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
5284 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5286 // {} in inline assembly are neon specifiers, not assembly variant
5288 NoAsmVariants = true;
5290 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
5291 // contributes to the alignment of the containing aggregate in the same way
5292 // a plain (non bit-field) member of that type would, without exception for
5293 // zero-sized or anonymous bit-fields."
5294 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
5295 UseZeroLengthBitfieldAlignment = true;
5297 // AArch64 targets default to using the ARM C++ ABI.
5298 TheCXXABI.set(TargetCXXABI::GenericAArch64);
5301 StringRef getABI() const override { return ABI; }
5302 bool setABI(const std::string &Name) override {
5303 if (Name != "aapcs" && Name != "darwinpcs")
5310 bool setCPU(const std::string &Name) override {
5311 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5312 .Case("generic", true)
5313 .Cases("cortex-a53", "cortex-a57", "cortex-a72", "cortex-a35", true)
5314 .Case("cyclone", true)
5319 void getTargetDefines(const LangOptions &Opts,
5320 MacroBuilder &Builder) const override {
5321 // Target identification.
5322 Builder.defineMacro("__aarch64__");
5324 // Target properties.
5325 Builder.defineMacro("_LP64");
5326 Builder.defineMacro("__LP64__");
5328 // ACLE predefines. Many can only have one possible value on v8 AArch64.
5329 Builder.defineMacro("__ARM_ACLE", "200");
5330 Builder.defineMacro("__ARM_ARCH", "8");
5331 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
5333 Builder.defineMacro("__ARM_64BIT_STATE", "1");
5334 Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
5335 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
5337 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
5338 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
5339 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
5340 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
5341 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
5342 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
5343 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
5345 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
5347 // 0xe implies support for half, single and double precision operations.
5348 Builder.defineMacro("__ARM_FP", "0xE");
5350 // PCS specifies this for SysV variants, which is all we support. Other ABIs
5351 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
5352 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
5353 Builder.defineMacro("__ARM_FP16_ARGS", "1");
5355 if (Opts.UnsafeFPMath)
5356 Builder.defineMacro("__ARM_FP_FAST", "1");
5358 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
5360 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5361 Opts.ShortEnums ? "1" : "4");
5363 if (FPU == NeonMode) {
5364 Builder.defineMacro("__ARM_NEON", "1");
5365 // 64-bit NEON supports half, single and double precision operations.
5366 Builder.defineMacro("__ARM_NEON_FP", "0xE");
5370 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
5373 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
5376 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
5379 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
5381 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
5382 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
5383 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
5384 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
5385 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
5388 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5389 return llvm::makeArrayRef(BuiltinInfo,
5390 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin);
5393 bool hasFeature(StringRef Feature) const override {
5394 return Feature == "aarch64" ||
5395 Feature == "arm64" ||
5397 (Feature == "neon" && FPU == NeonMode);
5400 bool handleTargetFeatures(std::vector<std::string> &Features,
5401 DiagnosticsEngine &Diags) override {
5408 for (const auto &Feature : Features) {
5409 if (Feature == "+neon")
5411 if (Feature == "+crc")
5413 if (Feature == "+crypto")
5415 if (Feature == "+strict-align")
5417 if (Feature == "+v8.1a")
5421 setDataLayoutString();
5426 bool isCLZForZeroUndef() const override { return false; }
5428 BuiltinVaListKind getBuiltinVaListKind() const override {
5429 return TargetInfo::AArch64ABIBuiltinVaList;
5432 ArrayRef<const char *> getGCCRegNames() const override;
5433 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5435 bool validateAsmConstraint(const char *&Name,
5436 TargetInfo::ConstraintInfo &Info) const override {
5440 case 'w': // Floating point and SIMD registers (V0-V31)
5441 Info.setAllowsRegister();
5443 case 'I': // Constant that can be used with an ADD instruction
5444 case 'J': // Constant that can be used with a SUB instruction
5445 case 'K': // Constant that can be used with a 32-bit logical instruction
5446 case 'L': // Constant that can be used with a 64-bit logical instruction
5447 case 'M': // Constant that can be used as a 32-bit MOV immediate
5448 case 'N': // Constant that can be used as a 64-bit MOV immediate
5449 case 'Y': // Floating point constant zero
5450 case 'Z': // Integer constant zero
5452 case 'Q': // A memory reference with base register and no offset
5453 Info.setAllowsMemory();
5455 case 'S': // A symbolic address
5456 Info.setAllowsRegister();
5459 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
5460 // Utf: A memory address suitable for ldp/stp in TF mode.
5461 // Usa: An absolute symbolic address.
5462 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
5463 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
5464 case 'z': // Zero register, wzr or xzr
5465 Info.setAllowsRegister();
5467 case 'x': // Floating point and SIMD registers (V0-V15)
5468 Info.setAllowsRegister();
5475 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5476 std::string &SuggestedModifier) const override {
5477 // Strip off constraint modifiers.
5478 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
5479 Constraint = Constraint.substr(1);
5481 switch (Constraint[0]) {
5489 // For now assume that the person knows what they're
5490 // doing with the modifier.
5493 // By default an 'r' constraint will be in the 'x'
5498 SuggestedModifier = "w";
5505 const char *getClobbers() const override { return ""; }
5507 int getEHDataRegisterNumber(unsigned RegNo) const override {
5516 const char *const AArch64TargetInfo::GCCRegNames[] = {
5517 // 32-bit Integer registers
5518 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
5519 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
5520 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
5522 // 64-bit Integer registers
5523 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
5524 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
5525 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
5527 // 32-bit floating point regsisters
5528 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
5529 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
5530 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5532 // 64-bit floating point regsisters
5533 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
5534 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
5535 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5538 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
5539 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
5540 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
5543 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
5544 return llvm::makeArrayRef(GCCRegNames);
5547 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
5548 { { "w31" }, "wsp" },
5549 { { "x29" }, "fp" },
5550 { { "x30" }, "lr" },
5551 { { "x31" }, "sp" },
5552 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
5553 // don't want to substitute one of these for a different-sized one.
5556 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
5557 return llvm::makeArrayRef(GCCRegAliases);
5560 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
5561 #define BUILTIN(ID, TYPE, ATTRS) \
5562 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5563 #include "clang/Basic/BuiltinsNEON.def"
5565 #define BUILTIN(ID, TYPE, ATTRS) \
5566 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5567 #include "clang/Basic/BuiltinsAArch64.def"
5570 class AArch64leTargetInfo : public AArch64TargetInfo {
5571 void setDataLayoutString() override {
5572 if (getTriple().isOSBinFormatMachO())
5573 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128";
5575 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128";
5579 AArch64leTargetInfo(const llvm::Triple &Triple)
5580 : AArch64TargetInfo(Triple) {
5583 void getTargetDefines(const LangOptions &Opts,
5584 MacroBuilder &Builder) const override {
5585 Builder.defineMacro("__AARCH64EL__");
5586 AArch64TargetInfo::getTargetDefines(Opts, Builder);
5590 class AArch64beTargetInfo : public AArch64TargetInfo {
5591 void setDataLayoutString() override {
5592 assert(!getTriple().isOSBinFormatMachO());
5593 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128";
5597 AArch64beTargetInfo(const llvm::Triple &Triple)
5598 : AArch64TargetInfo(Triple) { }
5599 void getTargetDefines(const LangOptions &Opts,
5600 MacroBuilder &Builder) const override {
5601 Builder.defineMacro("__AARCH64EB__");
5602 Builder.defineMacro("__AARCH_BIG_ENDIAN");
5603 Builder.defineMacro("__ARM_BIG_ENDIAN");
5604 AArch64TargetInfo::getTargetDefines(Opts, Builder);
5608 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
5610 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5611 MacroBuilder &Builder) const override {
5612 Builder.defineMacro("__AARCH64_SIMD__");
5613 Builder.defineMacro("__ARM64_ARCH_8__");
5614 Builder.defineMacro("__ARM_NEON__");
5615 Builder.defineMacro("__LITTLE_ENDIAN__");
5616 Builder.defineMacro("__REGISTER_PREFIX__", "");
5617 Builder.defineMacro("__arm64", "1");
5618 Builder.defineMacro("__arm64__", "1");
5620 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5624 DarwinAArch64TargetInfo(const llvm::Triple &Triple)
5625 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
5626 Int64Type = SignedLongLong;
5627 WCharType = SignedInt;
5628 UseSignedCharForObjCBool = false;
5630 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
5631 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5633 TheCXXABI.set(TargetCXXABI::iOS64);
5636 BuiltinVaListKind getBuiltinVaListKind() const override {
5637 return TargetInfo::CharPtrBuiltinVaList;
5641 // Hexagon abstract base class
5642 class HexagonTargetInfo : public TargetInfo {
5643 static const Builtin::Info BuiltinInfo[];
5644 static const char * const GCCRegNames[];
5645 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5647 bool HasHVX, HasHVXDouble;
5650 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5652 DataLayoutString = "e-m:e-p:32:32:32-"
5653 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-"
5654 "f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32";
5655 SizeType = UnsignedInt;
5656 PtrDiffType = SignedInt;
5657 IntPtrType = SignedInt;
5659 // {} in inline assembly are packet specifiers, not assembly variant
5661 NoAsmVariants = true;
5663 LargeArrayMinWidth = 64;
5664 LargeArrayAlign = 64;
5665 UseBitFieldTypeAlignment = true;
5666 ZeroLengthBitfieldBoundary = 32;
5667 HasHVX = HasHVXDouble = false;
5670 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5671 return llvm::makeArrayRef(BuiltinInfo,
5672 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin);
5675 bool validateAsmConstraint(const char *&Name,
5676 TargetInfo::ConstraintInfo &Info) const override {
5680 void getTargetDefines(const LangOptions &Opts,
5681 MacroBuilder &Builder) const override;
5683 bool isCLZForZeroUndef() const override { return false; }
5685 bool hasFeature(StringRef Feature) const override {
5686 return llvm::StringSwitch<bool>(Feature)
5687 .Case("hexagon", true)
5688 .Case("hvx", HasHVX)
5689 .Case("hvx-double", HasHVXDouble)
5693 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
5694 StringRef CPU, const std::vector<std::string> &FeaturesVec)
5697 bool handleTargetFeatures(std::vector<std::string> &Features,
5698 DiagnosticsEngine &Diags) override;
5700 BuiltinVaListKind getBuiltinVaListKind() const override {
5701 return TargetInfo::CharPtrBuiltinVaList;
5703 ArrayRef<const char *> getGCCRegNames() const override;
5704 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5705 const char *getClobbers() const override {
5709 static const char *getHexagonCPUSuffix(StringRef Name) {
5710 return llvm::StringSwitch<const char*>(Name)
5711 .Case("hexagonv4", "4")
5712 .Case("hexagonv5", "5")
5713 .Case("hexagonv55", "55")
5714 .Case("hexagonv60", "60")
5718 bool setCPU(const std::string &Name) override {
5719 if (!getHexagonCPUSuffix(Name))
5725 int getEHDataRegisterNumber(unsigned RegNo) const override {
5726 return RegNo < 2 ? RegNo : -1;
5730 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5731 MacroBuilder &Builder) const {
5732 Builder.defineMacro("__qdsp6__", "1");
5733 Builder.defineMacro("__hexagon__", "1");
5735 if (CPU == "hexagonv4") {
5736 Builder.defineMacro("__HEXAGON_V4__");
5737 Builder.defineMacro("__HEXAGON_ARCH__", "4");
5738 if (Opts.HexagonQdsp6Compat) {
5739 Builder.defineMacro("__QDSP6_V4__");
5740 Builder.defineMacro("__QDSP6_ARCH__", "4");
5742 } else if (CPU == "hexagonv5") {
5743 Builder.defineMacro("__HEXAGON_V5__");
5744 Builder.defineMacro("__HEXAGON_ARCH__", "5");
5745 if(Opts.HexagonQdsp6Compat) {
5746 Builder.defineMacro("__QDSP6_V5__");
5747 Builder.defineMacro("__QDSP6_ARCH__", "5");
5749 } else if (CPU == "hexagonv60") {
5750 Builder.defineMacro("__HEXAGON_V60__");
5751 Builder.defineMacro("__HEXAGON_ARCH__", "60");
5752 Builder.defineMacro("__QDSP6_V60__");
5753 Builder.defineMacro("__QDSP6_ARCH__", "60");
5757 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
5758 DiagnosticsEngine &Diags) {
5759 for (auto &F : Features) {
5762 else if (F == "-hvx")
5763 HasHVX = HasHVXDouble = false;
5764 else if (F == "+hvx-double")
5765 HasHVX = HasHVXDouble = true;
5766 else if (F == "-hvx-double")
5767 HasHVXDouble = false;
5772 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features,
5773 DiagnosticsEngine &Diags, StringRef CPU,
5774 const std::vector<std::string> &FeaturesVec) const {
5775 // Default for v60: -hvx, -hvx-double.
5776 Features["hvx"] = false;
5777 Features["hvx-double"] = false;
5779 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
5783 const char *const HexagonTargetInfo::GCCRegNames[] = {
5784 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5785 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5786 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5787 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5788 "p0", "p1", "p2", "p3",
5789 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5792 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const {
5793 return llvm::makeArrayRef(GCCRegNames);
5796 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5797 { { "sp" }, "r29" },
5798 { { "fp" }, "r30" },
5799 { { "lr" }, "r31" },
5802 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const {
5803 return llvm::makeArrayRef(GCCRegAliases);
5807 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5808 #define BUILTIN(ID, TYPE, ATTRS) \
5809 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5810 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5811 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5812 #include "clang/Basic/BuiltinsHexagon.def"
5815 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5816 class SparcTargetInfo : public TargetInfo {
5817 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5818 static const char * const GCCRegNames[];
5821 SparcTargetInfo(const llvm::Triple &Triple)
5822 : TargetInfo(Triple), SoftFloat(false) {}
5824 bool handleTargetFeatures(std::vector<std::string> &Features,
5825 DiagnosticsEngine &Diags) override {
5826 // The backend doesn't actually handle soft float yet, but in case someone
5827 // is using the support for the front end continue to support it.
5828 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
5829 if (Feature != Features.end()) {
5831 Features.erase(Feature);
5835 void getTargetDefines(const LangOptions &Opts,
5836 MacroBuilder &Builder) const override {
5837 DefineStd(Builder, "sparc", Opts);
5838 Builder.defineMacro("__REGISTER_PREFIX__", "");
5841 Builder.defineMacro("SOFT_FLOAT", "1");
5844 bool hasFeature(StringRef Feature) const override {
5845 return llvm::StringSwitch<bool>(Feature)
5846 .Case("softfloat", SoftFloat)
5847 .Case("sparc", true)
5851 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5852 // FIXME: Implement!
5855 BuiltinVaListKind getBuiltinVaListKind() const override {
5856 return TargetInfo::VoidPtrBuiltinVaList;
5858 ArrayRef<const char *> getGCCRegNames() const override;
5859 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5860 bool validateAsmConstraint(const char *&Name,
5861 TargetInfo::ConstraintInfo &info) const override {
5862 // FIXME: Implement!
5864 case 'I': // Signed 13-bit constant
5866 case 'K': // 32-bit constant with the low 12 bits clear
5867 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5868 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5869 case 'N': // Same as 'K' but zext (required for SIMode)
5870 case 'O': // The constant 4096
5875 const char *getClobbers() const override {
5876 // FIXME: Implement!
5880 // No Sparc V7 for now, the backend doesn't support it anyway.
5900 enum CPUGeneration {
5905 CPUGeneration getCPUGeneration(CPUKind Kind) const {
5913 case CK_SPARCLITE86X:
5919 case CK_ULTRASPARC3:
5926 llvm_unreachable("Unexpected CPU kind");
5929 CPUKind getCPUKind(StringRef Name) const {
5930 return llvm::StringSwitch<CPUKind>(Name)
5932 .Case("supersparc", CK_SUPERSPARC)
5933 .Case("sparclite", CK_SPARCLITE)
5934 .Case("f934", CK_F934)
5935 .Case("hypersparc", CK_HYPERSPARC)
5936 .Case("sparclite86x", CK_SPARCLITE86X)
5937 .Case("sparclet", CK_SPARCLET)
5938 .Case("tsc701", CK_TSC701)
5940 .Case("ultrasparc", CK_ULTRASPARC)
5941 .Case("ultrasparc3", CK_ULTRASPARC3)
5942 .Case("niagara", CK_NIAGARA)
5943 .Case("niagara2", CK_NIAGARA2)
5944 .Case("niagara3", CK_NIAGARA3)
5945 .Case("niagara4", CK_NIAGARA4)
5946 .Default(CK_GENERIC);
5949 bool setCPU(const std::string &Name) override {
5950 CPU = getCPUKind(Name);
5951 return CPU != CK_GENERIC;
5955 const char * const SparcTargetInfo::GCCRegNames[] = {
5956 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5957 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5958 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5959 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5962 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
5963 return llvm::makeArrayRef(GCCRegNames);
5966 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5977 { { "o2" }, "r10" },
5978 { { "o3" }, "r11" },
5979 { { "o4" }, "r12" },
5980 { { "o5" }, "r13" },
5981 { { "o6", "sp" }, "r14" },
5982 { { "o7" }, "r15" },
5983 { { "l0" }, "r16" },
5984 { { "l1" }, "r17" },
5985 { { "l2" }, "r18" },
5986 { { "l3" }, "r19" },
5987 { { "l4" }, "r20" },
5988 { { "l5" }, "r21" },
5989 { { "l6" }, "r22" },
5990 { { "l7" }, "r23" },
5991 { { "i0" }, "r24" },
5992 { { "i1" }, "r25" },
5993 { { "i2" }, "r26" },
5994 { { "i3" }, "r27" },
5995 { { "i4" }, "r28" },
5996 { { "i5" }, "r29" },
5997 { { "i6", "fp" }, "r30" },
5998 { { "i7" }, "r31" },
6001 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
6002 return llvm::makeArrayRef(GCCRegAliases);
6005 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
6006 class SparcV8TargetInfo : public SparcTargetInfo {
6008 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
6009 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
6010 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
6011 switch (getTriple().getOS()) {
6013 SizeType = UnsignedInt;
6014 IntPtrType = SignedInt;
6015 PtrDiffType = SignedInt;
6017 case llvm::Triple::NetBSD:
6018 case llvm::Triple::OpenBSD:
6019 SizeType = UnsignedLong;
6020 IntPtrType = SignedLong;
6021 PtrDiffType = SignedLong;
6026 void getTargetDefines(const LangOptions &Opts,
6027 MacroBuilder &Builder) const override {
6028 SparcTargetInfo::getTargetDefines(Opts, Builder);
6029 switch (getCPUGeneration(CPU)) {
6031 Builder.defineMacro("__sparcv8");
6032 if (getTriple().getOS() != llvm::Triple::Solaris)
6033 Builder.defineMacro("__sparcv8__");
6036 Builder.defineMacro("__sparcv9");
6037 if (getTriple().getOS() != llvm::Triple::Solaris) {
6038 Builder.defineMacro("__sparcv9__");
6039 Builder.defineMacro("__sparc_v9__");
6046 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
6047 class SparcV8elTargetInfo : public SparcV8TargetInfo {
6049 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) {
6050 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64";
6055 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
6056 class SparcV9TargetInfo : public SparcTargetInfo {
6058 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
6059 // FIXME: Support Sparc quad-precision long double?
6060 DataLayoutString = "E-m:e-i64:64-n32:64-S128";
6061 // This is an LP64 platform.
6062 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6064 // OpenBSD uses long long for int64_t and intmax_t.
6065 if (getTriple().getOS() == llvm::Triple::OpenBSD)
6066 IntMaxType = SignedLongLong;
6068 IntMaxType = SignedLong;
6069 Int64Type = IntMaxType;
6071 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
6072 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
6073 LongDoubleWidth = 128;
6074 LongDoubleAlign = 128;
6075 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6076 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6079 void getTargetDefines(const LangOptions &Opts,
6080 MacroBuilder &Builder) const override {
6081 SparcTargetInfo::getTargetDefines(Opts, Builder);
6082 Builder.defineMacro("__sparcv9");
6083 Builder.defineMacro("__arch64__");
6084 // Solaris doesn't need these variants, but the BSDs do.
6085 if (getTriple().getOS() != llvm::Triple::Solaris) {
6086 Builder.defineMacro("__sparc64__");
6087 Builder.defineMacro("__sparc_v9__");
6088 Builder.defineMacro("__sparcv9__");
6092 bool setCPU(const std::string &Name) override {
6093 if (!SparcTargetInfo::setCPU(Name))
6095 return getCPUGeneration(CPU) == CG_V9;
6099 class SystemZTargetInfo : public TargetInfo {
6100 static const Builtin::Info BuiltinInfo[];
6101 static const char *const GCCRegNames[];
6103 bool HasTransactionalExecution;
6107 SystemZTargetInfo(const llvm::Triple &Triple)
6108 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false),
6110 IntMaxType = SignedLong;
6111 Int64Type = SignedLong;
6112 TLSSupported = true;
6113 IntWidth = IntAlign = 32;
6114 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
6115 PointerWidth = PointerAlign = 64;
6116 LongDoubleWidth = 128;
6117 LongDoubleAlign = 64;
6118 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6119 DefaultAlignForAttributeAligned = 64;
6120 MinGlobalAlign = 16;
6121 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
6122 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6124 void getTargetDefines(const LangOptions &Opts,
6125 MacroBuilder &Builder) const override {
6126 Builder.defineMacro("__s390__");
6127 Builder.defineMacro("__s390x__");
6128 Builder.defineMacro("__zarch__");
6129 Builder.defineMacro("__LONG_DOUBLE_128__");
6130 if (HasTransactionalExecution)
6131 Builder.defineMacro("__HTM__");
6133 Builder.defineMacro("__VEC__", "10301");
6135 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6136 return llvm::makeArrayRef(BuiltinInfo,
6137 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin);
6140 ArrayRef<const char *> getGCCRegNames() const override;
6141 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6145 bool validateAsmConstraint(const char *&Name,
6146 TargetInfo::ConstraintInfo &info) const override;
6147 const char *getClobbers() const override {
6148 // FIXME: Is this really right?
6151 BuiltinVaListKind getBuiltinVaListKind() const override {
6152 return TargetInfo::SystemZBuiltinVaList;
6154 bool setCPU(const std::string &Name) override {
6156 bool CPUKnown = llvm::StringSwitch<bool>(Name)
6159 .Case("zEC12", true)
6166 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6168 const std::vector<std::string> &FeaturesVec) const override {
6170 Features["transactional-execution"] = true;
6172 Features["transactional-execution"] = true;
6173 Features["vector"] = true;
6175 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6178 bool handleTargetFeatures(std::vector<std::string> &Features,
6179 DiagnosticsEngine &Diags) override {
6180 HasTransactionalExecution = false;
6181 for (const auto &Feature : Features) {
6182 if (Feature == "+transactional-execution")
6183 HasTransactionalExecution = true;
6184 else if (Feature == "+vector")
6187 // If we use the vector ABI, vector types are 64-bit aligned.
6189 MaxVectorAlign = 64;
6190 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
6191 "-v128:64-a:8:16-n32:64";
6196 bool hasFeature(StringRef Feature) const override {
6197 return llvm::StringSwitch<bool>(Feature)
6198 .Case("systemz", true)
6199 .Case("htm", HasTransactionalExecution)
6200 .Case("vx", HasVector)
6204 StringRef getABI() const override {
6210 bool useFloat128ManglingForLongDouble() const override {
6215 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
6216 #define BUILTIN(ID, TYPE, ATTRS) \
6217 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6218 #include "clang/Basic/BuiltinsSystemZ.def"
6221 const char *const SystemZTargetInfo::GCCRegNames[] = {
6222 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6223 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6224 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
6225 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
6228 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
6229 return llvm::makeArrayRef(GCCRegNames);
6232 bool SystemZTargetInfo::
6233 validateAsmConstraint(const char *&Name,
6234 TargetInfo::ConstraintInfo &Info) const {
6239 case 'a': // Address register
6240 case 'd': // Data register (equivalent to 'r')
6241 case 'f': // Floating-point register
6242 Info.setAllowsRegister();
6245 case 'I': // Unsigned 8-bit constant
6246 case 'J': // Unsigned 12-bit constant
6247 case 'K': // Signed 16-bit constant
6248 case 'L': // Signed 20-bit displacement (on all targets we support)
6249 case 'M': // 0x7fffffff
6252 case 'Q': // Memory with base and unsigned 12-bit displacement
6253 case 'R': // Likewise, plus an index
6254 case 'S': // Memory with base and signed 20-bit displacement
6255 case 'T': // Likewise, plus an index
6256 Info.setAllowsMemory();
6261 class MSP430TargetInfo : public TargetInfo {
6262 static const char *const GCCRegNames[];
6265 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6267 TLSSupported = false;
6272 LongAlign = LongLongAlign = 16;
6276 SizeType = UnsignedInt;
6277 IntMaxType = SignedLongLong;
6278 IntPtrType = SignedInt;
6279 PtrDiffType = SignedInt;
6280 SigAtomicType = SignedLong;
6281 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
6283 void getTargetDefines(const LangOptions &Opts,
6284 MacroBuilder &Builder) const override {
6285 Builder.defineMacro("MSP430");
6286 Builder.defineMacro("__MSP430__");
6287 // FIXME: defines for different 'flavours' of MCU
6289 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6290 // FIXME: Implement.
6293 bool hasFeature(StringRef Feature) const override {
6294 return Feature == "msp430";
6296 ArrayRef<const char *> getGCCRegNames() const override;
6297 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6301 bool validateAsmConstraint(const char *&Name,
6302 TargetInfo::ConstraintInfo &info) const override {
6305 case 'K': // the constant 1
6306 case 'L': // constant -1^20 .. 1^19
6307 case 'M': // constant 1-4:
6310 // No target constraints for now.
6313 const char *getClobbers() const override {
6314 // FIXME: Is this really right?
6317 BuiltinVaListKind getBuiltinVaListKind() const override {
6319 return TargetInfo::CharPtrBuiltinVaList;
6323 const char *const MSP430TargetInfo::GCCRegNames[] = {
6324 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6325 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
6327 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const {
6328 return llvm::makeArrayRef(GCCRegNames);
6331 // LLVM and Clang cannot be used directly to output native binaries for
6332 // target, but is used to compile C code to llvm bitcode with correct
6333 // type and alignment information.
6335 // TCE uses the llvm bitcode as input and uses it for generating customized
6336 // target processor and program binary. TCE co-design environment is
6337 // publicly available in http://tce.cs.tut.fi
6339 static const unsigned TCEOpenCLAddrSpaceMap[] = {
6342 5, // opencl_constant
6343 // FIXME: generic has to be added to the target
6344 0, // opencl_generic
6350 class TCETargetInfo : public TargetInfo {
6352 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6353 TLSSupported = false;
6355 LongWidth = LongLongWidth = 32;
6358 LongAlign = LongLongAlign = 32;
6361 SizeType = UnsignedInt;
6362 IntMaxType = SignedLong;
6363 IntPtrType = SignedInt;
6364 PtrDiffType = SignedInt;
6369 LongDoubleWidth = 32;
6370 LongDoubleAlign = 32;
6371 FloatFormat = &llvm::APFloat::IEEEsingle;
6372 DoubleFormat = &llvm::APFloat::IEEEsingle;
6373 LongDoubleFormat = &llvm::APFloat::IEEEsingle;
6374 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
6375 "-f64:32-v64:32-v128:32-a:0:32-n32";
6376 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
6377 UseAddrSpaceMapMangling = true;
6380 void getTargetDefines(const LangOptions &Opts,
6381 MacroBuilder &Builder) const override {
6382 DefineStd(Builder, "tce", Opts);
6383 Builder.defineMacro("__TCE__");
6384 Builder.defineMacro("__TCE_V1__");
6386 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; }
6388 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
6389 const char *getClobbers() const override { return ""; }
6390 BuiltinVaListKind getBuiltinVaListKind() const override {
6391 return TargetInfo::VoidPtrBuiltinVaList;
6393 ArrayRef<const char *> getGCCRegNames() const override { return None; }
6394 bool validateAsmConstraint(const char *&Name,
6395 TargetInfo::ConstraintInfo &info) const override {
6398 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6403 class BPFTargetInfo : public TargetInfo {
6405 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6406 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6407 SizeType = UnsignedLong;
6408 PtrDiffType = SignedLong;
6409 IntPtrType = SignedLong;
6410 IntMaxType = SignedLong;
6411 Int64Type = SignedLong;
6413 if (Triple.getArch() == llvm::Triple::bpfeb) {
6415 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128";
6418 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128";
6420 MaxAtomicPromoteWidth = 64;
6421 MaxAtomicInlineWidth = 64;
6422 TLSSupported = false;
6424 void getTargetDefines(const LangOptions &Opts,
6425 MacroBuilder &Builder) const override {
6426 DefineStd(Builder, "bpf", Opts);
6427 Builder.defineMacro("__BPF__");
6429 bool hasFeature(StringRef Feature) const override {
6430 return Feature == "bpf";
6433 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
6434 const char *getClobbers() const override {
6437 BuiltinVaListKind getBuiltinVaListKind() const override {
6438 return TargetInfo::VoidPtrBuiltinVaList;
6440 ArrayRef<const char *> getGCCRegNames() const override {
6443 bool validateAsmConstraint(const char *&Name,
6444 TargetInfo::ConstraintInfo &info) const override {
6447 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6452 class MipsTargetInfoBase : public TargetInfo {
6453 virtual void setDataLayoutString() = 0;
6455 static const Builtin::Info BuiltinInfo[];
6462 HardFloat, SoftFloat
6474 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
6475 const std::string &CPUStr)
6476 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
6477 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
6478 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
6479 TheCXXABI.set(TargetCXXABI::GenericMIPS);
6482 bool isNaN2008Default() const {
6483 return CPU == "mips32r6" || CPU == "mips64r6";
6486 bool isFP64Default() const {
6487 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
6490 bool isNan2008() const override {
6494 StringRef getABI() const override { return ABI; }
6495 bool setCPU(const std::string &Name) override {
6496 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
6497 getTriple().getArch() == llvm::Triple::mipsel;
6499 return llvm::StringSwitch<bool>(Name)
6500 .Case("mips1", IsMips32)
6501 .Case("mips2", IsMips32)
6502 .Case("mips3", true)
6503 .Case("mips4", true)
6504 .Case("mips5", true)
6505 .Case("mips32", IsMips32)
6506 .Case("mips32r2", IsMips32)
6507 .Case("mips32r3", IsMips32)
6508 .Case("mips32r5", IsMips32)
6509 .Case("mips32r6", IsMips32)
6510 .Case("mips64", true)
6511 .Case("mips64r2", true)
6512 .Case("mips64r3", true)
6513 .Case("mips64r5", true)
6514 .Case("mips64r6", true)
6515 .Case("octeon", true)
6516 .Case("p5600", true)
6519 const std::string& getCPU() const { return CPU; }
6521 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6523 const std::vector<std::string> &FeaturesVec) const override {
6524 if (CPU == "octeon")
6525 Features["mips64r2"] = Features["cnmips"] = true;
6527 Features[CPU] = true;
6528 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6531 void getTargetDefines(const LangOptions &Opts,
6532 MacroBuilder &Builder) const override {
6533 Builder.defineMacro("__mips__");
6534 Builder.defineMacro("_mips");
6536 Builder.defineMacro("mips");
6538 Builder.defineMacro("__REGISTER_PREFIX__", "");
6542 Builder.defineMacro("__mips_hard_float", Twine(1));
6545 Builder.defineMacro("__mips_soft_float", Twine(1));
6550 Builder.defineMacro("__mips_single_float", Twine(1));
6552 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
6553 Builder.defineMacro("_MIPS_FPSET",
6554 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
6557 Builder.defineMacro("__mips16", Twine(1));
6560 Builder.defineMacro("__mips_micromips", Twine(1));
6563 Builder.defineMacro("__mips_nan2008", Twine(1));
6569 Builder.defineMacro("__mips_dsp_rev", Twine(1));
6570 Builder.defineMacro("__mips_dsp", Twine(1));
6573 Builder.defineMacro("__mips_dsp_rev", Twine(2));
6574 Builder.defineMacro("__mips_dspr2", Twine(1));
6575 Builder.defineMacro("__mips_dsp", Twine(1));
6580 Builder.defineMacro("__mips_msa", Twine(1));
6582 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
6583 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
6584 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
6586 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
6587 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
6589 // These shouldn't be defined for MIPS-I but there's no need to check
6590 // for that since MIPS-I isn't supported.
6591 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
6592 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
6593 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
6596 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6597 return llvm::makeArrayRef(BuiltinInfo,
6598 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin);
6600 bool hasFeature(StringRef Feature) const override {
6601 return llvm::StringSwitch<bool>(Feature)
6603 .Case("fp64", HasFP64)
6606 BuiltinVaListKind getBuiltinVaListKind() const override {
6607 return TargetInfo::VoidPtrBuiltinVaList;
6609 ArrayRef<const char *> getGCCRegNames() const override {
6610 static const char *const GCCRegNames[] = {
6611 // CPU register names
6612 // Must match second column of GCCRegAliases
6613 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
6614 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
6615 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
6616 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
6617 // Floating point register names
6618 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
6619 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
6620 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
6621 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
6622 // Hi/lo and condition register names
6623 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
6624 "$fcc5","$fcc6","$fcc7",
6625 // MSA register names
6626 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
6627 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
6628 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
6629 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
6630 // MSA control register names
6631 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
6632 "$msarequest", "$msamap", "$msaunmap"
6634 return llvm::makeArrayRef(GCCRegNames);
6636 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0;
6637 bool validateAsmConstraint(const char *&Name,
6638 TargetInfo::ConstraintInfo &Info) const override {
6642 case 'r': // CPU registers.
6643 case 'd': // Equivalent to "r" unless generating MIPS16 code.
6644 case 'y': // Equivalent to "r", backward compatibility only.
6645 case 'f': // floating-point registers.
6646 case 'c': // $25 for indirect jumps
6647 case 'l': // lo register
6648 case 'x': // hilo register pair
6649 Info.setAllowsRegister();
6651 case 'I': // Signed 16-bit constant
6652 case 'J': // Integer 0
6653 case 'K': // Unsigned 16-bit constant
6654 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
6655 case 'M': // Constants not loadable via lui, addiu, or ori
6656 case 'N': // Constant -1 to -65535
6657 case 'O': // A signed 15-bit constant
6658 case 'P': // A constant between 1 go 65535
6660 case 'R': // An address that can be used in a non-macro load or store
6661 Info.setAllowsMemory();
6664 if (Name[1] == 'C') { // An address usable by ll, and sc.
6665 Info.setAllowsMemory();
6666 Name++; // Skip over 'Z'.
6673 std::string convertConstraint(const char *&Constraint) const override {
6675 switch (*Constraint) {
6676 case 'Z': // Two-character constraint; add "^" hint for later parsing.
6677 if (Constraint[1] == 'C') {
6678 R = std::string("^") + std::string(Constraint, 2);
6684 return TargetInfo::convertConstraint(Constraint);
6687 const char *getClobbers() const override {
6688 // In GCC, $1 is not widely used in generated code (it's used only in a few
6689 // specific situations), so there is no real need for users to add it to
6690 // the clobbers list if they want to use it in their inline assembly code.
6692 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
6693 // code generation, so using it in inline assembly without adding it to the
6694 // clobbers list can cause conflicts between the inline assembly code and
6695 // the surrounding generated code.
6697 // Another problem is that LLVM is allowed to choose $1 for inline assembly
6698 // operands, which will conflict with the ".set at" assembler option (which
6699 // we use only for inline assembly, in order to maintain compatibility with
6700 // GCC) and will also conflict with the user's usage of $1.
6702 // The easiest way to avoid these conflicts and keep $1 as an allocatable
6703 // register for generated code is to automatically clobber $1 for all inline
6706 // FIXME: We should automatically clobber $1 only for inline assembly code
6707 // which actually uses it. This would allow LLVM to use $1 for inline
6708 // assembly operands if the user's assembly code doesn't use it.
6712 bool handleTargetFeatures(std::vector<std::string> &Features,
6713 DiagnosticsEngine &Diags) override {
6715 IsMicromips = false;
6716 IsNan2008 = isNaN2008Default();
6717 IsSingleFloat = false;
6718 FloatABI = HardFloat;
6720 HasFP64 = isFP64Default();
6722 for (const auto &Feature : Features) {
6723 if (Feature == "+single-float")
6724 IsSingleFloat = true;
6725 else if (Feature == "+soft-float")
6726 FloatABI = SoftFloat;
6727 else if (Feature == "+mips16")
6729 else if (Feature == "+micromips")
6731 else if (Feature == "+dsp")
6732 DspRev = std::max(DspRev, DSP1);
6733 else if (Feature == "+dspr2")
6734 DspRev = std::max(DspRev, DSP2);
6735 else if (Feature == "+msa")
6737 else if (Feature == "+fp64")
6739 else if (Feature == "-fp64")
6741 else if (Feature == "+nan2008")
6743 else if (Feature == "-nan2008")
6747 setDataLayoutString();
6752 int getEHDataRegisterNumber(unsigned RegNo) const override {
6753 if (RegNo == 0) return 4;
6754 if (RegNo == 1) return 5;
6758 bool isCLZForZeroUndef() const override { return false; }
6761 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
6762 #define BUILTIN(ID, TYPE, ATTRS) \
6763 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6764 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6765 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6766 #include "clang/Basic/BuiltinsMips.def"
6769 class Mips32TargetInfoBase : public MipsTargetInfoBase {
6771 Mips32TargetInfoBase(const llvm::Triple &Triple)
6772 : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
6773 SizeType = UnsignedInt;
6774 PtrDiffType = SignedInt;
6775 Int64Type = SignedLongLong;
6776 IntMaxType = Int64Type;
6777 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
6779 bool setABI(const std::string &Name) override {
6780 if (Name == "o32" || Name == "eabi") {
6786 void getTargetDefines(const LangOptions &Opts,
6787 MacroBuilder &Builder) const override {
6788 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6790 Builder.defineMacro("__mips", "32");
6791 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
6793 const std::string& CPUStr = getCPU();
6794 if (CPUStr == "mips32")
6795 Builder.defineMacro("__mips_isa_rev", "1");
6796 else if (CPUStr == "mips32r2")
6797 Builder.defineMacro("__mips_isa_rev", "2");
6798 else if (CPUStr == "mips32r3")
6799 Builder.defineMacro("__mips_isa_rev", "3");
6800 else if (CPUStr == "mips32r5")
6801 Builder.defineMacro("__mips_isa_rev", "5");
6802 else if (CPUStr == "mips32r6")
6803 Builder.defineMacro("__mips_isa_rev", "6");
6806 Builder.defineMacro("__mips_o32");
6807 Builder.defineMacro("_ABIO32", "1");
6808 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
6810 else if (ABI == "eabi")
6811 Builder.defineMacro("__mips_eabi");
6813 llvm_unreachable("Invalid ABI for Mips32.");
6815 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6816 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6826 { { "t2" }, "$10" },
6827 { { "t3" }, "$11" },
6828 { { "t4" }, "$12" },
6829 { { "t5" }, "$13" },
6830 { { "t6" }, "$14" },
6831 { { "t7" }, "$15" },
6832 { { "s0" }, "$16" },
6833 { { "s1" }, "$17" },
6834 { { "s2" }, "$18" },
6835 { { "s3" }, "$19" },
6836 { { "s4" }, "$20" },
6837 { { "s5" }, "$21" },
6838 { { "s6" }, "$22" },
6839 { { "s7" }, "$23" },
6840 { { "t8" }, "$24" },
6841 { { "t9" }, "$25" },
6842 { { "k0" }, "$26" },
6843 { { "k1" }, "$27" },
6844 { { "gp" }, "$28" },
6845 { { "sp","$sp" }, "$29" },
6846 { { "fp","$fp" }, "$30" },
6849 return llvm::makeArrayRef(GCCRegAliases);
6853 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
6854 void setDataLayoutString() override {
6855 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6859 Mips32EBTargetInfo(const llvm::Triple &Triple)
6860 : Mips32TargetInfoBase(Triple) {
6862 void getTargetDefines(const LangOptions &Opts,
6863 MacroBuilder &Builder) const override {
6864 DefineStd(Builder, "MIPSEB", Opts);
6865 Builder.defineMacro("_MIPSEB");
6866 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6870 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
6871 void setDataLayoutString() override {
6872 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6876 Mips32ELTargetInfo(const llvm::Triple &Triple)
6877 : Mips32TargetInfoBase(Triple) {
6880 void getTargetDefines(const LangOptions &Opts,
6881 MacroBuilder &Builder) const override {
6882 DefineStd(Builder, "MIPSEL", Opts);
6883 Builder.defineMacro("_MIPSEL");
6884 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6888 class Mips64TargetInfoBase : public MipsTargetInfoBase {
6890 Mips64TargetInfoBase(const llvm::Triple &Triple)
6891 : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6892 LongDoubleWidth = LongDoubleAlign = 128;
6893 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6894 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6895 LongDoubleWidth = LongDoubleAlign = 64;
6896 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6899 SuitableAlign = 128;
6900 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6903 void setN64ABITypes() {
6904 LongWidth = LongAlign = 64;
6905 PointerWidth = PointerAlign = 64;
6906 SizeType = UnsignedLong;
6907 PtrDiffType = SignedLong;
6908 Int64Type = SignedLong;
6909 IntMaxType = Int64Type;
6912 void setN32ABITypes() {
6913 LongWidth = LongAlign = 32;
6914 PointerWidth = PointerAlign = 32;
6915 SizeType = UnsignedInt;
6916 PtrDiffType = SignedInt;
6917 Int64Type = SignedLongLong;
6918 IntMaxType = Int64Type;
6921 bool setABI(const std::string &Name) override {
6922 if (Name == "n32") {
6927 if (Name == "n64") {
6935 void getTargetDefines(const LangOptions &Opts,
6936 MacroBuilder &Builder) const override {
6937 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6939 Builder.defineMacro("__mips", "64");
6940 Builder.defineMacro("__mips64");
6941 Builder.defineMacro("__mips64__");
6942 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6944 const std::string& CPUStr = getCPU();
6945 if (CPUStr == "mips64")
6946 Builder.defineMacro("__mips_isa_rev", "1");
6947 else if (CPUStr == "mips64r2")
6948 Builder.defineMacro("__mips_isa_rev", "2");
6949 else if (CPUStr == "mips64r3")
6950 Builder.defineMacro("__mips_isa_rev", "3");
6951 else if (CPUStr == "mips64r5")
6952 Builder.defineMacro("__mips_isa_rev", "5");
6953 else if (CPUStr == "mips64r6")
6954 Builder.defineMacro("__mips_isa_rev", "6");
6957 Builder.defineMacro("__mips_n32");
6958 Builder.defineMacro("_ABIN32", "2");
6959 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6961 else if (ABI == "n64") {
6962 Builder.defineMacro("__mips_n64");
6963 Builder.defineMacro("_ABI64", "3");
6964 Builder.defineMacro("_MIPS_SIM", "_ABI64");
6967 llvm_unreachable("Invalid ABI for Mips64.");
6969 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
6971 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6972 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6982 { { "a6" }, "$10" },
6983 { { "a7" }, "$11" },
6984 { { "t0" }, "$12" },
6985 { { "t1" }, "$13" },
6986 { { "t2" }, "$14" },
6987 { { "t3" }, "$15" },
6988 { { "s0" }, "$16" },
6989 { { "s1" }, "$17" },
6990 { { "s2" }, "$18" },
6991 { { "s3" }, "$19" },
6992 { { "s4" }, "$20" },
6993 { { "s5" }, "$21" },
6994 { { "s6" }, "$22" },
6995 { { "s7" }, "$23" },
6996 { { "t8" }, "$24" },
6997 { { "t9" }, "$25" },
6998 { { "k0" }, "$26" },
6999 { { "k1" }, "$27" },
7000 { { "gp" }, "$28" },
7001 { { "sp","$sp" }, "$29" },
7002 { { "fp","$fp" }, "$30" },
7005 return llvm::makeArrayRef(GCCRegAliases);
7008 bool hasInt128Type() const override { return true; }
7011 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
7012 void setDataLayoutString() override {
7014 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7016 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7021 Mips64EBTargetInfo(const llvm::Triple &Triple)
7022 : Mips64TargetInfoBase(Triple) {}
7023 void getTargetDefines(const LangOptions &Opts,
7024 MacroBuilder &Builder) const override {
7025 DefineStd(Builder, "MIPSEB", Opts);
7026 Builder.defineMacro("_MIPSEB");
7027 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
7031 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
7032 void setDataLayoutString() override {
7034 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7036 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7039 Mips64ELTargetInfo(const llvm::Triple &Triple)
7040 : Mips64TargetInfoBase(Triple) {
7041 // Default ABI is n64.
7044 void getTargetDefines(const LangOptions &Opts,
7045 MacroBuilder &Builder) const override {
7046 DefineStd(Builder, "MIPSEL", Opts);
7047 Builder.defineMacro("_MIPSEL");
7048 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
7052 class PNaClTargetInfo : public TargetInfo {
7054 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
7056 this->UserLabelPrefix = "";
7057 this->LongAlign = 32;
7058 this->LongWidth = 32;
7059 this->PointerAlign = 32;
7060 this->PointerWidth = 32;
7061 this->IntMaxType = TargetInfo::SignedLongLong;
7062 this->Int64Type = TargetInfo::SignedLongLong;
7063 this->DoubleAlign = 64;
7064 this->LongDoubleWidth = 64;
7065 this->LongDoubleAlign = 64;
7066 this->SizeType = TargetInfo::UnsignedInt;
7067 this->PtrDiffType = TargetInfo::SignedInt;
7068 this->IntPtrType = TargetInfo::SignedInt;
7069 this->RegParmMax = 0; // Disallow regparm
7072 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
7073 Builder.defineMacro("__le32__");
7074 Builder.defineMacro("__pnacl__");
7076 void getTargetDefines(const LangOptions &Opts,
7077 MacroBuilder &Builder) const override {
7078 getArchDefines(Opts, Builder);
7080 bool hasFeature(StringRef Feature) const override {
7081 return Feature == "pnacl";
7083 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7084 BuiltinVaListKind getBuiltinVaListKind() const override {
7085 return TargetInfo::PNaClABIBuiltinVaList;
7087 ArrayRef<const char *> getGCCRegNames() const override;
7088 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
7089 bool validateAsmConstraint(const char *&Name,
7090 TargetInfo::ConstraintInfo &Info) const override {
7094 const char *getClobbers() const override {
7099 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const {
7103 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const {
7107 // We attempt to use PNaCl (le32) frontend and Mips32EL backend.
7108 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo {
7110 NaClMips32ELTargetInfo(const llvm::Triple &Triple) :
7111 Mips32ELTargetInfo(Triple) {
7114 BuiltinVaListKind getBuiltinVaListKind() const override {
7115 return TargetInfo::PNaClABIBuiltinVaList;
7119 class Le64TargetInfo : public TargetInfo {
7120 static const Builtin::Info BuiltinInfo[];
7123 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
7125 NoAsmVariants = true;
7126 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7127 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7128 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
7131 void getTargetDefines(const LangOptions &Opts,
7132 MacroBuilder &Builder) const override {
7133 DefineStd(Builder, "unix", Opts);
7134 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
7135 Builder.defineMacro("__ELF__");
7137 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7138 return llvm::makeArrayRef(BuiltinInfo,
7139 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin);
7141 BuiltinVaListKind getBuiltinVaListKind() const override {
7142 return TargetInfo::PNaClABIBuiltinVaList;
7144 const char *getClobbers() const override { return ""; }
7145 ArrayRef<const char *> getGCCRegNames() const override {
7148 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7151 bool validateAsmConstraint(const char *&Name,
7152 TargetInfo::ConstraintInfo &Info) const override {
7156 bool hasProtectedVisibility() const override { return false; }
7159 class WebAssemblyTargetInfo : public TargetInfo {
7160 static const Builtin::Info BuiltinInfo[];
7168 explicit WebAssemblyTargetInfo(const llvm::Triple &T)
7169 : TargetInfo(T), SIMDLevel(NoSIMD) {
7171 NoAsmVariants = true;
7172 SuitableAlign = 128;
7173 LargeArrayMinWidth = 128;
7174 LargeArrayAlign = 128;
7175 SimdDefaultAlign = 128;
7176 SigAtomicType = SignedLong;
7177 LongDoubleWidth = LongDoubleAlign = 128;
7178 LongDoubleFormat = &llvm::APFloat::IEEEquad;
7182 void getTargetDefines(const LangOptions &Opts,
7183 MacroBuilder &Builder) const override {
7184 defineCPUMacros(Builder, "wasm", /*Tuning=*/false);
7185 if (SIMDLevel >= SIMD128)
7186 Builder.defineMacro("__wasm_simd128__");
7191 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7193 const std::vector<std::string> &FeaturesVec) const override {
7194 if (CPU == "bleeding-edge")
7195 Features["simd128"] = true;
7196 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7198 bool hasFeature(StringRef Feature) const final {
7199 return llvm::StringSwitch<bool>(Feature)
7200 .Case("simd128", SIMDLevel >= SIMD128)
7203 bool handleTargetFeatures(std::vector<std::string> &Features,
7204 DiagnosticsEngine &Diags) final {
7205 for (const auto &Feature : Features) {
7206 if (Feature == "+simd128") {
7207 SIMDLevel = std::max(SIMDLevel, SIMD128);
7210 if (Feature == "-simd128") {
7211 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1));
7215 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature
7216 << "-target-feature";
7221 bool setCPU(const std::string &Name) final {
7222 return llvm::StringSwitch<bool>(Name)
7224 .Case("bleeding-edge", true)
7225 .Case("generic", true)
7228 ArrayRef<Builtin::Info> getTargetBuiltins() const final {
7229 return llvm::makeArrayRef(BuiltinInfo,
7230 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin);
7232 BuiltinVaListKind getBuiltinVaListKind() const final {
7233 return VoidPtrBuiltinVaList;
7235 ArrayRef<const char *> getGCCRegNames() const final {
7238 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final {
7242 validateAsmConstraint(const char *&Name,
7243 TargetInfo::ConstraintInfo &Info) const final {
7246 const char *getClobbers() const final { return ""; }
7247 bool isCLZForZeroUndef() const final { return false; }
7248 bool hasInt128Type() const final { return true; }
7249 IntType getIntTypeByWidth(unsigned BitWidth,
7250 bool IsSigned) const final {
7251 // WebAssembly prefers long long for explicitly 64-bit integers.
7252 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
7253 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
7255 IntType getLeastIntTypeByWidth(unsigned BitWidth,
7256 bool IsSigned) const final {
7257 // WebAssembly uses long long for int_least64_t and int_fast64_t.
7258 return BitWidth == 64
7259 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
7260 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
7264 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = {
7265 #define BUILTIN(ID, TYPE, ATTRS) \
7266 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7267 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
7268 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
7269 #include "clang/Basic/BuiltinsWebAssembly.def"
7272 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo {
7274 explicit WebAssembly32TargetInfo(const llvm::Triple &T)
7275 : WebAssemblyTargetInfo(T) {
7276 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
7277 DataLayoutString = "e-p:32:32-i64:64-n32:64-S128";
7281 void getTargetDefines(const LangOptions &Opts,
7282 MacroBuilder &Builder) const override {
7283 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
7284 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false);
7288 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo {
7290 explicit WebAssembly64TargetInfo(const llvm::Triple &T)
7291 : WebAssemblyTargetInfo(T) {
7292 LongAlign = LongWidth = 64;
7293 PointerAlign = PointerWidth = 64;
7294 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7295 DataLayoutString = "e-p:64:64-i64:64-n32:64-S128";
7299 void getTargetDefines(const LangOptions &Opts,
7300 MacroBuilder &Builder) const override {
7301 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
7302 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false);
7306 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
7307 #define BUILTIN(ID, TYPE, ATTRS) \
7308 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7309 #include "clang/Basic/BuiltinsLe64.def"
7312 static const unsigned SPIRAddrSpaceMap[] = {
7315 2, // opencl_constant
7316 4, // opencl_generic
7321 class SPIRTargetInfo : public TargetInfo {
7323 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
7324 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
7325 "SPIR target must use unknown OS");
7326 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
7327 "SPIR target must use unknown environment type");
7329 TLSSupported = false;
7330 LongWidth = LongAlign = 64;
7331 AddrSpaceMap = &SPIRAddrSpaceMap;
7332 UseAddrSpaceMapMangling = true;
7333 // Define available target features
7334 // These must be defined in sorted order!
7335 NoAsmVariants = true;
7337 void getTargetDefines(const LangOptions &Opts,
7338 MacroBuilder &Builder) const override {
7339 DefineStd(Builder, "SPIR", Opts);
7341 bool hasFeature(StringRef Feature) const override {
7342 return Feature == "spir";
7345 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7346 const char *getClobbers() const override { return ""; }
7347 ArrayRef<const char *> getGCCRegNames() const override { return None; }
7348 bool validateAsmConstraint(const char *&Name,
7349 TargetInfo::ConstraintInfo &info) const override {
7352 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7355 BuiltinVaListKind getBuiltinVaListKind() const override {
7356 return TargetInfo::VoidPtrBuiltinVaList;
7359 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
7360 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK
7364 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
7365 return CC_SpirFunction;
7369 class SPIR32TargetInfo : public SPIRTargetInfo {
7371 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
7372 PointerWidth = PointerAlign = 32;
7373 SizeType = TargetInfo::UnsignedInt;
7374 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
7375 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
7376 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
7378 void getTargetDefines(const LangOptions &Opts,
7379 MacroBuilder &Builder) const override {
7380 DefineStd(Builder, "SPIR32", Opts);
7384 class SPIR64TargetInfo : public SPIRTargetInfo {
7386 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
7387 PointerWidth = PointerAlign = 64;
7388 SizeType = TargetInfo::UnsignedLong;
7389 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
7390 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
7391 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
7393 void getTargetDefines(const LangOptions &Opts,
7394 MacroBuilder &Builder) const override {
7395 DefineStd(Builder, "SPIR64", Opts);
7399 class XCoreTargetInfo : public TargetInfo {
7400 static const Builtin::Info BuiltinInfo[];
7402 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
7404 NoAsmVariants = true;
7407 DoubleAlign = LongDoubleAlign = 32;
7408 SizeType = UnsignedInt;
7409 PtrDiffType = SignedInt;
7410 IntPtrType = SignedInt;
7411 WCharType = UnsignedChar;
7412 WIntType = UnsignedInt;
7413 UseZeroLengthBitfieldAlignment = true;
7414 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
7415 "-f64:32-a:0:32-n32";
7417 void getTargetDefines(const LangOptions &Opts,
7418 MacroBuilder &Builder) const override {
7419 Builder.defineMacro("__XS1B__");
7421 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7422 return llvm::makeArrayRef(BuiltinInfo,
7423 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin);
7425 BuiltinVaListKind getBuiltinVaListKind() const override {
7426 return TargetInfo::VoidPtrBuiltinVaList;
7428 const char *getClobbers() const override {
7431 ArrayRef<const char *> getGCCRegNames() const override {
7432 static const char * const GCCRegNames[] = {
7433 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7434 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
7436 return llvm::makeArrayRef(GCCRegNames);
7438 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7441 bool validateAsmConstraint(const char *&Name,
7442 TargetInfo::ConstraintInfo &Info) const override {
7445 int getEHDataRegisterNumber(unsigned RegNo) const override {
7446 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
7447 return (RegNo < 2)? RegNo : -1;
7451 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
7452 #define BUILTIN(ID, TYPE, ATTRS) \
7453 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7454 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
7455 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
7456 #include "clang/Basic/BuiltinsXCore.def"
7459 // x86_32 Android target
7460 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
7462 AndroidX86_32TargetInfo(const llvm::Triple &Triple)
7463 : LinuxTargetInfo<X86_32TargetInfo>(Triple) {
7465 LongDoubleWidth = 64;
7466 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
7470 // x86_64 Android target
7471 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
7473 AndroidX86_64TargetInfo(const llvm::Triple &Triple)
7474 : LinuxTargetInfo<X86_64TargetInfo>(Triple) {
7475 LongDoubleFormat = &llvm::APFloat::IEEEquad;
7478 bool useFloat128ManglingForLongDouble() const override {
7482 } // end anonymous namespace
7484 //===----------------------------------------------------------------------===//
7486 //===----------------------------------------------------------------------===//
7488 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
7489 llvm::Triple::OSType os = Triple.getOS();
7491 switch (Triple.getArch()) {
7495 case llvm::Triple::xcore:
7496 return new XCoreTargetInfo(Triple);
7498 case llvm::Triple::hexagon:
7499 return new HexagonTargetInfo(Triple);
7501 case llvm::Triple::aarch64:
7502 if (Triple.isOSDarwin())
7503 return new DarwinAArch64TargetInfo(Triple);
7506 case llvm::Triple::CloudABI:
7507 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple);
7508 case llvm::Triple::FreeBSD:
7509 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
7510 case llvm::Triple::Linux:
7511 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
7512 case llvm::Triple::NetBSD:
7513 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
7515 return new AArch64leTargetInfo(Triple);
7518 case llvm::Triple::aarch64_be:
7520 case llvm::Triple::FreeBSD:
7521 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
7522 case llvm::Triple::Linux:
7523 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
7524 case llvm::Triple::NetBSD:
7525 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
7527 return new AArch64beTargetInfo(Triple);
7530 case llvm::Triple::arm:
7531 case llvm::Triple::thumb:
7532 if (Triple.isOSBinFormatMachO())
7533 return new DarwinARMTargetInfo(Triple);
7536 case llvm::Triple::Linux:
7537 return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
7538 case llvm::Triple::FreeBSD:
7539 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
7540 case llvm::Triple::NetBSD:
7541 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
7542 case llvm::Triple::OpenBSD:
7543 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
7544 case llvm::Triple::Bitrig:
7545 return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
7546 case llvm::Triple::RTEMS:
7547 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
7548 case llvm::Triple::NaCl:
7549 return new NaClTargetInfo<ARMleTargetInfo>(Triple);
7550 case llvm::Triple::Win32:
7551 switch (Triple.getEnvironment()) {
7552 case llvm::Triple::Cygnus:
7553 return new CygwinARMTargetInfo(Triple);
7554 case llvm::Triple::GNU:
7555 return new MinGWARMTargetInfo(Triple);
7556 case llvm::Triple::Itanium:
7557 return new ItaniumWindowsARMleTargetInfo(Triple);
7558 case llvm::Triple::MSVC:
7559 default: // Assume MSVC for unknown environments
7560 return new MicrosoftARMleTargetInfo(Triple);
7563 return new ARMleTargetInfo(Triple);
7566 case llvm::Triple::armeb:
7567 case llvm::Triple::thumbeb:
7568 if (Triple.isOSDarwin())
7569 return new DarwinARMTargetInfo(Triple);
7572 case llvm::Triple::Linux:
7573 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
7574 case llvm::Triple::FreeBSD:
7575 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
7576 case llvm::Triple::NetBSD:
7577 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
7578 case llvm::Triple::OpenBSD:
7579 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
7580 case llvm::Triple::Bitrig:
7581 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
7582 case llvm::Triple::RTEMS:
7583 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
7584 case llvm::Triple::NaCl:
7585 return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
7587 return new ARMbeTargetInfo(Triple);
7590 case llvm::Triple::bpfeb:
7591 case llvm::Triple::bpfel:
7592 return new BPFTargetInfo(Triple);
7594 case llvm::Triple::msp430:
7595 return new MSP430TargetInfo(Triple);
7597 case llvm::Triple::mips:
7599 case llvm::Triple::Linux:
7600 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
7601 case llvm::Triple::RTEMS:
7602 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
7603 case llvm::Triple::FreeBSD:
7604 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
7605 case llvm::Triple::NetBSD:
7606 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
7608 return new Mips32EBTargetInfo(Triple);
7611 case llvm::Triple::mipsel:
7613 case llvm::Triple::Linux:
7614 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
7615 case llvm::Triple::RTEMS:
7616 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
7617 case llvm::Triple::FreeBSD:
7618 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
7619 case llvm::Triple::NetBSD:
7620 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
7621 case llvm::Triple::NaCl:
7622 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple);
7624 return new Mips32ELTargetInfo(Triple);
7627 case llvm::Triple::mips64:
7629 case llvm::Triple::Linux:
7630 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
7631 case llvm::Triple::RTEMS:
7632 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
7633 case llvm::Triple::FreeBSD:
7634 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7635 case llvm::Triple::NetBSD:
7636 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7637 case llvm::Triple::OpenBSD:
7638 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7640 return new Mips64EBTargetInfo(Triple);
7643 case llvm::Triple::mips64el:
7645 case llvm::Triple::Linux:
7646 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
7647 case llvm::Triple::RTEMS:
7648 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
7649 case llvm::Triple::FreeBSD:
7650 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7651 case llvm::Triple::NetBSD:
7652 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7653 case llvm::Triple::OpenBSD:
7654 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7656 return new Mips64ELTargetInfo(Triple);
7659 case llvm::Triple::le32:
7661 case llvm::Triple::NaCl:
7662 return new NaClTargetInfo<PNaClTargetInfo>(Triple);
7667 case llvm::Triple::le64:
7668 return new Le64TargetInfo(Triple);
7670 case llvm::Triple::ppc:
7671 if (Triple.isOSDarwin())
7672 return new DarwinPPC32TargetInfo(Triple);
7674 case llvm::Triple::Linux:
7675 return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
7676 case llvm::Triple::FreeBSD:
7677 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
7678 case llvm::Triple::NetBSD:
7679 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
7680 case llvm::Triple::OpenBSD:
7681 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
7682 case llvm::Triple::RTEMS:
7683 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
7685 return new PPC32TargetInfo(Triple);
7688 case llvm::Triple::ppc64:
7689 if (Triple.isOSDarwin())
7690 return new DarwinPPC64TargetInfo(Triple);
7692 case llvm::Triple::Linux:
7693 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7694 case llvm::Triple::Lv2:
7695 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
7696 case llvm::Triple::FreeBSD:
7697 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
7698 case llvm::Triple::NetBSD:
7699 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7701 return new PPC64TargetInfo(Triple);
7704 case llvm::Triple::ppc64le:
7706 case llvm::Triple::Linux:
7707 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7708 case llvm::Triple::NetBSD:
7709 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7711 return new PPC64TargetInfo(Triple);
7714 case llvm::Triple::nvptx:
7715 return new NVPTX32TargetInfo(Triple);
7716 case llvm::Triple::nvptx64:
7717 return new NVPTX64TargetInfo(Triple);
7719 case llvm::Triple::amdgcn:
7720 case llvm::Triple::r600:
7721 return new AMDGPUTargetInfo(Triple);
7723 case llvm::Triple::sparc:
7725 case llvm::Triple::Linux:
7726 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
7727 case llvm::Triple::Solaris:
7728 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple);
7729 case llvm::Triple::NetBSD:
7730 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
7731 case llvm::Triple::OpenBSD:
7732 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
7733 case llvm::Triple::RTEMS:
7734 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
7736 return new SparcV8TargetInfo(Triple);
7739 // The 'sparcel' architecture copies all the above cases except for Solaris.
7740 case llvm::Triple::sparcel:
7742 case llvm::Triple::Linux:
7743 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple);
7744 case llvm::Triple::NetBSD:
7745 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7746 case llvm::Triple::OpenBSD:
7747 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7748 case llvm::Triple::RTEMS:
7749 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple);
7751 return new SparcV8elTargetInfo(Triple);
7754 case llvm::Triple::sparcv9:
7756 case llvm::Triple::Linux:
7757 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
7758 case llvm::Triple::Solaris:
7759 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
7760 case llvm::Triple::NetBSD:
7761 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
7762 case llvm::Triple::OpenBSD:
7763 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
7764 case llvm::Triple::FreeBSD:
7765 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
7767 return new SparcV9TargetInfo(Triple);
7770 case llvm::Triple::systemz:
7772 case llvm::Triple::Linux:
7773 return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
7775 return new SystemZTargetInfo(Triple);
7778 case llvm::Triple::tce:
7779 return new TCETargetInfo(Triple);
7781 case llvm::Triple::x86:
7782 if (Triple.isOSDarwin())
7783 return new DarwinI386TargetInfo(Triple);
7786 case llvm::Triple::CloudABI:
7787 return new CloudABITargetInfo<X86_32TargetInfo>(Triple);
7788 case llvm::Triple::Linux: {
7789 switch (Triple.getEnvironment()) {
7791 return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
7792 case llvm::Triple::Android:
7793 return new AndroidX86_32TargetInfo(Triple);
7796 case llvm::Triple::DragonFly:
7797 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
7798 case llvm::Triple::NetBSD:
7799 return new NetBSDI386TargetInfo(Triple);
7800 case llvm::Triple::OpenBSD:
7801 return new OpenBSDI386TargetInfo(Triple);
7802 case llvm::Triple::Bitrig:
7803 return new BitrigI386TargetInfo(Triple);
7804 case llvm::Triple::FreeBSD:
7805 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7806 case llvm::Triple::KFreeBSD:
7807 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7808 case llvm::Triple::Minix:
7809 return new MinixTargetInfo<X86_32TargetInfo>(Triple);
7810 case llvm::Triple::Solaris:
7811 return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
7812 case llvm::Triple::Win32: {
7813 switch (Triple.getEnvironment()) {
7814 case llvm::Triple::Cygnus:
7815 return new CygwinX86_32TargetInfo(Triple);
7816 case llvm::Triple::GNU:
7817 return new MinGWX86_32TargetInfo(Triple);
7818 case llvm::Triple::Itanium:
7819 case llvm::Triple::MSVC:
7820 default: // Assume MSVC for unknown environments
7821 return new MicrosoftX86_32TargetInfo(Triple);
7824 case llvm::Triple::Haiku:
7825 return new HaikuX86_32TargetInfo(Triple);
7826 case llvm::Triple::RTEMS:
7827 return new RTEMSX86_32TargetInfo(Triple);
7828 case llvm::Triple::NaCl:
7829 return new NaClTargetInfo<X86_32TargetInfo>(Triple);
7830 case llvm::Triple::ELFIAMCU:
7831 return new MCUX86_32TargetInfo(Triple);
7833 return new X86_32TargetInfo(Triple);
7836 case llvm::Triple::x86_64:
7837 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
7838 return new DarwinX86_64TargetInfo(Triple);
7841 case llvm::Triple::CloudABI:
7842 return new CloudABITargetInfo<X86_64TargetInfo>(Triple);
7843 case llvm::Triple::Linux: {
7844 switch (Triple.getEnvironment()) {
7846 return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
7847 case llvm::Triple::Android:
7848 return new AndroidX86_64TargetInfo(Triple);
7851 case llvm::Triple::DragonFly:
7852 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
7853 case llvm::Triple::NetBSD:
7854 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
7855 case llvm::Triple::OpenBSD:
7856 return new OpenBSDX86_64TargetInfo(Triple);
7857 case llvm::Triple::Bitrig:
7858 return new BitrigX86_64TargetInfo(Triple);
7859 case llvm::Triple::FreeBSD:
7860 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7861 case llvm::Triple::KFreeBSD:
7862 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7863 case llvm::Triple::Solaris:
7864 return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
7865 case llvm::Triple::Win32: {
7866 switch (Triple.getEnvironment()) {
7867 case llvm::Triple::Cygnus:
7868 return new CygwinX86_64TargetInfo(Triple);
7869 case llvm::Triple::GNU:
7870 return new MinGWX86_64TargetInfo(Triple);
7871 case llvm::Triple::MSVC:
7872 default: // Assume MSVC for unknown environments
7873 return new MicrosoftX86_64TargetInfo(Triple);
7876 case llvm::Triple::NaCl:
7877 return new NaClTargetInfo<X86_64TargetInfo>(Triple);
7878 case llvm::Triple::PS4:
7879 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple);
7881 return new X86_64TargetInfo(Triple);
7884 case llvm::Triple::spir: {
7885 if (Triple.getOS() != llvm::Triple::UnknownOS ||
7886 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7888 return new SPIR32TargetInfo(Triple);
7890 case llvm::Triple::spir64: {
7891 if (Triple.getOS() != llvm::Triple::UnknownOS ||
7892 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7894 return new SPIR64TargetInfo(Triple);
7896 case llvm::Triple::wasm32:
7897 if (!(Triple == llvm::Triple("wasm32-unknown-unknown")))
7899 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple);
7900 case llvm::Triple::wasm64:
7901 if (!(Triple == llvm::Triple("wasm64-unknown-unknown")))
7903 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple);
7907 /// CreateTargetInfo - Return the target info object for the specified target
7910 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
7911 const std::shared_ptr<TargetOptions> &Opts) {
7912 llvm::Triple Triple(Opts->Triple);
7914 // Construct the target
7915 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
7917 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
7920 Target->TargetOpts = Opts;
7922 // Set the target CPU if specified.
7923 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
7924 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
7928 // Set the target ABI if specified.
7929 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
7930 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
7934 // Set the fp math unit.
7935 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
7936 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
7940 // Compute the default target features, we need the target to handle this
7941 // because features may have dependencies on one another.
7942 llvm::StringMap<bool> Features;
7943 if (!Target->initFeatureMap(Features, Diags, Opts->CPU,
7944 Opts->FeaturesAsWritten))
7947 // Add the features to the compile options.
7948 Opts->Features.clear();
7949 for (const auto &F : Features)
7950 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str());
7952 if (!Target->handleTargetFeatures(Opts->Features, Diags))
7955 return Target.release();