1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
33 using namespace clang;
35 //===----------------------------------------------------------------------===//
36 // Common code shared among targets.
37 //===----------------------------------------------------------------------===//
39 /// DefineStd - Define a macro name and standard variants. For example if
40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
43 const LangOptions &Opts) {
44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
47 // in the user's namespace.
49 Builder.defineMacro(MacroName);
52 Builder.defineMacro("__" + MacroName);
55 Builder.defineMacro("__" + MacroName + "__");
58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
60 Builder.defineMacro("__" + CPUName);
61 Builder.defineMacro("__" + CPUName + "__");
63 Builder.defineMacro("__tune_" + CPUName + "__");
66 //===----------------------------------------------------------------------===//
67 // Defines specific to certain operating systems.
68 //===----------------------------------------------------------------------===//
71 template<typename TgtInfo>
72 class OSTargetInfo : public TgtInfo {
74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
75 MacroBuilder &Builder) const=0;
77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
78 void getTargetDefines(const LangOptions &Opts,
79 MacroBuilder &Builder) const override {
80 TgtInfo::getTargetDefines(Opts, Builder);
81 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
85 } // end anonymous namespace
88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
89 const llvm::Triple &Triple,
90 StringRef &PlatformName,
91 VersionTuple &PlatformMinVersion) {
92 Builder.defineMacro("__APPLE_CC__", "6000");
93 Builder.defineMacro("__APPLE__");
94 Builder.defineMacro("OBJC_NEW_PROPERTIES");
95 // AddressSanitizer doesn't play well with source fortification, which is on
96 // by default on Darwin.
97 if (Opts.Sanitize.has(SanitizerKind::Address))
98 Builder.defineMacro("_FORTIFY_SOURCE", "0");
100 if (!Opts.ObjCAutoRefCount) {
101 // __weak is always defined, for use in blocks and with objc pointers.
102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
104 // Darwin defines __strong even in C mode (just to nothing).
105 if (Opts.getGC() != LangOptions::NonGC)
106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
108 Builder.defineMacro("__strong", "");
110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even
111 // allow this in C, since one might have block pointers in structs that
112 // are used in pure C code and in Objective-C ARC.
113 Builder.defineMacro("__unsafe_unretained", "");
117 Builder.defineMacro("__STATIC__");
119 Builder.defineMacro("__DYNAMIC__");
121 if (Opts.POSIXThreads)
122 Builder.defineMacro("_REENTRANT");
124 // Get the platform type and version number from the triple.
125 unsigned Maj, Min, Rev;
126 if (Triple.isMacOSX()) {
127 Triple.getMacOSXVersion(Maj, Min, Rev);
128 PlatformName = "macosx";
130 Triple.getOSVersion(Maj, Min, Rev);
131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
134 // If -target arch-pc-win32-macho option specified, we're
135 // generating code for Win32 ABI. No need to emit
136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
137 if (PlatformName == "win32") {
138 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
142 // Set the appropriate OS version define.
143 if (Triple.isiOS()) {
144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
147 Str[1] = '0' + (Min / 10);
148 Str[2] = '0' + (Min % 10);
149 Str[3] = '0' + (Rev / 10);
150 Str[4] = '0' + (Rev % 10);
152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
154 } else if (Triple.isMacOSX()) {
155 // Note that the Driver allows versions which aren't representable in the
156 // define (because we only get a single digit for the minor and micro
157 // revision numbers). So, we limit them to the maximum representable
159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
161 if (Maj < 10 || (Maj == 10 && Min < 10)) {
162 Str[0] = '0' + (Maj / 10);
163 Str[1] = '0' + (Maj % 10);
164 Str[2] = '0' + std::min(Min, 9U);
165 Str[3] = '0' + std::min(Rev, 9U);
168 // Handle versions > 10.9.
169 Str[0] = '0' + (Maj / 10);
170 Str[1] = '0' + (Maj % 10);
171 Str[2] = '0' + (Min / 10);
172 Str[3] = '0' + (Min % 10);
173 Str[4] = '0' + (Rev / 10);
174 Str[5] = '0' + (Rev % 10);
177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
180 // Tell users about the kernel if there is one.
181 if (Triple.isOSDarwin())
182 Builder.defineMacro("__MACH__");
184 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
188 template<typename Target>
189 class DarwinTargetInfo : public OSTargetInfo<Target> {
191 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
192 MacroBuilder &Builder) const override {
193 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
194 this->PlatformMinVersion);
198 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
199 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
200 this->MCountName = "\01mcount";
203 std::string isValidSectionSpecifier(StringRef SR) const override {
204 // Let MCSectionMachO validate this.
205 StringRef Segment, Section;
206 unsigned TAA, StubSize;
208 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
209 TAA, HasTAA, StubSize);
212 const char *getStaticInitSectionSpecifier() const override {
213 // FIXME: We should return 0 when building kexts.
214 return "__TEXT,__StaticInit,regular,pure_instructions";
217 /// Darwin does not support protected visibility. Darwin's "default"
218 /// is very similar to ELF's "protected"; Darwin requires a "weak"
219 /// attribute on declarations that can be dynamically replaced.
220 bool hasProtectedVisibility() const override {
226 // DragonFlyBSD Target
227 template<typename Target>
228 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
230 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
231 MacroBuilder &Builder) const override {
232 // DragonFly defines; list based off of gcc output
233 Builder.defineMacro("__DragonFly__");
234 Builder.defineMacro("__DragonFly_cc_version", "100001");
235 Builder.defineMacro("__ELF__");
236 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
237 Builder.defineMacro("__tune_i386__");
238 DefineStd(Builder, "unix", Opts);
241 DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
242 : OSTargetInfo<Target>(Triple) {
243 this->UserLabelPrefix = "";
245 switch (Triple.getArch()) {
247 case llvm::Triple::x86:
248 case llvm::Triple::x86_64:
249 this->MCountName = ".mcount";
256 template<typename Target>
257 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
259 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
260 MacroBuilder &Builder) const override {
261 // FreeBSD defines; list based off of gcc output
263 unsigned Release = Triple.getOSMajorVersion();
267 Builder.defineMacro("__FreeBSD__", Twine(Release));
268 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
269 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
270 DefineStd(Builder, "unix", Opts);
271 Builder.defineMacro("__ELF__");
273 // On FreeBSD, wchar_t contains the number of the code point as
274 // used by the character set of the locale. These character sets are
275 // not necessarily a superset of ASCII.
277 // FIXME: This is wrong; the macro refers to the numerical values
278 // of wchar_t *literals*, which are not locale-dependent. However,
279 // FreeBSD systems apparently depend on us getting this wrong, and
280 // setting this to 1 is conforming even if all the basic source
281 // character literals have the same encoding as char and wchar_t.
282 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
285 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
286 this->UserLabelPrefix = "";
288 switch (Triple.getArch()) {
290 case llvm::Triple::x86:
291 case llvm::Triple::x86_64:
292 this->MCountName = ".mcount";
294 case llvm::Triple::mips:
295 case llvm::Triple::mipsel:
296 case llvm::Triple::ppc:
297 case llvm::Triple::ppc64:
298 case llvm::Triple::ppc64le:
299 this->MCountName = "_mcount";
301 case llvm::Triple::arm:
302 this->MCountName = "__mcount";
308 // GNU/kFreeBSD Target
309 template<typename Target>
310 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
312 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
313 MacroBuilder &Builder) const override {
314 // GNU/kFreeBSD defines; list based off of gcc output
316 DefineStd(Builder, "unix", Opts);
317 Builder.defineMacro("__FreeBSD_kernel__");
318 Builder.defineMacro("__GLIBC__");
319 Builder.defineMacro("__ELF__");
320 if (Opts.POSIXThreads)
321 Builder.defineMacro("_REENTRANT");
323 Builder.defineMacro("_GNU_SOURCE");
326 KFreeBSDTargetInfo(const llvm::Triple &Triple)
327 : OSTargetInfo<Target>(Triple) {
328 this->UserLabelPrefix = "";
333 template<typename Target>
334 class MinixTargetInfo : public OSTargetInfo<Target> {
336 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
337 MacroBuilder &Builder) const override {
340 Builder.defineMacro("__minix", "3");
341 Builder.defineMacro("_EM_WSIZE", "4");
342 Builder.defineMacro("_EM_PSIZE", "4");
343 Builder.defineMacro("_EM_SSIZE", "2");
344 Builder.defineMacro("_EM_LSIZE", "4");
345 Builder.defineMacro("_EM_FSIZE", "4");
346 Builder.defineMacro("_EM_DSIZE", "8");
347 Builder.defineMacro("__ELF__");
348 DefineStd(Builder, "unix", Opts);
351 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
352 this->UserLabelPrefix = "";
357 template<typename Target>
358 class LinuxTargetInfo : public OSTargetInfo<Target> {
360 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
361 MacroBuilder &Builder) const override {
362 // Linux defines; list based off of gcc output
363 DefineStd(Builder, "unix", Opts);
364 DefineStd(Builder, "linux", Opts);
365 Builder.defineMacro("__gnu_linux__");
366 Builder.defineMacro("__ELF__");
367 if (Triple.getEnvironment() == llvm::Triple::Android)
368 Builder.defineMacro("__ANDROID__", "1");
369 if (Opts.POSIXThreads)
370 Builder.defineMacro("_REENTRANT");
372 Builder.defineMacro("_GNU_SOURCE");
375 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
376 this->UserLabelPrefix = "";
377 this->WIntType = TargetInfo::UnsignedInt;
379 switch (Triple.getArch()) {
382 case llvm::Triple::ppc:
383 case llvm::Triple::ppc64:
384 case llvm::Triple::ppc64le:
385 this->MCountName = "_mcount";
390 const char *getStaticInitSectionSpecifier() const override {
391 return ".text.startup";
396 template<typename Target>
397 class NetBSDTargetInfo : public OSTargetInfo<Target> {
399 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
400 MacroBuilder &Builder) const override {
401 // NetBSD defines; list based off of gcc output
402 Builder.defineMacro("__NetBSD__");
403 Builder.defineMacro("__unix__");
404 Builder.defineMacro("__ELF__");
405 if (Opts.POSIXThreads)
406 Builder.defineMacro("_POSIX_THREADS");
408 switch (Triple.getArch()) {
411 case llvm::Triple::arm:
412 case llvm::Triple::armeb:
413 case llvm::Triple::thumb:
414 case llvm::Triple::thumbeb:
415 Builder.defineMacro("__ARM_DWARF_EH__");
420 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
421 this->UserLabelPrefix = "";
422 this->MCountName = "_mcount";
427 template<typename Target>
428 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
430 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
431 MacroBuilder &Builder) const override {
432 // OpenBSD defines; list based off of gcc output
434 Builder.defineMacro("__OpenBSD__");
435 DefineStd(Builder, "unix", Opts);
436 Builder.defineMacro("__ELF__");
437 if (Opts.POSIXThreads)
438 Builder.defineMacro("_REENTRANT");
441 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
442 this->UserLabelPrefix = "";
443 this->TLSSupported = false;
445 switch (Triple.getArch()) {
447 case llvm::Triple::x86:
448 case llvm::Triple::x86_64:
449 case llvm::Triple::arm:
450 case llvm::Triple::sparc:
451 this->MCountName = "__mcount";
453 case llvm::Triple::mips64:
454 case llvm::Triple::mips64el:
455 case llvm::Triple::ppc:
456 case llvm::Triple::sparcv9:
457 this->MCountName = "_mcount";
464 template<typename Target>
465 class BitrigTargetInfo : public OSTargetInfo<Target> {
467 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
468 MacroBuilder &Builder) const override {
469 // Bitrig defines; list based off of gcc output
471 Builder.defineMacro("__Bitrig__");
472 DefineStd(Builder, "unix", Opts);
473 Builder.defineMacro("__ELF__");
474 if (Opts.POSIXThreads)
475 Builder.defineMacro("_REENTRANT");
478 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
479 this->UserLabelPrefix = "";
480 this->MCountName = "__mcount";
485 template<typename Target>
486 class PSPTargetInfo : public OSTargetInfo<Target> {
488 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
489 MacroBuilder &Builder) const override {
490 // PSP defines; list based on the output of the pspdev gcc toolchain.
491 Builder.defineMacro("PSP");
492 Builder.defineMacro("_PSP");
493 Builder.defineMacro("__psp__");
494 Builder.defineMacro("__ELF__");
497 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
498 this->UserLabelPrefix = "";
503 template<typename Target>
504 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
506 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
507 MacroBuilder &Builder) const override {
509 Builder.defineMacro("__PPC__");
510 Builder.defineMacro("__PPU__");
511 Builder.defineMacro("__CELLOS_LV2__");
512 Builder.defineMacro("__ELF__");
513 Builder.defineMacro("__LP32__");
514 Builder.defineMacro("_ARCH_PPC64");
515 Builder.defineMacro("__powerpc64__");
518 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
519 this->UserLabelPrefix = "";
520 this->LongWidth = this->LongAlign = 32;
521 this->PointerWidth = this->PointerAlign = 32;
522 this->IntMaxType = TargetInfo::SignedLongLong;
523 this->Int64Type = TargetInfo::SignedLongLong;
524 this->SizeType = TargetInfo::UnsignedInt;
525 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
530 template<typename Target>
531 class SolarisTargetInfo : public OSTargetInfo<Target> {
533 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
534 MacroBuilder &Builder) const override {
535 DefineStd(Builder, "sun", Opts);
536 DefineStd(Builder, "unix", Opts);
537 Builder.defineMacro("__ELF__");
538 Builder.defineMacro("__svr4__");
539 Builder.defineMacro("__SVR4");
540 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
541 // newer, but to 500 for everything else. feature_test.h has a check to
542 // ensure that you are not using C99 with an old version of X/Open or C89
543 // with a new version.
545 Builder.defineMacro("_XOPEN_SOURCE", "600");
547 Builder.defineMacro("_XOPEN_SOURCE", "500");
549 Builder.defineMacro("__C99FEATURES__");
550 Builder.defineMacro("_LARGEFILE_SOURCE");
551 Builder.defineMacro("_LARGEFILE64_SOURCE");
552 Builder.defineMacro("__EXTENSIONS__");
553 Builder.defineMacro("_REENTRANT");
556 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
557 this->UserLabelPrefix = "";
558 this->WCharType = this->SignedInt;
559 // FIXME: WIntType should be SignedLong
564 template<typename Target>
565 class WindowsTargetInfo : public OSTargetInfo<Target> {
567 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
568 MacroBuilder &Builder) const override {
569 Builder.defineMacro("_WIN32");
571 void getVisualStudioDefines(const LangOptions &Opts,
572 MacroBuilder &Builder) const {
573 if (Opts.CPlusPlus) {
575 Builder.defineMacro("_CPPRTTI");
578 Builder.defineMacro("_CPPUNWIND");
581 if (!Opts.CharIsSigned)
582 Builder.defineMacro("_CHAR_UNSIGNED");
584 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
585 // but it works for now.
586 if (Opts.POSIXThreads)
587 Builder.defineMacro("_MT");
589 if (Opts.MSCompatibilityVersion) {
590 Builder.defineMacro("_MSC_VER",
591 Twine(Opts.MSCompatibilityVersion / 100000));
592 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
593 // FIXME We cannot encode the revision information into 32-bits
594 Builder.defineMacro("_MSC_BUILD", Twine(1));
597 if (Opts.MicrosoftExt) {
598 Builder.defineMacro("_MSC_EXTENSIONS");
600 if (Opts.CPlusPlus11) {
601 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
602 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
603 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
607 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
611 WindowsTargetInfo(const llvm::Triple &Triple)
612 : OSTargetInfo<Target>(Triple) {}
615 template <typename Target>
616 class NaClTargetInfo : public OSTargetInfo<Target> {
618 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
619 MacroBuilder &Builder) const override {
620 if (Opts.POSIXThreads)
621 Builder.defineMacro("_REENTRANT");
623 Builder.defineMacro("_GNU_SOURCE");
625 DefineStd(Builder, "unix", Opts);
626 Builder.defineMacro("__ELF__");
627 Builder.defineMacro("__native_client__");
631 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
632 this->UserLabelPrefix = "";
633 this->LongAlign = 32;
634 this->LongWidth = 32;
635 this->PointerAlign = 32;
636 this->PointerWidth = 32;
637 this->IntMaxType = TargetInfo::SignedLongLong;
638 this->Int64Type = TargetInfo::SignedLongLong;
639 this->DoubleAlign = 64;
640 this->LongDoubleWidth = 64;
641 this->LongDoubleAlign = 64;
642 this->LongLongWidth = 64;
643 this->LongLongAlign = 64;
644 this->SizeType = TargetInfo::UnsignedInt;
645 this->PtrDiffType = TargetInfo::SignedInt;
646 this->IntPtrType = TargetInfo::SignedInt;
647 // RegParmMax is inherited from the underlying architecture
648 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
649 if (Triple.getArch() == llvm::Triple::arm) {
650 this->DescriptionString =
651 "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
652 } else if (Triple.getArch() == llvm::Triple::x86) {
653 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
654 } else if (Triple.getArch() == llvm::Triple::x86_64) {
655 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
656 } else if (Triple.getArch() == llvm::Triple::mipsel) {
657 // Handled on mips' setDescriptionString.
659 assert(Triple.getArch() == llvm::Triple::le32);
660 this->DescriptionString = "e-p:32:32-i64:64";
663 typename Target::CallingConvCheckResult checkCallingConvention(
664 CallingConv CC) const override {
665 return CC == CC_PnaclCall ? Target::CCCR_OK :
666 Target::checkCallingConvention(CC);
669 } // end anonymous namespace.
671 //===----------------------------------------------------------------------===//
672 // Specific target implementations.
673 //===----------------------------------------------------------------------===//
676 // PPC abstract base class
677 class PPCTargetInfo : public TargetInfo {
678 static const Builtin::Info BuiltinInfo[];
679 static const char * const GCCRegNames[];
680 static const TargetInfo::GCCRegAlias GCCRegAliases[];
683 // Target cpu features.
691 PPCTargetInfo(const llvm::Triple &Triple)
692 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false) {
693 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
694 LongDoubleWidth = LongDoubleAlign = 128;
695 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
698 /// \brief Flags for architecture specific defines.
701 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
702 ArchDefinePpcgr = 1 << 1,
703 ArchDefinePpcsq = 1 << 2,
704 ArchDefine440 = 1 << 3,
705 ArchDefine603 = 1 << 4,
706 ArchDefine604 = 1 << 5,
707 ArchDefinePwr4 = 1 << 6,
708 ArchDefinePwr5 = 1 << 7,
709 ArchDefinePwr5x = 1 << 8,
710 ArchDefinePwr6 = 1 << 9,
711 ArchDefinePwr6x = 1 << 10,
712 ArchDefinePwr7 = 1 << 11,
713 ArchDefinePwr8 = 1 << 12,
714 ArchDefineA2 = 1 << 13,
715 ArchDefineA2q = 1 << 14
718 // Note: GCC recognizes the following additional cpus:
719 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
720 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
722 bool setCPU(const std::string &Name) override {
723 bool CPUKnown = llvm::StringSwitch<bool>(Name)
724 .Case("generic", true)
746 .Case("e500mc", true)
748 .Case("power3", true)
750 .Case("power4", true)
752 .Case("power5", true)
754 .Case("power5x", true)
756 .Case("power6", true)
758 .Case("power6x", true)
760 .Case("power7", true)
762 .Case("power8", true)
764 .Case("powerpc", true)
766 .Case("powerpc64", true)
768 .Case("powerpc64le", true)
769 .Case("ppc64le", true)
779 StringRef getABI() const override { return ABI; }
781 void getTargetBuiltins(const Builtin::Info *&Records,
782 unsigned &NumRecords) const override {
783 Records = BuiltinInfo;
784 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
787 bool isCLZForZeroUndef() const override { return false; }
789 void getTargetDefines(const LangOptions &Opts,
790 MacroBuilder &Builder) const override;
792 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
794 bool handleTargetFeatures(std::vector<std::string> &Features,
795 DiagnosticsEngine &Diags) override;
796 bool hasFeature(StringRef Feature) const override;
798 void getGCCRegNames(const char * const *&Names,
799 unsigned &NumNames) const override;
800 void getGCCRegAliases(const GCCRegAlias *&Aliases,
801 unsigned &NumAliases) const override;
802 bool validateAsmConstraint(const char *&Name,
803 TargetInfo::ConstraintInfo &Info) const override {
805 default: return false;
808 case 'b': // Base register
809 case 'f': // Floating point register
810 Info.setAllowsRegister();
812 // FIXME: The following are added to allow parsing.
813 // I just took a guess at what the actions should be.
814 // Also, is more specific checking needed? I.e. specific registers?
815 case 'd': // Floating point register (containing 64-bit value)
816 case 'v': // Altivec vector register
817 Info.setAllowsRegister();
821 case 'd':// VSX vector register to hold vector double data
822 case 'f':// VSX vector register to hold vector float data
823 case 's':// VSX vector register to hold scalar float data
824 case 'a':// Any VSX register
825 case 'c':// An individual CR bit
830 Info.setAllowsRegister();
831 Name++; // Skip over 'w'.
833 case 'h': // `MQ', `CTR', or `LINK' register
834 case 'q': // `MQ' register
835 case 'c': // `CTR' register
836 case 'l': // `LINK' register
837 case 'x': // `CR' register (condition register) number 0
838 case 'y': // `CR' register (condition register)
839 case 'z': // `XER[CA]' carry bit (part of the XER register)
840 Info.setAllowsRegister();
842 case 'I': // Signed 16-bit constant
843 case 'J': // Unsigned 16-bit constant shifted left 16 bits
844 // (use `L' instead for SImode constants)
845 case 'K': // Unsigned 16-bit constant
846 case 'L': // Signed 16-bit constant shifted left 16 bits
847 case 'M': // Constant larger than 31
848 case 'N': // Exact power of 2
849 case 'P': // Constant whose negation is a signed 16-bit constant
850 case 'G': // Floating point constant that can be loaded into a
851 // register with one instruction per word
852 case 'H': // Integer/Floating point constant that can be loaded
853 // into a register using three instructions
855 case 'm': // Memory operand. Note that on PowerPC targets, m can
856 // include addresses that update the base register. It
857 // is therefore only safe to use `m' in an asm statement
858 // if that asm statement accesses the operand exactly once.
859 // The asm statement must also use `%U<opno>' as a
860 // placeholder for the "update" flag in the corresponding
861 // load or store instruction. For example:
862 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
864 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
865 // is not. Use es rather than m if you don't want the base
866 // register to be updated.
870 // es: A "stable" memory operand; that is, one which does not
871 // include any automodification of the base register. Unlike
872 // `m', this constraint can be used in asm statements that
873 // might access the operand several times, or that might not
875 Info.setAllowsMemory();
876 Name++; // Skip over 'e'.
878 case 'Q': // Memory operand that is an offset from a register (it is
879 // usually better to use `m' or `es' in asm statements)
880 case 'Z': // Memory operand that is an indexed or indirect from a
881 // register (it is usually better to use `m' or `es' in
883 Info.setAllowsMemory();
884 Info.setAllowsRegister();
886 case 'R': // AIX TOC entry
887 case 'a': // Address operand that is an indexed or indirect from a
888 // register (`p' is preferable for asm statements)
889 case 'S': // Constant suitable as a 64-bit mask operand
890 case 'T': // Constant suitable as a 32-bit mask operand
891 case 'U': // System V Release 4 small data area reference
892 case 't': // AND masks that can be performed by two rldic{l, r}
894 case 'W': // Vector constant that does not require memory
895 case 'j': // Vector constant that is all zeros.
901 std::string convertConstraint(const char *&Constraint) const override {
903 switch (*Constraint) {
906 // Two-character constraint; add "^" hint for later parsing.
907 R = std::string("^") + std::string(Constraint, 2);
911 return TargetInfo::convertConstraint(Constraint);
915 const char *getClobbers() const override {
918 int getEHDataRegisterNumber(unsigned RegNo) const override {
919 if (RegNo == 0) return 3;
920 if (RegNo == 1) return 4;
924 bool hasSjLjLowering() const override {
929 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
930 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
931 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
933 #include "clang/Basic/BuiltinsPPC.def"
936 /// handleTargetFeatures - Perform initialization based on the user
937 /// configured set of features.
938 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
939 DiagnosticsEngine &Diags) {
940 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
941 // Ignore disabled features.
942 if (Features[i][0] == '-')
945 StringRef Feature = StringRef(Features[i]).substr(1);
947 if (Feature == "vsx") {
952 if (Feature == "power8-vector") {
957 // TODO: Finish this list and add an assert that we've handled them
964 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
965 /// #defines that are not tied to a specific subtarget.
966 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
967 MacroBuilder &Builder) const {
968 // Target identification.
969 Builder.defineMacro("__ppc__");
970 Builder.defineMacro("__PPC__");
971 Builder.defineMacro("_ARCH_PPC");
972 Builder.defineMacro("__powerpc__");
973 Builder.defineMacro("__POWERPC__");
974 if (PointerWidth == 64) {
975 Builder.defineMacro("_ARCH_PPC64");
976 Builder.defineMacro("__powerpc64__");
977 Builder.defineMacro("__ppc64__");
978 Builder.defineMacro("__PPC64__");
981 // Target properties.
982 if (getTriple().getArch() == llvm::Triple::ppc64le) {
983 Builder.defineMacro("_LITTLE_ENDIAN");
985 if (getTriple().getOS() != llvm::Triple::NetBSD &&
986 getTriple().getOS() != llvm::Triple::OpenBSD)
987 Builder.defineMacro("_BIG_ENDIAN");
992 Builder.defineMacro("_CALL_ELF", "1");
994 Builder.defineMacro("_CALL_ELF", "2");
996 // Subtarget options.
997 Builder.defineMacro("__NATURAL_ALIGNMENT__");
998 Builder.defineMacro("__REGISTER_PREFIX__", "");
1000 // FIXME: Should be controlled by command line option.
1001 if (LongDoubleWidth == 128)
1002 Builder.defineMacro("__LONG_DOUBLE_128__");
1005 Builder.defineMacro("__VEC__", "10206");
1006 Builder.defineMacro("__ALTIVEC__");
1009 // CPU identification.
1010 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1011 .Case("440", ArchDefineName)
1012 .Case("450", ArchDefineName | ArchDefine440)
1013 .Case("601", ArchDefineName)
1014 .Case("602", ArchDefineName | ArchDefinePpcgr)
1015 .Case("603", ArchDefineName | ArchDefinePpcgr)
1016 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1017 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1018 .Case("604", ArchDefineName | ArchDefinePpcgr)
1019 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1020 .Case("620", ArchDefineName | ArchDefinePpcgr)
1021 .Case("630", ArchDefineName | ArchDefinePpcgr)
1022 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1023 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1024 .Case("750", ArchDefineName | ArchDefinePpcgr)
1025 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1027 .Case("a2", ArchDefineA2)
1028 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1029 .Case("pwr3", ArchDefinePpcgr)
1030 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1031 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1033 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1034 | ArchDefinePpcgr | ArchDefinePpcsq)
1035 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1036 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1037 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1038 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1040 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1041 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1042 | ArchDefinePpcgr | ArchDefinePpcsq)
1043 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1044 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1045 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1046 .Case("power3", ArchDefinePpcgr)
1047 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1048 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1050 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1051 | ArchDefinePpcgr | ArchDefinePpcsq)
1052 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1053 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1054 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1055 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1057 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1058 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1059 | ArchDefinePpcgr | ArchDefinePpcsq)
1060 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1061 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1062 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1063 .Default(ArchDefineNone);
1065 if (defs & ArchDefineName)
1066 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1067 if (defs & ArchDefinePpcgr)
1068 Builder.defineMacro("_ARCH_PPCGR");
1069 if (defs & ArchDefinePpcsq)
1070 Builder.defineMacro("_ARCH_PPCSQ");
1071 if (defs & ArchDefine440)
1072 Builder.defineMacro("_ARCH_440");
1073 if (defs & ArchDefine603)
1074 Builder.defineMacro("_ARCH_603");
1075 if (defs & ArchDefine604)
1076 Builder.defineMacro("_ARCH_604");
1077 if (defs & ArchDefinePwr4)
1078 Builder.defineMacro("_ARCH_PWR4");
1079 if (defs & ArchDefinePwr5)
1080 Builder.defineMacro("_ARCH_PWR5");
1081 if (defs & ArchDefinePwr5x)
1082 Builder.defineMacro("_ARCH_PWR5X");
1083 if (defs & ArchDefinePwr6)
1084 Builder.defineMacro("_ARCH_PWR6");
1085 if (defs & ArchDefinePwr6x)
1086 Builder.defineMacro("_ARCH_PWR6X");
1087 if (defs & ArchDefinePwr7)
1088 Builder.defineMacro("_ARCH_PWR7");
1089 if (defs & ArchDefinePwr8)
1090 Builder.defineMacro("_ARCH_PWR8");
1091 if (defs & ArchDefineA2)
1092 Builder.defineMacro("_ARCH_A2");
1093 if (defs & ArchDefineA2q) {
1094 Builder.defineMacro("_ARCH_A2Q");
1095 Builder.defineMacro("_ARCH_QP");
1098 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1099 Builder.defineMacro("__bg__");
1100 Builder.defineMacro("__THW_BLUEGENE__");
1101 Builder.defineMacro("__bgq__");
1102 Builder.defineMacro("__TOS_BGQ__");
1106 Builder.defineMacro("__VSX__");
1108 Builder.defineMacro("__POWER8_VECTOR__");
1110 // FIXME: The following are not yet generated here by Clang, but are
1111 // generated by GCC:
1114 // __RECIP_PRECISION__
1115 // __APPLE_ALTIVEC__
1124 // __CMODEL_MEDIUM__
1131 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1132 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1142 .Case("ppc64", true)
1143 .Case("ppc64le", true)
1146 Features["qpx"] = (CPU == "a2q");
1149 Features[ABI] = true;
1152 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1153 return llvm::StringSwitch<bool>(Feature)
1154 .Case("powerpc", true)
1155 .Case("vsx", HasVSX)
1156 .Case("power8-vector", HasP8Vector)
1160 const char * const PPCTargetInfo::GCCRegNames[] = {
1161 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1162 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1163 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1164 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1165 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1166 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1167 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1168 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1169 "mq", "lr", "ctr", "ap",
1170 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1172 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1173 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1174 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1175 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1177 "spe_acc", "spefscr",
1181 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1182 unsigned &NumNames) const {
1183 Names = GCCRegNames;
1184 NumNames = llvm::array_lengthof(GCCRegNames);
1187 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1188 // While some of these aliases do map to different registers
1189 // they still share the same register name.
1200 { { "10" }, "r10" },
1201 { { "11" }, "r11" },
1202 { { "12" }, "r12" },
1203 { { "13" }, "r13" },
1204 { { "14" }, "r14" },
1205 { { "15" }, "r15" },
1206 { { "16" }, "r16" },
1207 { { "17" }, "r17" },
1208 { { "18" }, "r18" },
1209 { { "19" }, "r19" },
1210 { { "20" }, "r20" },
1211 { { "21" }, "r21" },
1212 { { "22" }, "r22" },
1213 { { "23" }, "r23" },
1214 { { "24" }, "r24" },
1215 { { "25" }, "r25" },
1216 { { "26" }, "r26" },
1217 { { "27" }, "r27" },
1218 { { "28" }, "r28" },
1219 { { "29" }, "r29" },
1220 { { "30" }, "r30" },
1221 { { "31" }, "r31" },
1222 { { "fr0" }, "f0" },
1223 { { "fr1" }, "f1" },
1224 { { "fr2" }, "f2" },
1225 { { "fr3" }, "f3" },
1226 { { "fr4" }, "f4" },
1227 { { "fr5" }, "f5" },
1228 { { "fr6" }, "f6" },
1229 { { "fr7" }, "f7" },
1230 { { "fr8" }, "f8" },
1231 { { "fr9" }, "f9" },
1232 { { "fr10" }, "f10" },
1233 { { "fr11" }, "f11" },
1234 { { "fr12" }, "f12" },
1235 { { "fr13" }, "f13" },
1236 { { "fr14" }, "f14" },
1237 { { "fr15" }, "f15" },
1238 { { "fr16" }, "f16" },
1239 { { "fr17" }, "f17" },
1240 { { "fr18" }, "f18" },
1241 { { "fr19" }, "f19" },
1242 { { "fr20" }, "f20" },
1243 { { "fr21" }, "f21" },
1244 { { "fr22" }, "f22" },
1245 { { "fr23" }, "f23" },
1246 { { "fr24" }, "f24" },
1247 { { "fr25" }, "f25" },
1248 { { "fr26" }, "f26" },
1249 { { "fr27" }, "f27" },
1250 { { "fr28" }, "f28" },
1251 { { "fr29" }, "f29" },
1252 { { "fr30" }, "f30" },
1253 { { "fr31" }, "f31" },
1254 { { "cc" }, "cr0" },
1257 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1258 unsigned &NumAliases) const {
1259 Aliases = GCCRegAliases;
1260 NumAliases = llvm::array_lengthof(GCCRegAliases);
1262 } // end anonymous namespace.
1265 class PPC32TargetInfo : public PPCTargetInfo {
1267 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1268 DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1270 switch (getTriple().getOS()) {
1271 case llvm::Triple::Linux:
1272 case llvm::Triple::FreeBSD:
1273 case llvm::Triple::NetBSD:
1274 SizeType = UnsignedInt;
1275 PtrDiffType = SignedInt;
1276 IntPtrType = SignedInt;
1282 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1283 LongDoubleWidth = LongDoubleAlign = 64;
1284 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1287 // PPC32 supports atomics up to 4 bytes.
1288 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1291 BuiltinVaListKind getBuiltinVaListKind() const override {
1292 // This is the ELF definition, and is overridden by the Darwin sub-target
1293 return TargetInfo::PowerABIBuiltinVaList;
1296 } // end anonymous namespace.
1298 // Note: ABI differences may eventually require us to have a separate
1299 // TargetInfo for little endian.
1301 class PPC64TargetInfo : public PPCTargetInfo {
1303 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1304 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1305 IntMaxType = SignedLong;
1306 Int64Type = SignedLong;
1308 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1309 DescriptionString = "e-m:e-i64:64-n32:64";
1312 DescriptionString = "E-m:e-i64:64-n32:64";
1316 switch (getTriple().getOS()) {
1317 case llvm::Triple::FreeBSD:
1318 LongDoubleWidth = LongDoubleAlign = 64;
1319 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1321 case llvm::Triple::NetBSD:
1322 IntMaxType = SignedLongLong;
1323 Int64Type = SignedLongLong;
1329 // PPC64 supports atomics up to 8 bytes.
1330 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1332 BuiltinVaListKind getBuiltinVaListKind() const override {
1333 return TargetInfo::CharPtrBuiltinVaList;
1335 // PPC64 Linux-specifc ABI options.
1336 bool setABI(const std::string &Name) override {
1337 if (Name == "elfv1" || Name == "elfv2") {
1344 } // end anonymous namespace.
1348 class DarwinPPC32TargetInfo :
1349 public DarwinTargetInfo<PPC32TargetInfo> {
1351 DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1352 : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1353 HasAlignMac68kSupport = true;
1354 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1355 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1357 SuitableAlign = 128;
1358 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1360 BuiltinVaListKind getBuiltinVaListKind() const override {
1361 return TargetInfo::CharPtrBuiltinVaList;
1365 class DarwinPPC64TargetInfo :
1366 public DarwinTargetInfo<PPC64TargetInfo> {
1368 DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1369 : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1370 HasAlignMac68kSupport = true;
1371 SuitableAlign = 128;
1372 DescriptionString = "E-m:o-i64:64-n32:64";
1375 } // end anonymous namespace.
1378 static const unsigned NVPTXAddrSpaceMap[] = {
1381 4, // opencl_constant
1382 // FIXME: generic has to be added to the target
1383 0, // opencl_generic
1388 class NVPTXTargetInfo : public TargetInfo {
1389 static const char * const GCCRegNames[];
1390 static const Builtin::Info BuiltinInfo[];
1392 // The GPU profiles supported by the NVPTX backend
1402 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1404 TLSSupported = false;
1405 LongWidth = LongAlign = 64;
1406 AddrSpaceMap = &NVPTXAddrSpaceMap;
1407 UseAddrSpaceMapMangling = true;
1408 // Define available target features
1409 // These must be defined in sorted order!
1410 NoAsmVariants = true;
1411 // Set the default GPU to sm20
1414 void getTargetDefines(const LangOptions &Opts,
1415 MacroBuilder &Builder) const override {
1416 Builder.defineMacro("__PTX__");
1417 Builder.defineMacro("__NVPTX__");
1418 if (Opts.CUDAIsDevice) {
1419 // Set __CUDA_ARCH__ for the GPU specified.
1420 std::string CUDAArchCode;
1423 CUDAArchCode = "200";
1426 CUDAArchCode = "210";
1429 CUDAArchCode = "300";
1432 CUDAArchCode = "350";
1435 llvm_unreachable("Unhandled target CPU");
1437 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1440 void getTargetBuiltins(const Builtin::Info *&Records,
1441 unsigned &NumRecords) const override {
1442 Records = BuiltinInfo;
1443 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1445 bool hasFeature(StringRef Feature) const override {
1446 return Feature == "ptx" || Feature == "nvptx";
1449 void getGCCRegNames(const char * const *&Names,
1450 unsigned &NumNames) const override;
1451 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1452 unsigned &NumAliases) const override {
1458 validateAsmConstraint(const char *&Name,
1459 TargetInfo::ConstraintInfo &Info) const override {
1461 default: return false;
1468 Info.setAllowsRegister();
1472 const char *getClobbers() const override {
1473 // FIXME: Is this really right?
1476 BuiltinVaListKind getBuiltinVaListKind() const override {
1478 return TargetInfo::CharPtrBuiltinVaList;
1480 bool setCPU(const std::string &Name) override {
1481 GPU = llvm::StringSwitch<GPUKind>(Name)
1482 .Case("sm_20", GK_SM20)
1483 .Case("sm_21", GK_SM21)
1484 .Case("sm_30", GK_SM30)
1485 .Case("sm_35", GK_SM35)
1488 return GPU != GK_NONE;
1492 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1493 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1494 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1496 #include "clang/Basic/BuiltinsNVPTX.def"
1499 const char * const NVPTXTargetInfo::GCCRegNames[] = {
1503 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1504 unsigned &NumNames) const {
1505 Names = GCCRegNames;
1506 NumNames = llvm::array_lengthof(GCCRegNames);
1509 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1511 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1512 PointerWidth = PointerAlign = 32;
1513 SizeType = PtrDiffType = TargetInfo::UnsignedInt;
1514 IntPtrType = TargetInfo::SignedInt;
1515 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1519 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1521 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1522 PointerWidth = PointerAlign = 64;
1523 SizeType = PtrDiffType = TargetInfo::UnsignedLongLong;
1524 IntPtrType = TargetInfo::SignedLongLong;
1525 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1532 static const unsigned R600AddrSpaceMap[] = {
1535 2, // opencl_constant
1536 4, // opencl_generic
1542 // If you edit the description strings, make sure you update
1543 // getPointerWidthV().
1545 static const char *DescriptionStringR600 =
1546 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1547 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1549 static const char *DescriptionStringR600DoubleOps =
1550 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1551 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1553 static const char *DescriptionStringSI =
1554 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1555 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1556 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1558 class R600TargetInfo : public TargetInfo {
1559 static const Builtin::Info BuiltinInfo[];
1561 /// \brief The GPU profiles supported by the R600 target.
1569 GK_EVERGREEN_DOUBLE_OPS,
1570 GK_NORTHERN_ISLANDS,
1572 GK_SOUTHERN_ISLANDS,
1577 R600TargetInfo(const llvm::Triple &Triple)
1578 : TargetInfo(Triple), GPU(GK_R600) {
1579 DescriptionString = DescriptionStringR600;
1580 AddrSpaceMap = &R600AddrSpaceMap;
1581 UseAddrSpaceMapMangling = true;
1584 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1585 if (GPU <= GK_CAYMAN)
1598 const char * getClobbers() const override {
1602 void getGCCRegNames(const char * const *&Names,
1603 unsigned &numNames) const override {
1608 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1609 unsigned &NumAliases) const override {
1614 bool validateAsmConstraint(const char *&Name,
1615 TargetInfo::ConstraintInfo &info) const override {
1619 void getTargetBuiltins(const Builtin::Info *&Records,
1620 unsigned &NumRecords) const override {
1621 Records = BuiltinInfo;
1622 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;
1625 void getTargetDefines(const LangOptions &Opts,
1626 MacroBuilder &Builder) const override {
1627 Builder.defineMacro("__R600__");
1630 BuiltinVaListKind getBuiltinVaListKind() const override {
1631 return TargetInfo::CharPtrBuiltinVaList;
1634 bool setCPU(const std::string &Name) override {
1635 GPU = llvm::StringSwitch<GPUKind>(Name)
1636 .Case("r600" , GK_R600)
1637 .Case("rv610", GK_R600)
1638 .Case("rv620", GK_R600)
1639 .Case("rv630", GK_R600)
1640 .Case("rv635", GK_R600)
1641 .Case("rs780", GK_R600)
1642 .Case("rs880", GK_R600)
1643 .Case("rv670", GK_R600_DOUBLE_OPS)
1644 .Case("rv710", GK_R700)
1645 .Case("rv730", GK_R700)
1646 .Case("rv740", GK_R700_DOUBLE_OPS)
1647 .Case("rv770", GK_R700_DOUBLE_OPS)
1648 .Case("palm", GK_EVERGREEN)
1649 .Case("cedar", GK_EVERGREEN)
1650 .Case("sumo", GK_EVERGREEN)
1651 .Case("sumo2", GK_EVERGREEN)
1652 .Case("redwood", GK_EVERGREEN)
1653 .Case("juniper", GK_EVERGREEN)
1654 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
1655 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
1656 .Case("barts", GK_NORTHERN_ISLANDS)
1657 .Case("turks", GK_NORTHERN_ISLANDS)
1658 .Case("caicos", GK_NORTHERN_ISLANDS)
1659 .Case("cayman", GK_CAYMAN)
1660 .Case("aruba", GK_CAYMAN)
1661 .Case("tahiti", GK_SOUTHERN_ISLANDS)
1662 .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1663 .Case("verde", GK_SOUTHERN_ISLANDS)
1664 .Case("oland", GK_SOUTHERN_ISLANDS)
1665 .Case("hainan", GK_SOUTHERN_ISLANDS)
1666 .Case("bonaire", GK_SEA_ISLANDS)
1667 .Case("kabini", GK_SEA_ISLANDS)
1668 .Case("kaveri", GK_SEA_ISLANDS)
1669 .Case("hawaii", GK_SEA_ISLANDS)
1670 .Case("mullins", GK_SEA_ISLANDS)
1673 if (GPU == GK_NONE) {
1677 // Set the correct data layout
1683 case GK_NORTHERN_ISLANDS:
1684 DescriptionString = DescriptionStringR600;
1686 case GK_R600_DOUBLE_OPS:
1687 case GK_R700_DOUBLE_OPS:
1688 case GK_EVERGREEN_DOUBLE_OPS:
1690 DescriptionString = DescriptionStringR600DoubleOps;
1692 case GK_SOUTHERN_ISLANDS:
1693 case GK_SEA_ISLANDS:
1694 DescriptionString = DescriptionStringSI;
1702 const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
1703 #define BUILTIN(ID, TYPE, ATTRS) \
1704 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1705 #include "clang/Basic/BuiltinsR600.def"
1708 } // end anonymous namespace
1711 // Namespace for x86 abstract base class
1712 const Builtin::Info BuiltinInfo[] = {
1713 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1714 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1716 #include "clang/Basic/BuiltinsX86.def"
1719 static const char* const GCCRegNames[] = {
1720 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1721 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1722 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1723 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1724 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1725 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1726 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1727 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1728 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1731 const TargetInfo::AddlRegName AddlRegNames[] = {
1732 { { "al", "ah", "eax", "rax" }, 0 },
1733 { { "bl", "bh", "ebx", "rbx" }, 3 },
1734 { { "cl", "ch", "ecx", "rcx" }, 2 },
1735 { { "dl", "dh", "edx", "rdx" }, 1 },
1736 { { "esi", "rsi" }, 4 },
1737 { { "edi", "rdi" }, 5 },
1738 { { "esp", "rsp" }, 7 },
1739 { { "ebp", "rbp" }, 6 },
1742 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1743 // most of the implementation can be shared.
1744 class X86TargetInfo : public TargetInfo {
1746 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1749 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1773 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW,
1778 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1780 /// Each enumeration represents a particular CPU supported by Clang. These
1781 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1786 /// i386-generation processors.
1792 /// i486-generation processors.
1801 /// i586-generation processors, P5 microarchitecture based.
1809 /// i686-generation processors, P6 / Pentium M microarchitecture based.
1819 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1820 /// Clang however has some logic to suport this.
1821 // FIXME: Warn, deprecate, and potentially remove this.
1826 /// Netburst microarchitecture based processors.
1835 /// Core microarchitecture based processors.
1839 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1840 /// codename which GCC no longer accepts as an option to -march, but Clang
1841 /// has some logic for recognizing it.
1842 // FIXME: Warn, deprecate, and potentially remove this.
1854 /// Nehalem microarchitecture based processors.
1858 /// Westmere microarchitecture based processors.
1861 /// \name Sandy Bridge
1862 /// Sandy Bridge microarchitecture based processors.
1865 /// \name Ivy Bridge
1866 /// Ivy Bridge microarchitecture based processors.
1870 /// Haswell microarchitecture based processors.
1874 /// Broadwell microarchitecture based processors.
1878 /// Skylake microarchitecture based processors.
1881 /// \name Knights Landing
1882 /// Knights Landing processor.
1886 /// K6 architecture processors.
1894 /// K7 architecture processors.
1897 CK_AthlonThunderbird,
1904 /// K8 architecture processors.
1917 /// Bobcat architecture processors.
1924 /// Bulldozer architecture processors.
1932 /// This specification is deprecated and will be removed in the future.
1933 /// Users should prefer \see CK_K8.
1934 // FIXME: Warn on this when the CPU is set to it.
1940 /// Geode processors.
1953 X86TargetInfo(const llvm::Triple &Triple)
1954 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1955 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
1956 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
1957 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
1958 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
1959 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
1960 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
1961 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
1963 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1965 unsigned getFloatEvalMethod() const override {
1966 // X87 evaluates with 80 bits "long double" precision.
1967 return SSELevel == NoSSE ? 2 : 0;
1969 void getTargetBuiltins(const Builtin::Info *&Records,
1970 unsigned &NumRecords) const override {
1971 Records = BuiltinInfo;
1972 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1974 void getGCCRegNames(const char * const *&Names,
1975 unsigned &NumNames) const override {
1976 Names = GCCRegNames;
1977 NumNames = llvm::array_lengthof(GCCRegNames);
1979 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1980 unsigned &NumAliases) const override {
1984 void getGCCAddlRegNames(const AddlRegName *&Names,
1985 unsigned &NumNames) const override {
1986 Names = AddlRegNames;
1987 NumNames = llvm::array_lengthof(AddlRegNames);
1989 bool validateAsmConstraint(const char *&Name,
1990 TargetInfo::ConstraintInfo &info) const override;
1992 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
1994 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
1996 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
1998 std::string convertConstraint(const char *&Constraint) const override;
1999 const char *getClobbers() const override {
2000 return "~{dirflag},~{fpsr},~{flags}";
2002 void getTargetDefines(const LangOptions &Opts,
2003 MacroBuilder &Builder) const override;
2004 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2006 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2008 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2010 void setFeatureEnabled(llvm::StringMap<bool> &Features,
2011 StringRef Name, bool Enabled) const override {
2012 setFeatureEnabledImpl(Features, Name, Enabled);
2014 // This exists purely to cut down on the number of virtual calls in
2015 // getDefaultFeatures which calls this repeatedly.
2016 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2017 StringRef Name, bool Enabled);
2018 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
2019 bool hasFeature(StringRef Feature) const override;
2020 bool handleTargetFeatures(std::vector<std::string> &Features,
2021 DiagnosticsEngine &Diags) override;
2022 StringRef getABI() const override {
2023 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2025 else if (getTriple().getArch() == llvm::Triple::x86 &&
2026 MMX3DNowLevel == NoMMX3DNow)
2030 bool setCPU(const std::string &Name) override {
2031 CPU = llvm::StringSwitch<CPUKind>(Name)
2032 .Case("i386", CK_i386)
2033 .Case("i486", CK_i486)
2034 .Case("winchip-c6", CK_WinChipC6)
2035 .Case("winchip2", CK_WinChip2)
2037 .Case("i586", CK_i586)
2038 .Case("pentium", CK_Pentium)
2039 .Case("pentium-mmx", CK_PentiumMMX)
2040 .Case("i686", CK_i686)
2041 .Case("pentiumpro", CK_PentiumPro)
2042 .Case("pentium2", CK_Pentium2)
2043 .Case("pentium3", CK_Pentium3)
2044 .Case("pentium3m", CK_Pentium3M)
2045 .Case("pentium-m", CK_PentiumM)
2046 .Case("c3-2", CK_C3_2)
2047 .Case("yonah", CK_Yonah)
2048 .Case("pentium4", CK_Pentium4)
2049 .Case("pentium4m", CK_Pentium4M)
2050 .Case("prescott", CK_Prescott)
2051 .Case("nocona", CK_Nocona)
2052 .Case("core2", CK_Core2)
2053 .Case("penryn", CK_Penryn)
2054 .Case("bonnell", CK_Bonnell)
2055 .Case("atom", CK_Bonnell) // Legacy name.
2056 .Case("silvermont", CK_Silvermont)
2057 .Case("slm", CK_Silvermont) // Legacy name.
2058 .Case("nehalem", CK_Nehalem)
2059 .Case("corei7", CK_Nehalem) // Legacy name.
2060 .Case("westmere", CK_Westmere)
2061 .Case("sandybridge", CK_SandyBridge)
2062 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2063 .Case("ivybridge", CK_IvyBridge)
2064 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2065 .Case("haswell", CK_Haswell)
2066 .Case("core-avx2", CK_Haswell) // Legacy name.
2067 .Case("broadwell", CK_Broadwell)
2068 .Case("skylake", CK_Skylake)
2069 .Case("skx", CK_Skylake) // Legacy name.
2070 .Case("knl", CK_KNL)
2072 .Case("k6-2", CK_K6_2)
2073 .Case("k6-3", CK_K6_3)
2074 .Case("athlon", CK_Athlon)
2075 .Case("athlon-tbird", CK_AthlonThunderbird)
2076 .Case("athlon-4", CK_Athlon4)
2077 .Case("athlon-xp", CK_AthlonXP)
2078 .Case("athlon-mp", CK_AthlonMP)
2079 .Case("athlon64", CK_Athlon64)
2080 .Case("athlon64-sse3", CK_Athlon64SSE3)
2081 .Case("athlon-fx", CK_AthlonFX)
2083 .Case("k8-sse3", CK_K8SSE3)
2084 .Case("opteron", CK_Opteron)
2085 .Case("opteron-sse3", CK_OpteronSSE3)
2086 .Case("barcelona", CK_AMDFAM10)
2087 .Case("amdfam10", CK_AMDFAM10)
2088 .Case("btver1", CK_BTVER1)
2089 .Case("btver2", CK_BTVER2)
2090 .Case("bdver1", CK_BDVER1)
2091 .Case("bdver2", CK_BDVER2)
2092 .Case("bdver3", CK_BDVER3)
2093 .Case("bdver4", CK_BDVER4)
2094 .Case("x86-64", CK_x86_64)
2095 .Case("geode", CK_Geode)
2096 .Default(CK_Generic);
2098 // Perform any per-CPU checks necessary to determine if this CPU is
2100 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2101 // invalid without explaining *why*.
2104 // No processor selected!
2130 case CK_AthlonThunderbird:
2135 // Only accept certain architectures when compiling in 32-bit mode.
2136 if (getTriple().getArch() != llvm::Triple::x86)
2147 case CK_SandyBridge:
2154 case CK_Athlon64SSE3:
2159 case CK_OpteronSSE3:
2170 llvm_unreachable("Unhandled CPU kind");
2173 bool setFPMath(StringRef Name) override;
2175 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2176 // We accept all non-ARM calling conventions
2177 return (CC == CC_X86ThisCall ||
2178 CC == CC_X86FastCall ||
2179 CC == CC_X86StdCall ||
2180 CC == CC_X86VectorCall ||
2182 CC == CC_X86Pascal ||
2183 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2186 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2187 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2190 bool hasSjLjLowering() const override {
2195 bool X86TargetInfo::setFPMath(StringRef Name) {
2196 if (Name == "387") {
2200 if (Name == "sse") {
2207 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2208 // FIXME: This *really* should not be here.
2210 // X86_64 always has SSE2.
2211 if (getTriple().getArch() == llvm::Triple::x86_64)
2212 setFeatureEnabledImpl(Features, "sse2", true);
2227 setFeatureEnabledImpl(Features, "mmx", true);
2232 setFeatureEnabledImpl(Features, "sse", true);
2238 setFeatureEnabledImpl(Features, "sse2", true);
2243 setFeatureEnabledImpl(Features, "sse3", true);
2244 setFeatureEnabledImpl(Features, "cx16", true);
2248 setFeatureEnabledImpl(Features, "ssse3", true);
2249 setFeatureEnabledImpl(Features, "cx16", true);
2252 setFeatureEnabledImpl(Features, "sse4.1", true);
2253 setFeatureEnabledImpl(Features, "cx16", true);
2256 setFeatureEnabledImpl(Features, "avx512f", true);
2257 setFeatureEnabledImpl(Features, "avx512cd", true);
2258 setFeatureEnabledImpl(Features, "avx512dq", true);
2259 setFeatureEnabledImpl(Features, "avx512bw", true);
2260 setFeatureEnabledImpl(Features, "avx512vl", true);
2263 setFeatureEnabledImpl(Features, "rdseed", true);
2264 setFeatureEnabledImpl(Features, "adx", true);
2267 setFeatureEnabledImpl(Features, "avx2", true);
2268 setFeatureEnabledImpl(Features, "lzcnt", true);
2269 setFeatureEnabledImpl(Features, "bmi", true);
2270 setFeatureEnabledImpl(Features, "bmi2", true);
2271 setFeatureEnabledImpl(Features, "rtm", true);
2272 setFeatureEnabledImpl(Features, "fma", true);
2275 setFeatureEnabledImpl(Features, "rdrnd", true);
2276 setFeatureEnabledImpl(Features, "f16c", true);
2277 setFeatureEnabledImpl(Features, "fsgsbase", true);
2279 case CK_SandyBridge:
2280 setFeatureEnabledImpl(Features, "avx", true);
2284 setFeatureEnabledImpl(Features, "aes", true);
2285 setFeatureEnabledImpl(Features, "pclmul", true);
2288 setFeatureEnabledImpl(Features, "sse4.2", true);
2289 setFeatureEnabledImpl(Features, "cx16", true);
2292 setFeatureEnabledImpl(Features, "avx512f", true);
2293 setFeatureEnabledImpl(Features, "avx512cd", true);
2294 setFeatureEnabledImpl(Features, "avx512er", true);
2295 setFeatureEnabledImpl(Features, "avx512pf", true);
2296 setFeatureEnabledImpl(Features, "rdseed", true);
2297 setFeatureEnabledImpl(Features, "adx", true);
2298 setFeatureEnabledImpl(Features, "lzcnt", true);
2299 setFeatureEnabledImpl(Features, "bmi", true);
2300 setFeatureEnabledImpl(Features, "bmi2", true);
2301 setFeatureEnabledImpl(Features, "rtm", true);
2302 setFeatureEnabledImpl(Features, "fma", true);
2303 setFeatureEnabledImpl(Features, "rdrnd", true);
2304 setFeatureEnabledImpl(Features, "f16c", true);
2305 setFeatureEnabledImpl(Features, "fsgsbase", true);
2306 setFeatureEnabledImpl(Features, "aes", true);
2307 setFeatureEnabledImpl(Features, "pclmul", true);
2308 setFeatureEnabledImpl(Features, "cx16", true);
2314 setFeatureEnabledImpl(Features, "3dnow", true);
2317 case CK_AthlonThunderbird:
2319 setFeatureEnabledImpl(Features, "3dnowa", true);
2324 setFeatureEnabledImpl(Features, "sse", true);
2325 setFeatureEnabledImpl(Features, "3dnowa", true);
2331 setFeatureEnabledImpl(Features, "sse2", true);
2332 setFeatureEnabledImpl(Features, "3dnowa", true);
2335 setFeatureEnabledImpl(Features, "sse4a", true);
2336 setFeatureEnabledImpl(Features, "lzcnt", true);
2337 setFeatureEnabledImpl(Features, "popcnt", true);
2340 case CK_OpteronSSE3:
2341 case CK_Athlon64SSE3:
2342 setFeatureEnabledImpl(Features, "sse3", true);
2343 setFeatureEnabledImpl(Features, "3dnowa", true);
2346 setFeatureEnabledImpl(Features, "avx", true);
2347 setFeatureEnabledImpl(Features, "aes", true);
2348 setFeatureEnabledImpl(Features, "pclmul", true);
2349 setFeatureEnabledImpl(Features, "bmi", true);
2350 setFeatureEnabledImpl(Features, "f16c", true);
2353 setFeatureEnabledImpl(Features, "ssse3", true);
2354 setFeatureEnabledImpl(Features, "sse4a", true);
2355 setFeatureEnabledImpl(Features, "lzcnt", true);
2356 setFeatureEnabledImpl(Features, "popcnt", true);
2357 setFeatureEnabledImpl(Features, "prfchw", true);
2358 setFeatureEnabledImpl(Features, "cx16", true);
2361 setFeatureEnabledImpl(Features, "avx2", true);
2362 setFeatureEnabledImpl(Features, "bmi2", true);
2365 setFeatureEnabledImpl(Features, "fsgsbase", true);
2368 setFeatureEnabledImpl(Features, "bmi", true);
2369 setFeatureEnabledImpl(Features, "fma", true);
2370 setFeatureEnabledImpl(Features, "f16c", true);
2371 setFeatureEnabledImpl(Features, "tbm", true);
2374 // xop implies avx, sse4a and fma4.
2375 setFeatureEnabledImpl(Features, "xop", true);
2376 setFeatureEnabledImpl(Features, "lzcnt", true);
2377 setFeatureEnabledImpl(Features, "aes", true);
2378 setFeatureEnabledImpl(Features, "pclmul", true);
2379 setFeatureEnabledImpl(Features, "prfchw", true);
2380 setFeatureEnabledImpl(Features, "cx16", true);
2385 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2386 X86SSEEnum Level, bool Enabled) {
2390 Features["avx512f"] = true;
2392 Features["avx2"] = true;
2394 Features["avx"] = true;
2396 Features["sse4.2"] = true;
2398 Features["sse4.1"] = true;
2400 Features["ssse3"] = true;
2402 Features["sse3"] = true;
2404 Features["sse2"] = true;
2406 Features["sse"] = true;
2416 Features["sse"] = false;
2418 Features["sse2"] = Features["pclmul"] = Features["aes"] =
2419 Features["sha"] = false;
2421 Features["sse3"] = false;
2422 setXOPLevel(Features, NoXOP, false);
2424 Features["ssse3"] = false;
2426 Features["sse4.1"] = false;
2428 Features["sse4.2"] = false;
2430 Features["fma"] = Features["avx"] = Features["f16c"] = false;
2431 setXOPLevel(Features, FMA4, false);
2433 Features["avx2"] = false;
2435 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2436 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2437 Features["avx512vl"] = false;
2441 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2442 MMX3DNowEnum Level, bool Enabled) {
2445 case AMD3DNowAthlon:
2446 Features["3dnowa"] = true;
2448 Features["3dnow"] = true;
2450 Features["mmx"] = true;
2460 Features["mmx"] = false;
2462 Features["3dnow"] = false;
2463 case AMD3DNowAthlon:
2464 Features["3dnowa"] = false;
2468 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2473 Features["xop"] = true;
2475 Features["fma4"] = true;
2476 setSSELevel(Features, AVX, true);
2478 Features["sse4a"] = true;
2479 setSSELevel(Features, SSE3, true);
2489 Features["sse4a"] = false;
2491 Features["fma4"] = false;
2493 Features["xop"] = false;
2497 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2498 StringRef Name, bool Enabled) {
2499 // FIXME: This *really* should not be here. We need some way of translating
2500 // options into llvm subtarget features.
2504 Features[Name] = Enabled;
2506 if (Name == "mmx") {
2507 setMMXLevel(Features, MMX, Enabled);
2508 } else if (Name == "sse") {
2509 setSSELevel(Features, SSE1, Enabled);
2510 } else if (Name == "sse2") {
2511 setSSELevel(Features, SSE2, Enabled);
2512 } else if (Name == "sse3") {
2513 setSSELevel(Features, SSE3, Enabled);
2514 } else if (Name == "ssse3") {
2515 setSSELevel(Features, SSSE3, Enabled);
2516 } else if (Name == "sse4.2") {
2517 setSSELevel(Features, SSE42, Enabled);
2518 } else if (Name == "sse4.1") {
2519 setSSELevel(Features, SSE41, Enabled);
2520 } else if (Name == "3dnow") {
2521 setMMXLevel(Features, AMD3DNow, Enabled);
2522 } else if (Name == "3dnowa") {
2523 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2524 } else if (Name == "aes") {
2526 setSSELevel(Features, SSE2, Enabled);
2527 } else if (Name == "pclmul") {
2529 setSSELevel(Features, SSE2, Enabled);
2530 } else if (Name == "avx") {
2531 setSSELevel(Features, AVX, Enabled);
2532 } else if (Name == "avx2") {
2533 setSSELevel(Features, AVX2, Enabled);
2534 } else if (Name == "avx512f") {
2535 setSSELevel(Features, AVX512F, Enabled);
2536 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2537 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2539 setSSELevel(Features, AVX512F, Enabled);
2540 } else if (Name == "fma") {
2542 setSSELevel(Features, AVX, Enabled);
2543 } else if (Name == "fma4") {
2544 setXOPLevel(Features, FMA4, Enabled);
2545 } else if (Name == "xop") {
2546 setXOPLevel(Features, XOP, Enabled);
2547 } else if (Name == "sse4a") {
2548 setXOPLevel(Features, SSE4A, Enabled);
2549 } else if (Name == "f16c") {
2551 setSSELevel(Features, AVX, Enabled);
2552 } else if (Name == "sha") {
2554 setSSELevel(Features, SSE2, Enabled);
2558 /// handleTargetFeatures - Perform initialization based on the user
2559 /// configured set of features.
2560 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2561 DiagnosticsEngine &Diags) {
2562 // Remember the maximum enabled sselevel.
2563 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2564 // Ignore disabled features.
2565 if (Features[i][0] == '-')
2568 StringRef Feature = StringRef(Features[i]).substr(1);
2570 if (Feature == "aes") {
2575 if (Feature == "pclmul") {
2580 if (Feature == "lzcnt") {
2585 if (Feature == "rdrnd") {
2590 if (Feature == "fsgsbase") {
2595 if (Feature == "bmi") {
2600 if (Feature == "bmi2") {
2605 if (Feature == "popcnt") {
2610 if (Feature == "rtm") {
2615 if (Feature == "prfchw") {
2620 if (Feature == "rdseed") {
2625 if (Feature == "adx") {
2630 if (Feature == "tbm") {
2635 if (Feature == "fma") {
2640 if (Feature == "f16c") {
2645 if (Feature == "avx512cd") {
2650 if (Feature == "avx512er") {
2655 if (Feature == "avx512pf") {
2660 if (Feature == "avx512dq") {
2665 if (Feature == "avx512bw") {
2670 if (Feature == "avx512vl") {
2675 if (Feature == "sha") {
2680 if (Feature == "cx16") {
2685 assert(Features[i][0] == '+' && "Invalid target feature!");
2686 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2687 .Case("avx512f", AVX512F)
2690 .Case("sse4.2", SSE42)
2691 .Case("sse4.1", SSE41)
2692 .Case("ssse3", SSSE3)
2697 SSELevel = std::max(SSELevel, Level);
2699 MMX3DNowEnum ThreeDNowLevel =
2700 llvm::StringSwitch<MMX3DNowEnum>(Feature)
2701 .Case("3dnowa", AMD3DNowAthlon)
2702 .Case("3dnow", AMD3DNow)
2704 .Default(NoMMX3DNow);
2705 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2707 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2710 .Case("sse4a", SSE4A)
2712 XOPLevel = std::max(XOPLevel, XLevel);
2715 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2716 // Can't do this earlier because we need to be able to explicitly enable
2717 // popcnt and still disable sse4.2.
2718 if (!HasPOPCNT && SSELevel >= SSE42 &&
2719 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2721 Features.push_back("+popcnt");
2724 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2725 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2726 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2728 Features.push_back("+prfchw");
2731 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2732 // matches the selected sse level.
2733 if (FPMath == FP_SSE && SSELevel < SSE1) {
2734 Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2736 } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2737 Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2741 // Don't tell the backend if we're turning off mmx; it will end up disabling
2742 // SSE, which we don't want.
2743 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2745 std::vector<std::string>::iterator it;
2746 it = std::find(Features.begin(), Features.end(), "-mmx");
2747 if (it != Features.end())
2749 else if (SSELevel > NoSSE)
2750 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2754 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2755 /// definitions for this particular subtarget.
2756 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2757 MacroBuilder &Builder) const {
2758 // Target identification.
2759 if (getTriple().getArch() == llvm::Triple::x86_64) {
2760 Builder.defineMacro("__amd64__");
2761 Builder.defineMacro("__amd64");
2762 Builder.defineMacro("__x86_64");
2763 Builder.defineMacro("__x86_64__");
2764 if (getTriple().getArchName() == "x86_64h") {
2765 Builder.defineMacro("__x86_64h");
2766 Builder.defineMacro("__x86_64h__");
2769 DefineStd(Builder, "i386", Opts);
2772 // Subtarget options.
2773 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2774 // truly should be based on -mtune options.
2779 // The rest are coming from the i386 define above.
2780 Builder.defineMacro("__tune_i386__");
2786 defineCPUMacros(Builder, "i486");
2789 Builder.defineMacro("__pentium_mmx__");
2790 Builder.defineMacro("__tune_pentium_mmx__");
2794 defineCPUMacros(Builder, "i586");
2795 defineCPUMacros(Builder, "pentium");
2800 Builder.defineMacro("__tune_pentium3__");
2804 Builder.defineMacro("__tune_pentium2__");
2807 Builder.defineMacro("__tune_i686__");
2808 Builder.defineMacro("__tune_pentiumpro__");
2811 Builder.defineMacro("__i686");
2812 Builder.defineMacro("__i686__");
2813 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2814 Builder.defineMacro("__pentiumpro");
2815 Builder.defineMacro("__pentiumpro__");
2819 defineCPUMacros(Builder, "pentium4");
2824 defineCPUMacros(Builder, "nocona");
2828 defineCPUMacros(Builder, "core2");
2831 defineCPUMacros(Builder, "atom");
2834 defineCPUMacros(Builder, "slm");
2838 case CK_SandyBridge:
2842 // FIXME: Historically, we defined this legacy name, it would be nice to
2843 // remove it at some point. We've never exposed fine-grained names for
2844 // recent primary x86 CPUs, and we should keep it that way.
2845 defineCPUMacros(Builder, "corei7");
2848 // FIXME: Historically, we defined this legacy name, it would be nice to
2849 // remove it at some point. This is the only fine-grained CPU macro in the
2850 // main intel CPU line, and it would be better to not have these and force
2851 // people to use ISA macros.
2852 defineCPUMacros(Builder, "skx");
2855 defineCPUMacros(Builder, "knl");
2858 Builder.defineMacro("__k6_2__");
2859 Builder.defineMacro("__tune_k6_2__");
2862 if (CPU != CK_K6_2) { // In case of fallthrough
2863 // FIXME: GCC may be enabling these in cases where some other k6
2864 // architecture is specified but -m3dnow is explicitly provided. The
2865 // exact semantics need to be determined and emulated here.
2866 Builder.defineMacro("__k6_3__");
2867 Builder.defineMacro("__tune_k6_3__");
2871 defineCPUMacros(Builder, "k6");
2874 case CK_AthlonThunderbird:
2878 defineCPUMacros(Builder, "athlon");
2879 if (SSELevel != NoSSE) {
2880 Builder.defineMacro("__athlon_sse__");
2881 Builder.defineMacro("__tune_athlon_sse__");
2888 case CK_OpteronSSE3:
2890 case CK_Athlon64SSE3:
2892 defineCPUMacros(Builder, "k8");
2895 defineCPUMacros(Builder, "amdfam10");
2898 defineCPUMacros(Builder, "btver1");
2901 defineCPUMacros(Builder, "btver2");
2904 defineCPUMacros(Builder, "bdver1");
2907 defineCPUMacros(Builder, "bdver2");
2910 defineCPUMacros(Builder, "bdver3");
2913 defineCPUMacros(Builder, "bdver4");
2916 defineCPUMacros(Builder, "geode");
2920 // Target properties.
2921 Builder.defineMacro("__REGISTER_PREFIX__", "");
2923 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2924 // functions in glibc header files that use FP Stack inline asm which the
2925 // backend can't deal with (PR879).
2926 Builder.defineMacro("__NO_MATH_INLINES");
2929 Builder.defineMacro("__AES__");
2932 Builder.defineMacro("__PCLMUL__");
2935 Builder.defineMacro("__LZCNT__");
2938 Builder.defineMacro("__RDRND__");
2941 Builder.defineMacro("__FSGSBASE__");
2944 Builder.defineMacro("__BMI__");
2947 Builder.defineMacro("__BMI2__");
2950 Builder.defineMacro("__POPCNT__");
2953 Builder.defineMacro("__RTM__");
2956 Builder.defineMacro("__PRFCHW__");
2959 Builder.defineMacro("__RDSEED__");
2962 Builder.defineMacro("__ADX__");
2965 Builder.defineMacro("__TBM__");
2969 Builder.defineMacro("__XOP__");
2971 Builder.defineMacro("__FMA4__");
2973 Builder.defineMacro("__SSE4A__");
2979 Builder.defineMacro("__FMA__");
2982 Builder.defineMacro("__F16C__");
2985 Builder.defineMacro("__AVX512CD__");
2987 Builder.defineMacro("__AVX512ER__");
2989 Builder.defineMacro("__AVX512PF__");
2991 Builder.defineMacro("__AVX512DQ__");
2993 Builder.defineMacro("__AVX512BW__");
2995 Builder.defineMacro("__AVX512VL__");
2998 Builder.defineMacro("__SHA__");
3001 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3003 // Each case falls through to the previous one here.
3006 Builder.defineMacro("__AVX512F__");
3008 Builder.defineMacro("__AVX2__");
3010 Builder.defineMacro("__AVX__");
3012 Builder.defineMacro("__SSE4_2__");
3014 Builder.defineMacro("__SSE4_1__");
3016 Builder.defineMacro("__SSSE3__");
3018 Builder.defineMacro("__SSE3__");
3020 Builder.defineMacro("__SSE2__");
3021 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
3023 Builder.defineMacro("__SSE__");
3024 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
3029 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3039 Builder.defineMacro("_M_IX86_FP", Twine(2));
3042 Builder.defineMacro("_M_IX86_FP", Twine(1));
3045 Builder.defineMacro("_M_IX86_FP", Twine(0));
3049 // Each case falls through to the previous one here.
3050 switch (MMX3DNowLevel) {
3051 case AMD3DNowAthlon:
3052 Builder.defineMacro("__3dNOW_A__");
3054 Builder.defineMacro("__3dNOW__");
3056 Builder.defineMacro("__MMX__");
3061 if (CPU >= CK_i486) {
3062 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3063 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3064 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3067 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3070 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3071 return llvm::StringSwitch<bool>(Feature)
3072 .Case("aes", HasAES)
3073 .Case("avx", SSELevel >= AVX)
3074 .Case("avx2", SSELevel >= AVX2)
3075 .Case("avx512f", SSELevel >= AVX512F)
3076 .Case("avx512cd", HasAVX512CD)
3077 .Case("avx512er", HasAVX512ER)
3078 .Case("avx512pf", HasAVX512PF)
3079 .Case("avx512dq", HasAVX512DQ)
3080 .Case("avx512bw", HasAVX512BW)
3081 .Case("avx512vl", HasAVX512VL)
3082 .Case("bmi", HasBMI)
3083 .Case("bmi2", HasBMI2)
3084 .Case("cx16", HasCX16)
3085 .Case("f16c", HasF16C)
3086 .Case("fma", HasFMA)
3087 .Case("fma4", XOPLevel >= FMA4)
3088 .Case("fsgsbase", HasFSGSBASE)
3089 .Case("lzcnt", HasLZCNT)
3090 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3091 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3092 .Case("mmx", MMX3DNowLevel >= MMX)
3093 .Case("pclmul", HasPCLMUL)
3094 .Case("popcnt", HasPOPCNT)
3095 .Case("prfchw", HasPRFCHW)
3096 .Case("rdrnd", HasRDRND)
3097 .Case("rdseed", HasRDSEED)
3098 .Case("rtm", HasRTM)
3099 .Case("sha", HasSHA)
3100 .Case("sse", SSELevel >= SSE1)
3101 .Case("sse2", SSELevel >= SSE2)
3102 .Case("sse3", SSELevel >= SSE3)
3103 .Case("ssse3", SSELevel >= SSSE3)
3104 .Case("sse4.1", SSELevel >= SSE41)
3105 .Case("sse4.2", SSELevel >= SSE42)
3106 .Case("sse4a", XOPLevel >= SSE4A)
3107 .Case("tbm", HasTBM)
3109 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3110 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3111 .Case("xop", XOPLevel >= XOP)
3116 X86TargetInfo::validateAsmConstraint(const char *&Name,
3117 TargetInfo::ConstraintInfo &Info) const {
3119 default: return false;
3121 Info.setRequiresImmediate(0, 31);
3124 Info.setRequiresImmediate(0, 63);
3127 Info.setRequiresImmediate(-128, 127);
3130 // FIXME: properly analyze this constraint:
3131 // must be one of 0xff, 0xffff, or 0xffffffff
3134 Info.setRequiresImmediate(0, 3);
3137 Info.setRequiresImmediate(0, 255);
3140 Info.setRequiresImmediate(0, 127);
3142 case 'Y': // first letter of a pair:
3143 switch (*(Name+1)) {
3144 default: return false;
3145 case '0': // First SSE register.
3146 case 't': // Any SSE register, when SSE2 is enabled.
3147 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
3148 case 'm': // any MMX register, when inter-unit moves enabled.
3149 break; // falls through to setAllowsRegister.
3151 case 'f': // any x87 floating point stack register.
3152 // Constraint 'f' cannot be used for output operands.
3153 if (Info.ConstraintStr[0] == '=')
3156 Info.setAllowsRegister();
3164 case 'A': // edx:eax.
3165 case 't': // top of floating point stack.
3166 case 'u': // second from top of floating point stack.
3167 case 'q': // Any register accessible as [r]l: a, b, c, and d.
3168 case 'y': // Any MMX register.
3169 case 'x': // Any SSE register.
3170 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3171 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3172 case 'l': // "Index" registers: any general register that can be used as an
3173 // index in a base+index memory access.
3174 Info.setAllowsRegister();
3176 case 'C': // SSE floating point constant.
3177 case 'G': // x87 floating point constant.
3178 case 'e': // 32-bit signed integer constant for use with zero-extending
3179 // x86_64 instructions.
3180 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3181 // x86_64 instructions.
3186 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3187 unsigned Size) const {
3188 // Strip off constraint modifiers.
3189 while (Constraint[0] == '=' ||
3190 Constraint[0] == '+' ||
3191 Constraint[0] == '&')
3192 Constraint = Constraint.substr(1);
3194 return validateOperandSize(Constraint, Size);
3197 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3198 unsigned Size) const {
3199 return validateOperandSize(Constraint, Size);
3202 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3203 unsigned Size) const {
3204 switch (Constraint[0]) {
3213 // 256-bit ymm registers can be used if target supports AVX.
3214 return Size <= (SSELevel >= AVX ? 256U : 128U);
3221 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3222 switch (*Constraint) {
3223 case 'a': return std::string("{ax}");
3224 case 'b': return std::string("{bx}");
3225 case 'c': return std::string("{cx}");
3226 case 'd': return std::string("{dx}");
3227 case 'S': return std::string("{si}");
3228 case 'D': return std::string("{di}");
3229 case 'p': // address
3230 return std::string("im");
3231 case 't': // top of floating point stack.
3232 return std::string("{st}");
3233 case 'u': // second from top of floating point stack.
3234 return std::string("{st(1)}"); // second from top of floating point stack.
3236 return std::string(1, *Constraint);
3239 } // end anonymous namespace
3242 // X86-32 generic target
3243 class X86_32TargetInfo : public X86TargetInfo {
3245 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3246 DoubleAlign = LongLongAlign = 32;
3247 LongDoubleWidth = 96;
3248 LongDoubleAlign = 32;
3249 SuitableAlign = 128;
3250 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3251 SizeType = UnsignedInt;
3252 PtrDiffType = SignedInt;
3253 IntPtrType = SignedInt;
3256 // Use fpret for all types.
3257 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3258 (1 << TargetInfo::Double) |
3259 (1 << TargetInfo::LongDouble));
3261 // x86-32 has atomics up to 8 bytes
3262 // FIXME: Check that we actually have cmpxchg8b before setting
3263 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3264 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3266 BuiltinVaListKind getBuiltinVaListKind() const override {
3267 return TargetInfo::CharPtrBuiltinVaList;
3270 int getEHDataRegisterNumber(unsigned RegNo) const override {
3271 if (RegNo == 0) return 0;
3272 if (RegNo == 1) return 2;
3275 bool validateOperandSize(StringRef Constraint,
3276 unsigned Size) const override {
3277 switch (Constraint[0]) {
3293 return X86TargetInfo::validateOperandSize(Constraint, Size);
3296 } // end anonymous namespace
3299 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3301 NetBSDI386TargetInfo(const llvm::Triple &Triple)
3302 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3304 unsigned getFloatEvalMethod() const override {
3305 unsigned Major, Minor, Micro;
3306 getTriple().getOSVersion(Major, Minor, Micro);
3307 // New NetBSD uses the default rounding mode.
3308 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3309 return X86_32TargetInfo::getFloatEvalMethod();
3310 // NetBSD before 6.99.26 defaults to "double" rounding.
3314 } // end anonymous namespace
3317 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3319 OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3320 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3321 SizeType = UnsignedLong;
3322 IntPtrType = SignedLong;
3323 PtrDiffType = SignedLong;
3326 } // end anonymous namespace
3329 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3331 BitrigI386TargetInfo(const llvm::Triple &Triple)
3332 : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3333 SizeType = UnsignedLong;
3334 IntPtrType = SignedLong;
3335 PtrDiffType = SignedLong;
3338 } // end anonymous namespace
3341 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3343 DarwinI386TargetInfo(const llvm::Triple &Triple)
3344 : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3345 LongDoubleWidth = 128;
3346 LongDoubleAlign = 128;
3347 SuitableAlign = 128;
3348 MaxVectorAlign = 256;
3349 SizeType = UnsignedLong;
3350 IntPtrType = SignedLong;
3351 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3352 HasAlignMac68kSupport = true;
3356 } // end anonymous namespace
3359 // x86-32 Windows target
3360 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3362 WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3363 : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3364 WCharType = UnsignedShort;
3365 DoubleAlign = LongLongAlign = 64;
3367 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3368 DescriptionString = IsWinCOFF ? "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"
3369 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-S32";
3371 void getTargetDefines(const LangOptions &Opts,
3372 MacroBuilder &Builder) const override {
3373 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3377 // x86-32 Windows Visual Studio target
3378 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3380 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3381 : WindowsX86_32TargetInfo(Triple) {
3382 LongDoubleWidth = LongDoubleAlign = 64;
3383 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3385 void getTargetDefines(const LangOptions &Opts,
3386 MacroBuilder &Builder) const override {
3387 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3388 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3389 // The value of the following reflects processor type.
3390 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3391 // We lost the original triple, so we use the default.
3392 Builder.defineMacro("_M_IX86", "600");
3395 } // end anonymous namespace
3397 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3398 Builder.defineMacro("__MSVCRT__");
3399 Builder.defineMacro("__MINGW32__");
3401 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports
3402 // __declspec natively under -fms-extensions, but we define a no-op __declspec
3403 // macro anyway for pre-processor compatibility.
3404 if (Opts.MicrosoftExt)
3405 Builder.defineMacro("__declspec", "__declspec");
3407 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3409 if (!Opts.MicrosoftExt) {
3410 // Provide macros for all the calling convention keywords. Provide both
3411 // single and double underscore prefixed variants. These are available on
3412 // x64 as well as x86, even though they have no effect.
3413 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3414 for (const char *CC : CCs) {
3415 std::string GCCSpelling = "__attribute__((__";
3417 GCCSpelling += "__))";
3418 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3419 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3425 // x86-32 MinGW target
3426 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3428 MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3429 : WindowsX86_32TargetInfo(Triple) {}
3430 void getTargetDefines(const LangOptions &Opts,
3431 MacroBuilder &Builder) const override {
3432 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3433 DefineStd(Builder, "WIN32", Opts);
3434 DefineStd(Builder, "WINNT", Opts);
3435 Builder.defineMacro("_X86_");
3436 addMinGWDefines(Opts, Builder);
3439 } // end anonymous namespace
3442 // x86-32 Cygwin target
3443 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3445 CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3446 : X86_32TargetInfo(Triple) {
3447 TLSSupported = false;
3448 WCharType = UnsignedShort;
3449 DoubleAlign = LongLongAlign = 64;
3450 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3452 void getTargetDefines(const LangOptions &Opts,
3453 MacroBuilder &Builder) const override {
3454 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3455 Builder.defineMacro("_X86_");
3456 Builder.defineMacro("__CYGWIN__");
3457 Builder.defineMacro("__CYGWIN32__");
3458 DefineStd(Builder, "unix", Opts);
3460 Builder.defineMacro("_GNU_SOURCE");
3463 } // end anonymous namespace
3466 // x86-32 Haiku target
3467 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3469 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3470 SizeType = UnsignedLong;
3471 IntPtrType = SignedLong;
3472 PtrDiffType = SignedLong;
3473 ProcessIDType = SignedLong;
3474 this->UserLabelPrefix = "";
3475 this->TLSSupported = false;
3477 void getTargetDefines(const LangOptions &Opts,
3478 MacroBuilder &Builder) const override {
3479 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3480 Builder.defineMacro("__INTEL__");
3481 Builder.defineMacro("__HAIKU__");
3484 } // end anonymous namespace
3487 template<typename Target>
3488 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3490 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3491 MacroBuilder &Builder) const override {
3492 // RTEMS defines; list based off of gcc output
3494 Builder.defineMacro("__rtems__");
3495 Builder.defineMacro("__ELF__");
3499 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3500 this->UserLabelPrefix = "";
3502 switch (Triple.getArch()) {
3504 case llvm::Triple::x86:
3505 // this->MCountName = ".mcount";
3507 case llvm::Triple::mips:
3508 case llvm::Triple::mipsel:
3509 case llvm::Triple::ppc:
3510 case llvm::Triple::ppc64:
3511 case llvm::Triple::ppc64le:
3512 // this->MCountName = "_mcount";
3514 case llvm::Triple::arm:
3515 // this->MCountName = "__mcount";
3522 // x86-32 RTEMS target
3523 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3525 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3526 SizeType = UnsignedLong;
3527 IntPtrType = SignedLong;
3528 PtrDiffType = SignedLong;
3529 this->UserLabelPrefix = "";
3531 void getTargetDefines(const LangOptions &Opts,
3532 MacroBuilder &Builder) const override {
3533 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3534 Builder.defineMacro("__INTEL__");
3535 Builder.defineMacro("__rtems__");
3538 } // end anonymous namespace
3541 // x86-64 generic target
3542 class X86_64TargetInfo : public X86TargetInfo {
3544 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3545 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3546 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3547 LongDoubleWidth = 128;
3548 LongDoubleAlign = 128;
3549 LargeArrayMinWidth = 128;
3550 LargeArrayAlign = 128;
3551 SuitableAlign = 128;
3552 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
3553 PtrDiffType = IsX32 ? SignedInt : SignedLong;
3554 IntPtrType = IsX32 ? SignedInt : SignedLong;
3555 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
3556 Int64Type = IsX32 ? SignedLongLong : SignedLong;
3559 // Pointers are 32-bit in x32.
3560 DescriptionString = (IsX32)
3561 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3562 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3564 // Use fpret only for long double.
3565 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3567 // Use fp2ret for _Complex long double.
3568 ComplexLongDoubleUsesFP2Ret = true;
3570 // x86-64 has atomics up to 16 bytes.
3571 MaxAtomicPromoteWidth = 128;
3572 MaxAtomicInlineWidth = 128;
3574 BuiltinVaListKind getBuiltinVaListKind() const override {
3575 return TargetInfo::X86_64ABIBuiltinVaList;
3578 int getEHDataRegisterNumber(unsigned RegNo) const override {
3579 if (RegNo == 0) return 0;
3580 if (RegNo == 1) return 1;
3584 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3585 return (CC == CC_C ||
3586 CC == CC_X86VectorCall ||
3587 CC == CC_IntelOclBicc ||
3588 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3591 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3595 // for x32 we need it here explicitly
3596 bool hasInt128Type() const override { return true; }
3598 } // end anonymous namespace
3601 // x86-64 Windows target
3602 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3604 WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3605 : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3606 WCharType = UnsignedShort;
3607 LongWidth = LongAlign = 32;
3608 DoubleAlign = LongLongAlign = 64;
3609 IntMaxType = SignedLongLong;
3610 Int64Type = SignedLongLong;
3611 SizeType = UnsignedLongLong;
3612 PtrDiffType = SignedLongLong;
3613 IntPtrType = SignedLongLong;
3614 this->UserLabelPrefix = "";
3616 void getTargetDefines(const LangOptions &Opts,
3617 MacroBuilder &Builder) const override {
3618 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3619 Builder.defineMacro("_WIN64");
3621 BuiltinVaListKind getBuiltinVaListKind() const override {
3622 return TargetInfo::CharPtrBuiltinVaList;
3624 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3625 return (CC == CC_C ||
3626 CC == CC_X86VectorCall ||
3627 CC == CC_IntelOclBicc ||
3628 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
3631 } // end anonymous namespace
3634 // x86-64 Windows Visual Studio target
3635 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3637 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3638 : WindowsX86_64TargetInfo(Triple) {
3639 LongDoubleWidth = LongDoubleAlign = 64;
3640 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3642 void getTargetDefines(const LangOptions &Opts,
3643 MacroBuilder &Builder) const override {
3644 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3645 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3646 Builder.defineMacro("_M_X64");
3647 Builder.defineMacro("_M_AMD64");
3650 } // end anonymous namespace
3653 // x86-64 MinGW target
3654 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3656 MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3657 : WindowsX86_64TargetInfo(Triple) {}
3658 void getTargetDefines(const LangOptions &Opts,
3659 MacroBuilder &Builder) const override {
3660 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3661 DefineStd(Builder, "WIN64", Opts);
3662 Builder.defineMacro("__MINGW64__");
3663 addMinGWDefines(Opts, Builder);
3665 // GCC defines this macro when it is using __gxx_personality_seh0.
3666 if (!Opts.SjLjExceptions)
3667 Builder.defineMacro("__SEH__");
3670 } // end anonymous namespace
3673 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3675 DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3676 : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3677 Int64Type = SignedLongLong;
3678 MaxVectorAlign = 256;
3679 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3680 llvm::Triple T = llvm::Triple(Triple);
3682 UseSignedCharForObjCBool = false;
3683 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3686 } // end anonymous namespace
3689 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3691 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3692 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3693 IntMaxType = SignedLongLong;
3694 Int64Type = SignedLongLong;
3697 } // end anonymous namespace
3700 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3702 BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3703 : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3704 IntMaxType = SignedLongLong;
3705 Int64Type = SignedLongLong;
3712 class ARMTargetInfo : public TargetInfo {
3713 // Possible FPU choices.
3722 // Possible HWDiv features.
3724 HWDivThumb = (1 << 0),
3728 static bool FPUModeIsVFP(FPUMode Mode) {
3729 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3732 static const TargetInfo::GCCRegAlias GCCRegAliases[];
3733 static const char * const GCCRegNames[];
3735 std::string ABI, CPU;
3745 unsigned IsAAPCS : 1;
3746 unsigned IsThumb : 1;
3749 // Initialized via features.
3750 unsigned SoftFloat : 1;
3751 unsigned SoftFloatABI : 1;
3754 unsigned Crypto : 1;
3756 // ACLE 6.5.1 Hardware floating point
3758 HW_FP_HP = (1 << 1), /// half (16-bit)
3759 HW_FP_SP = (1 << 2), /// single (32-bit)
3760 HW_FP_DP = (1 << 3), /// double (64-bit)
3764 static const Builtin::Info BuiltinInfo[];
3766 static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3767 StringRef ArchName = T.getArchName();
3768 if (T.getArch() == llvm::Triple::arm ||
3769 T.getArch() == llvm::Triple::armeb) {
3770 StringRef VersionStr;
3771 if (ArchName.startswith("armv"))
3772 VersionStr = ArchName.substr(4, 1);
3773 else if (ArchName.startswith("armebv"))
3774 VersionStr = ArchName.substr(6, 1);
3778 if (VersionStr.getAsInteger(10, Version))
3780 return Version >= 6;
3782 assert(T.getArch() == llvm::Triple::thumb ||
3783 T.getArch() == llvm::Triple::thumbeb);
3784 StringRef VersionStr;
3785 if (ArchName.startswith("thumbv"))
3786 VersionStr = ArchName.substr(6, 1);
3787 else if (ArchName.startswith("thumbebv"))
3788 VersionStr = ArchName.substr(8, 1);
3792 if (VersionStr.getAsInteger(10, Version))
3794 return Version >= 7;
3797 void setABIAAPCS() {
3800 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
3801 const llvm::Triple &T = getTriple();
3803 // size_t is unsigned long on MachO-derived environments and NetBSD.
3804 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD)
3805 SizeType = UnsignedLong;
3807 SizeType = UnsignedInt;
3809 switch (T.getOS()) {
3810 case llvm::Triple::NetBSD:
3811 WCharType = SignedInt;
3813 case llvm::Triple::Win32:
3814 WCharType = UnsignedShort;
3816 case llvm::Triple::Linux:
3818 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3819 WCharType = UnsignedInt;
3823 UseBitFieldTypeAlignment = true;
3825 ZeroLengthBitfieldBoundary = 0;
3827 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3828 // so set preferred for small types to 32.
3829 if (T.isOSBinFormatMachO()) {
3831 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3832 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3833 } else if (T.isOSWindows()) {
3834 // FIXME: this is invalid for WindowsCE
3835 assert(!BigEndian && "Windows on ARM does not support big endian");
3836 DescriptionString = "e"
3846 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3847 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3850 // FIXME: Enumerated types are variable width in straight AAPCS.
3854 const llvm::Triple &T = getTriple();
3858 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3860 // size_t is unsigned int on FreeBSD.
3861 if (T.getOS() == llvm::Triple::FreeBSD)
3862 SizeType = UnsignedInt;
3864 SizeType = UnsignedLong;
3866 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3867 WCharType = SignedInt;
3869 // Do not respect the alignment of bit-field types when laying out
3870 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3871 UseBitFieldTypeAlignment = false;
3873 /// gcc forces the alignment to 4 bytes, regardless of the type of the
3874 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
3876 ZeroLengthBitfieldBoundary = 32;
3878 if (T.isOSBinFormatMachO())
3881 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3882 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3886 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3887 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3889 // FIXME: Override "preferred align" for double and long long.
3893 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
3894 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
3895 IsAAPCS(true), HW_FP(0) {
3896 BigEndian = IsBigEndian;
3898 switch (getTriple().getOS()) {
3899 case llvm::Triple::NetBSD:
3900 PtrDiffType = SignedLong;
3903 PtrDiffType = SignedInt;
3907 // {} in inline assembly are neon specifiers, not assembly variant
3909 NoAsmVariants = true;
3911 // FIXME: Should we just treat this as a feature?
3912 IsThumb = getTriple().getArchName().startswith("thumb");
3914 // FIXME: This duplicates code from the driver that sets the -target-abi
3915 // option - this code is used if -target-abi isn't passed and should
3916 // be unified in some way.
3917 if (Triple.isOSBinFormatMachO()) {
3918 // The backend is hardwired to assume AAPCS for M-class processors, ensure
3919 // the frontend matches that.
3920 if (Triple.getEnvironment() == llvm::Triple::EABI ||
3921 Triple.getOS() == llvm::Triple::UnknownOS ||
3922 StringRef(CPU).startswith("cortex-m")) {
3927 } else if (Triple.isOSWindows()) {
3928 // FIXME: this is invalid for WindowsCE
3931 // Select the default based on the platform.
3932 switch (Triple.getEnvironment()) {
3933 case llvm::Triple::Android:
3934 case llvm::Triple::GNUEABI:
3935 case llvm::Triple::GNUEABIHF:
3936 setABI("aapcs-linux");
3938 case llvm::Triple::EABIHF:
3939 case llvm::Triple::EABI:
3942 case llvm::Triple::GNU:
3946 if (Triple.getOS() == llvm::Triple::NetBSD)
3954 // ARM targets default to using the ARM C++ ABI.
3955 TheCXXABI.set(TargetCXXABI::GenericARM);
3957 // ARM has atomics up to 8 bytes
3958 MaxAtomicPromoteWidth = 64;
3959 if (shouldUseInlineAtomic(getTriple()))
3960 MaxAtomicInlineWidth = 64;
3962 // Do force alignment of members that follow zero length bitfields. If
3963 // the alignment of the zero-length bitfield is greater than the member
3964 // that follows it, `bar', `bar' will be aligned as the type of the
3965 // zero length bitfield.
3966 UseZeroLengthBitfieldAlignment = true;
3968 StringRef getABI() const override { return ABI; }
3969 bool setABI(const std::string &Name) override {
3972 // The defaults (above) are for AAPCS, check if we need to change them.
3974 // FIXME: We need support for -meabi... we could just mangle it into the
3976 if (Name == "apcs-gnu") {
3980 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
3987 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
3988 StringRef ArchName = getTriple().getArchName();
3989 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3990 Features["vfp2"] = true;
3991 else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
3992 Features["vfp3"] = true;
3993 Features["neon"] = true;
3995 else if (CPU == "cortex-a5") {
3996 Features["vfp4"] = true;
3997 Features["neon"] = true;
3998 } else if (CPU == "swift" || CPU == "cortex-a7" ||
3999 CPU == "cortex-a12" || CPU == "cortex-a15" ||
4000 CPU == "cortex-a17" || CPU == "krait") {
4001 Features["vfp4"] = true;
4002 Features["neon"] = true;
4003 Features["hwdiv"] = true;
4004 Features["hwdiv-arm"] = true;
4005 } else if (CPU == "cyclone") {
4006 Features["v8fp"] = true;
4007 Features["neon"] = true;
4008 Features["hwdiv"] = true;
4009 Features["hwdiv-arm"] = true;
4010 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
4011 Features["fp-armv8"] = true;
4012 Features["neon"] = true;
4013 Features["hwdiv"] = true;
4014 Features["hwdiv-arm"] = true;
4015 Features["crc"] = true;
4016 Features["crypto"] = true;
4017 } else if (CPU == "cortex-r5" ||
4018 // Enable the hwdiv extension for all v8a AArch32 cores by
4020 ArchName == "armv8a" || ArchName == "armv8" ||
4021 ArchName == "armebv8a" || ArchName == "armebv8" ||
4022 ArchName == "thumbv8a" || ArchName == "thumbv8" ||
4023 ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
4024 Features["hwdiv"] = true;
4025 Features["hwdiv-arm"] = true;
4026 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7") {
4027 Features["hwdiv"] = true;
4031 bool handleTargetFeatures(std::vector<std::string> &Features,
4032 DiagnosticsEngine &Diags) override {
4036 SoftFloat = SoftFloatABI = false;
4039 for (const auto &Feature : Features) {
4040 if (Feature == "+soft-float") {
4042 } else if (Feature == "+soft-float-abi") {
4043 SoftFloatABI = true;
4044 } else if (Feature == "+vfp2") {
4046 HW_FP = HW_FP_SP | HW_FP_DP;
4047 } else if (Feature == "+vfp3") {
4049 HW_FP = HW_FP_SP | HW_FP_DP;
4050 } else if (Feature == "+vfp4") {
4052 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4053 } else if (Feature == "+fp-armv8") {
4055 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4056 } else if (Feature == "+neon") {
4058 HW_FP = HW_FP_SP | HW_FP_DP;
4059 } else if (Feature == "+hwdiv") {
4060 HWDiv |= HWDivThumb;
4061 } else if (Feature == "+hwdiv-arm") {
4063 } else if (Feature == "+crc") {
4065 } else if (Feature == "+crypto") {
4067 } else if (Feature == "+fp-only-sp") {
4072 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4073 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4077 if (FPMath == FP_Neon)
4078 Features.push_back("+neonfp");
4079 else if (FPMath == FP_VFP)
4080 Features.push_back("-neonfp");
4082 // Remove front-end specific options which the backend handles differently.
4083 const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" };
4084 for (const auto &FEFeature : FrontEndFeatures) {
4085 auto Feature = std::find(Features.begin(), Features.end(), FEFeature);
4086 if (Feature != Features.end())
4087 Features.erase(Feature);
4093 bool hasFeature(StringRef Feature) const override {
4094 return llvm::StringSwitch<bool>(Feature)
4096 .Case("softfloat", SoftFloat)
4097 .Case("thumb", IsThumb)
4098 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4099 .Case("hwdiv", HWDiv & HWDivThumb)
4100 .Case("hwdiv-arm", HWDiv & HWDivARM)
4103 // FIXME: Should we actually have some table instead of these switches?
4104 static const char *getCPUDefineSuffix(StringRef Name) {
4105 return llvm::StringSwitch<const char *>(Name)
4106 .Cases("arm8", "arm810", "4")
4107 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110",
4109 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
4110 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
4111 .Case("ep9312", "4T")
4112 .Cases("arm10tdmi", "arm1020t", "5T")
4113 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
4114 .Case("arm926ej-s", "5TEJ")
4115 .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
4116 .Cases("xscale", "iwmmxt", "5TE")
4117 .Case("arm1136j-s", "6J")
4118 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
4119 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
4120 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
4121 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
4122 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4124 .Cases("cortex-r4", "cortex-r5", "7R")
4125 .Case("swift", "7S")
4126 .Case("cyclone", "8A")
4127 .Case("cortex-m3", "7M")
4128 .Cases("cortex-m4", "cortex-m7", "7EM")
4129 .Case("cortex-m0", "6M")
4130 .Cases("cortex-a53", "cortex-a57", "8A")
4133 static const char *getCPUProfile(StringRef Name) {
4134 return llvm::StringSwitch<const char *>(Name)
4135 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
4136 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4138 .Cases("cortex-a53", "cortex-a57", "A")
4139 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m7", "M")
4140 .Cases("cortex-r4", "cortex-r5", "R")
4143 bool setCPU(const std::string &Name) override {
4144 if (!getCPUDefineSuffix(Name))
4147 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4148 StringRef Profile = getCPUProfile(Name);
4149 if (Profile == "M" && MaxAtomicInlineWidth) {
4150 MaxAtomicPromoteWidth = 32;
4151 MaxAtomicInlineWidth = 32;
4157 bool setFPMath(StringRef Name) override;
4158 bool supportsThumb(StringRef ArchName, StringRef CPUArch,
4159 unsigned CPUArchVer) const {
4160 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
4161 (CPUArch.find('M') != StringRef::npos);
4163 bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
4164 unsigned CPUArchVer) const {
4165 // We check both CPUArchVer and ArchName because when only triple is
4166 // specified, the default CPU is arm1136j-s.
4167 return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
4168 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
4170 void getTargetDefines(const LangOptions &Opts,
4171 MacroBuilder &Builder) const override {
4172 // Target identification.
4173 Builder.defineMacro("__arm");
4174 Builder.defineMacro("__arm__");
4176 // Target properties.
4177 Builder.defineMacro("__REGISTER_PREFIX__", "");
4179 StringRef CPUArch = getCPUDefineSuffix(CPU);
4180 unsigned int CPUArchVer;
4181 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
4182 llvm_unreachable("Invalid char for architecture version number");
4183 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
4185 // ACLE 6.4.1 ARM/Thumb instruction set architecture
4186 StringRef CPUProfile = getCPUProfile(CPU);
4187 StringRef ArchName = getTriple().getArchName();
4189 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4190 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
4191 if (CPUArch[0] >= '8') {
4192 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4193 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4196 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
4197 // is not defined for the M-profile.
4198 // NOTE that the deffault profile is assumed to be 'A'
4199 if (CPUProfile.empty() || CPUProfile != "M")
4200 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4202 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4203 // Thumb ISA (including v6-M). It is set to 2 if the core supports the
4204 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4205 if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4206 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4207 else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
4208 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4210 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4211 // instruction set such as ARM or Thumb.
4212 Builder.defineMacro("__ARM_32BIT_STATE", "1");
4214 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4216 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4217 if (!CPUProfile.empty())
4218 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4220 // ACLE 6.5.1 Hardware Floating Point
4222 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4225 Builder.defineMacro("__ARM_ACLE", "200");
4227 // Subtarget options.
4229 // FIXME: It's more complicated than this and we don't really support
4231 // Windows on ARM does not "support" interworking
4232 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
4233 Builder.defineMacro("__THUMB_INTERWORK__");
4235 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4236 // Embedded targets on Darwin follow AAPCS, but not EABI.
4237 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4238 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4239 Builder.defineMacro("__ARM_EABI__");
4240 Builder.defineMacro("__ARM_PCS", "1");
4242 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4243 Builder.defineMacro("__ARM_PCS_VFP", "1");
4247 Builder.defineMacro("__SOFTFP__");
4249 if (CPU == "xscale")
4250 Builder.defineMacro("__XSCALE__");
4253 Builder.defineMacro("__THUMBEL__");
4254 Builder.defineMacro("__thumb__");
4255 if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4256 Builder.defineMacro("__thumb2__");
4258 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4259 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4261 // Note, this is always on in gcc, even though it doesn't make sense.
4262 Builder.defineMacro("__APCS_32__");
4264 if (FPUModeIsVFP((FPUMode) FPU)) {
4265 Builder.defineMacro("__VFP_FP__");
4267 Builder.defineMacro("__ARM_VFPV2__");
4269 Builder.defineMacro("__ARM_VFPV3__");
4271 Builder.defineMacro("__ARM_VFPV4__");
4274 // This only gets set when Neon instructions are actually available, unlike
4275 // the VFP define, hence the soft float and arch check. This is subtly
4276 // different from gcc, we follow the intent which was that it should be set
4277 // when Neon instructions are actually available.
4278 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
4279 Builder.defineMacro("__ARM_NEON");
4280 Builder.defineMacro("__ARM_NEON__");
4283 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4284 Opts.ShortWChar ? "2" : "4");
4286 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4287 Opts.ShortEnums ? "1" : "4");
4290 Builder.defineMacro("__ARM_FEATURE_CRC32");
4293 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4295 if (CPUArchVer >= 6 && CPUArch != "6M") {
4296 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4297 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4298 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4299 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4302 bool is5EOrAbove = (CPUArchVer >= 6 ||
4304 CPUArch.find('E') != StringRef::npos));
4305 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer));
4306 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM"))
4307 Builder.defineMacro("__ARM_FEATURE_DSP");
4309 void getTargetBuiltins(const Builtin::Info *&Records,
4310 unsigned &NumRecords) const override {
4311 Records = BuiltinInfo;
4312 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4314 bool isCLZForZeroUndef() const override { return false; }
4315 BuiltinVaListKind getBuiltinVaListKind() const override {
4316 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4318 void getGCCRegNames(const char * const *&Names,
4319 unsigned &NumNames) const override;
4320 void getGCCRegAliases(const GCCRegAlias *&Aliases,
4321 unsigned &NumAliases) const override;
4322 bool validateAsmConstraint(const char *&Name,
4323 TargetInfo::ConstraintInfo &Info) const override {
4328 case 'w': // VFP Floating point register single precision
4329 case 'P': // VFP Floating point register double precision
4330 Info.setAllowsRegister();
4339 case 'Q': // A memory address that is a single base register.
4340 Info.setAllowsMemory();
4342 case 'U': // a memory reference...
4344 case 'q': // ...ARMV4 ldrsb
4345 case 'v': // ...VFP load/store (reg+constant offset)
4346 case 'y': // ...iWMMXt load/store
4347 case 't': // address valid for load/store opaque types wider
4349 case 'n': // valid address for Neon doubleword vector load/store
4350 case 'm': // valid address for Neon element and structure load/store
4351 case 's': // valid address for non-offset loads/stores of quad-word
4352 // values in four ARM registers
4353 Info.setAllowsMemory();
4360 std::string convertConstraint(const char *&Constraint) const override {
4362 switch (*Constraint) {
4363 case 'U': // Two-character constraint; add "^" hint for later parsing.
4364 R = std::string("^") + std::string(Constraint, 2);
4367 case 'p': // 'p' should be translated to 'r' by default.
4368 R = std::string("r");
4371 return std::string(1, *Constraint);
4376 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4377 std::string &SuggestedModifier) const override {
4378 bool isOutput = (Constraint[0] == '=');
4379 bool isInOut = (Constraint[0] == '+');
4381 // Strip off constraint modifiers.
4382 while (Constraint[0] == '=' ||
4383 Constraint[0] == '+' ||
4384 Constraint[0] == '&')
4385 Constraint = Constraint.substr(1);
4387 switch (Constraint[0]) {
4392 return (isInOut || isOutput || Size <= 64);
4394 // A register of size 32 cannot fit a vector type.
4402 const char *getClobbers() const override {
4403 // FIXME: Is this really right?
4407 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4408 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4411 int getEHDataRegisterNumber(unsigned RegNo) const override {
4412 if (RegNo == 0) return 0;
4413 if (RegNo == 1) return 1;
4418 bool ARMTargetInfo::setFPMath(StringRef Name) {
4419 if (Name == "neon") {
4422 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4430 const char * const ARMTargetInfo::GCCRegNames[] = {
4431 // Integer registers
4432 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4433 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4436 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4437 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4438 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4439 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4442 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4443 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4444 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4445 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4448 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4449 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4452 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4453 unsigned &NumNames) const {
4454 Names = GCCRegNames;
4455 NumNames = llvm::array_lengthof(GCCRegNames);
4458 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4468 { { "v6", "rfp" }, "r9" },
4469 { { "sl" }, "r10" },
4470 { { "fp" }, "r11" },
4471 { { "ip" }, "r12" },
4472 { { "r13" }, "sp" },
4473 { { "r14" }, "lr" },
4474 { { "r15" }, "pc" },
4475 // The S, D and Q registers overlap, but aren't really aliases; we
4476 // don't want to substitute one of these for a different-sized one.
4479 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4480 unsigned &NumAliases) const {
4481 Aliases = GCCRegAliases;
4482 NumAliases = llvm::array_lengthof(GCCRegAliases);
4485 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4486 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4487 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4489 #include "clang/Basic/BuiltinsNEON.def"
4491 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4492 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4493 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4495 #include "clang/Basic/BuiltinsARM.def"
4498 class ARMleTargetInfo : public ARMTargetInfo {
4500 ARMleTargetInfo(const llvm::Triple &Triple)
4501 : ARMTargetInfo(Triple, false) { }
4502 virtual void getTargetDefines(const LangOptions &Opts,
4503 MacroBuilder &Builder) const {
4504 Builder.defineMacro("__ARMEL__");
4505 ARMTargetInfo::getTargetDefines(Opts, Builder);
4509 class ARMbeTargetInfo : public ARMTargetInfo {
4511 ARMbeTargetInfo(const llvm::Triple &Triple)
4512 : ARMTargetInfo(Triple, true) { }
4513 virtual void getTargetDefines(const LangOptions &Opts,
4514 MacroBuilder &Builder) const {
4515 Builder.defineMacro("__ARMEB__");
4516 Builder.defineMacro("__ARM_BIG_ENDIAN");
4517 ARMTargetInfo::getTargetDefines(Opts, Builder);
4520 } // end anonymous namespace.
4523 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4524 const llvm::Triple Triple;
4526 WindowsARMTargetInfo(const llvm::Triple &Triple)
4527 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4528 TLSSupported = false;
4529 WCharType = UnsignedShort;
4530 SizeType = UnsignedInt;
4531 UserLabelPrefix = "";
4533 void getVisualStudioDefines(const LangOptions &Opts,
4534 MacroBuilder &Builder) const {
4535 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4537 // FIXME: this is invalid for WindowsCE
4538 Builder.defineMacro("_M_ARM_NT", "1");
4539 Builder.defineMacro("_M_ARMT", "_M_ARM");
4540 Builder.defineMacro("_M_THUMB", "_M_ARM");
4542 assert((Triple.getArch() == llvm::Triple::arm ||
4543 Triple.getArch() == llvm::Triple::thumb) &&
4544 "invalid architecture for Windows ARM target info");
4545 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4546 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4548 // TODO map the complete set of values
4549 // 31: VFPv3 40: VFPv4
4550 Builder.defineMacro("_M_ARM_FP", "31");
4552 BuiltinVaListKind getBuiltinVaListKind() const override {
4553 return TargetInfo::CharPtrBuiltinVaList;
4557 // Windows ARM + Itanium C++ ABI Target
4558 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4560 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4561 : WindowsARMTargetInfo(Triple) {
4562 TheCXXABI.set(TargetCXXABI::GenericARM);
4565 void getTargetDefines(const LangOptions &Opts,
4566 MacroBuilder &Builder) const override {
4567 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4569 if (Opts.MSVCCompat)
4570 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4574 // Windows ARM, MS (C++) ABI
4575 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4577 MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4578 : WindowsARMTargetInfo(Triple) {
4579 TheCXXABI.set(TargetCXXABI::Microsoft);
4582 void getTargetDefines(const LangOptions &Opts,
4583 MacroBuilder &Builder) const override {
4584 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4585 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4592 class DarwinARMTargetInfo :
4593 public DarwinTargetInfo<ARMleTargetInfo> {
4595 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4596 MacroBuilder &Builder) const override {
4597 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4601 DarwinARMTargetInfo(const llvm::Triple &Triple)
4602 : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4603 HasAlignMac68kSupport = true;
4604 // iOS always has 64-bit atomic instructions.
4605 // FIXME: This should be based off of the target features in
4607 MaxAtomicInlineWidth = 64;
4609 // Darwin on iOS uses a variant of the ARM C++ ABI.
4610 TheCXXABI.set(TargetCXXABI::iOS);
4613 } // end anonymous namespace.
4617 class AArch64TargetInfo : public TargetInfo {
4618 virtual void setDescriptionString() = 0;
4619 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4620 static const char *const GCCRegNames[];
4631 static const Builtin::Info BuiltinInfo[];
4636 AArch64TargetInfo(const llvm::Triple &Triple)
4637 : TargetInfo(Triple), ABI("aapcs") {
4639 if (getTriple().getOS() == llvm::Triple::NetBSD) {
4640 WCharType = SignedInt;
4642 // NetBSD apparently prefers consistency across ARM targets to consistency
4643 // across 64-bit targets.
4644 Int64Type = SignedLongLong;
4645 IntMaxType = SignedLongLong;
4647 WCharType = UnsignedInt;
4648 Int64Type = SignedLong;
4649 IntMaxType = SignedLong;
4652 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4653 MaxVectorAlign = 128;
4655 MaxAtomicInlineWidth = 128;
4656 MaxAtomicPromoteWidth = 128;
4658 LongDoubleWidth = LongDoubleAlign = 128;
4659 LongDoubleFormat = &llvm::APFloat::IEEEquad;
4661 // {} in inline assembly are neon specifiers, not assembly variant
4663 NoAsmVariants = true;
4665 // AArch64 targets default to using the ARM C++ ABI.
4666 TheCXXABI.set(TargetCXXABI::GenericAArch64);
4669 StringRef getABI() const override { return ABI; }
4670 bool setABI(const std::string &Name) override {
4671 if (Name != "aapcs" && Name != "darwinpcs")
4678 bool setCPU(const std::string &Name) override {
4679 bool CPUKnown = llvm::StringSwitch<bool>(Name)
4680 .Case("generic", true)
4681 .Cases("cortex-a53", "cortex-a57", true)
4682 .Case("cyclone", true)
4687 virtual void getTargetDefines(const LangOptions &Opts,
4688 MacroBuilder &Builder) const override {
4689 // Target identification.
4690 Builder.defineMacro("__aarch64__");
4692 // Target properties.
4693 Builder.defineMacro("_LP64");
4694 Builder.defineMacro("__LP64__");
4696 // ACLE predefines. Many can only have one possible value on v8 AArch64.
4697 Builder.defineMacro("__ARM_ACLE", "200");
4698 Builder.defineMacro("__ARM_ARCH", "8");
4699 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4701 Builder.defineMacro("__ARM_64BIT_STATE");
4702 Builder.defineMacro("__ARM_PCS_AAPCS64");
4703 Builder.defineMacro("__ARM_ARCH_ISA_A64");
4705 Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4706 Builder.defineMacro("__ARM_FEATURE_CLZ");
4707 Builder.defineMacro("__ARM_FEATURE_FMA");
4708 Builder.defineMacro("__ARM_FEATURE_DIV");
4709 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
4710 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
4711 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4712 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4714 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4716 // 0xe implies support for half, single and double precision operations.
4717 Builder.defineMacro("__ARM_FP", "0xe");
4719 // PCS specifies this for SysV variants, which is all we support. Other ABIs
4720 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4721 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4723 if (Opts.FastMath || Opts.FiniteMathOnly)
4724 Builder.defineMacro("__ARM_FP_FAST");
4726 if (Opts.C99 && !Opts.Freestanding)
4727 Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4729 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4731 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4732 Opts.ShortEnums ? "1" : "4");
4734 if (FPU == NeonMode) {
4735 Builder.defineMacro("__ARM_NEON");
4736 // 64-bit NEON supports half, single and double precision operations.
4737 Builder.defineMacro("__ARM_NEON_FP", "0xe");
4741 Builder.defineMacro("__ARM_FEATURE_CRC32");
4744 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4747 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4748 unsigned &NumRecords) const override {
4749 Records = BuiltinInfo;
4750 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
4753 bool hasFeature(StringRef Feature) const override {
4754 return Feature == "aarch64" ||
4755 Feature == "arm64" ||
4756 (Feature == "neon" && FPU == NeonMode);
4759 bool handleTargetFeatures(std::vector<std::string> &Features,
4760 DiagnosticsEngine &Diags) override {
4764 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
4765 if (Features[i] == "+neon")
4767 if (Features[i] == "+crc")
4769 if (Features[i] == "+crypto")
4773 setDescriptionString();
4778 bool isCLZForZeroUndef() const override { return false; }
4780 BuiltinVaListKind getBuiltinVaListKind() const override {
4781 return TargetInfo::AArch64ABIBuiltinVaList;
4784 virtual void getGCCRegNames(const char *const *&Names,
4785 unsigned &NumNames) const override;
4786 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4787 unsigned &NumAliases) const override;
4790 validateAsmConstraint(const char *&Name,
4791 TargetInfo::ConstraintInfo &Info) const override {
4795 case 'w': // Floating point and SIMD registers (V0-V31)
4796 Info.setAllowsRegister();
4798 case 'I': // Constant that can be used with an ADD instruction
4799 case 'J': // Constant that can be used with a SUB instruction
4800 case 'K': // Constant that can be used with a 32-bit logical instruction
4801 case 'L': // Constant that can be used with a 64-bit logical instruction
4802 case 'M': // Constant that can be used as a 32-bit MOV immediate
4803 case 'N': // Constant that can be used as a 64-bit MOV immediate
4804 case 'Y': // Floating point constant zero
4805 case 'Z': // Integer constant zero
4807 case 'Q': // A memory reference with base register and no offset
4808 Info.setAllowsMemory();
4810 case 'S': // A symbolic address
4811 Info.setAllowsRegister();
4814 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
4815 // Utf: A memory address suitable for ldp/stp in TF mode.
4816 // Usa: An absolute symbolic address.
4817 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
4818 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
4819 case 'z': // Zero register, wzr or xzr
4820 Info.setAllowsRegister();
4822 case 'x': // Floating point and SIMD registers (V0-V15)
4823 Info.setAllowsRegister();
4830 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4831 std::string &SuggestedModifier) const override {
4832 // Strip off constraint modifiers.
4833 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
4834 Constraint = Constraint.substr(1);
4836 switch (Constraint[0]) {
4844 // For now assume that the person knows what they're
4845 // doing with the modifier.
4848 // By default an 'r' constraint will be in the 'x'
4853 SuggestedModifier = "w";
4860 const char *getClobbers() const override { return ""; }
4862 int getEHDataRegisterNumber(unsigned RegNo) const override {
4871 const char *const AArch64TargetInfo::GCCRegNames[] = {
4872 // 32-bit Integer registers
4873 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
4874 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
4875 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
4877 // 64-bit Integer registers
4878 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
4879 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
4880 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
4882 // 32-bit floating point regsisters
4883 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
4884 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
4885 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4887 // 64-bit floating point regsisters
4888 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
4889 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
4890 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4893 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
4894 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
4895 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
4898 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
4899 unsigned &NumNames) const {
4900 Names = GCCRegNames;
4901 NumNames = llvm::array_lengthof(GCCRegNames);
4904 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
4905 { { "w31" }, "wsp" },
4906 { { "x29" }, "fp" },
4907 { { "x30" }, "lr" },
4908 { { "x31" }, "sp" },
4909 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
4910 // don't want to substitute one of these for a different-sized one.
4913 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4914 unsigned &NumAliases) const {
4915 Aliases = GCCRegAliases;
4916 NumAliases = llvm::array_lengthof(GCCRegAliases);
4919 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
4920 #define BUILTIN(ID, TYPE, ATTRS) \
4921 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4922 #include "clang/Basic/BuiltinsNEON.def"
4924 #define BUILTIN(ID, TYPE, ATTRS) \
4925 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4926 #include "clang/Basic/BuiltinsAArch64.def"
4929 class AArch64leTargetInfo : public AArch64TargetInfo {
4930 void setDescriptionString() override {
4931 if (getTriple().isOSBinFormatMachO())
4932 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
4934 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
4938 AArch64leTargetInfo(const llvm::Triple &Triple)
4939 : AArch64TargetInfo(Triple) {
4942 void getTargetDefines(const LangOptions &Opts,
4943 MacroBuilder &Builder) const override {
4944 Builder.defineMacro("__AARCH64EL__");
4945 AArch64TargetInfo::getTargetDefines(Opts, Builder);
4949 class AArch64beTargetInfo : public AArch64TargetInfo {
4950 void setDescriptionString() override {
4951 assert(!getTriple().isOSBinFormatMachO());
4952 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
4956 AArch64beTargetInfo(const llvm::Triple &Triple)
4957 : AArch64TargetInfo(Triple) { }
4958 void getTargetDefines(const LangOptions &Opts,
4959 MacroBuilder &Builder) const override {
4960 Builder.defineMacro("__AARCH64EB__");
4961 Builder.defineMacro("__AARCH_BIG_ENDIAN");
4962 Builder.defineMacro("__ARM_BIG_ENDIAN");
4963 AArch64TargetInfo::getTargetDefines(Opts, Builder);
4966 } // end anonymous namespace.
4969 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
4971 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4972 MacroBuilder &Builder) const override {
4973 Builder.defineMacro("__AARCH64_SIMD__");
4974 Builder.defineMacro("__ARM64_ARCH_8__");
4975 Builder.defineMacro("__ARM_NEON__");
4976 Builder.defineMacro("__LITTLE_ENDIAN__");
4977 Builder.defineMacro("__REGISTER_PREFIX__", "");
4978 Builder.defineMacro("__arm64", "1");
4979 Builder.defineMacro("__arm64__", "1");
4981 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4985 DarwinAArch64TargetInfo(const llvm::Triple &Triple)
4986 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
4987 Int64Type = SignedLongLong;
4988 WCharType = SignedInt;
4989 UseSignedCharForObjCBool = false;
4991 LongDoubleWidth = LongDoubleAlign = 64;
4992 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4994 TheCXXABI.set(TargetCXXABI::iOS64);
4997 BuiltinVaListKind getBuiltinVaListKind() const override {
4998 return TargetInfo::CharPtrBuiltinVaList;
5001 } // end anonymous namespace
5004 // Hexagon abstract base class
5005 class HexagonTargetInfo : public TargetInfo {
5006 static const Builtin::Info BuiltinInfo[];
5007 static const char * const GCCRegNames[];
5008 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5011 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5013 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
5015 // {} in inline assembly are packet specifiers, not assembly variant
5017 NoAsmVariants = true;
5020 void getTargetBuiltins(const Builtin::Info *&Records,
5021 unsigned &NumRecords) const override {
5022 Records = BuiltinInfo;
5023 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
5026 bool validateAsmConstraint(const char *&Name,
5027 TargetInfo::ConstraintInfo &Info) const override {
5031 void getTargetDefines(const LangOptions &Opts,
5032 MacroBuilder &Builder) const override;
5034 bool hasFeature(StringRef Feature) const override {
5035 return Feature == "hexagon";
5038 BuiltinVaListKind getBuiltinVaListKind() const override {
5039 return TargetInfo::CharPtrBuiltinVaList;
5041 void getGCCRegNames(const char * const *&Names,
5042 unsigned &NumNames) const override;
5043 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5044 unsigned &NumAliases) const override;
5045 const char *getClobbers() const override {
5049 static const char *getHexagonCPUSuffix(StringRef Name) {
5050 return llvm::StringSwitch<const char*>(Name)
5051 .Case("hexagonv4", "4")
5052 .Case("hexagonv5", "5")
5056 bool setCPU(const std::string &Name) override {
5057 if (!getHexagonCPUSuffix(Name))
5065 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5066 MacroBuilder &Builder) const {
5067 Builder.defineMacro("qdsp6");
5068 Builder.defineMacro("__qdsp6", "1");
5069 Builder.defineMacro("__qdsp6__", "1");
5071 Builder.defineMacro("hexagon");
5072 Builder.defineMacro("__hexagon", "1");
5073 Builder.defineMacro("__hexagon__", "1");
5075 if(CPU == "hexagonv1") {
5076 Builder.defineMacro("__HEXAGON_V1__");
5077 Builder.defineMacro("__HEXAGON_ARCH__", "1");
5078 if(Opts.HexagonQdsp6Compat) {
5079 Builder.defineMacro("__QDSP6_V1__");
5080 Builder.defineMacro("__QDSP6_ARCH__", "1");
5083 else if(CPU == "hexagonv2") {
5084 Builder.defineMacro("__HEXAGON_V2__");
5085 Builder.defineMacro("__HEXAGON_ARCH__", "2");
5086 if(Opts.HexagonQdsp6Compat) {
5087 Builder.defineMacro("__QDSP6_V2__");
5088 Builder.defineMacro("__QDSP6_ARCH__", "2");
5091 else if(CPU == "hexagonv3") {
5092 Builder.defineMacro("__HEXAGON_V3__");
5093 Builder.defineMacro("__HEXAGON_ARCH__", "3");
5094 if(Opts.HexagonQdsp6Compat) {
5095 Builder.defineMacro("__QDSP6_V3__");
5096 Builder.defineMacro("__QDSP6_ARCH__", "3");
5099 else if(CPU == "hexagonv4") {
5100 Builder.defineMacro("__HEXAGON_V4__");
5101 Builder.defineMacro("__HEXAGON_ARCH__", "4");
5102 if(Opts.HexagonQdsp6Compat) {
5103 Builder.defineMacro("__QDSP6_V4__");
5104 Builder.defineMacro("__QDSP6_ARCH__", "4");
5107 else if(CPU == "hexagonv5") {
5108 Builder.defineMacro("__HEXAGON_V5__");
5109 Builder.defineMacro("__HEXAGON_ARCH__", "5");
5110 if(Opts.HexagonQdsp6Compat) {
5111 Builder.defineMacro("__QDSP6_V5__");
5112 Builder.defineMacro("__QDSP6_ARCH__", "5");
5117 const char * const HexagonTargetInfo::GCCRegNames[] = {
5118 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5119 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5120 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5121 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5122 "p0", "p1", "p2", "p3",
5123 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5126 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
5127 unsigned &NumNames) const {
5128 Names = GCCRegNames;
5129 NumNames = llvm::array_lengthof(GCCRegNames);
5133 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5134 { { "sp" }, "r29" },
5135 { { "fp" }, "r30" },
5136 { { "lr" }, "r31" },
5139 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5140 unsigned &NumAliases) const {
5141 Aliases = GCCRegAliases;
5142 NumAliases = llvm::array_lengthof(GCCRegAliases);
5146 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5147 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5148 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5150 #include "clang/Basic/BuiltinsHexagon.def"
5156 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5157 class SparcTargetInfo : public TargetInfo {
5158 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5159 static const char * const GCCRegNames[];
5162 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
5164 bool handleTargetFeatures(std::vector<std::string> &Features,
5165 DiagnosticsEngine &Diags) override {
5167 for (unsigned i = 0, e = Features.size(); i != e; ++i)
5168 if (Features[i] == "+soft-float")
5172 void getTargetDefines(const LangOptions &Opts,
5173 MacroBuilder &Builder) const override {
5174 DefineStd(Builder, "sparc", Opts);
5175 Builder.defineMacro("__REGISTER_PREFIX__", "");
5178 Builder.defineMacro("SOFT_FLOAT", "1");
5181 bool hasFeature(StringRef Feature) const override {
5182 return llvm::StringSwitch<bool>(Feature)
5183 .Case("softfloat", SoftFloat)
5184 .Case("sparc", true)
5188 void getTargetBuiltins(const Builtin::Info *&Records,
5189 unsigned &NumRecords) const override {
5190 // FIXME: Implement!
5192 BuiltinVaListKind getBuiltinVaListKind() const override {
5193 return TargetInfo::VoidPtrBuiltinVaList;
5195 void getGCCRegNames(const char * const *&Names,
5196 unsigned &NumNames) const override;
5197 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5198 unsigned &NumAliases) const override;
5199 bool validateAsmConstraint(const char *&Name,
5200 TargetInfo::ConstraintInfo &info) const override {
5201 // FIXME: Implement!
5203 case 'I': // Signed 13-bit constant
5205 case 'K': // 32-bit constant with the low 12 bits clear
5206 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5207 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5208 case 'N': // Same as 'K' but zext (required for SIMode)
5209 case 'O': // The constant 4096
5214 const char *getClobbers() const override {
5215 // FIXME: Implement!
5220 const char * const SparcTargetInfo::GCCRegNames[] = {
5221 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5222 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5223 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5224 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5227 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5228 unsigned &NumNames) const {
5229 Names = GCCRegNames;
5230 NumNames = llvm::array_lengthof(GCCRegNames);
5233 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5244 { { "o2" }, "r10" },
5245 { { "o3" }, "r11" },
5246 { { "o4" }, "r12" },
5247 { { "o5" }, "r13" },
5248 { { "o6", "sp" }, "r14" },
5249 { { "o7" }, "r15" },
5250 { { "l0" }, "r16" },
5251 { { "l1" }, "r17" },
5252 { { "l2" }, "r18" },
5253 { { "l3" }, "r19" },
5254 { { "l4" }, "r20" },
5255 { { "l5" }, "r21" },
5256 { { "l6" }, "r22" },
5257 { { "l7" }, "r23" },
5258 { { "i0" }, "r24" },
5259 { { "i1" }, "r25" },
5260 { { "i2" }, "r26" },
5261 { { "i3" }, "r27" },
5262 { { "i4" }, "r28" },
5263 { { "i5" }, "r29" },
5264 { { "i6", "fp" }, "r30" },
5265 { { "i7" }, "r31" },
5268 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5269 unsigned &NumAliases) const {
5270 Aliases = GCCRegAliases;
5271 NumAliases = llvm::array_lengthof(GCCRegAliases);
5274 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
5275 class SparcV8TargetInfo : public SparcTargetInfo {
5277 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5278 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5281 void getTargetDefines(const LangOptions &Opts,
5282 MacroBuilder &Builder) const override {
5283 SparcTargetInfo::getTargetDefines(Opts, Builder);
5284 Builder.defineMacro("__sparcv8");
5288 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5289 class SparcV9TargetInfo : public SparcTargetInfo {
5291 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5292 // FIXME: Support Sparc quad-precision long double?
5293 DescriptionString = "E-m:e-i64:64-n32:64-S128";
5294 // This is an LP64 platform.
5295 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5297 // OpenBSD uses long long for int64_t and intmax_t.
5298 if (getTriple().getOS() == llvm::Triple::OpenBSD)
5299 IntMaxType = SignedLongLong;
5301 IntMaxType = SignedLong;
5302 Int64Type = IntMaxType;
5304 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5305 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5306 LongDoubleWidth = 128;
5307 LongDoubleAlign = 128;
5308 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5309 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5312 void getTargetDefines(const LangOptions &Opts,
5313 MacroBuilder &Builder) const override {
5314 SparcTargetInfo::getTargetDefines(Opts, Builder);
5315 Builder.defineMacro("__sparcv9");
5316 Builder.defineMacro("__arch64__");
5317 // Solaris doesn't need these variants, but the BSDs do.
5318 if (getTriple().getOS() != llvm::Triple::Solaris) {
5319 Builder.defineMacro("__sparc64__");
5320 Builder.defineMacro("__sparc_v9__");
5321 Builder.defineMacro("__sparcv9__");
5325 bool setCPU(const std::string &Name) override {
5326 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5328 .Case("ultrasparc", true)
5329 .Case("ultrasparc3", true)
5330 .Case("niagara", true)
5331 .Case("niagara2", true)
5332 .Case("niagara3", true)
5333 .Case("niagara4", true)
5336 // No need to store the CPU yet. There aren't any CPU-specific
5337 // macros to define.
5342 } // end anonymous namespace.
5345 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
5347 SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
5348 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
5349 SizeType = UnsignedInt;
5350 PtrDiffType = SignedInt;
5353 } // end anonymous namespace.
5356 class SystemZTargetInfo : public TargetInfo {
5357 static const char *const GCCRegNames[];
5360 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5361 TLSSupported = true;
5362 IntWidth = IntAlign = 32;
5363 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5364 PointerWidth = PointerAlign = 64;
5365 LongDoubleWidth = 128;
5366 LongDoubleAlign = 64;
5367 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5368 MinGlobalAlign = 16;
5369 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5370 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5372 void getTargetDefines(const LangOptions &Opts,
5373 MacroBuilder &Builder) const override {
5374 Builder.defineMacro("__s390__");
5375 Builder.defineMacro("__s390x__");
5376 Builder.defineMacro("__zarch__");
5377 Builder.defineMacro("__LONG_DOUBLE_128__");
5379 void getTargetBuiltins(const Builtin::Info *&Records,
5380 unsigned &NumRecords) const override {
5381 // FIXME: Implement.
5386 void getGCCRegNames(const char *const *&Names,
5387 unsigned &NumNames) const override;
5388 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5389 unsigned &NumAliases) const override {
5394 bool validateAsmConstraint(const char *&Name,
5395 TargetInfo::ConstraintInfo &info) const override;
5396 const char *getClobbers() const override {
5397 // FIXME: Is this really right?
5400 BuiltinVaListKind getBuiltinVaListKind() const override {
5401 return TargetInfo::SystemZBuiltinVaList;
5403 bool setCPU(const std::string &Name) override {
5404 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5407 .Case("zEC12", true)
5410 // No need to store the CPU yet. There aren't any CPU-specific
5411 // macros to define.
5416 const char *const SystemZTargetInfo::GCCRegNames[] = {
5417 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5418 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5419 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
5420 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
5423 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5424 unsigned &NumNames) const {
5425 Names = GCCRegNames;
5426 NumNames = llvm::array_lengthof(GCCRegNames);
5429 bool SystemZTargetInfo::
5430 validateAsmConstraint(const char *&Name,
5431 TargetInfo::ConstraintInfo &Info) const {
5436 case 'a': // Address register
5437 case 'd': // Data register (equivalent to 'r')
5438 case 'f': // Floating-point register
5439 Info.setAllowsRegister();
5442 case 'I': // Unsigned 8-bit constant
5443 case 'J': // Unsigned 12-bit constant
5444 case 'K': // Signed 16-bit constant
5445 case 'L': // Signed 20-bit displacement (on all targets we support)
5446 case 'M': // 0x7fffffff
5449 case 'Q': // Memory with base and unsigned 12-bit displacement
5450 case 'R': // Likewise, plus an index
5451 case 'S': // Memory with base and signed 20-bit displacement
5452 case 'T': // Likewise, plus an index
5453 Info.setAllowsMemory();
5460 class MSP430TargetInfo : public TargetInfo {
5461 static const char * const GCCRegNames[];
5463 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5465 TLSSupported = false;
5466 IntWidth = 16; IntAlign = 16;
5467 LongWidth = 32; LongLongWidth = 64;
5468 LongAlign = LongLongAlign = 16;
5469 PointerWidth = 16; PointerAlign = 16;
5471 SizeType = UnsignedInt;
5472 IntMaxType = SignedLongLong;
5473 IntPtrType = SignedInt;
5474 PtrDiffType = SignedInt;
5475 SigAtomicType = SignedLong;
5476 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5478 void getTargetDefines(const LangOptions &Opts,
5479 MacroBuilder &Builder) const override {
5480 Builder.defineMacro("MSP430");
5481 Builder.defineMacro("__MSP430__");
5482 // FIXME: defines for different 'flavours' of MCU
5484 void getTargetBuiltins(const Builtin::Info *&Records,
5485 unsigned &NumRecords) const override {
5486 // FIXME: Implement.
5490 bool hasFeature(StringRef Feature) const override {
5491 return Feature == "msp430";
5493 void getGCCRegNames(const char * const *&Names,
5494 unsigned &NumNames) const override;
5495 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5496 unsigned &NumAliases) const override {
5502 validateAsmConstraint(const char *&Name,
5503 TargetInfo::ConstraintInfo &info) const override {
5506 case 'K': // the constant 1
5507 case 'L': // constant -1^20 .. 1^19
5508 case 'M': // constant 1-4:
5511 // No target constraints for now.
5514 const char *getClobbers() const override {
5515 // FIXME: Is this really right?
5518 BuiltinVaListKind getBuiltinVaListKind() const override {
5520 return TargetInfo::CharPtrBuiltinVaList;
5524 const char * const MSP430TargetInfo::GCCRegNames[] = {
5525 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5526 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5529 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5530 unsigned &NumNames) const {
5531 Names = GCCRegNames;
5532 NumNames = llvm::array_lengthof(GCCRegNames);
5538 // LLVM and Clang cannot be used directly to output native binaries for
5539 // target, but is used to compile C code to llvm bitcode with correct
5540 // type and alignment information.
5542 // TCE uses the llvm bitcode as input and uses it for generating customized
5543 // target processor and program binary. TCE co-design environment is
5544 // publicly available in http://tce.cs.tut.fi
5546 static const unsigned TCEOpenCLAddrSpaceMap[] = {
5549 5, // opencl_constant
5550 // FIXME: generic has to be added to the target
5551 0, // opencl_generic
5557 class TCETargetInfo : public TargetInfo{
5559 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5560 TLSSupported = false;
5562 LongWidth = LongLongWidth = 32;
5565 LongAlign = LongLongAlign = 32;
5568 SizeType = UnsignedInt;
5569 IntMaxType = SignedLong;
5570 IntPtrType = SignedInt;
5571 PtrDiffType = SignedInt;
5576 LongDoubleWidth = 32;
5577 LongDoubleAlign = 32;
5578 FloatFormat = &llvm::APFloat::IEEEsingle;
5579 DoubleFormat = &llvm::APFloat::IEEEsingle;
5580 LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5581 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5582 "-f64:32-v64:32-v128:32-a:0:32-n32";
5583 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5584 UseAddrSpaceMapMangling = true;
5587 void getTargetDefines(const LangOptions &Opts,
5588 MacroBuilder &Builder) const override {
5589 DefineStd(Builder, "tce", Opts);
5590 Builder.defineMacro("__TCE__");
5591 Builder.defineMacro("__TCE_V1__");
5593 bool hasFeature(StringRef Feature) const override {
5594 return Feature == "tce";
5597 void getTargetBuiltins(const Builtin::Info *&Records,
5598 unsigned &NumRecords) const override {}
5599 const char *getClobbers() const override {
5602 BuiltinVaListKind getBuiltinVaListKind() const override {
5603 return TargetInfo::VoidPtrBuiltinVaList;
5605 void getGCCRegNames(const char * const *&Names,
5606 unsigned &NumNames) const override {}
5607 bool validateAsmConstraint(const char *&Name,
5608 TargetInfo::ConstraintInfo &info) const override{
5611 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5612 unsigned &NumAliases) const override {}
5617 class MipsTargetInfoBase : public TargetInfo {
5618 virtual void setDescriptionString() = 0;
5620 static const Builtin::Info BuiltinInfo[];
5627 HardFloat, SoftFloat
5639 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5640 const std::string &CPUStr)
5641 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
5642 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
5643 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
5644 TheCXXABI.set(TargetCXXABI::GenericMIPS);
5647 bool isNaN2008Default() const {
5648 return CPU == "mips32r6" || CPU == "mips64r6";
5651 bool isFP64Default() const {
5652 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
5655 StringRef getABI() const override { return ABI; }
5656 bool setCPU(const std::string &Name) override {
5657 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
5658 getTriple().getArch() == llvm::Triple::mipsel;
5660 return llvm::StringSwitch<bool>(Name)
5661 .Case("mips1", IsMips32)
5662 .Case("mips2", IsMips32)
5663 .Case("mips3", true)
5664 .Case("mips4", true)
5665 .Case("mips5", true)
5666 .Case("mips32", IsMips32)
5667 .Case("mips32r2", IsMips32)
5668 .Case("mips32r6", IsMips32)
5669 .Case("mips64", true)
5670 .Case("mips64r2", true)
5671 .Case("mips64r6", true)
5672 .Case("octeon", true)
5675 const std::string& getCPU() const { return CPU; }
5676 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5677 // The backend enables certain ABI's by default according to the
5679 // Disable both possible defaults so that we don't end up with multiple
5680 // ABI's selected and trigger an assertion.
5681 Features["o32"] = false;
5682 Features["n64"] = false;
5684 Features[ABI] = true;
5685 if (CPU == "octeon")
5686 Features["mips64r2"] = Features["cnmips"] = true;
5688 Features[CPU] = true;
5691 void getTargetDefines(const LangOptions &Opts,
5692 MacroBuilder &Builder) const override {
5693 Builder.defineMacro("__mips__");
5694 Builder.defineMacro("_mips");
5696 Builder.defineMacro("mips");
5698 Builder.defineMacro("__REGISTER_PREFIX__", "");
5702 Builder.defineMacro("__mips_hard_float", Twine(1));
5705 Builder.defineMacro("__mips_soft_float", Twine(1));
5710 Builder.defineMacro("__mips_single_float", Twine(1));
5712 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
5713 Builder.defineMacro("_MIPS_FPSET",
5714 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
5717 Builder.defineMacro("__mips16", Twine(1));
5720 Builder.defineMacro("__mips_micromips", Twine(1));
5723 Builder.defineMacro("__mips_nan2008", Twine(1));
5729 Builder.defineMacro("__mips_dsp_rev", Twine(1));
5730 Builder.defineMacro("__mips_dsp", Twine(1));
5733 Builder.defineMacro("__mips_dsp_rev", Twine(2));
5734 Builder.defineMacro("__mips_dspr2", Twine(1));
5735 Builder.defineMacro("__mips_dsp", Twine(1));
5740 Builder.defineMacro("__mips_msa", Twine(1));
5742 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
5743 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
5744 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
5746 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
5747 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
5750 void getTargetBuiltins(const Builtin::Info *&Records,
5751 unsigned &NumRecords) const override {
5752 Records = BuiltinInfo;
5753 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
5755 bool hasFeature(StringRef Feature) const override {
5756 return llvm::StringSwitch<bool>(Feature)
5758 .Case("fp64", HasFP64)
5761 BuiltinVaListKind getBuiltinVaListKind() const override {
5762 return TargetInfo::VoidPtrBuiltinVaList;
5764 void getGCCRegNames(const char * const *&Names,
5765 unsigned &NumNames) const override {
5766 static const char *const GCCRegNames[] = {
5767 // CPU register names
5768 // Must match second column of GCCRegAliases
5769 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
5770 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
5771 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
5772 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
5773 // Floating point register names
5774 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
5775 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
5776 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
5777 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
5778 // Hi/lo and condition register names
5779 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
5780 "$fcc5","$fcc6","$fcc7",
5781 // MSA register names
5782 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
5783 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
5784 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
5785 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
5786 // MSA control register names
5787 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
5788 "$msarequest", "$msamap", "$msaunmap"
5790 Names = GCCRegNames;
5791 NumNames = llvm::array_lengthof(GCCRegNames);
5793 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5794 unsigned &NumAliases) const override = 0;
5795 bool validateAsmConstraint(const char *&Name,
5796 TargetInfo::ConstraintInfo &Info) const override {
5800 case 'r': // CPU registers.
5801 case 'd': // Equivalent to "r" unless generating MIPS16 code.
5802 case 'y': // Equivalent to "r", backward compatibility only.
5803 case 'f': // floating-point registers.
5804 case 'c': // $25 for indirect jumps
5805 case 'l': // lo register
5806 case 'x': // hilo register pair
5807 Info.setAllowsRegister();
5809 case 'I': // Signed 16-bit constant
5810 case 'J': // Integer 0
5811 case 'K': // Unsigned 16-bit constant
5812 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
5813 case 'M': // Constants not loadable via lui, addiu, or ori
5814 case 'N': // Constant -1 to -65535
5815 case 'O': // A signed 15-bit constant
5816 case 'P': // A constant between 1 go 65535
5818 case 'R': // An address that can be used in a non-macro load or store
5819 Info.setAllowsMemory();
5824 const char *getClobbers() const override {
5825 // In GCC, $1 is not widely used in generated code (it's used only in a few
5826 // specific situations), so there is no real need for users to add it to
5827 // the clobbers list if they want to use it in their inline assembly code.
5829 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
5830 // code generation, so using it in inline assembly without adding it to the
5831 // clobbers list can cause conflicts between the inline assembly code and
5832 // the surrounding generated code.
5834 // Another problem is that LLVM is allowed to choose $1 for inline assembly
5835 // operands, which will conflict with the ".set at" assembler option (which
5836 // we use only for inline assembly, in order to maintain compatibility with
5837 // GCC) and will also conflict with the user's usage of $1.
5839 // The easiest way to avoid these conflicts and keep $1 as an allocatable
5840 // register for generated code is to automatically clobber $1 for all inline
5843 // FIXME: We should automatically clobber $1 only for inline assembly code
5844 // which actually uses it. This would allow LLVM to use $1 for inline
5845 // assembly operands if the user's assembly code doesn't use it.
5849 bool handleTargetFeatures(std::vector<std::string> &Features,
5850 DiagnosticsEngine &Diags) override {
5852 IsMicromips = false;
5853 IsNan2008 = isNaN2008Default();
5854 IsSingleFloat = false;
5855 FloatABI = HardFloat;
5857 HasFP64 = isFP64Default();
5859 for (std::vector<std::string>::iterator it = Features.begin(),
5860 ie = Features.end(); it != ie; ++it) {
5861 if (*it == "+single-float")
5862 IsSingleFloat = true;
5863 else if (*it == "+soft-float")
5864 FloatABI = SoftFloat;
5865 else if (*it == "+mips16")
5867 else if (*it == "+micromips")
5869 else if (*it == "+dsp")
5870 DspRev = std::max(DspRev, DSP1);
5871 else if (*it == "+dspr2")
5872 DspRev = std::max(DspRev, DSP2);
5873 else if (*it == "+msa")
5875 else if (*it == "+fp64")
5877 else if (*it == "-fp64")
5879 else if (*it == "+nan2008")
5881 else if (*it == "-nan2008")
5885 // Remove front-end specific options.
5886 std::vector<std::string>::iterator it =
5887 std::find(Features.begin(), Features.end(), "+soft-float");
5888 if (it != Features.end())
5891 setDescriptionString();
5896 int getEHDataRegisterNumber(unsigned RegNo) const override {
5897 if (RegNo == 0) return 4;
5898 if (RegNo == 1) return 5;
5902 bool isCLZForZeroUndef() const override { return false; }
5905 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
5906 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5907 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5909 #include "clang/Basic/BuiltinsMips.def"
5912 class Mips32TargetInfoBase : public MipsTargetInfoBase {
5914 Mips32TargetInfoBase(const llvm::Triple &Triple)
5915 : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
5916 SizeType = UnsignedInt;
5917 PtrDiffType = SignedInt;
5918 Int64Type = SignedLongLong;
5919 IntMaxType = Int64Type;
5920 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
5922 bool setABI(const std::string &Name) override {
5923 if (Name == "o32" || Name == "eabi") {
5929 void getTargetDefines(const LangOptions &Opts,
5930 MacroBuilder &Builder) const override {
5931 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5933 Builder.defineMacro("__mips", "32");
5934 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
5936 const std::string& CPUStr = getCPU();
5937 if (CPUStr == "mips32")
5938 Builder.defineMacro("__mips_isa_rev", "1");
5939 else if (CPUStr == "mips32r2")
5940 Builder.defineMacro("__mips_isa_rev", "2");
5941 else if (CPUStr == "mips32r6")
5942 Builder.defineMacro("__mips_isa_rev", "6");
5945 Builder.defineMacro("__mips_o32");
5946 Builder.defineMacro("_ABIO32", "1");
5947 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
5949 else if (ABI == "eabi")
5950 Builder.defineMacro("__mips_eabi");
5952 llvm_unreachable("Invalid ABI for Mips32.");
5954 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5955 unsigned &NumAliases) const override {
5956 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5966 { { "t2" }, "$10" },
5967 { { "t3" }, "$11" },
5968 { { "t4" }, "$12" },
5969 { { "t5" }, "$13" },
5970 { { "t6" }, "$14" },
5971 { { "t7" }, "$15" },
5972 { { "s0" }, "$16" },
5973 { { "s1" }, "$17" },
5974 { { "s2" }, "$18" },
5975 { { "s3" }, "$19" },
5976 { { "s4" }, "$20" },
5977 { { "s5" }, "$21" },
5978 { { "s6" }, "$22" },
5979 { { "s7" }, "$23" },
5980 { { "t8" }, "$24" },
5981 { { "t9" }, "$25" },
5982 { { "k0" }, "$26" },
5983 { { "k1" }, "$27" },
5984 { { "gp" }, "$28" },
5985 { { "sp","$sp" }, "$29" },
5986 { { "fp","$fp" }, "$30" },
5989 Aliases = GCCRegAliases;
5990 NumAliases = llvm::array_lengthof(GCCRegAliases);
5994 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
5995 void setDescriptionString() override {
5996 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6000 Mips32EBTargetInfo(const llvm::Triple &Triple)
6001 : Mips32TargetInfoBase(Triple) {
6003 void getTargetDefines(const LangOptions &Opts,
6004 MacroBuilder &Builder) const override {
6005 DefineStd(Builder, "MIPSEB", Opts);
6006 Builder.defineMacro("_MIPSEB");
6007 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6011 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
6012 void setDescriptionString() override {
6013 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6017 Mips32ELTargetInfo(const llvm::Triple &Triple)
6018 : Mips32TargetInfoBase(Triple) {
6021 void getTargetDefines(const LangOptions &Opts,
6022 MacroBuilder &Builder) const override {
6023 DefineStd(Builder, "MIPSEL", Opts);
6024 Builder.defineMacro("_MIPSEL");
6025 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6029 class Mips64TargetInfoBase : public MipsTargetInfoBase {
6031 Mips64TargetInfoBase(const llvm::Triple &Triple)
6032 : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6033 LongDoubleWidth = LongDoubleAlign = 128;
6034 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6035 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6036 LongDoubleWidth = LongDoubleAlign = 64;
6037 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6040 SuitableAlign = 128;
6041 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6044 void setN64ABITypes() {
6045 LongWidth = LongAlign = 64;
6046 PointerWidth = PointerAlign = 64;
6047 SizeType = UnsignedLong;
6048 PtrDiffType = SignedLong;
6049 Int64Type = SignedLong;
6050 IntMaxType = Int64Type;
6053 void setN32ABITypes() {
6054 LongWidth = LongAlign = 32;
6055 PointerWidth = PointerAlign = 32;
6056 SizeType = UnsignedInt;
6057 PtrDiffType = SignedInt;
6058 Int64Type = SignedLongLong;
6059 IntMaxType = Int64Type;
6062 bool setABI(const std::string &Name) override {
6063 if (Name == "n32") {
6068 if (Name == "n64") {
6076 void getTargetDefines(const LangOptions &Opts,
6077 MacroBuilder &Builder) const override {
6078 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6080 Builder.defineMacro("__mips", "64");
6081 Builder.defineMacro("__mips64");
6082 Builder.defineMacro("__mips64__");
6083 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6085 const std::string& CPUStr = getCPU();
6086 if (CPUStr == "mips64")
6087 Builder.defineMacro("__mips_isa_rev", "1");
6088 else if (CPUStr == "mips64r2")
6089 Builder.defineMacro("__mips_isa_rev", "2");
6090 else if (CPUStr == "mips64r6")
6091 Builder.defineMacro("__mips_isa_rev", "6");
6094 Builder.defineMacro("__mips_n32");
6095 Builder.defineMacro("_ABIN32", "2");
6096 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6098 else if (ABI == "n64") {
6099 Builder.defineMacro("__mips_n64");
6100 Builder.defineMacro("_ABI64", "3");
6101 Builder.defineMacro("_MIPS_SIM", "_ABI64");
6104 llvm_unreachable("Invalid ABI for Mips64.");
6106 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6107 unsigned &NumAliases) const override {
6108 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6118 { { "a6" }, "$10" },
6119 { { "a7" }, "$11" },
6120 { { "t0" }, "$12" },
6121 { { "t1" }, "$13" },
6122 { { "t2" }, "$14" },
6123 { { "t3" }, "$15" },
6124 { { "s0" }, "$16" },
6125 { { "s1" }, "$17" },
6126 { { "s2" }, "$18" },
6127 { { "s3" }, "$19" },
6128 { { "s4" }, "$20" },
6129 { { "s5" }, "$21" },
6130 { { "s6" }, "$22" },
6131 { { "s7" }, "$23" },
6132 { { "t8" }, "$24" },
6133 { { "t9" }, "$25" },
6134 { { "k0" }, "$26" },
6135 { { "k1" }, "$27" },
6136 { { "gp" }, "$28" },
6137 { { "sp","$sp" }, "$29" },
6138 { { "fp","$fp" }, "$30" },
6141 Aliases = GCCRegAliases;
6142 NumAliases = llvm::array_lengthof(GCCRegAliases);
6145 bool hasInt128Type() const override { return true; }
6148 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
6149 void setDescriptionString() override {
6151 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6153 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6158 Mips64EBTargetInfo(const llvm::Triple &Triple)
6159 : Mips64TargetInfoBase(Triple) {}
6160 void getTargetDefines(const LangOptions &Opts,
6161 MacroBuilder &Builder) const override {
6162 DefineStd(Builder, "MIPSEB", Opts);
6163 Builder.defineMacro("_MIPSEB");
6164 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6168 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
6169 void setDescriptionString() override {
6171 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6173 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6176 Mips64ELTargetInfo(const llvm::Triple &Triple)
6177 : Mips64TargetInfoBase(Triple) {
6178 // Default ABI is n64.
6181 void getTargetDefines(const LangOptions &Opts,
6182 MacroBuilder &Builder) const override {
6183 DefineStd(Builder, "MIPSEL", Opts);
6184 Builder.defineMacro("_MIPSEL");
6185 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6188 } // end anonymous namespace.
6191 class PNaClTargetInfo : public TargetInfo {
6193 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6195 this->UserLabelPrefix = "";
6196 this->LongAlign = 32;
6197 this->LongWidth = 32;
6198 this->PointerAlign = 32;
6199 this->PointerWidth = 32;
6200 this->IntMaxType = TargetInfo::SignedLongLong;
6201 this->Int64Type = TargetInfo::SignedLongLong;
6202 this->DoubleAlign = 64;
6203 this->LongDoubleWidth = 64;
6204 this->LongDoubleAlign = 64;
6205 this->SizeType = TargetInfo::UnsignedInt;
6206 this->PtrDiffType = TargetInfo::SignedInt;
6207 this->IntPtrType = TargetInfo::SignedInt;
6208 this->RegParmMax = 0; // Disallow regparm
6211 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6213 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6214 Builder.defineMacro("__le32__");
6215 Builder.defineMacro("__pnacl__");
6217 void getTargetDefines(const LangOptions &Opts,
6218 MacroBuilder &Builder) const override {
6219 getArchDefines(Opts, Builder);
6221 bool hasFeature(StringRef Feature) const override {
6222 return Feature == "pnacl";
6224 void getTargetBuiltins(const Builtin::Info *&Records,
6225 unsigned &NumRecords) const override {
6227 BuiltinVaListKind getBuiltinVaListKind() const override {
6228 return TargetInfo::PNaClABIBuiltinVaList;
6230 void getGCCRegNames(const char * const *&Names,
6231 unsigned &NumNames) const override;
6232 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6233 unsigned &NumAliases) const override;
6234 bool validateAsmConstraint(const char *&Name,
6235 TargetInfo::ConstraintInfo &Info) const override {
6239 const char *getClobbers() const override {
6244 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6245 unsigned &NumNames) const {
6250 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6251 unsigned &NumAliases) const {
6255 } // end anonymous namespace.
6258 class Le64TargetInfo : public TargetInfo {
6259 static const Builtin::Info BuiltinInfo[];
6262 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6264 NoAsmVariants = true;
6265 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6266 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6268 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
6271 void getTargetDefines(const LangOptions &Opts,
6272 MacroBuilder &Builder) const override {
6273 DefineStd(Builder, "unix", Opts);
6274 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6275 Builder.defineMacro("__ELF__");
6277 void getTargetBuiltins(const Builtin::Info *&Records,
6278 unsigned &NumRecords) const override {
6279 Records = BuiltinInfo;
6280 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
6282 BuiltinVaListKind getBuiltinVaListKind() const override {
6283 return TargetInfo::PNaClABIBuiltinVaList;
6285 const char *getClobbers() const override { return ""; }
6286 void getGCCRegNames(const char *const *&Names,
6287 unsigned &NumNames) const override {
6291 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6292 unsigned &NumAliases) const override {
6296 bool validateAsmConstraint(const char *&Name,
6297 TargetInfo::ConstraintInfo &Info) const override {
6301 bool hasProtectedVisibility() const override { return false; }
6303 } // end anonymous namespace.
6305 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
6306 #define BUILTIN(ID, TYPE, ATTRS) \
6307 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6308 #include "clang/Basic/BuiltinsLe64.def"
6312 static const unsigned SPIRAddrSpaceMap[] = {
6315 2, // opencl_constant
6316 4, // opencl_generic
6321 class SPIRTargetInfo : public TargetInfo {
6323 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6324 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6325 "SPIR target must use unknown OS");
6326 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6327 "SPIR target must use unknown environment type");
6329 TLSSupported = false;
6330 LongWidth = LongAlign = 64;
6331 AddrSpaceMap = &SPIRAddrSpaceMap;
6332 UseAddrSpaceMapMangling = true;
6333 // Define available target features
6334 // These must be defined in sorted order!
6335 NoAsmVariants = true;
6337 void getTargetDefines(const LangOptions &Opts,
6338 MacroBuilder &Builder) const override {
6339 DefineStd(Builder, "SPIR", Opts);
6341 bool hasFeature(StringRef Feature) const override {
6342 return Feature == "spir";
6345 void getTargetBuiltins(const Builtin::Info *&Records,
6346 unsigned &NumRecords) const override {}
6347 const char *getClobbers() const override {
6350 void getGCCRegNames(const char * const *&Names,
6351 unsigned &NumNames) const override {}
6353 validateAsmConstraint(const char *&Name,
6354 TargetInfo::ConstraintInfo &info) const override {
6357 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6358 unsigned &NumAliases) const override {}
6359 BuiltinVaListKind getBuiltinVaListKind() const override {
6360 return TargetInfo::VoidPtrBuiltinVaList;
6365 class SPIR32TargetInfo : public SPIRTargetInfo {
6367 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6368 PointerWidth = PointerAlign = 32;
6369 SizeType = TargetInfo::UnsignedInt;
6370 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6372 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6373 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6375 void getTargetDefines(const LangOptions &Opts,
6376 MacroBuilder &Builder) const override {
6377 DefineStd(Builder, "SPIR32", Opts);
6381 class SPIR64TargetInfo : public SPIRTargetInfo {
6383 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6384 PointerWidth = PointerAlign = 64;
6385 SizeType = TargetInfo::UnsignedLong;
6386 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6387 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6388 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6390 void getTargetDefines(const LangOptions &Opts,
6391 MacroBuilder &Builder) const override {
6392 DefineStd(Builder, "SPIR64", Opts);
6398 class XCoreTargetInfo : public TargetInfo {
6399 static const Builtin::Info BuiltinInfo[];
6401 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6403 NoAsmVariants = true;
6406 DoubleAlign = LongDoubleAlign = 32;
6407 SizeType = UnsignedInt;
6408 PtrDiffType = SignedInt;
6409 IntPtrType = SignedInt;
6410 WCharType = UnsignedChar;
6411 WIntType = UnsignedInt;
6412 UseZeroLengthBitfieldAlignment = true;
6413 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6414 "-f64:32-a:0:32-n32";
6416 void getTargetDefines(const LangOptions &Opts,
6417 MacroBuilder &Builder) const override {
6418 Builder.defineMacro("__XS1B__");
6420 void getTargetBuiltins(const Builtin::Info *&Records,
6421 unsigned &NumRecords) const override {
6422 Records = BuiltinInfo;
6423 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
6425 BuiltinVaListKind getBuiltinVaListKind() const override {
6426 return TargetInfo::VoidPtrBuiltinVaList;
6428 const char *getClobbers() const override {
6431 void getGCCRegNames(const char * const *&Names,
6432 unsigned &NumNames) const override {
6433 static const char * const GCCRegNames[] = {
6434 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6435 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
6437 Names = GCCRegNames;
6438 NumNames = llvm::array_lengthof(GCCRegNames);
6440 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6441 unsigned &NumAliases) const override {
6445 bool validateAsmConstraint(const char *&Name,
6446 TargetInfo::ConstraintInfo &Info) const override {
6449 int getEHDataRegisterNumber(unsigned RegNo) const override {
6450 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6451 return (RegNo < 2)? RegNo : -1;
6455 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6456 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6457 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6459 #include "clang/Basic/BuiltinsXCore.def"
6461 } // end anonymous namespace.
6464 //===----------------------------------------------------------------------===//
6466 //===----------------------------------------------------------------------===//
6468 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6469 llvm::Triple::OSType os = Triple.getOS();
6471 switch (Triple.getArch()) {
6475 case llvm::Triple::xcore:
6476 return new XCoreTargetInfo(Triple);
6478 case llvm::Triple::hexagon:
6479 return new HexagonTargetInfo(Triple);
6481 case llvm::Triple::aarch64:
6482 if (Triple.isOSDarwin())
6483 return new DarwinAArch64TargetInfo(Triple);
6486 case llvm::Triple::FreeBSD:
6487 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
6488 case llvm::Triple::Linux:
6489 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6490 case llvm::Triple::NetBSD:
6491 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6493 return new AArch64leTargetInfo(Triple);
6496 case llvm::Triple::aarch64_be:
6498 case llvm::Triple::FreeBSD:
6499 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
6500 case llvm::Triple::Linux:
6501 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6502 case llvm::Triple::NetBSD:
6503 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6505 return new AArch64beTargetInfo(Triple);
6508 case llvm::Triple::arm:
6509 case llvm::Triple::thumb:
6510 if (Triple.isOSBinFormatMachO())
6511 return new DarwinARMTargetInfo(Triple);
6514 case llvm::Triple::Linux:
6515 return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6516 case llvm::Triple::FreeBSD:
6517 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6518 case llvm::Triple::NetBSD:
6519 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6520 case llvm::Triple::OpenBSD:
6521 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6522 case llvm::Triple::Bitrig:
6523 return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6524 case llvm::Triple::RTEMS:
6525 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6526 case llvm::Triple::NaCl:
6527 return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6528 case llvm::Triple::Win32:
6529 switch (Triple.getEnvironment()) {
6531 return new ARMleTargetInfo(Triple);
6532 case llvm::Triple::Itanium:
6533 return new ItaniumWindowsARMleTargetInfo(Triple);
6534 case llvm::Triple::MSVC:
6535 return new MicrosoftARMleTargetInfo(Triple);
6538 return new ARMleTargetInfo(Triple);
6541 case llvm::Triple::armeb:
6542 case llvm::Triple::thumbeb:
6543 if (Triple.isOSDarwin())
6544 return new DarwinARMTargetInfo(Triple);
6547 case llvm::Triple::Linux:
6548 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6549 case llvm::Triple::FreeBSD:
6550 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6551 case llvm::Triple::NetBSD:
6552 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6553 case llvm::Triple::OpenBSD:
6554 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6555 case llvm::Triple::Bitrig:
6556 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6557 case llvm::Triple::RTEMS:
6558 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6559 case llvm::Triple::NaCl:
6560 return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6562 return new ARMbeTargetInfo(Triple);
6565 case llvm::Triple::msp430:
6566 return new MSP430TargetInfo(Triple);
6568 case llvm::Triple::mips:
6570 case llvm::Triple::Linux:
6571 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6572 case llvm::Triple::RTEMS:
6573 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6574 case llvm::Triple::FreeBSD:
6575 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6576 case llvm::Triple::NetBSD:
6577 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6579 return new Mips32EBTargetInfo(Triple);
6582 case llvm::Triple::mipsel:
6584 case llvm::Triple::Linux:
6585 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6586 case llvm::Triple::RTEMS:
6587 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
6588 case llvm::Triple::FreeBSD:
6589 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6590 case llvm::Triple::NetBSD:
6591 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6592 case llvm::Triple::NaCl:
6593 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
6595 return new Mips32ELTargetInfo(Triple);
6598 case llvm::Triple::mips64:
6600 case llvm::Triple::Linux:
6601 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
6602 case llvm::Triple::RTEMS:
6603 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
6604 case llvm::Triple::FreeBSD:
6605 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6606 case llvm::Triple::NetBSD:
6607 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6608 case llvm::Triple::OpenBSD:
6609 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6611 return new Mips64EBTargetInfo(Triple);
6614 case llvm::Triple::mips64el:
6616 case llvm::Triple::Linux:
6617 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
6618 case llvm::Triple::RTEMS:
6619 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
6620 case llvm::Triple::FreeBSD:
6621 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6622 case llvm::Triple::NetBSD:
6623 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6624 case llvm::Triple::OpenBSD:
6625 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6627 return new Mips64ELTargetInfo(Triple);
6630 case llvm::Triple::le32:
6632 case llvm::Triple::NaCl:
6633 return new NaClTargetInfo<PNaClTargetInfo>(Triple);
6638 case llvm::Triple::le64:
6639 return new Le64TargetInfo(Triple);
6641 case llvm::Triple::ppc:
6642 if (Triple.isOSDarwin())
6643 return new DarwinPPC32TargetInfo(Triple);
6645 case llvm::Triple::Linux:
6646 return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
6647 case llvm::Triple::FreeBSD:
6648 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
6649 case llvm::Triple::NetBSD:
6650 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
6651 case llvm::Triple::OpenBSD:
6652 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
6653 case llvm::Triple::RTEMS:
6654 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
6656 return new PPC32TargetInfo(Triple);
6659 case llvm::Triple::ppc64:
6660 if (Triple.isOSDarwin())
6661 return new DarwinPPC64TargetInfo(Triple);
6663 case llvm::Triple::Linux:
6664 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6665 case llvm::Triple::Lv2:
6666 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
6667 case llvm::Triple::FreeBSD:
6668 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
6669 case llvm::Triple::NetBSD:
6670 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6672 return new PPC64TargetInfo(Triple);
6675 case llvm::Triple::ppc64le:
6677 case llvm::Triple::Linux:
6678 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6679 case llvm::Triple::NetBSD:
6680 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6682 return new PPC64TargetInfo(Triple);
6685 case llvm::Triple::nvptx:
6686 return new NVPTX32TargetInfo(Triple);
6687 case llvm::Triple::nvptx64:
6688 return new NVPTX64TargetInfo(Triple);
6690 case llvm::Triple::amdgcn:
6691 case llvm::Triple::r600:
6692 return new R600TargetInfo(Triple);
6694 case llvm::Triple::sparc:
6696 case llvm::Triple::Linux:
6697 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
6698 case llvm::Triple::Solaris:
6699 return new SolarisSparcV8TargetInfo(Triple);
6700 case llvm::Triple::NetBSD:
6701 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
6702 case llvm::Triple::OpenBSD:
6703 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
6704 case llvm::Triple::RTEMS:
6705 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
6707 return new SparcV8TargetInfo(Triple);
6710 case llvm::Triple::sparcv9:
6712 case llvm::Triple::Linux:
6713 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
6714 case llvm::Triple::Solaris:
6715 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
6716 case llvm::Triple::NetBSD:
6717 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
6718 case llvm::Triple::OpenBSD:
6719 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
6720 case llvm::Triple::FreeBSD:
6721 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
6723 return new SparcV9TargetInfo(Triple);
6726 case llvm::Triple::systemz:
6728 case llvm::Triple::Linux:
6729 return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
6731 return new SystemZTargetInfo(Triple);
6734 case llvm::Triple::tce:
6735 return new TCETargetInfo(Triple);
6737 case llvm::Triple::x86:
6738 if (Triple.isOSDarwin())
6739 return new DarwinI386TargetInfo(Triple);
6742 case llvm::Triple::Linux:
6743 return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
6744 case llvm::Triple::DragonFly:
6745 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
6746 case llvm::Triple::NetBSD:
6747 return new NetBSDI386TargetInfo(Triple);
6748 case llvm::Triple::OpenBSD:
6749 return new OpenBSDI386TargetInfo(Triple);
6750 case llvm::Triple::Bitrig:
6751 return new BitrigI386TargetInfo(Triple);
6752 case llvm::Triple::FreeBSD:
6753 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6754 case llvm::Triple::KFreeBSD:
6755 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6756 case llvm::Triple::Minix:
6757 return new MinixTargetInfo<X86_32TargetInfo>(Triple);
6758 case llvm::Triple::Solaris:
6759 return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
6760 case llvm::Triple::Win32: {
6761 switch (Triple.getEnvironment()) {
6763 return new X86_32TargetInfo(Triple);
6764 case llvm::Triple::Cygnus:
6765 return new CygwinX86_32TargetInfo(Triple);
6766 case llvm::Triple::GNU:
6767 return new MinGWX86_32TargetInfo(Triple);
6768 case llvm::Triple::Itanium:
6769 case llvm::Triple::MSVC:
6770 return new MicrosoftX86_32TargetInfo(Triple);
6773 case llvm::Triple::Haiku:
6774 return new HaikuX86_32TargetInfo(Triple);
6775 case llvm::Triple::RTEMS:
6776 return new RTEMSX86_32TargetInfo(Triple);
6777 case llvm::Triple::NaCl:
6778 return new NaClTargetInfo<X86_32TargetInfo>(Triple);
6780 return new X86_32TargetInfo(Triple);
6783 case llvm::Triple::x86_64:
6784 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
6785 return new DarwinX86_64TargetInfo(Triple);
6788 case llvm::Triple::Linux:
6789 return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
6790 case llvm::Triple::DragonFly:
6791 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
6792 case llvm::Triple::NetBSD:
6793 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
6794 case llvm::Triple::OpenBSD:
6795 return new OpenBSDX86_64TargetInfo(Triple);
6796 case llvm::Triple::Bitrig:
6797 return new BitrigX86_64TargetInfo(Triple);
6798 case llvm::Triple::FreeBSD:
6799 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6800 case llvm::Triple::KFreeBSD:
6801 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6802 case llvm::Triple::Solaris:
6803 return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
6804 case llvm::Triple::Win32: {
6805 switch (Triple.getEnvironment()) {
6807 return new X86_64TargetInfo(Triple);
6808 case llvm::Triple::GNU:
6809 return new MinGWX86_64TargetInfo(Triple);
6810 case llvm::Triple::MSVC:
6811 return new MicrosoftX86_64TargetInfo(Triple);
6814 case llvm::Triple::NaCl:
6815 return new NaClTargetInfo<X86_64TargetInfo>(Triple);
6817 return new X86_64TargetInfo(Triple);
6820 case llvm::Triple::spir: {
6821 if (Triple.getOS() != llvm::Triple::UnknownOS ||
6822 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6824 return new SPIR32TargetInfo(Triple);
6826 case llvm::Triple::spir64: {
6827 if (Triple.getOS() != llvm::Triple::UnknownOS ||
6828 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6830 return new SPIR64TargetInfo(Triple);
6835 /// CreateTargetInfo - Return the target info object for the specified target
6838 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
6839 const std::shared_ptr<TargetOptions> &Opts) {
6840 llvm::Triple Triple(Opts->Triple);
6842 // Construct the target
6843 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
6845 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
6848 Target->TargetOpts = Opts;
6850 // Set the target CPU if specified.
6851 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
6852 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
6856 // Set the target ABI if specified.
6857 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
6858 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
6862 // Set the fp math unit.
6863 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
6864 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
6868 // Compute the default target features, we need the target to handle this
6869 // because features may have dependencies on one another.
6870 llvm::StringMap<bool> Features;
6871 Target->getDefaultFeatures(Features);
6873 // Apply the user specified deltas.
6874 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
6876 const char *Name = Opts->FeaturesAsWritten[I].c_str();
6877 // Apply the feature via the target.
6878 bool Enabled = Name[0] == '+';
6879 Target->setFeatureEnabled(Features, Name + 1, Enabled);
6882 // Add the features to the compile options.
6884 // FIXME: If we are completely confident that we have the right set, we only
6885 // need to pass the minuses.
6886 Opts->Features.clear();
6887 for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
6888 ie = Features.end(); it != ie; ++it)
6889 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
6890 if (!Target->handleTargetFeatures(Opts->Features, Diags))
6893 return Target.release();