1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/Triple.h"
27 #include "llvm/IR/Type.h"
28 #include "llvm/MC/MCSectionMachO.h"
29 #include "llvm/Support/ErrorHandling.h"
32 using namespace clang;
34 //===----------------------------------------------------------------------===//
35 // Common code shared among targets.
36 //===----------------------------------------------------------------------===//
38 /// DefineStd - Define a macro name and standard variants. For example if
39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42 const LangOptions &Opts) {
43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46 // in the user's namespace.
48 Builder.defineMacro(MacroName);
51 Builder.defineMacro("__" + MacroName);
54 Builder.defineMacro("__" + MacroName + "__");
57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
59 Builder.defineMacro("__" + CPUName);
60 Builder.defineMacro("__" + CPUName + "__");
62 Builder.defineMacro("__tune_" + CPUName + "__");
65 //===----------------------------------------------------------------------===//
66 // Defines specific to certain operating systems.
67 //===----------------------------------------------------------------------===//
70 template<typename TgtInfo>
71 class OSTargetInfo : public TgtInfo {
73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74 MacroBuilder &Builder) const=0;
76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
77 void getTargetDefines(const LangOptions &Opts,
78 MacroBuilder &Builder) const override {
79 TgtInfo::getTargetDefines(Opts, Builder);
80 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
84 } // end anonymous namespace
87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88 const llvm::Triple &Triple,
89 StringRef &PlatformName,
90 VersionTuple &PlatformMinVersion) {
91 Builder.defineMacro("__APPLE_CC__", "6000");
92 Builder.defineMacro("__APPLE__");
93 Builder.defineMacro("OBJC_NEW_PROPERTIES");
94 // AddressSanitizer doesn't play well with source fortification, which is on
95 // by default on Darwin.
96 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98 if (!Opts.ObjCAutoRefCount) {
99 // __weak is always defined, for use in blocks and with objc pointers.
100 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102 // Darwin defines __strong even in C mode (just to nothing).
103 if (Opts.getGC() != LangOptions::NonGC)
104 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106 Builder.defineMacro("__strong", "");
108 // __unsafe_unretained is defined to nothing in non-ARC mode. We even
109 // allow this in C, since one might have block pointers in structs that
110 // are used in pure C code and in Objective-C ARC.
111 Builder.defineMacro("__unsafe_unretained", "");
115 Builder.defineMacro("__STATIC__");
117 Builder.defineMacro("__DYNAMIC__");
119 if (Opts.POSIXThreads)
120 Builder.defineMacro("_REENTRANT");
122 // Get the platform type and version number from the triple.
123 unsigned Maj, Min, Rev;
124 if (Triple.isMacOSX()) {
125 Triple.getMacOSXVersion(Maj, Min, Rev);
126 PlatformName = "macosx";
128 Triple.getOSVersion(Maj, Min, Rev);
129 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
132 // If -target arch-pc-win32-macho option specified, we're
133 // generating code for Win32 ABI. No need to emit
134 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
135 if (PlatformName == "win32") {
136 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
140 // Set the appropriate OS version define.
141 if (Triple.isiOS()) {
142 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
145 Str[1] = '0' + (Min / 10);
146 Str[2] = '0' + (Min % 10);
147 Str[3] = '0' + (Rev / 10);
148 Str[4] = '0' + (Rev % 10);
150 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
152 } else if (Triple.isMacOSX()) {
153 // Note that the Driver allows versions which aren't representable in the
154 // define (because we only get a single digit for the minor and micro
155 // revision numbers). So, we limit them to the maximum representable
157 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159 if (Maj < 10 || (Maj == 10 && Min < 10)) {
160 Str[0] = '0' + (Maj / 10);
161 Str[1] = '0' + (Maj % 10);
162 Str[2] = '0' + std::min(Min, 9U);
163 Str[3] = '0' + std::min(Rev, 9U);
166 // Handle versions > 10.9.
167 Str[0] = '0' + (Maj / 10);
168 Str[1] = '0' + (Maj % 10);
169 Str[2] = '0' + (Min / 10);
170 Str[3] = '0' + (Min % 10);
171 Str[4] = '0' + (Rev / 10);
172 Str[5] = '0' + (Rev % 10);
175 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
178 // Tell users about the kernel if there is one.
179 if (Triple.isOSDarwin())
180 Builder.defineMacro("__MACH__");
182 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
186 template<typename Target>
187 class DarwinTargetInfo : public OSTargetInfo<Target> {
189 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
190 MacroBuilder &Builder) const override {
191 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
192 this->PlatformMinVersion);
196 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
197 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
198 this->MCountName = "\01mcount";
201 std::string isValidSectionSpecifier(StringRef SR) const override {
202 // Let MCSectionMachO validate this.
203 StringRef Segment, Section;
204 unsigned TAA, StubSize;
206 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
207 TAA, HasTAA, StubSize);
210 const char *getStaticInitSectionSpecifier() const override {
211 // FIXME: We should return 0 when building kexts.
212 return "__TEXT,__StaticInit,regular,pure_instructions";
215 /// Darwin does not support protected visibility. Darwin's "default"
216 /// is very similar to ELF's "protected"; Darwin requires a "weak"
217 /// attribute on declarations that can be dynamically replaced.
218 bool hasProtectedVisibility() const override {
224 // DragonFlyBSD Target
225 template<typename Target>
226 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
228 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
229 MacroBuilder &Builder) const override {
230 // DragonFly defines; list based off of gcc output
231 Builder.defineMacro("__DragonFly__");
232 Builder.defineMacro("__DragonFly_cc_version", "100001");
233 Builder.defineMacro("__ELF__");
234 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
235 Builder.defineMacro("__tune_i386__");
236 DefineStd(Builder, "unix", Opts);
239 DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
240 : OSTargetInfo<Target>(Triple) {
241 this->UserLabelPrefix = "";
243 switch (Triple.getArch()) {
245 case llvm::Triple::x86:
246 case llvm::Triple::x86_64:
247 this->MCountName = ".mcount";
254 template<typename Target>
255 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
257 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
258 MacroBuilder &Builder) const override {
259 // FreeBSD defines; list based off of gcc output
261 unsigned Release = Triple.getOSMajorVersion();
265 Builder.defineMacro("__FreeBSD__", Twine(Release));
266 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
267 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
268 DefineStd(Builder, "unix", Opts);
269 Builder.defineMacro("__ELF__");
271 // On FreeBSD, wchar_t contains the number of the code point as
272 // used by the character set of the locale. These character sets are
273 // not necessarily a superset of ASCII.
274 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
277 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
278 this->UserLabelPrefix = "";
280 switch (Triple.getArch()) {
282 case llvm::Triple::x86:
283 case llvm::Triple::x86_64:
284 this->MCountName = ".mcount";
286 case llvm::Triple::mips:
287 case llvm::Triple::mipsel:
288 case llvm::Triple::ppc:
289 case llvm::Triple::ppc64:
290 case llvm::Triple::ppc64le:
291 this->MCountName = "_mcount";
293 case llvm::Triple::arm:
294 this->MCountName = "__mcount";
300 // GNU/kFreeBSD Target
301 template<typename Target>
302 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
304 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
305 MacroBuilder &Builder) const override {
306 // GNU/kFreeBSD defines; list based off of gcc output
308 DefineStd(Builder, "unix", Opts);
309 Builder.defineMacro("__FreeBSD_kernel__");
310 Builder.defineMacro("__GLIBC__");
311 Builder.defineMacro("__ELF__");
312 if (Opts.POSIXThreads)
313 Builder.defineMacro("_REENTRANT");
315 Builder.defineMacro("_GNU_SOURCE");
318 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
319 this->UserLabelPrefix = "";
324 template<typename Target>
325 class MinixTargetInfo : public OSTargetInfo<Target> {
327 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
328 MacroBuilder &Builder) const override {
331 Builder.defineMacro("__minix", "3");
332 Builder.defineMacro("_EM_WSIZE", "4");
333 Builder.defineMacro("_EM_PSIZE", "4");
334 Builder.defineMacro("_EM_SSIZE", "2");
335 Builder.defineMacro("_EM_LSIZE", "4");
336 Builder.defineMacro("_EM_FSIZE", "4");
337 Builder.defineMacro("_EM_DSIZE", "8");
338 Builder.defineMacro("__ELF__");
339 DefineStd(Builder, "unix", Opts);
342 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
343 this->UserLabelPrefix = "";
348 template<typename Target>
349 class LinuxTargetInfo : public OSTargetInfo<Target> {
351 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
352 MacroBuilder &Builder) const override {
353 // Linux defines; list based off of gcc output
354 DefineStd(Builder, "unix", Opts);
355 DefineStd(Builder, "linux", Opts);
356 Builder.defineMacro("__gnu_linux__");
357 Builder.defineMacro("__ELF__");
358 if (Triple.getEnvironment() == llvm::Triple::Android)
359 Builder.defineMacro("__ANDROID__", "1");
360 if (Opts.POSIXThreads)
361 Builder.defineMacro("_REENTRANT");
363 Builder.defineMacro("_GNU_SOURCE");
366 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
367 this->UserLabelPrefix = "";
368 this->WIntType = TargetInfo::UnsignedInt;
370 switch (Triple.getArch()) {
373 case llvm::Triple::ppc:
374 case llvm::Triple::ppc64:
375 case llvm::Triple::ppc64le:
376 this->MCountName = "_mcount";
381 const char *getStaticInitSectionSpecifier() const override {
382 return ".text.startup";
387 template<typename Target>
388 class NetBSDTargetInfo : public OSTargetInfo<Target> {
390 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
391 MacroBuilder &Builder) const override {
392 // NetBSD defines; list based off of gcc output
393 Builder.defineMacro("__NetBSD__");
394 Builder.defineMacro("__unix__");
395 Builder.defineMacro("__ELF__");
396 if (Opts.POSIXThreads)
397 Builder.defineMacro("_POSIX_THREADS");
399 switch (Triple.getArch()) {
402 case llvm::Triple::arm:
403 case llvm::Triple::armeb:
404 case llvm::Triple::thumb:
405 case llvm::Triple::thumbeb:
406 Builder.defineMacro("__ARM_DWARF_EH__");
411 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
412 this->UserLabelPrefix = "";
417 template<typename Target>
418 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
420 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
421 MacroBuilder &Builder) const override {
422 // OpenBSD defines; list based off of gcc output
424 Builder.defineMacro("__OpenBSD__");
425 DefineStd(Builder, "unix", Opts);
426 Builder.defineMacro("__ELF__");
427 if (Opts.POSIXThreads)
428 Builder.defineMacro("_REENTRANT");
431 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
432 this->UserLabelPrefix = "";
433 this->TLSSupported = false;
435 switch (Triple.getArch()) {
437 case llvm::Triple::x86:
438 case llvm::Triple::x86_64:
439 case llvm::Triple::arm:
440 case llvm::Triple::sparc:
441 this->MCountName = "__mcount";
443 case llvm::Triple::mips64:
444 case llvm::Triple::mips64el:
445 case llvm::Triple::ppc:
446 case llvm::Triple::sparcv9:
447 this->MCountName = "_mcount";
454 template<typename Target>
455 class BitrigTargetInfo : public OSTargetInfo<Target> {
457 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
458 MacroBuilder &Builder) const override {
459 // Bitrig defines; list based off of gcc output
461 Builder.defineMacro("__Bitrig__");
462 DefineStd(Builder, "unix", Opts);
463 Builder.defineMacro("__ELF__");
464 if (Opts.POSIXThreads)
465 Builder.defineMacro("_REENTRANT");
468 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
469 this->UserLabelPrefix = "";
470 this->MCountName = "__mcount";
475 template<typename Target>
476 class PSPTargetInfo : public OSTargetInfo<Target> {
478 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
479 MacroBuilder &Builder) const override {
480 // PSP defines; list based on the output of the pspdev gcc toolchain.
481 Builder.defineMacro("PSP");
482 Builder.defineMacro("_PSP");
483 Builder.defineMacro("__psp__");
484 Builder.defineMacro("__ELF__");
487 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
488 this->UserLabelPrefix = "";
493 template<typename Target>
494 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
496 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
497 MacroBuilder &Builder) const override {
499 Builder.defineMacro("__PPC__");
500 Builder.defineMacro("__PPU__");
501 Builder.defineMacro("__CELLOS_LV2__");
502 Builder.defineMacro("__ELF__");
503 Builder.defineMacro("__LP32__");
504 Builder.defineMacro("_ARCH_PPC64");
505 Builder.defineMacro("__powerpc64__");
508 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
509 this->UserLabelPrefix = "";
510 this->LongWidth = this->LongAlign = 32;
511 this->PointerWidth = this->PointerAlign = 32;
512 this->IntMaxType = TargetInfo::SignedLongLong;
513 this->Int64Type = TargetInfo::SignedLongLong;
514 this->SizeType = TargetInfo::UnsignedInt;
515 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
520 template<typename Target>
521 class AuroraUXTargetInfo : public OSTargetInfo<Target> {
523 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
524 MacroBuilder &Builder) const override {
525 DefineStd(Builder, "sun", Opts);
526 DefineStd(Builder, "unix", Opts);
527 Builder.defineMacro("__ELF__");
528 Builder.defineMacro("__svr4__");
529 Builder.defineMacro("__SVR4");
532 AuroraUXTargetInfo(const llvm::Triple &Triple)
533 : OSTargetInfo<Target>(Triple) {
534 this->UserLabelPrefix = "";
535 this->WCharType = this->SignedLong;
536 // FIXME: WIntType should be SignedLong
541 template<typename Target>
542 class SolarisTargetInfo : public OSTargetInfo<Target> {
544 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
545 MacroBuilder &Builder) const override {
546 DefineStd(Builder, "sun", Opts);
547 DefineStd(Builder, "unix", Opts);
548 Builder.defineMacro("__ELF__");
549 Builder.defineMacro("__svr4__");
550 Builder.defineMacro("__SVR4");
551 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
552 // newer, but to 500 for everything else. feature_test.h has a check to
553 // ensure that you are not using C99 with an old version of X/Open or C89
554 // with a new version.
555 if (Opts.C99 || Opts.C11)
556 Builder.defineMacro("_XOPEN_SOURCE", "600");
558 Builder.defineMacro("_XOPEN_SOURCE", "500");
560 Builder.defineMacro("__C99FEATURES__");
561 Builder.defineMacro("_LARGEFILE_SOURCE");
562 Builder.defineMacro("_LARGEFILE64_SOURCE");
563 Builder.defineMacro("__EXTENSIONS__");
564 Builder.defineMacro("_REENTRANT");
567 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
568 this->UserLabelPrefix = "";
569 this->WCharType = this->SignedInt;
570 // FIXME: WIntType should be SignedLong
575 template<typename Target>
576 class WindowsTargetInfo : public OSTargetInfo<Target> {
578 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
579 MacroBuilder &Builder) const override {
580 Builder.defineMacro("_WIN32");
582 void getVisualStudioDefines(const LangOptions &Opts,
583 MacroBuilder &Builder) const {
584 if (Opts.CPlusPlus) {
586 Builder.defineMacro("_CPPRTTI");
589 Builder.defineMacro("_CPPUNWIND");
592 if (!Opts.CharIsSigned)
593 Builder.defineMacro("_CHAR_UNSIGNED");
595 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
596 // but it works for now.
597 if (Opts.POSIXThreads)
598 Builder.defineMacro("_MT");
600 if (Opts.MSCompatibilityVersion) {
601 Builder.defineMacro("_MSC_VER",
602 Twine(Opts.MSCompatibilityVersion / 100000));
603 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
604 // FIXME We cannot encode the revision information into 32-bits
605 Builder.defineMacro("_MSC_BUILD", Twine(1));
608 if (Opts.MicrosoftExt) {
609 Builder.defineMacro("_MSC_EXTENSIONS");
611 if (Opts.CPlusPlus11) {
612 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
613 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
614 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
618 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
622 WindowsTargetInfo(const llvm::Triple &Triple)
623 : OSTargetInfo<Target>(Triple) {}
626 template <typename Target>
627 class NaClTargetInfo : public OSTargetInfo<Target> {
629 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
630 MacroBuilder &Builder) const override {
631 if (Opts.POSIXThreads)
632 Builder.defineMacro("_REENTRANT");
634 Builder.defineMacro("_GNU_SOURCE");
636 DefineStd(Builder, "unix", Opts);
637 Builder.defineMacro("__ELF__");
638 Builder.defineMacro("__native_client__");
642 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
643 this->UserLabelPrefix = "";
644 this->LongAlign = 32;
645 this->LongWidth = 32;
646 this->PointerAlign = 32;
647 this->PointerWidth = 32;
648 this->IntMaxType = TargetInfo::SignedLongLong;
649 this->Int64Type = TargetInfo::SignedLongLong;
650 this->DoubleAlign = 64;
651 this->LongDoubleWidth = 64;
652 this->LongDoubleAlign = 64;
653 this->LongLongWidth = 64;
654 this->LongLongAlign = 64;
655 this->SizeType = TargetInfo::UnsignedInt;
656 this->PtrDiffType = TargetInfo::SignedInt;
657 this->IntPtrType = TargetInfo::SignedInt;
658 // RegParmMax is inherited from the underlying architecture
659 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
660 if (Triple.getArch() == llvm::Triple::arm) {
661 this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S128";
662 } else if (Triple.getArch() == llvm::Triple::x86) {
663 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
664 } else if (Triple.getArch() == llvm::Triple::x86_64) {
665 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
666 } else if (Triple.getArch() == llvm::Triple::mipsel) {
667 // Handled on mips' setDescriptionString.
669 assert(Triple.getArch() == llvm::Triple::le32);
670 this->DescriptionString = "e-p:32:32-i64:64";
673 typename Target::CallingConvCheckResult checkCallingConvention(
674 CallingConv CC) const override {
675 return CC == CC_PnaclCall ? Target::CCCR_OK :
676 Target::checkCallingConvention(CC);
679 } // end anonymous namespace.
681 //===----------------------------------------------------------------------===//
682 // Specific target implementations.
683 //===----------------------------------------------------------------------===//
686 // PPC abstract base class
687 class PPCTargetInfo : public TargetInfo {
688 static const Builtin::Info BuiltinInfo[];
689 static const char * const GCCRegNames[];
690 static const TargetInfo::GCCRegAlias GCCRegAliases[];
693 // Target cpu features.
697 PPCTargetInfo(const llvm::Triple &Triple)
698 : TargetInfo(Triple), HasVSX(false) {
699 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
700 LongDoubleWidth = LongDoubleAlign = 128;
701 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
704 /// \brief Flags for architecture specific defines.
707 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
708 ArchDefinePpcgr = 1 << 1,
709 ArchDefinePpcsq = 1 << 2,
710 ArchDefine440 = 1 << 3,
711 ArchDefine603 = 1 << 4,
712 ArchDefine604 = 1 << 5,
713 ArchDefinePwr4 = 1 << 6,
714 ArchDefinePwr5 = 1 << 7,
715 ArchDefinePwr5x = 1 << 8,
716 ArchDefinePwr6 = 1 << 9,
717 ArchDefinePwr6x = 1 << 10,
718 ArchDefinePwr7 = 1 << 11,
719 ArchDefinePwr8 = 1 << 12,
720 ArchDefineA2 = 1 << 13,
721 ArchDefineA2q = 1 << 14
724 // Note: GCC recognizes the following additional cpus:
725 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
726 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
728 bool setCPU(const std::string &Name) override {
729 bool CPUKnown = llvm::StringSwitch<bool>(Name)
730 .Case("generic", true)
752 .Case("e500mc", true)
754 .Case("power3", true)
756 .Case("power4", true)
758 .Case("power5", true)
760 .Case("power5x", true)
762 .Case("power6", true)
764 .Case("power6x", true)
766 .Case("power7", true)
768 .Case("power8", true)
770 .Case("powerpc", true)
772 .Case("powerpc64", true)
774 .Case("powerpc64le", true)
775 .Case("ppc64le", true)
784 void getTargetBuiltins(const Builtin::Info *&Records,
785 unsigned &NumRecords) const override {
786 Records = BuiltinInfo;
787 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
790 bool isCLZForZeroUndef() const override { return false; }
792 void getTargetDefines(const LangOptions &Opts,
793 MacroBuilder &Builder) const override;
795 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
797 bool handleTargetFeatures(std::vector<std::string> &Features,
798 DiagnosticsEngine &Diags) override;
799 bool hasFeature(StringRef Feature) const override;
801 void getGCCRegNames(const char * const *&Names,
802 unsigned &NumNames) const override;
803 void getGCCRegAliases(const GCCRegAlias *&Aliases,
804 unsigned &NumAliases) const override;
805 bool validateAsmConstraint(const char *&Name,
806 TargetInfo::ConstraintInfo &Info) const override {
808 default: return false;
811 case 'b': // Base register
812 case 'f': // Floating point register
813 Info.setAllowsRegister();
815 // FIXME: The following are added to allow parsing.
816 // I just took a guess at what the actions should be.
817 // Also, is more specific checking needed? I.e. specific registers?
818 case 'd': // Floating point register (containing 64-bit value)
819 case 'v': // Altivec vector register
820 Info.setAllowsRegister();
824 case 'd':// VSX vector register to hold vector double data
825 case 'f':// VSX vector register to hold vector float data
826 case 's':// VSX vector register to hold scalar float data
827 case 'a':// Any VSX register
828 case 'c':// An individual CR bit
833 Info.setAllowsRegister();
834 Name++; // Skip over 'w'.
836 case 'h': // `MQ', `CTR', or `LINK' register
837 case 'q': // `MQ' register
838 case 'c': // `CTR' register
839 case 'l': // `LINK' register
840 case 'x': // `CR' register (condition register) number 0
841 case 'y': // `CR' register (condition register)
842 case 'z': // `XER[CA]' carry bit (part of the XER register)
843 Info.setAllowsRegister();
845 case 'I': // Signed 16-bit constant
846 case 'J': // Unsigned 16-bit constant shifted left 16 bits
847 // (use `L' instead for SImode constants)
848 case 'K': // Unsigned 16-bit constant
849 case 'L': // Signed 16-bit constant shifted left 16 bits
850 case 'M': // Constant larger than 31
851 case 'N': // Exact power of 2
852 case 'P': // Constant whose negation is a signed 16-bit constant
853 case 'G': // Floating point constant that can be loaded into a
854 // register with one instruction per word
855 case 'H': // Integer/Floating point constant that can be loaded
856 // into a register using three instructions
858 case 'm': // Memory operand. Note that on PowerPC targets, m can
859 // include addresses that update the base register. It
860 // is therefore only safe to use `m' in an asm statement
861 // if that asm statement accesses the operand exactly once.
862 // The asm statement must also use `%U<opno>' as a
863 // placeholder for the "update" flag in the corresponding
864 // load or store instruction. For example:
865 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
867 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
868 // is not. Use es rather than m if you don't want the base
869 // register to be updated.
873 // es: A "stable" memory operand; that is, one which does not
874 // include any automodification of the base register. Unlike
875 // `m', this constraint can be used in asm statements that
876 // might access the operand several times, or that might not
878 Info.setAllowsMemory();
879 Name++; // Skip over 'e'.
881 case 'Q': // Memory operand that is an offset from a register (it is
882 // usually better to use `m' or `es' in asm statements)
883 case 'Z': // Memory operand that is an indexed or indirect from a
884 // register (it is usually better to use `m' or `es' in
886 Info.setAllowsMemory();
887 Info.setAllowsRegister();
889 case 'R': // AIX TOC entry
890 case 'a': // Address operand that is an indexed or indirect from a
891 // register (`p' is preferable for asm statements)
892 case 'S': // Constant suitable as a 64-bit mask operand
893 case 'T': // Constant suitable as a 32-bit mask operand
894 case 'U': // System V Release 4 small data area reference
895 case 't': // AND masks that can be performed by two rldic{l, r}
897 case 'W': // Vector constant that does not require memory
898 case 'j': // Vector constant that is all zeros.
904 std::string convertConstraint(const char *&Constraint) const override {
906 switch (*Constraint) {
909 // Two-character constraint; add "^" hint for later parsing.
910 R = std::string("^") + std::string(Constraint, 2);
914 return TargetInfo::convertConstraint(Constraint);
918 const char *getClobbers() const override {
921 int getEHDataRegisterNumber(unsigned RegNo) const override {
922 if (RegNo == 0) return 3;
923 if (RegNo == 1) return 4;
928 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
929 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
930 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
932 #include "clang/Basic/BuiltinsPPC.def"
935 /// handleTargetFeatures - Perform initialization based on the user
936 /// configured set of features.
937 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
938 DiagnosticsEngine &Diags) {
939 // Remember the maximum enabled sselevel.
940 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
941 // Ignore disabled features.
942 if (Features[i][0] == '-')
945 StringRef Feature = StringRef(Features[i]).substr(1);
947 if (Feature == "vsx") {
952 // TODO: Finish this list and add an assert that we've handled them
959 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
960 /// #defines that are not tied to a specific subtarget.
961 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
962 MacroBuilder &Builder) const {
963 // Target identification.
964 Builder.defineMacro("__ppc__");
965 Builder.defineMacro("__PPC__");
966 Builder.defineMacro("_ARCH_PPC");
967 Builder.defineMacro("__powerpc__");
968 Builder.defineMacro("__POWERPC__");
969 if (PointerWidth == 64) {
970 Builder.defineMacro("_ARCH_PPC64");
971 Builder.defineMacro("__powerpc64__");
972 Builder.defineMacro("__ppc64__");
973 Builder.defineMacro("__PPC64__");
976 // Target properties.
977 if (getTriple().getArch() == llvm::Triple::ppc64le) {
978 Builder.defineMacro("_LITTLE_ENDIAN");
979 Builder.defineMacro("_CALL_ELF","2");
981 if (getTriple().getOS() != llvm::Triple::NetBSD &&
982 getTriple().getOS() != llvm::Triple::OpenBSD)
983 Builder.defineMacro("_BIG_ENDIAN");
986 // Subtarget options.
987 Builder.defineMacro("__NATURAL_ALIGNMENT__");
988 Builder.defineMacro("__REGISTER_PREFIX__", "");
990 // FIXME: Should be controlled by command line option.
991 if (LongDoubleWidth == 128)
992 Builder.defineMacro("__LONG_DOUBLE_128__");
995 Builder.defineMacro("__VEC__", "10206");
996 Builder.defineMacro("__ALTIVEC__");
999 // CPU identification.
1000 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1001 .Case("440", ArchDefineName)
1002 .Case("450", ArchDefineName | ArchDefine440)
1003 .Case("601", ArchDefineName)
1004 .Case("602", ArchDefineName | ArchDefinePpcgr)
1005 .Case("603", ArchDefineName | ArchDefinePpcgr)
1006 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1007 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1008 .Case("604", ArchDefineName | ArchDefinePpcgr)
1009 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1010 .Case("620", ArchDefineName | ArchDefinePpcgr)
1011 .Case("630", ArchDefineName | ArchDefinePpcgr)
1012 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1013 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1014 .Case("750", ArchDefineName | ArchDefinePpcgr)
1015 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1017 .Case("a2", ArchDefineA2)
1018 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1019 .Case("pwr3", ArchDefinePpcgr)
1020 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1021 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1023 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1024 | ArchDefinePpcgr | ArchDefinePpcsq)
1025 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1026 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1027 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1028 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1030 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1031 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1032 | ArchDefinePpcgr | ArchDefinePpcsq)
1033 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1034 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1035 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1036 .Case("power3", ArchDefinePpcgr)
1037 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1038 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1040 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1041 | ArchDefinePpcgr | ArchDefinePpcsq)
1042 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1043 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1044 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1045 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1047 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1048 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1049 | ArchDefinePpcgr | ArchDefinePpcsq)
1050 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1051 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1052 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1053 .Default(ArchDefineNone);
1055 if (defs & ArchDefineName)
1056 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1057 if (defs & ArchDefinePpcgr)
1058 Builder.defineMacro("_ARCH_PPCGR");
1059 if (defs & ArchDefinePpcsq)
1060 Builder.defineMacro("_ARCH_PPCSQ");
1061 if (defs & ArchDefine440)
1062 Builder.defineMacro("_ARCH_440");
1063 if (defs & ArchDefine603)
1064 Builder.defineMacro("_ARCH_603");
1065 if (defs & ArchDefine604)
1066 Builder.defineMacro("_ARCH_604");
1067 if (defs & ArchDefinePwr4)
1068 Builder.defineMacro("_ARCH_PWR4");
1069 if (defs & ArchDefinePwr5)
1070 Builder.defineMacro("_ARCH_PWR5");
1071 if (defs & ArchDefinePwr5x)
1072 Builder.defineMacro("_ARCH_PWR5X");
1073 if (defs & ArchDefinePwr6)
1074 Builder.defineMacro("_ARCH_PWR6");
1075 if (defs & ArchDefinePwr6x)
1076 Builder.defineMacro("_ARCH_PWR6X");
1077 if (defs & ArchDefinePwr7)
1078 Builder.defineMacro("_ARCH_PWR7");
1079 if (defs & ArchDefinePwr8)
1080 Builder.defineMacro("_ARCH_PWR8");
1081 if (defs & ArchDefineA2)
1082 Builder.defineMacro("_ARCH_A2");
1083 if (defs & ArchDefineA2q) {
1084 Builder.defineMacro("_ARCH_A2Q");
1085 Builder.defineMacro("_ARCH_QP");
1088 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1089 Builder.defineMacro("__bg__");
1090 Builder.defineMacro("__THW_BLUEGENE__");
1091 Builder.defineMacro("__bgq__");
1092 Builder.defineMacro("__TOS_BGQ__");
1096 Builder.defineMacro("__VSX__");
1098 // FIXME: The following are not yet generated here by Clang, but are
1099 // generated by GCC:
1102 // __RECIP_PRECISION__
1103 // __APPLE_ALTIVEC__
1112 // __CMODEL_MEDIUM__
1119 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1120 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1130 .Case("ppc64", true)
1131 .Case("ppc64le", true)
1134 Features["qpx"] = (CPU == "a2q");
1137 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1138 return Feature == "powerpc";
1142 const char * const PPCTargetInfo::GCCRegNames[] = {
1143 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1144 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1145 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1146 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1147 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1148 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1149 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1150 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1151 "mq", "lr", "ctr", "ap",
1152 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1154 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1155 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1156 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1157 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1159 "spe_acc", "spefscr",
1163 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1164 unsigned &NumNames) const {
1165 Names = GCCRegNames;
1166 NumNames = llvm::array_lengthof(GCCRegNames);
1169 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1170 // While some of these aliases do map to different registers
1171 // they still share the same register name.
1182 { { "10" }, "r10" },
1183 { { "11" }, "r11" },
1184 { { "12" }, "r12" },
1185 { { "13" }, "r13" },
1186 { { "14" }, "r14" },
1187 { { "15" }, "r15" },
1188 { { "16" }, "r16" },
1189 { { "17" }, "r17" },
1190 { { "18" }, "r18" },
1191 { { "19" }, "r19" },
1192 { { "20" }, "r20" },
1193 { { "21" }, "r21" },
1194 { { "22" }, "r22" },
1195 { { "23" }, "r23" },
1196 { { "24" }, "r24" },
1197 { { "25" }, "r25" },
1198 { { "26" }, "r26" },
1199 { { "27" }, "r27" },
1200 { { "28" }, "r28" },
1201 { { "29" }, "r29" },
1202 { { "30" }, "r30" },
1203 { { "31" }, "r31" },
1204 { { "fr0" }, "f0" },
1205 { { "fr1" }, "f1" },
1206 { { "fr2" }, "f2" },
1207 { { "fr3" }, "f3" },
1208 { { "fr4" }, "f4" },
1209 { { "fr5" }, "f5" },
1210 { { "fr6" }, "f6" },
1211 { { "fr7" }, "f7" },
1212 { { "fr8" }, "f8" },
1213 { { "fr9" }, "f9" },
1214 { { "fr10" }, "f10" },
1215 { { "fr11" }, "f11" },
1216 { { "fr12" }, "f12" },
1217 { { "fr13" }, "f13" },
1218 { { "fr14" }, "f14" },
1219 { { "fr15" }, "f15" },
1220 { { "fr16" }, "f16" },
1221 { { "fr17" }, "f17" },
1222 { { "fr18" }, "f18" },
1223 { { "fr19" }, "f19" },
1224 { { "fr20" }, "f20" },
1225 { { "fr21" }, "f21" },
1226 { { "fr22" }, "f22" },
1227 { { "fr23" }, "f23" },
1228 { { "fr24" }, "f24" },
1229 { { "fr25" }, "f25" },
1230 { { "fr26" }, "f26" },
1231 { { "fr27" }, "f27" },
1232 { { "fr28" }, "f28" },
1233 { { "fr29" }, "f29" },
1234 { { "fr30" }, "f30" },
1235 { { "fr31" }, "f31" },
1236 { { "cc" }, "cr0" },
1239 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1240 unsigned &NumAliases) const {
1241 Aliases = GCCRegAliases;
1242 NumAliases = llvm::array_lengthof(GCCRegAliases);
1244 } // end anonymous namespace.
1247 class PPC32TargetInfo : public PPCTargetInfo {
1249 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1250 DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1252 switch (getTriple().getOS()) {
1253 case llvm::Triple::Linux:
1254 case llvm::Triple::FreeBSD:
1255 case llvm::Triple::NetBSD:
1256 SizeType = UnsignedInt;
1257 PtrDiffType = SignedInt;
1258 IntPtrType = SignedInt;
1264 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1265 LongDoubleWidth = LongDoubleAlign = 64;
1266 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1269 // PPC32 supports atomics up to 4 bytes.
1270 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1273 BuiltinVaListKind getBuiltinVaListKind() const override {
1274 // This is the ELF definition, and is overridden by the Darwin sub-target
1275 return TargetInfo::PowerABIBuiltinVaList;
1278 } // end anonymous namespace.
1280 // Note: ABI differences may eventually require us to have a separate
1281 // TargetInfo for little endian.
1283 class PPC64TargetInfo : public PPCTargetInfo {
1285 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1286 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1287 IntMaxType = SignedLong;
1288 Int64Type = SignedLong;
1290 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1291 LongDoubleWidth = LongDoubleAlign = 64;
1292 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1293 DescriptionString = "E-m:e-i64:64-n32:64";
1295 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1296 DescriptionString = "e-m:e-i64:64-n32:64";
1298 DescriptionString = "E-m:e-i64:64-n32:64";
1302 // PPC64 supports atomics up to 8 bytes.
1303 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1305 BuiltinVaListKind getBuiltinVaListKind() const override {
1306 return TargetInfo::CharPtrBuiltinVaList;
1309 } // end anonymous namespace.
1313 class DarwinPPC32TargetInfo :
1314 public DarwinTargetInfo<PPC32TargetInfo> {
1316 DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1317 : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1318 HasAlignMac68kSupport = true;
1319 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1320 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1322 SuitableAlign = 128;
1323 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1325 BuiltinVaListKind getBuiltinVaListKind() const override {
1326 return TargetInfo::CharPtrBuiltinVaList;
1330 class DarwinPPC64TargetInfo :
1331 public DarwinTargetInfo<PPC64TargetInfo> {
1333 DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1334 : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1335 HasAlignMac68kSupport = true;
1336 SuitableAlign = 128;
1337 DescriptionString = "E-m:o-i64:64-n32:64";
1340 } // end anonymous namespace.
1343 static const unsigned NVPTXAddrSpaceMap[] = {
1346 4, // opencl_constant
1351 class NVPTXTargetInfo : public TargetInfo {
1352 static const char * const GCCRegNames[];
1353 static const Builtin::Info BuiltinInfo[];
1355 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1357 TLSSupported = false;
1358 LongWidth = LongAlign = 64;
1359 AddrSpaceMap = &NVPTXAddrSpaceMap;
1360 UseAddrSpaceMapMangling = true;
1361 // Define available target features
1362 // These must be defined in sorted order!
1363 NoAsmVariants = true;
1365 void getTargetDefines(const LangOptions &Opts,
1366 MacroBuilder &Builder) const override {
1367 Builder.defineMacro("__PTX__");
1368 Builder.defineMacro("__NVPTX__");
1370 void getTargetBuiltins(const Builtin::Info *&Records,
1371 unsigned &NumRecords) const override {
1372 Records = BuiltinInfo;
1373 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1375 bool hasFeature(StringRef Feature) const override {
1376 return Feature == "ptx" || Feature == "nvptx";
1379 void getGCCRegNames(const char * const *&Names,
1380 unsigned &NumNames) const override;
1381 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1382 unsigned &NumAliases) const override {
1387 bool validateAsmConstraint(const char *&Name,
1388 TargetInfo::ConstraintInfo &Info) const override {
1390 default: return false;
1397 Info.setAllowsRegister();
1401 const char *getClobbers() const override {
1402 // FIXME: Is this really right?
1405 BuiltinVaListKind getBuiltinVaListKind() const override {
1407 return TargetInfo::CharPtrBuiltinVaList;
1409 bool setCPU(const std::string &Name) override {
1410 bool Valid = llvm::StringSwitch<bool>(Name)
1411 .Case("sm_20", true)
1412 .Case("sm_21", true)
1413 .Case("sm_30", true)
1414 .Case("sm_35", true)
1421 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1422 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1423 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1425 #include "clang/Basic/BuiltinsNVPTX.def"
1428 const char * const NVPTXTargetInfo::GCCRegNames[] = {
1432 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1433 unsigned &NumNames) const {
1434 Names = GCCRegNames;
1435 NumNames = llvm::array_lengthof(GCCRegNames);
1438 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1440 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1441 PointerWidth = PointerAlign = 32;
1442 SizeType = PtrDiffType = TargetInfo::UnsignedInt;
1443 IntPtrType = TargetInfo::SignedInt;
1444 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1448 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1450 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1451 PointerWidth = PointerAlign = 64;
1452 SizeType = PtrDiffType = TargetInfo::UnsignedLongLong;
1453 IntPtrType = TargetInfo::SignedLongLong;
1454 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1461 static const unsigned R600AddrSpaceMap[] = {
1464 2, // opencl_constant
1470 static const char *DescriptionStringR600 =
1471 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1472 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1474 static const char *DescriptionStringR600DoubleOps =
1475 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1476 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1478 static const char *DescriptionStringSI =
1479 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1480 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1481 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1483 class R600TargetInfo : public TargetInfo {
1484 static const Builtin::Info BuiltinInfo[];
1486 /// \brief The GPU profiles supported by the R600 target.
1494 GK_EVERGREEN_DOUBLE_OPS,
1495 GK_NORTHERN_ISLANDS,
1497 GK_SOUTHERN_ISLANDS,
1502 R600TargetInfo(const llvm::Triple &Triple)
1503 : TargetInfo(Triple), GPU(GK_R600) {
1504 DescriptionString = DescriptionStringR600;
1505 AddrSpaceMap = &R600AddrSpaceMap;
1506 UseAddrSpaceMapMangling = true;
1509 const char * getClobbers() const override {
1513 void getGCCRegNames(const char * const *&Names,
1514 unsigned &numNames) const override {
1519 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1520 unsigned &NumAliases) const override {
1525 bool validateAsmConstraint(const char *&Name,
1526 TargetInfo::ConstraintInfo &info) const override {
1530 void getTargetBuiltins(const Builtin::Info *&Records,
1531 unsigned &NumRecords) const override {
1532 Records = BuiltinInfo;
1533 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;
1536 void getTargetDefines(const LangOptions &Opts,
1537 MacroBuilder &Builder) const override {
1538 Builder.defineMacro("__R600__");
1541 BuiltinVaListKind getBuiltinVaListKind() const override {
1542 return TargetInfo::CharPtrBuiltinVaList;
1545 bool setCPU(const std::string &Name) override {
1546 GPU = llvm::StringSwitch<GPUKind>(Name)
1547 .Case("r600" , GK_R600)
1548 .Case("rv610", GK_R600)
1549 .Case("rv620", GK_R600)
1550 .Case("rv630", GK_R600)
1551 .Case("rv635", GK_R600)
1552 .Case("rs780", GK_R600)
1553 .Case("rs880", GK_R600)
1554 .Case("rv670", GK_R600_DOUBLE_OPS)
1555 .Case("rv710", GK_R700)
1556 .Case("rv730", GK_R700)
1557 .Case("rv740", GK_R700_DOUBLE_OPS)
1558 .Case("rv770", GK_R700_DOUBLE_OPS)
1559 .Case("palm", GK_EVERGREEN)
1560 .Case("cedar", GK_EVERGREEN)
1561 .Case("sumo", GK_EVERGREEN)
1562 .Case("sumo2", GK_EVERGREEN)
1563 .Case("redwood", GK_EVERGREEN)
1564 .Case("juniper", GK_EVERGREEN)
1565 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
1566 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
1567 .Case("barts", GK_NORTHERN_ISLANDS)
1568 .Case("turks", GK_NORTHERN_ISLANDS)
1569 .Case("caicos", GK_NORTHERN_ISLANDS)
1570 .Case("cayman", GK_CAYMAN)
1571 .Case("aruba", GK_CAYMAN)
1572 .Case("tahiti", GK_SOUTHERN_ISLANDS)
1573 .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1574 .Case("verde", GK_SOUTHERN_ISLANDS)
1575 .Case("oland", GK_SOUTHERN_ISLANDS)
1576 .Case("bonaire", GK_SEA_ISLANDS)
1577 .Case("kabini", GK_SEA_ISLANDS)
1578 .Case("kaveri", GK_SEA_ISLANDS)
1579 .Case("hawaii", GK_SEA_ISLANDS)
1580 .Case("mullins", GK_SEA_ISLANDS)
1583 if (GPU == GK_NONE) {
1587 // Set the correct data layout
1593 case GK_NORTHERN_ISLANDS:
1594 DescriptionString = DescriptionStringR600;
1596 case GK_R600_DOUBLE_OPS:
1597 case GK_R700_DOUBLE_OPS:
1598 case GK_EVERGREEN_DOUBLE_OPS:
1600 DescriptionString = DescriptionStringR600DoubleOps;
1602 case GK_SOUTHERN_ISLANDS:
1603 case GK_SEA_ISLANDS:
1604 DescriptionString = DescriptionStringSI;
1612 const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
1613 #define BUILTIN(ID, TYPE, ATTRS) \
1614 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1615 #include "clang/Basic/BuiltinsR600.def"
1618 } // end anonymous namespace
1621 // Namespace for x86 abstract base class
1622 const Builtin::Info BuiltinInfo[] = {
1623 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1624 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1626 #include "clang/Basic/BuiltinsX86.def"
1629 static const char* const GCCRegNames[] = {
1630 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1631 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1632 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1633 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1634 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1635 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1636 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1637 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1638 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1641 const TargetInfo::AddlRegName AddlRegNames[] = {
1642 { { "al", "ah", "eax", "rax" }, 0 },
1643 { { "bl", "bh", "ebx", "rbx" }, 3 },
1644 { { "cl", "ch", "ecx", "rcx" }, 2 },
1645 { { "dl", "dh", "edx", "rdx" }, 1 },
1646 { { "esi", "rsi" }, 4 },
1647 { { "edi", "rdi" }, 5 },
1648 { { "esp", "rsp" }, 7 },
1649 { { "ebp", "rbp" }, 6 },
1652 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1653 // most of the implementation can be shared.
1654 class X86TargetInfo : public TargetInfo {
1656 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1659 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1681 bool HasAVX512CD, HasAVX512ER, HasAVX512PF;
1685 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1687 /// Each enumeration represents a particular CPU supported by Clang. These
1688 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1693 /// i386-generation processors.
1699 /// i486-generation processors.
1708 /// i586-generation processors, P5 microarchitecture based.
1716 /// i686-generation processors, P6 / Pentium M microarchitecture based.
1726 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1727 /// Clang however has some logic to suport this.
1728 // FIXME: Warn, deprecate, and potentially remove this.
1733 /// Netburst microarchitecture based processors.
1742 /// Core microarchitecture based processors.
1746 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1747 /// codename which GCC no longer accepts as an option to -march, but Clang
1748 /// has some logic for recognizing it.
1749 // FIXME: Warn, deprecate, and potentially remove this.
1761 /// Nehalem microarchitecture based processors.
1769 /// \name Knights Landing
1770 /// Knights Landing processor.
1774 /// K6 architecture processors.
1782 /// K7 architecture processors.
1785 CK_AthlonThunderbird,
1792 /// K8 architecture processors.
1805 /// Bobcat architecture processors.
1812 /// Bulldozer architecture processors.
1820 /// This specification is deprecated and will be removed in the future.
1821 /// Users should prefer \see CK_K8.
1822 // FIXME: Warn on this when the CPU is set to it.
1827 /// Geode processors.
1840 X86TargetInfo(const llvm::Triple &Triple)
1841 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1842 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
1843 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false),
1844 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false),
1845 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false),
1846 HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic),
1847 FPMath(FP_Default) {
1849 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1851 unsigned getFloatEvalMethod() const override {
1852 // X87 evaluates with 80 bits "long double" precision.
1853 return SSELevel == NoSSE ? 2 : 0;
1855 void getTargetBuiltins(const Builtin::Info *&Records,
1856 unsigned &NumRecords) const override {
1857 Records = BuiltinInfo;
1858 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1860 void getGCCRegNames(const char * const *&Names,
1861 unsigned &NumNames) const override {
1862 Names = GCCRegNames;
1863 NumNames = llvm::array_lengthof(GCCRegNames);
1865 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1866 unsigned &NumAliases) const override {
1870 void getGCCAddlRegNames(const AddlRegName *&Names,
1871 unsigned &NumNames) const override {
1872 Names = AddlRegNames;
1873 NumNames = llvm::array_lengthof(AddlRegNames);
1875 bool validateAsmConstraint(const char *&Name,
1876 TargetInfo::ConstraintInfo &info) const override;
1877 std::string convertConstraint(const char *&Constraint) const override;
1878 const char *getClobbers() const override {
1879 return "~{dirflag},~{fpsr},~{flags}";
1881 void getTargetDefines(const LangOptions &Opts,
1882 MacroBuilder &Builder) const override;
1883 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
1885 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
1887 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
1889 void setFeatureEnabled(llvm::StringMap<bool> &Features,
1890 StringRef Name, bool Enabled) const override {
1891 setFeatureEnabledImpl(Features, Name, Enabled);
1893 // This exists purely to cut down on the number of virtual calls in
1894 // getDefaultFeatures which calls this repeatedly.
1895 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
1896 StringRef Name, bool Enabled);
1897 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
1898 bool hasFeature(StringRef Feature) const override;
1899 bool handleTargetFeatures(std::vector<std::string> &Features,
1900 DiagnosticsEngine &Diags) override;
1901 StringRef getABI() const override {
1902 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1904 else if (getTriple().getArch() == llvm::Triple::x86 &&
1905 MMX3DNowLevel == NoMMX3DNow)
1909 bool setCPU(const std::string &Name) override {
1910 CPU = llvm::StringSwitch<CPUKind>(Name)
1911 .Case("i386", CK_i386)
1912 .Case("i486", CK_i486)
1913 .Case("winchip-c6", CK_WinChipC6)
1914 .Case("winchip2", CK_WinChip2)
1916 .Case("i586", CK_i586)
1917 .Case("pentium", CK_Pentium)
1918 .Case("pentium-mmx", CK_PentiumMMX)
1919 .Case("i686", CK_i686)
1920 .Case("pentiumpro", CK_PentiumPro)
1921 .Case("pentium2", CK_Pentium2)
1922 .Case("pentium3", CK_Pentium3)
1923 .Case("pentium3m", CK_Pentium3M)
1924 .Case("pentium-m", CK_PentiumM)
1925 .Case("c3-2", CK_C3_2)
1926 .Case("yonah", CK_Yonah)
1927 .Case("pentium4", CK_Pentium4)
1928 .Case("pentium4m", CK_Pentium4M)
1929 .Case("prescott", CK_Prescott)
1930 .Case("nocona", CK_Nocona)
1931 .Case("core2", CK_Core2)
1932 .Case("penryn", CK_Penryn)
1933 .Case("atom", CK_Atom)
1934 .Case("slm", CK_Silvermont)
1935 .Case("corei7", CK_Corei7)
1936 .Case("corei7-avx", CK_Corei7AVX)
1937 .Case("core-avx-i", CK_CoreAVXi)
1938 .Case("core-avx2", CK_CoreAVX2)
1939 .Case("knl", CK_KNL)
1941 .Case("k6-2", CK_K6_2)
1942 .Case("k6-3", CK_K6_3)
1943 .Case("athlon", CK_Athlon)
1944 .Case("athlon-tbird", CK_AthlonThunderbird)
1945 .Case("athlon-4", CK_Athlon4)
1946 .Case("athlon-xp", CK_AthlonXP)
1947 .Case("athlon-mp", CK_AthlonMP)
1948 .Case("athlon64", CK_Athlon64)
1949 .Case("athlon64-sse3", CK_Athlon64SSE3)
1950 .Case("athlon-fx", CK_AthlonFX)
1952 .Case("k8-sse3", CK_K8SSE3)
1953 .Case("opteron", CK_Opteron)
1954 .Case("opteron-sse3", CK_OpteronSSE3)
1955 .Case("amdfam10", CK_AMDFAM10)
1956 .Case("btver1", CK_BTVER1)
1957 .Case("btver2", CK_BTVER2)
1958 .Case("bdver1", CK_BDVER1)
1959 .Case("bdver2", CK_BDVER2)
1960 .Case("bdver3", CK_BDVER3)
1961 .Case("bdver4", CK_BDVER4)
1962 .Case("x86-64", CK_x86_64)
1963 .Case("geode", CK_Geode)
1964 .Default(CK_Generic);
1966 // Perform any per-CPU checks necessary to determine if this CPU is
1968 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1969 // invalid without explaining *why*.
1972 // No processor selected!
1998 case CK_AthlonThunderbird:
2003 // Only accept certain architectures when compiling in 32-bit mode.
2004 if (getTriple().getArch() != llvm::Triple::x86)
2019 case CK_Athlon64SSE3:
2024 case CK_OpteronSSE3:
2035 llvm_unreachable("Unhandled CPU kind");
2038 bool setFPMath(StringRef Name) override;
2040 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2041 // We accept all non-ARM calling conventions
2042 return (CC == CC_X86ThisCall ||
2043 CC == CC_X86FastCall ||
2044 CC == CC_X86StdCall ||
2046 CC == CC_X86Pascal ||
2047 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2050 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2051 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2055 bool X86TargetInfo::setFPMath(StringRef Name) {
2056 if (Name == "387") {
2060 if (Name == "sse") {
2067 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2068 // FIXME: This *really* should not be here.
2070 // X86_64 always has SSE2.
2071 if (getTriple().getArch() == llvm::Triple::x86_64)
2072 setFeatureEnabledImpl(Features, "sse2", true);
2085 setFeatureEnabledImpl(Features, "mmx", true);
2089 setFeatureEnabledImpl(Features, "sse", true);
2095 setFeatureEnabledImpl(Features, "sse2", true);
2100 setFeatureEnabledImpl(Features, "sse3", true);
2101 setFeatureEnabledImpl(Features, "cx16", true);
2104 setFeatureEnabledImpl(Features, "ssse3", true);
2105 setFeatureEnabledImpl(Features, "cx16", true);
2108 setFeatureEnabledImpl(Features, "sse4.1", true);
2109 setFeatureEnabledImpl(Features, "cx16", true);
2112 setFeatureEnabledImpl(Features, "ssse3", true);
2113 setFeatureEnabledImpl(Features, "cx16", true);
2116 setFeatureEnabledImpl(Features, "sse4.2", true);
2117 setFeatureEnabledImpl(Features, "aes", true);
2118 setFeatureEnabledImpl(Features, "cx16", true);
2119 setFeatureEnabledImpl(Features, "pclmul", true);
2122 setFeatureEnabledImpl(Features, "sse4.2", true);
2123 setFeatureEnabledImpl(Features, "cx16", true);
2126 setFeatureEnabledImpl(Features, "avx", true);
2127 setFeatureEnabledImpl(Features, "aes", true);
2128 setFeatureEnabledImpl(Features, "cx16", true);
2129 setFeatureEnabledImpl(Features, "pclmul", true);
2132 setFeatureEnabledImpl(Features, "avx", true);
2133 setFeatureEnabledImpl(Features, "aes", true);
2134 setFeatureEnabledImpl(Features, "pclmul", true);
2135 setFeatureEnabledImpl(Features, "rdrnd", true);
2136 setFeatureEnabledImpl(Features, "f16c", true);
2139 setFeatureEnabledImpl(Features, "avx2", true);
2140 setFeatureEnabledImpl(Features, "aes", true);
2141 setFeatureEnabledImpl(Features, "pclmul", true);
2142 setFeatureEnabledImpl(Features, "lzcnt", true);
2143 setFeatureEnabledImpl(Features, "rdrnd", true);
2144 setFeatureEnabledImpl(Features, "f16c", true);
2145 setFeatureEnabledImpl(Features, "bmi", true);
2146 setFeatureEnabledImpl(Features, "bmi2", true);
2147 setFeatureEnabledImpl(Features, "rtm", true);
2148 setFeatureEnabledImpl(Features, "fma", true);
2149 setFeatureEnabledImpl(Features, "cx16", true);
2152 setFeatureEnabledImpl(Features, "avx512f", true);
2153 setFeatureEnabledImpl(Features, "avx512cd", true);
2154 setFeatureEnabledImpl(Features, "avx512er", true);
2155 setFeatureEnabledImpl(Features, "avx512pf", true);
2156 setFeatureEnabledImpl(Features, "aes", true);
2157 setFeatureEnabledImpl(Features, "pclmul", true);
2158 setFeatureEnabledImpl(Features, "lzcnt", true);
2159 setFeatureEnabledImpl(Features, "rdrnd", true);
2160 setFeatureEnabledImpl(Features, "f16c", true);
2161 setFeatureEnabledImpl(Features, "bmi", true);
2162 setFeatureEnabledImpl(Features, "bmi2", true);
2163 setFeatureEnabledImpl(Features, "rtm", true);
2164 setFeatureEnabledImpl(Features, "fma", true);
2168 setFeatureEnabledImpl(Features, "mmx", true);
2174 setFeatureEnabledImpl(Features, "3dnow", true);
2177 case CK_AthlonThunderbird:
2179 setFeatureEnabledImpl(Features, "3dnowa", true);
2184 setFeatureEnabledImpl(Features, "sse", true);
2185 setFeatureEnabledImpl(Features, "3dnowa", true);
2191 setFeatureEnabledImpl(Features, "sse2", true);
2192 setFeatureEnabledImpl(Features, "3dnowa", true);
2195 case CK_OpteronSSE3:
2196 case CK_Athlon64SSE3:
2197 setFeatureEnabledImpl(Features, "sse3", true);
2198 setFeatureEnabledImpl(Features, "3dnowa", true);
2201 setFeatureEnabledImpl(Features, "sse3", true);
2202 setFeatureEnabledImpl(Features, "sse4a", true);
2203 setFeatureEnabledImpl(Features, "3dnowa", true);
2204 setFeatureEnabledImpl(Features, "lzcnt", true);
2205 setFeatureEnabledImpl(Features, "popcnt", true);
2208 setFeatureEnabledImpl(Features, "ssse3", true);
2209 setFeatureEnabledImpl(Features, "sse4a", true);
2210 setFeatureEnabledImpl(Features, "cx16", true);
2211 setFeatureEnabledImpl(Features, "lzcnt", true);
2212 setFeatureEnabledImpl(Features, "popcnt", true);
2213 setFeatureEnabledImpl(Features, "prfchw", true);
2216 setFeatureEnabledImpl(Features, "avx", true);
2217 setFeatureEnabledImpl(Features, "sse4a", true);
2218 setFeatureEnabledImpl(Features, "lzcnt", true);
2219 setFeatureEnabledImpl(Features, "aes", true);
2220 setFeatureEnabledImpl(Features, "pclmul", true);
2221 setFeatureEnabledImpl(Features, "prfchw", true);
2222 setFeatureEnabledImpl(Features, "bmi", true);
2223 setFeatureEnabledImpl(Features, "f16c", true);
2224 setFeatureEnabledImpl(Features, "cx16", true);
2227 setFeatureEnabledImpl(Features, "xop", true);
2228 setFeatureEnabledImpl(Features, "lzcnt", true);
2229 setFeatureEnabledImpl(Features, "aes", true);
2230 setFeatureEnabledImpl(Features, "pclmul", true);
2231 setFeatureEnabledImpl(Features, "prfchw", true);
2232 setFeatureEnabledImpl(Features, "cx16", true);
2235 setFeatureEnabledImpl(Features, "avx2", true);
2236 setFeatureEnabledImpl(Features, "bmi2", true);
2240 setFeatureEnabledImpl(Features, "xop", true);
2241 setFeatureEnabledImpl(Features, "lzcnt", true);
2242 setFeatureEnabledImpl(Features, "aes", true);
2243 setFeatureEnabledImpl(Features, "pclmul", true);
2244 setFeatureEnabledImpl(Features, "prfchw", true);
2245 setFeatureEnabledImpl(Features, "bmi", true);
2246 setFeatureEnabledImpl(Features, "fma", true);
2247 setFeatureEnabledImpl(Features, "f16c", true);
2248 setFeatureEnabledImpl(Features, "tbm", true);
2249 setFeatureEnabledImpl(Features, "cx16", true);
2252 setFeatureEnabledImpl(Features, "sse", true);
2257 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2258 X86SSEEnum Level, bool Enabled) {
2262 Features["avx512f"] = true;
2264 Features["avx2"] = true;
2266 Features["avx"] = true;
2268 Features["sse4.2"] = true;
2270 Features["sse4.1"] = true;
2272 Features["ssse3"] = true;
2274 Features["sse3"] = true;
2276 Features["sse2"] = true;
2278 Features["sse"] = true;
2288 Features["sse"] = false;
2290 Features["sse2"] = Features["pclmul"] = Features["aes"] =
2291 Features["sha"] = false;
2293 Features["sse3"] = false;
2294 setXOPLevel(Features, NoXOP, false);
2296 Features["ssse3"] = false;
2298 Features["sse4.1"] = false;
2300 Features["sse4.2"] = false;
2302 Features["fma"] = Features["avx"] = Features["f16c"] = false;
2303 setXOPLevel(Features, FMA4, false);
2305 Features["avx2"] = false;
2307 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2308 Features["avx512pf"] = false;
2312 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2313 MMX3DNowEnum Level, bool Enabled) {
2316 case AMD3DNowAthlon:
2317 Features["3dnowa"] = true;
2319 Features["3dnow"] = true;
2321 Features["mmx"] = true;
2331 Features["mmx"] = false;
2333 Features["3dnow"] = false;
2334 case AMD3DNowAthlon:
2335 Features["3dnowa"] = false;
2339 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2344 Features["xop"] = true;
2346 Features["fma4"] = true;
2347 setSSELevel(Features, AVX, true);
2349 Features["sse4a"] = true;
2350 setSSELevel(Features, SSE3, true);
2360 Features["sse4a"] = false;
2362 Features["fma4"] = false;
2364 Features["xop"] = false;
2368 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2369 StringRef Name, bool Enabled) {
2370 // FIXME: This *really* should not be here. We need some way of translating
2371 // options into llvm subtarget features.
2375 Features[Name] = Enabled;
2377 if (Name == "mmx") {
2378 setMMXLevel(Features, MMX, Enabled);
2379 } else if (Name == "sse") {
2380 setSSELevel(Features, SSE1, Enabled);
2381 } else if (Name == "sse2") {
2382 setSSELevel(Features, SSE2, Enabled);
2383 } else if (Name == "sse3") {
2384 setSSELevel(Features, SSE3, Enabled);
2385 } else if (Name == "ssse3") {
2386 setSSELevel(Features, SSSE3, Enabled);
2387 } else if (Name == "sse4.2") {
2388 setSSELevel(Features, SSE42, Enabled);
2389 } else if (Name == "sse4.1") {
2390 setSSELevel(Features, SSE41, Enabled);
2391 } else if (Name == "3dnow") {
2392 setMMXLevel(Features, AMD3DNow, Enabled);
2393 } else if (Name == "3dnowa") {
2394 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2395 } else if (Name == "aes") {
2397 setSSELevel(Features, SSE2, Enabled);
2398 } else if (Name == "pclmul") {
2400 setSSELevel(Features, SSE2, Enabled);
2401 } else if (Name == "avx") {
2402 setSSELevel(Features, AVX, Enabled);
2403 } else if (Name == "avx2") {
2404 setSSELevel(Features, AVX2, Enabled);
2405 } else if (Name == "avx512f") {
2406 setSSELevel(Features, AVX512F, Enabled);
2407 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") {
2409 setSSELevel(Features, AVX512F, Enabled);
2410 } else if (Name == "fma") {
2412 setSSELevel(Features, AVX, Enabled);
2413 } else if (Name == "fma4") {
2414 setXOPLevel(Features, FMA4, Enabled);
2415 } else if (Name == "xop") {
2416 setXOPLevel(Features, XOP, Enabled);
2417 } else if (Name == "sse4a") {
2418 setXOPLevel(Features, SSE4A, Enabled);
2419 } else if (Name == "f16c") {
2421 setSSELevel(Features, AVX, Enabled);
2422 } else if (Name == "sha") {
2424 setSSELevel(Features, SSE2, Enabled);
2428 /// handleTargetFeatures - Perform initialization based on the user
2429 /// configured set of features.
2430 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2431 DiagnosticsEngine &Diags) {
2432 // Remember the maximum enabled sselevel.
2433 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2434 // Ignore disabled features.
2435 if (Features[i][0] == '-')
2438 StringRef Feature = StringRef(Features[i]).substr(1);
2440 if (Feature == "aes") {
2445 if (Feature == "pclmul") {
2450 if (Feature == "lzcnt") {
2455 if (Feature == "rdrnd") {
2460 if (Feature == "bmi") {
2465 if (Feature == "bmi2") {
2470 if (Feature == "popcnt") {
2475 if (Feature == "rtm") {
2480 if (Feature == "prfchw") {
2485 if (Feature == "rdseed") {
2490 if (Feature == "tbm") {
2495 if (Feature == "fma") {
2500 if (Feature == "f16c") {
2505 if (Feature == "avx512cd") {
2510 if (Feature == "avx512er") {
2515 if (Feature == "avx512pf") {
2520 if (Feature == "sha") {
2525 if (Feature == "cx16") {
2530 assert(Features[i][0] == '+' && "Invalid target feature!");
2531 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2532 .Case("avx512f", AVX512F)
2535 .Case("sse4.2", SSE42)
2536 .Case("sse4.1", SSE41)
2537 .Case("ssse3", SSSE3)
2542 SSELevel = std::max(SSELevel, Level);
2544 MMX3DNowEnum ThreeDNowLevel =
2545 llvm::StringSwitch<MMX3DNowEnum>(Feature)
2546 .Case("3dnowa", AMD3DNowAthlon)
2547 .Case("3dnow", AMD3DNow)
2549 .Default(NoMMX3DNow);
2550 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2552 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2555 .Case("sse4a", SSE4A)
2557 XOPLevel = std::max(XOPLevel, XLevel);
2560 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2561 // Can't do this earlier because we need to be able to explicitly enable
2562 // popcnt and still disable sse4.2.
2563 if (!HasPOPCNT && SSELevel >= SSE42 &&
2564 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2566 Features.push_back("+popcnt");
2569 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2570 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2571 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2573 Features.push_back("+prfchw");
2576 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2577 // matches the selected sse level.
2578 if (FPMath == FP_SSE && SSELevel < SSE1) {
2579 Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2581 } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2582 Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2586 // Don't tell the backend if we're turning off mmx; it will end up disabling
2587 // SSE, which we don't want.
2588 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2590 std::vector<std::string>::iterator it;
2591 it = std::find(Features.begin(), Features.end(), "-mmx");
2592 if (it != Features.end())
2594 else if (SSELevel > NoSSE)
2595 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2599 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2600 /// definitions for this particular subtarget.
2601 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2602 MacroBuilder &Builder) const {
2603 // Target identification.
2604 if (getTriple().getArch() == llvm::Triple::x86_64) {
2605 Builder.defineMacro("__amd64__");
2606 Builder.defineMacro("__amd64");
2607 Builder.defineMacro("__x86_64");
2608 Builder.defineMacro("__x86_64__");
2610 DefineStd(Builder, "i386", Opts);
2613 // Subtarget options.
2614 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2615 // truly should be based on -mtune options.
2620 // The rest are coming from the i386 define above.
2621 Builder.defineMacro("__tune_i386__");
2627 defineCPUMacros(Builder, "i486");
2630 Builder.defineMacro("__pentium_mmx__");
2631 Builder.defineMacro("__tune_pentium_mmx__");
2635 defineCPUMacros(Builder, "i586");
2636 defineCPUMacros(Builder, "pentium");
2641 Builder.defineMacro("__tune_pentium3__");
2645 Builder.defineMacro("__tune_pentium2__");
2648 Builder.defineMacro("__tune_i686__");
2649 Builder.defineMacro("__tune_pentiumpro__");
2652 Builder.defineMacro("__i686");
2653 Builder.defineMacro("__i686__");
2654 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2655 Builder.defineMacro("__pentiumpro");
2656 Builder.defineMacro("__pentiumpro__");
2660 defineCPUMacros(Builder, "pentium4");
2665 defineCPUMacros(Builder, "nocona");
2669 defineCPUMacros(Builder, "core2");
2672 defineCPUMacros(Builder, "atom");
2675 defineCPUMacros(Builder, "slm");
2681 defineCPUMacros(Builder, "corei7");
2684 defineCPUMacros(Builder, "knl");
2687 Builder.defineMacro("__k6_2__");
2688 Builder.defineMacro("__tune_k6_2__");
2691 if (CPU != CK_K6_2) { // In case of fallthrough
2692 // FIXME: GCC may be enabling these in cases where some other k6
2693 // architecture is specified but -m3dnow is explicitly provided. The
2694 // exact semantics need to be determined and emulated here.
2695 Builder.defineMacro("__k6_3__");
2696 Builder.defineMacro("__tune_k6_3__");
2700 defineCPUMacros(Builder, "k6");
2703 case CK_AthlonThunderbird:
2707 defineCPUMacros(Builder, "athlon");
2708 if (SSELevel != NoSSE) {
2709 Builder.defineMacro("__athlon_sse__");
2710 Builder.defineMacro("__tune_athlon_sse__");
2717 case CK_OpteronSSE3:
2719 case CK_Athlon64SSE3:
2721 defineCPUMacros(Builder, "k8");
2724 defineCPUMacros(Builder, "amdfam10");
2727 defineCPUMacros(Builder, "btver1");
2730 defineCPUMacros(Builder, "btver2");
2733 defineCPUMacros(Builder, "bdver1");
2736 defineCPUMacros(Builder, "bdver2");
2739 defineCPUMacros(Builder, "bdver3");
2742 defineCPUMacros(Builder, "bdver4");
2745 defineCPUMacros(Builder, "geode");
2749 // Target properties.
2750 Builder.defineMacro("__REGISTER_PREFIX__", "");
2752 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2753 // functions in glibc header files that use FP Stack inline asm which the
2754 // backend can't deal with (PR879).
2755 Builder.defineMacro("__NO_MATH_INLINES");
2758 Builder.defineMacro("__AES__");
2761 Builder.defineMacro("__PCLMUL__");
2764 Builder.defineMacro("__LZCNT__");
2767 Builder.defineMacro("__RDRND__");
2770 Builder.defineMacro("__BMI__");
2773 Builder.defineMacro("__BMI2__");
2776 Builder.defineMacro("__POPCNT__");
2779 Builder.defineMacro("__RTM__");
2782 Builder.defineMacro("__PRFCHW__");
2785 Builder.defineMacro("__RDSEED__");
2788 Builder.defineMacro("__TBM__");
2792 Builder.defineMacro("__XOP__");
2794 Builder.defineMacro("__FMA4__");
2796 Builder.defineMacro("__SSE4A__");
2802 Builder.defineMacro("__FMA__");
2805 Builder.defineMacro("__F16C__");
2808 Builder.defineMacro("__AVX512CD__");
2810 Builder.defineMacro("__AVX512ER__");
2812 Builder.defineMacro("__AVX512PF__");
2815 Builder.defineMacro("__SHA__");
2818 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
2820 // Each case falls through to the previous one here.
2823 Builder.defineMacro("__AVX512F__");
2825 Builder.defineMacro("__AVX2__");
2827 Builder.defineMacro("__AVX__");
2829 Builder.defineMacro("__SSE4_2__");
2831 Builder.defineMacro("__SSE4_1__");
2833 Builder.defineMacro("__SSSE3__");
2835 Builder.defineMacro("__SSE3__");
2837 Builder.defineMacro("__SSE2__");
2838 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
2840 Builder.defineMacro("__SSE__");
2841 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
2846 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2856 Builder.defineMacro("_M_IX86_FP", Twine(2));
2859 Builder.defineMacro("_M_IX86_FP", Twine(1));
2862 Builder.defineMacro("_M_IX86_FP", Twine(0));
2866 // Each case falls through to the previous one here.
2867 switch (MMX3DNowLevel) {
2868 case AMD3DNowAthlon:
2869 Builder.defineMacro("__3dNOW_A__");
2871 Builder.defineMacro("__3dNOW__");
2873 Builder.defineMacro("__MMX__");
2878 if (CPU >= CK_i486) {
2879 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
2880 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
2881 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
2884 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
2887 bool X86TargetInfo::hasFeature(StringRef Feature) const {
2888 return llvm::StringSwitch<bool>(Feature)
2889 .Case("aes", HasAES)
2890 .Case("avx", SSELevel >= AVX)
2891 .Case("avx2", SSELevel >= AVX2)
2892 .Case("avx512f", SSELevel >= AVX512F)
2893 .Case("avx512cd", HasAVX512CD)
2894 .Case("avx512er", HasAVX512ER)
2895 .Case("avx512pf", HasAVX512PF)
2896 .Case("bmi", HasBMI)
2897 .Case("bmi2", HasBMI2)
2898 .Case("cx16", HasCX16)
2899 .Case("f16c", HasF16C)
2900 .Case("fma", HasFMA)
2901 .Case("fma4", XOPLevel >= FMA4)
2902 .Case("tbm", HasTBM)
2903 .Case("lzcnt", HasLZCNT)
2904 .Case("rdrnd", HasRDRND)
2905 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2906 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2907 .Case("mmx", MMX3DNowLevel >= MMX)
2908 .Case("pclmul", HasPCLMUL)
2909 .Case("popcnt", HasPOPCNT)
2910 .Case("rtm", HasRTM)
2911 .Case("prfchw", HasPRFCHW)
2912 .Case("rdseed", HasRDSEED)
2913 .Case("sha", HasSHA)
2914 .Case("sse", SSELevel >= SSE1)
2915 .Case("sse2", SSELevel >= SSE2)
2916 .Case("sse3", SSELevel >= SSE3)
2917 .Case("ssse3", SSELevel >= SSSE3)
2918 .Case("sse4.1", SSELevel >= SSE41)
2919 .Case("sse4.2", SSELevel >= SSE42)
2920 .Case("sse4a", XOPLevel >= SSE4A)
2922 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2923 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2924 .Case("xop", XOPLevel >= XOP)
2929 X86TargetInfo::validateAsmConstraint(const char *&Name,
2930 TargetInfo::ConstraintInfo &Info) const {
2932 default: return false;
2933 case 'Y': // first letter of a pair:
2934 switch (*(Name+1)) {
2935 default: return false;
2936 case '0': // First SSE register.
2937 case 't': // Any SSE register, when SSE2 is enabled.
2938 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
2939 case 'm': // any MMX register, when inter-unit moves enabled.
2940 break; // falls through to setAllowsRegister.
2942 case 'f': // any x87 floating point stack register.
2943 // Constraint 'f' cannot be used for output operands.
2944 if (Info.ConstraintStr[0] == '=')
2947 Info.setAllowsRegister();
2955 case 'A': // edx:eax.
2956 case 't': // top of floating point stack.
2957 case 'u': // second from top of floating point stack.
2958 case 'q': // Any register accessible as [r]l: a, b, c, and d.
2959 case 'y': // Any MMX register.
2960 case 'x': // Any SSE register.
2961 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2962 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2963 case 'l': // "Index" registers: any general register that can be used as an
2964 // index in a base+index memory access.
2965 Info.setAllowsRegister();
2967 case 'C': // SSE floating point constant.
2968 case 'G': // x87 floating point constant.
2969 case 'e': // 32-bit signed integer constant for use with zero-extending
2970 // x86_64 instructions.
2971 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2972 // x86_64 instructions.
2979 X86TargetInfo::convertConstraint(const char *&Constraint) const {
2980 switch (*Constraint) {
2981 case 'a': return std::string("{ax}");
2982 case 'b': return std::string("{bx}");
2983 case 'c': return std::string("{cx}");
2984 case 'd': return std::string("{dx}");
2985 case 'S': return std::string("{si}");
2986 case 'D': return std::string("{di}");
2987 case 'p': // address
2988 return std::string("im");
2989 case 't': // top of floating point stack.
2990 return std::string("{st}");
2991 case 'u': // second from top of floating point stack.
2992 return std::string("{st(1)}"); // second from top of floating point stack.
2994 return std::string(1, *Constraint);
2997 } // end anonymous namespace
3000 // X86-32 generic target
3001 class X86_32TargetInfo : public X86TargetInfo {
3003 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3004 DoubleAlign = LongLongAlign = 32;
3005 LongDoubleWidth = 96;
3006 LongDoubleAlign = 32;
3007 SuitableAlign = 128;
3008 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3009 SizeType = UnsignedInt;
3010 PtrDiffType = SignedInt;
3011 IntPtrType = SignedInt;
3014 // Use fpret for all types.
3015 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3016 (1 << TargetInfo::Double) |
3017 (1 << TargetInfo::LongDouble));
3019 // x86-32 has atomics up to 8 bytes
3020 // FIXME: Check that we actually have cmpxchg8b before setting
3021 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3022 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3024 BuiltinVaListKind getBuiltinVaListKind() const override {
3025 return TargetInfo::CharPtrBuiltinVaList;
3028 int getEHDataRegisterNumber(unsigned RegNo) const override {
3029 if (RegNo == 0) return 0;
3030 if (RegNo == 1) return 2;
3033 bool validateInputSize(StringRef Constraint,
3034 unsigned Size) const override {
3035 switch (Constraint[0]) {
3047 } // end anonymous namespace
3050 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3052 NetBSDI386TargetInfo(const llvm::Triple &Triple)
3053 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3055 unsigned getFloatEvalMethod() const override {
3056 unsigned Major, Minor, Micro;
3057 getTriple().getOSVersion(Major, Minor, Micro);
3058 // New NetBSD uses the default rounding mode.
3059 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3060 return X86_32TargetInfo::getFloatEvalMethod();
3061 // NetBSD before 6.99.26 defaults to "double" rounding.
3065 } // end anonymous namespace
3068 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3070 OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3071 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3072 SizeType = UnsignedLong;
3073 IntPtrType = SignedLong;
3074 PtrDiffType = SignedLong;
3077 } // end anonymous namespace
3080 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3082 BitrigI386TargetInfo(const llvm::Triple &Triple)
3083 : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3084 SizeType = UnsignedLong;
3085 IntPtrType = SignedLong;
3086 PtrDiffType = SignedLong;
3089 } // end anonymous namespace
3092 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3094 DarwinI386TargetInfo(const llvm::Triple &Triple)
3095 : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3096 LongDoubleWidth = 128;
3097 LongDoubleAlign = 128;
3098 SuitableAlign = 128;
3099 MaxVectorAlign = 256;
3100 SizeType = UnsignedLong;
3101 IntPtrType = SignedLong;
3102 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3103 HasAlignMac68kSupport = true;
3107 } // end anonymous namespace
3110 // x86-32 Windows target
3111 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3113 WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3114 : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3115 WCharType = UnsignedShort;
3116 DoubleAlign = LongLongAlign = 64;
3117 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3119 void getTargetDefines(const LangOptions &Opts,
3120 MacroBuilder &Builder) const override {
3121 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3125 // x86-32 Windows Visual Studio target
3126 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3128 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3129 : WindowsX86_32TargetInfo(Triple) {
3130 LongDoubleWidth = LongDoubleAlign = 64;
3131 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3133 void getTargetDefines(const LangOptions &Opts,
3134 MacroBuilder &Builder) const override {
3135 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3136 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3137 // The value of the following reflects processor type.
3138 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3139 // We lost the original triple, so we use the default.
3140 Builder.defineMacro("_M_IX86", "600");
3143 } // end anonymous namespace
3145 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3146 Builder.defineMacro("__MSVCRT__");
3147 Builder.defineMacro("__MINGW32__");
3149 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports
3150 // __declspec natively under -fms-extensions, but we define a no-op __declspec
3151 // macro anyway for pre-processor compatibility.
3152 if (Opts.MicrosoftExt)
3153 Builder.defineMacro("__declspec", "__declspec");
3155 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3157 if (!Opts.MicrosoftExt) {
3158 // Provide macros for all the calling convention keywords. Provide both
3159 // single and double underscore prefixed variants. These are available on
3160 // x64 as well as x86, even though they have no effect.
3161 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3162 for (const char *CC : CCs) {
3163 std::string GCCSpelling = "__attribute__((__";
3165 GCCSpelling += "__))";
3166 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3167 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3173 // x86-32 MinGW target
3174 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3176 MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3177 : WindowsX86_32TargetInfo(Triple) {}
3178 void getTargetDefines(const LangOptions &Opts,
3179 MacroBuilder &Builder) const override {
3180 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3181 DefineStd(Builder, "WIN32", Opts);
3182 DefineStd(Builder, "WINNT", Opts);
3183 Builder.defineMacro("_X86_");
3184 addMinGWDefines(Opts, Builder);
3187 } // end anonymous namespace
3190 // x86-32 Cygwin target
3191 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3193 CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3194 : X86_32TargetInfo(Triple) {
3195 TLSSupported = false;
3196 WCharType = UnsignedShort;
3197 DoubleAlign = LongLongAlign = 64;
3198 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3200 void getTargetDefines(const LangOptions &Opts,
3201 MacroBuilder &Builder) const override {
3202 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3203 Builder.defineMacro("_X86_");
3204 Builder.defineMacro("__CYGWIN__");
3205 Builder.defineMacro("__CYGWIN32__");
3206 DefineStd(Builder, "unix", Opts);
3208 Builder.defineMacro("_GNU_SOURCE");
3211 } // end anonymous namespace
3214 // x86-32 Haiku target
3215 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3217 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3218 SizeType = UnsignedLong;
3219 IntPtrType = SignedLong;
3220 PtrDiffType = SignedLong;
3221 ProcessIDType = SignedLong;
3222 this->UserLabelPrefix = "";
3223 this->TLSSupported = false;
3225 void getTargetDefines(const LangOptions &Opts,
3226 MacroBuilder &Builder) const override {
3227 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3228 Builder.defineMacro("__INTEL__");
3229 Builder.defineMacro("__HAIKU__");
3232 } // end anonymous namespace
3235 template<typename Target>
3236 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3238 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3239 MacroBuilder &Builder) const override {
3240 // RTEMS defines; list based off of gcc output
3242 Builder.defineMacro("__rtems__");
3243 Builder.defineMacro("__ELF__");
3247 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3248 this->UserLabelPrefix = "";
3250 switch (Triple.getArch()) {
3252 case llvm::Triple::x86:
3253 // this->MCountName = ".mcount";
3255 case llvm::Triple::mips:
3256 case llvm::Triple::mipsel:
3257 case llvm::Triple::ppc:
3258 case llvm::Triple::ppc64:
3259 case llvm::Triple::ppc64le:
3260 // this->MCountName = "_mcount";
3262 case llvm::Triple::arm:
3263 // this->MCountName = "__mcount";
3270 // x86-32 RTEMS target
3271 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3273 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3274 SizeType = UnsignedLong;
3275 IntPtrType = SignedLong;
3276 PtrDiffType = SignedLong;
3277 this->UserLabelPrefix = "";
3279 void getTargetDefines(const LangOptions &Opts,
3280 MacroBuilder &Builder) const override {
3281 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3282 Builder.defineMacro("__INTEL__");
3283 Builder.defineMacro("__rtems__");
3286 } // end anonymous namespace
3289 // x86-64 generic target
3290 class X86_64TargetInfo : public X86TargetInfo {
3292 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3293 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3294 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3295 LongDoubleWidth = 128;
3296 LongDoubleAlign = 128;
3297 LargeArrayMinWidth = 128;
3298 LargeArrayAlign = 128;
3299 SuitableAlign = 128;
3300 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
3301 PtrDiffType = IsX32 ? SignedInt : SignedLong;
3302 IntPtrType = IsX32 ? SignedInt : SignedLong;
3303 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
3304 Int64Type = IsX32 ? SignedLongLong : SignedLong;
3307 DescriptionString = (IsX32)
3308 ? "e-m:e-" "p:32:32-" "i64:64-f80:128-n8:16:32:64-S128"
3309 : "e-m:e-" "i64:64-f80:128-n8:16:32:64-S128";
3311 // Use fpret only for long double.
3312 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3314 // Use fp2ret for _Complex long double.
3315 ComplexLongDoubleUsesFP2Ret = true;
3317 // x86-64 has atomics up to 16 bytes.
3318 MaxAtomicPromoteWidth = 128;
3319 MaxAtomicInlineWidth = 128;
3321 BuiltinVaListKind getBuiltinVaListKind() const override {
3322 return TargetInfo::X86_64ABIBuiltinVaList;
3325 int getEHDataRegisterNumber(unsigned RegNo) const override {
3326 if (RegNo == 0) return 0;
3327 if (RegNo == 1) return 1;
3331 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3332 return (CC == CC_C ||
3333 CC == CC_IntelOclBicc ||
3334 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3337 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3342 } // end anonymous namespace
3345 // x86-64 Windows target
3346 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3348 WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3349 : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3350 WCharType = UnsignedShort;
3351 LongWidth = LongAlign = 32;
3352 DoubleAlign = LongLongAlign = 64;
3353 IntMaxType = SignedLongLong;
3354 Int64Type = SignedLongLong;
3355 SizeType = UnsignedLongLong;
3356 PtrDiffType = SignedLongLong;
3357 IntPtrType = SignedLongLong;
3358 this->UserLabelPrefix = "";
3360 void getTargetDefines(const LangOptions &Opts,
3361 MacroBuilder &Builder) const override {
3362 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3363 Builder.defineMacro("_WIN64");
3365 BuiltinVaListKind getBuiltinVaListKind() const override {
3366 return TargetInfo::CharPtrBuiltinVaList;
3368 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3369 return (CC == CC_C ||
3370 CC == CC_IntelOclBicc ||
3371 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
3374 } // end anonymous namespace
3377 // x86-64 Windows Visual Studio target
3378 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3380 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3381 : WindowsX86_64TargetInfo(Triple) {
3382 LongDoubleWidth = LongDoubleAlign = 64;
3383 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3385 void getTargetDefines(const LangOptions &Opts,
3386 MacroBuilder &Builder) const override {
3387 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3388 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3389 Builder.defineMacro("_M_X64");
3390 Builder.defineMacro("_M_AMD64");
3393 } // end anonymous namespace
3396 // x86-64 MinGW target
3397 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3399 MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3400 : WindowsX86_64TargetInfo(Triple) {}
3401 void getTargetDefines(const LangOptions &Opts,
3402 MacroBuilder &Builder) const override {
3403 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3404 DefineStd(Builder, "WIN64", Opts);
3405 Builder.defineMacro("__MINGW64__");
3406 addMinGWDefines(Opts, Builder);
3409 } // end anonymous namespace
3412 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3414 DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3415 : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3416 Int64Type = SignedLongLong;
3417 MaxVectorAlign = 256;
3418 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3419 llvm::Triple T = llvm::Triple(Triple);
3420 if (T.getOS() == llvm::Triple::IOS)
3421 UseSignedCharForObjCBool = false;
3422 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3425 } // end anonymous namespace
3428 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3430 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3431 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3432 IntMaxType = SignedLongLong;
3433 Int64Type = SignedLongLong;
3436 } // end anonymous namespace
3439 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3441 BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3442 : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3443 IntMaxType = SignedLongLong;
3444 Int64Type = SignedLongLong;
3451 class ARMTargetInfo : public TargetInfo {
3452 // Possible FPU choices.
3461 // Possible HWDiv features.
3463 HWDivThumb = (1 << 0),
3467 static bool FPUModeIsVFP(FPUMode Mode) {
3468 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3471 static const TargetInfo::GCCRegAlias GCCRegAliases[];
3472 static const char * const GCCRegNames[];
3474 std::string ABI, CPU;
3484 unsigned IsAAPCS : 1;
3485 unsigned IsThumb : 1;
3488 // Initialized via features.
3489 unsigned SoftFloat : 1;
3490 unsigned SoftFloatABI : 1;
3493 unsigned Crypto : 1;
3495 static const Builtin::Info BuiltinInfo[];
3497 static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3498 StringRef ArchName = T.getArchName();
3499 if (T.getArch() == llvm::Triple::arm ||
3500 T.getArch() == llvm::Triple::armeb) {
3501 StringRef VersionStr;
3502 if (ArchName.startswith("armv"))
3503 VersionStr = ArchName.substr(4, 1);
3504 else if (ArchName.startswith("armebv"))
3505 VersionStr = ArchName.substr(6, 1);
3509 if (VersionStr.getAsInteger(10, Version))
3511 return Version >= 6;
3513 assert(T.getArch() == llvm::Triple::thumb ||
3514 T.getArch() == llvm::Triple::thumbeb);
3515 StringRef VersionStr;
3516 if (ArchName.startswith("thumbv"))
3517 VersionStr = ArchName.substr(6, 1);
3518 else if (ArchName.startswith("thumbebv"))
3519 VersionStr = ArchName.substr(8, 1);
3523 if (VersionStr.getAsInteger(10, Version))
3525 return Version >= 7;
3528 void setABIAAPCS() {
3531 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
3532 const llvm::Triple &T = getTriple();
3534 // size_t is unsigned long on Darwin and NetBSD.
3535 if (T.isOSDarwin() || T.getOS() == llvm::Triple::NetBSD)
3536 SizeType = UnsignedLong;
3538 SizeType = UnsignedInt;
3540 switch (T.getOS()) {
3541 case llvm::Triple::NetBSD:
3542 WCharType = SignedInt;
3544 case llvm::Triple::Win32:
3545 WCharType = UnsignedShort;
3547 case llvm::Triple::Linux:
3549 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3550 WCharType = UnsignedInt;
3554 UseBitFieldTypeAlignment = true;
3556 ZeroLengthBitfieldBoundary = 0;
3559 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3560 // so set preferred for small types to 32.
3561 if (T.isOSBinFormatMachO()) {
3562 DescriptionString = BigEndian ?
3563 "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
3564 "v128:64:128-a:0:32-n32-S64" :
3565 "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
3566 "v128:64:128-a:0:32-n32-S64";
3567 } else if (T.isOSWindows()) {
3568 // FIXME: this is invalid for WindowsCE
3569 assert(!BigEndian && "Windows on ARM does not support big endian");
3570 DescriptionString = "e"
3573 "-i1:8:32-i8:8:32-i16:16:32-i64:64"
3579 DescriptionString = BigEndian ?
3580 "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
3581 "v128:64:128-a:0:32-n32-S64" :
3582 "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
3583 "v128:64:128-a:0:32-n32-S64";
3586 if (T.isOSBinFormatMachO())
3587 DescriptionString = BigEndian ?
3588 "E-m:o-p:32:32-i64:64-v128:64:128-n32-S64" :
3589 "e-m:o-p:32:32-i64:64-v128:64:128-n32-S64";
3591 DescriptionString = BigEndian ?
3592 "E-m:e-p:32:32-i64:64-v128:64:128-n32-S64" :
3593 "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64";
3596 // FIXME: Enumerated types are variable width in straight AAPCS.
3600 const llvm::Triple &T = getTriple();
3604 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3606 // size_t is unsigned int on FreeBSD.
3607 if (T.getOS() == llvm::Triple::FreeBSD)
3608 SizeType = UnsignedInt;
3610 SizeType = UnsignedLong;
3612 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3613 WCharType = SignedInt;
3615 // Do not respect the alignment of bit-field types when laying out
3616 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3617 UseBitFieldTypeAlignment = false;
3619 /// gcc forces the alignment to 4 bytes, regardless of the type of the
3620 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
3622 ZeroLengthBitfieldBoundary = 32;
3625 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3626 // so set preferred for small types to 32.
3627 if (T.isOSBinFormatMachO())
3628 DescriptionString = BigEndian ?
3629 "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64"
3630 "-v64:32:64-v128:32:128-a:0:32-n32-S32" :
3631 "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64"
3632 "-v64:32:64-v128:32:128-a:0:32-n32-S32";
3634 DescriptionString = BigEndian ?
3635 "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64"
3636 "-v64:32:64-v128:32:128-a:0:32-n32-S32" :
3637 "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64"
3638 "-v64:32:64-v128:32:128-a:0:32-n32-S32";
3640 if (T.isOSBinFormatMachO())
3641 DescriptionString = BigEndian ?
3642 "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" :
3643 "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3645 DescriptionString = BigEndian ?
3646 "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" :
3647 "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3650 // FIXME: Override "preferred align" for double and long long.
3654 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
3655 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
3657 BigEndian = IsBigEndian;
3659 switch (getTriple().getOS()) {
3660 case llvm::Triple::NetBSD:
3661 PtrDiffType = SignedLong;
3664 PtrDiffType = SignedInt;
3668 // {} in inline assembly are neon specifiers, not assembly variant
3670 NoAsmVariants = true;
3672 // FIXME: Should we just treat this as a feature?
3673 IsThumb = getTriple().getArchName().startswith("thumb");
3675 setABI("aapcs-linux");
3677 // ARM targets default to using the ARM C++ ABI.
3678 TheCXXABI.set(TargetCXXABI::GenericARM);
3680 // ARM has atomics up to 8 bytes
3681 MaxAtomicPromoteWidth = 64;
3682 if (shouldUseInlineAtomic(getTriple()))
3683 MaxAtomicInlineWidth = 64;
3685 // Do force alignment of members that follow zero length bitfields. If
3686 // the alignment of the zero-length bitfield is greater than the member
3687 // that follows it, `bar', `bar' will be aligned as the type of the
3688 // zero length bitfield.
3689 UseZeroLengthBitfieldAlignment = true;
3691 StringRef getABI() const override { return ABI; }
3692 bool setABI(const std::string &Name) override {
3695 // The defaults (above) are for AAPCS, check if we need to change them.
3697 // FIXME: We need support for -meabi... we could just mangle it into the
3699 if (Name == "apcs-gnu") {
3703 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
3710 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
3712 Features["aapcs"] = true;
3714 Features["apcs"] = true;
3716 StringRef ArchName = getTriple().getArchName();
3717 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3718 Features["vfp2"] = true;
3719 else if (CPU == "cortex-a8" || CPU == "cortex-a9" ||
3720 CPU == "cortex-a9-mp") {
3721 Features["vfp3"] = true;
3722 Features["neon"] = true;
3724 else if (CPU == "cortex-a5") {
3725 Features["vfp4"] = true;
3726 Features["neon"] = true;
3727 } else if (CPU == "swift" || CPU == "cortex-a7" ||
3728 CPU == "cortex-a12" || CPU == "cortex-a15" ||
3730 Features["vfp4"] = true;
3731 Features["neon"] = true;
3732 Features["hwdiv"] = true;
3733 Features["hwdiv-arm"] = true;
3734 } else if (CPU == "cyclone") {
3735 Features["v8fp"] = true;
3736 Features["neon"] = true;
3737 Features["hwdiv"] = true;
3738 Features["hwdiv-arm"] = true;
3739 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
3740 Features["fp-armv8"] = true;
3741 Features["neon"] = true;
3742 Features["hwdiv"] = true;
3743 Features["hwdiv-arm"] = true;
3744 Features["crc"] = true;
3745 Features["crypto"] = true;
3746 } else if (CPU == "cortex-r5" ||
3747 // Enable the hwdiv extension for all v8a AArch32 cores by
3749 ArchName == "armv8a" || ArchName == "armv8" ||
3750 ArchName == "armebv8a" || ArchName == "armebv8" ||
3751 ArchName == "thumbv8a" || ArchName == "thumbv8" ||
3752 ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
3753 Features["hwdiv"] = true;
3754 Features["hwdiv-arm"] = true;
3755 } else if (CPU == "cortex-m3" || CPU == "cortex-m4") {
3756 Features["hwdiv"] = true;
3760 bool handleTargetFeatures(std::vector<std::string> &Features,
3761 DiagnosticsEngine &Diags) override {
3765 SoftFloat = SoftFloatABI = false;
3767 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3768 if (Features[i] == "+soft-float")
3770 else if (Features[i] == "+soft-float-abi")
3771 SoftFloatABI = true;
3772 else if (Features[i] == "+vfp2")
3774 else if (Features[i] == "+vfp3")
3776 else if (Features[i] == "+vfp4")
3778 else if (Features[i] == "+fp-armv8")
3780 else if (Features[i] == "+neon")
3782 else if (Features[i] == "+hwdiv")
3783 HWDiv |= HWDivThumb;
3784 else if (Features[i] == "+hwdiv-arm")
3786 else if (Features[i] == "+crc")
3788 else if (Features[i] == "+crypto")
3792 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
3793 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
3797 if (FPMath == FP_Neon)
3798 Features.push_back("+neonfp");
3799 else if (FPMath == FP_VFP)
3800 Features.push_back("-neonfp");
3802 // Remove front-end specific options which the backend handles differently.
3803 std::vector<std::string>::iterator it;
3804 it = std::find(Features.begin(), Features.end(), "+soft-float");
3805 if (it != Features.end())
3807 it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3808 if (it != Features.end())
3813 bool hasFeature(StringRef Feature) const override {
3814 return llvm::StringSwitch<bool>(Feature)
3816 .Case("softfloat", SoftFloat)
3817 .Case("thumb", IsThumb)
3818 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
3819 .Case("hwdiv", HWDiv & HWDivThumb)
3820 .Case("hwdiv-arm", HWDiv & HWDivARM)
3823 // FIXME: Should we actually have some table instead of these switches?
3824 static const char *getCPUDefineSuffix(StringRef Name) {
3825 return llvm::StringSwitch<const char*>(Name)
3826 .Cases("arm8", "arm810", "4")
3827 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3828 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3829 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3830 .Case("ep9312", "4T")
3831 .Cases("arm10tdmi", "arm1020t", "5T")
3832 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3833 .Case("arm926ej-s", "5TEJ")
3834 .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3835 .Cases("xscale", "iwmmxt", "5TE")
3836 .Case("arm1136j-s", "6J")
3837 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3838 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3839 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3840 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A")
3841 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "7A")
3842 .Cases("cortex-r4", "cortex-r5", "7R")
3843 .Case("swift", "7S")
3844 .Case("cyclone", "8A")
3845 .Case("cortex-m3", "7M")
3846 .Case("cortex-m4", "7EM")
3847 .Case("cortex-m0", "6M")
3848 .Cases("cortex-a53", "cortex-a57", "8A")
3851 static const char *getCPUProfile(StringRef Name) {
3852 return llvm::StringSwitch<const char*>(Name)
3853 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
3854 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "A")
3855 .Cases("cortex-a53", "cortex-a57", "A")
3856 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3857 .Cases("cortex-r4", "cortex-r5", "R")
3860 bool setCPU(const std::string &Name) override {
3861 if (!getCPUDefineSuffix(Name))
3864 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
3865 StringRef Profile = getCPUProfile(Name);
3866 if (Profile == "M" && MaxAtomicInlineWidth) {
3867 MaxAtomicPromoteWidth = 32;
3868 MaxAtomicInlineWidth = 32;
3874 bool setFPMath(StringRef Name) override;
3875 bool supportsThumb(StringRef ArchName, StringRef CPUArch,
3876 unsigned CPUArchVer) const {
3877 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
3878 (CPUArch.find('M') != StringRef::npos);
3880 bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
3881 unsigned CPUArchVer) const {
3882 // We check both CPUArchVer and ArchName because when only triple is
3883 // specified, the default CPU is arm1136j-s.
3884 return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
3885 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
3887 void getTargetDefines(const LangOptions &Opts,
3888 MacroBuilder &Builder) const override {
3889 // Target identification.
3890 Builder.defineMacro("__arm");
3891 Builder.defineMacro("__arm__");
3893 // Target properties.
3894 Builder.defineMacro("__REGISTER_PREFIX__", "");
3896 StringRef CPUArch = getCPUDefineSuffix(CPU);
3897 unsigned int CPUArchVer;
3898 if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) {
3899 llvm_unreachable("Invalid char for architecture version number");
3901 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3903 // ACLE 6.4.1 ARM/Thumb instruction set architecture
3904 StringRef CPUProfile = getCPUProfile(CPU);
3905 StringRef ArchName = getTriple().getArchName();
3907 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
3908 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3910 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
3911 // is not defined for the M-profile.
3912 // NOTE that the deffault profile is assumed to be 'A'
3913 if (CPUProfile.empty() || CPUProfile != "M")
3914 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
3916 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
3917 // Thumb ISA (including v6-M). It is set to 2 if the core supports the
3918 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
3919 if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
3920 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
3921 else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
3922 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
3924 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
3925 // instruction set such as ARM or Thumb.
3926 Builder.defineMacro("__ARM_32BIT_STATE", "1");
3928 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
3930 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
3931 if (!CPUProfile.empty())
3932 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
3935 Builder.defineMacro("__ARM_ACLE", "200");
3937 // Subtarget options.
3939 // FIXME: It's more complicated than this and we don't really support
3941 // Windows on ARM does not "support" interworking
3942 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
3943 Builder.defineMacro("__THUMB_INTERWORK__");
3945 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3946 // Embedded targets on Darwin follow AAPCS, but not EABI.
3947 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
3948 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
3949 Builder.defineMacro("__ARM_EABI__");
3950 Builder.defineMacro("__ARM_PCS", "1");
3952 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3953 Builder.defineMacro("__ARM_PCS_VFP", "1");
3957 Builder.defineMacro("__SOFTFP__");
3959 if (CPU == "xscale")
3960 Builder.defineMacro("__XSCALE__");
3963 Builder.defineMacro("__THUMBEL__");
3964 Builder.defineMacro("__thumb__");
3965 if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
3966 Builder.defineMacro("__thumb2__");
3968 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
3969 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
3971 // Note, this is always on in gcc, even though it doesn't make sense.
3972 Builder.defineMacro("__APCS_32__");
3974 if (FPUModeIsVFP((FPUMode) FPU)) {
3975 Builder.defineMacro("__VFP_FP__");
3977 Builder.defineMacro("__ARM_VFPV2__");
3979 Builder.defineMacro("__ARM_VFPV3__");
3981 Builder.defineMacro("__ARM_VFPV4__");
3984 // This only gets set when Neon instructions are actually available, unlike
3985 // the VFP define, hence the soft float and arch check. This is subtly
3986 // different from gcc, we follow the intent which was that it should be set
3987 // when Neon instructions are actually available.
3988 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
3989 Builder.defineMacro("__ARM_NEON");
3990 Builder.defineMacro("__ARM_NEON__");
3993 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
3994 Opts.ShortWChar ? "2" : "4");
3996 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
3997 Opts.ShortEnums ? "1" : "4");
4000 Builder.defineMacro("__ARM_FEATURE_CRC32");
4003 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4005 if (CPUArchVer >= 6 && CPUArch != "6M") {
4006 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4007 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4008 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4009 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4012 void getTargetBuiltins(const Builtin::Info *&Records,
4013 unsigned &NumRecords) const override {
4014 Records = BuiltinInfo;
4015 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4017 bool isCLZForZeroUndef() const override { return false; }
4018 BuiltinVaListKind getBuiltinVaListKind() const override {
4019 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4021 void getGCCRegNames(const char * const *&Names,
4022 unsigned &NumNames) const override;
4023 void getGCCRegAliases(const GCCRegAlias *&Aliases,
4024 unsigned &NumAliases) const override;
4025 bool validateAsmConstraint(const char *&Name,
4026 TargetInfo::ConstraintInfo &Info) const override {
4031 case 'w': // VFP Floating point register single precision
4032 case 'P': // VFP Floating point register double precision
4033 Info.setAllowsRegister();
4035 case 'Q': // A memory address that is a single base register.
4036 Info.setAllowsMemory();
4038 case 'U': // a memory reference...
4040 case 'q': // ...ARMV4 ldrsb
4041 case 'v': // ...VFP load/store (reg+constant offset)
4042 case 'y': // ...iWMMXt load/store
4043 case 't': // address valid for load/store opaque types wider
4045 case 'n': // valid address for Neon doubleword vector load/store
4046 case 'm': // valid address for Neon element and structure load/store
4047 case 's': // valid address for non-offset loads/stores of quad-word
4048 // values in four ARM registers
4049 Info.setAllowsMemory();
4056 std::string convertConstraint(const char *&Constraint) const override {
4058 switch (*Constraint) {
4059 case 'U': // Two-character constraint; add "^" hint for later parsing.
4060 R = std::string("^") + std::string(Constraint, 2);
4063 case 'p': // 'p' should be translated to 'r' by default.
4064 R = std::string("r");
4067 return std::string(1, *Constraint);
4071 bool validateConstraintModifier(StringRef Constraint, const char Modifier,
4072 unsigned Size) const override {
4073 bool isOutput = (Constraint[0] == '=');
4074 bool isInOut = (Constraint[0] == '+');
4076 // Strip off constraint modifiers.
4077 while (Constraint[0] == '=' ||
4078 Constraint[0] == '+' ||
4079 Constraint[0] == '&')
4080 Constraint = Constraint.substr(1);
4082 switch (Constraint[0]) {
4087 return (isInOut || isOutput || Size <= 64);
4089 // A register of size 32 cannot fit a vector type.
4097 const char *getClobbers() const override {
4098 // FIXME: Is this really right?
4102 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4103 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4106 int getEHDataRegisterNumber(unsigned RegNo) const override {
4107 if (RegNo == 0) return 0;
4108 if (RegNo == 1) return 1;
4113 bool ARMTargetInfo::setFPMath(StringRef Name) {
4114 if (Name == "neon") {
4117 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4125 const char * const ARMTargetInfo::GCCRegNames[] = {
4126 // Integer registers
4127 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4128 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4131 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4132 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4133 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4134 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4137 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4138 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4139 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4140 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4143 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4144 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4147 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4148 unsigned &NumNames) const {
4149 Names = GCCRegNames;
4150 NumNames = llvm::array_lengthof(GCCRegNames);
4153 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4163 { { "v6", "rfp" }, "r9" },
4164 { { "sl" }, "r10" },
4165 { { "fp" }, "r11" },
4166 { { "ip" }, "r12" },
4167 { { "r13" }, "sp" },
4168 { { "r14" }, "lr" },
4169 { { "r15" }, "pc" },
4170 // The S, D and Q registers overlap, but aren't really aliases; we
4171 // don't want to substitute one of these for a different-sized one.
4174 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4175 unsigned &NumAliases) const {
4176 Aliases = GCCRegAliases;
4177 NumAliases = llvm::array_lengthof(GCCRegAliases);
4180 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4181 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4182 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4184 #include "clang/Basic/BuiltinsNEON.def"
4186 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4187 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4188 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4190 #include "clang/Basic/BuiltinsARM.def"
4193 class ARMleTargetInfo : public ARMTargetInfo {
4195 ARMleTargetInfo(const llvm::Triple &Triple)
4196 : ARMTargetInfo(Triple, false) { }
4197 virtual void getTargetDefines(const LangOptions &Opts,
4198 MacroBuilder &Builder) const {
4199 Builder.defineMacro("__ARMEL__");
4200 ARMTargetInfo::getTargetDefines(Opts, Builder);
4204 class ARMbeTargetInfo : public ARMTargetInfo {
4206 ARMbeTargetInfo(const llvm::Triple &Triple)
4207 : ARMTargetInfo(Triple, true) { }
4208 virtual void getTargetDefines(const LangOptions &Opts,
4209 MacroBuilder &Builder) const {
4210 Builder.defineMacro("__ARMEB__");
4211 Builder.defineMacro("__ARM_BIG_ENDIAN");
4212 ARMTargetInfo::getTargetDefines(Opts, Builder);
4215 } // end anonymous namespace.
4218 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4219 const llvm::Triple Triple;
4221 WindowsARMTargetInfo(const llvm::Triple &Triple)
4222 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4223 TLSSupported = false;
4224 WCharType = UnsignedShort;
4225 SizeType = UnsignedInt;
4226 UserLabelPrefix = "";
4228 void getVisualStudioDefines(const LangOptions &Opts,
4229 MacroBuilder &Builder) const {
4230 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4232 // FIXME: this is invalid for WindowsCE
4233 Builder.defineMacro("_M_ARM_NT", "1");
4234 Builder.defineMacro("_M_ARMT", "_M_ARM");
4235 Builder.defineMacro("_M_THUMB", "_M_ARM");
4237 assert((Triple.getArch() == llvm::Triple::arm ||
4238 Triple.getArch() == llvm::Triple::thumb) &&
4239 "invalid architecture for Windows ARM target info");
4240 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4241 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4243 // TODO map the complete set of values
4244 // 31: VFPv3 40: VFPv4
4245 Builder.defineMacro("_M_ARM_FP", "31");
4247 BuiltinVaListKind getBuiltinVaListKind() const override {
4248 return TargetInfo::CharPtrBuiltinVaList;
4252 // Windows ARM + Itanium C++ ABI Target
4253 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4255 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4256 : WindowsARMTargetInfo(Triple) {
4257 TheCXXABI.set(TargetCXXABI::GenericARM);
4260 void getTargetDefines(const LangOptions &Opts,
4261 MacroBuilder &Builder) const override {
4262 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4264 if (Opts.MSVCCompat)
4265 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4269 // Windows ARM, MS (C++) ABI
4270 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4272 MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4273 : WindowsARMTargetInfo(Triple) {
4274 TheCXXABI.set(TargetCXXABI::Microsoft);
4277 void getTargetDefines(const LangOptions &Opts,
4278 MacroBuilder &Builder) const override {
4279 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4280 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4287 class DarwinARMTargetInfo :
4288 public DarwinTargetInfo<ARMleTargetInfo> {
4290 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4291 MacroBuilder &Builder) const override {
4292 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4296 DarwinARMTargetInfo(const llvm::Triple &Triple)
4297 : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4298 HasAlignMac68kSupport = true;
4299 // iOS always has 64-bit atomic instructions.
4300 // FIXME: This should be based off of the target features in ARMleTargetInfo.
4301 MaxAtomicInlineWidth = 64;
4303 // Darwin on iOS uses a variant of the ARM C++ ABI.
4304 TheCXXABI.set(TargetCXXABI::iOS);
4307 } // end anonymous namespace.
4311 class AArch64TargetInfo : public TargetInfo {
4312 virtual void setDescriptionString() = 0;
4313 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4314 static const char *const GCCRegNames[];
4325 static const Builtin::Info BuiltinInfo[];
4330 AArch64TargetInfo(const llvm::Triple &Triple)
4331 : TargetInfo(Triple), ABI("aapcs") {
4333 if (getTriple().getOS() == llvm::Triple::NetBSD) {
4334 WCharType = SignedInt;
4336 // NetBSD apparently prefers consistency across ARM targets to consistency
4337 // across 64-bit targets.
4338 Int64Type = SignedLongLong;
4339 IntMaxType = SignedLongLong;
4341 WCharType = UnsignedInt;
4342 Int64Type = SignedLong;
4343 IntMaxType = SignedLong;
4346 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4347 MaxVectorAlign = 128;
4349 MaxAtomicInlineWidth = 128;
4350 MaxAtomicPromoteWidth = 128;
4352 LongDoubleWidth = LongDoubleAlign = 128;
4353 LongDoubleFormat = &llvm::APFloat::IEEEquad;
4355 // {} in inline assembly are neon specifiers, not assembly variant
4357 NoAsmVariants = true;
4359 // AArch64 targets default to using the ARM C++ ABI.
4360 TheCXXABI.set(TargetCXXABI::GenericAArch64);
4363 StringRef getABI() const override { return ABI; }
4364 virtual bool setABI(const std::string &Name) {
4365 if (Name != "aapcs" && Name != "darwinpcs")
4372 virtual bool setCPU(const std::string &Name) {
4373 bool CPUKnown = llvm::StringSwitch<bool>(Name)
4374 .Case("generic", true)
4375 .Cases("cortex-a53", "cortex-a57", true)
4376 .Case("cyclone", true)
4381 virtual void getTargetDefines(const LangOptions &Opts,
4382 MacroBuilder &Builder) const {
4383 // Target identification.
4384 Builder.defineMacro("__aarch64__");
4386 // Target properties.
4387 Builder.defineMacro("_LP64");
4388 Builder.defineMacro("__LP64__");
4390 // ACLE predefines. Many can only have one possible value on v8 AArch64.
4391 Builder.defineMacro("__ARM_ACLE", "200");
4392 Builder.defineMacro("__ARM_ARCH", "8");
4393 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4395 Builder.defineMacro("__ARM_64BIT_STATE");
4396 Builder.defineMacro("__ARM_PCS_AAPCS64");
4397 Builder.defineMacro("__ARM_ARCH_ISA_A64");
4399 Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4400 Builder.defineMacro("__ARM_FEATURE_CLZ");
4401 Builder.defineMacro("__ARM_FEATURE_FMA");
4402 Builder.defineMacro("__ARM_FEATURE_DIV");
4404 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4406 // 0xe implies support for half, single and double precision operations.
4407 Builder.defineMacro("__ARM_FP", "0xe");
4409 // PCS specifies this for SysV variants, which is all we support. Other ABIs
4410 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4411 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4413 if (Opts.FastMath || Opts.FiniteMathOnly)
4414 Builder.defineMacro("__ARM_FP_FAST");
4416 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
4417 Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4419 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4421 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4422 Opts.ShortEnums ? "1" : "4");
4424 if (FPU == NeonMode) {
4425 Builder.defineMacro("__ARM_NEON");
4426 // 64-bit NEON supports half, single and double precision operations.
4427 Builder.defineMacro("__ARM_NEON_FP", "0xe");
4431 Builder.defineMacro("__ARM_FEATURE_CRC32");
4434 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4437 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4438 unsigned &NumRecords) const {
4439 Records = BuiltinInfo;
4440 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
4443 virtual bool hasFeature(StringRef Feature) const {
4444 return Feature == "aarch64" ||
4445 Feature == "arm64" ||
4446 (Feature == "neon" && FPU == NeonMode);
4449 bool handleTargetFeatures(std::vector<std::string> &Features,
4450 DiagnosticsEngine &Diags) override {
4454 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
4455 if (Features[i] == "+neon")
4457 if (Features[i] == "+crc")
4459 if (Features[i] == "+crypto")
4463 setDescriptionString();
4468 virtual bool isCLZForZeroUndef() const { return false; }
4470 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4471 return TargetInfo::AArch64ABIBuiltinVaList;
4474 virtual void getGCCRegNames(const char *const *&Names,
4475 unsigned &NumNames) const;
4476 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4477 unsigned &NumAliases) const;
4479 virtual bool validateAsmConstraint(const char *&Name,
4480 TargetInfo::ConstraintInfo &Info) const {
4484 case 'w': // Floating point and SIMD registers (V0-V31)
4485 Info.setAllowsRegister();
4487 case 'I': // Constant that can be used with an ADD instruction
4488 case 'J': // Constant that can be used with a SUB instruction
4489 case 'K': // Constant that can be used with a 32-bit logical instruction
4490 case 'L': // Constant that can be used with a 64-bit logical instruction
4491 case 'M': // Constant that can be used as a 32-bit MOV immediate
4492 case 'N': // Constant that can be used as a 64-bit MOV immediate
4493 case 'Y': // Floating point constant zero
4494 case 'Z': // Integer constant zero
4496 case 'Q': // A memory reference with base register and no offset
4497 Info.setAllowsMemory();
4499 case 'S': // A symbolic address
4500 Info.setAllowsRegister();
4503 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
4504 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
4505 // Usa: An absolute symbolic address
4506 // Ush: The high part (bits 32:12) of a pc-relative symbolic address
4507 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
4508 case 'z': // Zero register, wzr or xzr
4509 Info.setAllowsRegister();
4511 case 'x': // Floating point and SIMD registers (V0-V15)
4512 Info.setAllowsRegister();
4518 virtual const char *getClobbers() const { return ""; }
4520 int getEHDataRegisterNumber(unsigned RegNo) const {
4529 const char *const AArch64TargetInfo::GCCRegNames[] = {
4530 // 32-bit Integer registers
4531 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
4532 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
4533 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
4535 // 64-bit Integer registers
4536 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
4537 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
4538 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
4540 // 32-bit floating point regsisters
4541 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
4542 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
4543 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4545 // 64-bit floating point regsisters
4546 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
4547 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
4548 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4551 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
4552 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
4553 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
4556 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
4557 unsigned &NumNames) const {
4558 Names = GCCRegNames;
4559 NumNames = llvm::array_lengthof(GCCRegNames);
4562 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
4563 { { "w31" }, "wsp" },
4564 { { "x29" }, "fp" },
4565 { { "x30" }, "lr" },
4566 { { "x31" }, "sp" },
4567 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
4568 // don't want to substitute one of these for a different-sized one.
4571 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4572 unsigned &NumAliases) const {
4573 Aliases = GCCRegAliases;
4574 NumAliases = llvm::array_lengthof(GCCRegAliases);
4577 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
4578 #define BUILTIN(ID, TYPE, ATTRS) \
4579 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4580 #include "clang/Basic/BuiltinsNEON.def"
4582 #define BUILTIN(ID, TYPE, ATTRS) \
4583 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4584 #include "clang/Basic/BuiltinsAArch64.def"
4587 class AArch64leTargetInfo : public AArch64TargetInfo {
4588 void setDescriptionString() override {
4589 if (getTriple().isOSBinFormatMachO())
4590 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
4592 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
4596 AArch64leTargetInfo(const llvm::Triple &Triple)
4597 : AArch64TargetInfo(Triple) {
4600 void getTargetDefines(const LangOptions &Opts,
4601 MacroBuilder &Builder) const override {
4602 Builder.defineMacro("__AARCH64EL__");
4603 AArch64TargetInfo::getTargetDefines(Opts, Builder);
4607 class AArch64beTargetInfo : public AArch64TargetInfo {
4608 void setDescriptionString() override {
4609 assert(!getTriple().isOSBinFormatMachO());
4610 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
4614 AArch64beTargetInfo(const llvm::Triple &Triple)
4615 : AArch64TargetInfo(Triple) { }
4616 void getTargetDefines(const LangOptions &Opts,
4617 MacroBuilder &Builder) const override {
4618 Builder.defineMacro("__AARCH64EB__");
4619 Builder.defineMacro("__AARCH_BIG_ENDIAN");
4620 Builder.defineMacro("__ARM_BIG_ENDIAN");
4621 AArch64TargetInfo::getTargetDefines(Opts, Builder);
4624 } // end anonymous namespace.
4627 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
4629 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4630 MacroBuilder &Builder) const override {
4631 Builder.defineMacro("__AARCH64_SIMD__");
4632 Builder.defineMacro("__ARM64_ARCH_8__");
4633 Builder.defineMacro("__ARM_NEON__");
4634 Builder.defineMacro("__LITTLE_ENDIAN__");
4635 Builder.defineMacro("__REGISTER_PREFIX__", "");
4636 Builder.defineMacro("__arm64", "1");
4637 Builder.defineMacro("__arm64__", "1");
4639 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4643 DarwinAArch64TargetInfo(const llvm::Triple &Triple)
4644 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
4645 Int64Type = SignedLongLong;
4646 WCharType = SignedInt;
4647 UseSignedCharForObjCBool = false;
4649 LongDoubleWidth = LongDoubleAlign = 64;
4650 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4652 TheCXXABI.set(TargetCXXABI::iOS64);
4655 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4656 return TargetInfo::CharPtrBuiltinVaList;
4659 } // end anonymous namespace
4662 // Hexagon abstract base class
4663 class HexagonTargetInfo : public TargetInfo {
4664 static const Builtin::Info BuiltinInfo[];
4665 static const char * const GCCRegNames[];
4666 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4669 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4671 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
4673 // {} in inline assembly are packet specifiers, not assembly variant
4675 NoAsmVariants = true;
4678 void getTargetBuiltins(const Builtin::Info *&Records,
4679 unsigned &NumRecords) const override {
4680 Records = BuiltinInfo;
4681 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
4684 bool validateAsmConstraint(const char *&Name,
4685 TargetInfo::ConstraintInfo &Info) const override {
4689 void getTargetDefines(const LangOptions &Opts,
4690 MacroBuilder &Builder) const override;
4692 bool hasFeature(StringRef Feature) const override {
4693 return Feature == "hexagon";
4696 BuiltinVaListKind getBuiltinVaListKind() const override {
4697 return TargetInfo::CharPtrBuiltinVaList;
4699 void getGCCRegNames(const char * const *&Names,
4700 unsigned &NumNames) const override;
4701 void getGCCRegAliases(const GCCRegAlias *&Aliases,
4702 unsigned &NumAliases) const override;
4703 const char *getClobbers() const override {
4707 static const char *getHexagonCPUSuffix(StringRef Name) {
4708 return llvm::StringSwitch<const char*>(Name)
4709 .Case("hexagonv4", "4")
4710 .Case("hexagonv5", "5")
4714 bool setCPU(const std::string &Name) override {
4715 if (!getHexagonCPUSuffix(Name))
4723 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4724 MacroBuilder &Builder) const {
4725 Builder.defineMacro("qdsp6");
4726 Builder.defineMacro("__qdsp6", "1");
4727 Builder.defineMacro("__qdsp6__", "1");
4729 Builder.defineMacro("hexagon");
4730 Builder.defineMacro("__hexagon", "1");
4731 Builder.defineMacro("__hexagon__", "1");
4733 if(CPU == "hexagonv1") {
4734 Builder.defineMacro("__HEXAGON_V1__");
4735 Builder.defineMacro("__HEXAGON_ARCH__", "1");
4736 if(Opts.HexagonQdsp6Compat) {
4737 Builder.defineMacro("__QDSP6_V1__");
4738 Builder.defineMacro("__QDSP6_ARCH__", "1");
4741 else if(CPU == "hexagonv2") {
4742 Builder.defineMacro("__HEXAGON_V2__");
4743 Builder.defineMacro("__HEXAGON_ARCH__", "2");
4744 if(Opts.HexagonQdsp6Compat) {
4745 Builder.defineMacro("__QDSP6_V2__");
4746 Builder.defineMacro("__QDSP6_ARCH__", "2");
4749 else if(CPU == "hexagonv3") {
4750 Builder.defineMacro("__HEXAGON_V3__");
4751 Builder.defineMacro("__HEXAGON_ARCH__", "3");
4752 if(Opts.HexagonQdsp6Compat) {
4753 Builder.defineMacro("__QDSP6_V3__");
4754 Builder.defineMacro("__QDSP6_ARCH__", "3");
4757 else if(CPU == "hexagonv4") {
4758 Builder.defineMacro("__HEXAGON_V4__");
4759 Builder.defineMacro("__HEXAGON_ARCH__", "4");
4760 if(Opts.HexagonQdsp6Compat) {
4761 Builder.defineMacro("__QDSP6_V4__");
4762 Builder.defineMacro("__QDSP6_ARCH__", "4");
4765 else if(CPU == "hexagonv5") {
4766 Builder.defineMacro("__HEXAGON_V5__");
4767 Builder.defineMacro("__HEXAGON_ARCH__", "5");
4768 if(Opts.HexagonQdsp6Compat) {
4769 Builder.defineMacro("__QDSP6_V5__");
4770 Builder.defineMacro("__QDSP6_ARCH__", "5");
4775 const char * const HexagonTargetInfo::GCCRegNames[] = {
4776 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4777 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4778 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4779 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
4780 "p0", "p1", "p2", "p3",
4781 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
4784 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
4785 unsigned &NumNames) const {
4786 Names = GCCRegNames;
4787 NumNames = llvm::array_lengthof(GCCRegNames);
4791 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
4792 { { "sp" }, "r29" },
4793 { { "fp" }, "r30" },
4794 { { "lr" }, "r31" },
4797 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4798 unsigned &NumAliases) const {
4799 Aliases = GCCRegAliases;
4800 NumAliases = llvm::array_lengthof(GCCRegAliases);
4804 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
4805 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4806 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4808 #include "clang/Basic/BuiltinsHexagon.def"
4814 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
4815 class SparcTargetInfo : public TargetInfo {
4816 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4817 static const char * const GCCRegNames[];
4820 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
4822 bool handleTargetFeatures(std::vector<std::string> &Features,
4823 DiagnosticsEngine &Diags) override {
4825 for (unsigned i = 0, e = Features.size(); i != e; ++i)
4826 if (Features[i] == "+soft-float")
4830 void getTargetDefines(const LangOptions &Opts,
4831 MacroBuilder &Builder) const override {
4832 DefineStd(Builder, "sparc", Opts);
4833 Builder.defineMacro("__REGISTER_PREFIX__", "");
4836 Builder.defineMacro("SOFT_FLOAT", "1");
4839 bool hasFeature(StringRef Feature) const override {
4840 return llvm::StringSwitch<bool>(Feature)
4841 .Case("softfloat", SoftFloat)
4842 .Case("sparc", true)
4846 void getTargetBuiltins(const Builtin::Info *&Records,
4847 unsigned &NumRecords) const override {
4848 // FIXME: Implement!
4850 BuiltinVaListKind getBuiltinVaListKind() const override {
4851 return TargetInfo::VoidPtrBuiltinVaList;
4853 void getGCCRegNames(const char * const *&Names,
4854 unsigned &NumNames) const override;
4855 void getGCCRegAliases(const GCCRegAlias *&Aliases,
4856 unsigned &NumAliases) const override;
4857 bool validateAsmConstraint(const char *&Name,
4858 TargetInfo::ConstraintInfo &info) const override {
4859 // FIXME: Implement!
4862 const char *getClobbers() const override {
4863 // FIXME: Implement!
4868 const char * const SparcTargetInfo::GCCRegNames[] = {
4869 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4870 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4871 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4872 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4875 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
4876 unsigned &NumNames) const {
4877 Names = GCCRegNames;
4878 NumNames = llvm::array_lengthof(GCCRegNames);
4881 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
4892 { { "o2" }, "r10" },
4893 { { "o3" }, "r11" },
4894 { { "o4" }, "r12" },
4895 { { "o5" }, "r13" },
4896 { { "o6", "sp" }, "r14" },
4897 { { "o7" }, "r15" },
4898 { { "l0" }, "r16" },
4899 { { "l1" }, "r17" },
4900 { { "l2" }, "r18" },
4901 { { "l3" }, "r19" },
4902 { { "l4" }, "r20" },
4903 { { "l5" }, "r21" },
4904 { { "l6" }, "r22" },
4905 { { "l7" }, "r23" },
4906 { { "i0" }, "r24" },
4907 { { "i1" }, "r25" },
4908 { { "i2" }, "r26" },
4909 { { "i3" }, "r27" },
4910 { { "i4" }, "r28" },
4911 { { "i5" }, "r29" },
4912 { { "i6", "fp" }, "r30" },
4913 { { "i7" }, "r31" },
4916 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4917 unsigned &NumAliases) const {
4918 Aliases = GCCRegAliases;
4919 NumAliases = llvm::array_lengthof(GCCRegAliases);
4922 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
4923 class SparcV8TargetInfo : public SparcTargetInfo {
4925 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
4926 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
4929 void getTargetDefines(const LangOptions &Opts,
4930 MacroBuilder &Builder) const override {
4931 SparcTargetInfo::getTargetDefines(Opts, Builder);
4932 Builder.defineMacro("__sparcv8");
4936 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
4937 class SparcV9TargetInfo : public SparcTargetInfo {
4939 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
4940 // FIXME: Support Sparc quad-precision long double?
4941 DescriptionString = "E-m:e-i64:64-n32:64-S128";
4942 // This is an LP64 platform.
4943 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4945 // OpenBSD uses long long for int64_t and intmax_t.
4946 if (getTriple().getOS() == llvm::Triple::OpenBSD)
4947 IntMaxType = SignedLongLong;
4949 IntMaxType = SignedLong;
4950 Int64Type = IntMaxType;
4952 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
4953 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
4954 LongDoubleWidth = 128;
4955 LongDoubleAlign = 128;
4956 LongDoubleFormat = &llvm::APFloat::IEEEquad;
4957 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4960 void getTargetDefines(const LangOptions &Opts,
4961 MacroBuilder &Builder) const override {
4962 SparcTargetInfo::getTargetDefines(Opts, Builder);
4963 Builder.defineMacro("__sparcv9");
4964 Builder.defineMacro("__arch64__");
4965 // Solaris and its derivative AuroraUX don't need these variants, but the
4967 if (getTriple().getOS() != llvm::Triple::Solaris &&
4968 getTriple().getOS() != llvm::Triple::AuroraUX) {
4969 Builder.defineMacro("__sparc64__");
4970 Builder.defineMacro("__sparc_v9__");
4971 Builder.defineMacro("__sparcv9__");
4975 bool setCPU(const std::string &Name) override {
4976 bool CPUKnown = llvm::StringSwitch<bool>(Name)
4978 .Case("ultrasparc", true)
4979 .Case("ultrasparc3", true)
4980 .Case("niagara", true)
4981 .Case("niagara2", true)
4982 .Case("niagara3", true)
4983 .Case("niagara4", true)
4986 // No need to store the CPU yet. There aren't any CPU-specific
4987 // macros to define.
4992 } // end anonymous namespace.
4995 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
4997 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple)
4998 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) {
4999 SizeType = UnsignedInt;
5000 PtrDiffType = SignedInt;
5003 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
5005 SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
5006 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
5007 SizeType = UnsignedInt;
5008 PtrDiffType = SignedInt;
5011 } // end anonymous namespace.
5014 class SystemZTargetInfo : public TargetInfo {
5015 static const char *const GCCRegNames[];
5018 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5019 TLSSupported = true;
5020 IntWidth = IntAlign = 32;
5021 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5022 PointerWidth = PointerAlign = 64;
5023 LongDoubleWidth = 128;
5024 LongDoubleAlign = 64;
5025 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5026 MinGlobalAlign = 16;
5027 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5028 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5030 void getTargetDefines(const LangOptions &Opts,
5031 MacroBuilder &Builder) const override {
5032 Builder.defineMacro("__s390__");
5033 Builder.defineMacro("__s390x__");
5034 Builder.defineMacro("__zarch__");
5035 Builder.defineMacro("__LONG_DOUBLE_128__");
5037 void getTargetBuiltins(const Builtin::Info *&Records,
5038 unsigned &NumRecords) const override {
5039 // FIXME: Implement.
5044 void getGCCRegNames(const char *const *&Names,
5045 unsigned &NumNames) const override;
5046 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5047 unsigned &NumAliases) const override {
5052 bool validateAsmConstraint(const char *&Name,
5053 TargetInfo::ConstraintInfo &info) const override;
5054 const char *getClobbers() const override {
5055 // FIXME: Is this really right?
5058 BuiltinVaListKind getBuiltinVaListKind() const override {
5059 return TargetInfo::SystemZBuiltinVaList;
5061 bool setCPU(const std::string &Name) override {
5062 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5065 .Case("zEC12", true)
5068 // No need to store the CPU yet. There aren't any CPU-specific
5069 // macros to define.
5074 const char *const SystemZTargetInfo::GCCRegNames[] = {
5075 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5076 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5077 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
5078 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
5081 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5082 unsigned &NumNames) const {
5083 Names = GCCRegNames;
5084 NumNames = llvm::array_lengthof(GCCRegNames);
5087 bool SystemZTargetInfo::
5088 validateAsmConstraint(const char *&Name,
5089 TargetInfo::ConstraintInfo &Info) const {
5094 case 'a': // Address register
5095 case 'd': // Data register (equivalent to 'r')
5096 case 'f': // Floating-point register
5097 Info.setAllowsRegister();
5100 case 'I': // Unsigned 8-bit constant
5101 case 'J': // Unsigned 12-bit constant
5102 case 'K': // Signed 16-bit constant
5103 case 'L': // Signed 20-bit displacement (on all targets we support)
5104 case 'M': // 0x7fffffff
5107 case 'Q': // Memory with base and unsigned 12-bit displacement
5108 case 'R': // Likewise, plus an index
5109 case 'S': // Memory with base and signed 20-bit displacement
5110 case 'T': // Likewise, plus an index
5111 Info.setAllowsMemory();
5118 class MSP430TargetInfo : public TargetInfo {
5119 static const char * const GCCRegNames[];
5121 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5123 TLSSupported = false;
5124 IntWidth = 16; IntAlign = 16;
5125 LongWidth = 32; LongLongWidth = 64;
5126 LongAlign = LongLongAlign = 16;
5127 PointerWidth = 16; PointerAlign = 16;
5129 SizeType = UnsignedInt;
5130 IntMaxType = SignedLongLong;
5131 IntPtrType = SignedInt;
5132 PtrDiffType = SignedInt;
5133 SigAtomicType = SignedLong;
5134 DescriptionString = "e-m:e-p:16:16-i32:16:32-n8:16";
5136 void getTargetDefines(const LangOptions &Opts,
5137 MacroBuilder &Builder) const override {
5138 Builder.defineMacro("MSP430");
5139 Builder.defineMacro("__MSP430__");
5140 // FIXME: defines for different 'flavours' of MCU
5142 void getTargetBuiltins(const Builtin::Info *&Records,
5143 unsigned &NumRecords) const override {
5144 // FIXME: Implement.
5148 bool hasFeature(StringRef Feature) const override {
5149 return Feature == "msp430";
5151 void getGCCRegNames(const char * const *&Names,
5152 unsigned &NumNames) const override;
5153 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5154 unsigned &NumAliases) const override {
5159 bool validateAsmConstraint(const char *&Name,
5160 TargetInfo::ConstraintInfo &info) const override {
5161 // No target constraints for now.
5164 const char *getClobbers() const override {
5165 // FIXME: Is this really right?
5168 BuiltinVaListKind getBuiltinVaListKind() const override {
5170 return TargetInfo::CharPtrBuiltinVaList;
5174 const char * const MSP430TargetInfo::GCCRegNames[] = {
5175 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5176 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5179 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5180 unsigned &NumNames) const {
5181 Names = GCCRegNames;
5182 NumNames = llvm::array_lengthof(GCCRegNames);
5188 // LLVM and Clang cannot be used directly to output native binaries for
5189 // target, but is used to compile C code to llvm bitcode with correct
5190 // type and alignment information.
5192 // TCE uses the llvm bitcode as input and uses it for generating customized
5193 // target processor and program binary. TCE co-design environment is
5194 // publicly available in http://tce.cs.tut.fi
5196 static const unsigned TCEOpenCLAddrSpaceMap[] = {
5199 5, // opencl_constant
5205 class TCETargetInfo : public TargetInfo{
5207 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5208 TLSSupported = false;
5210 LongWidth = LongLongWidth = 32;
5213 LongAlign = LongLongAlign = 32;
5216 SizeType = UnsignedInt;
5217 IntMaxType = SignedLong;
5218 IntPtrType = SignedInt;
5219 PtrDiffType = SignedInt;
5224 LongDoubleWidth = 32;
5225 LongDoubleAlign = 32;
5226 FloatFormat = &llvm::APFloat::IEEEsingle;
5227 DoubleFormat = &llvm::APFloat::IEEEsingle;
5228 LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5229 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5230 "-f64:32-v64:32-v128:32-a:0:32-n32";
5231 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5232 UseAddrSpaceMapMangling = true;
5235 void getTargetDefines(const LangOptions &Opts,
5236 MacroBuilder &Builder) const override {
5237 DefineStd(Builder, "tce", Opts);
5238 Builder.defineMacro("__TCE__");
5239 Builder.defineMacro("__TCE_V1__");
5241 bool hasFeature(StringRef Feature) const override {
5242 return Feature == "tce";
5245 void getTargetBuiltins(const Builtin::Info *&Records,
5246 unsigned &NumRecords) const override {}
5247 const char *getClobbers() const override {
5250 BuiltinVaListKind getBuiltinVaListKind() const override {
5251 return TargetInfo::VoidPtrBuiltinVaList;
5253 void getGCCRegNames(const char * const *&Names,
5254 unsigned &NumNames) const override {}
5255 bool validateAsmConstraint(const char *&Name,
5256 TargetInfo::ConstraintInfo &info) const override{
5259 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5260 unsigned &NumAliases) const override {}
5265 class MipsTargetInfoBase : public TargetInfo {
5266 virtual void setDescriptionString() = 0;
5268 static const Builtin::Info BuiltinInfo[];
5275 HardFloat, SoftFloat
5287 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5288 const std::string &CPUStr)
5289 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
5290 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
5291 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {}
5293 bool isNaN2008Default() const {
5294 return CPU == "mips32r6" || CPU == "mips64r6";
5297 bool isFP64Default() const {
5298 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
5301 StringRef getABI() const override { return ABI; }
5302 bool setCPU(const std::string &Name) override {
5303 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
5304 getTriple().getArch() == llvm::Triple::mipsel;
5306 return llvm::StringSwitch<bool>(Name)
5307 .Case("mips1", IsMips32)
5308 .Case("mips2", IsMips32)
5309 .Case("mips3", true)
5310 .Case("mips4", true)
5311 .Case("mips5", true)
5312 .Case("mips32", IsMips32)
5313 .Case("mips32r2", IsMips32)
5314 .Case("mips32r6", IsMips32)
5315 .Case("mips64", true)
5316 .Case("mips64r2", true)
5317 .Case("mips64r6", true)
5318 .Case("octeon", true)
5321 const std::string& getCPU() const { return CPU; }
5322 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5323 // The backend enables certain ABI's by default according to the
5325 // Disable both possible defaults so that we don't end up with multiple
5326 // ABI's selected and trigger an assertion.
5327 Features["o32"] = false;
5328 Features["n64"] = false;
5330 Features[ABI] = true;
5331 if (CPU == "octeon")
5332 Features["mips64r2"] = Features["cnmips"] = true;
5334 Features[CPU] = true;
5337 void getTargetDefines(const LangOptions &Opts,
5338 MacroBuilder &Builder) const override {
5339 Builder.defineMacro("__mips__");
5340 Builder.defineMacro("_mips");
5342 Builder.defineMacro("mips");
5344 Builder.defineMacro("__REGISTER_PREFIX__", "");
5348 Builder.defineMacro("__mips_hard_float", Twine(1));
5351 Builder.defineMacro("__mips_soft_float", Twine(1));
5356 Builder.defineMacro("__mips_single_float", Twine(1));
5358 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
5359 Builder.defineMacro("_MIPS_FPSET",
5360 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
5363 Builder.defineMacro("__mips16", Twine(1));
5366 Builder.defineMacro("__mips_micromips", Twine(1));
5369 Builder.defineMacro("__mips_nan2008", Twine(1));
5375 Builder.defineMacro("__mips_dsp_rev", Twine(1));
5376 Builder.defineMacro("__mips_dsp", Twine(1));
5379 Builder.defineMacro("__mips_dsp_rev", Twine(2));
5380 Builder.defineMacro("__mips_dspr2", Twine(1));
5381 Builder.defineMacro("__mips_dsp", Twine(1));
5386 Builder.defineMacro("__mips_msa", Twine(1));
5388 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
5389 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
5390 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
5392 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
5393 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
5396 void getTargetBuiltins(const Builtin::Info *&Records,
5397 unsigned &NumRecords) const override {
5398 Records = BuiltinInfo;
5399 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
5401 bool hasFeature(StringRef Feature) const override {
5402 return llvm::StringSwitch<bool>(Feature)
5404 .Case("fp64", HasFP64)
5407 BuiltinVaListKind getBuiltinVaListKind() const override {
5408 return TargetInfo::VoidPtrBuiltinVaList;
5410 void getGCCRegNames(const char * const *&Names,
5411 unsigned &NumNames) const override {
5412 static const char *const GCCRegNames[] = {
5413 // CPU register names
5414 // Must match second column of GCCRegAliases
5415 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
5416 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
5417 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
5418 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
5419 // Floating point register names
5420 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
5421 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
5422 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
5423 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
5424 // Hi/lo and condition register names
5425 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
5426 "$fcc5","$fcc6","$fcc7",
5427 // MSA register names
5428 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
5429 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
5430 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
5431 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
5432 // MSA control register names
5433 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
5434 "$msarequest", "$msamap", "$msaunmap"
5436 Names = GCCRegNames;
5437 NumNames = llvm::array_lengthof(GCCRegNames);
5439 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5440 unsigned &NumAliases) const override = 0;
5441 bool validateAsmConstraint(const char *&Name,
5442 TargetInfo::ConstraintInfo &Info) const override {
5447 case 'r': // CPU registers.
5448 case 'd': // Equivalent to "r" unless generating MIPS16 code.
5449 case 'y': // Equivalent to "r", backward compatibility only.
5450 case 'f': // floating-point registers.
5451 case 'c': // $25 for indirect jumps
5452 case 'l': // lo register
5453 case 'x': // hilo register pair
5454 Info.setAllowsRegister();
5456 case 'R': // An address that can be used in a non-macro load or store
5457 Info.setAllowsMemory();
5462 const char *getClobbers() const override {
5463 // FIXME: Implement!
5467 bool handleTargetFeatures(std::vector<std::string> &Features,
5468 DiagnosticsEngine &Diags) override {
5470 IsMicromips = false;
5471 IsNan2008 = isNaN2008Default();
5472 IsSingleFloat = false;
5473 FloatABI = HardFloat;
5475 HasFP64 = isFP64Default();
5477 for (std::vector<std::string>::iterator it = Features.begin(),
5478 ie = Features.end(); it != ie; ++it) {
5479 if (*it == "+single-float")
5480 IsSingleFloat = true;
5481 else if (*it == "+soft-float")
5482 FloatABI = SoftFloat;
5483 else if (*it == "+mips16")
5485 else if (*it == "+micromips")
5487 else if (*it == "+dsp")
5488 DspRev = std::max(DspRev, DSP1);
5489 else if (*it == "+dspr2")
5490 DspRev = std::max(DspRev, DSP2);
5491 else if (*it == "+msa")
5493 else if (*it == "+fp64")
5495 else if (*it == "-fp64")
5497 else if (*it == "+nan2008")
5499 else if (*it == "-nan2008")
5503 // Remove front-end specific options.
5504 std::vector<std::string>::iterator it =
5505 std::find(Features.begin(), Features.end(), "+soft-float");
5506 if (it != Features.end())
5509 setDescriptionString();
5514 int getEHDataRegisterNumber(unsigned RegNo) const override {
5515 if (RegNo == 0) return 4;
5516 if (RegNo == 1) return 5;
5520 bool isCLZForZeroUndef() const override { return false; }
5523 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
5524 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5525 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5527 #include "clang/Basic/BuiltinsMips.def"
5530 class Mips32TargetInfoBase : public MipsTargetInfoBase {
5532 Mips32TargetInfoBase(const llvm::Triple &Triple)
5533 : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
5534 SizeType = UnsignedInt;
5535 PtrDiffType = SignedInt;
5536 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
5538 bool setABI(const std::string &Name) override {
5539 if (Name == "o32" || Name == "eabi") {
5545 void getTargetDefines(const LangOptions &Opts,
5546 MacroBuilder &Builder) const override {
5547 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5549 Builder.defineMacro("__mips", "32");
5550 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
5552 const std::string& CPUStr = getCPU();
5553 if (CPUStr == "mips32")
5554 Builder.defineMacro("__mips_isa_rev", "1");
5555 else if (CPUStr == "mips32r2")
5556 Builder.defineMacro("__mips_isa_rev", "2");
5559 Builder.defineMacro("__mips_o32");
5560 Builder.defineMacro("_ABIO32", "1");
5561 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
5563 else if (ABI == "eabi")
5564 Builder.defineMacro("__mips_eabi");
5566 llvm_unreachable("Invalid ABI for Mips32.");
5568 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5569 unsigned &NumAliases) const override {
5570 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5580 { { "t2" }, "$10" },
5581 { { "t3" }, "$11" },
5582 { { "t4" }, "$12" },
5583 { { "t5" }, "$13" },
5584 { { "t6" }, "$14" },
5585 { { "t7" }, "$15" },
5586 { { "s0" }, "$16" },
5587 { { "s1" }, "$17" },
5588 { { "s2" }, "$18" },
5589 { { "s3" }, "$19" },
5590 { { "s4" }, "$20" },
5591 { { "s5" }, "$21" },
5592 { { "s6" }, "$22" },
5593 { { "s7" }, "$23" },
5594 { { "t8" }, "$24" },
5595 { { "t9" }, "$25" },
5596 { { "k0" }, "$26" },
5597 { { "k1" }, "$27" },
5598 { { "gp" }, "$28" },
5599 { { "sp","$sp" }, "$29" },
5600 { { "fp","$fp" }, "$30" },
5603 Aliases = GCCRegAliases;
5604 NumAliases = llvm::array_lengthof(GCCRegAliases);
5608 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
5609 void setDescriptionString() override {
5610 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
5614 Mips32EBTargetInfo(const llvm::Triple &Triple)
5615 : Mips32TargetInfoBase(Triple) {
5617 void getTargetDefines(const LangOptions &Opts,
5618 MacroBuilder &Builder) const override {
5619 DefineStd(Builder, "MIPSEB", Opts);
5620 Builder.defineMacro("_MIPSEB");
5621 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5625 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
5626 void setDescriptionString() override {
5627 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
5631 Mips32ELTargetInfo(const llvm::Triple &Triple)
5632 : Mips32TargetInfoBase(Triple) {
5635 void getTargetDefines(const LangOptions &Opts,
5636 MacroBuilder &Builder) const override {
5637 DefineStd(Builder, "MIPSEL", Opts);
5638 Builder.defineMacro("_MIPSEL");
5639 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5643 class Mips64TargetInfoBase : public MipsTargetInfoBase {
5645 Mips64TargetInfoBase(const llvm::Triple &Triple)
5646 : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
5647 LongDoubleWidth = LongDoubleAlign = 128;
5648 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5649 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
5650 LongDoubleWidth = LongDoubleAlign = 64;
5651 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5654 SuitableAlign = 128;
5655 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5658 void setN64ABITypes() {
5659 LongWidth = LongAlign = 64;
5660 PointerWidth = PointerAlign = 64;
5661 SizeType = UnsignedLong;
5662 PtrDiffType = SignedLong;
5665 void setN32ABITypes() {
5666 LongWidth = LongAlign = 32;
5667 PointerWidth = PointerAlign = 32;
5668 SizeType = UnsignedInt;
5669 PtrDiffType = SignedInt;
5672 bool setABI(const std::string &Name) override {
5673 if (Name == "n32") {
5678 if (Name == "n64") {
5686 void getTargetDefines(const LangOptions &Opts,
5687 MacroBuilder &Builder) const override {
5688 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5690 Builder.defineMacro("__mips", "64");
5691 Builder.defineMacro("__mips64");
5692 Builder.defineMacro("__mips64__");
5693 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
5695 const std::string& CPUStr = getCPU();
5696 if (CPUStr == "mips64")
5697 Builder.defineMacro("__mips_isa_rev", "1");
5698 else if (CPUStr == "mips64r2")
5699 Builder.defineMacro("__mips_isa_rev", "2");
5702 Builder.defineMacro("__mips_n32");
5703 Builder.defineMacro("_ABIN32", "2");
5704 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
5706 else if (ABI == "n64") {
5707 Builder.defineMacro("__mips_n64");
5708 Builder.defineMacro("_ABI64", "3");
5709 Builder.defineMacro("_MIPS_SIM", "_ABI64");
5712 llvm_unreachable("Invalid ABI for Mips64.");
5714 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5715 unsigned &NumAliases) const override {
5716 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5726 { { "a6" }, "$10" },
5727 { { "a7" }, "$11" },
5728 { { "t0" }, "$12" },
5729 { { "t1" }, "$13" },
5730 { { "t2" }, "$14" },
5731 { { "t3" }, "$15" },
5732 { { "s0" }, "$16" },
5733 { { "s1" }, "$17" },
5734 { { "s2" }, "$18" },
5735 { { "s3" }, "$19" },
5736 { { "s4" }, "$20" },
5737 { { "s5" }, "$21" },
5738 { { "s6" }, "$22" },
5739 { { "s7" }, "$23" },
5740 { { "t8" }, "$24" },
5741 { { "t9" }, "$25" },
5742 { { "k0" }, "$26" },
5743 { { "k1" }, "$27" },
5744 { { "gp" }, "$28" },
5745 { { "sp","$sp" }, "$29" },
5746 { { "fp","$fp" }, "$30" },
5749 Aliases = GCCRegAliases;
5750 NumAliases = llvm::array_lengthof(GCCRegAliases);
5753 bool hasInt128Type() const override { return true; }
5756 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
5757 void setDescriptionString() override {
5759 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
5761 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
5766 Mips64EBTargetInfo(const llvm::Triple &Triple)
5767 : Mips64TargetInfoBase(Triple) {}
5768 void getTargetDefines(const LangOptions &Opts,
5769 MacroBuilder &Builder) const override {
5770 DefineStd(Builder, "MIPSEB", Opts);
5771 Builder.defineMacro("_MIPSEB");
5772 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5776 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
5777 void setDescriptionString() override {
5779 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
5781 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
5784 Mips64ELTargetInfo(const llvm::Triple &Triple)
5785 : Mips64TargetInfoBase(Triple) {
5786 // Default ABI is n64.
5789 void getTargetDefines(const LangOptions &Opts,
5790 MacroBuilder &Builder) const override {
5791 DefineStd(Builder, "MIPSEL", Opts);
5792 Builder.defineMacro("_MIPSEL");
5793 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5796 } // end anonymous namespace.
5799 class PNaClTargetInfo : public TargetInfo {
5801 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5803 this->UserLabelPrefix = "";
5804 this->LongAlign = 32;
5805 this->LongWidth = 32;
5806 this->PointerAlign = 32;
5807 this->PointerWidth = 32;
5808 this->IntMaxType = TargetInfo::SignedLongLong;
5809 this->Int64Type = TargetInfo::SignedLongLong;
5810 this->DoubleAlign = 64;
5811 this->LongDoubleWidth = 64;
5812 this->LongDoubleAlign = 64;
5813 this->SizeType = TargetInfo::UnsignedInt;
5814 this->PtrDiffType = TargetInfo::SignedInt;
5815 this->IntPtrType = TargetInfo::SignedInt;
5816 this->RegParmMax = 0; // Disallow regparm
5819 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5821 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
5822 Builder.defineMacro("__le32__");
5823 Builder.defineMacro("__pnacl__");
5825 void getTargetDefines(const LangOptions &Opts,
5826 MacroBuilder &Builder) const override {
5827 getArchDefines(Opts, Builder);
5829 bool hasFeature(StringRef Feature) const override {
5830 return Feature == "pnacl";
5832 void getTargetBuiltins(const Builtin::Info *&Records,
5833 unsigned &NumRecords) const override {
5835 BuiltinVaListKind getBuiltinVaListKind() const override {
5836 return TargetInfo::PNaClABIBuiltinVaList;
5838 void getGCCRegNames(const char * const *&Names,
5839 unsigned &NumNames) const override;
5840 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5841 unsigned &NumAliases) const override;
5842 bool validateAsmConstraint(const char *&Name,
5843 TargetInfo::ConstraintInfo &Info) const override {
5847 const char *getClobbers() const override {
5852 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
5853 unsigned &NumNames) const {
5858 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5859 unsigned &NumAliases) const {
5863 } // end anonymous namespace.
5866 static const unsigned SPIRAddrSpaceMap[] = {
5869 2, // opencl_constant
5874 class SPIRTargetInfo : public TargetInfo {
5876 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5877 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
5878 "SPIR target must use unknown OS");
5879 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
5880 "SPIR target must use unknown environment type");
5882 TLSSupported = false;
5883 LongWidth = LongAlign = 64;
5884 AddrSpaceMap = &SPIRAddrSpaceMap;
5885 UseAddrSpaceMapMangling = true;
5886 // Define available target features
5887 // These must be defined in sorted order!
5888 NoAsmVariants = true;
5890 void getTargetDefines(const LangOptions &Opts,
5891 MacroBuilder &Builder) const override {
5892 DefineStd(Builder, "SPIR", Opts);
5894 bool hasFeature(StringRef Feature) const override {
5895 return Feature == "spir";
5898 void getTargetBuiltins(const Builtin::Info *&Records,
5899 unsigned &NumRecords) const override {}
5900 const char *getClobbers() const override {
5903 void getGCCRegNames(const char * const *&Names,
5904 unsigned &NumNames) const override {}
5905 bool validateAsmConstraint(const char *&Name,
5906 TargetInfo::ConstraintInfo &info) const override {
5909 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5910 unsigned &NumAliases) const override {}
5911 BuiltinVaListKind getBuiltinVaListKind() const override {
5912 return TargetInfo::VoidPtrBuiltinVaList;
5917 class SPIR32TargetInfo : public SPIRTargetInfo {
5919 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
5920 PointerWidth = PointerAlign = 32;
5921 SizeType = TargetInfo::UnsignedInt;
5922 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
5924 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
5925 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
5927 void getTargetDefines(const LangOptions &Opts,
5928 MacroBuilder &Builder) const override {
5929 DefineStd(Builder, "SPIR32", Opts);
5933 class SPIR64TargetInfo : public SPIRTargetInfo {
5935 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
5936 PointerWidth = PointerAlign = 64;
5937 SizeType = TargetInfo::UnsignedLong;
5938 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
5939 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
5940 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
5942 void getTargetDefines(const LangOptions &Opts,
5943 MacroBuilder &Builder) const override {
5944 DefineStd(Builder, "SPIR64", Opts);
5950 class XCoreTargetInfo : public TargetInfo {
5951 static const Builtin::Info BuiltinInfo[];
5953 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5955 NoAsmVariants = true;
5958 DoubleAlign = LongDoubleAlign = 32;
5959 SizeType = UnsignedInt;
5960 PtrDiffType = SignedInt;
5961 IntPtrType = SignedInt;
5962 WCharType = UnsignedChar;
5963 WIntType = UnsignedInt;
5964 UseZeroLengthBitfieldAlignment = true;
5965 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
5966 "-f64:32-a:0:32-n32";
5968 void getTargetDefines(const LangOptions &Opts,
5969 MacroBuilder &Builder) const override {
5970 Builder.defineMacro("__XS1B__");
5972 void getTargetBuiltins(const Builtin::Info *&Records,
5973 unsigned &NumRecords) const override {
5974 Records = BuiltinInfo;
5975 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
5977 BuiltinVaListKind getBuiltinVaListKind() const override {
5978 return TargetInfo::VoidPtrBuiltinVaList;
5980 const char *getClobbers() const override {
5983 void getGCCRegNames(const char * const *&Names,
5984 unsigned &NumNames) const override {
5985 static const char * const GCCRegNames[] = {
5986 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5987 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
5989 Names = GCCRegNames;
5990 NumNames = llvm::array_lengthof(GCCRegNames);
5992 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5993 unsigned &NumAliases) const override {
5997 bool validateAsmConstraint(const char *&Name,
5998 TargetInfo::ConstraintInfo &Info) const override {
6001 int getEHDataRegisterNumber(unsigned RegNo) const override {
6002 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6003 return (RegNo < 2)? RegNo : -1;
6007 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6008 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6009 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6011 #include "clang/Basic/BuiltinsXCore.def"
6013 } // end anonymous namespace.
6016 //===----------------------------------------------------------------------===//
6018 //===----------------------------------------------------------------------===//
6020 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6021 llvm::Triple::OSType os = Triple.getOS();
6023 switch (Triple.getArch()) {
6027 case llvm::Triple::xcore:
6028 return new XCoreTargetInfo(Triple);
6030 case llvm::Triple::hexagon:
6031 return new HexagonTargetInfo(Triple);
6033 case llvm::Triple::aarch64:
6034 case llvm::Triple::arm64:
6035 if (Triple.isOSDarwin())
6036 return new DarwinAArch64TargetInfo(Triple);
6039 case llvm::Triple::FreeBSD:
6040 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
6041 case llvm::Triple::Linux:
6042 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6043 case llvm::Triple::NetBSD:
6044 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6046 return new AArch64leTargetInfo(Triple);
6049 case llvm::Triple::aarch64_be:
6050 case llvm::Triple::arm64_be:
6052 case llvm::Triple::FreeBSD:
6053 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
6054 case llvm::Triple::Linux:
6055 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6056 case llvm::Triple::NetBSD:
6057 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6059 return new AArch64beTargetInfo(Triple);
6062 case llvm::Triple::arm:
6063 case llvm::Triple::thumb:
6064 if (Triple.isOSBinFormatMachO())
6065 return new DarwinARMTargetInfo(Triple);
6068 case llvm::Triple::Linux:
6069 return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6070 case llvm::Triple::FreeBSD:
6071 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6072 case llvm::Triple::NetBSD:
6073 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6074 case llvm::Triple::OpenBSD:
6075 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6076 case llvm::Triple::Bitrig:
6077 return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6078 case llvm::Triple::RTEMS:
6079 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6080 case llvm::Triple::NaCl:
6081 return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6082 case llvm::Triple::Win32:
6083 switch (Triple.getEnvironment()) {
6085 return new ARMleTargetInfo(Triple);
6086 case llvm::Triple::Itanium:
6087 return new ItaniumWindowsARMleTargetInfo(Triple);
6088 case llvm::Triple::MSVC:
6089 return new MicrosoftARMleTargetInfo(Triple);
6092 return new ARMleTargetInfo(Triple);
6095 case llvm::Triple::armeb:
6096 case llvm::Triple::thumbeb:
6097 if (Triple.isOSDarwin())
6098 return new DarwinARMTargetInfo(Triple);
6101 case llvm::Triple::Linux:
6102 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6103 case llvm::Triple::FreeBSD:
6104 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6105 case llvm::Triple::NetBSD:
6106 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6107 case llvm::Triple::OpenBSD:
6108 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6109 case llvm::Triple::Bitrig:
6110 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6111 case llvm::Triple::RTEMS:
6112 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6113 case llvm::Triple::NaCl:
6114 return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6116 return new ARMbeTargetInfo(Triple);
6119 case llvm::Triple::msp430:
6120 return new MSP430TargetInfo(Triple);
6122 case llvm::Triple::mips:
6124 case llvm::Triple::Linux:
6125 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6126 case llvm::Triple::RTEMS:
6127 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6128 case llvm::Triple::FreeBSD:
6129 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6130 case llvm::Triple::NetBSD:
6131 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6133 return new Mips32EBTargetInfo(Triple);
6136 case llvm::Triple::mipsel:
6138 case llvm::Triple::Linux:
6139 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6140 case llvm::Triple::RTEMS:
6141 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
6142 case llvm::Triple::FreeBSD:
6143 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6144 case llvm::Triple::NetBSD:
6145 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6146 case llvm::Triple::NaCl:
6147 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
6149 return new Mips32ELTargetInfo(Triple);
6152 case llvm::Triple::mips64:
6154 case llvm::Triple::Linux:
6155 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
6156 case llvm::Triple::RTEMS:
6157 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
6158 case llvm::Triple::FreeBSD:
6159 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6160 case llvm::Triple::NetBSD:
6161 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6162 case llvm::Triple::OpenBSD:
6163 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6165 return new Mips64EBTargetInfo(Triple);
6168 case llvm::Triple::mips64el:
6170 case llvm::Triple::Linux:
6171 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
6172 case llvm::Triple::RTEMS:
6173 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
6174 case llvm::Triple::FreeBSD:
6175 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6176 case llvm::Triple::NetBSD:
6177 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6178 case llvm::Triple::OpenBSD:
6179 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6181 return new Mips64ELTargetInfo(Triple);
6184 case llvm::Triple::le32:
6186 case llvm::Triple::NaCl:
6187 return new NaClTargetInfo<PNaClTargetInfo>(Triple);
6192 case llvm::Triple::ppc:
6193 if (Triple.isOSDarwin())
6194 return new DarwinPPC32TargetInfo(Triple);
6196 case llvm::Triple::Linux:
6197 return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
6198 case llvm::Triple::FreeBSD:
6199 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
6200 case llvm::Triple::NetBSD:
6201 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
6202 case llvm::Triple::OpenBSD:
6203 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
6204 case llvm::Triple::RTEMS:
6205 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
6207 return new PPC32TargetInfo(Triple);
6210 case llvm::Triple::ppc64:
6211 if (Triple.isOSDarwin())
6212 return new DarwinPPC64TargetInfo(Triple);
6214 case llvm::Triple::Linux:
6215 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6216 case llvm::Triple::Lv2:
6217 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
6218 case llvm::Triple::FreeBSD:
6219 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
6220 case llvm::Triple::NetBSD:
6221 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6223 return new PPC64TargetInfo(Triple);
6226 case llvm::Triple::ppc64le:
6228 case llvm::Triple::Linux:
6229 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6231 return new PPC64TargetInfo(Triple);
6234 case llvm::Triple::nvptx:
6235 return new NVPTX32TargetInfo(Triple);
6236 case llvm::Triple::nvptx64:
6237 return new NVPTX64TargetInfo(Triple);
6239 case llvm::Triple::r600:
6240 return new R600TargetInfo(Triple);
6242 case llvm::Triple::sparc:
6244 case llvm::Triple::Linux:
6245 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
6246 case llvm::Triple::AuroraUX:
6247 return new AuroraUXSparcV8TargetInfo(Triple);
6248 case llvm::Triple::Solaris:
6249 return new SolarisSparcV8TargetInfo(Triple);
6250 case llvm::Triple::NetBSD:
6251 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
6252 case llvm::Triple::OpenBSD:
6253 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
6254 case llvm::Triple::RTEMS:
6255 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
6257 return new SparcV8TargetInfo(Triple);
6260 case llvm::Triple::sparcv9:
6262 case llvm::Triple::Linux:
6263 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
6264 case llvm::Triple::AuroraUX:
6265 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple);
6266 case llvm::Triple::Solaris:
6267 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
6268 case llvm::Triple::NetBSD:
6269 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
6270 case llvm::Triple::OpenBSD:
6271 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
6272 case llvm::Triple::FreeBSD:
6273 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
6275 return new SparcV9TargetInfo(Triple);
6278 case llvm::Triple::systemz:
6280 case llvm::Triple::Linux:
6281 return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
6283 return new SystemZTargetInfo(Triple);
6286 case llvm::Triple::tce:
6287 return new TCETargetInfo(Triple);
6289 case llvm::Triple::x86:
6290 if (Triple.isOSDarwin())
6291 return new DarwinI386TargetInfo(Triple);
6294 case llvm::Triple::AuroraUX:
6295 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple);
6296 case llvm::Triple::Linux:
6297 return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
6298 case llvm::Triple::DragonFly:
6299 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
6300 case llvm::Triple::NetBSD:
6301 return new NetBSDI386TargetInfo(Triple);
6302 case llvm::Triple::OpenBSD:
6303 return new OpenBSDI386TargetInfo(Triple);
6304 case llvm::Triple::Bitrig:
6305 return new BitrigI386TargetInfo(Triple);
6306 case llvm::Triple::FreeBSD:
6307 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6308 case llvm::Triple::KFreeBSD:
6309 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6310 case llvm::Triple::Minix:
6311 return new MinixTargetInfo<X86_32TargetInfo>(Triple);
6312 case llvm::Triple::Solaris:
6313 return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
6314 case llvm::Triple::Win32: {
6315 switch (Triple.getEnvironment()) {
6317 return new X86_32TargetInfo(Triple);
6318 case llvm::Triple::Cygnus:
6319 return new CygwinX86_32TargetInfo(Triple);
6320 case llvm::Triple::GNU:
6321 return new MinGWX86_32TargetInfo(Triple);
6322 case llvm::Triple::Itanium:
6323 case llvm::Triple::MSVC:
6324 return new MicrosoftX86_32TargetInfo(Triple);
6327 case llvm::Triple::Haiku:
6328 return new HaikuX86_32TargetInfo(Triple);
6329 case llvm::Triple::RTEMS:
6330 return new RTEMSX86_32TargetInfo(Triple);
6331 case llvm::Triple::NaCl:
6332 return new NaClTargetInfo<X86_32TargetInfo>(Triple);
6334 return new X86_32TargetInfo(Triple);
6337 case llvm::Triple::x86_64:
6338 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
6339 return new DarwinX86_64TargetInfo(Triple);
6342 case llvm::Triple::AuroraUX:
6343 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple);
6344 case llvm::Triple::Linux:
6345 return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
6346 case llvm::Triple::DragonFly:
6347 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
6348 case llvm::Triple::NetBSD:
6349 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
6350 case llvm::Triple::OpenBSD:
6351 return new OpenBSDX86_64TargetInfo(Triple);
6352 case llvm::Triple::Bitrig:
6353 return new BitrigX86_64TargetInfo(Triple);
6354 case llvm::Triple::FreeBSD:
6355 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6356 case llvm::Triple::KFreeBSD:
6357 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6358 case llvm::Triple::Solaris:
6359 return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
6360 case llvm::Triple::Win32: {
6361 switch (Triple.getEnvironment()) {
6363 return new X86_64TargetInfo(Triple);
6364 case llvm::Triple::GNU:
6365 return new MinGWX86_64TargetInfo(Triple);
6366 case llvm::Triple::MSVC:
6367 return new MicrosoftX86_64TargetInfo(Triple);
6370 case llvm::Triple::NaCl:
6371 return new NaClTargetInfo<X86_64TargetInfo>(Triple);
6373 return new X86_64TargetInfo(Triple);
6376 case llvm::Triple::spir: {
6377 if (Triple.getOS() != llvm::Triple::UnknownOS ||
6378 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6380 return new SPIR32TargetInfo(Triple);
6382 case llvm::Triple::spir64: {
6383 if (Triple.getOS() != llvm::Triple::UnknownOS ||
6384 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6386 return new SPIR64TargetInfo(Triple);
6391 /// CreateTargetInfo - Return the target info object for the specified target
6394 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
6395 const std::shared_ptr<TargetOptions> &Opts) {
6396 llvm::Triple Triple(Opts->Triple);
6398 // Construct the target
6399 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
6401 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
6404 Target->TargetOpts = Opts;
6406 // Set the target CPU if specified.
6407 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
6408 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
6412 // Set the target ABI if specified.
6413 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
6414 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
6418 // Set the fp math unit.
6419 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
6420 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
6424 // Compute the default target features, we need the target to handle this
6425 // because features may have dependencies on one another.
6426 llvm::StringMap<bool> Features;
6427 Target->getDefaultFeatures(Features);
6429 // Apply the user specified deltas.
6430 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
6432 const char *Name = Opts->FeaturesAsWritten[I].c_str();
6433 // Apply the feature via the target.
6434 bool Enabled = Name[0] == '+';
6435 Target->setFeatureEnabled(Features, Name + 1, Enabled);
6438 // Add the features to the compile options.
6440 // FIXME: If we are completely confident that we have the right set, we only
6441 // need to pass the minuses.
6442 Opts->Features.clear();
6443 for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
6444 ie = Features.end(); it != ie; ++it)
6445 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
6446 if (!Target->handleTargetFeatures(Opts->Features, Diags))
6449 return Target.release();