1 //===--- Targets.cpp - Implement target feature support -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/Builtins.h"
16 #include "clang/Basic/Cuda.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetInfo.h"
22 #include "clang/Basic/TargetOptions.h"
23 #include "clang/Basic/Version.h"
24 #include "llvm/ADT/APFloat.h"
25 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringRef.h"
28 #include "llvm/ADT/StringSwitch.h"
29 #include "llvm/ADT/Triple.h"
30 #include "llvm/MC/MCSectionMachO.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/TargetParser.h"
36 using namespace clang;
38 //===----------------------------------------------------------------------===//
39 // Common code shared among targets.
40 //===----------------------------------------------------------------------===//
42 /// DefineStd - Define a macro name and standard variants. For example if
43 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
45 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
46 const LangOptions &Opts) {
47 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
49 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
50 // in the user's namespace.
52 Builder.defineMacro(MacroName);
55 Builder.defineMacro("__" + MacroName);
58 Builder.defineMacro("__" + MacroName + "__");
61 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
63 Builder.defineMacro("__" + CPUName);
64 Builder.defineMacro("__" + CPUName + "__");
66 Builder.defineMacro("__tune_" + CPUName + "__");
69 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
70 const TargetOptions &Opts);
72 //===----------------------------------------------------------------------===//
73 // Defines specific to certain operating systems.
74 //===----------------------------------------------------------------------===//
77 template<typename TgtInfo>
78 class OSTargetInfo : public TgtInfo {
80 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
81 MacroBuilder &Builder) const=0;
83 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
84 : TgtInfo(Triple, Opts) {}
85 void getTargetDefines(const LangOptions &Opts,
86 MacroBuilder &Builder) const override {
87 TgtInfo::getTargetDefines(Opts, Builder);
88 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
94 template <typename Target>
95 class CloudABITargetInfo : public OSTargetInfo<Target> {
97 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
98 MacroBuilder &Builder) const override {
99 Builder.defineMacro("__CloudABI__");
100 Builder.defineMacro("__ELF__");
102 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
103 Builder.defineMacro("__STDC_ISO_10646__", "201206L");
104 Builder.defineMacro("__STDC_UTF_16__");
105 Builder.defineMacro("__STDC_UTF_32__");
109 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
110 : OSTargetInfo<Target>(Triple, Opts) {}
113 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
114 const llvm::Triple &Triple,
115 StringRef &PlatformName,
116 VersionTuple &PlatformMinVersion) {
117 Builder.defineMacro("__APPLE_CC__", "6000");
118 Builder.defineMacro("__APPLE__");
119 Builder.defineMacro("OBJC_NEW_PROPERTIES");
120 // AddressSanitizer doesn't play well with source fortification, which is on
121 // by default on Darwin.
122 if (Opts.Sanitize.has(SanitizerKind::Address))
123 Builder.defineMacro("_FORTIFY_SOURCE", "0");
125 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode.
127 // __weak is always defined, for use in blocks and with objc pointers.
128 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
129 Builder.defineMacro("__strong", "");
130 Builder.defineMacro("__unsafe_unretained", "");
134 Builder.defineMacro("__STATIC__");
136 Builder.defineMacro("__DYNAMIC__");
138 if (Opts.POSIXThreads)
139 Builder.defineMacro("_REENTRANT");
141 // Get the platform type and version number from the triple.
142 unsigned Maj, Min, Rev;
143 if (Triple.isMacOSX()) {
144 Triple.getMacOSXVersion(Maj, Min, Rev);
145 PlatformName = "macos";
147 Triple.getOSVersion(Maj, Min, Rev);
148 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
151 // If -target arch-pc-win32-macho option specified, we're
152 // generating code for Win32 ABI. No need to emit
153 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
154 if (PlatformName == "win32") {
155 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
159 // Set the appropriate OS version define.
160 if (Triple.isiOS()) {
161 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
165 Str[1] = '0' + (Min / 10);
166 Str[2] = '0' + (Min % 10);
167 Str[3] = '0' + (Rev / 10);
168 Str[4] = '0' + (Rev % 10);
171 // Handle versions >= 10.
172 Str[0] = '0' + (Maj / 10);
173 Str[1] = '0' + (Maj % 10);
174 Str[2] = '0' + (Min / 10);
175 Str[3] = '0' + (Min % 10);
176 Str[4] = '0' + (Rev / 10);
177 Str[5] = '0' + (Rev % 10);
181 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str);
183 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
186 } else if (Triple.isWatchOS()) {
187 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
190 Str[1] = '0' + (Min / 10);
191 Str[2] = '0' + (Min % 10);
192 Str[3] = '0' + (Rev / 10);
193 Str[4] = '0' + (Rev % 10);
195 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str);
196 } else if (Triple.isMacOSX()) {
197 // Note that the Driver allows versions which aren't representable in the
198 // define (because we only get a single digit for the minor and micro
199 // revision numbers). So, we limit them to the maximum representable
201 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
203 if (Maj < 10 || (Maj == 10 && Min < 10)) {
204 Str[0] = '0' + (Maj / 10);
205 Str[1] = '0' + (Maj % 10);
206 Str[2] = '0' + std::min(Min, 9U);
207 Str[3] = '0' + std::min(Rev, 9U);
210 // Handle versions > 10.9.
211 Str[0] = '0' + (Maj / 10);
212 Str[1] = '0' + (Maj % 10);
213 Str[2] = '0' + (Min / 10);
214 Str[3] = '0' + (Min % 10);
215 Str[4] = '0' + (Rev / 10);
216 Str[5] = '0' + (Rev % 10);
219 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
222 // Tell users about the kernel if there is one.
223 if (Triple.isOSDarwin())
224 Builder.defineMacro("__MACH__");
226 // The Watch ABI uses Dwarf EH.
227 if(Triple.isWatchABI())
228 Builder.defineMacro("__ARM_DWARF_EH__");
230 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
233 template<typename Target>
234 class DarwinTargetInfo : public OSTargetInfo<Target> {
236 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
237 MacroBuilder &Builder) const override {
238 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
239 this->PlatformMinVersion);
243 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
244 : OSTargetInfo<Target>(Triple, Opts) {
245 // By default, no TLS, and we whitelist permitted architecture/OS
247 this->TLSSupported = false;
249 if (Triple.isMacOSX())
250 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7);
251 else if (Triple.isiOS()) {
252 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards.
253 if (Triple.getArch() == llvm::Triple::x86_64 ||
254 Triple.getArch() == llvm::Triple::aarch64)
255 this->TLSSupported = !Triple.isOSVersionLT(8);
256 else if (Triple.getArch() == llvm::Triple::x86 ||
257 Triple.getArch() == llvm::Triple::arm ||
258 Triple.getArch() == llvm::Triple::thumb)
259 this->TLSSupported = !Triple.isOSVersionLT(9);
260 } else if (Triple.isWatchOS())
261 this->TLSSupported = !Triple.isOSVersionLT(2);
263 this->MCountName = "\01mcount";
266 std::string isValidSectionSpecifier(StringRef SR) const override {
267 // Let MCSectionMachO validate this.
268 StringRef Segment, Section;
269 unsigned TAA, StubSize;
271 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
272 TAA, HasTAA, StubSize);
275 const char *getStaticInitSectionSpecifier() const override {
276 // FIXME: We should return 0 when building kexts.
277 return "__TEXT,__StaticInit,regular,pure_instructions";
280 /// Darwin does not support protected visibility. Darwin's "default"
281 /// is very similar to ELF's "protected"; Darwin requires a "weak"
282 /// attribute on declarations that can be dynamically replaced.
283 bool hasProtectedVisibility() const override {
287 unsigned getExnObjectAlignment() const override {
288 // The alignment of an exception object is 8-bytes for darwin since
289 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned))
290 // and therefore doesn't guarantee 16-byte alignment.
296 // DragonFlyBSD Target
297 template<typename Target>
298 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
300 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
301 MacroBuilder &Builder) const override {
302 // DragonFly defines; list based off of gcc output
303 Builder.defineMacro("__DragonFly__");
304 Builder.defineMacro("__DragonFly_cc_version", "100001");
305 Builder.defineMacro("__ELF__");
306 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
307 Builder.defineMacro("__tune_i386__");
308 DefineStd(Builder, "unix", Opts);
311 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
312 : OSTargetInfo<Target>(Triple, Opts) {
313 switch (Triple.getArch()) {
315 case llvm::Triple::x86:
316 case llvm::Triple::x86_64:
317 this->MCountName = ".mcount";
323 #ifndef FREEBSD_CC_VERSION
324 #define FREEBSD_CC_VERSION 0U
328 template<typename Target>
329 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
331 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
332 MacroBuilder &Builder) const override {
333 // FreeBSD defines; list based off of gcc output
335 unsigned Release = Triple.getOSMajorVersion();
338 unsigned CCVersion = FREEBSD_CC_VERSION;
340 CCVersion = Release * 100000U + 1U;
342 Builder.defineMacro("__FreeBSD__", Twine(Release));
343 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion));
344 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
345 DefineStd(Builder, "unix", Opts);
346 Builder.defineMacro("__ELF__");
348 // On FreeBSD, wchar_t contains the number of the code point as
349 // used by the character set of the locale. These character sets are
350 // not necessarily a superset of ASCII.
352 // FIXME: This is wrong; the macro refers to the numerical values
353 // of wchar_t *literals*, which are not locale-dependent. However,
354 // FreeBSD systems apparently depend on us getting this wrong, and
355 // setting this to 1 is conforming even if all the basic source
356 // character literals have the same encoding as char and wchar_t.
357 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
360 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
361 : OSTargetInfo<Target>(Triple, Opts) {
362 switch (Triple.getArch()) {
364 case llvm::Triple::x86:
365 case llvm::Triple::x86_64:
366 this->MCountName = ".mcount";
368 case llvm::Triple::mips:
369 case llvm::Triple::mipsel:
370 case llvm::Triple::ppc:
371 case llvm::Triple::ppc64:
372 case llvm::Triple::ppc64le:
373 this->MCountName = "_mcount";
375 case llvm::Triple::arm:
376 this->MCountName = "__mcount";
382 // GNU/kFreeBSD Target
383 template<typename Target>
384 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
386 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
387 MacroBuilder &Builder) const override {
388 // GNU/kFreeBSD defines; list based off of gcc output
390 DefineStd(Builder, "unix", Opts);
391 Builder.defineMacro("__FreeBSD_kernel__");
392 Builder.defineMacro("__GLIBC__");
393 Builder.defineMacro("__ELF__");
394 if (Opts.POSIXThreads)
395 Builder.defineMacro("_REENTRANT");
397 Builder.defineMacro("_GNU_SOURCE");
400 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
401 : OSTargetInfo<Target>(Triple, Opts) {}
405 template<typename Target>
406 class HaikuTargetInfo : public OSTargetInfo<Target> {
408 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
409 MacroBuilder &Builder) const override {
410 // Haiku defines; list based off of gcc output
411 Builder.defineMacro("__HAIKU__");
412 Builder.defineMacro("__ELF__");
413 DefineStd(Builder, "unix", Opts);
416 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
417 : OSTargetInfo<Target>(Triple, Opts) {
418 this->SizeType = TargetInfo::UnsignedLong;
419 this->IntPtrType = TargetInfo::SignedLong;
420 this->PtrDiffType = TargetInfo::SignedLong;
421 this->ProcessIDType = TargetInfo::SignedLong;
422 this->TLSSupported = false;
428 template<typename Target>
429 class MinixTargetInfo : public OSTargetInfo<Target> {
431 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
432 MacroBuilder &Builder) const override {
435 Builder.defineMacro("__minix", "3");
436 Builder.defineMacro("_EM_WSIZE", "4");
437 Builder.defineMacro("_EM_PSIZE", "4");
438 Builder.defineMacro("_EM_SSIZE", "2");
439 Builder.defineMacro("_EM_LSIZE", "4");
440 Builder.defineMacro("_EM_FSIZE", "4");
441 Builder.defineMacro("_EM_DSIZE", "8");
442 Builder.defineMacro("__ELF__");
443 DefineStd(Builder, "unix", Opts);
446 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
447 : OSTargetInfo<Target>(Triple, Opts) {}
451 template<typename Target>
452 class LinuxTargetInfo : public OSTargetInfo<Target> {
454 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
455 MacroBuilder &Builder) const override {
456 // Linux defines; list based off of gcc output
457 DefineStd(Builder, "unix", Opts);
458 DefineStd(Builder, "linux", Opts);
459 Builder.defineMacro("__gnu_linux__");
460 Builder.defineMacro("__ELF__");
461 if (Triple.isAndroid()) {
462 Builder.defineMacro("__ANDROID__", "1");
463 unsigned Maj, Min, Rev;
464 Triple.getEnvironmentVersion(Maj, Min, Rev);
465 this->PlatformName = "android";
466 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
468 if (Opts.POSIXThreads)
469 Builder.defineMacro("_REENTRANT");
471 Builder.defineMacro("_GNU_SOURCE");
472 if (this->HasFloat128)
473 Builder.defineMacro("__FLOAT128__");
476 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
477 : OSTargetInfo<Target>(Triple, Opts) {
478 this->WIntType = TargetInfo::UnsignedInt;
480 switch (Triple.getArch()) {
483 case llvm::Triple::ppc:
484 case llvm::Triple::ppc64:
485 case llvm::Triple::ppc64le:
486 this->MCountName = "_mcount";
488 case llvm::Triple::x86:
489 case llvm::Triple::x86_64:
490 case llvm::Triple::systemz:
491 this->HasFloat128 = true;
496 const char *getStaticInitSectionSpecifier() const override {
497 return ".text.startup";
502 template<typename Target>
503 class NetBSDTargetInfo : public OSTargetInfo<Target> {
505 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
506 MacroBuilder &Builder) const override {
507 // NetBSD defines; list based off of gcc output
508 Builder.defineMacro("__NetBSD__");
509 Builder.defineMacro("__unix__");
510 Builder.defineMacro("__ELF__");
511 if (Opts.POSIXThreads)
512 Builder.defineMacro("_POSIX_THREADS");
514 switch (Triple.getArch()) {
517 case llvm::Triple::arm:
518 case llvm::Triple::armeb:
519 case llvm::Triple::thumb:
520 case llvm::Triple::thumbeb:
521 Builder.defineMacro("__ARM_DWARF_EH__");
526 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
527 : OSTargetInfo<Target>(Triple, Opts) {
528 this->MCountName = "_mcount";
533 template<typename Target>
534 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
536 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
537 MacroBuilder &Builder) const override {
538 // OpenBSD defines; list based off of gcc output
540 Builder.defineMacro("__OpenBSD__");
541 DefineStd(Builder, "unix", Opts);
542 Builder.defineMacro("__ELF__");
543 if (Opts.POSIXThreads)
544 Builder.defineMacro("_REENTRANT");
547 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
548 : OSTargetInfo<Target>(Triple, Opts) {
549 this->TLSSupported = false;
551 switch (Triple.getArch()) {
553 case llvm::Triple::x86:
554 case llvm::Triple::x86_64:
555 case llvm::Triple::arm:
556 case llvm::Triple::sparc:
557 this->MCountName = "__mcount";
559 case llvm::Triple::mips64:
560 case llvm::Triple::mips64el:
561 case llvm::Triple::ppc:
562 case llvm::Triple::sparcv9:
563 this->MCountName = "_mcount";
570 template<typename Target>
571 class BitrigTargetInfo : public OSTargetInfo<Target> {
573 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
574 MacroBuilder &Builder) const override {
575 // Bitrig defines; list based off of gcc output
577 Builder.defineMacro("__Bitrig__");
578 DefineStd(Builder, "unix", Opts);
579 Builder.defineMacro("__ELF__");
580 if (Opts.POSIXThreads)
581 Builder.defineMacro("_REENTRANT");
583 switch (Triple.getArch()) {
586 case llvm::Triple::arm:
587 case llvm::Triple::armeb:
588 case llvm::Triple::thumb:
589 case llvm::Triple::thumbeb:
590 Builder.defineMacro("__ARM_DWARF_EH__");
595 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
596 : OSTargetInfo<Target>(Triple, Opts) {
597 this->MCountName = "__mcount";
602 template<typename Target>
603 class PSPTargetInfo : public OSTargetInfo<Target> {
605 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
606 MacroBuilder &Builder) const override {
607 // PSP defines; list based on the output of the pspdev gcc toolchain.
608 Builder.defineMacro("PSP");
609 Builder.defineMacro("_PSP");
610 Builder.defineMacro("__psp__");
611 Builder.defineMacro("__ELF__");
614 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {}
618 template<typename Target>
619 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
621 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
622 MacroBuilder &Builder) const override {
624 Builder.defineMacro("__PPC__");
625 Builder.defineMacro("__PPU__");
626 Builder.defineMacro("__CELLOS_LV2__");
627 Builder.defineMacro("__ELF__");
628 Builder.defineMacro("__LP32__");
629 Builder.defineMacro("_ARCH_PPC64");
630 Builder.defineMacro("__powerpc64__");
633 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
634 : OSTargetInfo<Target>(Triple, Opts) {
635 this->LongWidth = this->LongAlign = 32;
636 this->PointerWidth = this->PointerAlign = 32;
637 this->IntMaxType = TargetInfo::SignedLongLong;
638 this->Int64Type = TargetInfo::SignedLongLong;
639 this->SizeType = TargetInfo::UnsignedInt;
640 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64");
644 template <typename Target>
645 class PS4OSTargetInfo : public OSTargetInfo<Target> {
647 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
648 MacroBuilder &Builder) const override {
649 Builder.defineMacro("__FreeBSD__", "9");
650 Builder.defineMacro("__FreeBSD_cc_version", "900001");
651 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
652 DefineStd(Builder, "unix", Opts);
653 Builder.defineMacro("__ELF__");
654 Builder.defineMacro("__ORBIS__");
657 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
658 : OSTargetInfo<Target>(Triple, Opts) {
659 this->WCharType = this->UnsignedShort;
661 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits).
662 this->MaxTLSAlign = 256;
664 // On PS4, do not honor explicit bit field alignment,
665 // as in "__attribute__((aligned(2))) int b : 1;".
666 this->UseExplicitBitFieldAlignment = false;
668 switch (Triple.getArch()) {
670 case llvm::Triple::x86_64:
671 this->MCountName = ".mcount";
678 template<typename Target>
679 class SolarisTargetInfo : public OSTargetInfo<Target> {
681 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
682 MacroBuilder &Builder) const override {
683 DefineStd(Builder, "sun", Opts);
684 DefineStd(Builder, "unix", Opts);
685 Builder.defineMacro("__ELF__");
686 Builder.defineMacro("__svr4__");
687 Builder.defineMacro("__SVR4");
688 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
689 // newer, but to 500 for everything else. feature_test.h has a check to
690 // ensure that you are not using C99 with an old version of X/Open or C89
691 // with a new version.
693 Builder.defineMacro("_XOPEN_SOURCE", "600");
695 Builder.defineMacro("_XOPEN_SOURCE", "500");
697 Builder.defineMacro("__C99FEATURES__");
698 Builder.defineMacro("_LARGEFILE_SOURCE");
699 Builder.defineMacro("_LARGEFILE64_SOURCE");
700 Builder.defineMacro("__EXTENSIONS__");
701 Builder.defineMacro("_REENTRANT");
704 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
705 : OSTargetInfo<Target>(Triple, Opts) {
706 this->WCharType = this->SignedInt;
707 // FIXME: WIntType should be SignedLong
712 template<typename Target>
713 class WindowsTargetInfo : public OSTargetInfo<Target> {
715 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
716 MacroBuilder &Builder) const override {
717 Builder.defineMacro("_WIN32");
719 void getVisualStudioDefines(const LangOptions &Opts,
720 MacroBuilder &Builder) const {
721 if (Opts.CPlusPlus) {
723 Builder.defineMacro("_CPPRTTI");
725 if (Opts.CXXExceptions)
726 Builder.defineMacro("_CPPUNWIND");
730 Builder.defineMacro("__BOOL_DEFINED");
732 if (!Opts.CharIsSigned)
733 Builder.defineMacro("_CHAR_UNSIGNED");
735 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
736 // but it works for now.
737 if (Opts.POSIXThreads)
738 Builder.defineMacro("_MT");
740 if (Opts.MSCompatibilityVersion) {
741 Builder.defineMacro("_MSC_VER",
742 Twine(Opts.MSCompatibilityVersion / 100000));
743 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
744 // FIXME We cannot encode the revision information into 32-bits
745 Builder.defineMacro("_MSC_BUILD", Twine(1));
747 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
748 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
750 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) {
751 if (Opts.CPlusPlus1z)
752 Builder.defineMacro("_MSVC_LANG", "201403L");
753 else if (Opts.CPlusPlus14)
754 Builder.defineMacro("_MSVC_LANG", "201402L");
758 if (Opts.MicrosoftExt) {
759 Builder.defineMacro("_MSC_EXTENSIONS");
761 if (Opts.CPlusPlus11) {
762 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
763 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
764 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
768 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
772 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
773 : OSTargetInfo<Target>(Triple, Opts) {}
776 template <typename Target>
777 class NaClTargetInfo : public OSTargetInfo<Target> {
779 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
780 MacroBuilder &Builder) const override {
781 if (Opts.POSIXThreads)
782 Builder.defineMacro("_REENTRANT");
784 Builder.defineMacro("_GNU_SOURCE");
786 DefineStd(Builder, "unix", Opts);
787 Builder.defineMacro("__ELF__");
788 Builder.defineMacro("__native_client__");
792 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
793 : OSTargetInfo<Target>(Triple, Opts) {
794 this->LongAlign = 32;
795 this->LongWidth = 32;
796 this->PointerAlign = 32;
797 this->PointerWidth = 32;
798 this->IntMaxType = TargetInfo::SignedLongLong;
799 this->Int64Type = TargetInfo::SignedLongLong;
800 this->DoubleAlign = 64;
801 this->LongDoubleWidth = 64;
802 this->LongDoubleAlign = 64;
803 this->LongLongWidth = 64;
804 this->LongLongAlign = 64;
805 this->SizeType = TargetInfo::UnsignedInt;
806 this->PtrDiffType = TargetInfo::SignedInt;
807 this->IntPtrType = TargetInfo::SignedInt;
808 // RegParmMax is inherited from the underlying architecture
809 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
810 if (Triple.getArch() == llvm::Triple::arm) {
811 // Handled in ARM's setABI().
812 } else if (Triple.getArch() == llvm::Triple::x86) {
813 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128");
814 } else if (Triple.getArch() == llvm::Triple::x86_64) {
815 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128");
816 } else if (Triple.getArch() == llvm::Triple::mipsel) {
817 // Handled on mips' setDataLayout.
819 assert(Triple.getArch() == llvm::Triple::le32);
820 this->resetDataLayout("e-p:32:32-i64:64");
825 // WebAssembly target
826 template <typename Target>
827 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> {
828 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
829 MacroBuilder &Builder) const final {
830 // A common platform macro.
831 if (Opts.POSIXThreads)
832 Builder.defineMacro("_REENTRANT");
833 // Follow g++ convention and predefine _GNU_SOURCE for C++.
835 Builder.defineMacro("_GNU_SOURCE");
838 // As an optimization, group static init code together in a section.
839 const char *getStaticInitSectionSpecifier() const final {
840 return ".text.__startup";
844 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple,
845 const TargetOptions &Opts)
846 : OSTargetInfo<Target>(Triple, Opts) {
847 this->MCountName = "__mcount";
848 this->TheCXXABI.set(TargetCXXABI::WebAssembly);
852 //===----------------------------------------------------------------------===//
853 // Specific target implementations.
854 //===----------------------------------------------------------------------===//
856 // PPC abstract base class
857 class PPCTargetInfo : public TargetInfo {
858 static const Builtin::Info BuiltinInfo[];
859 static const char * const GCCRegNames[];
860 static const TargetInfo::GCCRegAlias GCCRegAliases[];
863 // Target cpu features.
877 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
878 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
879 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
880 HasBPERMD(false), HasExtDiv(false) {
881 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
882 SimdDefaultAlign = 128;
883 LongDoubleWidth = LongDoubleAlign = 128;
884 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
887 /// \brief Flags for architecture specific defines.
890 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
891 ArchDefinePpcgr = 1 << 1,
892 ArchDefinePpcsq = 1 << 2,
893 ArchDefine440 = 1 << 3,
894 ArchDefine603 = 1 << 4,
895 ArchDefine604 = 1 << 5,
896 ArchDefinePwr4 = 1 << 6,
897 ArchDefinePwr5 = 1 << 7,
898 ArchDefinePwr5x = 1 << 8,
899 ArchDefinePwr6 = 1 << 9,
900 ArchDefinePwr6x = 1 << 10,
901 ArchDefinePwr7 = 1 << 11,
902 ArchDefinePwr8 = 1 << 12,
903 ArchDefinePwr9 = 1 << 13,
904 ArchDefineA2 = 1 << 14,
905 ArchDefineA2q = 1 << 15
908 // Note: GCC recognizes the following additional cpus:
909 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
910 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
912 bool setCPU(const std::string &Name) override {
913 bool CPUKnown = llvm::StringSwitch<bool>(Name)
914 .Case("generic", true)
936 .Case("e500mc", true)
938 .Case("power3", true)
940 .Case("power4", true)
942 .Case("power5", true)
944 .Case("power5x", true)
946 .Case("power6", true)
948 .Case("power6x", true)
950 .Case("power7", true)
952 .Case("power8", true)
954 .Case("power9", true)
956 .Case("powerpc", true)
958 .Case("powerpc64", true)
960 .Case("powerpc64le", true)
961 .Case("ppc64le", true)
971 StringRef getABI() const override { return ABI; }
973 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
974 return llvm::makeArrayRef(BuiltinInfo,
975 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin);
978 bool isCLZForZeroUndef() const override { return false; }
980 void getTargetDefines(const LangOptions &Opts,
981 MacroBuilder &Builder) const override;
984 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
986 const std::vector<std::string> &FeaturesVec) const override;
988 bool handleTargetFeatures(std::vector<std::string> &Features,
989 DiagnosticsEngine &Diags) override;
990 bool hasFeature(StringRef Feature) const override;
991 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
992 bool Enabled) const override;
994 ArrayRef<const char *> getGCCRegNames() const override;
995 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
996 bool validateAsmConstraint(const char *&Name,
997 TargetInfo::ConstraintInfo &Info) const override {
999 default: return false;
1002 case 'b': // Base register
1003 case 'f': // Floating point register
1004 Info.setAllowsRegister();
1006 // FIXME: The following are added to allow parsing.
1007 // I just took a guess at what the actions should be.
1008 // Also, is more specific checking needed? I.e. specific registers?
1009 case 'd': // Floating point register (containing 64-bit value)
1010 case 'v': // Altivec vector register
1011 Info.setAllowsRegister();
1015 case 'd':// VSX vector register to hold vector double data
1016 case 'f':// VSX vector register to hold vector float data
1017 case 's':// VSX vector register to hold scalar float data
1018 case 'a':// Any VSX register
1019 case 'c':// An individual CR bit
1024 Info.setAllowsRegister();
1025 Name++; // Skip over 'w'.
1027 case 'h': // `MQ', `CTR', or `LINK' register
1028 case 'q': // `MQ' register
1029 case 'c': // `CTR' register
1030 case 'l': // `LINK' register
1031 case 'x': // `CR' register (condition register) number 0
1032 case 'y': // `CR' register (condition register)
1033 case 'z': // `XER[CA]' carry bit (part of the XER register)
1034 Info.setAllowsRegister();
1036 case 'I': // Signed 16-bit constant
1037 case 'J': // Unsigned 16-bit constant shifted left 16 bits
1038 // (use `L' instead for SImode constants)
1039 case 'K': // Unsigned 16-bit constant
1040 case 'L': // Signed 16-bit constant shifted left 16 bits
1041 case 'M': // Constant larger than 31
1042 case 'N': // Exact power of 2
1043 case 'P': // Constant whose negation is a signed 16-bit constant
1044 case 'G': // Floating point constant that can be loaded into a
1045 // register with one instruction per word
1046 case 'H': // Integer/Floating point constant that can be loaded
1047 // into a register using three instructions
1049 case 'm': // Memory operand. Note that on PowerPC targets, m can
1050 // include addresses that update the base register. It
1051 // is therefore only safe to use `m' in an asm statement
1052 // if that asm statement accesses the operand exactly once.
1053 // The asm statement must also use `%U<opno>' as a
1054 // placeholder for the "update" flag in the corresponding
1055 // load or store instruction. For example:
1056 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
1058 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
1059 // is not. Use es rather than m if you don't want the base
1060 // register to be updated.
1064 // es: A "stable" memory operand; that is, one which does not
1065 // include any automodification of the base register. Unlike
1066 // `m', this constraint can be used in asm statements that
1067 // might access the operand several times, or that might not
1068 // access it at all.
1069 Info.setAllowsMemory();
1070 Name++; // Skip over 'e'.
1072 case 'Q': // Memory operand that is an offset from a register (it is
1073 // usually better to use `m' or `es' in asm statements)
1074 case 'Z': // Memory operand that is an indexed or indirect from a
1075 // register (it is usually better to use `m' or `es' in
1077 Info.setAllowsMemory();
1078 Info.setAllowsRegister();
1080 case 'R': // AIX TOC entry
1081 case 'a': // Address operand that is an indexed or indirect from a
1082 // register (`p' is preferable for asm statements)
1083 case 'S': // Constant suitable as a 64-bit mask operand
1084 case 'T': // Constant suitable as a 32-bit mask operand
1085 case 'U': // System V Release 4 small data area reference
1086 case 't': // AND masks that can be performed by two rldic{l, r}
1088 case 'W': // Vector constant that does not require memory
1089 case 'j': // Vector constant that is all zeros.
1095 std::string convertConstraint(const char *&Constraint) const override {
1097 switch (*Constraint) {
1100 // Two-character constraint; add "^" hint for later parsing.
1101 R = std::string("^") + std::string(Constraint, 2);
1105 return TargetInfo::convertConstraint(Constraint);
1109 const char *getClobbers() const override {
1112 int getEHDataRegisterNumber(unsigned RegNo) const override {
1113 if (RegNo == 0) return 3;
1114 if (RegNo == 1) return 4;
1118 bool hasSjLjLowering() const override {
1122 bool useFloat128ManglingForLongDouble() const override {
1123 return LongDoubleWidth == 128 &&
1124 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble &&
1125 getTriple().isOSBinFormatELF();
1129 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
1130 #define BUILTIN(ID, TYPE, ATTRS) \
1131 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1132 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1133 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1134 #include "clang/Basic/BuiltinsPPC.def"
1137 /// handleTargetFeatures - Perform initialization based on the user
1138 /// configured set of features.
1139 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1140 DiagnosticsEngine &Diags) {
1141 for (const auto &Feature : Features) {
1142 if (Feature == "+vsx") {
1144 } else if (Feature == "+bpermd") {
1146 } else if (Feature == "+extdiv") {
1148 } else if (Feature == "+power8-vector") {
1150 } else if (Feature == "+crypto") {
1152 } else if (Feature == "+direct-move") {
1153 HasDirectMove = true;
1154 } else if (Feature == "+qpx") {
1156 } else if (Feature == "+htm") {
1158 } else if (Feature == "+float128") {
1161 // TODO: Finish this list and add an assert that we've handled them
1168 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1169 /// #defines that are not tied to a specific subtarget.
1170 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1171 MacroBuilder &Builder) const {
1172 // Target identification.
1173 Builder.defineMacro("__ppc__");
1174 Builder.defineMacro("__PPC__");
1175 Builder.defineMacro("_ARCH_PPC");
1176 Builder.defineMacro("__powerpc__");
1177 Builder.defineMacro("__POWERPC__");
1178 if (PointerWidth == 64) {
1179 Builder.defineMacro("_ARCH_PPC64");
1180 Builder.defineMacro("__powerpc64__");
1181 Builder.defineMacro("__ppc64__");
1182 Builder.defineMacro("__PPC64__");
1185 // Target properties.
1186 if (getTriple().getArch() == llvm::Triple::ppc64le) {
1187 Builder.defineMacro("_LITTLE_ENDIAN");
1189 if (getTriple().getOS() != llvm::Triple::NetBSD &&
1190 getTriple().getOS() != llvm::Triple::OpenBSD)
1191 Builder.defineMacro("_BIG_ENDIAN");
1195 if (ABI == "elfv1" || ABI == "elfv1-qpx")
1196 Builder.defineMacro("_CALL_ELF", "1");
1198 Builder.defineMacro("_CALL_ELF", "2");
1200 // Subtarget options.
1201 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1202 Builder.defineMacro("__REGISTER_PREFIX__", "");
1204 // FIXME: Should be controlled by command line option.
1205 if (LongDoubleWidth == 128)
1206 Builder.defineMacro("__LONG_DOUBLE_128__");
1209 Builder.defineMacro("__VEC__", "10206");
1210 Builder.defineMacro("__ALTIVEC__");
1213 // CPU identification.
1214 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1215 .Case("440", ArchDefineName)
1216 .Case("450", ArchDefineName | ArchDefine440)
1217 .Case("601", ArchDefineName)
1218 .Case("602", ArchDefineName | ArchDefinePpcgr)
1219 .Case("603", ArchDefineName | ArchDefinePpcgr)
1220 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1221 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1222 .Case("604", ArchDefineName | ArchDefinePpcgr)
1223 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1224 .Case("620", ArchDefineName | ArchDefinePpcgr)
1225 .Case("630", ArchDefineName | ArchDefinePpcgr)
1226 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1227 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1228 .Case("750", ArchDefineName | ArchDefinePpcgr)
1229 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1231 .Case("a2", ArchDefineA2)
1232 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1233 .Case("pwr3", ArchDefinePpcgr)
1234 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1235 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1237 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1238 | ArchDefinePpcgr | ArchDefinePpcsq)
1239 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1240 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1241 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1242 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1244 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1245 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1246 | ArchDefinePpcgr | ArchDefinePpcsq)
1247 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1248 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1249 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1250 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7
1251 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1252 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1254 .Case("power3", ArchDefinePpcgr)
1255 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1256 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1258 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1259 | ArchDefinePpcgr | ArchDefinePpcsq)
1260 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1261 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1262 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1263 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1265 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1266 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1267 | ArchDefinePpcgr | ArchDefinePpcsq)
1268 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1269 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1270 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1271 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7
1272 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1273 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1275 .Default(ArchDefineNone);
1277 if (defs & ArchDefineName)
1278 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1279 if (defs & ArchDefinePpcgr)
1280 Builder.defineMacro("_ARCH_PPCGR");
1281 if (defs & ArchDefinePpcsq)
1282 Builder.defineMacro("_ARCH_PPCSQ");
1283 if (defs & ArchDefine440)
1284 Builder.defineMacro("_ARCH_440");
1285 if (defs & ArchDefine603)
1286 Builder.defineMacro("_ARCH_603");
1287 if (defs & ArchDefine604)
1288 Builder.defineMacro("_ARCH_604");
1289 if (defs & ArchDefinePwr4)
1290 Builder.defineMacro("_ARCH_PWR4");
1291 if (defs & ArchDefinePwr5)
1292 Builder.defineMacro("_ARCH_PWR5");
1293 if (defs & ArchDefinePwr5x)
1294 Builder.defineMacro("_ARCH_PWR5X");
1295 if (defs & ArchDefinePwr6)
1296 Builder.defineMacro("_ARCH_PWR6");
1297 if (defs & ArchDefinePwr6x)
1298 Builder.defineMacro("_ARCH_PWR6X");
1299 if (defs & ArchDefinePwr7)
1300 Builder.defineMacro("_ARCH_PWR7");
1301 if (defs & ArchDefinePwr8)
1302 Builder.defineMacro("_ARCH_PWR8");
1303 if (defs & ArchDefinePwr9)
1304 Builder.defineMacro("_ARCH_PWR9");
1305 if (defs & ArchDefineA2)
1306 Builder.defineMacro("_ARCH_A2");
1307 if (defs & ArchDefineA2q) {
1308 Builder.defineMacro("_ARCH_A2Q");
1309 Builder.defineMacro("_ARCH_QP");
1312 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1313 Builder.defineMacro("__bg__");
1314 Builder.defineMacro("__THW_BLUEGENE__");
1315 Builder.defineMacro("__bgq__");
1316 Builder.defineMacro("__TOS_BGQ__");
1320 Builder.defineMacro("__VSX__");
1322 Builder.defineMacro("__POWER8_VECTOR__");
1324 Builder.defineMacro("__CRYPTO__");
1326 Builder.defineMacro("__HTM__");
1328 Builder.defineMacro("__FLOAT128__");
1330 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1331 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1332 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1333 if (PointerWidth == 64)
1334 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1336 // FIXME: The following are not yet generated here by Clang, but are
1337 // generated by GCC:
1340 // __RECIP_PRECISION__
1341 // __APPLE_ALTIVEC__
1350 // __CMODEL_MEDIUM__
1357 // Handle explicit options being passed to the compiler here: if we've
1358 // explicitly turned off vsx and turned on power8-vector or direct-move then
1359 // go ahead and error since the customer has expressed a somewhat incompatible
1361 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
1362 const std::vector<std::string> &FeaturesVec) {
1364 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") !=
1365 FeaturesVec.end()) {
1366 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") !=
1367 FeaturesVec.end()) {
1368 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
1373 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") !=
1374 FeaturesVec.end()) {
1375 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
1380 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") !=
1381 FeaturesVec.end()) {
1382 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
1391 bool PPCTargetInfo::initFeatureMap(
1392 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
1393 const std::vector<std::string> &FeaturesVec) const {
1394 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1405 .Case("ppc64", true)
1406 .Case("ppc64le", true)
1409 Features["qpx"] = (CPU == "a2q");
1410 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1411 .Case("ppc64le", true)
1415 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1416 .Case("ppc64le", true)
1420 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1421 .Case("ppc64le", true)
1426 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1427 .Case("ppc64le", true)
1432 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1433 .Case("ppc64le", true)
1437 Features["vsx"] = llvm::StringSwitch<bool>(CPU)
1438 .Case("ppc64le", true)
1444 if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
1447 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1450 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1451 return llvm::StringSwitch<bool>(Feature)
1452 .Case("powerpc", true)
1453 .Case("vsx", HasVSX)
1454 .Case("power8-vector", HasP8Vector)
1455 .Case("crypto", HasP8Crypto)
1456 .Case("direct-move", HasDirectMove)
1457 .Case("qpx", HasQPX)
1458 .Case("htm", HasHTM)
1459 .Case("bpermd", HasBPERMD)
1460 .Case("extdiv", HasExtDiv)
1461 .Case("float128", HasFloat128)
1465 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1466 StringRef Name, bool Enabled) const {
1467 // If we're enabling direct-move or power8-vector go ahead and enable vsx
1468 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user
1469 // incompatible options.
1471 if (Name == "direct-move") {
1472 Features[Name] = Features["vsx"] = true;
1473 } else if (Name == "power8-vector") {
1474 Features[Name] = Features["vsx"] = true;
1475 } else if (Name == "float128") {
1476 Features[Name] = Features["vsx"] = true;
1478 Features[Name] = true;
1481 if (Name == "vsx") {
1482 Features[Name] = Features["direct-move"] = Features["power8-vector"] =
1483 Features["float128"] = false;
1485 Features[Name] = false;
1490 const char * const PPCTargetInfo::GCCRegNames[] = {
1491 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1492 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1493 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1494 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1495 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1496 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1497 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1498 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1499 "mq", "lr", "ctr", "ap",
1500 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1502 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1503 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1504 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1505 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1507 "spe_acc", "spefscr",
1511 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const {
1512 return llvm::makeArrayRef(GCCRegNames);
1515 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1516 // While some of these aliases do map to different registers
1517 // they still share the same register name.
1528 { { "10" }, "r10" },
1529 { { "11" }, "r11" },
1530 { { "12" }, "r12" },
1531 { { "13" }, "r13" },
1532 { { "14" }, "r14" },
1533 { { "15" }, "r15" },
1534 { { "16" }, "r16" },
1535 { { "17" }, "r17" },
1536 { { "18" }, "r18" },
1537 { { "19" }, "r19" },
1538 { { "20" }, "r20" },
1539 { { "21" }, "r21" },
1540 { { "22" }, "r22" },
1541 { { "23" }, "r23" },
1542 { { "24" }, "r24" },
1543 { { "25" }, "r25" },
1544 { { "26" }, "r26" },
1545 { { "27" }, "r27" },
1546 { { "28" }, "r28" },
1547 { { "29" }, "r29" },
1548 { { "30" }, "r30" },
1549 { { "31" }, "r31" },
1550 { { "fr0" }, "f0" },
1551 { { "fr1" }, "f1" },
1552 { { "fr2" }, "f2" },
1553 { { "fr3" }, "f3" },
1554 { { "fr4" }, "f4" },
1555 { { "fr5" }, "f5" },
1556 { { "fr6" }, "f6" },
1557 { { "fr7" }, "f7" },
1558 { { "fr8" }, "f8" },
1559 { { "fr9" }, "f9" },
1560 { { "fr10" }, "f10" },
1561 { { "fr11" }, "f11" },
1562 { { "fr12" }, "f12" },
1563 { { "fr13" }, "f13" },
1564 { { "fr14" }, "f14" },
1565 { { "fr15" }, "f15" },
1566 { { "fr16" }, "f16" },
1567 { { "fr17" }, "f17" },
1568 { { "fr18" }, "f18" },
1569 { { "fr19" }, "f19" },
1570 { { "fr20" }, "f20" },
1571 { { "fr21" }, "f21" },
1572 { { "fr22" }, "f22" },
1573 { { "fr23" }, "f23" },
1574 { { "fr24" }, "f24" },
1575 { { "fr25" }, "f25" },
1576 { { "fr26" }, "f26" },
1577 { { "fr27" }, "f27" },
1578 { { "fr28" }, "f28" },
1579 { { "fr29" }, "f29" },
1580 { { "fr30" }, "f30" },
1581 { { "fr31" }, "f31" },
1582 { { "cc" }, "cr0" },
1585 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
1586 return llvm::makeArrayRef(GCCRegAliases);
1589 class PPC32TargetInfo : public PPCTargetInfo {
1591 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1592 : PPCTargetInfo(Triple, Opts) {
1593 resetDataLayout("E-m:e-p:32:32-i64:64-n32");
1595 switch (getTriple().getOS()) {
1596 case llvm::Triple::Linux:
1597 case llvm::Triple::FreeBSD:
1598 case llvm::Triple::NetBSD:
1599 SizeType = UnsignedInt;
1600 PtrDiffType = SignedInt;
1601 IntPtrType = SignedInt;
1607 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1608 LongDoubleWidth = LongDoubleAlign = 64;
1609 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1612 // PPC32 supports atomics up to 4 bytes.
1613 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1616 BuiltinVaListKind getBuiltinVaListKind() const override {
1617 // This is the ELF definition, and is overridden by the Darwin sub-target
1618 return TargetInfo::PowerABIBuiltinVaList;
1622 // Note: ABI differences may eventually require us to have a separate
1623 // TargetInfo for little endian.
1624 class PPC64TargetInfo : public PPCTargetInfo {
1626 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1627 : PPCTargetInfo(Triple, Opts) {
1628 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1629 IntMaxType = SignedLong;
1630 Int64Type = SignedLong;
1632 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1633 resetDataLayout("e-m:e-i64:64-n32:64");
1636 resetDataLayout("E-m:e-i64:64-n32:64");
1640 switch (getTriple().getOS()) {
1641 case llvm::Triple::FreeBSD:
1642 LongDoubleWidth = LongDoubleAlign = 64;
1643 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1645 case llvm::Triple::NetBSD:
1646 IntMaxType = SignedLongLong;
1647 Int64Type = SignedLongLong;
1653 // PPC64 supports atomics up to 8 bytes.
1654 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1656 BuiltinVaListKind getBuiltinVaListKind() const override {
1657 return TargetInfo::CharPtrBuiltinVaList;
1659 // PPC64 Linux-specific ABI options.
1660 bool setABI(const std::string &Name) override {
1661 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1669 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> {
1671 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1672 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
1673 HasAlignMac68kSupport = true;
1674 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1675 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1677 SuitableAlign = 128;
1678 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
1680 BuiltinVaListKind getBuiltinVaListKind() const override {
1681 return TargetInfo::CharPtrBuiltinVaList;
1685 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> {
1687 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1688 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
1689 HasAlignMac68kSupport = true;
1690 SuitableAlign = 128;
1691 resetDataLayout("E-m:o-i64:64-n32:64");
1695 static const unsigned NVPTXAddrSpaceMap[] = {
1698 4, // opencl_constant
1699 // FIXME: generic has to be added to the target
1700 0, // opencl_generic
1706 class NVPTXTargetInfo : public TargetInfo {
1707 static const char *const GCCRegNames[];
1708 static const Builtin::Info BuiltinInfo[];
1712 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1713 : TargetInfo(Triple) {
1715 TLSSupported = false;
1716 LongWidth = LongAlign = 64;
1717 AddrSpaceMap = &NVPTXAddrSpaceMap;
1718 UseAddrSpaceMapMangling = true;
1719 // Define available target features
1720 // These must be defined in sorted order!
1721 NoAsmVariants = true;
1722 GPU = CudaArch::SM_20;
1724 // If possible, get a TargetInfo for our host triple, so we can match its
1726 llvm::Triple HostTriple(Opts.HostTriple);
1727 if (HostTriple.isNVPTX())
1729 std::unique_ptr<TargetInfo> HostTarget(
1730 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts));
1735 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0);
1736 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0);
1737 BoolWidth = HostTarget->getBoolWidth();
1738 BoolAlign = HostTarget->getBoolAlign();
1739 IntWidth = HostTarget->getIntWidth();
1740 IntAlign = HostTarget->getIntAlign();
1741 HalfWidth = HostTarget->getHalfWidth();
1742 HalfAlign = HostTarget->getHalfAlign();
1743 FloatWidth = HostTarget->getFloatWidth();
1744 FloatAlign = HostTarget->getFloatAlign();
1745 DoubleWidth = HostTarget->getDoubleWidth();
1746 DoubleAlign = HostTarget->getDoubleAlign();
1747 LongWidth = HostTarget->getLongWidth();
1748 LongAlign = HostTarget->getLongAlign();
1749 LongLongWidth = HostTarget->getLongLongWidth();
1750 LongLongAlign = HostTarget->getLongLongAlign();
1751 MinGlobalAlign = HostTarget->getMinGlobalAlign();
1752 DefaultAlignForAttributeAligned =
1753 HostTarget->getDefaultAlignForAttributeAligned();
1754 SizeType = HostTarget->getSizeType();
1755 IntMaxType = HostTarget->getIntMaxType();
1756 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0);
1757 IntPtrType = HostTarget->getIntPtrType();
1758 WCharType = HostTarget->getWCharType();
1759 WIntType = HostTarget->getWIntType();
1760 Char16Type = HostTarget->getChar16Type();
1761 Char32Type = HostTarget->getChar32Type();
1762 Int64Type = HostTarget->getInt64Type();
1763 SigAtomicType = HostTarget->getSigAtomicType();
1764 ProcessIDType = HostTarget->getProcessIDType();
1766 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
1767 UseZeroLengthBitfieldAlignment =
1768 HostTarget->useZeroLengthBitfieldAlignment();
1769 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
1770 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
1772 // Properties intentionally not copied from host:
1773 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the
1774 // host/device boundary.
1775 // - SuitableAlign: Not visible across the host/device boundary, and may
1776 // correctly be different on host/device, e.g. if host has wider vector
1777 // types than device.
1778 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same
1779 // as its double type, but that's not necessarily true on the host.
1780 // TODO: nvcc emits a warning when using long double on device; we should
1783 void getTargetDefines(const LangOptions &Opts,
1784 MacroBuilder &Builder) const override {
1785 Builder.defineMacro("__PTX__");
1786 Builder.defineMacro("__NVPTX__");
1787 if (Opts.CUDAIsDevice) {
1788 // Set __CUDA_ARCH__ for the GPU specified.
1789 std::string CUDAArchCode = [this] {
1791 case CudaArch::UNKNOWN:
1792 assert(false && "No GPU arch when compiling CUDA device code.");
1794 case CudaArch::SM_20:
1796 case CudaArch::SM_21:
1798 case CudaArch::SM_30:
1800 case CudaArch::SM_32:
1802 case CudaArch::SM_35:
1804 case CudaArch::SM_37:
1806 case CudaArch::SM_50:
1808 case CudaArch::SM_52:
1810 case CudaArch::SM_53:
1812 case CudaArch::SM_60:
1814 case CudaArch::SM_61:
1816 case CudaArch::SM_62:
1819 llvm_unreachable("unhandled CudaArch");
1821 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1824 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1825 return llvm::makeArrayRef(BuiltinInfo,
1826 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin);
1828 bool hasFeature(StringRef Feature) const override {
1829 return Feature == "ptx" || Feature == "nvptx";
1832 ArrayRef<const char *> getGCCRegNames() const override;
1833 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1837 bool validateAsmConstraint(const char *&Name,
1838 TargetInfo::ConstraintInfo &Info) const override {
1848 Info.setAllowsRegister();
1852 const char *getClobbers() const override {
1853 // FIXME: Is this really right?
1856 BuiltinVaListKind getBuiltinVaListKind() const override {
1858 return TargetInfo::CharPtrBuiltinVaList;
1860 bool setCPU(const std::string &Name) override {
1861 GPU = StringToCudaArch(Name);
1862 return GPU != CudaArch::UNKNOWN;
1864 void setSupportedOpenCLOpts() override {
1865 auto &Opts = getSupportedOpenCLOpts();
1866 Opts.cl_clang_storage_class_specifiers = 1;
1867 Opts.cl_khr_gl_sharing = 1;
1868 Opts.cl_khr_icd = 1;
1870 Opts.cl_khr_fp64 = 1;
1871 Opts.cl_khr_byte_addressable_store = 1;
1872 Opts.cl_khr_global_int32_base_atomics = 1;
1873 Opts.cl_khr_global_int32_extended_atomics = 1;
1874 Opts.cl_khr_local_int32_base_atomics = 1;
1875 Opts.cl_khr_local_int32_extended_atomics = 1;
1879 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1880 #define BUILTIN(ID, TYPE, ATTRS) \
1881 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1882 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1883 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1884 #include "clang/Basic/BuiltinsNVPTX.def"
1887 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
1889 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
1890 return llvm::makeArrayRef(GCCRegNames);
1893 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1895 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1896 : NVPTXTargetInfo(Triple, Opts) {
1897 LongWidth = LongAlign = 32;
1898 PointerWidth = PointerAlign = 32;
1899 SizeType = TargetInfo::UnsignedInt;
1900 PtrDiffType = TargetInfo::SignedInt;
1901 IntPtrType = TargetInfo::SignedInt;
1902 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64");
1906 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1908 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1909 : NVPTXTargetInfo(Triple, Opts) {
1910 PointerWidth = PointerAlign = 64;
1911 SizeType = TargetInfo::UnsignedLong;
1912 PtrDiffType = TargetInfo::SignedLong;
1913 IntPtrType = TargetInfo::SignedLong;
1914 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64");
1918 static const unsigned AMDGPUAddrSpaceMap[] = {
1921 2, // opencl_constant
1922 4, // opencl_generic
1928 // If you edit the description strings, make sure you update
1929 // getPointerWidthV().
1931 static const char *const DataLayoutStringR600 =
1932 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1933 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1935 static const char *const DataLayoutStringSI =
1936 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
1937 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1938 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1940 class AMDGPUTargetInfo final : public TargetInfo {
1941 static const Builtin::Info BuiltinInfo[];
1942 static const char * const GCCRegNames[];
1944 /// \brief The GPU profiles supported by the AMDGPU target.
1952 GK_EVERGREEN_DOUBLE_OPS,
1953 GK_NORTHERN_ISLANDS,
1955 GK_SOUTHERN_ISLANDS,
1964 static bool isAMDGCN(const llvm::Triple &TT) {
1965 return TT.getArch() == llvm::Triple::amdgcn;
1969 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
1970 : TargetInfo(Triple) ,
1971 GPU(isAMDGCN(Triple) ? GK_SOUTHERN_ISLANDS : GK_R600),
1975 if (getTriple().getArch() == llvm::Triple::amdgcn) {
1981 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ?
1982 DataLayoutStringSI : DataLayoutStringR600);
1984 AddrSpaceMap = &AMDGPUAddrSpaceMap;
1985 UseAddrSpaceMapMangling = true;
1988 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1989 if (GPU <= GK_CAYMAN)
2002 const char * getClobbers() const override {
2006 ArrayRef<const char *> getGCCRegNames() const override;
2008 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2012 bool validateAsmConstraint(const char *&Name,
2013 TargetInfo::ConstraintInfo &Info) const override {
2018 Info.setAllowsRegister();
2024 bool initFeatureMap(llvm::StringMap<bool> &Features,
2025 DiagnosticsEngine &Diags, StringRef CPU,
2026 const std::vector<std::string> &FeatureVec) const override;
2028 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
2029 return llvm::makeArrayRef(BuiltinInfo,
2030 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin);
2033 void getTargetDefines(const LangOptions &Opts,
2034 MacroBuilder &Builder) const override {
2035 if (getTriple().getArch() == llvm::Triple::amdgcn)
2036 Builder.defineMacro("__AMDGCN__");
2038 Builder.defineMacro("__R600__");
2041 Builder.defineMacro("__HAS_FMAF__");
2043 Builder.defineMacro("__HAS_LDEXPF__");
2045 Builder.defineMacro("__HAS_FP64__");
2048 BuiltinVaListKind getBuiltinVaListKind() const override {
2049 return TargetInfo::CharPtrBuiltinVaList;
2052 static GPUKind parseR600Name(StringRef Name) {
2053 return llvm::StringSwitch<GPUKind>(Name)
2054 .Case("r600" , GK_R600)
2055 .Case("rv610", GK_R600)
2056 .Case("rv620", GK_R600)
2057 .Case("rv630", GK_R600)
2058 .Case("rv635", GK_R600)
2059 .Case("rs780", GK_R600)
2060 .Case("rs880", GK_R600)
2061 .Case("rv670", GK_R600_DOUBLE_OPS)
2062 .Case("rv710", GK_R700)
2063 .Case("rv730", GK_R700)
2064 .Case("rv740", GK_R700_DOUBLE_OPS)
2065 .Case("rv770", GK_R700_DOUBLE_OPS)
2066 .Case("palm", GK_EVERGREEN)
2067 .Case("cedar", GK_EVERGREEN)
2068 .Case("sumo", GK_EVERGREEN)
2069 .Case("sumo2", GK_EVERGREEN)
2070 .Case("redwood", GK_EVERGREEN)
2071 .Case("juniper", GK_EVERGREEN)
2072 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
2073 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
2074 .Case("barts", GK_NORTHERN_ISLANDS)
2075 .Case("turks", GK_NORTHERN_ISLANDS)
2076 .Case("caicos", GK_NORTHERN_ISLANDS)
2077 .Case("cayman", GK_CAYMAN)
2078 .Case("aruba", GK_CAYMAN)
2082 static GPUKind parseAMDGCNName(StringRef Name) {
2083 return llvm::StringSwitch<GPUKind>(Name)
2084 .Case("tahiti", GK_SOUTHERN_ISLANDS)
2085 .Case("pitcairn", GK_SOUTHERN_ISLANDS)
2086 .Case("verde", GK_SOUTHERN_ISLANDS)
2087 .Case("oland", GK_SOUTHERN_ISLANDS)
2088 .Case("hainan", GK_SOUTHERN_ISLANDS)
2089 .Case("bonaire", GK_SEA_ISLANDS)
2090 .Case("kabini", GK_SEA_ISLANDS)
2091 .Case("kaveri", GK_SEA_ISLANDS)
2092 .Case("hawaii", GK_SEA_ISLANDS)
2093 .Case("mullins", GK_SEA_ISLANDS)
2094 .Case("tonga", GK_VOLCANIC_ISLANDS)
2095 .Case("iceland", GK_VOLCANIC_ISLANDS)
2096 .Case("carrizo", GK_VOLCANIC_ISLANDS)
2097 .Case("fiji", GK_VOLCANIC_ISLANDS)
2098 .Case("stoney", GK_VOLCANIC_ISLANDS)
2099 .Case("polaris10", GK_VOLCANIC_ISLANDS)
2100 .Case("polaris11", GK_VOLCANIC_ISLANDS)
2104 bool setCPU(const std::string &Name) override {
2105 if (getTriple().getArch() == llvm::Triple::amdgcn)
2106 GPU = parseAMDGCNName(Name);
2108 GPU = parseR600Name(Name);
2110 return GPU != GK_NONE;
2113 void setSupportedOpenCLOpts() override {
2114 auto &Opts = getSupportedOpenCLOpts();
2115 Opts.cl_clang_storage_class_specifiers = 1;
2116 Opts.cl_khr_icd = 1;
2119 Opts.cl_khr_fp64 = 1;
2120 if (GPU >= GK_EVERGREEN) {
2121 Opts.cl_khr_byte_addressable_store = 1;
2122 Opts.cl_khr_global_int32_base_atomics = 1;
2123 Opts.cl_khr_global_int32_extended_atomics = 1;
2124 Opts.cl_khr_local_int32_base_atomics = 1;
2125 Opts.cl_khr_local_int32_extended_atomics = 1;
2127 if (GPU >= GK_SOUTHERN_ISLANDS) {
2128 Opts.cl_khr_fp16 = 1;
2129 Opts.cl_khr_int64_base_atomics = 1;
2130 Opts.cl_khr_int64_extended_atomics = 1;
2131 Opts.cl_khr_3d_image_writes = 1;
2135 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2138 return CCCR_Warning;
2140 case CC_OpenCLKernel:
2146 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
2147 #define BUILTIN(ID, TYPE, ATTRS) \
2148 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2149 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2150 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2151 #include "clang/Basic/BuiltinsAMDGPU.def"
2153 const char * const AMDGPUTargetInfo::GCCRegNames[] = {
2154 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2155 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2156 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2157 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
2158 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
2159 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
2160 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
2161 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
2162 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
2163 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
2164 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
2165 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
2166 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
2167 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
2168 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
2169 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
2170 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
2171 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
2172 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
2173 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
2174 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
2175 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
2176 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
2177 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
2178 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
2179 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
2180 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
2181 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
2182 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
2183 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
2184 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
2185 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
2186 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2187 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
2188 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
2189 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
2190 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
2191 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
2192 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
2193 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
2194 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
2195 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
2196 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
2197 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
2198 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
2199 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
2200 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
2201 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127",
2202 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi",
2203 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi"
2206 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const {
2207 return llvm::makeArrayRef(GCCRegNames);
2210 bool AMDGPUTargetInfo::initFeatureMap(
2211 llvm::StringMap<bool> &Features,
2212 DiagnosticsEngine &Diags, StringRef CPU,
2213 const std::vector<std::string> &FeatureVec) const {
2215 // XXX - What does the member GPU mean if device name string passed here?
2216 if (getTriple().getArch() == llvm::Triple::amdgcn) {
2220 switch (parseAMDGCNName(CPU)) {
2221 case GK_SOUTHERN_ISLANDS:
2222 case GK_SEA_ISLANDS:
2225 case GK_VOLCANIC_ISLANDS:
2226 Features["s-memrealtime"] = true;
2227 Features["16-bit-insts"] = true;
2233 llvm_unreachable("unhandled subtarget");
2239 switch (parseR600Name(CPU)) {
2243 case GK_NORTHERN_ISLANDS:
2245 case GK_R600_DOUBLE_OPS:
2246 case GK_R700_DOUBLE_OPS:
2247 case GK_EVERGREEN_DOUBLE_OPS:
2249 Features["fp64"] = true;
2254 llvm_unreachable("unhandled subtarget");
2258 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec);
2261 // Namespace for x86 abstract base class
2262 const Builtin::Info BuiltinInfo[] = {
2263 #define BUILTIN(ID, TYPE, ATTRS) \
2264 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2265 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
2266 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
2267 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2268 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2269 #include "clang/Basic/BuiltinsX86.def"
2272 static const char* const GCCRegNames[] = {
2273 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
2274 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
2275 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
2276 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
2277 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
2278 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2279 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
2280 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
2281 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
2282 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23",
2283 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31",
2284 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23",
2285 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31",
2286 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7",
2287 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15",
2288 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23",
2289 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31",
2292 const TargetInfo::AddlRegName AddlRegNames[] = {
2293 { { "al", "ah", "eax", "rax" }, 0 },
2294 { { "bl", "bh", "ebx", "rbx" }, 3 },
2295 { { "cl", "ch", "ecx", "rcx" }, 2 },
2296 { { "dl", "dh", "edx", "rdx" }, 1 },
2297 { { "esi", "rsi" }, 4 },
2298 { { "edi", "rdi" }, 5 },
2299 { { "esp", "rsp" }, 7 },
2300 { { "ebp", "rbp" }, 6 },
2301 { { "r8d", "r8w", "r8b" }, 38 },
2302 { { "r9d", "r9w", "r9b" }, 39 },
2303 { { "r10d", "r10w", "r10b" }, 40 },
2304 { { "r11d", "r11w", "r11b" }, 41 },
2305 { { "r12d", "r12w", "r12b" }, 42 },
2306 { { "r13d", "r13w", "r13b" }, 43 },
2307 { { "r14d", "r14w", "r14b" }, 44 },
2308 { { "r15d", "r15w", "r15b" }, 45 },
2311 // X86 target abstract base class; x86-32 and x86-64 are very close, so
2312 // most of the implementation can be shared.
2313 class X86TargetInfo : public TargetInfo {
2315 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
2318 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
2319 } MMX3DNowLevel = NoMMX3DNow;
2327 bool HasAES = false;
2328 bool HasPCLMUL = false;
2329 bool HasLZCNT = false;
2330 bool HasRDRND = false;
2331 bool HasFSGSBASE = false;
2332 bool HasBMI = false;
2333 bool HasBMI2 = false;
2334 bool HasPOPCNT = false;
2335 bool HasRTM = false;
2336 bool HasPRFCHW = false;
2337 bool HasRDSEED = false;
2338 bool HasADX = false;
2339 bool HasTBM = false;
2340 bool HasFMA = false;
2341 bool HasF16C = false;
2342 bool HasAVX512CD = false;
2343 bool HasAVX512ER = false;
2344 bool HasAVX512PF = false;
2345 bool HasAVX512DQ = false;
2346 bool HasAVX512BW = false;
2347 bool HasAVX512VL = false;
2348 bool HasAVX512VBMI = false;
2349 bool HasAVX512IFMA = false;
2350 bool HasSHA = false;
2351 bool HasMPX = false;
2352 bool HasSGX = false;
2353 bool HasCX16 = false;
2354 bool HasFXSR = false;
2355 bool HasXSAVE = false;
2356 bool HasXSAVEOPT = false;
2357 bool HasXSAVEC = false;
2358 bool HasXSAVES = false;
2359 bool HasMWAITX = false;
2360 bool HasPKU = false;
2361 bool HasCLFLUSHOPT = false;
2362 bool HasPCOMMIT = false;
2363 bool HasCLWB = false;
2364 bool HasUMIP = false;
2365 bool HasMOVBE = false;
2366 bool HasPREFETCHWT1 = false;
2368 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2370 /// Each enumeration represents a particular CPU supported by Clang. These
2371 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2376 /// i386-generation processors.
2382 /// i486-generation processors.
2391 /// i586-generation processors, P5 microarchitecture based.
2399 /// i686-generation processors, P6 / Pentium M microarchitecture based.
2409 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2410 /// Clang however has some logic to suport this.
2411 // FIXME: Warn, deprecate, and potentially remove this.
2416 /// Netburst microarchitecture based processors.
2425 /// Core microarchitecture based processors.
2429 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2430 /// codename which GCC no longer accepts as an option to -march, but Clang
2431 /// has some logic for recognizing it.
2432 // FIXME: Warn, deprecate, and potentially remove this.
2444 /// Nehalem microarchitecture based processors.
2448 /// Westmere microarchitecture based processors.
2451 /// \name Sandy Bridge
2452 /// Sandy Bridge microarchitecture based processors.
2455 /// \name Ivy Bridge
2456 /// Ivy Bridge microarchitecture based processors.
2460 /// Haswell microarchitecture based processors.
2464 /// Broadwell microarchitecture based processors.
2467 /// \name Skylake Client
2468 /// Skylake client microarchitecture based processors.
2471 /// \name Skylake Server
2472 /// Skylake server microarchitecture based processors.
2475 /// \name Cannonlake Client
2476 /// Cannonlake client microarchitecture based processors.
2479 /// \name Knights Landing
2480 /// Knights Landing processor.
2484 /// Lakemont microarchitecture based processors.
2488 /// K6 architecture processors.
2496 /// K7 architecture processors.
2499 CK_AthlonThunderbird,
2506 /// K8 architecture processors.
2519 /// Bobcat architecture processors.
2526 /// Bulldozer architecture processors.
2534 /// This specification is deprecated and will be removed in the future.
2535 /// Users should prefer \see CK_K8.
2536 // FIXME: Warn on this when the CPU is set to it.
2542 /// Geode processors.
2548 CPUKind getCPUKind(StringRef CPU) const {
2549 return llvm::StringSwitch<CPUKind>(CPU)
2550 .Case("i386", CK_i386)
2551 .Case("i486", CK_i486)
2552 .Case("winchip-c6", CK_WinChipC6)
2553 .Case("winchip2", CK_WinChip2)
2555 .Case("i586", CK_i586)
2556 .Case("pentium", CK_Pentium)
2557 .Case("pentium-mmx", CK_PentiumMMX)
2558 .Case("i686", CK_i686)
2559 .Case("pentiumpro", CK_PentiumPro)
2560 .Case("pentium2", CK_Pentium2)
2561 .Case("pentium3", CK_Pentium3)
2562 .Case("pentium3m", CK_Pentium3M)
2563 .Case("pentium-m", CK_PentiumM)
2564 .Case("c3-2", CK_C3_2)
2565 .Case("yonah", CK_Yonah)
2566 .Case("pentium4", CK_Pentium4)
2567 .Case("pentium4m", CK_Pentium4M)
2568 .Case("prescott", CK_Prescott)
2569 .Case("nocona", CK_Nocona)
2570 .Case("core2", CK_Core2)
2571 .Case("penryn", CK_Penryn)
2572 .Case("bonnell", CK_Bonnell)
2573 .Case("atom", CK_Bonnell) // Legacy name.
2574 .Case("silvermont", CK_Silvermont)
2575 .Case("slm", CK_Silvermont) // Legacy name.
2576 .Case("nehalem", CK_Nehalem)
2577 .Case("corei7", CK_Nehalem) // Legacy name.
2578 .Case("westmere", CK_Westmere)
2579 .Case("sandybridge", CK_SandyBridge)
2580 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2581 .Case("ivybridge", CK_IvyBridge)
2582 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2583 .Case("haswell", CK_Haswell)
2584 .Case("core-avx2", CK_Haswell) // Legacy name.
2585 .Case("broadwell", CK_Broadwell)
2586 .Case("skylake", CK_SkylakeClient)
2587 .Case("skylake-avx512", CK_SkylakeServer)
2588 .Case("skx", CK_SkylakeServer) // Legacy name.
2589 .Case("cannonlake", CK_Cannonlake)
2590 .Case("knl", CK_KNL)
2591 .Case("lakemont", CK_Lakemont)
2593 .Case("k6-2", CK_K6_2)
2594 .Case("k6-3", CK_K6_3)
2595 .Case("athlon", CK_Athlon)
2596 .Case("athlon-tbird", CK_AthlonThunderbird)
2597 .Case("athlon-4", CK_Athlon4)
2598 .Case("athlon-xp", CK_AthlonXP)
2599 .Case("athlon-mp", CK_AthlonMP)
2600 .Case("athlon64", CK_Athlon64)
2601 .Case("athlon64-sse3", CK_Athlon64SSE3)
2602 .Case("athlon-fx", CK_AthlonFX)
2604 .Case("k8-sse3", CK_K8SSE3)
2605 .Case("opteron", CK_Opteron)
2606 .Case("opteron-sse3", CK_OpteronSSE3)
2607 .Case("barcelona", CK_AMDFAM10)
2608 .Case("amdfam10", CK_AMDFAM10)
2609 .Case("btver1", CK_BTVER1)
2610 .Case("btver2", CK_BTVER2)
2611 .Case("bdver1", CK_BDVER1)
2612 .Case("bdver2", CK_BDVER2)
2613 .Case("bdver3", CK_BDVER3)
2614 .Case("bdver4", CK_BDVER4)
2615 .Case("x86-64", CK_x86_64)
2616 .Case("geode", CK_Geode)
2617 .Default(CK_Generic);
2624 } FPMath = FP_Default;
2627 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
2628 : TargetInfo(Triple) {
2630 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
2632 unsigned getFloatEvalMethod() const override {
2633 // X87 evaluates with 80 bits "long double" precision.
2634 return SSELevel == NoSSE ? 2 : 0;
2636 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
2637 return llvm::makeArrayRef(BuiltinInfo,
2638 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin);
2640 ArrayRef<const char *> getGCCRegNames() const override {
2641 return llvm::makeArrayRef(GCCRegNames);
2643 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2646 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
2647 return llvm::makeArrayRef(AddlRegNames);
2649 bool validateCpuSupports(StringRef Name) const override;
2650 bool validateAsmConstraint(const char *&Name,
2651 TargetInfo::ConstraintInfo &info) const override;
2653 bool validateGlobalRegisterVariable(StringRef RegName,
2655 bool &HasSizeMismatch) const override {
2656 // esp and ebp are the only 32-bit registers the x86 backend can currently
2658 if (RegName.equals("esp") || RegName.equals("ebp")) {
2659 // Check that the register size is 32-bit.
2660 HasSizeMismatch = RegSize != 32;
2667 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2669 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2671 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2673 std::string convertConstraint(const char *&Constraint) const override;
2674 const char *getClobbers() const override {
2675 return "~{dirflag},~{fpsr},~{flags}";
2677 void getTargetDefines(const LangOptions &Opts,
2678 MacroBuilder &Builder) const override;
2679 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2681 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2683 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2685 void setFeatureEnabled(llvm::StringMap<bool> &Features,
2686 StringRef Name, bool Enabled) const override {
2687 setFeatureEnabledImpl(Features, Name, Enabled);
2689 // This exists purely to cut down on the number of virtual calls in
2690 // initFeatureMap which calls this repeatedly.
2691 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2692 StringRef Name, bool Enabled);
2694 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
2696 const std::vector<std::string> &FeaturesVec) const override;
2697 bool hasFeature(StringRef Feature) const override;
2698 bool handleTargetFeatures(std::vector<std::string> &Features,
2699 DiagnosticsEngine &Diags) override;
2700 StringRef getABI() const override {
2701 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
2703 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2705 if (getTriple().getArch() == llvm::Triple::x86 &&
2706 MMX3DNowLevel == NoMMX3DNow)
2710 bool setCPU(const std::string &Name) override {
2711 CPU = getCPUKind(Name);
2713 // Perform any per-CPU checks necessary to determine if this CPU is
2715 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2716 // invalid without explaining *why*.
2719 // No processor selected!
2746 case CK_AthlonThunderbird:
2751 // Only accept certain architectures when compiling in 32-bit mode.
2752 if (getTriple().getArch() != llvm::Triple::x86)
2763 case CK_SandyBridge:
2767 case CK_SkylakeClient:
2768 case CK_SkylakeServer:
2772 case CK_Athlon64SSE3:
2777 case CK_OpteronSSE3:
2788 llvm_unreachable("Unhandled CPU kind");
2791 bool setFPMath(StringRef Name) override;
2793 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2794 // Most of the non-ARM calling conventions are i386 conventions.
2796 case CC_X86ThisCall:
2797 case CC_X86FastCall:
2799 case CC_X86VectorCall:
2803 case CC_IntelOclBicc:
2806 return CCCR_Warning;
2810 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2811 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2814 bool hasSjLjLowering() const override {
2818 void setSupportedOpenCLOpts() override {
2819 getSupportedOpenCLOpts().setAll();
2823 bool X86TargetInfo::setFPMath(StringRef Name) {
2824 if (Name == "387") {
2828 if (Name == "sse") {
2835 bool X86TargetInfo::initFeatureMap(
2836 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
2837 const std::vector<std::string> &FeaturesVec) const {
2838 // FIXME: This *really* should not be here.
2839 // X86_64 always has SSE2.
2840 if (getTriple().getArch() == llvm::Triple::x86_64)
2841 setFeatureEnabledImpl(Features, "sse2", true);
2843 const CPUKind Kind = getCPUKind(CPU);
2845 // Enable X87 for all X86 processors but Lakemont.
2846 if (Kind != CK_Lakemont)
2847 setFeatureEnabledImpl(Features, "x87", true);
2863 setFeatureEnabledImpl(Features, "mmx", true);
2868 setFeatureEnabledImpl(Features, "sse", true);
2869 setFeatureEnabledImpl(Features, "fxsr", true);
2875 setFeatureEnabledImpl(Features, "sse2", true);
2876 setFeatureEnabledImpl(Features, "fxsr", true);
2881 setFeatureEnabledImpl(Features, "sse3", true);
2882 setFeatureEnabledImpl(Features, "fxsr", true);
2883 setFeatureEnabledImpl(Features, "cx16", true);
2887 setFeatureEnabledImpl(Features, "ssse3", true);
2888 setFeatureEnabledImpl(Features, "fxsr", true);
2889 setFeatureEnabledImpl(Features, "cx16", true);
2892 setFeatureEnabledImpl(Features, "sse4.1", true);
2893 setFeatureEnabledImpl(Features, "fxsr", true);
2894 setFeatureEnabledImpl(Features, "cx16", true);
2897 setFeatureEnabledImpl(Features, "avx512ifma", true);
2898 setFeatureEnabledImpl(Features, "avx512vbmi", true);
2899 setFeatureEnabledImpl(Features, "sha", true);
2900 setFeatureEnabledImpl(Features, "umip", true);
2902 case CK_SkylakeServer:
2903 setFeatureEnabledImpl(Features, "avx512f", true);
2904 setFeatureEnabledImpl(Features, "avx512cd", true);
2905 setFeatureEnabledImpl(Features, "avx512dq", true);
2906 setFeatureEnabledImpl(Features, "avx512bw", true);
2907 setFeatureEnabledImpl(Features, "avx512vl", true);
2908 setFeatureEnabledImpl(Features, "pku", true);
2909 setFeatureEnabledImpl(Features, "pcommit", true);
2910 setFeatureEnabledImpl(Features, "clwb", true);
2912 case CK_SkylakeClient:
2913 setFeatureEnabledImpl(Features, "xsavec", true);
2914 setFeatureEnabledImpl(Features, "xsaves", true);
2915 setFeatureEnabledImpl(Features, "mpx", true);
2916 setFeatureEnabledImpl(Features, "sgx", true);
2917 setFeatureEnabledImpl(Features, "clflushopt", true);
2920 setFeatureEnabledImpl(Features, "rdseed", true);
2921 setFeatureEnabledImpl(Features, "adx", true);
2924 setFeatureEnabledImpl(Features, "avx2", true);
2925 setFeatureEnabledImpl(Features, "lzcnt", true);
2926 setFeatureEnabledImpl(Features, "bmi", true);
2927 setFeatureEnabledImpl(Features, "bmi2", true);
2928 setFeatureEnabledImpl(Features, "rtm", true);
2929 setFeatureEnabledImpl(Features, "fma", true);
2930 setFeatureEnabledImpl(Features, "movbe", true);
2933 setFeatureEnabledImpl(Features, "rdrnd", true);
2934 setFeatureEnabledImpl(Features, "f16c", true);
2935 setFeatureEnabledImpl(Features, "fsgsbase", true);
2937 case CK_SandyBridge:
2938 setFeatureEnabledImpl(Features, "avx", true);
2939 setFeatureEnabledImpl(Features, "xsave", true);
2940 setFeatureEnabledImpl(Features, "xsaveopt", true);
2944 setFeatureEnabledImpl(Features, "aes", true);
2945 setFeatureEnabledImpl(Features, "pclmul", true);
2948 setFeatureEnabledImpl(Features, "sse4.2", true);
2949 setFeatureEnabledImpl(Features, "fxsr", true);
2950 setFeatureEnabledImpl(Features, "cx16", true);
2953 setFeatureEnabledImpl(Features, "avx512f", true);
2954 setFeatureEnabledImpl(Features, "avx512cd", true);
2955 setFeatureEnabledImpl(Features, "avx512er", true);
2956 setFeatureEnabledImpl(Features, "avx512pf", true);
2957 setFeatureEnabledImpl(Features, "prefetchwt1", true);
2958 setFeatureEnabledImpl(Features, "fxsr", true);
2959 setFeatureEnabledImpl(Features, "rdseed", true);
2960 setFeatureEnabledImpl(Features, "adx", true);
2961 setFeatureEnabledImpl(Features, "lzcnt", true);
2962 setFeatureEnabledImpl(Features, "bmi", true);
2963 setFeatureEnabledImpl(Features, "bmi2", true);
2964 setFeatureEnabledImpl(Features, "rtm", true);
2965 setFeatureEnabledImpl(Features, "fma", true);
2966 setFeatureEnabledImpl(Features, "rdrnd", true);
2967 setFeatureEnabledImpl(Features, "f16c", true);
2968 setFeatureEnabledImpl(Features, "fsgsbase", true);
2969 setFeatureEnabledImpl(Features, "aes", true);
2970 setFeatureEnabledImpl(Features, "pclmul", true);
2971 setFeatureEnabledImpl(Features, "cx16", true);
2972 setFeatureEnabledImpl(Features, "xsaveopt", true);
2973 setFeatureEnabledImpl(Features, "xsave", true);
2974 setFeatureEnabledImpl(Features, "movbe", true);
2980 setFeatureEnabledImpl(Features, "3dnow", true);
2983 case CK_AthlonThunderbird:
2985 setFeatureEnabledImpl(Features, "3dnowa", true);
2990 setFeatureEnabledImpl(Features, "sse", true);
2991 setFeatureEnabledImpl(Features, "3dnowa", true);
2992 setFeatureEnabledImpl(Features, "fxsr", true);
2998 setFeatureEnabledImpl(Features, "sse2", true);
2999 setFeatureEnabledImpl(Features, "3dnowa", true);
3000 setFeatureEnabledImpl(Features, "fxsr", true);
3003 setFeatureEnabledImpl(Features, "sse4a", true);
3004 setFeatureEnabledImpl(Features, "lzcnt", true);
3005 setFeatureEnabledImpl(Features, "popcnt", true);
3008 case CK_OpteronSSE3:
3009 case CK_Athlon64SSE3:
3010 setFeatureEnabledImpl(Features, "sse3", true);
3011 setFeatureEnabledImpl(Features, "3dnowa", true);
3012 setFeatureEnabledImpl(Features, "fxsr", true);
3015 setFeatureEnabledImpl(Features, "avx", true);
3016 setFeatureEnabledImpl(Features, "aes", true);
3017 setFeatureEnabledImpl(Features, "pclmul", true);
3018 setFeatureEnabledImpl(Features, "bmi", true);
3019 setFeatureEnabledImpl(Features, "f16c", true);
3020 setFeatureEnabledImpl(Features, "xsaveopt", true);
3023 setFeatureEnabledImpl(Features, "ssse3", true);
3024 setFeatureEnabledImpl(Features, "sse4a", true);
3025 setFeatureEnabledImpl(Features, "lzcnt", true);
3026 setFeatureEnabledImpl(Features, "popcnt", true);
3027 setFeatureEnabledImpl(Features, "prfchw", true);
3028 setFeatureEnabledImpl(Features, "cx16", true);
3029 setFeatureEnabledImpl(Features, "fxsr", true);
3032 setFeatureEnabledImpl(Features, "avx2", true);
3033 setFeatureEnabledImpl(Features, "bmi2", true);
3034 setFeatureEnabledImpl(Features, "mwaitx", true);
3037 setFeatureEnabledImpl(Features, "fsgsbase", true);
3038 setFeatureEnabledImpl(Features, "xsaveopt", true);
3041 setFeatureEnabledImpl(Features, "bmi", true);
3042 setFeatureEnabledImpl(Features, "fma", true);
3043 setFeatureEnabledImpl(Features, "f16c", true);
3044 setFeatureEnabledImpl(Features, "tbm", true);
3047 // xop implies avx, sse4a and fma4.
3048 setFeatureEnabledImpl(Features, "xop", true);
3049 setFeatureEnabledImpl(Features, "lzcnt", true);
3050 setFeatureEnabledImpl(Features, "aes", true);
3051 setFeatureEnabledImpl(Features, "pclmul", true);
3052 setFeatureEnabledImpl(Features, "prfchw", true);
3053 setFeatureEnabledImpl(Features, "cx16", true);
3054 setFeatureEnabledImpl(Features, "fxsr", true);
3055 setFeatureEnabledImpl(Features, "xsave", true);
3058 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
3061 // Can't do this earlier because we need to be able to explicitly enable
3062 // or disable these features and the things that they depend upon.
3064 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
3065 auto I = Features.find("sse4.2");
3066 if (I != Features.end() && I->getValue() &&
3067 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
3069 Features["popcnt"] = true;
3071 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
3072 I = Features.find("3dnow");
3073 if (I != Features.end() && I->getValue() &&
3074 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
3076 Features["prfchw"] = true;
3078 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
3080 I = Features.find("sse");
3081 if (I != Features.end() && I->getValue() &&
3082 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
3084 Features["mmx"] = true;
3089 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
3090 X86SSEEnum Level, bool Enabled) {
3094 Features["avx512f"] = true;
3096 Features["avx2"] = true;
3098 Features["avx"] = true;
3099 Features["xsave"] = true;
3101 Features["sse4.2"] = true;
3103 Features["sse4.1"] = true;
3105 Features["ssse3"] = true;
3107 Features["sse3"] = true;
3109 Features["sse2"] = true;
3111 Features["sse"] = true;
3121 Features["sse"] = false;
3123 Features["sse2"] = Features["pclmul"] = Features["aes"] =
3124 Features["sha"] = false;
3126 Features["sse3"] = false;
3127 setXOPLevel(Features, NoXOP, false);
3129 Features["ssse3"] = false;
3131 Features["sse4.1"] = false;
3133 Features["sse4.2"] = false;
3135 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
3136 Features["xsaveopt"] = false;
3137 setXOPLevel(Features, FMA4, false);
3139 Features["avx2"] = false;
3141 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
3142 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
3143 Features["avx512vl"] = Features["avx512vbmi"] =
3144 Features["avx512ifma"] = false;
3148 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
3149 MMX3DNowEnum Level, bool Enabled) {
3152 case AMD3DNowAthlon:
3153 Features["3dnowa"] = true;
3155 Features["3dnow"] = true;
3157 Features["mmx"] = true;
3167 Features["mmx"] = false;
3169 Features["3dnow"] = false;
3170 case AMD3DNowAthlon:
3171 Features["3dnowa"] = false;
3175 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
3180 Features["xop"] = true;
3182 Features["fma4"] = true;
3183 setSSELevel(Features, AVX, true);
3185 Features["sse4a"] = true;
3186 setSSELevel(Features, SSE3, true);
3196 Features["sse4a"] = false;
3198 Features["fma4"] = false;
3200 Features["xop"] = false;
3204 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
3205 StringRef Name, bool Enabled) {
3206 // This is a bit of a hack to deal with the sse4 target feature when used
3207 // as part of the target attribute. We handle sse4 correctly everywhere
3208 // else. See below for more information on how we handle the sse4 options.
3210 Features[Name] = Enabled;
3212 if (Name == "mmx") {
3213 setMMXLevel(Features, MMX, Enabled);
3214 } else if (Name == "sse") {
3215 setSSELevel(Features, SSE1, Enabled);
3216 } else if (Name == "sse2") {
3217 setSSELevel(Features, SSE2, Enabled);
3218 } else if (Name == "sse3") {
3219 setSSELevel(Features, SSE3, Enabled);
3220 } else if (Name == "ssse3") {
3221 setSSELevel(Features, SSSE3, Enabled);
3222 } else if (Name == "sse4.2") {
3223 setSSELevel(Features, SSE42, Enabled);
3224 } else if (Name == "sse4.1") {
3225 setSSELevel(Features, SSE41, Enabled);
3226 } else if (Name == "3dnow") {
3227 setMMXLevel(Features, AMD3DNow, Enabled);
3228 } else if (Name == "3dnowa") {
3229 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
3230 } else if (Name == "aes") {
3232 setSSELevel(Features, SSE2, Enabled);
3233 } else if (Name == "pclmul") {
3235 setSSELevel(Features, SSE2, Enabled);
3236 } else if (Name == "avx") {
3237 setSSELevel(Features, AVX, Enabled);
3238 } else if (Name == "avx2") {
3239 setSSELevel(Features, AVX2, Enabled);
3240 } else if (Name == "avx512f") {
3241 setSSELevel(Features, AVX512F, Enabled);
3242 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
3243 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
3244 Name == "avx512vbmi" || Name == "avx512ifma") {
3246 setSSELevel(Features, AVX512F, Enabled);
3247 } else if (Name == "fma") {
3249 setSSELevel(Features, AVX, Enabled);
3250 } else if (Name == "fma4") {
3251 setXOPLevel(Features, FMA4, Enabled);
3252 } else if (Name == "xop") {
3253 setXOPLevel(Features, XOP, Enabled);
3254 } else if (Name == "sse4a") {
3255 setXOPLevel(Features, SSE4A, Enabled);
3256 } else if (Name == "f16c") {
3258 setSSELevel(Features, AVX, Enabled);
3259 } else if (Name == "sha") {
3261 setSSELevel(Features, SSE2, Enabled);
3262 } else if (Name == "sse4") {
3263 // We can get here via the __target__ attribute since that's not controlled
3264 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
3265 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
3268 setSSELevel(Features, SSE42, Enabled);
3270 setSSELevel(Features, SSE41, Enabled);
3271 } else if (Name == "xsave") {
3273 Features["xsaveopt"] = false;
3274 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
3276 Features["xsave"] = true;
3280 /// handleTargetFeatures - Perform initialization based on the user
3281 /// configured set of features.
3282 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
3283 DiagnosticsEngine &Diags) {
3284 for (const auto &Feature : Features) {
3285 if (Feature[0] != '+')
3288 if (Feature == "+aes") {
3290 } else if (Feature == "+pclmul") {
3292 } else if (Feature == "+lzcnt") {
3294 } else if (Feature == "+rdrnd") {
3296 } else if (Feature == "+fsgsbase") {
3298 } else if (Feature == "+bmi") {
3300 } else if (Feature == "+bmi2") {
3302 } else if (Feature == "+popcnt") {
3304 } else if (Feature == "+rtm") {
3306 } else if (Feature == "+prfchw") {
3308 } else if (Feature == "+rdseed") {
3310 } else if (Feature == "+adx") {
3312 } else if (Feature == "+tbm") {
3314 } else if (Feature == "+fma") {
3316 } else if (Feature == "+f16c") {
3318 } else if (Feature == "+avx512cd") {
3320 } else if (Feature == "+avx512er") {
3322 } else if (Feature == "+avx512pf") {
3324 } else if (Feature == "+avx512dq") {
3326 } else if (Feature == "+avx512bw") {
3328 } else if (Feature == "+avx512vl") {
3330 } else if (Feature == "+avx512vbmi") {
3331 HasAVX512VBMI = true;
3332 } else if (Feature == "+avx512ifma") {
3333 HasAVX512IFMA = true;
3334 } else if (Feature == "+sha") {
3336 } else if (Feature == "+mpx") {
3338 } else if (Feature == "+movbe") {
3340 } else if (Feature == "+sgx") {
3342 } else if (Feature == "+cx16") {
3344 } else if (Feature == "+fxsr") {
3346 } else if (Feature == "+xsave") {
3348 } else if (Feature == "+xsaveopt") {
3350 } else if (Feature == "+xsavec") {
3352 } else if (Feature == "+xsaves") {
3354 } else if (Feature == "+mwaitx") {
3356 } else if (Feature == "+pku") {
3358 } else if (Feature == "+clflushopt") {
3359 HasCLFLUSHOPT = true;
3360 } else if (Feature == "+pcommit") {
3362 } else if (Feature == "+clwb") {
3364 } else if (Feature == "+umip") {
3366 } else if (Feature == "+prefetchwt1") {
3367 HasPREFETCHWT1 = true;
3370 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
3371 .Case("+avx512f", AVX512F)
3372 .Case("+avx2", AVX2)
3374 .Case("+sse4.2", SSE42)
3375 .Case("+sse4.1", SSE41)
3376 .Case("+ssse3", SSSE3)
3377 .Case("+sse3", SSE3)
3378 .Case("+sse2", SSE2)
3381 SSELevel = std::max(SSELevel, Level);
3383 MMX3DNowEnum ThreeDNowLevel =
3384 llvm::StringSwitch<MMX3DNowEnum>(Feature)
3385 .Case("+3dnowa", AMD3DNowAthlon)
3386 .Case("+3dnow", AMD3DNow)
3388 .Default(NoMMX3DNow);
3389 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
3391 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
3393 .Case("+fma4", FMA4)
3394 .Case("+sse4a", SSE4A)
3396 XOPLevel = std::max(XOPLevel, XLevel);
3399 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
3400 // matches the selected sse level.
3401 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
3402 (FPMath == FP_387 && SSELevel >= SSE1)) {
3403 Diags.Report(diag::err_target_unsupported_fpmath) <<
3404 (FPMath == FP_SSE ? "sse" : "387");
3409 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3413 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
3414 /// definitions for this particular subtarget.
3415 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
3416 MacroBuilder &Builder) const {
3417 // Target identification.
3418 if (getTriple().getArch() == llvm::Triple::x86_64) {
3419 Builder.defineMacro("__amd64__");
3420 Builder.defineMacro("__amd64");
3421 Builder.defineMacro("__x86_64");
3422 Builder.defineMacro("__x86_64__");
3423 if (getTriple().getArchName() == "x86_64h") {
3424 Builder.defineMacro("__x86_64h");
3425 Builder.defineMacro("__x86_64h__");
3428 DefineStd(Builder, "i386", Opts);
3431 // Subtarget options.
3432 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
3433 // truly should be based on -mtune options.
3438 // The rest are coming from the i386 define above.
3439 Builder.defineMacro("__tune_i386__");
3445 defineCPUMacros(Builder, "i486");
3448 Builder.defineMacro("__pentium_mmx__");
3449 Builder.defineMacro("__tune_pentium_mmx__");
3453 defineCPUMacros(Builder, "i586");
3454 defineCPUMacros(Builder, "pentium");
3459 Builder.defineMacro("__tune_pentium3__");
3463 Builder.defineMacro("__tune_pentium2__");
3466 Builder.defineMacro("__tune_i686__");
3467 Builder.defineMacro("__tune_pentiumpro__");
3470 Builder.defineMacro("__i686");
3471 Builder.defineMacro("__i686__");
3472 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3473 Builder.defineMacro("__pentiumpro");
3474 Builder.defineMacro("__pentiumpro__");
3478 defineCPUMacros(Builder, "pentium4");
3483 defineCPUMacros(Builder, "nocona");
3487 defineCPUMacros(Builder, "core2");
3490 defineCPUMacros(Builder, "atom");
3493 defineCPUMacros(Builder, "slm");
3497 case CK_SandyBridge:
3501 case CK_SkylakeClient:
3502 // FIXME: Historically, we defined this legacy name, it would be nice to
3503 // remove it at some point. We've never exposed fine-grained names for
3504 // recent primary x86 CPUs, and we should keep it that way.
3505 defineCPUMacros(Builder, "corei7");
3507 case CK_SkylakeServer:
3508 defineCPUMacros(Builder, "skx");
3513 defineCPUMacros(Builder, "knl");
3516 Builder.defineMacro("__tune_lakemont__");
3519 Builder.defineMacro("__k6_2__");
3520 Builder.defineMacro("__tune_k6_2__");
3523 if (CPU != CK_K6_2) { // In case of fallthrough
3524 // FIXME: GCC may be enabling these in cases where some other k6
3525 // architecture is specified but -m3dnow is explicitly provided. The
3526 // exact semantics need to be determined and emulated here.
3527 Builder.defineMacro("__k6_3__");
3528 Builder.defineMacro("__tune_k6_3__");
3532 defineCPUMacros(Builder, "k6");
3535 case CK_AthlonThunderbird:
3539 defineCPUMacros(Builder, "athlon");
3540 if (SSELevel != NoSSE) {
3541 Builder.defineMacro("__athlon_sse__");
3542 Builder.defineMacro("__tune_athlon_sse__");
3549 case CK_OpteronSSE3:
3551 case CK_Athlon64SSE3:
3553 defineCPUMacros(Builder, "k8");
3556 defineCPUMacros(Builder, "amdfam10");
3559 defineCPUMacros(Builder, "btver1");
3562 defineCPUMacros(Builder, "btver2");
3565 defineCPUMacros(Builder, "bdver1");
3568 defineCPUMacros(Builder, "bdver2");
3571 defineCPUMacros(Builder, "bdver3");
3574 defineCPUMacros(Builder, "bdver4");
3577 defineCPUMacros(Builder, "geode");
3581 // Target properties.
3582 Builder.defineMacro("__REGISTER_PREFIX__", "");
3584 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3585 // functions in glibc header files that use FP Stack inline asm which the
3586 // backend can't deal with (PR879).
3587 Builder.defineMacro("__NO_MATH_INLINES");
3590 Builder.defineMacro("__AES__");
3593 Builder.defineMacro("__PCLMUL__");
3596 Builder.defineMacro("__LZCNT__");
3599 Builder.defineMacro("__RDRND__");
3602 Builder.defineMacro("__FSGSBASE__");
3605 Builder.defineMacro("__BMI__");
3608 Builder.defineMacro("__BMI2__");
3611 Builder.defineMacro("__POPCNT__");
3614 Builder.defineMacro("__RTM__");
3617 Builder.defineMacro("__PRFCHW__");
3620 Builder.defineMacro("__RDSEED__");
3623 Builder.defineMacro("__ADX__");
3626 Builder.defineMacro("__TBM__");
3629 Builder.defineMacro("__MWAITX__");
3633 Builder.defineMacro("__XOP__");
3635 Builder.defineMacro("__FMA4__");
3637 Builder.defineMacro("__SSE4A__");
3643 Builder.defineMacro("__FMA__");
3646 Builder.defineMacro("__F16C__");
3649 Builder.defineMacro("__AVX512CD__");
3651 Builder.defineMacro("__AVX512ER__");
3653 Builder.defineMacro("__AVX512PF__");
3655 Builder.defineMacro("__AVX512DQ__");
3657 Builder.defineMacro("__AVX512BW__");
3659 Builder.defineMacro("__AVX512VL__");
3661 Builder.defineMacro("__AVX512VBMI__");
3663 Builder.defineMacro("__AVX512IFMA__");
3666 Builder.defineMacro("__SHA__");
3669 Builder.defineMacro("__FXSR__");
3671 Builder.defineMacro("__XSAVE__");
3673 Builder.defineMacro("__XSAVEOPT__");
3675 Builder.defineMacro("__XSAVEC__");
3677 Builder.defineMacro("__XSAVES__");
3679 Builder.defineMacro("__PKU__");
3681 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3683 // Each case falls through to the previous one here.
3686 Builder.defineMacro("__AVX512F__");
3688 Builder.defineMacro("__AVX2__");
3690 Builder.defineMacro("__AVX__");
3692 Builder.defineMacro("__SSE4_2__");
3694 Builder.defineMacro("__SSE4_1__");
3696 Builder.defineMacro("__SSSE3__");
3698 Builder.defineMacro("__SSE3__");
3700 Builder.defineMacro("__SSE2__");
3701 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
3703 Builder.defineMacro("__SSE__");
3704 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
3709 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3719 Builder.defineMacro("_M_IX86_FP", Twine(2));
3722 Builder.defineMacro("_M_IX86_FP", Twine(1));
3725 Builder.defineMacro("_M_IX86_FP", Twine(0));
3729 // Each case falls through to the previous one here.
3730 switch (MMX3DNowLevel) {
3731 case AMD3DNowAthlon:
3732 Builder.defineMacro("__3dNOW_A__");
3734 Builder.defineMacro("__3dNOW__");
3736 Builder.defineMacro("__MMX__");
3741 if (CPU >= CK_i486) {
3742 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3743 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3744 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3747 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3750 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3751 return llvm::StringSwitch<bool>(Feature)
3752 .Case("aes", HasAES)
3753 .Case("avx", SSELevel >= AVX)
3754 .Case("avx2", SSELevel >= AVX2)
3755 .Case("avx512f", SSELevel >= AVX512F)
3756 .Case("avx512cd", HasAVX512CD)
3757 .Case("avx512er", HasAVX512ER)
3758 .Case("avx512pf", HasAVX512PF)
3759 .Case("avx512dq", HasAVX512DQ)
3760 .Case("avx512bw", HasAVX512BW)
3761 .Case("avx512vl", HasAVX512VL)
3762 .Case("avx512vbmi", HasAVX512VBMI)
3763 .Case("avx512ifma", HasAVX512IFMA)
3764 .Case("bmi", HasBMI)
3765 .Case("bmi2", HasBMI2)
3766 .Case("clflushopt", HasCLFLUSHOPT)
3767 .Case("clwb", HasCLWB)
3768 .Case("cx16", HasCX16)
3769 .Case("f16c", HasF16C)
3770 .Case("fma", HasFMA)
3771 .Case("fma4", XOPLevel >= FMA4)
3772 .Case("fsgsbase", HasFSGSBASE)
3773 .Case("fxsr", HasFXSR)
3774 .Case("lzcnt", HasLZCNT)
3775 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3776 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3777 .Case("mmx", MMX3DNowLevel >= MMX)
3778 .Case("movbe", HasMOVBE)
3779 .Case("mpx", HasMPX)
3780 .Case("pclmul", HasPCLMUL)
3781 .Case("pcommit", HasPCOMMIT)
3782 .Case("pku", HasPKU)
3783 .Case("popcnt", HasPOPCNT)
3784 .Case("prefetchwt1", HasPREFETCHWT1)
3785 .Case("prfchw", HasPRFCHW)
3786 .Case("rdrnd", HasRDRND)
3787 .Case("rdseed", HasRDSEED)
3788 .Case("rtm", HasRTM)
3789 .Case("sgx", HasSGX)
3790 .Case("sha", HasSHA)
3791 .Case("sse", SSELevel >= SSE1)
3792 .Case("sse2", SSELevel >= SSE2)
3793 .Case("sse3", SSELevel >= SSE3)
3794 .Case("ssse3", SSELevel >= SSSE3)
3795 .Case("sse4.1", SSELevel >= SSE41)
3796 .Case("sse4.2", SSELevel >= SSE42)
3797 .Case("sse4a", XOPLevel >= SSE4A)
3798 .Case("tbm", HasTBM)
3799 .Case("umip", HasUMIP)
3801 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3802 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3803 .Case("xop", XOPLevel >= XOP)
3804 .Case("xsave", HasXSAVE)
3805 .Case("xsavec", HasXSAVEC)
3806 .Case("xsaves", HasXSAVES)
3807 .Case("xsaveopt", HasXSAVEOPT)
3811 // We can't use a generic validation scheme for the features accepted here
3812 // versus subtarget features accepted in the target attribute because the
3813 // bitfield structure that's initialized in the runtime only supports the
3814 // below currently rather than the full range of subtarget features. (See
3815 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
3816 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
3817 return llvm::StringSwitch<bool>(FeatureStr)
3820 .Case("popcnt", true)
3824 .Case("ssse3", true)
3825 .Case("sse4.1", true)
3826 .Case("sse4.2", true)
3829 .Case("sse4a", true)
3833 .Case("avx512f", true)
3837 .Case("pclmul", true)
3838 .Case("avx512vl", true)
3839 .Case("avx512bw", true)
3840 .Case("avx512dq", true)
3841 .Case("avx512cd", true)
3842 .Case("avx512er", true)
3843 .Case("avx512pf", true)
3844 .Case("avx512vbmi", true)
3845 .Case("avx512ifma", true)
3850 X86TargetInfo::validateAsmConstraint(const char *&Name,
3851 TargetInfo::ConstraintInfo &Info) const {
3853 default: return false;
3854 // Constant constraints.
3855 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
3857 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3858 // x86_64 instructions.
3860 Info.setRequiresImmediate();
3863 Info.setRequiresImmediate(0, 31);
3866 Info.setRequiresImmediate(0, 63);
3869 Info.setRequiresImmediate(-128, 127);
3872 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) });
3875 Info.setRequiresImmediate(0, 3);
3878 Info.setRequiresImmediate(0, 255);
3881 Info.setRequiresImmediate(0, 127);
3883 // Register constraints.
3884 case 'Y': // 'Y' is the first character for several 2-character constraints.
3885 // Shift the pointer to the second character of the constraint.
3890 case '0': // First SSE register.
3891 case 't': // Any SSE register, when SSE2 is enabled.
3892 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
3893 case 'm': // Any MMX register, when inter-unit moves enabled.
3894 Info.setAllowsRegister();
3897 case 'f': // Any x87 floating point stack register.
3898 // Constraint 'f' cannot be used for output operands.
3899 if (Info.ConstraintStr[0] == '=')
3901 Info.setAllowsRegister();
3909 case 'A': // edx:eax.
3910 case 't': // Top of floating point stack.
3911 case 'u': // Second from top of floating point stack.
3912 case 'q': // Any register accessible as [r]l: a, b, c, and d.
3913 case 'y': // Any MMX register.
3914 case 'x': // Any SSE register.
3915 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3916 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3917 case 'l': // "Index" registers: any general register that can be used as an
3918 // index in a base+index memory access.
3919 Info.setAllowsRegister();
3921 // Floating point constant constraints.
3922 case 'C': // SSE floating point constant.
3923 case 'G': // x87 floating point constant.
3928 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3929 unsigned Size) const {
3930 // Strip off constraint modifiers.
3931 while (Constraint[0] == '=' ||
3932 Constraint[0] == '+' ||
3933 Constraint[0] == '&')
3934 Constraint = Constraint.substr(1);
3936 return validateOperandSize(Constraint, Size);
3939 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3940 unsigned Size) const {
3941 return validateOperandSize(Constraint, Size);
3944 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3945 unsigned Size) const {
3946 switch (Constraint[0]) {
3955 if (SSELevel >= AVX512F)
3956 // 512-bit zmm registers can be used if target supports AVX512F.
3957 return Size <= 512U;
3958 else if (SSELevel >= AVX)
3959 // 256-bit ymm registers can be used if target supports AVX.
3960 return Size <= 256U;
3961 return Size <= 128U;
3963 // 'Y' is the first character for several 2-character constraints.
3964 switch (Constraint[1]) {
3967 // 'Ym' is synonymous with 'y'.
3971 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
3972 if (SSELevel >= AVX512F)
3973 return Size <= 512U;
3974 else if (SSELevel >= AVX)
3975 return Size <= 256U;
3976 return SSELevel >= SSE2 && Size <= 128U;
3985 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3986 switch (*Constraint) {
3987 case 'a': return std::string("{ax}");
3988 case 'b': return std::string("{bx}");
3989 case 'c': return std::string("{cx}");
3990 case 'd': return std::string("{dx}");
3991 case 'S': return std::string("{si}");
3992 case 'D': return std::string("{di}");
3993 case 'p': // address
3994 return std::string("im");
3995 case 't': // top of floating point stack.
3996 return std::string("{st}");
3997 case 'u': // second from top of floating point stack.
3998 return std::string("{st(1)}"); // second from top of floating point stack.
4000 return std::string(1, *Constraint);
4004 // X86-32 generic target
4005 class X86_32TargetInfo : public X86TargetInfo {
4007 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4008 : X86TargetInfo(Triple, Opts) {
4009 DoubleAlign = LongLongAlign = 32;
4010 LongDoubleWidth = 96;
4011 LongDoubleAlign = 32;
4012 SuitableAlign = 128;
4013 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128");
4014 SizeType = UnsignedInt;
4015 PtrDiffType = SignedInt;
4016 IntPtrType = SignedInt;
4019 // Use fpret for all types.
4020 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
4021 (1 << TargetInfo::Double) |
4022 (1 << TargetInfo::LongDouble));
4024 // x86-32 has atomics up to 8 bytes
4025 // FIXME: Check that we actually have cmpxchg8b before setting
4026 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
4027 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4029 BuiltinVaListKind getBuiltinVaListKind() const override {
4030 return TargetInfo::CharPtrBuiltinVaList;
4033 int getEHDataRegisterNumber(unsigned RegNo) const override {
4034 if (RegNo == 0) return 0;
4035 if (RegNo == 1) return 2;
4038 bool validateOperandSize(StringRef Constraint,
4039 unsigned Size) const override {
4040 switch (Constraint[0]) {
4056 return X86TargetInfo::validateOperandSize(Constraint, Size);
4060 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
4062 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4063 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {}
4065 unsigned getFloatEvalMethod() const override {
4066 unsigned Major, Minor, Micro;
4067 getTriple().getOSVersion(Major, Minor, Micro);
4068 // New NetBSD uses the default rounding mode.
4069 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
4070 return X86_32TargetInfo::getFloatEvalMethod();
4071 // NetBSD before 6.99.26 defaults to "double" rounding.
4076 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
4078 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4079 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4080 SizeType = UnsignedLong;
4081 IntPtrType = SignedLong;
4082 PtrDiffType = SignedLong;
4086 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
4088 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4089 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4090 SizeType = UnsignedLong;
4091 IntPtrType = SignedLong;
4092 PtrDiffType = SignedLong;
4096 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
4098 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4099 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4100 LongDoubleWidth = 128;
4101 LongDoubleAlign = 128;
4102 SuitableAlign = 128;
4103 MaxVectorAlign = 256;
4104 // The watchOS simulator uses the builtin bool type for Objective-C.
4105 llvm::Triple T = llvm::Triple(Triple);
4107 UseSignedCharForObjCBool = false;
4108 SizeType = UnsignedLong;
4109 IntPtrType = SignedLong;
4110 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128");
4111 HasAlignMac68kSupport = true;
4114 bool handleTargetFeatures(std::vector<std::string> &Features,
4115 DiagnosticsEngine &Diags) override {
4116 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features,
4119 // We now know the features we have: we can decide how to align vectors.
4121 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4126 // x86-32 Windows target
4127 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
4129 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4130 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4131 WCharType = UnsignedShort;
4132 DoubleAlign = LongLongAlign = 64;
4134 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4135 resetDataLayout(IsWinCOFF
4136 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
4137 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4139 void getTargetDefines(const LangOptions &Opts,
4140 MacroBuilder &Builder) const override {
4141 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4145 // x86-32 Windows Visual Studio target
4146 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
4148 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple,
4149 const TargetOptions &Opts)
4150 : WindowsX86_32TargetInfo(Triple, Opts) {
4151 LongDoubleWidth = LongDoubleAlign = 64;
4152 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4154 void getTargetDefines(const LangOptions &Opts,
4155 MacroBuilder &Builder) const override {
4156 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4157 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
4158 // The value of the following reflects processor type.
4159 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
4160 // We lost the original triple, so we use the default.
4161 Builder.defineMacro("_M_IX86", "600");
4165 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4166 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang
4167 // supports __declspec natively under -fms-extensions, but we define a no-op
4168 // __declspec macro anyway for pre-processor compatibility.
4169 if (Opts.MicrosoftExt)
4170 Builder.defineMacro("__declspec", "__declspec");
4172 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
4174 if (!Opts.MicrosoftExt) {
4175 // Provide macros for all the calling convention keywords. Provide both
4176 // single and double underscore prefixed variants. These are available on
4177 // x64 as well as x86, even though they have no effect.
4178 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
4179 for (const char *CC : CCs) {
4180 std::string GCCSpelling = "__attribute__((__";
4182 GCCSpelling += "__))";
4183 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
4184 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
4189 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4190 Builder.defineMacro("__MSVCRT__");
4191 Builder.defineMacro("__MINGW32__");
4192 addCygMingDefines(Opts, Builder);
4195 // x86-32 MinGW target
4196 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
4198 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4199 : WindowsX86_32TargetInfo(Triple, Opts) {}
4200 void getTargetDefines(const LangOptions &Opts,
4201 MacroBuilder &Builder) const override {
4202 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4203 DefineStd(Builder, "WIN32", Opts);
4204 DefineStd(Builder, "WINNT", Opts);
4205 Builder.defineMacro("_X86_");
4206 addMinGWDefines(Opts, Builder);
4210 // x86-32 Cygwin target
4211 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
4213 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4214 : X86_32TargetInfo(Triple, Opts) {
4215 WCharType = UnsignedShort;
4216 DoubleAlign = LongLongAlign = 64;
4217 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4219 void getTargetDefines(const LangOptions &Opts,
4220 MacroBuilder &Builder) const override {
4221 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4222 Builder.defineMacro("_X86_");
4223 Builder.defineMacro("__CYGWIN__");
4224 Builder.defineMacro("__CYGWIN32__");
4225 addCygMingDefines(Opts, Builder);
4226 DefineStd(Builder, "unix", Opts);
4228 Builder.defineMacro("_GNU_SOURCE");
4232 // x86-32 Haiku target
4233 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> {
4235 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4236 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4238 void getTargetDefines(const LangOptions &Opts,
4239 MacroBuilder &Builder) const override {
4240 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4241 Builder.defineMacro("__INTEL__");
4245 // X86-32 MCU target
4246 class MCUX86_32TargetInfo : public X86_32TargetInfo {
4248 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4249 : X86_32TargetInfo(Triple, Opts) {
4250 LongDoubleWidth = 64;
4251 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4252 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32");
4253 WIntType = UnsignedInt;
4256 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4257 // On MCU we support only C calling convention.
4258 return CC == CC_C ? CCCR_OK : CCCR_Warning;
4261 void getTargetDefines(const LangOptions &Opts,
4262 MacroBuilder &Builder) const override {
4263 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4264 Builder.defineMacro("__iamcu");
4265 Builder.defineMacro("__iamcu__");
4268 bool allowsLargerPreferedTypeAlignment() const override {
4274 template<typename Target>
4275 class RTEMSTargetInfo : public OSTargetInfo<Target> {
4277 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4278 MacroBuilder &Builder) const override {
4279 // RTEMS defines; list based off of gcc output
4281 Builder.defineMacro("__rtems__");
4282 Builder.defineMacro("__ELF__");
4286 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4287 : OSTargetInfo<Target>(Triple, Opts) {
4288 switch (Triple.getArch()) {
4290 case llvm::Triple::x86:
4291 // this->MCountName = ".mcount";
4293 case llvm::Triple::mips:
4294 case llvm::Triple::mipsel:
4295 case llvm::Triple::ppc:
4296 case llvm::Triple::ppc64:
4297 case llvm::Triple::ppc64le:
4298 // this->MCountName = "_mcount";
4300 case llvm::Triple::arm:
4301 // this->MCountName = "__mcount";
4307 // x86-32 RTEMS target
4308 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
4310 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4311 : X86_32TargetInfo(Triple, Opts) {
4312 SizeType = UnsignedLong;
4313 IntPtrType = SignedLong;
4314 PtrDiffType = SignedLong;
4316 void getTargetDefines(const LangOptions &Opts,
4317 MacroBuilder &Builder) const override {
4318 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4319 Builder.defineMacro("__INTEL__");
4320 Builder.defineMacro("__rtems__");
4324 // x86-64 generic target
4325 class X86_64TargetInfo : public X86TargetInfo {
4327 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4328 : X86TargetInfo(Triple, Opts) {
4329 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
4331 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4332 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
4333 LongDoubleWidth = 128;
4334 LongDoubleAlign = 128;
4335 LargeArrayMinWidth = 128;
4336 LargeArrayAlign = 128;
4337 SuitableAlign = 128;
4338 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
4339 PtrDiffType = IsX32 ? SignedInt : SignedLong;
4340 IntPtrType = IsX32 ? SignedInt : SignedLong;
4341 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
4342 Int64Type = IsX32 ? SignedLongLong : SignedLong;
4345 // Pointers are 32-bit in x32.
4346 resetDataLayout(IsX32
4347 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
4348 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
4349 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128");
4351 // Use fpret only for long double.
4352 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
4354 // Use fp2ret for _Complex long double.
4355 ComplexLongDoubleUsesFP2Ret = true;
4357 // Make __builtin_ms_va_list available.
4358 HasBuiltinMSVaList = true;
4360 // x86-64 has atomics up to 16 bytes.
4361 MaxAtomicPromoteWidth = 128;
4362 MaxAtomicInlineWidth = 128;
4364 BuiltinVaListKind getBuiltinVaListKind() const override {
4365 return TargetInfo::X86_64ABIBuiltinVaList;
4368 int getEHDataRegisterNumber(unsigned RegNo) const override {
4369 if (RegNo == 0) return 0;
4370 if (RegNo == 1) return 1;
4374 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4378 case CC_X86VectorCall:
4379 case CC_IntelOclBicc:
4380 case CC_X86_64Win64:
4381 case CC_PreserveMost:
4382 case CC_PreserveAll:
4385 return CCCR_Warning;
4389 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
4393 // for x32 we need it here explicitly
4394 bool hasInt128Type() const override { return true; }
4395 unsigned getUnwindWordWidth() const override { return 64; }
4396 unsigned getRegisterWidth() const override { return 64; }
4398 bool validateGlobalRegisterVariable(StringRef RegName,
4400 bool &HasSizeMismatch) const override {
4401 // rsp and rbp are the only 64-bit registers the x86 backend can currently
4403 if (RegName.equals("rsp") || RegName.equals("rbp")) {
4404 // Check that the register size is 64-bit.
4405 HasSizeMismatch = RegSize != 64;
4409 // Check if the register is a 32-bit register the backend can handle.
4410 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize,
4415 // x86-64 Windows target
4416 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
4418 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4419 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4420 WCharType = UnsignedShort;
4421 LongWidth = LongAlign = 32;
4422 DoubleAlign = LongLongAlign = 64;
4423 IntMaxType = SignedLongLong;
4424 Int64Type = SignedLongLong;
4425 SizeType = UnsignedLongLong;
4426 PtrDiffType = SignedLongLong;
4427 IntPtrType = SignedLongLong;
4430 void getTargetDefines(const LangOptions &Opts,
4431 MacroBuilder &Builder) const override {
4432 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
4433 Builder.defineMacro("_WIN64");
4436 BuiltinVaListKind getBuiltinVaListKind() const override {
4437 return TargetInfo::CharPtrBuiltinVaList;
4440 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4443 case CC_X86ThisCall:
4444 case CC_X86FastCall:
4447 case CC_X86VectorCall:
4448 case CC_IntelOclBicc:
4452 return CCCR_Warning;
4457 // x86-64 Windows Visual Studio target
4458 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
4460 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple,
4461 const TargetOptions &Opts)
4462 : WindowsX86_64TargetInfo(Triple, Opts) {
4463 LongDoubleWidth = LongDoubleAlign = 64;
4464 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4466 void getTargetDefines(const LangOptions &Opts,
4467 MacroBuilder &Builder) const override {
4468 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4469 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
4470 Builder.defineMacro("_M_X64", "100");
4471 Builder.defineMacro("_M_AMD64", "100");
4475 // x86-64 MinGW target
4476 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
4478 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4479 : WindowsX86_64TargetInfo(Triple, Opts) {
4480 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
4481 // with x86 FP ops. Weird.
4482 LongDoubleWidth = LongDoubleAlign = 128;
4483 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
4486 void getTargetDefines(const LangOptions &Opts,
4487 MacroBuilder &Builder) const override {
4488 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4489 DefineStd(Builder, "WIN64", Opts);
4490 Builder.defineMacro("__MINGW64__");
4491 addMinGWDefines(Opts, Builder);
4493 // GCC defines this macro when it is using __gxx_personality_seh0.
4494 if (!Opts.SjLjExceptions)
4495 Builder.defineMacro("__SEH__");
4499 // x86-64 Cygwin target
4500 class CygwinX86_64TargetInfo : public X86_64TargetInfo {
4502 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4503 : X86_64TargetInfo(Triple, Opts) {
4504 TLSSupported = false;
4505 WCharType = UnsignedShort;
4507 void getTargetDefines(const LangOptions &Opts,
4508 MacroBuilder &Builder) const override {
4509 X86_64TargetInfo::getTargetDefines(Opts, Builder);
4510 Builder.defineMacro("__x86_64__");
4511 Builder.defineMacro("__CYGWIN__");
4512 Builder.defineMacro("__CYGWIN64__");
4513 addCygMingDefines(Opts, Builder);
4514 DefineStd(Builder, "unix", Opts);
4516 Builder.defineMacro("_GNU_SOURCE");
4518 // GCC defines this macro when it is using __gxx_personality_seh0.
4519 if (!Opts.SjLjExceptions)
4520 Builder.defineMacro("__SEH__");
4524 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
4526 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4527 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4528 Int64Type = SignedLongLong;
4529 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
4530 llvm::Triple T = llvm::Triple(Triple);
4532 UseSignedCharForObjCBool = false;
4533 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128");
4536 bool handleTargetFeatures(std::vector<std::string> &Features,
4537 DiagnosticsEngine &Diags) override {
4538 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features,
4541 // We now know the features we have: we can decide how to align vectors.
4543 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4548 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
4550 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4551 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4552 IntMaxType = SignedLongLong;
4553 Int64Type = SignedLongLong;
4557 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
4559 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4560 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4561 IntMaxType = SignedLongLong;
4562 Int64Type = SignedLongLong;
4566 class ARMTargetInfo : public TargetInfo {
4567 // Possible FPU choices.
4576 // Possible HWDiv features.
4578 HWDivThumb = (1 << 0),
4582 static bool FPUModeIsVFP(FPUMode Mode) {
4583 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
4586 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4587 static const char * const GCCRegNames[];
4589 std::string ABI, CPU;
4591 StringRef CPUProfile;
4601 unsigned ArchKind = llvm::ARM::AK_ARMV4T;
4602 unsigned ArchProfile;
4603 unsigned ArchVersion;
4607 unsigned IsAAPCS : 1;
4610 // Initialized via features.
4611 unsigned SoftFloat : 1;
4612 unsigned SoftFloatABI : 1;
4615 unsigned Crypto : 1;
4617 unsigned Unaligned : 1;
4620 LDREX_B = (1 << 0), /// byte (8-bit)
4621 LDREX_H = (1 << 1), /// half (16-bit)
4622 LDREX_W = (1 << 2), /// word (32-bit)
4623 LDREX_D = (1 << 3), /// double (64-bit)
4628 // ACLE 6.5.1 Hardware floating point
4630 HW_FP_HP = (1 << 1), /// half (16-bit)
4631 HW_FP_SP = (1 << 2), /// single (32-bit)
4632 HW_FP_DP = (1 << 3), /// double (64-bit)
4636 static const Builtin::Info BuiltinInfo[];
4638 void setABIAAPCS() {
4641 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4642 const llvm::Triple &T = getTriple();
4644 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig.
4645 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
4646 T.getOS() == llvm::Triple::Bitrig)
4647 SizeType = UnsignedLong;
4649 SizeType = UnsignedInt;
4651 switch (T.getOS()) {
4652 case llvm::Triple::NetBSD:
4653 WCharType = SignedInt;
4655 case llvm::Triple::Win32:
4656 WCharType = UnsignedShort;
4658 case llvm::Triple::Linux:
4660 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
4661 WCharType = UnsignedInt;
4665 UseBitFieldTypeAlignment = true;
4667 ZeroLengthBitfieldBoundary = 0;
4669 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
4670 // so set preferred for small types to 32.
4671 if (T.isOSBinFormatMachO()) {
4672 resetDataLayout(BigEndian
4673 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4674 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
4675 } else if (T.isOSWindows()) {
4676 assert(!BigEndian && "Windows on ARM does not support big endian");
4685 } else if (T.isOSNaCl()) {
4686 assert(!BigEndian && "NaCl on ARM does not support big endian");
4687 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128");
4689 resetDataLayout(BigEndian
4690 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4691 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
4694 // FIXME: Enumerated types are variable width in straight AAPCS.
4697 void setABIAPCS(bool IsAAPCS16) {
4698 const llvm::Triple &T = getTriple();
4703 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4705 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
4707 // size_t is unsigned int on FreeBSD.
4708 if (T.getOS() == llvm::Triple::FreeBSD)
4709 SizeType = UnsignedInt;
4711 SizeType = UnsignedLong;
4713 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
4714 WCharType = SignedInt;
4716 // Do not respect the alignment of bit-field types when laying out
4717 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
4718 UseBitFieldTypeAlignment = false;
4720 /// gcc forces the alignment to 4 bytes, regardless of the type of the
4721 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
4723 ZeroLengthBitfieldBoundary = 32;
4725 if (T.isOSBinFormatMachO() && IsAAPCS16) {
4726 assert(!BigEndian && "AAPCS16 does not support big-endian");
4727 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128");
4728 } else if (T.isOSBinFormatMachO())
4731 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4732 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
4736 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4737 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
4739 // FIXME: Override "preferred align" for double and long long.
4742 void setArchInfo() {
4743 StringRef ArchName = getTriple().getArchName();
4745 ArchISA = llvm::ARM::parseArchISA(ArchName);
4746 CPU = llvm::ARM::getDefaultCPU(ArchName);
4747 unsigned AK = llvm::ARM::parseArch(ArchName);
4748 if (AK != llvm::ARM::AK_INVALID)
4750 setArchInfo(ArchKind);
4753 void setArchInfo(unsigned Kind) {
4756 // cache TargetParser info
4758 SubArch = llvm::ARM::getSubArch(ArchKind);
4759 ArchProfile = llvm::ARM::parseArchProfile(SubArch);
4760 ArchVersion = llvm::ARM::parseArchVersion(SubArch);
4762 // cache CPU related strings
4763 CPUAttr = getCPUAttr();
4764 CPUProfile = getCPUProfile();
4768 // when triple does not specify a sub arch,
4769 // then we are not using inline atomics
4770 bool ShouldUseInlineAtomic =
4771 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) ||
4772 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
4773 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4774 if (ArchProfile == llvm::ARM::PK_M) {
4775 MaxAtomicPromoteWidth = 32;
4776 if (ShouldUseInlineAtomic)
4777 MaxAtomicInlineWidth = 32;
4780 MaxAtomicPromoteWidth = 64;
4781 if (ShouldUseInlineAtomic)
4782 MaxAtomicInlineWidth = 64;
4786 bool isThumb() const {
4787 return (ArchISA == llvm::ARM::IK_THUMB);
4790 bool supportsThumb() const {
4791 return CPUAttr.count('T') || ArchVersion >= 6;
4794 bool supportsThumb2() const {
4795 return CPUAttr.equals("6T2") ||
4796 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE"));
4799 StringRef getCPUAttr() const {
4800 // For most sub-arches, the build attribute CPU name is enough.
4801 // For Cortex variants, it's slightly different.
4804 return llvm::ARM::getCPUAttr(ArchKind);
4805 case llvm::ARM::AK_ARMV6M:
4807 case llvm::ARM::AK_ARMV7S:
4809 case llvm::ARM::AK_ARMV7A:
4811 case llvm::ARM::AK_ARMV7R:
4813 case llvm::ARM::AK_ARMV7M:
4815 case llvm::ARM::AK_ARMV7EM:
4817 case llvm::ARM::AK_ARMV8A:
4819 case llvm::ARM::AK_ARMV8_1A:
4821 case llvm::ARM::AK_ARMV8_2A:
4823 case llvm::ARM::AK_ARMV8MBaseline:
4825 case llvm::ARM::AK_ARMV8MMainline:
4830 StringRef getCPUProfile() const {
4831 switch(ArchProfile) {
4832 case llvm::ARM::PK_A:
4834 case llvm::ARM::PK_R:
4836 case llvm::ARM::PK_M:
4844 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts,
4846 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0),
4848 BigEndian = IsBigEndian;
4850 switch (getTriple().getOS()) {
4851 case llvm::Triple::NetBSD:
4852 PtrDiffType = SignedLong;
4855 PtrDiffType = SignedInt;
4859 // Cache arch related info.
4862 // {} in inline assembly are neon specifiers, not assembly variant
4864 NoAsmVariants = true;
4866 // FIXME: This duplicates code from the driver that sets the -target-abi
4867 // option - this code is used if -target-abi isn't passed and should
4868 // be unified in some way.
4869 if (Triple.isOSBinFormatMachO()) {
4870 // The backend is hardwired to assume AAPCS for M-class processors, ensure
4871 // the frontend matches that.
4872 if (Triple.getEnvironment() == llvm::Triple::EABI ||
4873 Triple.getOS() == llvm::Triple::UnknownOS ||
4874 StringRef(CPU).startswith("cortex-m")) {
4876 } else if (Triple.isWatchABI()) {
4881 } else if (Triple.isOSWindows()) {
4882 // FIXME: this is invalid for WindowsCE
4885 // Select the default based on the platform.
4886 switch (Triple.getEnvironment()) {
4887 case llvm::Triple::Android:
4888 case llvm::Triple::GNUEABI:
4889 case llvm::Triple::GNUEABIHF:
4890 case llvm::Triple::MuslEABI:
4891 case llvm::Triple::MuslEABIHF:
4892 setABI("aapcs-linux");
4894 case llvm::Triple::EABIHF:
4895 case llvm::Triple::EABI:
4898 case llvm::Triple::GNU:
4902 if (Triple.getOS() == llvm::Triple::NetBSD)
4910 // ARM targets default to using the ARM C++ ABI.
4911 TheCXXABI.set(TargetCXXABI::GenericARM);
4913 // ARM has atomics up to 8 bytes
4916 // Do force alignment of members that follow zero length bitfields. If
4917 // the alignment of the zero-length bitfield is greater than the member
4918 // that follows it, `bar', `bar' will be aligned as the type of the
4919 // zero length bitfield.
4920 UseZeroLengthBitfieldAlignment = true;
4922 if (Triple.getOS() == llvm::Triple::Linux ||
4923 Triple.getOS() == llvm::Triple::UnknownOS)
4925 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount";
4928 StringRef getABI() const override { return ABI; }
4930 bool setABI(const std::string &Name) override {
4933 // The defaults (above) are for AAPCS, check if we need to change them.
4935 // FIXME: We need support for -meabi... we could just mangle it into the
4937 if (Name == "apcs-gnu" || Name == "aapcs16") {
4938 setABIAPCS(Name == "aapcs16");
4941 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
4948 // FIXME: This should be based on Arch attributes, not CPU names.
4950 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
4952 const std::vector<std::string> &FeaturesVec) const override {
4954 std::vector<const char*> TargetFeatures;
4955 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName());
4957 // get default FPU features
4958 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
4959 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
4961 // get default Extension features
4962 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
4963 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
4965 for (const char *Feature : TargetFeatures)
4966 if (Feature[0] == '+')
4967 Features[Feature+1] = true;
4969 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
4972 bool handleTargetFeatures(std::vector<std::string> &Features,
4973 DiagnosticsEngine &Diags) override {
4979 SoftFloat = SoftFloatABI = false;
4982 // This does not diagnose illegal cases like having both
4983 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
4984 uint32_t HW_FP_remove = 0;
4985 for (const auto &Feature : Features) {
4986 if (Feature == "+soft-float") {
4988 } else if (Feature == "+soft-float-abi") {
4989 SoftFloatABI = true;
4990 } else if (Feature == "+vfp2") {
4992 HW_FP |= HW_FP_SP | HW_FP_DP;
4993 } else if (Feature == "+vfp3") {
4995 HW_FP |= HW_FP_SP | HW_FP_DP;
4996 } else if (Feature == "+vfp4") {
4998 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
4999 } else if (Feature == "+fp-armv8") {
5001 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
5002 } else if (Feature == "+neon") {
5004 HW_FP |= HW_FP_SP | HW_FP_DP;
5005 } else if (Feature == "+hwdiv") {
5006 HWDiv |= HWDivThumb;
5007 } else if (Feature == "+hwdiv-arm") {
5009 } else if (Feature == "+crc") {
5011 } else if (Feature == "+crypto") {
5013 } else if (Feature == "+dsp") {
5015 } else if (Feature == "+fp-only-sp") {
5016 HW_FP_remove |= HW_FP_DP;
5017 } else if (Feature == "+strict-align") {
5019 } else if (Feature == "+fp16") {
5023 HW_FP &= ~HW_FP_remove;
5025 switch (ArchVersion) {
5027 if (ArchProfile == llvm::ARM::PK_M)
5029 else if (ArchKind == llvm::ARM::AK_ARMV6K)
5030 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5035 if (ArchProfile == llvm::ARM::PK_M)
5036 LDREX = LDREX_W | LDREX_H | LDREX_B ;
5038 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5041 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5044 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
5045 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
5049 if (FPMath == FP_Neon)
5050 Features.push_back("+neonfp");
5051 else if (FPMath == FP_VFP)
5052 Features.push_back("-neonfp");
5054 // Remove front-end specific options which the backend handles differently.
5056 std::find(Features.begin(), Features.end(), "+soft-float-abi");
5057 if (Feature != Features.end())
5058 Features.erase(Feature);
5063 bool hasFeature(StringRef Feature) const override {
5064 return llvm::StringSwitch<bool>(Feature)
5066 .Case("aarch32", true)
5067 .Case("softfloat", SoftFloat)
5068 .Case("thumb", isThumb())
5069 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
5070 .Case("hwdiv", HWDiv & HWDivThumb)
5071 .Case("hwdiv-arm", HWDiv & HWDivARM)
5075 bool setCPU(const std::string &Name) override {
5076 if (Name != "generic")
5077 setArchInfo(llvm::ARM::parseCPUArch(Name));
5079 if (ArchKind == llvm::ARM::AK_INVALID)
5086 bool setFPMath(StringRef Name) override;
5088 void getTargetDefines(const LangOptions &Opts,
5089 MacroBuilder &Builder) const override {
5090 // Target identification.
5091 Builder.defineMacro("__arm");
5092 Builder.defineMacro("__arm__");
5093 // For bare-metal none-eabi.
5094 if (getTriple().getOS() == llvm::Triple::UnknownOS &&
5095 getTriple().getEnvironment() == llvm::Triple::EABI)
5096 Builder.defineMacro("__ELF__");
5098 // Target properties.
5099 Builder.defineMacro("__REGISTER_PREFIX__", "");
5101 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
5102 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
5103 if (getTriple().isWatchABI())
5104 Builder.defineMacro("__ARM_ARCH_7K__", "2");
5106 if (!CPUAttr.empty())
5107 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
5109 // ACLE 6.4.1 ARM/Thumb instruction set architecture
5110 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
5111 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
5113 if (ArchVersion >= 8) {
5114 // ACLE 6.5.7 Crypto Extension
5116 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
5117 // ACLE 6.5.8 CRC32 Extension
5119 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
5120 // ACLE 6.5.10 Numeric Maximum and Minimum
5121 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
5122 // ACLE 6.5.9 Directed Rounding
5123 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
5126 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
5127 // is not defined for the M-profile.
5128 // NOTE that the default profile is assumed to be 'A'
5129 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M)
5130 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
5132 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original
5133 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the
5134 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all
5135 // v7 and v8 architectures excluding v8-M Baseline.
5136 if (supportsThumb2())
5137 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
5138 else if (supportsThumb())
5139 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
5141 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
5142 // instruction set such as ARM or Thumb.
5143 Builder.defineMacro("__ARM_32BIT_STATE", "1");
5145 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
5147 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
5148 if (!CPUProfile.empty())
5149 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
5151 // ACLE 6.4.3 Unaligned access supported in hardware
5153 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
5155 // ACLE 6.4.4 LDREX/STREX
5157 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX));
5160 if (ArchVersion == 5 ||
5161 (ArchVersion == 6 && CPUProfile != "M") ||
5163 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
5165 // ACLE 6.5.1 Hardware Floating Point
5167 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
5170 Builder.defineMacro("__ARM_ACLE", "200");
5172 // FP16 support (we currently only support IEEE format).
5173 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
5174 Builder.defineMacro("__ARM_FP16_ARGS", "1");
5176 // ACLE 6.5.3 Fused multiply-accumulate (FMA)
5177 if (ArchVersion >= 7 && (FPU & VFP4FPU))
5178 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
5180 // Subtarget options.
5182 // FIXME: It's more complicated than this and we don't really support
5184 // Windows on ARM does not "support" interworking
5185 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows())
5186 Builder.defineMacro("__THUMB_INTERWORK__");
5188 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
5189 // Embedded targets on Darwin follow AAPCS, but not EABI.
5190 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
5191 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows())
5192 Builder.defineMacro("__ARM_EABI__");
5193 Builder.defineMacro("__ARM_PCS", "1");
5196 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" ||
5198 Builder.defineMacro("__ARM_PCS_VFP", "1");
5201 Builder.defineMacro("__SOFTFP__");
5203 if (CPU == "xscale")
5204 Builder.defineMacro("__XSCALE__");
5207 Builder.defineMacro("__THUMBEL__");
5208 Builder.defineMacro("__thumb__");
5209 if (supportsThumb2())
5210 Builder.defineMacro("__thumb2__");
5213 // ACLE 6.4.9 32-bit SIMD instructions
5214 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
5215 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
5217 // ACLE 6.4.10 Hardware Integer Divide
5218 if (((HWDiv & HWDivThumb) && isThumb()) ||
5219 ((HWDiv & HWDivARM) && !isThumb())) {
5220 Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
5221 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
5224 // Note, this is always on in gcc, even though it doesn't make sense.
5225 Builder.defineMacro("__APCS_32__");
5227 if (FPUModeIsVFP((FPUMode) FPU)) {
5228 Builder.defineMacro("__VFP_FP__");
5230 Builder.defineMacro("__ARM_VFPV2__");
5232 Builder.defineMacro("__ARM_VFPV3__");
5234 Builder.defineMacro("__ARM_VFPV4__");
5237 // This only gets set when Neon instructions are actually available, unlike
5238 // the VFP define, hence the soft float and arch check. This is subtly
5239 // different from gcc, we follow the intent which was that it should be set
5240 // when Neon instructions are actually available.
5241 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
5242 Builder.defineMacro("__ARM_NEON", "1");
5243 Builder.defineMacro("__ARM_NEON__");
5244 // current AArch32 NEON implementations do not support double-precision
5245 // floating-point even when it is present in VFP.
5246 Builder.defineMacro("__ARM_NEON_FP",
5247 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP));
5250 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
5251 Opts.ShortWChar ? "2" : "4");
5253 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5254 Opts.ShortEnums ? "1" : "4");
5256 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") {
5257 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
5258 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
5259 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
5260 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
5263 // ACLE 6.4.7 DSP instructions
5265 Builder.defineMacro("__ARM_FEATURE_DSP", "1");
5268 // ACLE 6.4.8 Saturation instructions
5270 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) {
5271 Builder.defineMacro("__ARM_FEATURE_SAT", "1");
5275 // ACLE 6.4.6 Q (saturation) flag
5277 Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
5279 if (Opts.UnsafeFPMath)
5280 Builder.defineMacro("__ARM_FP_FAST", "1");
5282 if (ArchKind == llvm::ARM::AK_ARMV8_1A)
5283 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
5286 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5287 return llvm::makeArrayRef(BuiltinInfo,
5288 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin);
5290 bool isCLZForZeroUndef() const override { return false; }
5291 BuiltinVaListKind getBuiltinVaListKind() const override {
5293 ? AAPCSABIBuiltinVaList
5294 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList
5295 : TargetInfo::VoidPtrBuiltinVaList);
5297 ArrayRef<const char *> getGCCRegNames() const override;
5298 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5299 bool validateAsmConstraint(const char *&Name,
5300 TargetInfo::ConstraintInfo &Info) const override {
5305 case 't': // VFP Floating point register single precision
5306 case 'w': // VFP Floating point register double precision
5307 Info.setAllowsRegister();
5316 case 'Q': // A memory address that is a single base register.
5317 Info.setAllowsMemory();
5319 case 'U': // a memory reference...
5321 case 'q': // ...ARMV4 ldrsb
5322 case 'v': // ...VFP load/store (reg+constant offset)
5323 case 'y': // ...iWMMXt load/store
5324 case 't': // address valid for load/store opaque types wider
5326 case 'n': // valid address for Neon doubleword vector load/store
5327 case 'm': // valid address for Neon element and structure load/store
5328 case 's': // valid address for non-offset loads/stores of quad-word
5329 // values in four ARM registers
5330 Info.setAllowsMemory();
5337 std::string convertConstraint(const char *&Constraint) const override {
5339 switch (*Constraint) {
5340 case 'U': // Two-character constraint; add "^" hint for later parsing.
5341 R = std::string("^") + std::string(Constraint, 2);
5344 case 'p': // 'p' should be translated to 'r' by default.
5345 R = std::string("r");
5348 return std::string(1, *Constraint);
5353 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5354 std::string &SuggestedModifier) const override {
5355 bool isOutput = (Constraint[0] == '=');
5356 bool isInOut = (Constraint[0] == '+');
5358 // Strip off constraint modifiers.
5359 while (Constraint[0] == '=' ||
5360 Constraint[0] == '+' ||
5361 Constraint[0] == '&')
5362 Constraint = Constraint.substr(1);
5364 switch (Constraint[0]) {
5369 return (isInOut || isOutput || Size <= 64);
5371 // A register of size 32 cannot fit a vector type.
5379 const char *getClobbers() const override {
5380 // FIXME: Is this really right?
5384 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5391 return CCCR_Warning;
5395 int getEHDataRegisterNumber(unsigned RegNo) const override {
5396 if (RegNo == 0) return 0;
5397 if (RegNo == 1) return 1;
5401 bool hasSjLjLowering() const override {
5406 bool ARMTargetInfo::setFPMath(StringRef Name) {
5407 if (Name == "neon") {
5410 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
5418 const char * const ARMTargetInfo::GCCRegNames[] = {
5419 // Integer registers
5420 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5421 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
5424 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
5425 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
5426 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
5427 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5430 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
5431 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
5432 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
5433 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5436 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
5437 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
5440 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
5441 return llvm::makeArrayRef(GCCRegNames);
5444 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
5454 { { "v6", "rfp" }, "r9" },
5455 { { "sl" }, "r10" },
5456 { { "fp" }, "r11" },
5457 { { "ip" }, "r12" },
5458 { { "r13" }, "sp" },
5459 { { "r14" }, "lr" },
5460 { { "r15" }, "pc" },
5461 // The S, D and Q registers overlap, but aren't really aliases; we
5462 // don't want to substitute one of these for a different-sized one.
5465 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
5466 return llvm::makeArrayRef(GCCRegAliases);
5469 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
5470 #define BUILTIN(ID, TYPE, ATTRS) \
5471 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5472 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5473 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5474 #include "clang/Basic/BuiltinsNEON.def"
5476 #define BUILTIN(ID, TYPE, ATTRS) \
5477 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5478 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \
5479 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr },
5480 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5481 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5482 #include "clang/Basic/BuiltinsARM.def"
5485 class ARMleTargetInfo : public ARMTargetInfo {
5487 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5488 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/false) {}
5489 void getTargetDefines(const LangOptions &Opts,
5490 MacroBuilder &Builder) const override {
5491 Builder.defineMacro("__ARMEL__");
5492 ARMTargetInfo::getTargetDefines(Opts, Builder);
5496 class ARMbeTargetInfo : public ARMTargetInfo {
5498 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5499 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/true) {}
5500 void getTargetDefines(const LangOptions &Opts,
5501 MacroBuilder &Builder) const override {
5502 Builder.defineMacro("__ARMEB__");
5503 Builder.defineMacro("__ARM_BIG_ENDIAN");
5504 ARMTargetInfo::getTargetDefines(Opts, Builder);
5508 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
5509 const llvm::Triple Triple;
5511 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5512 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
5513 WCharType = UnsignedShort;
5514 SizeType = UnsignedInt;
5516 void getVisualStudioDefines(const LangOptions &Opts,
5517 MacroBuilder &Builder) const {
5518 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
5520 // FIXME: this is invalid for WindowsCE
5521 Builder.defineMacro("_M_ARM_NT", "1");
5522 Builder.defineMacro("_M_ARMT", "_M_ARM");
5523 Builder.defineMacro("_M_THUMB", "_M_ARM");
5525 assert((Triple.getArch() == llvm::Triple::arm ||
5526 Triple.getArch() == llvm::Triple::thumb) &&
5527 "invalid architecture for Windows ARM target info");
5528 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
5529 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
5531 // TODO map the complete set of values
5532 // 31: VFPv3 40: VFPv4
5533 Builder.defineMacro("_M_ARM_FP", "31");
5535 BuiltinVaListKind getBuiltinVaListKind() const override {
5536 return TargetInfo::CharPtrBuiltinVaList;
5538 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5541 case CC_X86ThisCall:
5542 case CC_X86FastCall:
5543 case CC_X86VectorCall:
5548 return CCCR_Warning;
5553 // Windows ARM + Itanium C++ ABI Target
5554 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
5556 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple,
5557 const TargetOptions &Opts)
5558 : WindowsARMTargetInfo(Triple, Opts) {
5559 TheCXXABI.set(TargetCXXABI::GenericARM);
5562 void getTargetDefines(const LangOptions &Opts,
5563 MacroBuilder &Builder) const override {
5564 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5566 if (Opts.MSVCCompat)
5567 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5571 // Windows ARM, MS (C++) ABI
5572 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
5574 MicrosoftARMleTargetInfo(const llvm::Triple &Triple,
5575 const TargetOptions &Opts)
5576 : WindowsARMTargetInfo(Triple, Opts) {
5577 TheCXXABI.set(TargetCXXABI::Microsoft);
5580 void getTargetDefines(const LangOptions &Opts,
5581 MacroBuilder &Builder) const override {
5582 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5583 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5588 class MinGWARMTargetInfo : public WindowsARMTargetInfo {
5590 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5591 : WindowsARMTargetInfo(Triple, Opts) {
5592 TheCXXABI.set(TargetCXXABI::GenericARM);
5595 void getTargetDefines(const LangOptions &Opts,
5596 MacroBuilder &Builder) const override {
5597 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5598 DefineStd(Builder, "WIN32", Opts);
5599 DefineStd(Builder, "WINNT", Opts);
5600 Builder.defineMacro("_ARM_");
5601 addMinGWDefines(Opts, Builder);
5605 // ARM Cygwin target
5606 class CygwinARMTargetInfo : public ARMleTargetInfo {
5608 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5609 : ARMleTargetInfo(Triple, Opts) {
5610 TLSSupported = false;
5611 WCharType = UnsignedShort;
5612 DoubleAlign = LongLongAlign = 64;
5613 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
5615 void getTargetDefines(const LangOptions &Opts,
5616 MacroBuilder &Builder) const override {
5617 ARMleTargetInfo::getTargetDefines(Opts, Builder);
5618 Builder.defineMacro("_ARM_");
5619 Builder.defineMacro("__CYGWIN__");
5620 Builder.defineMacro("__CYGWIN32__");
5621 DefineStd(Builder, "unix", Opts);
5623 Builder.defineMacro("_GNU_SOURCE");
5627 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> {
5629 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5630 MacroBuilder &Builder) const override {
5631 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5635 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5636 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
5637 HasAlignMac68kSupport = true;
5638 // iOS always has 64-bit atomic instructions.
5639 // FIXME: This should be based off of the target features in
5641 MaxAtomicInlineWidth = 64;
5643 if (Triple.isWatchABI()) {
5644 // Darwin on iOS uses a variant of the ARM C++ ABI.
5645 TheCXXABI.set(TargetCXXABI::WatchOS);
5647 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that
5648 // size_t is long, it's a bit weird for it to be int.
5649 PtrDiffType = SignedLong;
5651 // BOOL should be a real boolean on the new ABI
5652 UseSignedCharForObjCBool = false;
5654 TheCXXABI.set(TargetCXXABI::iOS);
5658 class AArch64TargetInfo : public TargetInfo {
5659 virtual void setDataLayout() = 0;
5660 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5661 static const char *const GCCRegNames[];
5674 static const Builtin::Info BuiltinInfo[];
5679 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5680 : TargetInfo(Triple), ABI("aapcs") {
5681 if (getTriple().getOS() == llvm::Triple::NetBSD) {
5682 WCharType = SignedInt;
5684 // NetBSD apparently prefers consistency across ARM targets to consistency
5685 // across 64-bit targets.
5686 Int64Type = SignedLongLong;
5687 IntMaxType = SignedLongLong;
5689 WCharType = UnsignedInt;
5690 Int64Type = SignedLong;
5691 IntMaxType = SignedLong;
5694 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5695 MaxVectorAlign = 128;
5696 MaxAtomicInlineWidth = 128;
5697 MaxAtomicPromoteWidth = 128;
5699 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
5700 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5702 // {} in inline assembly are neon specifiers, not assembly variant
5704 NoAsmVariants = true;
5706 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
5707 // contributes to the alignment of the containing aggregate in the same way
5708 // a plain (non bit-field) member of that type would, without exception for
5709 // zero-sized or anonymous bit-fields."
5710 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
5711 UseZeroLengthBitfieldAlignment = true;
5713 // AArch64 targets default to using the ARM C++ ABI.
5714 TheCXXABI.set(TargetCXXABI::GenericAArch64);
5716 if (Triple.getOS() == llvm::Triple::Linux ||
5717 Triple.getOS() == llvm::Triple::UnknownOS)
5718 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount";
5721 StringRef getABI() const override { return ABI; }
5722 bool setABI(const std::string &Name) override {
5723 if (Name != "aapcs" && Name != "darwinpcs")
5730 bool setCPU(const std::string &Name) override {
5731 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5732 .Case("generic", true)
5733 .Cases("cortex-a53", "cortex-a57", "cortex-a72",
5734 "cortex-a35", "exynos-m1", true)
5735 .Case("cortex-a73", true)
5736 .Case("cyclone", true)
5738 .Case("vulcan", true)
5743 void getTargetDefines(const LangOptions &Opts,
5744 MacroBuilder &Builder) const override {
5745 // Target identification.
5746 Builder.defineMacro("__aarch64__");
5748 // Target properties.
5749 Builder.defineMacro("_LP64");
5750 Builder.defineMacro("__LP64__");
5752 // ACLE predefines. Many can only have one possible value on v8 AArch64.
5753 Builder.defineMacro("__ARM_ACLE", "200");
5754 Builder.defineMacro("__ARM_ARCH", "8");
5755 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
5757 Builder.defineMacro("__ARM_64BIT_STATE", "1");
5758 Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
5759 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
5761 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
5762 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
5763 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
5764 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
5765 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
5766 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
5767 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
5769 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
5771 // 0xe implies support for half, single and double precision operations.
5772 Builder.defineMacro("__ARM_FP", "0xE");
5774 // PCS specifies this for SysV variants, which is all we support. Other ABIs
5775 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
5776 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
5777 Builder.defineMacro("__ARM_FP16_ARGS", "1");
5779 if (Opts.UnsafeFPMath)
5780 Builder.defineMacro("__ARM_FP_FAST", "1");
5782 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
5784 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5785 Opts.ShortEnums ? "1" : "4");
5787 if (FPU == NeonMode) {
5788 Builder.defineMacro("__ARM_NEON", "1");
5789 // 64-bit NEON supports half, single and double precision operations.
5790 Builder.defineMacro("__ARM_NEON_FP", "0xE");
5794 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
5797 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
5800 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
5803 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
5805 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
5806 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
5807 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
5808 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
5809 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
5812 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5813 return llvm::makeArrayRef(BuiltinInfo,
5814 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin);
5817 bool hasFeature(StringRef Feature) const override {
5818 return Feature == "aarch64" ||
5819 Feature == "arm64" ||
5821 (Feature == "neon" && FPU == NeonMode);
5824 bool handleTargetFeatures(std::vector<std::string> &Features,
5825 DiagnosticsEngine &Diags) override {
5832 for (const auto &Feature : Features) {
5833 if (Feature == "+neon")
5835 if (Feature == "+crc")
5837 if (Feature == "+crypto")
5839 if (Feature == "+strict-align")
5841 if (Feature == "+v8.1a")
5850 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5854 case CC_PreserveMost:
5855 case CC_PreserveAll:
5858 return CCCR_Warning;
5862 bool isCLZForZeroUndef() const override { return false; }
5864 BuiltinVaListKind getBuiltinVaListKind() const override {
5865 return TargetInfo::AArch64ABIBuiltinVaList;
5868 ArrayRef<const char *> getGCCRegNames() const override;
5869 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5871 bool validateAsmConstraint(const char *&Name,
5872 TargetInfo::ConstraintInfo &Info) const override {
5876 case 'w': // Floating point and SIMD registers (V0-V31)
5877 Info.setAllowsRegister();
5879 case 'I': // Constant that can be used with an ADD instruction
5880 case 'J': // Constant that can be used with a SUB instruction
5881 case 'K': // Constant that can be used with a 32-bit logical instruction
5882 case 'L': // Constant that can be used with a 64-bit logical instruction
5883 case 'M': // Constant that can be used as a 32-bit MOV immediate
5884 case 'N': // Constant that can be used as a 64-bit MOV immediate
5885 case 'Y': // Floating point constant zero
5886 case 'Z': // Integer constant zero
5888 case 'Q': // A memory reference with base register and no offset
5889 Info.setAllowsMemory();
5891 case 'S': // A symbolic address
5892 Info.setAllowsRegister();
5895 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
5896 // Utf: A memory address suitable for ldp/stp in TF mode.
5897 // Usa: An absolute symbolic address.
5898 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
5899 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
5900 case 'z': // Zero register, wzr or xzr
5901 Info.setAllowsRegister();
5903 case 'x': // Floating point and SIMD registers (V0-V15)
5904 Info.setAllowsRegister();
5911 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5912 std::string &SuggestedModifier) const override {
5913 // Strip off constraint modifiers.
5914 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
5915 Constraint = Constraint.substr(1);
5917 switch (Constraint[0]) {
5925 // For now assume that the person knows what they're
5926 // doing with the modifier.
5929 // By default an 'r' constraint will be in the 'x'
5934 SuggestedModifier = "w";
5941 const char *getClobbers() const override { return ""; }
5943 int getEHDataRegisterNumber(unsigned RegNo) const override {
5952 const char *const AArch64TargetInfo::GCCRegNames[] = {
5953 // 32-bit Integer registers
5954 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
5955 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
5956 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
5958 // 64-bit Integer registers
5959 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
5960 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
5961 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
5963 // 32-bit floating point regsisters
5964 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
5965 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
5966 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5968 // 64-bit floating point regsisters
5969 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
5970 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
5971 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5974 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
5975 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
5976 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
5979 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
5980 return llvm::makeArrayRef(GCCRegNames);
5983 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
5984 { { "w31" }, "wsp" },
5985 { { "x29" }, "fp" },
5986 { { "x30" }, "lr" },
5987 { { "x31" }, "sp" },
5988 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
5989 // don't want to substitute one of these for a different-sized one.
5992 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
5993 return llvm::makeArrayRef(GCCRegAliases);
5996 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
5997 #define BUILTIN(ID, TYPE, ATTRS) \
5998 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5999 #include "clang/Basic/BuiltinsNEON.def"
6001 #define BUILTIN(ID, TYPE, ATTRS) \
6002 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6003 #include "clang/Basic/BuiltinsAArch64.def"
6006 class AArch64leTargetInfo : public AArch64TargetInfo {
6007 void setDataLayout() override {
6008 if (getTriple().isOSBinFormatMachO())
6009 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128");
6011 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6015 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6016 : AArch64TargetInfo(Triple, Opts) {
6019 void getTargetDefines(const LangOptions &Opts,
6020 MacroBuilder &Builder) const override {
6021 Builder.defineMacro("__AARCH64EL__");
6022 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6026 class AArch64beTargetInfo : public AArch64TargetInfo {
6027 void setDataLayout() override {
6028 assert(!getTriple().isOSBinFormatMachO());
6029 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6033 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6034 : AArch64TargetInfo(Triple, Opts) {}
6035 void getTargetDefines(const LangOptions &Opts,
6036 MacroBuilder &Builder) const override {
6037 Builder.defineMacro("__AARCH64EB__");
6038 Builder.defineMacro("__AARCH_BIG_ENDIAN");
6039 Builder.defineMacro("__ARM_BIG_ENDIAN");
6040 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6044 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
6046 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
6047 MacroBuilder &Builder) const override {
6048 Builder.defineMacro("__AARCH64_SIMD__");
6049 Builder.defineMacro("__ARM64_ARCH_8__");
6050 Builder.defineMacro("__ARM_NEON__");
6051 Builder.defineMacro("__LITTLE_ENDIAN__");
6052 Builder.defineMacro("__REGISTER_PREFIX__", "");
6053 Builder.defineMacro("__arm64", "1");
6054 Builder.defineMacro("__arm64__", "1");
6056 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
6060 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6061 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
6062 Int64Type = SignedLongLong;
6063 WCharType = SignedInt;
6064 UseSignedCharForObjCBool = false;
6066 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
6067 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6069 TheCXXABI.set(TargetCXXABI::iOS64);
6072 BuiltinVaListKind getBuiltinVaListKind() const override {
6073 return TargetInfo::CharPtrBuiltinVaList;
6077 // Hexagon abstract base class
6078 class HexagonTargetInfo : public TargetInfo {
6079 static const Builtin::Info BuiltinInfo[];
6080 static const char * const GCCRegNames[];
6081 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6083 bool HasHVX, HasHVXDouble;
6086 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6087 : TargetInfo(Triple) {
6089 // Specify the vector alignment explicitly. For v512x1, the calculated
6090 // alignment would be 512*alignment(i1), which is 512 bytes, instead of
6091 // the required minimum of 64 bytes.
6092 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-"
6093 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
6094 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048");
6095 SizeType = UnsignedInt;
6096 PtrDiffType = SignedInt;
6097 IntPtrType = SignedInt;
6099 // {} in inline assembly are packet specifiers, not assembly variant
6101 NoAsmVariants = true;
6103 LargeArrayMinWidth = 64;
6104 LargeArrayAlign = 64;
6105 UseBitFieldTypeAlignment = true;
6106 ZeroLengthBitfieldBoundary = 32;
6107 HasHVX = HasHVXDouble = false;
6110 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6111 return llvm::makeArrayRef(BuiltinInfo,
6112 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin);
6115 bool validateAsmConstraint(const char *&Name,
6116 TargetInfo::ConstraintInfo &Info) const override {
6121 Info.setAllowsRegister();
6126 // Relocatable constant.
6132 void getTargetDefines(const LangOptions &Opts,
6133 MacroBuilder &Builder) const override;
6135 bool isCLZForZeroUndef() const override { return false; }
6137 bool hasFeature(StringRef Feature) const override {
6138 return llvm::StringSwitch<bool>(Feature)
6139 .Case("hexagon", true)
6140 .Case("hvx", HasHVX)
6141 .Case("hvx-double", HasHVXDouble)
6145 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6146 StringRef CPU, const std::vector<std::string> &FeaturesVec)
6149 bool handleTargetFeatures(std::vector<std::string> &Features,
6150 DiagnosticsEngine &Diags) override;
6152 BuiltinVaListKind getBuiltinVaListKind() const override {
6153 return TargetInfo::CharPtrBuiltinVaList;
6155 ArrayRef<const char *> getGCCRegNames() const override;
6156 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6157 const char *getClobbers() const override {
6161 static const char *getHexagonCPUSuffix(StringRef Name) {
6162 return llvm::StringSwitch<const char*>(Name)
6163 .Case("hexagonv4", "4")
6164 .Case("hexagonv5", "5")
6165 .Case("hexagonv55", "55")
6166 .Case("hexagonv60", "60")
6170 bool setCPU(const std::string &Name) override {
6171 if (!getHexagonCPUSuffix(Name))
6177 int getEHDataRegisterNumber(unsigned RegNo) const override {
6178 return RegNo < 2 ? RegNo : -1;
6182 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
6183 MacroBuilder &Builder) const {
6184 Builder.defineMacro("__qdsp6__", "1");
6185 Builder.defineMacro("__hexagon__", "1");
6187 if (CPU == "hexagonv4") {
6188 Builder.defineMacro("__HEXAGON_V4__");
6189 Builder.defineMacro("__HEXAGON_ARCH__", "4");
6190 if (Opts.HexagonQdsp6Compat) {
6191 Builder.defineMacro("__QDSP6_V4__");
6192 Builder.defineMacro("__QDSP6_ARCH__", "4");
6194 } else if (CPU == "hexagonv5") {
6195 Builder.defineMacro("__HEXAGON_V5__");
6196 Builder.defineMacro("__HEXAGON_ARCH__", "5");
6197 if(Opts.HexagonQdsp6Compat) {
6198 Builder.defineMacro("__QDSP6_V5__");
6199 Builder.defineMacro("__QDSP6_ARCH__", "5");
6201 } else if (CPU == "hexagonv55") {
6202 Builder.defineMacro("__HEXAGON_V55__");
6203 Builder.defineMacro("__HEXAGON_ARCH__", "55");
6204 Builder.defineMacro("__QDSP6_V55__");
6205 Builder.defineMacro("__QDSP6_ARCH__", "55");
6206 } else if (CPU == "hexagonv60") {
6207 Builder.defineMacro("__HEXAGON_V60__");
6208 Builder.defineMacro("__HEXAGON_ARCH__", "60");
6209 Builder.defineMacro("__QDSP6_V60__");
6210 Builder.defineMacro("__QDSP6_ARCH__", "60");
6213 if (hasFeature("hvx")) {
6214 Builder.defineMacro("__HVX__");
6215 if (hasFeature("hvx-double"))
6216 Builder.defineMacro("__HVXDBL__");
6220 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
6221 DiagnosticsEngine &Diags) {
6222 for (auto &F : Features) {
6225 else if (F == "-hvx")
6226 HasHVX = HasHVXDouble = false;
6227 else if (F == "+hvx-double")
6228 HasHVX = HasHVXDouble = true;
6229 else if (F == "-hvx-double")
6230 HasHVXDouble = false;
6235 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features,
6236 DiagnosticsEngine &Diags, StringRef CPU,
6237 const std::vector<std::string> &FeaturesVec) const {
6238 // Default for v60: -hvx, -hvx-double.
6239 Features["hvx"] = false;
6240 Features["hvx-double"] = false;
6242 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6246 const char *const HexagonTargetInfo::GCCRegNames[] = {
6247 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6248 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6249 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6250 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
6251 "p0", "p1", "p2", "p3",
6252 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
6255 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const {
6256 return llvm::makeArrayRef(GCCRegNames);
6259 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
6260 { { "sp" }, "r29" },
6261 { { "fp" }, "r30" },
6262 { { "lr" }, "r31" },
6265 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const {
6266 return llvm::makeArrayRef(GCCRegAliases);
6270 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
6271 #define BUILTIN(ID, TYPE, ATTRS) \
6272 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6273 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6274 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6275 #include "clang/Basic/BuiltinsHexagon.def"
6278 class LanaiTargetInfo : public TargetInfo {
6279 // Class for Lanai (32-bit).
6280 // The CPU profiles supported by the Lanai backend
6286 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6287 static const char *const GCCRegNames[];
6290 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6291 : TargetInfo(Triple) {
6292 // Description string has to be kept in sync with backend.
6293 resetDataLayout("E" // Big endian
6294 "-m:e" // ELF name manging
6295 "-p:32:32" // 32 bit pointers, 32 bit aligned
6296 "-i64:64" // 64 bit integers, 64 bit aligned
6297 "-a:0:32" // 32 bit alignment of objects of aggregate type
6298 "-n32" // 32 bit native integer width
6299 "-S64" // 64 bit natural stack alignment
6302 // Setting RegParmMax equal to what mregparm was set to in the old
6306 // Set the default CPU to V11
6309 // Temporary approach to make everything at least word-aligned and allow for
6310 // safely casting between pointers with different alignment requirements.
6311 // TODO: Remove this when there are no more cast align warnings on the
6313 MinGlobalAlign = 32;
6316 void getTargetDefines(const LangOptions &Opts,
6317 MacroBuilder &Builder) const override {
6318 // Define __lanai__ when building for target lanai.
6319 Builder.defineMacro("__lanai__");
6321 // Set define for the CPU specified.
6324 Builder.defineMacro("__LANAI_V11__");
6327 llvm_unreachable("Unhandled target CPU");
6331 bool setCPU(const std::string &Name) override {
6332 CPU = llvm::StringSwitch<CPUKind>(Name)
6333 .Case("v11", CK_V11)
6336 return CPU != CK_NONE;
6339 bool hasFeature(StringRef Feature) const override {
6340 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false);
6343 ArrayRef<const char *> getGCCRegNames() const override;
6345 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6347 BuiltinVaListKind getBuiltinVaListKind() const override {
6348 return TargetInfo::VoidPtrBuiltinVaList;
6351 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
6353 bool validateAsmConstraint(const char *&Name,
6354 TargetInfo::ConstraintInfo &info) const override {
6358 const char *getClobbers() const override { return ""; }
6361 const char *const LanaiTargetInfo::GCCRegNames[] = {
6362 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
6363 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
6364 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
6366 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const {
6367 return llvm::makeArrayRef(GCCRegNames);
6370 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = {
6380 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const {
6381 return llvm::makeArrayRef(GCCRegAliases);
6384 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
6385 class SparcTargetInfo : public TargetInfo {
6386 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6387 static const char * const GCCRegNames[];
6390 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6391 : TargetInfo(Triple), SoftFloat(false) {}
6393 int getEHDataRegisterNumber(unsigned RegNo) const override {
6394 if (RegNo == 0) return 24;
6395 if (RegNo == 1) return 25;
6399 bool handleTargetFeatures(std::vector<std::string> &Features,
6400 DiagnosticsEngine &Diags) override {
6401 // Check if software floating point is enabled
6402 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
6403 if (Feature != Features.end()) {
6408 void getTargetDefines(const LangOptions &Opts,
6409 MacroBuilder &Builder) const override {
6410 DefineStd(Builder, "sparc", Opts);
6411 Builder.defineMacro("__REGISTER_PREFIX__", "");
6414 Builder.defineMacro("SOFT_FLOAT", "1");
6417 bool hasFeature(StringRef Feature) const override {
6418 return llvm::StringSwitch<bool>(Feature)
6419 .Case("softfloat", SoftFloat)
6420 .Case("sparc", true)
6424 bool hasSjLjLowering() const override {
6428 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6429 // FIXME: Implement!
6432 BuiltinVaListKind getBuiltinVaListKind() const override {
6433 return TargetInfo::VoidPtrBuiltinVaList;
6435 ArrayRef<const char *> getGCCRegNames() const override;
6436 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6437 bool validateAsmConstraint(const char *&Name,
6438 TargetInfo::ConstraintInfo &info) const override {
6439 // FIXME: Implement!
6441 case 'I': // Signed 13-bit constant
6443 case 'K': // 32-bit constant with the low 12 bits clear
6444 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
6445 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
6446 case 'N': // Same as 'K' but zext (required for SIMode)
6447 case 'O': // The constant 4096
6452 const char *getClobbers() const override {
6453 // FIXME: Implement!
6457 // No Sparc V7 for now, the backend doesn't support it anyway.
6487 enum CPUGeneration {
6492 CPUGeneration getCPUGeneration(CPUKind Kind) const {
6500 case CK_SPARCLITE86X:
6506 case CK_LEON2_AT697E:
6507 case CK_LEON2_AT697F:
6509 case CK_LEON3_UT699:
6510 case CK_LEON3_GR712RC:
6512 case CK_LEON4_GR740:
6516 case CK_ULTRASPARC3:
6523 llvm_unreachable("Unexpected CPU kind");
6526 CPUKind getCPUKind(StringRef Name) const {
6527 return llvm::StringSwitch<CPUKind>(Name)
6529 .Case("supersparc", CK_SUPERSPARC)
6530 .Case("sparclite", CK_SPARCLITE)
6531 .Case("f934", CK_F934)
6532 .Case("hypersparc", CK_HYPERSPARC)
6533 .Case("sparclite86x", CK_SPARCLITE86X)
6534 .Case("sparclet", CK_SPARCLET)
6535 .Case("tsc701", CK_TSC701)
6537 .Case("ultrasparc", CK_ULTRASPARC)
6538 .Case("ultrasparc3", CK_ULTRASPARC3)
6539 .Case("niagara", CK_NIAGARA)
6540 .Case("niagara2", CK_NIAGARA2)
6541 .Case("niagara3", CK_NIAGARA3)
6542 .Case("niagara4", CK_NIAGARA4)
6543 .Case("myriad2", CK_MYRIAD2_1)
6544 .Case("myriad2.1", CK_MYRIAD2_1)
6545 .Case("myriad2.2", CK_MYRIAD2_2)
6546 .Case("leon2", CK_LEON2)
6547 .Case("at697e", CK_LEON2_AT697E)
6548 .Case("at697f", CK_LEON2_AT697F)
6549 .Case("leon3", CK_LEON3)
6550 .Case("ut699", CK_LEON3_UT699)
6551 .Case("gr712rc", CK_LEON3_GR712RC)
6552 .Case("leon4", CK_LEON4)
6553 .Case("gr740", CK_LEON4_GR740)
6554 .Default(CK_GENERIC);
6557 bool setCPU(const std::string &Name) override {
6558 CPU = getCPUKind(Name);
6559 return CPU != CK_GENERIC;
6563 const char * const SparcTargetInfo::GCCRegNames[] = {
6564 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6565 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6566 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6567 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6570 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
6571 return llvm::makeArrayRef(GCCRegNames);
6574 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
6585 { { "o2" }, "r10" },
6586 { { "o3" }, "r11" },
6587 { { "o4" }, "r12" },
6588 { { "o5" }, "r13" },
6589 { { "o6", "sp" }, "r14" },
6590 { { "o7" }, "r15" },
6591 { { "l0" }, "r16" },
6592 { { "l1" }, "r17" },
6593 { { "l2" }, "r18" },
6594 { { "l3" }, "r19" },
6595 { { "l4" }, "r20" },
6596 { { "l5" }, "r21" },
6597 { { "l6" }, "r22" },
6598 { { "l7" }, "r23" },
6599 { { "i0" }, "r24" },
6600 { { "i1" }, "r25" },
6601 { { "i2" }, "r26" },
6602 { { "i3" }, "r27" },
6603 { { "i4" }, "r28" },
6604 { { "i5" }, "r29" },
6605 { { "i6", "fp" }, "r30" },
6606 { { "i7" }, "r31" },
6609 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
6610 return llvm::makeArrayRef(GCCRegAliases);
6613 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
6614 class SparcV8TargetInfo : public SparcTargetInfo {
6616 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6617 : SparcTargetInfo(Triple, Opts) {
6618 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64");
6619 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
6620 switch (getTriple().getOS()) {
6622 SizeType = UnsignedInt;
6623 IntPtrType = SignedInt;
6624 PtrDiffType = SignedInt;
6626 case llvm::Triple::NetBSD:
6627 case llvm::Triple::OpenBSD:
6628 SizeType = UnsignedLong;
6629 IntPtrType = SignedLong;
6630 PtrDiffType = SignedLong;
6633 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6636 void getTargetDefines(const LangOptions &Opts,
6637 MacroBuilder &Builder) const override {
6638 SparcTargetInfo::getTargetDefines(Opts, Builder);
6639 switch (getCPUGeneration(CPU)) {
6641 Builder.defineMacro("__sparcv8");
6642 if (getTriple().getOS() != llvm::Triple::Solaris)
6643 Builder.defineMacro("__sparcv8__");
6646 Builder.defineMacro("__sparcv9");
6647 if (getTriple().getOS() != llvm::Triple::Solaris) {
6648 Builder.defineMacro("__sparcv9__");
6649 Builder.defineMacro("__sparc_v9__");
6653 if (getTriple().getVendor() == llvm::Triple::Myriad) {
6656 Builder.defineMacro("__myriad2", "1");
6657 Builder.defineMacro("__myriad2__", "1");
6660 Builder.defineMacro("__myriad2", "2");
6661 Builder.defineMacro("__myriad2__", "2");
6669 bool hasSjLjLowering() const override {
6674 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
6675 class SparcV8elTargetInfo : public SparcV8TargetInfo {
6677 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6678 : SparcV8TargetInfo(Triple, Opts) {
6679 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64");
6684 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
6685 class SparcV9TargetInfo : public SparcTargetInfo {
6687 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6688 : SparcTargetInfo(Triple, Opts) {
6689 // FIXME: Support Sparc quad-precision long double?
6690 resetDataLayout("E-m:e-i64:64-n32:64-S128");
6691 // This is an LP64 platform.
6692 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6694 // OpenBSD uses long long for int64_t and intmax_t.
6695 if (getTriple().getOS() == llvm::Triple::OpenBSD)
6696 IntMaxType = SignedLongLong;
6698 IntMaxType = SignedLong;
6699 Int64Type = IntMaxType;
6701 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
6702 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
6703 LongDoubleWidth = 128;
6704 LongDoubleAlign = 128;
6705 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6706 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6709 void getTargetDefines(const LangOptions &Opts,
6710 MacroBuilder &Builder) const override {
6711 SparcTargetInfo::getTargetDefines(Opts, Builder);
6712 Builder.defineMacro("__sparcv9");
6713 Builder.defineMacro("__arch64__");
6714 // Solaris doesn't need these variants, but the BSDs do.
6715 if (getTriple().getOS() != llvm::Triple::Solaris) {
6716 Builder.defineMacro("__sparc64__");
6717 Builder.defineMacro("__sparc_v9__");
6718 Builder.defineMacro("__sparcv9__");
6722 bool setCPU(const std::string &Name) override {
6723 if (!SparcTargetInfo::setCPU(Name))
6725 return getCPUGeneration(CPU) == CG_V9;
6729 class SystemZTargetInfo : public TargetInfo {
6730 static const Builtin::Info BuiltinInfo[];
6731 static const char *const GCCRegNames[];
6733 bool HasTransactionalExecution;
6737 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6738 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false),
6740 IntMaxType = SignedLong;
6741 Int64Type = SignedLong;
6742 TLSSupported = true;
6743 IntWidth = IntAlign = 32;
6744 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
6745 PointerWidth = PointerAlign = 64;
6746 LongDoubleWidth = 128;
6747 LongDoubleAlign = 64;
6748 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6749 DefaultAlignForAttributeAligned = 64;
6750 MinGlobalAlign = 16;
6751 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64");
6752 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6754 void getTargetDefines(const LangOptions &Opts,
6755 MacroBuilder &Builder) const override {
6756 Builder.defineMacro("__s390__");
6757 Builder.defineMacro("__s390x__");
6758 Builder.defineMacro("__zarch__");
6759 Builder.defineMacro("__LONG_DOUBLE_128__");
6761 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
6762 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
6763 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
6764 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
6766 if (HasTransactionalExecution)
6767 Builder.defineMacro("__HTM__");
6769 Builder.defineMacro("__VEC__", "10301");
6771 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6772 return llvm::makeArrayRef(BuiltinInfo,
6773 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin);
6776 ArrayRef<const char *> getGCCRegNames() const override;
6777 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6781 bool validateAsmConstraint(const char *&Name,
6782 TargetInfo::ConstraintInfo &info) const override;
6783 const char *getClobbers() const override {
6784 // FIXME: Is this really right?
6787 BuiltinVaListKind getBuiltinVaListKind() const override {
6788 return TargetInfo::SystemZBuiltinVaList;
6790 bool setCPU(const std::string &Name) override {
6792 bool CPUKnown = llvm::StringSwitch<bool>(Name)
6795 .Case("zEC12", true)
6802 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6804 const std::vector<std::string> &FeaturesVec) const override {
6806 Features["transactional-execution"] = true;
6808 Features["transactional-execution"] = true;
6809 Features["vector"] = true;
6811 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6814 bool handleTargetFeatures(std::vector<std::string> &Features,
6815 DiagnosticsEngine &Diags) override {
6816 HasTransactionalExecution = false;
6817 for (const auto &Feature : Features) {
6818 if (Feature == "+transactional-execution")
6819 HasTransactionalExecution = true;
6820 else if (Feature == "+vector")
6823 // If we use the vector ABI, vector types are 64-bit aligned.
6825 MaxVectorAlign = 64;
6826 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
6827 "-v128:64-a:8:16-n32:64");
6832 bool hasFeature(StringRef Feature) const override {
6833 return llvm::StringSwitch<bool>(Feature)
6834 .Case("systemz", true)
6835 .Case("htm", HasTransactionalExecution)
6836 .Case("vx", HasVector)
6840 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6846 return CCCR_Warning;
6850 StringRef getABI() const override {
6856 bool useFloat128ManglingForLongDouble() const override {
6861 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
6862 #define BUILTIN(ID, TYPE, ATTRS) \
6863 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6864 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
6865 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
6866 #include "clang/Basic/BuiltinsSystemZ.def"
6869 const char *const SystemZTargetInfo::GCCRegNames[] = {
6870 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6871 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6872 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
6873 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
6876 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
6877 return llvm::makeArrayRef(GCCRegNames);
6880 bool SystemZTargetInfo::
6881 validateAsmConstraint(const char *&Name,
6882 TargetInfo::ConstraintInfo &Info) const {
6887 case 'a': // Address register
6888 case 'd': // Data register (equivalent to 'r')
6889 case 'f': // Floating-point register
6890 Info.setAllowsRegister();
6893 case 'I': // Unsigned 8-bit constant
6894 case 'J': // Unsigned 12-bit constant
6895 case 'K': // Signed 16-bit constant
6896 case 'L': // Signed 20-bit displacement (on all targets we support)
6897 case 'M': // 0x7fffffff
6900 case 'Q': // Memory with base and unsigned 12-bit displacement
6901 case 'R': // Likewise, plus an index
6902 case 'S': // Memory with base and signed 20-bit displacement
6903 case 'T': // Likewise, plus an index
6904 Info.setAllowsMemory();
6909 class MSP430TargetInfo : public TargetInfo {
6910 static const char *const GCCRegNames[];
6913 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6914 : TargetInfo(Triple) {
6916 TLSSupported = false;
6921 LongAlign = LongLongAlign = 16;
6925 SizeType = UnsignedInt;
6926 IntMaxType = SignedLongLong;
6927 IntPtrType = SignedInt;
6928 PtrDiffType = SignedInt;
6929 SigAtomicType = SignedLong;
6930 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16");
6932 void getTargetDefines(const LangOptions &Opts,
6933 MacroBuilder &Builder) const override {
6934 Builder.defineMacro("MSP430");
6935 Builder.defineMacro("__MSP430__");
6936 // FIXME: defines for different 'flavours' of MCU
6938 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6939 // FIXME: Implement.
6942 bool hasFeature(StringRef Feature) const override {
6943 return Feature == "msp430";
6945 ArrayRef<const char *> getGCCRegNames() const override;
6946 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6950 bool validateAsmConstraint(const char *&Name,
6951 TargetInfo::ConstraintInfo &info) const override {
6954 case 'K': // the constant 1
6955 case 'L': // constant -1^20 .. 1^19
6956 case 'M': // constant 1-4:
6959 // No target constraints for now.
6962 const char *getClobbers() const override {
6963 // FIXME: Is this really right?
6966 BuiltinVaListKind getBuiltinVaListKind() const override {
6968 return TargetInfo::CharPtrBuiltinVaList;
6972 const char *const MSP430TargetInfo::GCCRegNames[] = {
6973 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6974 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
6976 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const {
6977 return llvm::makeArrayRef(GCCRegNames);
6980 // LLVM and Clang cannot be used directly to output native binaries for
6981 // target, but is used to compile C code to llvm bitcode with correct
6982 // type and alignment information.
6984 // TCE uses the llvm bitcode as input and uses it for generating customized
6985 // target processor and program binary. TCE co-design environment is
6986 // publicly available in http://tce.cs.tut.fi
6988 static const unsigned TCEOpenCLAddrSpaceMap[] = {
6991 5, // opencl_constant
6992 // FIXME: generic has to be added to the target
6993 0, // opencl_generic
6999 class TCETargetInfo : public TargetInfo {
7001 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7002 : TargetInfo(Triple) {
7003 TLSSupported = false;
7005 LongWidth = LongLongWidth = 32;
7008 LongAlign = LongLongAlign = 32;
7011 SizeType = UnsignedInt;
7012 IntMaxType = SignedLong;
7013 IntPtrType = SignedInt;
7014 PtrDiffType = SignedInt;
7019 LongDoubleWidth = 32;
7020 LongDoubleAlign = 32;
7021 FloatFormat = &llvm::APFloat::IEEEsingle;
7022 DoubleFormat = &llvm::APFloat::IEEEsingle;
7023 LongDoubleFormat = &llvm::APFloat::IEEEsingle;
7024 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32"
7025 "-f64:32-v64:32-v128:32-a:0:32-n32");
7026 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
7027 UseAddrSpaceMapMangling = true;
7030 void getTargetDefines(const LangOptions &Opts,
7031 MacroBuilder &Builder) const override {
7032 DefineStd(Builder, "tce", Opts);
7033 Builder.defineMacro("__TCE__");
7034 Builder.defineMacro("__TCE_V1__");
7036 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; }
7038 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7039 const char *getClobbers() const override { return ""; }
7040 BuiltinVaListKind getBuiltinVaListKind() const override {
7041 return TargetInfo::VoidPtrBuiltinVaList;
7043 ArrayRef<const char *> getGCCRegNames() const override { return None; }
7044 bool validateAsmConstraint(const char *&Name,
7045 TargetInfo::ConstraintInfo &info) const override {
7048 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7053 class BPFTargetInfo : public TargetInfo {
7055 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7056 : TargetInfo(Triple) {
7057 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7058 SizeType = UnsignedLong;
7059 PtrDiffType = SignedLong;
7060 IntPtrType = SignedLong;
7061 IntMaxType = SignedLong;
7062 Int64Type = SignedLong;
7064 if (Triple.getArch() == llvm::Triple::bpfeb) {
7066 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128");
7069 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
7071 MaxAtomicPromoteWidth = 64;
7072 MaxAtomicInlineWidth = 64;
7073 TLSSupported = false;
7075 void getTargetDefines(const LangOptions &Opts,
7076 MacroBuilder &Builder) const override {
7077 DefineStd(Builder, "bpf", Opts);
7078 Builder.defineMacro("__BPF__");
7080 bool hasFeature(StringRef Feature) const override {
7081 return Feature == "bpf";
7084 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7085 const char *getClobbers() const override {
7088 BuiltinVaListKind getBuiltinVaListKind() const override {
7089 return TargetInfo::VoidPtrBuiltinVaList;
7091 ArrayRef<const char *> getGCCRegNames() const override {
7094 bool validateAsmConstraint(const char *&Name,
7095 TargetInfo::ConstraintInfo &info) const override {
7098 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7103 class MipsTargetInfo : public TargetInfo {
7104 void setDataLayout() {
7108 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
7109 else if (ABI == "n32")
7110 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7111 else if (ABI == "n64")
7112 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7114 llvm_unreachable("Invalid ABI");
7117 resetDataLayout(("E-" + Layout).str());
7119 resetDataLayout(("e-" + Layout).str());
7123 static const Builtin::Info BuiltinInfo[];
7130 HardFloat, SoftFloat
7142 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7143 : TargetInfo(Triple), IsMips16(false), IsMicromips(false),
7144 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
7145 DspRev(NoDSP), HasMSA(false), HasFP64(false) {
7146 TheCXXABI.set(TargetCXXABI::GenericMIPS);
7147 BigEndian = getTriple().getArch() == llvm::Triple::mips ||
7148 getTriple().getArch() == llvm::Triple::mips64;
7150 setABI((getTriple().getArch() == llvm::Triple::mips ||
7151 getTriple().getArch() == llvm::Triple::mipsel)
7155 CPU = ABI == "o32" ? "mips32r2" : "mips64r2";
7158 bool isNaN2008Default() const {
7159 return CPU == "mips32r6" || CPU == "mips64r6";
7162 bool isFP64Default() const {
7163 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
7166 bool isNan2008() const override {
7170 bool processorSupportsGPR64() const {
7171 return llvm::StringSwitch<bool>(CPU)
7172 .Case("mips3", true)
7173 .Case("mips4", true)
7174 .Case("mips5", true)
7175 .Case("mips64", true)
7176 .Case("mips64r2", true)
7177 .Case("mips64r3", true)
7178 .Case("mips64r5", true)
7179 .Case("mips64r6", true)
7180 .Case("octeon", true)
7185 StringRef getABI() const override { return ABI; }
7186 bool setABI(const std::string &Name) override {
7187 if (Name == "o32") {
7193 if (Name == "n32") {
7198 if (Name == "n64") {
7206 void setO32ABITypes() {
7207 Int64Type = SignedLongLong;
7208 IntMaxType = Int64Type;
7209 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
7210 LongDoubleWidth = LongDoubleAlign = 64;
7211 LongWidth = LongAlign = 32;
7212 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
7213 PointerWidth = PointerAlign = 32;
7214 PtrDiffType = SignedInt;
7215 SizeType = UnsignedInt;
7219 void setN32N64ABITypes() {
7220 LongDoubleWidth = LongDoubleAlign = 128;
7221 LongDoubleFormat = &llvm::APFloat::IEEEquad;
7222 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
7223 LongDoubleWidth = LongDoubleAlign = 64;
7224 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
7226 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7227 SuitableAlign = 128;
7230 void setN64ABITypes() {
7231 setN32N64ABITypes();
7232 Int64Type = SignedLong;
7233 IntMaxType = Int64Type;
7234 LongWidth = LongAlign = 64;
7235 PointerWidth = PointerAlign = 64;
7236 PtrDiffType = SignedLong;
7237 SizeType = UnsignedLong;
7240 void setN32ABITypes() {
7241 setN32N64ABITypes();
7242 Int64Type = SignedLongLong;
7243 IntMaxType = Int64Type;
7244 LongWidth = LongAlign = 32;
7245 PointerWidth = PointerAlign = 32;
7246 PtrDiffType = SignedInt;
7247 SizeType = UnsignedInt;
7250 bool setCPU(const std::string &Name) override {
7252 return llvm::StringSwitch<bool>(Name)
7253 .Case("mips1", true)
7254 .Case("mips2", true)
7255 .Case("mips3", true)
7256 .Case("mips4", true)
7257 .Case("mips5", true)
7258 .Case("mips32", true)
7259 .Case("mips32r2", true)
7260 .Case("mips32r3", true)
7261 .Case("mips32r5", true)
7262 .Case("mips32r6", true)
7263 .Case("mips64", true)
7264 .Case("mips64r2", true)
7265 .Case("mips64r3", true)
7266 .Case("mips64r5", true)
7267 .Case("mips64r6", true)
7268 .Case("octeon", true)
7269 .Case("p5600", true)
7272 const std::string& getCPU() const { return CPU; }
7274 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7276 const std::vector<std::string> &FeaturesVec) const override {
7279 if (CPU == "octeon")
7280 Features["mips64r2"] = Features["cnmips"] = true;
7282 Features[CPU] = true;
7283 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7286 void getTargetDefines(const LangOptions &Opts,
7287 MacroBuilder &Builder) const override {
7289 DefineStd(Builder, "MIPSEB", Opts);
7290 Builder.defineMacro("_MIPSEB");
7292 DefineStd(Builder, "MIPSEL", Opts);
7293 Builder.defineMacro("_MIPSEL");
7296 Builder.defineMacro("__mips__");
7297 Builder.defineMacro("_mips");
7299 Builder.defineMacro("mips");
7302 Builder.defineMacro("__mips", "32");
7303 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
7305 Builder.defineMacro("__mips", "64");
7306 Builder.defineMacro("__mips64");
7307 Builder.defineMacro("__mips64__");
7308 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
7311 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU())
7312 .Cases("mips32", "mips64", "1")
7313 .Cases("mips32r2", "mips64r2", "2")
7314 .Cases("mips32r3", "mips64r3", "3")
7315 .Cases("mips32r5", "mips64r5", "5")
7316 .Cases("mips32r6", "mips64r6", "6")
7318 if (!ISARev.empty())
7319 Builder.defineMacro("__mips_isa_rev", ISARev);
7322 Builder.defineMacro("__mips_o32");
7323 Builder.defineMacro("_ABIO32", "1");
7324 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
7325 } else if (ABI == "n32") {
7326 Builder.defineMacro("__mips_n32");
7327 Builder.defineMacro("_ABIN32", "2");
7328 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
7329 } else if (ABI == "n64") {
7330 Builder.defineMacro("__mips_n64");
7331 Builder.defineMacro("_ABI64", "3");
7332 Builder.defineMacro("_MIPS_SIM", "_ABI64");
7334 llvm_unreachable("Invalid ABI.");
7336 Builder.defineMacro("__REGISTER_PREFIX__", "");
7340 Builder.defineMacro("__mips_hard_float", Twine(1));
7343 Builder.defineMacro("__mips_soft_float", Twine(1));
7348 Builder.defineMacro("__mips_single_float", Twine(1));
7350 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
7351 Builder.defineMacro("_MIPS_FPSET",
7352 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
7355 Builder.defineMacro("__mips16", Twine(1));
7358 Builder.defineMacro("__mips_micromips", Twine(1));
7361 Builder.defineMacro("__mips_nan2008", Twine(1));
7367 Builder.defineMacro("__mips_dsp_rev", Twine(1));
7368 Builder.defineMacro("__mips_dsp", Twine(1));
7371 Builder.defineMacro("__mips_dsp_rev", Twine(2));
7372 Builder.defineMacro("__mips_dspr2", Twine(1));
7373 Builder.defineMacro("__mips_dsp", Twine(1));
7378 Builder.defineMacro("__mips_msa", Twine(1));
7380 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
7381 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
7382 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
7384 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
7385 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
7387 // These shouldn't be defined for MIPS-I but there's no need to check
7388 // for that since MIPS-I isn't supported.
7389 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
7390 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
7391 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
7393 // 32-bit MIPS processors don't have the necessary lld/scd instructions
7394 // found in 64-bit processors. In the case of O32 on a 64-bit processor,
7395 // the instructions exist but using them violates the ABI since they
7396 // require 64-bit GPRs and O32 only supports 32-bit GPRs.
7397 if (ABI == "n32" || ABI == "n64")
7398 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
7401 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7402 return llvm::makeArrayRef(BuiltinInfo,
7403 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin);
7405 bool hasFeature(StringRef Feature) const override {
7406 return llvm::StringSwitch<bool>(Feature)
7408 .Case("fp64", HasFP64)
7411 BuiltinVaListKind getBuiltinVaListKind() const override {
7412 return TargetInfo::VoidPtrBuiltinVaList;
7414 ArrayRef<const char *> getGCCRegNames() const override {
7415 static const char *const GCCRegNames[] = {
7416 // CPU register names
7417 // Must match second column of GCCRegAliases
7418 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
7419 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
7420 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
7421 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
7422 // Floating point register names
7423 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
7424 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
7425 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
7426 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
7427 // Hi/lo and condition register names
7428 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
7429 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo",
7431 // MSA register names
7432 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
7433 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
7434 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
7435 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
7436 // MSA control register names
7437 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
7438 "$msarequest", "$msamap", "$msaunmap"
7440 return llvm::makeArrayRef(GCCRegNames);
7442 bool validateAsmConstraint(const char *&Name,
7443 TargetInfo::ConstraintInfo &Info) const override {
7447 case 'r': // CPU registers.
7448 case 'd': // Equivalent to "r" unless generating MIPS16 code.
7449 case 'y': // Equivalent to "r", backward compatibility only.
7450 case 'f': // floating-point registers.
7451 case 'c': // $25 for indirect jumps
7452 case 'l': // lo register
7453 case 'x': // hilo register pair
7454 Info.setAllowsRegister();
7456 case 'I': // Signed 16-bit constant
7457 case 'J': // Integer 0
7458 case 'K': // Unsigned 16-bit constant
7459 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
7460 case 'M': // Constants not loadable via lui, addiu, or ori
7461 case 'N': // Constant -1 to -65535
7462 case 'O': // A signed 15-bit constant
7463 case 'P': // A constant between 1 go 65535
7465 case 'R': // An address that can be used in a non-macro load or store
7466 Info.setAllowsMemory();
7469 if (Name[1] == 'C') { // An address usable by ll, and sc.
7470 Info.setAllowsMemory();
7471 Name++; // Skip over 'Z'.
7478 std::string convertConstraint(const char *&Constraint) const override {
7480 switch (*Constraint) {
7481 case 'Z': // Two-character constraint; add "^" hint for later parsing.
7482 if (Constraint[1] == 'C') {
7483 R = std::string("^") + std::string(Constraint, 2);
7489 return TargetInfo::convertConstraint(Constraint);
7492 const char *getClobbers() const override {
7493 // In GCC, $1 is not widely used in generated code (it's used only in a few
7494 // specific situations), so there is no real need for users to add it to
7495 // the clobbers list if they want to use it in their inline assembly code.
7497 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
7498 // code generation, so using it in inline assembly without adding it to the
7499 // clobbers list can cause conflicts between the inline assembly code and
7500 // the surrounding generated code.
7502 // Another problem is that LLVM is allowed to choose $1 for inline assembly
7503 // operands, which will conflict with the ".set at" assembler option (which
7504 // we use only for inline assembly, in order to maintain compatibility with
7505 // GCC) and will also conflict with the user's usage of $1.
7507 // The easiest way to avoid these conflicts and keep $1 as an allocatable
7508 // register for generated code is to automatically clobber $1 for all inline
7511 // FIXME: We should automatically clobber $1 only for inline assembly code
7512 // which actually uses it. This would allow LLVM to use $1 for inline
7513 // assembly operands if the user's assembly code doesn't use it.
7517 bool handleTargetFeatures(std::vector<std::string> &Features,
7518 DiagnosticsEngine &Diags) override {
7520 IsMicromips = false;
7521 IsNan2008 = isNaN2008Default();
7522 IsSingleFloat = false;
7523 FloatABI = HardFloat;
7525 HasFP64 = isFP64Default();
7527 for (const auto &Feature : Features) {
7528 if (Feature == "+single-float")
7529 IsSingleFloat = true;
7530 else if (Feature == "+soft-float")
7531 FloatABI = SoftFloat;
7532 else if (Feature == "+mips16")
7534 else if (Feature == "+micromips")
7536 else if (Feature == "+dsp")
7537 DspRev = std::max(DspRev, DSP1);
7538 else if (Feature == "+dspr2")
7539 DspRev = std::max(DspRev, DSP2);
7540 else if (Feature == "+msa")
7542 else if (Feature == "+fp64")
7544 else if (Feature == "-fp64")
7546 else if (Feature == "+nan2008")
7548 else if (Feature == "-nan2008")
7557 int getEHDataRegisterNumber(unsigned RegNo) const override {
7558 if (RegNo == 0) return 4;
7559 if (RegNo == 1) return 5;
7563 bool isCLZForZeroUndef() const override { return false; }
7565 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7566 static const TargetInfo::GCCRegAlias O32RegAliases[] = {
7567 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
7568 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
7569 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"},
7570 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"},
7571 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"},
7572 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
7573 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
7574 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
7575 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
7576 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
7578 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = {
7579 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
7580 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
7581 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"},
7582 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"},
7583 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"},
7584 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
7585 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
7586 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
7587 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
7588 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
7591 return llvm::makeArrayRef(O32RegAliases);
7592 return llvm::makeArrayRef(NewABIRegAliases);
7595 bool hasInt128Type() const override {
7596 return ABI == "n32" || ABI == "n64";
7599 bool validateTarget(DiagnosticsEngine &Diags) const override {
7600 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle
7601 // this yet. It's better to fail here than on the backend assertion.
7602 if (processorSupportsGPR64() && ABI == "o32") {
7603 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
7607 // 64-bit ABI's require 64-bit CPU's.
7608 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) {
7609 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
7613 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend
7614 // can't handle this yet. It's better to fail here than on the
7615 // backend assertion.
7616 if ((getTriple().getArch() == llvm::Triple::mips64 ||
7617 getTriple().getArch() == llvm::Triple::mips64el) &&
7619 Diags.Report(diag::err_target_unsupported_abi_for_triple)
7620 << ABI << getTriple().str();
7624 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend
7625 // can't handle this yet. It's better to fail here than on the
7626 // backend assertion.
7627 if ((getTriple().getArch() == llvm::Triple::mips ||
7628 getTriple().getArch() == llvm::Triple::mipsel) &&
7629 (ABI == "n32" || ABI == "n64")) {
7630 Diags.Report(diag::err_target_unsupported_abi_for_triple)
7631 << ABI << getTriple().str();
7639 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = {
7640 #define BUILTIN(ID, TYPE, ATTRS) \
7641 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7642 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
7643 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
7644 #include "clang/Basic/BuiltinsMips.def"
7647 class PNaClTargetInfo : public TargetInfo {
7649 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7650 : TargetInfo(Triple) {
7652 this->LongAlign = 32;
7653 this->LongWidth = 32;
7654 this->PointerAlign = 32;
7655 this->PointerWidth = 32;
7656 this->IntMaxType = TargetInfo::SignedLongLong;
7657 this->Int64Type = TargetInfo::SignedLongLong;
7658 this->DoubleAlign = 64;
7659 this->LongDoubleWidth = 64;
7660 this->LongDoubleAlign = 64;
7661 this->SizeType = TargetInfo::UnsignedInt;
7662 this->PtrDiffType = TargetInfo::SignedInt;
7663 this->IntPtrType = TargetInfo::SignedInt;
7664 this->RegParmMax = 0; // Disallow regparm
7667 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
7668 Builder.defineMacro("__le32__");
7669 Builder.defineMacro("__pnacl__");
7671 void getTargetDefines(const LangOptions &Opts,
7672 MacroBuilder &Builder) const override {
7673 getArchDefines(Opts, Builder);
7675 bool hasFeature(StringRef Feature) const override {
7676 return Feature == "pnacl";
7678 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7679 BuiltinVaListKind getBuiltinVaListKind() const override {
7680 return TargetInfo::PNaClABIBuiltinVaList;
7682 ArrayRef<const char *> getGCCRegNames() const override;
7683 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
7684 bool validateAsmConstraint(const char *&Name,
7685 TargetInfo::ConstraintInfo &Info) const override {
7689 const char *getClobbers() const override {
7694 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const {
7698 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const {
7702 // We attempt to use PNaCl (le32) frontend and Mips32EL backend.
7703 class NaClMips32TargetInfo : public MipsTargetInfo {
7705 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7706 : MipsTargetInfo(Triple, Opts) {}
7708 BuiltinVaListKind getBuiltinVaListKind() const override {
7709 return TargetInfo::PNaClABIBuiltinVaList;
7713 class Le64TargetInfo : public TargetInfo {
7714 static const Builtin::Info BuiltinInfo[];
7717 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7718 : TargetInfo(Triple) {
7720 NoAsmVariants = true;
7721 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7722 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7723 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128");
7726 void getTargetDefines(const LangOptions &Opts,
7727 MacroBuilder &Builder) const override {
7728 DefineStd(Builder, "unix", Opts);
7729 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
7730 Builder.defineMacro("__ELF__");
7732 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7733 return llvm::makeArrayRef(BuiltinInfo,
7734 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin);
7736 BuiltinVaListKind getBuiltinVaListKind() const override {
7737 return TargetInfo::PNaClABIBuiltinVaList;
7739 const char *getClobbers() const override { return ""; }
7740 ArrayRef<const char *> getGCCRegNames() const override {
7743 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7746 bool validateAsmConstraint(const char *&Name,
7747 TargetInfo::ConstraintInfo &Info) const override {
7751 bool hasProtectedVisibility() const override { return false; }
7754 class WebAssemblyTargetInfo : public TargetInfo {
7755 static const Builtin::Info BuiltinInfo[];
7763 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &)
7764 : TargetInfo(T), SIMDLevel(NoSIMD) {
7766 NoAsmVariants = true;
7767 SuitableAlign = 128;
7768 LargeArrayMinWidth = 128;
7769 LargeArrayAlign = 128;
7770 SimdDefaultAlign = 128;
7771 SigAtomicType = SignedLong;
7772 LongDoubleWidth = LongDoubleAlign = 128;
7773 LongDoubleFormat = &llvm::APFloat::IEEEquad;
7777 void getTargetDefines(const LangOptions &Opts,
7778 MacroBuilder &Builder) const override {
7779 defineCPUMacros(Builder, "wasm", /*Tuning=*/false);
7780 if (SIMDLevel >= SIMD128)
7781 Builder.defineMacro("__wasm_simd128__");
7786 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7788 const std::vector<std::string> &FeaturesVec) const override {
7789 if (CPU == "bleeding-edge")
7790 Features["simd128"] = true;
7791 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7793 bool hasFeature(StringRef Feature) const final {
7794 return llvm::StringSwitch<bool>(Feature)
7795 .Case("simd128", SIMDLevel >= SIMD128)
7798 bool handleTargetFeatures(std::vector<std::string> &Features,
7799 DiagnosticsEngine &Diags) final {
7800 for (const auto &Feature : Features) {
7801 if (Feature == "+simd128") {
7802 SIMDLevel = std::max(SIMDLevel, SIMD128);
7805 if (Feature == "-simd128") {
7806 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1));
7810 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature
7811 << "-target-feature";
7816 bool setCPU(const std::string &Name) final {
7817 return llvm::StringSwitch<bool>(Name)
7819 .Case("bleeding-edge", true)
7820 .Case("generic", true)
7823 ArrayRef<Builtin::Info> getTargetBuiltins() const final {
7824 return llvm::makeArrayRef(BuiltinInfo,
7825 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin);
7827 BuiltinVaListKind getBuiltinVaListKind() const final {
7828 return VoidPtrBuiltinVaList;
7830 ArrayRef<const char *> getGCCRegNames() const final {
7833 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final {
7837 validateAsmConstraint(const char *&Name,
7838 TargetInfo::ConstraintInfo &Info) const final {
7841 const char *getClobbers() const final { return ""; }
7842 bool isCLZForZeroUndef() const final { return false; }
7843 bool hasInt128Type() const final { return true; }
7844 IntType getIntTypeByWidth(unsigned BitWidth,
7845 bool IsSigned) const final {
7846 // WebAssembly prefers long long for explicitly 64-bit integers.
7847 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
7848 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
7850 IntType getLeastIntTypeByWidth(unsigned BitWidth,
7851 bool IsSigned) const final {
7852 // WebAssembly uses long long for int_least64_t and int_fast64_t.
7853 return BitWidth == 64
7854 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
7855 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
7859 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = {
7860 #define BUILTIN(ID, TYPE, ATTRS) \
7861 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7862 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
7863 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
7864 #include "clang/Basic/BuiltinsWebAssembly.def"
7867 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo {
7869 explicit WebAssembly32TargetInfo(const llvm::Triple &T,
7870 const TargetOptions &Opts)
7871 : WebAssemblyTargetInfo(T, Opts) {
7872 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
7873 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128");
7877 void getTargetDefines(const LangOptions &Opts,
7878 MacroBuilder &Builder) const override {
7879 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
7880 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false);
7884 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo {
7886 explicit WebAssembly64TargetInfo(const llvm::Triple &T,
7887 const TargetOptions &Opts)
7888 : WebAssemblyTargetInfo(T, Opts) {
7889 LongAlign = LongWidth = 64;
7890 PointerAlign = PointerWidth = 64;
7891 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7892 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
7896 void getTargetDefines(const LangOptions &Opts,
7897 MacroBuilder &Builder) const override {
7898 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
7899 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false);
7903 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
7904 #define BUILTIN(ID, TYPE, ATTRS) \
7905 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7906 #include "clang/Basic/BuiltinsLe64.def"
7909 static const unsigned SPIRAddrSpaceMap[] = {
7912 2, // opencl_constant
7913 4, // opencl_generic
7918 class SPIRTargetInfo : public TargetInfo {
7920 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7921 : TargetInfo(Triple) {
7922 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
7923 "SPIR target must use unknown OS");
7924 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
7925 "SPIR target must use unknown environment type");
7927 TLSSupported = false;
7928 LongWidth = LongAlign = 64;
7929 AddrSpaceMap = &SPIRAddrSpaceMap;
7930 UseAddrSpaceMapMangling = true;
7931 // Define available target features
7932 // These must be defined in sorted order!
7933 NoAsmVariants = true;
7935 void getTargetDefines(const LangOptions &Opts,
7936 MacroBuilder &Builder) const override {
7937 DefineStd(Builder, "SPIR", Opts);
7939 bool hasFeature(StringRef Feature) const override {
7940 return Feature == "spir";
7943 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7944 const char *getClobbers() const override { return ""; }
7945 ArrayRef<const char *> getGCCRegNames() const override { return None; }
7946 bool validateAsmConstraint(const char *&Name,
7947 TargetInfo::ConstraintInfo &info) const override {
7950 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7953 BuiltinVaListKind getBuiltinVaListKind() const override {
7954 return TargetInfo::VoidPtrBuiltinVaList;
7957 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
7958 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK
7962 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
7963 return CC_SpirFunction;
7966 void setSupportedOpenCLOpts() override {
7967 // Assume all OpenCL extensions and optional core features are supported
7968 // for SPIR since it is a generic target.
7969 getSupportedOpenCLOpts().setAll();
7973 class SPIR32TargetInfo : public SPIRTargetInfo {
7975 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7976 : SPIRTargetInfo(Triple, Opts) {
7977 PointerWidth = PointerAlign = 32;
7978 SizeType = TargetInfo::UnsignedInt;
7979 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
7980 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
7981 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
7983 void getTargetDefines(const LangOptions &Opts,
7984 MacroBuilder &Builder) const override {
7985 DefineStd(Builder, "SPIR32", Opts);
7989 class SPIR64TargetInfo : public SPIRTargetInfo {
7991 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7992 : SPIRTargetInfo(Triple, Opts) {
7993 PointerWidth = PointerAlign = 64;
7994 SizeType = TargetInfo::UnsignedLong;
7995 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
7996 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
7997 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
7999 void getTargetDefines(const LangOptions &Opts,
8000 MacroBuilder &Builder) const override {
8001 DefineStd(Builder, "SPIR64", Opts);
8005 class XCoreTargetInfo : public TargetInfo {
8006 static const Builtin::Info BuiltinInfo[];
8008 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8009 : TargetInfo(Triple) {
8011 NoAsmVariants = true;
8014 DoubleAlign = LongDoubleAlign = 32;
8015 SizeType = UnsignedInt;
8016 PtrDiffType = SignedInt;
8017 IntPtrType = SignedInt;
8018 WCharType = UnsignedChar;
8019 WIntType = UnsignedInt;
8020 UseZeroLengthBitfieldAlignment = true;
8021 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
8022 "-f64:32-a:0:32-n32");
8024 void getTargetDefines(const LangOptions &Opts,
8025 MacroBuilder &Builder) const override {
8026 Builder.defineMacro("__XS1B__");
8028 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8029 return llvm::makeArrayRef(BuiltinInfo,
8030 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin);
8032 BuiltinVaListKind getBuiltinVaListKind() const override {
8033 return TargetInfo::VoidPtrBuiltinVaList;
8035 const char *getClobbers() const override {
8038 ArrayRef<const char *> getGCCRegNames() const override {
8039 static const char * const GCCRegNames[] = {
8040 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8041 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
8043 return llvm::makeArrayRef(GCCRegNames);
8045 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8048 bool validateAsmConstraint(const char *&Name,
8049 TargetInfo::ConstraintInfo &Info) const override {
8052 int getEHDataRegisterNumber(unsigned RegNo) const override {
8053 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
8054 return (RegNo < 2)? RegNo : -1;
8056 bool allowsLargerPreferedTypeAlignment() const override {
8061 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
8062 #define BUILTIN(ID, TYPE, ATTRS) \
8063 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8064 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8065 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8066 #include "clang/Basic/BuiltinsXCore.def"
8069 // x86_32 Android target
8070 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
8072 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8073 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) {
8075 LongDoubleWidth = 64;
8076 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
8080 // x86_64 Android target
8081 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
8083 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8084 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) {
8085 LongDoubleFormat = &llvm::APFloat::IEEEquad;
8088 bool useFloat128ManglingForLongDouble() const override {
8093 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes
8094 class RenderScript32TargetInfo : public ARMleTargetInfo {
8096 RenderScript32TargetInfo(const llvm::Triple &Triple,
8097 const TargetOptions &Opts)
8098 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(),
8100 Triple.getEnvironmentName()),
8102 LongWidth = LongAlign = 64;
8104 void getTargetDefines(const LangOptions &Opts,
8105 MacroBuilder &Builder) const override {
8106 Builder.defineMacro("__RENDERSCRIPT__");
8107 ARMleTargetInfo::getTargetDefines(Opts, Builder);
8111 // 64-bit RenderScript is aarch64
8112 class RenderScript64TargetInfo : public AArch64leTargetInfo {
8114 RenderScript64TargetInfo(const llvm::Triple &Triple,
8115 const TargetOptions &Opts)
8116 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(),
8118 Triple.getEnvironmentName()),
8121 void getTargetDefines(const LangOptions &Opts,
8122 MacroBuilder &Builder) const override {
8123 Builder.defineMacro("__RENDERSCRIPT__");
8124 AArch64leTargetInfo::getTargetDefines(Opts, Builder);
8128 } // end anonymous namespace
8130 //===----------------------------------------------------------------------===//
8132 //===----------------------------------------------------------------------===//
8134 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
8135 const TargetOptions &Opts) {
8136 llvm::Triple::OSType os = Triple.getOS();
8138 switch (Triple.getArch()) {
8142 case llvm::Triple::xcore:
8143 return new XCoreTargetInfo(Triple, Opts);
8145 case llvm::Triple::hexagon:
8146 return new HexagonTargetInfo(Triple, Opts);
8148 case llvm::Triple::lanai:
8149 return new LanaiTargetInfo(Triple, Opts);
8151 case llvm::Triple::aarch64:
8152 if (Triple.isOSDarwin())
8153 return new DarwinAArch64TargetInfo(Triple, Opts);
8156 case llvm::Triple::CloudABI:
8157 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts);
8158 case llvm::Triple::FreeBSD:
8159 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
8160 case llvm::Triple::Linux:
8161 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts);
8162 case llvm::Triple::NetBSD:
8163 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
8165 return new AArch64leTargetInfo(Triple, Opts);
8168 case llvm::Triple::aarch64_be:
8170 case llvm::Triple::FreeBSD:
8171 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
8172 case llvm::Triple::Linux:
8173 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts);
8174 case llvm::Triple::NetBSD:
8175 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
8177 return new AArch64beTargetInfo(Triple, Opts);
8180 case llvm::Triple::arm:
8181 case llvm::Triple::thumb:
8182 if (Triple.isOSBinFormatMachO())
8183 return new DarwinARMTargetInfo(Triple, Opts);
8186 case llvm::Triple::CloudABI:
8187 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts);
8188 case llvm::Triple::Linux:
8189 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts);
8190 case llvm::Triple::FreeBSD:
8191 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
8192 case llvm::Triple::NetBSD:
8193 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
8194 case llvm::Triple::OpenBSD:
8195 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
8196 case llvm::Triple::Bitrig:
8197 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts);
8198 case llvm::Triple::RTEMS:
8199 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts);
8200 case llvm::Triple::NaCl:
8201 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts);
8202 case llvm::Triple::Win32:
8203 switch (Triple.getEnvironment()) {
8204 case llvm::Triple::Cygnus:
8205 return new CygwinARMTargetInfo(Triple, Opts);
8206 case llvm::Triple::GNU:
8207 return new MinGWARMTargetInfo(Triple, Opts);
8208 case llvm::Triple::Itanium:
8209 return new ItaniumWindowsARMleTargetInfo(Triple, Opts);
8210 case llvm::Triple::MSVC:
8211 default: // Assume MSVC for unknown environments
8212 return new MicrosoftARMleTargetInfo(Triple, Opts);
8215 return new ARMleTargetInfo(Triple, Opts);
8218 case llvm::Triple::armeb:
8219 case llvm::Triple::thumbeb:
8220 if (Triple.isOSDarwin())
8221 return new DarwinARMTargetInfo(Triple, Opts);
8224 case llvm::Triple::Linux:
8225 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8226 case llvm::Triple::FreeBSD:
8227 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8228 case llvm::Triple::NetBSD:
8229 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8230 case llvm::Triple::OpenBSD:
8231 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8232 case llvm::Triple::Bitrig:
8233 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8234 case llvm::Triple::RTEMS:
8235 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8236 case llvm::Triple::NaCl:
8237 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts);
8239 return new ARMbeTargetInfo(Triple, Opts);
8242 case llvm::Triple::bpfeb:
8243 case llvm::Triple::bpfel:
8244 return new BPFTargetInfo(Triple, Opts);
8246 case llvm::Triple::msp430:
8247 return new MSP430TargetInfo(Triple, Opts);
8249 case llvm::Triple::mips:
8251 case llvm::Triple::Linux:
8252 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
8253 case llvm::Triple::RTEMS:
8254 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
8255 case llvm::Triple::FreeBSD:
8256 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8257 case llvm::Triple::NetBSD:
8258 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8260 return new MipsTargetInfo(Triple, Opts);
8263 case llvm::Triple::mipsel:
8265 case llvm::Triple::Linux:
8266 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
8267 case llvm::Triple::RTEMS:
8268 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
8269 case llvm::Triple::FreeBSD:
8270 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8271 case llvm::Triple::NetBSD:
8272 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8273 case llvm::Triple::NaCl:
8274 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts);
8276 return new MipsTargetInfo(Triple, Opts);
8279 case llvm::Triple::mips64:
8281 case llvm::Triple::Linux:
8282 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
8283 case llvm::Triple::RTEMS:
8284 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
8285 case llvm::Triple::FreeBSD:
8286 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8287 case llvm::Triple::NetBSD:
8288 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8289 case llvm::Triple::OpenBSD:
8290 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8292 return new MipsTargetInfo(Triple, Opts);
8295 case llvm::Triple::mips64el:
8297 case llvm::Triple::Linux:
8298 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
8299 case llvm::Triple::RTEMS:
8300 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
8301 case llvm::Triple::FreeBSD:
8302 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8303 case llvm::Triple::NetBSD:
8304 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8305 case llvm::Triple::OpenBSD:
8306 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
8308 return new MipsTargetInfo(Triple, Opts);
8311 case llvm::Triple::le32:
8313 case llvm::Triple::NaCl:
8314 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts);
8319 case llvm::Triple::le64:
8320 return new Le64TargetInfo(Triple, Opts);
8322 case llvm::Triple::ppc:
8323 if (Triple.isOSDarwin())
8324 return new DarwinPPC32TargetInfo(Triple, Opts);
8326 case llvm::Triple::Linux:
8327 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts);
8328 case llvm::Triple::FreeBSD:
8329 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
8330 case llvm::Triple::NetBSD:
8331 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
8332 case llvm::Triple::OpenBSD:
8333 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
8334 case llvm::Triple::RTEMS:
8335 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts);
8337 return new PPC32TargetInfo(Triple, Opts);
8340 case llvm::Triple::ppc64:
8341 if (Triple.isOSDarwin())
8342 return new DarwinPPC64TargetInfo(Triple, Opts);
8344 case llvm::Triple::Linux:
8345 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
8346 case llvm::Triple::Lv2:
8347 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts);
8348 case llvm::Triple::FreeBSD:
8349 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
8350 case llvm::Triple::NetBSD:
8351 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
8353 return new PPC64TargetInfo(Triple, Opts);
8356 case llvm::Triple::ppc64le:
8358 case llvm::Triple::Linux:
8359 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
8360 case llvm::Triple::NetBSD:
8361 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
8363 return new PPC64TargetInfo(Triple, Opts);
8366 case llvm::Triple::nvptx:
8367 return new NVPTX32TargetInfo(Triple, Opts);
8368 case llvm::Triple::nvptx64:
8369 return new NVPTX64TargetInfo(Triple, Opts);
8371 case llvm::Triple::amdgcn:
8372 case llvm::Triple::r600:
8373 return new AMDGPUTargetInfo(Triple, Opts);
8375 case llvm::Triple::sparc:
8377 case llvm::Triple::Linux:
8378 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8379 case llvm::Triple::Solaris:
8380 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8381 case llvm::Triple::NetBSD:
8382 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8383 case llvm::Triple::OpenBSD:
8384 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8385 case llvm::Triple::RTEMS:
8386 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts);
8388 return new SparcV8TargetInfo(Triple, Opts);
8391 // The 'sparcel' architecture copies all the above cases except for Solaris.
8392 case llvm::Triple::sparcel:
8394 case llvm::Triple::Linux:
8395 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
8396 case llvm::Triple::NetBSD:
8397 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
8398 case llvm::Triple::OpenBSD:
8399 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
8400 case llvm::Triple::RTEMS:
8401 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
8403 return new SparcV8elTargetInfo(Triple, Opts);
8406 case llvm::Triple::sparcv9:
8408 case llvm::Triple::Linux:
8409 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8410 case llvm::Triple::Solaris:
8411 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8412 case llvm::Triple::NetBSD:
8413 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8414 case llvm::Triple::OpenBSD:
8415 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8416 case llvm::Triple::FreeBSD:
8417 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
8419 return new SparcV9TargetInfo(Triple, Opts);
8422 case llvm::Triple::systemz:
8424 case llvm::Triple::Linux:
8425 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts);
8427 return new SystemZTargetInfo(Triple, Opts);
8430 case llvm::Triple::tce:
8431 return new TCETargetInfo(Triple, Opts);
8433 case llvm::Triple::x86:
8434 if (Triple.isOSDarwin())
8435 return new DarwinI386TargetInfo(Triple, Opts);
8438 case llvm::Triple::CloudABI:
8439 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts);
8440 case llvm::Triple::Linux: {
8441 switch (Triple.getEnvironment()) {
8443 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts);
8444 case llvm::Triple::Android:
8445 return new AndroidX86_32TargetInfo(Triple, Opts);
8448 case llvm::Triple::DragonFly:
8449 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
8450 case llvm::Triple::NetBSD:
8451 return new NetBSDI386TargetInfo(Triple, Opts);
8452 case llvm::Triple::OpenBSD:
8453 return new OpenBSDI386TargetInfo(Triple, Opts);
8454 case llvm::Triple::Bitrig:
8455 return new BitrigI386TargetInfo(Triple, Opts);
8456 case llvm::Triple::FreeBSD:
8457 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
8458 case llvm::Triple::KFreeBSD:
8459 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
8460 case llvm::Triple::Minix:
8461 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts);
8462 case llvm::Triple::Solaris:
8463 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts);
8464 case llvm::Triple::Win32: {
8465 switch (Triple.getEnvironment()) {
8466 case llvm::Triple::Cygnus:
8467 return new CygwinX86_32TargetInfo(Triple, Opts);
8468 case llvm::Triple::GNU:
8469 return new MinGWX86_32TargetInfo(Triple, Opts);
8470 case llvm::Triple::Itanium:
8471 case llvm::Triple::MSVC:
8472 default: // Assume MSVC for unknown environments
8473 return new MicrosoftX86_32TargetInfo(Triple, Opts);
8476 case llvm::Triple::Haiku:
8477 return new HaikuX86_32TargetInfo(Triple, Opts);
8478 case llvm::Triple::RTEMS:
8479 return new RTEMSX86_32TargetInfo(Triple, Opts);
8480 case llvm::Triple::NaCl:
8481 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts);
8482 case llvm::Triple::ELFIAMCU:
8483 return new MCUX86_32TargetInfo(Triple, Opts);
8485 return new X86_32TargetInfo(Triple, Opts);
8488 case llvm::Triple::x86_64:
8489 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
8490 return new DarwinX86_64TargetInfo(Triple, Opts);
8493 case llvm::Triple::CloudABI:
8494 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts);
8495 case llvm::Triple::Linux: {
8496 switch (Triple.getEnvironment()) {
8498 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts);
8499 case llvm::Triple::Android:
8500 return new AndroidX86_64TargetInfo(Triple, Opts);
8503 case llvm::Triple::DragonFly:
8504 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
8505 case llvm::Triple::NetBSD:
8506 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
8507 case llvm::Triple::OpenBSD:
8508 return new OpenBSDX86_64TargetInfo(Triple, Opts);
8509 case llvm::Triple::Bitrig:
8510 return new BitrigX86_64TargetInfo(Triple, Opts);
8511 case llvm::Triple::FreeBSD:
8512 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
8513 case llvm::Triple::KFreeBSD:
8514 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
8515 case llvm::Triple::Solaris:
8516 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts);
8517 case llvm::Triple::Win32: {
8518 switch (Triple.getEnvironment()) {
8519 case llvm::Triple::Cygnus:
8520 return new CygwinX86_64TargetInfo(Triple, Opts);
8521 case llvm::Triple::GNU:
8522 return new MinGWX86_64TargetInfo(Triple, Opts);
8523 case llvm::Triple::MSVC:
8524 default: // Assume MSVC for unknown environments
8525 return new MicrosoftX86_64TargetInfo(Triple, Opts);
8528 case llvm::Triple::Haiku:
8529 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts);
8530 case llvm::Triple::NaCl:
8531 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts);
8532 case llvm::Triple::PS4:
8533 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts);
8535 return new X86_64TargetInfo(Triple, Opts);
8538 case llvm::Triple::spir: {
8539 if (Triple.getOS() != llvm::Triple::UnknownOS ||
8540 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
8542 return new SPIR32TargetInfo(Triple, Opts);
8544 case llvm::Triple::spir64: {
8545 if (Triple.getOS() != llvm::Triple::UnknownOS ||
8546 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
8548 return new SPIR64TargetInfo(Triple, Opts);
8550 case llvm::Triple::wasm32:
8551 if (!(Triple == llvm::Triple("wasm32-unknown-unknown")))
8553 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts);
8554 case llvm::Triple::wasm64:
8555 if (!(Triple == llvm::Triple("wasm64-unknown-unknown")))
8557 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts);
8559 case llvm::Triple::renderscript32:
8560 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts);
8561 case llvm::Triple::renderscript64:
8562 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts);
8566 /// CreateTargetInfo - Return the target info object for the specified target
8569 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
8570 const std::shared_ptr<TargetOptions> &Opts) {
8571 llvm::Triple Triple(Opts->Triple);
8573 // Construct the target
8574 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts));
8576 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
8579 Target->TargetOpts = Opts;
8581 // Set the target CPU if specified.
8582 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
8583 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
8587 // Set the target ABI if specified.
8588 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
8589 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
8593 // Set the fp math unit.
8594 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
8595 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
8599 // Compute the default target features, we need the target to handle this
8600 // because features may have dependencies on one another.
8601 llvm::StringMap<bool> Features;
8602 if (!Target->initFeatureMap(Features, Diags, Opts->CPU,
8603 Opts->FeaturesAsWritten))
8606 // Add the features to the compile options.
8607 Opts->Features.clear();
8608 for (const auto &F : Features)
8609 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str());
8611 if (!Target->handleTargetFeatures(Opts->Features, Diags))
8614 Target->setSupportedOpenCLOpts();
8616 if (!Target->validateTarget(Diags))
8619 return Target.release();