1 //===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // These classes wrap the information about a call or function
11 // definition used to handle ABI compliancy.
13 //===----------------------------------------------------------------------===//
15 #include "TargetInfo.h"
19 #include "CodeGenFunction.h"
20 #include "clang/AST/RecordLayout.h"
21 #include "clang/CodeGen/CGFunctionInfo.h"
22 #include "clang/Frontend/CodeGenOptions.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/ADT/Triple.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/Type.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include <algorithm> // std::sort
30 using namespace clang;
31 using namespace CodeGen;
33 static void AssignToArrayRange(CodeGen::CGBuilderTy &Builder,
38 // Alternatively, we could emit this as a loop in the source.
39 for (unsigned I = FirstIndex; I <= LastIndex; ++I) {
41 Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I);
42 Builder.CreateStore(Value, Cell);
46 static bool isAggregateTypeForABI(QualType T) {
47 return !CodeGenFunction::hasScalarEvaluationKind(T) ||
48 T->isMemberFunctionPointerType();
51 ABIInfo::~ABIInfo() {}
53 static CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT,
55 const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl());
57 return CGCXXABI::RAA_Default;
58 return CXXABI.getRecordArgABI(RD);
61 static CGCXXABI::RecordArgABI getRecordArgABI(QualType T,
63 const RecordType *RT = T->getAs<RecordType>();
65 return CGCXXABI::RAA_Default;
66 return getRecordArgABI(RT, CXXABI);
69 /// Pass transparent unions as if they were the type of the first element. Sema
70 /// should ensure that all elements of the union have the same "machine type".
71 static QualType useFirstFieldIfTransparentUnion(QualType Ty) {
72 if (const RecordType *UT = Ty->getAsUnionType()) {
73 const RecordDecl *UD = UT->getDecl();
74 if (UD->hasAttr<TransparentUnionAttr>()) {
75 assert(!UD->field_empty() && "sema created an empty transparent union");
76 return UD->field_begin()->getType();
82 CGCXXABI &ABIInfo::getCXXABI() const {
83 return CGT.getCXXABI();
86 ASTContext &ABIInfo::getContext() const {
87 return CGT.getContext();
90 llvm::LLVMContext &ABIInfo::getVMContext() const {
91 return CGT.getLLVMContext();
94 const llvm::DataLayout &ABIInfo::getDataLayout() const {
95 return CGT.getDataLayout();
98 const TargetInfo &ABIInfo::getTarget() const {
99 return CGT.getTarget();
102 bool ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
106 bool ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
107 uint64_t Members) const {
111 bool ABIInfo::shouldSignExtUnsignedType(QualType Ty) const {
115 void ABIArgInfo::dump() const {
116 raw_ostream &OS = llvm::errs();
117 OS << "(ABIArgInfo Kind=";
120 OS << "Direct Type=";
121 if (llvm::Type *Ty = getCoerceToType())
133 OS << "InAlloca Offset=" << getInAllocaFieldIndex();
136 OS << "Indirect Align=" << getIndirectAlign()
137 << " ByVal=" << getIndirectByVal()
138 << " Realign=" << getIndirectRealign();
147 TargetCodeGenInfo::~TargetCodeGenInfo() { delete Info; }
149 // If someone can figure out a general rule for this, that would be great.
150 // It's probably just doomed to be platform-dependent, though.
151 unsigned TargetCodeGenInfo::getSizeOfUnwindException() const {
153 // x86-64 FreeBSD, Linux, Darwin
154 // x86-32 FreeBSD, Linux, Darwin
155 // PowerPC Linux, Darwin
156 // ARM Darwin (*not* EABI)
161 bool TargetCodeGenInfo::isNoProtoCallVariadic(const CallArgList &args,
162 const FunctionNoProtoType *fnType) const {
163 // The following conventions are known to require this to be false:
166 // For everything else, we just prefer false unless we opt out.
171 TargetCodeGenInfo::getDependentLibraryOption(llvm::StringRef Lib,
172 llvm::SmallString<24> &Opt) const {
173 // This assumes the user is passing a library name like "rt" instead of a
174 // filename like "librt.a/so", and that they don't care whether it's static or
180 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays);
182 /// isEmptyField - Return true iff a the field is "empty", that is it
183 /// is an unnamed bit-field or an (array of) empty record(s).
184 static bool isEmptyField(ASTContext &Context, const FieldDecl *FD,
186 if (FD->isUnnamedBitfield())
189 QualType FT = FD->getType();
191 // Constant arrays of empty records count as empty, strip them off.
192 // Constant arrays of zero length always count as empty.
194 while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
195 if (AT->getSize() == 0)
197 FT = AT->getElementType();
200 const RecordType *RT = FT->getAs<RecordType>();
204 // C++ record fields are never empty, at least in the Itanium ABI.
206 // FIXME: We should use a predicate for whether this behavior is true in the
208 if (isa<CXXRecordDecl>(RT->getDecl()))
211 return isEmptyRecord(Context, FT, AllowArrays);
214 /// isEmptyRecord - Return true iff a structure contains only empty
215 /// fields. Note that a structure with a flexible array member is not
216 /// considered empty.
217 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) {
218 const RecordType *RT = T->getAs<RecordType>();
221 const RecordDecl *RD = RT->getDecl();
222 if (RD->hasFlexibleArrayMember())
225 // If this is a C++ record, check the bases first.
226 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
227 for (const auto &I : CXXRD->bases())
228 if (!isEmptyRecord(Context, I.getType(), true))
231 for (const auto *I : RD->fields())
232 if (!isEmptyField(Context, I, AllowArrays))
237 /// isSingleElementStruct - Determine if a structure is a "single
238 /// element struct", i.e. it has exactly one non-empty field or
239 /// exactly one field which is itself a single element
240 /// struct. Structures with flexible array members are never
241 /// considered single element structs.
243 /// \return The field declaration for the single non-empty field, if
245 static const Type *isSingleElementStruct(QualType T, ASTContext &Context) {
246 const RecordType *RT = T->getAs<RecordType>();
250 const RecordDecl *RD = RT->getDecl();
251 if (RD->hasFlexibleArrayMember())
254 const Type *Found = nullptr;
256 // If this is a C++ record, check the bases first.
257 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
258 for (const auto &I : CXXRD->bases()) {
259 // Ignore empty records.
260 if (isEmptyRecord(Context, I.getType(), true))
263 // If we already found an element then this isn't a single-element struct.
267 // If this is non-empty and not a single element struct, the composite
268 // cannot be a single element struct.
269 Found = isSingleElementStruct(I.getType(), Context);
275 // Check for single element.
276 for (const auto *FD : RD->fields()) {
277 QualType FT = FD->getType();
279 // Ignore empty fields.
280 if (isEmptyField(Context, FD, true))
283 // If we already found an element then this isn't a single-element
288 // Treat single element arrays as the element.
289 while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
290 if (AT->getSize().getZExtValue() != 1)
292 FT = AT->getElementType();
295 if (!isAggregateTypeForABI(FT)) {
296 Found = FT.getTypePtr();
298 Found = isSingleElementStruct(FT, Context);
304 // We don't consider a struct a single-element struct if it has
305 // padding beyond the element type.
306 if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T))
312 static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) {
313 // Treat complex types as the element type.
314 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
315 Ty = CTy->getElementType();
317 // Check for a type which we know has a simple scalar argument-passing
318 // convention without any padding. (We're specifically looking for 32
319 // and 64-bit integer and integer-equivalents, float, and double.)
320 if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() &&
321 !Ty->isEnumeralType() && !Ty->isBlockPointerType())
324 uint64_t Size = Context.getTypeSize(Ty);
325 return Size == 32 || Size == 64;
328 /// canExpandIndirectArgument - Test whether an argument type which is to be
329 /// passed indirectly (on the stack) would have the equivalent layout if it was
330 /// expanded into separate arguments. If so, we prefer to do the latter to avoid
331 /// inhibiting optimizations.
333 // FIXME: This predicate is missing many cases, currently it just follows
334 // llvm-gcc (checks that all fields are 32-bit or 64-bit primitive types). We
335 // should probably make this smarter, or better yet make the LLVM backend
336 // capable of handling it.
337 static bool canExpandIndirectArgument(QualType Ty, ASTContext &Context) {
338 // We can only expand structure types.
339 const RecordType *RT = Ty->getAs<RecordType>();
343 // We can only expand (C) structures.
345 // FIXME: This needs to be generalized to handle classes as well.
346 const RecordDecl *RD = RT->getDecl();
350 // We try to expand CLike CXXRecordDecl.
351 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
352 if (!CXXRD->isCLike())
358 for (const auto *FD : RD->fields()) {
359 if (!is32Or64BitBasicType(FD->getType(), Context))
362 // FIXME: Reject bit-fields wholesale; there are two problems, we don't know
363 // how to expand them yet, and the predicate for telling if a bitfield still
364 // counts as "basic" is more complicated than what we were doing previously.
365 if (FD->isBitField())
368 Size += Context.getTypeSize(FD->getType());
371 // Make sure there are not any holes in the struct.
372 if (Size != Context.getTypeSize(Ty))
379 /// DefaultABIInfo - The default implementation for ABI specific
380 /// details. This implementation provides information which results in
381 /// self-consistent and sensible LLVM IR generation, but does not
382 /// conform to any particular ABI.
383 class DefaultABIInfo : public ABIInfo {
385 DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
387 ABIArgInfo classifyReturnType(QualType RetTy) const;
388 ABIArgInfo classifyArgumentType(QualType RetTy) const;
390 void computeInfo(CGFunctionInfo &FI) const override {
391 if (!getCXXABI().classifyReturnType(FI))
392 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
393 for (auto &I : FI.arguments())
394 I.info = classifyArgumentType(I.type);
397 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
398 CodeGenFunction &CGF) const override;
401 class DefaultTargetCodeGenInfo : public TargetCodeGenInfo {
403 DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
404 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
407 llvm::Value *DefaultABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
408 CodeGenFunction &CGF) const {
412 ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty) const {
413 Ty = useFirstFieldIfTransparentUnion(Ty);
415 if (isAggregateTypeForABI(Ty)) {
416 // Records with non-trivial destructors/copy-constructors should not be
418 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
419 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
421 return ABIArgInfo::getIndirect(0);
424 // Treat an enum type as its underlying type.
425 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
426 Ty = EnumTy->getDecl()->getIntegerType();
428 return (Ty->isPromotableIntegerType() ?
429 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
432 ABIArgInfo DefaultABIInfo::classifyReturnType(QualType RetTy) const {
433 if (RetTy->isVoidType())
434 return ABIArgInfo::getIgnore();
436 if (isAggregateTypeForABI(RetTy))
437 return ABIArgInfo::getIndirect(0);
439 // Treat an enum type as its underlying type.
440 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
441 RetTy = EnumTy->getDecl()->getIntegerType();
443 return (RetTy->isPromotableIntegerType() ?
444 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
447 //===----------------------------------------------------------------------===//
448 // le32/PNaCl bitcode ABI Implementation
450 // This is a simplified version of the x86_32 ABI. Arguments and return values
451 // are always passed on the stack.
452 //===----------------------------------------------------------------------===//
454 class PNaClABIInfo : public ABIInfo {
456 PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
458 ABIArgInfo classifyReturnType(QualType RetTy) const;
459 ABIArgInfo classifyArgumentType(QualType RetTy) const;
461 void computeInfo(CGFunctionInfo &FI) const override;
462 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
463 CodeGenFunction &CGF) const override;
466 class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
468 PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
469 : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {}
472 void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
473 if (!getCXXABI().classifyReturnType(FI))
474 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
476 for (auto &I : FI.arguments())
477 I.info = classifyArgumentType(I.type);
480 llvm::Value *PNaClABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
481 CodeGenFunction &CGF) const {
485 /// \brief Classify argument of given type \p Ty.
486 ABIArgInfo PNaClABIInfo::classifyArgumentType(QualType Ty) const {
487 if (isAggregateTypeForABI(Ty)) {
488 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
489 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
490 return ABIArgInfo::getIndirect(0);
491 } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
492 // Treat an enum type as its underlying type.
493 Ty = EnumTy->getDecl()->getIntegerType();
494 } else if (Ty->isFloatingType()) {
495 // Floating-point types don't go inreg.
496 return ABIArgInfo::getDirect();
499 return (Ty->isPromotableIntegerType() ?
500 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
503 ABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const {
504 if (RetTy->isVoidType())
505 return ABIArgInfo::getIgnore();
507 // In the PNaCl ABI we always return records/structures on the stack.
508 if (isAggregateTypeForABI(RetTy))
509 return ABIArgInfo::getIndirect(0);
511 // Treat an enum type as its underlying type.
512 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
513 RetTy = EnumTy->getDecl()->getIntegerType();
515 return (RetTy->isPromotableIntegerType() ?
516 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
519 /// IsX86_MMXType - Return true if this is an MMX type.
520 bool IsX86_MMXType(llvm::Type *IRType) {
521 // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
522 return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
523 cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
524 IRType->getScalarSizeInBits() != 64;
527 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
528 StringRef Constraint,
530 if ((Constraint == "y" || Constraint == "&y") && Ty->isVectorTy()) {
531 if (cast<llvm::VectorType>(Ty)->getBitWidth() != 64) {
532 // Invalid MMX constraint
536 return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
539 // No operation needed
543 /// Returns true if this type can be passed in SSE registers with the
544 /// X86_VectorCall calling convention. Shared between x86_32 and x86_64.
545 static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) {
546 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
547 if (BT->isFloatingPoint() && BT->getKind() != BuiltinType::Half)
549 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
550 // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX
551 // registers specially.
552 unsigned VecSize = Context.getTypeSize(VT);
553 if (VecSize == 128 || VecSize == 256 || VecSize == 512)
559 /// Returns true if this aggregate is small enough to be passed in SSE registers
560 /// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64.
561 static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) {
562 return NumMembers <= 4;
565 //===----------------------------------------------------------------------===//
566 // X86-32 ABI Implementation
567 //===----------------------------------------------------------------------===//
569 /// \brief Similar to llvm::CCState, but for Clang.
571 CCState(unsigned CC) : CC(CC), FreeRegs(0), FreeSSERegs(0) {}
575 unsigned FreeSSERegs;
578 /// X86_32ABIInfo - The X86-32 ABI information.
579 class X86_32ABIInfo : public ABIInfo {
585 static const unsigned MinABIStackAlignInBytes = 4;
587 bool IsDarwinVectorABI;
588 bool IsSmallStructInRegABI;
589 bool IsWin32StructABI;
590 unsigned DefaultNumRegisterParameters;
592 static bool isRegisterSize(unsigned Size) {
593 return (Size == 8 || Size == 16 || Size == 32 || Size == 64);
596 bool isHomogeneousAggregateBaseType(QualType Ty) const override {
597 // FIXME: Assumes vectorcall is in use.
598 return isX86VectorTypeForVectorCall(getContext(), Ty);
601 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
602 uint64_t NumMembers) const override {
603 // FIXME: Assumes vectorcall is in use.
604 return isX86VectorCallAggregateSmallEnough(NumMembers);
607 bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const;
609 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
610 /// such that the argument will be passed in memory.
611 ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
613 ABIArgInfo getIndirectReturnResult(CCState &State) const;
615 /// \brief Return the alignment to use for the given type on the stack.
616 unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const;
618 Class classify(QualType Ty) const;
619 ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
620 ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
621 bool shouldUseInReg(QualType Ty, CCState &State, bool &NeedsPadding) const;
623 /// \brief Rewrite the function info so that all memory arguments use
625 void rewriteWithInAlloca(CGFunctionInfo &FI) const;
627 void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
628 unsigned &StackOffset, ABIArgInfo &Info,
629 QualType Type) const;
633 void computeInfo(CGFunctionInfo &FI) const override;
634 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
635 CodeGenFunction &CGF) const override;
637 X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool d, bool p, bool w,
639 : ABIInfo(CGT), IsDarwinVectorABI(d), IsSmallStructInRegABI(p),
640 IsWin32StructABI(w), DefaultNumRegisterParameters(r) {}
643 class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
645 X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
646 bool d, bool p, bool w, unsigned r)
647 :TargetCodeGenInfo(new X86_32ABIInfo(CGT, d, p, w, r)) {}
649 static bool isStructReturnInRegABI(
650 const llvm::Triple &Triple, const CodeGenOptions &Opts);
652 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
653 CodeGen::CodeGenModule &CGM) const override;
655 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
656 // Darwin uses different dwarf register numbers for EH.
657 if (CGM.getTarget().getTriple().isOSDarwin()) return 5;
661 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
662 llvm::Value *Address) const override;
664 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
665 StringRef Constraint,
666 llvm::Type* Ty) const override {
667 return X86AdjustInlineAsmType(CGF, Constraint, Ty);
670 void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue,
671 std::string &Constraints,
672 std::vector<llvm::Type *> &ResultRegTypes,
673 std::vector<llvm::Type *> &ResultTruncRegTypes,
674 std::vector<LValue> &ResultRegDests,
675 std::string &AsmString,
676 unsigned NumOutputs) const override;
679 getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
680 unsigned Sig = (0xeb << 0) | // jmp rel8
681 (0x06 << 8) | // .+0x08
684 return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
690 /// Rewrite input constraint references after adding some output constraints.
691 /// In the case where there is one output and one input and we add one output,
692 /// we need to replace all operand references greater than or equal to 1:
695 /// The result will be:
698 static void rewriteInputConstraintReferences(unsigned FirstIn,
700 std::string &AsmString) {
702 llvm::raw_string_ostream OS(Buf);
704 while (Pos < AsmString.size()) {
705 size_t DollarStart = AsmString.find('$', Pos);
706 if (DollarStart == std::string::npos)
707 DollarStart = AsmString.size();
708 size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart);
709 if (DollarEnd == std::string::npos)
710 DollarEnd = AsmString.size();
711 OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
713 size_t NumDollars = DollarEnd - DollarStart;
714 if (NumDollars % 2 != 0 && Pos < AsmString.size()) {
715 // We have an operand reference.
716 size_t DigitStart = Pos;
717 size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart);
718 if (DigitEnd == std::string::npos)
719 DigitEnd = AsmString.size();
720 StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
721 unsigned OperandIndex;
722 if (!OperandStr.getAsInteger(10, OperandIndex)) {
723 if (OperandIndex >= FirstIn)
724 OperandIndex += NumNewOuts;
732 AsmString = std::move(OS.str());
735 /// Add output constraints for EAX:EDX because they are return registers.
736 void X86_32TargetCodeGenInfo::addReturnRegisterOutputs(
737 CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints,
738 std::vector<llvm::Type *> &ResultRegTypes,
739 std::vector<llvm::Type *> &ResultTruncRegTypes,
740 std::vector<LValue> &ResultRegDests, std::string &AsmString,
741 unsigned NumOutputs) const {
742 uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType());
744 // Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is
746 if (!Constraints.empty())
748 if (RetWidth <= 32) {
749 Constraints += "={eax}";
750 ResultRegTypes.push_back(CGF.Int32Ty);
752 // Use the 'A' constraint for EAX:EDX.
754 ResultRegTypes.push_back(CGF.Int64Ty);
757 // Truncate EAX or EAX:EDX to an integer of the appropriate size.
758 llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth);
759 ResultTruncRegTypes.push_back(CoerceTy);
761 // Coerce the integer by bitcasting the return slot pointer.
762 ReturnSlot.setAddress(CGF.Builder.CreateBitCast(ReturnSlot.getAddress(),
763 CoerceTy->getPointerTo()));
764 ResultRegDests.push_back(ReturnSlot);
766 rewriteInputConstraintReferences(NumOutputs, 1, AsmString);
769 /// shouldReturnTypeInRegister - Determine if the given type should be
770 /// passed in a register (for the Darwin ABI).
771 bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
772 ASTContext &Context) const {
773 uint64_t Size = Context.getTypeSize(Ty);
775 // Type must be register sized.
776 if (!isRegisterSize(Size))
779 if (Ty->isVectorType()) {
780 // 64- and 128- bit vectors inside structures are not returned in
782 if (Size == 64 || Size == 128)
788 // If this is a builtin, pointer, enum, complex type, member pointer, or
789 // member function pointer it is ok.
790 if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() ||
791 Ty->isAnyComplexType() || Ty->isEnumeralType() ||
792 Ty->isBlockPointerType() || Ty->isMemberPointerType())
795 // Arrays are treated like records.
796 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty))
797 return shouldReturnTypeInRegister(AT->getElementType(), Context);
799 // Otherwise, it must be a record type.
800 const RecordType *RT = Ty->getAs<RecordType>();
801 if (!RT) return false;
803 // FIXME: Traverse bases here too.
805 // Structure types are passed in register if all fields would be
806 // passed in a register.
807 for (const auto *FD : RT->getDecl()->fields()) {
808 // Empty fields are ignored.
809 if (isEmptyField(Context, FD, true))
812 // Check fields recursively.
813 if (!shouldReturnTypeInRegister(FD->getType(), Context))
819 ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(CCState &State) const {
820 // If the return value is indirect, then the hidden argument is consuming one
822 if (State.FreeRegs) {
824 return ABIArgInfo::getIndirectInReg(/*Align=*/0, /*ByVal=*/false);
826 return ABIArgInfo::getIndirect(/*Align=*/0, /*ByVal=*/false);
829 ABIArgInfo X86_32ABIInfo::classifyReturnType(QualType RetTy,
830 CCState &State) const {
831 if (RetTy->isVoidType())
832 return ABIArgInfo::getIgnore();
834 const Type *Base = nullptr;
835 uint64_t NumElts = 0;
836 if (State.CC == llvm::CallingConv::X86_VectorCall &&
837 isHomogeneousAggregate(RetTy, Base, NumElts)) {
838 // The LLVM struct type for such an aggregate should lower properly.
839 return ABIArgInfo::getDirect();
842 if (const VectorType *VT = RetTy->getAs<VectorType>()) {
843 // On Darwin, some vectors are returned in registers.
844 if (IsDarwinVectorABI) {
845 uint64_t Size = getContext().getTypeSize(RetTy);
847 // 128-bit vectors are a special case; they are returned in
848 // registers and we need to make sure to pick a type the LLVM
849 // backend will like.
851 return ABIArgInfo::getDirect(llvm::VectorType::get(
852 llvm::Type::getInt64Ty(getVMContext()), 2));
854 // Always return in register if it fits in a general purpose
855 // register, or if it is 64 bits and has a single element.
856 if ((Size == 8 || Size == 16 || Size == 32) ||
857 (Size == 64 && VT->getNumElements() == 1))
858 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
861 return getIndirectReturnResult(State);
864 return ABIArgInfo::getDirect();
867 if (isAggregateTypeForABI(RetTy)) {
868 if (const RecordType *RT = RetTy->getAs<RecordType>()) {
869 // Structures with flexible arrays are always indirect.
870 if (RT->getDecl()->hasFlexibleArrayMember())
871 return getIndirectReturnResult(State);
874 // If specified, structs and unions are always indirect.
875 if (!IsSmallStructInRegABI && !RetTy->isAnyComplexType())
876 return getIndirectReturnResult(State);
878 // Small structures which are register sized are generally returned
880 if (shouldReturnTypeInRegister(RetTy, getContext())) {
881 uint64_t Size = getContext().getTypeSize(RetTy);
883 // As a special-case, if the struct is a "single-element" struct, and
884 // the field is of type "float" or "double", return it in a
885 // floating-point register. (MSVC does not apply this special case.)
886 // We apply a similar transformation for pointer types to improve the
887 // quality of the generated IR.
888 if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
889 if ((!IsWin32StructABI && SeltTy->isRealFloatingType())
890 || SeltTy->hasPointerRepresentation())
891 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
893 // FIXME: We should be able to narrow this integer in cases with dead
895 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size));
898 return getIndirectReturnResult(State);
901 // Treat an enum type as its underlying type.
902 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
903 RetTy = EnumTy->getDecl()->getIntegerType();
905 return (RetTy->isPromotableIntegerType() ?
906 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
909 static bool isSSEVectorType(ASTContext &Context, QualType Ty) {
910 return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128;
913 static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) {
914 const RecordType *RT = Ty->getAs<RecordType>();
917 const RecordDecl *RD = RT->getDecl();
919 // If this is a C++ record, check the bases first.
920 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
921 for (const auto &I : CXXRD->bases())
922 if (!isRecordWithSSEVectorType(Context, I.getType()))
925 for (const auto *i : RD->fields()) {
926 QualType FT = i->getType();
928 if (isSSEVectorType(Context, FT))
931 if (isRecordWithSSEVectorType(Context, FT))
938 unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty,
939 unsigned Align) const {
940 // Otherwise, if the alignment is less than or equal to the minimum ABI
941 // alignment, just use the default; the backend will handle this.
942 if (Align <= MinABIStackAlignInBytes)
943 return 0; // Use default alignment.
945 // On non-Darwin, the stack type alignment is always 4.
946 if (!IsDarwinVectorABI) {
947 // Set explicit alignment, since we may need to realign the top.
948 return MinABIStackAlignInBytes;
951 // Otherwise, if the type contains an SSE vector type, the alignment is 16.
952 if (Align >= 16 && (isSSEVectorType(getContext(), Ty) ||
953 isRecordWithSSEVectorType(getContext(), Ty)))
956 return MinABIStackAlignInBytes;
959 ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal,
960 CCState &State) const {
962 if (State.FreeRegs) {
963 --State.FreeRegs; // Non-byval indirects just use one pointer.
964 return ABIArgInfo::getIndirectInReg(0, false);
966 return ABIArgInfo::getIndirect(0, false);
969 // Compute the byval alignment.
970 unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
971 unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign);
973 return ABIArgInfo::getIndirect(4, /*ByVal=*/true);
975 // If the stack alignment is less than the type alignment, realign the
977 bool Realign = TypeAlign > StackAlign;
978 return ABIArgInfo::getIndirect(StackAlign, /*ByVal=*/true, Realign);
981 X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const {
982 const Type *T = isSingleElementStruct(Ty, getContext());
986 if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
987 BuiltinType::Kind K = BT->getKind();
988 if (K == BuiltinType::Float || K == BuiltinType::Double)
994 bool X86_32ABIInfo::shouldUseInReg(QualType Ty, CCState &State,
995 bool &NeedsPadding) const {
996 NeedsPadding = false;
997 Class C = classify(Ty);
1001 unsigned Size = getContext().getTypeSize(Ty);
1002 unsigned SizeInRegs = (Size + 31) / 32;
1004 if (SizeInRegs == 0)
1007 if (SizeInRegs > State.FreeRegs) {
1012 State.FreeRegs -= SizeInRegs;
1014 if (State.CC == llvm::CallingConv::X86_FastCall ||
1015 State.CC == llvm::CallingConv::X86_VectorCall) {
1019 if (Ty->isIntegralOrEnumerationType())
1022 if (Ty->isPointerType())
1025 if (Ty->isReferenceType())
1029 NeedsPadding = true;
1037 ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
1038 CCState &State) const {
1039 // FIXME: Set alignment on indirect arguments.
1041 Ty = useFirstFieldIfTransparentUnion(Ty);
1043 // Check with the C++ ABI first.
1044 const RecordType *RT = Ty->getAs<RecordType>();
1046 CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
1047 if (RAA == CGCXXABI::RAA_Indirect) {
1048 return getIndirectResult(Ty, false, State);
1049 } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
1050 // The field index doesn't matter, we'll fix it up later.
1051 return ABIArgInfo::getInAlloca(/*FieldIndex=*/0);
1055 // vectorcall adds the concept of a homogenous vector aggregate, similar
1056 // to other targets.
1057 const Type *Base = nullptr;
1058 uint64_t NumElts = 0;
1059 if (State.CC == llvm::CallingConv::X86_VectorCall &&
1060 isHomogeneousAggregate(Ty, Base, NumElts)) {
1061 if (State.FreeSSERegs >= NumElts) {
1062 State.FreeSSERegs -= NumElts;
1063 if (Ty->isBuiltinType() || Ty->isVectorType())
1064 return ABIArgInfo::getDirect();
1065 return ABIArgInfo::getExpand();
1067 return getIndirectResult(Ty, /*ByVal=*/false, State);
1070 if (isAggregateTypeForABI(Ty)) {
1072 // Structs are always byval on win32, regardless of what they contain.
1073 if (IsWin32StructABI)
1074 return getIndirectResult(Ty, true, State);
1076 // Structures with flexible arrays are always indirect.
1077 if (RT->getDecl()->hasFlexibleArrayMember())
1078 return getIndirectResult(Ty, true, State);
1081 // Ignore empty structs/unions.
1082 if (isEmptyRecord(getContext(), Ty, true))
1083 return ABIArgInfo::getIgnore();
1085 llvm::LLVMContext &LLVMContext = getVMContext();
1086 llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
1088 if (shouldUseInReg(Ty, State, NeedsPadding)) {
1089 unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
1090 SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
1091 llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
1092 return ABIArgInfo::getDirectInReg(Result);
1094 llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr;
1096 // Expand small (<= 128-bit) record types when we know that the stack layout
1097 // of those arguments will match the struct. This is important because the
1098 // LLVM backend isn't smart enough to remove byval, which inhibits many
1100 if (getContext().getTypeSize(Ty) <= 4*32 &&
1101 canExpandIndirectArgument(Ty, getContext()))
1102 return ABIArgInfo::getExpandWithPadding(
1103 State.CC == llvm::CallingConv::X86_FastCall ||
1104 State.CC == llvm::CallingConv::X86_VectorCall,
1107 return getIndirectResult(Ty, true, State);
1110 if (const VectorType *VT = Ty->getAs<VectorType>()) {
1111 // On Darwin, some vectors are passed in memory, we handle this by passing
1112 // it as an i8/i16/i32/i64.
1113 if (IsDarwinVectorABI) {
1114 uint64_t Size = getContext().getTypeSize(Ty);
1115 if ((Size == 8 || Size == 16 || Size == 32) ||
1116 (Size == 64 && VT->getNumElements() == 1))
1117 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1121 if (IsX86_MMXType(CGT.ConvertType(Ty)))
1122 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
1124 return ABIArgInfo::getDirect();
1128 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
1129 Ty = EnumTy->getDecl()->getIntegerType();
1132 bool InReg = shouldUseInReg(Ty, State, NeedsPadding);
1134 if (Ty->isPromotableIntegerType()) {
1136 return ABIArgInfo::getExtendInReg();
1137 return ABIArgInfo::getExtend();
1140 return ABIArgInfo::getDirectInReg();
1141 return ABIArgInfo::getDirect();
1144 void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
1145 CCState State(FI.getCallingConvention());
1146 if (State.CC == llvm::CallingConv::X86_FastCall)
1148 else if (State.CC == llvm::CallingConv::X86_VectorCall) {
1150 State.FreeSSERegs = 6;
1151 } else if (FI.getHasRegParm())
1152 State.FreeRegs = FI.getRegParm();
1154 State.FreeRegs = DefaultNumRegisterParameters;
1156 if (!getCXXABI().classifyReturnType(FI)) {
1157 FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), State);
1158 } else if (FI.getReturnInfo().isIndirect()) {
1159 // The C++ ABI is not aware of register usage, so we have to check if the
1160 // return value was sret and put it in a register ourselves if appropriate.
1161 if (State.FreeRegs) {
1162 --State.FreeRegs; // The sret parameter consumes a register.
1163 FI.getReturnInfo().setInReg(true);
1167 // The chain argument effectively gives us another free register.
1168 if (FI.isChainCall())
1171 bool UsedInAlloca = false;
1172 for (auto &I : FI.arguments()) {
1173 I.info = classifyArgumentType(I.type, State);
1174 UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1177 // If we needed to use inalloca for any argument, do a second pass and rewrite
1178 // all the memory arguments to use inalloca.
1180 rewriteWithInAlloca(FI);
1184 X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1185 unsigned &StackOffset,
1186 ABIArgInfo &Info, QualType Type) const {
1187 assert(StackOffset % 4U == 0 && "unaligned inalloca struct");
1188 Info = ABIArgInfo::getInAlloca(FrameFields.size());
1189 FrameFields.push_back(CGT.ConvertTypeForMem(Type));
1190 StackOffset += getContext().getTypeSizeInChars(Type).getQuantity();
1192 // Insert padding bytes to respect alignment. For x86_32, each argument is 4
1194 if (StackOffset % 4U) {
1195 unsigned OldOffset = StackOffset;
1196 StackOffset = llvm::RoundUpToAlignment(StackOffset, 4U);
1197 unsigned NumBytes = StackOffset - OldOffset;
1199 llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
1200 Ty = llvm::ArrayType::get(Ty, NumBytes);
1201 FrameFields.push_back(Ty);
1205 static bool isArgInAlloca(const ABIArgInfo &Info) {
1206 // Leave ignored and inreg arguments alone.
1207 switch (Info.getKind()) {
1208 case ABIArgInfo::InAlloca:
1210 case ABIArgInfo::Indirect:
1211 assert(Info.getIndirectByVal());
1213 case ABIArgInfo::Ignore:
1215 case ABIArgInfo::Direct:
1216 case ABIArgInfo::Extend:
1217 case ABIArgInfo::Expand:
1218 if (Info.getInReg())
1222 llvm_unreachable("invalid enum");
1225 void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
1226 assert(IsWin32StructABI && "inalloca only supported on win32");
1228 // Build a packed struct type for all of the arguments in memory.
1229 SmallVector<llvm::Type *, 6> FrameFields;
1231 unsigned StackOffset = 0;
1232 CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end();
1234 // Put 'this' into the struct before 'sret', if necessary.
1236 FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
1237 ABIArgInfo &Ret = FI.getReturnInfo();
1238 if (Ret.isIndirect() && Ret.isSRetAfterThis() && !IsThisCall &&
1239 isArgInAlloca(I->info)) {
1240 addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1244 // Put the sret parameter into the inalloca struct if it's in memory.
1245 if (Ret.isIndirect() && !Ret.getInReg()) {
1246 CanQualType PtrTy = getContext().getPointerType(FI.getReturnType());
1247 addFieldToArgStruct(FrameFields, StackOffset, Ret, PtrTy);
1248 // On Windows, the hidden sret parameter is always returned in eax.
1249 Ret.setInAllocaSRet(IsWin32StructABI);
1252 // Skip the 'this' parameter in ecx.
1256 // Put arguments passed in memory into the struct.
1257 for (; I != E; ++I) {
1258 if (isArgInAlloca(I->info))
1259 addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1262 FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
1263 /*isPacked=*/true));
1266 llvm::Value *X86_32ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
1267 CodeGenFunction &CGF) const {
1268 llvm::Type *BPP = CGF.Int8PtrPtrTy;
1270 CGBuilderTy &Builder = CGF.Builder;
1271 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP,
1273 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur");
1275 // Compute if the address needs to be aligned
1276 unsigned Align = CGF.getContext().getTypeAlignInChars(Ty).getQuantity();
1277 Align = getTypeStackAlignInBytes(Ty, Align);
1278 Align = std::max(Align, 4U);
1280 // addr = (addr + align - 1) & -align;
1281 llvm::Value *Offset =
1282 llvm::ConstantInt::get(CGF.Int32Ty, Align - 1);
1283 Addr = CGF.Builder.CreateGEP(Addr, Offset);
1284 llvm::Value *AsInt = CGF.Builder.CreatePtrToInt(Addr,
1286 llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int32Ty, -Align);
1287 Addr = CGF.Builder.CreateIntToPtr(CGF.Builder.CreateAnd(AsInt, Mask),
1293 llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
1294 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy);
1297 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, Align);
1298 llvm::Value *NextAddr =
1299 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset),
1301 Builder.CreateStore(NextAddr, VAListAddrAsBPP);
1306 bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
1307 const llvm::Triple &Triple, const CodeGenOptions &Opts) {
1308 assert(Triple.getArch() == llvm::Triple::x86);
1310 switch (Opts.getStructReturnConvention()) {
1311 case CodeGenOptions::SRCK_Default:
1313 case CodeGenOptions::SRCK_OnStack: // -fpcc-struct-return
1315 case CodeGenOptions::SRCK_InRegs: // -freg-struct-return
1319 if (Triple.isOSDarwin())
1322 switch (Triple.getOS()) {
1323 case llvm::Triple::DragonFly:
1324 case llvm::Triple::FreeBSD:
1325 case llvm::Triple::OpenBSD:
1326 case llvm::Triple::Bitrig:
1327 case llvm::Triple::Win32:
1334 void X86_32TargetCodeGenInfo::setTargetAttributes(const Decl *D,
1335 llvm::GlobalValue *GV,
1336 CodeGen::CodeGenModule &CGM) const {
1337 if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) {
1338 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1339 // Get the LLVM function.
1340 llvm::Function *Fn = cast<llvm::Function>(GV);
1342 // Now add the 'alignstack' attribute with a value of 16.
1343 llvm::AttrBuilder B;
1344 B.addStackAlignmentAttr(16);
1345 Fn->addAttributes(llvm::AttributeSet::FunctionIndex,
1346 llvm::AttributeSet::get(CGM.getLLVMContext(),
1347 llvm::AttributeSet::FunctionIndex,
1353 bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
1354 CodeGen::CodeGenFunction &CGF,
1355 llvm::Value *Address) const {
1356 CodeGen::CGBuilderTy &Builder = CGF.Builder;
1358 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
1360 // 0-7 are the eight integer registers; the order is different
1361 // on Darwin (for EH), but the range is the same.
1363 AssignToArrayRange(Builder, Address, Four8, 0, 8);
1365 if (CGF.CGM.getTarget().getTriple().isOSDarwin()) {
1366 // 12-16 are st(0..4). Not sure why we stop at 4.
1367 // These have size 16, which is sizeof(long double) on
1368 // platforms with 8-byte alignment for that type.
1369 llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
1370 AssignToArrayRange(Builder, Address, Sixteen8, 12, 16);
1373 // 9 is %eflags, which doesn't get a size on Darwin for some
1375 Builder.CreateStore(
1376 Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9));
1378 // 11-16 are st(0..5). Not sure why we stop at 5.
1379 // These have size 12, which is sizeof(long double) on
1380 // platforms with 4-byte alignment for that type.
1381 llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12);
1382 AssignToArrayRange(Builder, Address, Twelve8, 11, 16);
1388 //===----------------------------------------------------------------------===//
1389 // X86-64 ABI Implementation
1390 //===----------------------------------------------------------------------===//
1394 /// The AVX ABI level for X86 targets.
1395 enum class X86AVXABILevel {
1401 /// \p returns the size in bits of the largest (native) vector for \p AVXLevel.
1402 static unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) {
1404 case X86AVXABILevel::AVX512:
1406 case X86AVXABILevel::AVX:
1408 case X86AVXABILevel::None:
1411 llvm_unreachable("Unknown AVXLevel");
1414 /// X86_64ABIInfo - The X86_64 ABI information.
1415 class X86_64ABIInfo : public ABIInfo {
1427 /// merge - Implement the X86_64 ABI merging algorithm.
1429 /// Merge an accumulating classification \arg Accum with a field
1430 /// classification \arg Field.
1432 /// \param Accum - The accumulating classification. This should
1433 /// always be either NoClass or the result of a previous merge
1434 /// call. In addition, this should never be Memory (the caller
1435 /// should just return Memory for the aggregate).
1436 static Class merge(Class Accum, Class Field);
1438 /// postMerge - Implement the X86_64 ABI post merging algorithm.
1440 /// Post merger cleanup, reduces a malformed Hi and Lo pair to
1441 /// final MEMORY or SSE classes when necessary.
1443 /// \param AggregateSize - The size of the current aggregate in
1444 /// the classification process.
1446 /// \param Lo - The classification for the parts of the type
1447 /// residing in the low word of the containing object.
1449 /// \param Hi - The classification for the parts of the type
1450 /// residing in the higher words of the containing object.
1452 void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
1454 /// classify - Determine the x86_64 register classes in which the
1455 /// given type T should be passed.
1457 /// \param Lo - The classification for the parts of the type
1458 /// residing in the low word of the containing object.
1460 /// \param Hi - The classification for the parts of the type
1461 /// residing in the high word of the containing object.
1463 /// \param OffsetBase - The bit offset of this type in the
1464 /// containing object. Some parameters are classified different
1465 /// depending on whether they straddle an eightbyte boundary.
1467 /// \param isNamedArg - Whether the argument in question is a "named"
1468 /// argument, as used in AMD64-ABI 3.5.7.
1470 /// If a word is unused its result will be NoClass; if a type should
1471 /// be passed in Memory then at least the classification of \arg Lo
1474 /// The \arg Lo class will be NoClass iff the argument is ignored.
1476 /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
1477 /// also be ComplexX87.
1478 void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
1479 bool isNamedArg) const;
1481 llvm::Type *GetByteVectorType(QualType Ty) const;
1482 llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType,
1483 unsigned IROffset, QualType SourceTy,
1484 unsigned SourceOffset) const;
1485 llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType,
1486 unsigned IROffset, QualType SourceTy,
1487 unsigned SourceOffset) const;
1489 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1490 /// such that the argument will be returned in memory.
1491 ABIArgInfo getIndirectReturnResult(QualType Ty) const;
1493 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1494 /// such that the argument will be passed in memory.
1496 /// \param freeIntRegs - The number of free integer registers remaining
1498 ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const;
1500 ABIArgInfo classifyReturnType(QualType RetTy) const;
1502 ABIArgInfo classifyArgumentType(QualType Ty,
1503 unsigned freeIntRegs,
1504 unsigned &neededInt,
1505 unsigned &neededSSE,
1506 bool isNamedArg) const;
1508 bool IsIllegalVectorType(QualType Ty) const;
1510 /// The 0.98 ABI revision clarified a lot of ambiguities,
1511 /// unfortunately in ways that were not always consistent with
1512 /// certain previous compilers. In particular, platforms which
1513 /// required strict binary compatibility with older versions of GCC
1514 /// may need to exempt themselves.
1515 bool honorsRevision0_98() const {
1516 return !getTarget().getTriple().isOSDarwin();
1519 X86AVXABILevel AVXLevel;
1520 // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on
1522 bool Has64BitPointers;
1525 X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) :
1526 ABIInfo(CGT), AVXLevel(AVXLevel),
1527 Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) {
1530 bool isPassedUsingAVXType(QualType type) const {
1531 unsigned neededInt, neededSSE;
1532 // The freeIntRegs argument doesn't matter here.
1533 ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE,
1534 /*isNamedArg*/true);
1535 if (info.isDirect()) {
1536 llvm::Type *ty = info.getCoerceToType();
1537 if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty))
1538 return (vectorTy->getBitWidth() > 128);
1543 void computeInfo(CGFunctionInfo &FI) const override;
1545 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
1546 CodeGenFunction &CGF) const override;
1548 bool has64BitPointers() const {
1549 return Has64BitPointers;
1553 /// WinX86_64ABIInfo - The Windows X86_64 ABI information.
1554 class WinX86_64ABIInfo : public ABIInfo {
1556 WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT)
1558 IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {}
1560 void computeInfo(CGFunctionInfo &FI) const override;
1562 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
1563 CodeGenFunction &CGF) const override;
1565 bool isHomogeneousAggregateBaseType(QualType Ty) const override {
1566 // FIXME: Assumes vectorcall is in use.
1567 return isX86VectorTypeForVectorCall(getContext(), Ty);
1570 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
1571 uint64_t NumMembers) const override {
1572 // FIXME: Assumes vectorcall is in use.
1573 return isX86VectorCallAggregateSmallEnough(NumMembers);
1577 ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs,
1578 bool IsReturnType) const;
1583 class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
1585 X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
1586 : TargetCodeGenInfo(new X86_64ABIInfo(CGT, AVXLevel)) {}
1588 const X86_64ABIInfo &getABIInfo() const {
1589 return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo());
1592 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
1596 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1597 llvm::Value *Address) const override {
1598 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
1600 // 0-15 are the 16 integer registers.
1602 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
1606 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
1607 StringRef Constraint,
1608 llvm::Type* Ty) const override {
1609 return X86AdjustInlineAsmType(CGF, Constraint, Ty);
1612 bool isNoProtoCallVariadic(const CallArgList &args,
1613 const FunctionNoProtoType *fnType) const override {
1614 // The default CC on x86-64 sets %al to the number of SSA
1615 // registers used, and GCC sets this when calling an unprototyped
1616 // function, so we override the default behavior. However, don't do
1617 // that when AVX types are involved: the ABI explicitly states it is
1618 // undefined, and it doesn't work in practice because of how the ABI
1619 // defines varargs anyway.
1620 if (fnType->getCallConv() == CC_C) {
1621 bool HasAVXType = false;
1622 for (CallArgList::const_iterator
1623 it = args.begin(), ie = args.end(); it != ie; ++it) {
1624 if (getABIInfo().isPassedUsingAVXType(it->Ty)) {
1634 return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType);
1638 getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
1640 if (getABIInfo().has64BitPointers())
1641 Sig = (0xeb << 0) | // jmp rel8
1642 (0x0a << 8) | // .+0x0c
1646 Sig = (0xeb << 0) | // jmp rel8
1647 (0x06 << 8) | // .+0x08
1650 return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
1654 class PS4TargetCodeGenInfo : public X86_64TargetCodeGenInfo {
1656 PS4TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
1657 : X86_64TargetCodeGenInfo(CGT, AVXLevel) {}
1659 void getDependentLibraryOption(llvm::StringRef Lib,
1660 llvm::SmallString<24> &Opt) const override {
1666 static std::string qualifyWindowsLibrary(llvm::StringRef Lib) {
1667 // If the argument does not end in .lib, automatically add the suffix.
1668 // If the argument contains a space, enclose it in quotes.
1669 // This matches the behavior of MSVC.
1670 bool Quote = (Lib.find(" ") != StringRef::npos);
1671 std::string ArgStr = Quote ? "\"" : "";
1673 if (!Lib.endswith_lower(".lib"))
1675 ArgStr += Quote ? "\"" : "";
1679 class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
1681 WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
1682 bool d, bool p, bool w, unsigned RegParms)
1683 : X86_32TargetCodeGenInfo(CGT, d, p, w, RegParms) {}
1685 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
1686 CodeGen::CodeGenModule &CGM) const override;
1688 void getDependentLibraryOption(llvm::StringRef Lib,
1689 llvm::SmallString<24> &Opt) const override {
1690 Opt = "/DEFAULTLIB:";
1691 Opt += qualifyWindowsLibrary(Lib);
1694 void getDetectMismatchOption(llvm::StringRef Name,
1695 llvm::StringRef Value,
1696 llvm::SmallString<32> &Opt) const override {
1697 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
1701 static void addStackProbeSizeTargetAttribute(const Decl *D,
1702 llvm::GlobalValue *GV,
1703 CodeGen::CodeGenModule &CGM) {
1704 if (isa<FunctionDecl>(D)) {
1705 if (CGM.getCodeGenOpts().StackProbeSize != 4096) {
1706 llvm::Function *Fn = cast<llvm::Function>(GV);
1708 Fn->addFnAttr("stack-probe-size",
1709 llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
1714 void WinX86_32TargetCodeGenInfo::setTargetAttributes(const Decl *D,
1715 llvm::GlobalValue *GV,
1716 CodeGen::CodeGenModule &CGM) const {
1717 X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
1719 addStackProbeSizeTargetAttribute(D, GV, CGM);
1722 class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo {
1724 WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
1725 X86AVXABILevel AVXLevel)
1726 : TargetCodeGenInfo(new WinX86_64ABIInfo(CGT)) {}
1728 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
1729 CodeGen::CodeGenModule &CGM) const override;
1731 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
1735 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1736 llvm::Value *Address) const override {
1737 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
1739 // 0-15 are the 16 integer registers.
1741 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
1745 void getDependentLibraryOption(llvm::StringRef Lib,
1746 llvm::SmallString<24> &Opt) const override {
1747 Opt = "/DEFAULTLIB:";
1748 Opt += qualifyWindowsLibrary(Lib);
1751 void getDetectMismatchOption(llvm::StringRef Name,
1752 llvm::StringRef Value,
1753 llvm::SmallString<32> &Opt) const override {
1754 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
1758 void WinX86_64TargetCodeGenInfo::setTargetAttributes(const Decl *D,
1759 llvm::GlobalValue *GV,
1760 CodeGen::CodeGenModule &CGM) const {
1761 TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
1763 addStackProbeSizeTargetAttribute(D, GV, CGM);
1767 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
1769 // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
1771 // (a) If one of the classes is Memory, the whole argument is passed in
1774 // (b) If X87UP is not preceded by X87, the whole argument is passed in
1777 // (c) If the size of the aggregate exceeds two eightbytes and the first
1778 // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
1779 // argument is passed in memory. NOTE: This is necessary to keep the
1780 // ABI working for processors that don't support the __m256 type.
1782 // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
1784 // Some of these are enforced by the merging logic. Others can arise
1785 // only with unions; for example:
1786 // union { _Complex double; unsigned; }
1788 // Note that clauses (b) and (c) were added in 0.98.
1792 if (Hi == X87Up && Lo != X87 && honorsRevision0_98())
1794 if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp))
1796 if (Hi == SSEUp && Lo != SSE)
1800 X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) {
1801 // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
1802 // classified recursively so that always two fields are
1803 // considered. The resulting class is calculated according to
1804 // the classes of the fields in the eightbyte:
1806 // (a) If both classes are equal, this is the resulting class.
1808 // (b) If one of the classes is NO_CLASS, the resulting class is
1811 // (c) If one of the classes is MEMORY, the result is the MEMORY
1814 // (d) If one of the classes is INTEGER, the result is the
1817 // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class,
1818 // MEMORY is used as class.
1820 // (f) Otherwise class SSE is used.
1822 // Accum should never be memory (we should have returned) or
1823 // ComplexX87 (because this cannot be passed in a structure).
1824 assert((Accum != Memory && Accum != ComplexX87) &&
1825 "Invalid accumulated classification during merge.");
1826 if (Accum == Field || Field == NoClass)
1828 if (Field == Memory)
1830 if (Accum == NoClass)
1832 if (Accum == Integer || Field == Integer)
1834 if (Field == X87 || Field == X87Up || Field == ComplexX87 ||
1835 Accum == X87 || Accum == X87Up)
1840 void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase,
1841 Class &Lo, Class &Hi, bool isNamedArg) const {
1842 // FIXME: This code can be simplified by introducing a simple value class for
1843 // Class pairs with appropriate constructor methods for the various
1846 // FIXME: Some of the split computations are wrong; unaligned vectors
1847 // shouldn't be passed in registers for example, so there is no chance they
1848 // can straddle an eightbyte. Verify & simplify.
1852 Class &Current = OffsetBase < 64 ? Lo : Hi;
1855 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
1856 BuiltinType::Kind k = BT->getKind();
1858 if (k == BuiltinType::Void) {
1860 } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) {
1863 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
1865 } else if (k == BuiltinType::Float || k == BuiltinType::Double) {
1867 } else if (k == BuiltinType::LongDouble) {
1868 const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
1869 if (LDF == &llvm::APFloat::IEEEquad) {
1872 } else if (LDF == &llvm::APFloat::x87DoubleExtended) {
1875 } else if (LDF == &llvm::APFloat::IEEEdouble) {
1878 llvm_unreachable("unexpected long double representation!");
1880 // FIXME: _Decimal32 and _Decimal64 are SSE.
1881 // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
1885 if (const EnumType *ET = Ty->getAs<EnumType>()) {
1886 // Classify the underlying integer type.
1887 classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
1891 if (Ty->hasPointerRepresentation()) {
1896 if (Ty->isMemberPointerType()) {
1897 if (Ty->isMemberFunctionPointerType()) {
1898 if (Has64BitPointers) {
1899 // If Has64BitPointers, this is an {i64, i64}, so classify both
1903 // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
1904 // straddles an eightbyte boundary, Hi should be classified as well.
1905 uint64_t EB_FuncPtr = (OffsetBase) / 64;
1906 uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
1907 if (EB_FuncPtr != EB_ThisAdj) {
1919 if (const VectorType *VT = Ty->getAs<VectorType>()) {
1920 uint64_t Size = getContext().getTypeSize(VT);
1922 // gcc passes all <4 x char>, <2 x short>, <1 x int>, <1 x
1923 // float> as integer.
1926 // If this type crosses an eightbyte boundary, it should be
1928 uint64_t EB_Real = (OffsetBase) / 64;
1929 uint64_t EB_Imag = (OffsetBase + Size - 1) / 64;
1930 if (EB_Real != EB_Imag)
1932 } else if (Size == 64) {
1933 // gcc passes <1 x double> in memory. :(
1934 if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double))
1937 // gcc passes <1 x long long> as INTEGER.
1938 if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::LongLong) ||
1939 VT->getElementType()->isSpecificBuiltinType(BuiltinType::ULongLong) ||
1940 VT->getElementType()->isSpecificBuiltinType(BuiltinType::Long) ||
1941 VT->getElementType()->isSpecificBuiltinType(BuiltinType::ULong))
1946 // If this type crosses an eightbyte boundary, it should be
1948 if (OffsetBase && OffsetBase != 64)
1950 } else if (Size == 128 ||
1951 (isNamedArg && Size <= getNativeVectorSizeForAVXABI(AVXLevel))) {
1952 // Arguments of 256-bits are split into four eightbyte chunks. The
1953 // least significant one belongs to class SSE and all the others to class
1954 // SSEUP. The original Lo and Hi design considers that types can't be
1955 // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
1956 // This design isn't correct for 256-bits, but since there're no cases
1957 // where the upper parts would need to be inspected, avoid adding
1958 // complexity and just consider Hi to match the 64-256 part.
1960 // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
1961 // registers if they are "named", i.e. not part of the "..." of a
1962 // variadic function.
1964 // Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are
1965 // split into eight eightbyte chunks, one SSE and seven SSEUP.
1972 if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
1973 QualType ET = getContext().getCanonicalType(CT->getElementType());
1975 uint64_t Size = getContext().getTypeSize(Ty);
1976 if (ET->isIntegralOrEnumerationType()) {
1979 else if (Size <= 128)
1981 } else if (ET == getContext().FloatTy) {
1983 } else if (ET == getContext().DoubleTy) {
1985 } else if (ET == getContext().LongDoubleTy) {
1986 const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
1987 if (LDF == &llvm::APFloat::IEEEquad)
1989 else if (LDF == &llvm::APFloat::x87DoubleExtended)
1990 Current = ComplexX87;
1991 else if (LDF == &llvm::APFloat::IEEEdouble)
1994 llvm_unreachable("unexpected long double representation!");
1997 // If this complex type crosses an eightbyte boundary then it
1999 uint64_t EB_Real = (OffsetBase) / 64;
2000 uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64;
2001 if (Hi == NoClass && EB_Real != EB_Imag)
2007 if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
2008 // Arrays are treated like structures.
2010 uint64_t Size = getContext().getTypeSize(Ty);
2012 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2013 // than four eightbytes, ..., it has class MEMORY.
2017 // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
2018 // fields, it has class MEMORY.
2020 // Only need to check alignment of array base.
2021 if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
2024 // Otherwise implement simplified merge. We could be smarter about
2025 // this, but it isn't worth it and would be harder to verify.
2027 uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
2028 uint64_t ArraySize = AT->getSize().getZExtValue();
2030 // The only case a 256-bit wide vector could be used is when the array
2031 // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2032 // to work for sizes wider than 128, early check and fallback to memory.
2033 if (Size > 128 && EltSize != 256)
2036 for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) {
2037 Class FieldLo, FieldHi;
2038 classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
2039 Lo = merge(Lo, FieldLo);
2040 Hi = merge(Hi, FieldHi);
2041 if (Lo == Memory || Hi == Memory)
2045 postMerge(Size, Lo, Hi);
2046 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
2050 if (const RecordType *RT = Ty->getAs<RecordType>()) {
2051 uint64_t Size = getContext().getTypeSize(Ty);
2053 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2054 // than four eightbytes, ..., it has class MEMORY.
2058 // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
2059 // copy constructor or a non-trivial destructor, it is passed by invisible
2061 if (getRecordArgABI(RT, getCXXABI()))
2064 const RecordDecl *RD = RT->getDecl();
2066 // Assume variable sized types are passed in memory.
2067 if (RD->hasFlexibleArrayMember())
2070 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
2072 // Reset Lo class, this will be recomputed.
2075 // If this is a C++ record, classify the bases first.
2076 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2077 for (const auto &I : CXXRD->bases()) {
2078 assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2079 "Unexpected base class!");
2080 const CXXRecordDecl *Base =
2081 cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
2083 // Classify this field.
2085 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
2086 // single eightbyte, each is classified separately. Each eightbyte gets
2087 // initialized to class NO_CLASS.
2088 Class FieldLo, FieldHi;
2090 OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base));
2091 classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
2092 Lo = merge(Lo, FieldLo);
2093 Hi = merge(Hi, FieldHi);
2094 if (Lo == Memory || Hi == Memory) {
2095 postMerge(Size, Lo, Hi);
2101 // Classify the fields one at a time, merging the results.
2103 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2104 i != e; ++i, ++idx) {
2105 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2106 bool BitField = i->isBitField();
2108 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
2109 // four eightbytes, or it contains unaligned fields, it has class MEMORY.
2111 // The only case a 256-bit wide vector could be used is when the struct
2112 // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2113 // to work for sizes wider than 128, early check and fallback to memory.
2115 if (Size > 128 && getContext().getTypeSize(i->getType()) != 256) {
2117 postMerge(Size, Lo, Hi);
2120 // Note, skip this test for bit-fields, see below.
2121 if (!BitField && Offset % getContext().getTypeAlign(i->getType())) {
2123 postMerge(Size, Lo, Hi);
2127 // Classify this field.
2129 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
2130 // exceeds a single eightbyte, each is classified
2131 // separately. Each eightbyte gets initialized to class
2133 Class FieldLo, FieldHi;
2135 // Bit-fields require special handling, they do not force the
2136 // structure to be passed in memory even if unaligned, and
2137 // therefore they can straddle an eightbyte.
2139 // Ignore padding bit-fields.
2140 if (i->isUnnamedBitfield())
2143 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2144 uint64_t Size = i->getBitWidthValue(getContext());
2146 uint64_t EB_Lo = Offset / 64;
2147 uint64_t EB_Hi = (Offset + Size - 1) / 64;
2150 assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes.");
2155 FieldHi = EB_Hi ? Integer : NoClass;
2158 classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
2159 Lo = merge(Lo, FieldLo);
2160 Hi = merge(Hi, FieldHi);
2161 if (Lo == Memory || Hi == Memory)
2165 postMerge(Size, Lo, Hi);
2169 ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const {
2170 // If this is a scalar LLVM value then assume LLVM will pass it in the right
2172 if (!isAggregateTypeForABI(Ty)) {
2173 // Treat an enum type as its underlying type.
2174 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2175 Ty = EnumTy->getDecl()->getIntegerType();
2177 return (Ty->isPromotableIntegerType() ?
2178 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
2181 return ABIArgInfo::getIndirect(0);
2184 bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const {
2185 if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
2186 uint64_t Size = getContext().getTypeSize(VecTy);
2187 unsigned LargestVector = getNativeVectorSizeForAVXABI(AVXLevel);
2188 if (Size <= 64 || Size > LargestVector)
2195 ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty,
2196 unsigned freeIntRegs) const {
2197 // If this is a scalar LLVM value then assume LLVM will pass it in the right
2200 // This assumption is optimistic, as there could be free registers available
2201 // when we need to pass this argument in memory, and LLVM could try to pass
2202 // the argument in the free register. This does not seem to happen currently,
2203 // but this code would be much safer if we could mark the argument with
2204 // 'onstack'. See PR12193.
2205 if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty)) {
2206 // Treat an enum type as its underlying type.
2207 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2208 Ty = EnumTy->getDecl()->getIntegerType();
2210 return (Ty->isPromotableIntegerType() ?
2211 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
2214 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
2215 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
2217 // Compute the byval alignment. We specify the alignment of the byval in all
2218 // cases so that the mid-level optimizer knows the alignment of the byval.
2219 unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U);
2221 // Attempt to avoid passing indirect results using byval when possible. This
2222 // is important for good codegen.
2224 // We do this by coercing the value into a scalar type which the backend can
2225 // handle naturally (i.e., without using byval).
2227 // For simplicity, we currently only do this when we have exhausted all of the
2228 // free integer registers. Doing this when there are free integer registers
2229 // would require more care, as we would have to ensure that the coerced value
2230 // did not claim the unused register. That would require either reording the
2231 // arguments to the function (so that any subsequent inreg values came first),
2232 // or only doing this optimization when there were no following arguments that
2235 // We currently expect it to be rare (particularly in well written code) for
2236 // arguments to be passed on the stack when there are still free integer
2237 // registers available (this would typically imply large structs being passed
2238 // by value), so this seems like a fair tradeoff for now.
2240 // We can revisit this if the backend grows support for 'onstack' parameter
2241 // attributes. See PR12193.
2242 if (freeIntRegs == 0) {
2243 uint64_t Size = getContext().getTypeSize(Ty);
2245 // If this type fits in an eightbyte, coerce it into the matching integral
2246 // type, which will end up on the stack (with alignment 8).
2247 if (Align == 8 && Size <= 64)
2248 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
2252 return ABIArgInfo::getIndirect(Align);
2255 /// The ABI specifies that a value should be passed in a full vector XMM/YMM
2256 /// register. Pick an LLVM IR type that will be passed as a vector register.
2257 llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const {
2258 // Wrapper structs/arrays that only contain vectors are passed just like
2259 // vectors; strip them off if present.
2260 if (const Type *InnerTy = isSingleElementStruct(Ty, getContext()))
2261 Ty = QualType(InnerTy, 0);
2263 llvm::Type *IRType = CGT.ConvertType(Ty);
2264 if (isa<llvm::VectorType>(IRType) ||
2265 IRType->getTypeID() == llvm::Type::FP128TyID)
2268 // We couldn't find the preferred IR vector type for 'Ty'.
2269 uint64_t Size = getContext().getTypeSize(Ty);
2270 assert((Size == 128 || Size == 256) && "Invalid type found!");
2272 // Return a LLVM IR vector type based on the size of 'Ty'.
2273 return llvm::VectorType::get(llvm::Type::getDoubleTy(getVMContext()),
2277 /// BitsContainNoUserData - Return true if the specified [start,end) bit range
2278 /// is known to either be off the end of the specified type or being in
2279 /// alignment padding. The user type specified is known to be at most 128 bits
2280 /// in size, and have passed through X86_64ABIInfo::classify with a successful
2281 /// classification that put one of the two halves in the INTEGER class.
2283 /// It is conservatively correct to return false.
2284 static bool BitsContainNoUserData(QualType Ty, unsigned StartBit,
2285 unsigned EndBit, ASTContext &Context) {
2286 // If the bytes being queried are off the end of the type, there is no user
2287 // data hiding here. This handles analysis of builtins, vectors and other
2288 // types that don't contain interesting padding.
2289 unsigned TySize = (unsigned)Context.getTypeSize(Ty);
2290 if (TySize <= StartBit)
2293 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) {
2294 unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
2295 unsigned NumElts = (unsigned)AT->getSize().getZExtValue();
2297 // Check each element to see if the element overlaps with the queried range.
2298 for (unsigned i = 0; i != NumElts; ++i) {
2299 // If the element is after the span we care about, then we're done..
2300 unsigned EltOffset = i*EltSize;
2301 if (EltOffset >= EndBit) break;
2303 unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0;
2304 if (!BitsContainNoUserData(AT->getElementType(), EltStart,
2305 EndBit-EltOffset, Context))
2308 // If it overlaps no elements, then it is safe to process as padding.
2312 if (const RecordType *RT = Ty->getAs<RecordType>()) {
2313 const RecordDecl *RD = RT->getDecl();
2314 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
2316 // If this is a C++ record, check the bases first.
2317 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2318 for (const auto &I : CXXRD->bases()) {
2319 assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2320 "Unexpected base class!");
2321 const CXXRecordDecl *Base =
2322 cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
2324 // If the base is after the span we care about, ignore it.
2325 unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base));
2326 if (BaseOffset >= EndBit) continue;
2328 unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0;
2329 if (!BitsContainNoUserData(I.getType(), BaseStart,
2330 EndBit-BaseOffset, Context))
2335 // Verify that no field has data that overlaps the region of interest. Yes
2336 // this could be sped up a lot by being smarter about queried fields,
2337 // however we're only looking at structs up to 16 bytes, so we don't care
2340 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2341 i != e; ++i, ++idx) {
2342 unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx);
2344 // If we found a field after the region we care about, then we're done.
2345 if (FieldOffset >= EndBit) break;
2347 unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0;
2348 if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
2353 // If nothing in this record overlapped the area of interest, then we're
2361 /// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a
2362 /// float member at the specified offset. For example, {int,{float}} has a
2363 /// float at offset 4. It is conservatively correct for this routine to return
2365 static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset,
2366 const llvm::DataLayout &TD) {
2367 // Base case if we find a float.
2368 if (IROffset == 0 && IRType->isFloatTy())
2371 // If this is a struct, recurse into the field at the specified offset.
2372 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
2373 const llvm::StructLayout *SL = TD.getStructLayout(STy);
2374 unsigned Elt = SL->getElementContainingOffset(IROffset);
2375 IROffset -= SL->getElementOffset(Elt);
2376 return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD);
2379 // If this is an array, recurse into the field at the specified offset.
2380 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
2381 llvm::Type *EltTy = ATy->getElementType();
2382 unsigned EltSize = TD.getTypeAllocSize(EltTy);
2383 IROffset -= IROffset/EltSize*EltSize;
2384 return ContainsFloatAtOffset(EltTy, IROffset, TD);
2391 /// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
2392 /// low 8 bytes of an XMM register, corresponding to the SSE class.
2393 llvm::Type *X86_64ABIInfo::
2394 GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset,
2395 QualType SourceTy, unsigned SourceOffset) const {
2396 // The only three choices we have are either double, <2 x float>, or float. We
2397 // pass as float if the last 4 bytes is just padding. This happens for
2398 // structs that contain 3 floats.
2399 if (BitsContainNoUserData(SourceTy, SourceOffset*8+32,
2400 SourceOffset*8+64, getContext()))
2401 return llvm::Type::getFloatTy(getVMContext());
2403 // We want to pass as <2 x float> if the LLVM IR type contains a float at
2404 // offset+0 and offset+4. Walk the LLVM IR type to find out if this is the
2406 if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) &&
2407 ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout()))
2408 return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2);
2410 return llvm::Type::getDoubleTy(getVMContext());
2414 /// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
2415 /// an 8-byte GPR. This means that we either have a scalar or we are talking
2416 /// about the high or low part of an up-to-16-byte struct. This routine picks
2417 /// the best LLVM IR type to represent this, which may be i64 or may be anything
2418 /// else that the backend will pass in a GPR that works better (e.g. i8, %foo*,
2421 /// PrefType is an LLVM IR type that corresponds to (part of) the IR type for
2422 /// the source type. IROffset is an offset in bytes into the LLVM IR type that
2423 /// the 8-byte value references. PrefType may be null.
2425 /// SourceTy is the source-level type for the entire argument. SourceOffset is
2426 /// an offset into this that we're processing (which is always either 0 or 8).
2428 llvm::Type *X86_64ABIInfo::
2429 GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
2430 QualType SourceTy, unsigned SourceOffset) const {
2431 // If we're dealing with an un-offset LLVM IR type, then it means that we're
2432 // returning an 8-byte unit starting with it. See if we can safely use it.
2433 if (IROffset == 0) {
2434 // Pointers and int64's always fill the 8-byte unit.
2435 if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) ||
2436 IRType->isIntegerTy(64))
2439 // If we have a 1/2/4-byte integer, we can use it only if the rest of the
2440 // goodness in the source type is just tail padding. This is allowed to
2441 // kick in for struct {double,int} on the int, but not on
2442 // struct{double,int,int} because we wouldn't return the second int. We
2443 // have to do this analysis on the source type because we can't depend on
2444 // unions being lowered a specific way etc.
2445 if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) ||
2446 IRType->isIntegerTy(32) ||
2447 (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) {
2448 unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 :
2449 cast<llvm::IntegerType>(IRType)->getBitWidth();
2451 if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth,
2452 SourceOffset*8+64, getContext()))
2457 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
2458 // If this is a struct, recurse into the field at the specified offset.
2459 const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy);
2460 if (IROffset < SL->getSizeInBytes()) {
2461 unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
2462 IROffset -= SL->getElementOffset(FieldIdx);
2464 return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
2465 SourceTy, SourceOffset);
2469 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
2470 llvm::Type *EltTy = ATy->getElementType();
2471 unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
2472 unsigned EltOffset = IROffset/EltSize*EltSize;
2473 return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
2477 // Okay, we don't have any better idea of what to pass, so we pass this in an
2478 // integer register that isn't too big to fit the rest of the struct.
2479 unsigned TySizeInBytes =
2480 (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity();
2482 assert(TySizeInBytes != SourceOffset && "Empty field?");
2484 // It is always safe to classify this as an integer type up to i64 that
2485 // isn't larger than the structure.
2486 return llvm::IntegerType::get(getVMContext(),
2487 std::min(TySizeInBytes-SourceOffset, 8U)*8);
2491 /// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
2492 /// be used as elements of a two register pair to pass or return, return a
2493 /// first class aggregate to represent them. For example, if the low part of
2494 /// a by-value argument should be passed as i32* and the high part as float,
2495 /// return {i32*, float}.
2497 GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi,
2498 const llvm::DataLayout &TD) {
2499 // In order to correctly satisfy the ABI, we need to the high part to start
2500 // at offset 8. If the high and low parts we inferred are both 4-byte types
2501 // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have
2502 // the second element at offset 8. Check for this:
2503 unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo);
2504 unsigned HiAlign = TD.getABITypeAlignment(Hi);
2505 unsigned HiStart = llvm::RoundUpToAlignment(LoSize, HiAlign);
2506 assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!");
2508 // To handle this, we have to increase the size of the low part so that the
2509 // second element will start at an 8 byte offset. We can't increase the size
2510 // of the second element because it might make us access off the end of the
2513 // There are usually two sorts of types the ABI generation code can produce
2514 // for the low part of a pair that aren't 8 bytes in size: float or
2515 // i8/i16/i32. This can also include pointers when they are 32-bit (X32 and
2517 // Promote these to a larger type.
2518 if (Lo->isFloatTy())
2519 Lo = llvm::Type::getDoubleTy(Lo->getContext());
2521 assert((Lo->isIntegerTy() || Lo->isPointerTy())
2522 && "Invalid/unknown lo type");
2523 Lo = llvm::Type::getInt64Ty(Lo->getContext());
2527 llvm::StructType *Result = llvm::StructType::get(Lo, Hi, nullptr);
2530 // Verify that the second element is at an 8-byte offset.
2531 assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
2532 "Invalid x86-64 argument pair!");
2536 ABIArgInfo X86_64ABIInfo::
2537 classifyReturnType(QualType RetTy) const {
2538 // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
2539 // classification algorithm.
2540 X86_64ABIInfo::Class Lo, Hi;
2541 classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);
2543 // Check some invariants.
2544 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
2545 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
2547 llvm::Type *ResType = nullptr;
2551 return ABIArgInfo::getIgnore();
2552 // If the low part is just padding, it takes no register, leave ResType
2554 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
2555 "Unknown missing lo part");
2560 llvm_unreachable("Invalid classification for lo word.");
2562 // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
2565 return getIndirectReturnResult(RetTy);
2567 // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
2568 // available register of the sequence %rax, %rdx is used.
2570 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
2572 // If we have a sign or zero extended integer, make sure to return Extend
2573 // so that the parameter gets the right LLVM IR attributes.
2574 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
2575 // Treat an enum type as its underlying type.
2576 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
2577 RetTy = EnumTy->getDecl()->getIntegerType();
2579 if (RetTy->isIntegralOrEnumerationType() &&
2580 RetTy->isPromotableIntegerType())
2581 return ABIArgInfo::getExtend();
2585 // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
2586 // available SSE register of the sequence %xmm0, %xmm1 is used.
2588 ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
2591 // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
2592 // returned on the X87 stack in %st0 as 80-bit x87 number.
2594 ResType = llvm::Type::getX86_FP80Ty(getVMContext());
2597 // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
2598 // part of the value is returned in %st0 and the imaginary part in
2601 assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.");
2602 ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()),
2603 llvm::Type::getX86_FP80Ty(getVMContext()),
2608 llvm::Type *HighPart = nullptr;
2610 // Memory was handled previously and X87 should
2611 // never occur as a hi class.
2614 llvm_unreachable("Invalid classification for hi word.");
2616 case ComplexX87: // Previously handled.
2621 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
2622 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
2623 return ABIArgInfo::getDirect(HighPart, 8);
2626 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
2627 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
2628 return ABIArgInfo::getDirect(HighPart, 8);
2631 // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
2632 // is passed in the next available eightbyte chunk if the last used
2635 // SSEUP should always be preceded by SSE, just widen.
2637 assert(Lo == SSE && "Unexpected SSEUp classification.");
2638 ResType = GetByteVectorType(RetTy);
2641 // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
2642 // returned together with the previous X87 value in %st0.
2644 // If X87Up is preceded by X87, we don't need to do
2645 // anything. However, in some cases with unions it may not be
2646 // preceded by X87. In such situations we follow gcc and pass the
2647 // extra bits in an SSE reg.
2649 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
2650 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
2651 return ABIArgInfo::getDirect(HighPart, 8);
2656 // If a high part was specified, merge it together with the low part. It is
2657 // known to pass in the high eightbyte of the result. We do this by forming a
2658 // first class struct aggregate with the high and low part: {low, high}
2660 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
2662 return ABIArgInfo::getDirect(ResType);
2665 ABIArgInfo X86_64ABIInfo::classifyArgumentType(
2666 QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE,
2670 Ty = useFirstFieldIfTransparentUnion(Ty);
2672 X86_64ABIInfo::Class Lo, Hi;
2673 classify(Ty, 0, Lo, Hi, isNamedArg);
2675 // Check some invariants.
2676 // FIXME: Enforce these by construction.
2677 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
2678 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
2682 llvm::Type *ResType = nullptr;
2686 return ABIArgInfo::getIgnore();
2687 // If the low part is just padding, it takes no register, leave ResType
2689 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
2690 "Unknown missing lo part");
2693 // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
2697 // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
2698 // COMPLEX_X87, it is passed in memory.
2701 if (getRecordArgABI(Ty, getCXXABI()) == CGCXXABI::RAA_Indirect)
2703 return getIndirectResult(Ty, freeIntRegs);
2707 llvm_unreachable("Invalid classification for lo word.");
2709 // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
2710 // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
2715 // Pick an 8-byte type based on the preferred type.
2716 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);
2718 // If we have a sign or zero extended integer, make sure to return Extend
2719 // so that the parameter gets the right LLVM IR attributes.
2720 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
2721 // Treat an enum type as its underlying type.
2722 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2723 Ty = EnumTy->getDecl()->getIntegerType();
2725 if (Ty->isIntegralOrEnumerationType() &&
2726 Ty->isPromotableIntegerType())
2727 return ABIArgInfo::getExtend();
2732 // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
2733 // available SSE register is used, the registers are taken in the
2734 // order from %xmm0 to %xmm7.
2736 llvm::Type *IRType = CGT.ConvertType(Ty);
2737 ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);
2743 llvm::Type *HighPart = nullptr;
2745 // Memory was handled previously, ComplexX87 and X87 should
2746 // never occur as hi classes, and X87Up must be preceded by X87,
2747 // which is passed in memory.
2751 llvm_unreachable("Invalid classification for hi word.");
2753 case NoClass: break;
2757 // Pick an 8-byte type based on the preferred type.
2758 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
2760 if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
2761 return ABIArgInfo::getDirect(HighPart, 8);
2764 // X87Up generally doesn't occur here (long double is passed in
2765 // memory), except in situations involving unions.
2768 HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
2770 if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
2771 return ABIArgInfo::getDirect(HighPart, 8);
2776 // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
2777 // eightbyte is passed in the upper half of the last used SSE
2778 // register. This only happens when 128-bit vectors are passed.
2780 assert(Lo == SSE && "Unexpected SSEUp classification");
2781 ResType = GetByteVectorType(Ty);
2785 // If a high part was specified, merge it together with the low part. It is
2786 // known to pass in the high eightbyte of the result. We do this by forming a
2787 // first class struct aggregate with the high and low part: {low, high}
2789 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
2791 return ABIArgInfo::getDirect(ResType);
2794 void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
2796 if (!getCXXABI().classifyReturnType(FI))
2797 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
2799 // Keep track of the number of assigned registers.
2800 unsigned freeIntRegs = 6, freeSSERegs = 8;
2802 // If the return value is indirect, then the hidden argument is consuming one
2803 // integer register.
2804 if (FI.getReturnInfo().isIndirect())
2807 // The chain argument effectively gives us another free register.
2808 if (FI.isChainCall())
2811 unsigned NumRequiredArgs = FI.getNumRequiredArgs();
2812 // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
2813 // get assigned (in left-to-right order) for passing as follows...
2815 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
2816 it != ie; ++it, ++ArgNo) {
2817 bool IsNamedArg = ArgNo < NumRequiredArgs;
2819 unsigned neededInt, neededSSE;
2820 it->info = classifyArgumentType(it->type, freeIntRegs, neededInt,
2821 neededSSE, IsNamedArg);
2823 // AMD64-ABI 3.2.3p3: If there are no registers available for any
2824 // eightbyte of an argument, the whole argument is passed on the
2825 // stack. If registers have already been assigned for some
2826 // eightbytes of such an argument, the assignments get reverted.
2827 if (freeIntRegs >= neededInt && freeSSERegs >= neededSSE) {
2828 freeIntRegs -= neededInt;
2829 freeSSERegs -= neededSSE;
2831 it->info = getIndirectResult(it->type, freeIntRegs);
2836 static llvm::Value *EmitVAArgFromMemory(llvm::Value *VAListAddr,
2838 CodeGenFunction &CGF) {
2839 llvm::Value *overflow_arg_area_p = CGF.Builder.CreateStructGEP(
2840 nullptr, VAListAddr, 2, "overflow_arg_area_p");
2841 llvm::Value *overflow_arg_area =
2842 CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area");
2844 // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
2845 // byte boundary if alignment needed by type exceeds 8 byte boundary.
2846 // It isn't stated explicitly in the standard, but in practice we use
2847 // alignment greater than 16 where necessary.
2848 uint64_t Align = CGF.getContext().getTypeAlign(Ty) / 8;
2850 // overflow_arg_area = (overflow_arg_area + align - 1) & -align;
2851 llvm::Value *Offset =
2852 llvm::ConstantInt::get(CGF.Int64Ty, Align - 1);
2853 overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset);
2854 llvm::Value *AsInt = CGF.Builder.CreatePtrToInt(overflow_arg_area,
2856 llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int64Ty, -(uint64_t)Align);
2858 CGF.Builder.CreateIntToPtr(CGF.Builder.CreateAnd(AsInt, Mask),
2859 overflow_arg_area->getType(),
2860 "overflow_arg_area.align");
2863 // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
2864 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
2866 CGF.Builder.CreateBitCast(overflow_arg_area,
2867 llvm::PointerType::getUnqual(LTy));
2869 // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
2870 // l->overflow_arg_area + sizeof(type).
2871 // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
2872 // an 8 byte boundary.
2874 uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8;
2875 llvm::Value *Offset =
2876 llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7);
2877 overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset,
2878 "overflow_arg_area.next");
2879 CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);
2881 // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
2885 llvm::Value *X86_64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
2886 CodeGenFunction &CGF) const {
2887 // Assume that va_list type is correct; should be pointer to LLVM type:
2891 // i8* overflow_arg_area;
2892 // i8* reg_save_area;
2894 unsigned neededInt, neededSSE;
2896 Ty = CGF.getContext().getCanonicalType(Ty);
2897 ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
2898 /*isNamedArg*/false);
2900 // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
2901 // in the registers. If not go to step 7.
2902 if (!neededInt && !neededSSE)
2903 return EmitVAArgFromMemory(VAListAddr, Ty, CGF);
2905 // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
2906 // general purpose registers needed to pass type and num_fp to hold
2907 // the number of floating point registers needed.
2909 // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
2910 // registers. In the case: l->gp_offset > 48 - num_gp * 8 or
2911 // l->fp_offset > 304 - num_fp * 16 go to step 7.
2913 // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of
2914 // register save space).
2916 llvm::Value *InRegs = nullptr;
2917 llvm::Value *gp_offset_p = nullptr, *gp_offset = nullptr;
2918 llvm::Value *fp_offset_p = nullptr, *fp_offset = nullptr;
2921 CGF.Builder.CreateStructGEP(nullptr, VAListAddr, 0, "gp_offset_p");
2922 gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset");
2923 InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
2924 InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp");
2929 CGF.Builder.CreateStructGEP(nullptr, VAListAddr, 1, "fp_offset_p");
2930 fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset");
2931 llvm::Value *FitsInFP =
2932 llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
2933 FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp");
2934 InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP;
2937 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
2938 llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
2939 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
2940 CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
2942 // Emit code to load the value if it was passed in registers.
2944 CGF.EmitBlock(InRegBlock);
2946 // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
2947 // an offset of l->gp_offset and/or l->fp_offset. This may require
2948 // copying to a temporary location in case the parameter is passed
2949 // in different register classes or requires an alignment greater
2950 // than 8 for general purpose registers and 16 for XMM registers.
2952 // FIXME: This really results in shameful code when we end up needing to
2953 // collect arguments from different places; often what should result in a
2954 // simple assembling of a structure from scattered addresses has many more
2955 // loads than necessary. Can we clean this up?
2956 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
2957 llvm::Value *RegAddr = CGF.Builder.CreateLoad(
2958 CGF.Builder.CreateStructGEP(nullptr, VAListAddr, 3), "reg_save_area");
2959 if (neededInt && neededSSE) {
2961 assert(AI.isDirect() && "Unexpected ABI info for mixed regs");
2962 llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType());
2963 llvm::Value *Tmp = CGF.CreateMemTemp(Ty);
2964 Tmp = CGF.Builder.CreateBitCast(Tmp, ST->getPointerTo());
2965 assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs");
2966 llvm::Type *TyLo = ST->getElementType(0);
2967 llvm::Type *TyHi = ST->getElementType(1);
2968 assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&
2969 "Unexpected ABI info for mixed regs");
2970 llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo);
2971 llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi);
2972 llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegAddr, gp_offset);
2973 llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegAddr, fp_offset);
2974 llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? FPAddr : GPAddr;
2975 llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? GPAddr : FPAddr;
2977 CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegLoAddr, PTyLo));
2978 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(ST, Tmp, 0));
2979 V = CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegHiAddr, PTyHi));
2980 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(ST, Tmp, 1));
2982 RegAddr = CGF.Builder.CreateBitCast(Tmp,
2983 llvm::PointerType::getUnqual(LTy));
2984 } else if (neededInt) {
2985 RegAddr = CGF.Builder.CreateGEP(RegAddr, gp_offset);
2986 RegAddr = CGF.Builder.CreateBitCast(RegAddr,
2987 llvm::PointerType::getUnqual(LTy));
2989 // Copy to a temporary if necessary to ensure the appropriate alignment.
2990 std::pair<CharUnits, CharUnits> SizeAlign =
2991 CGF.getContext().getTypeInfoInChars(Ty);
2992 uint64_t TySize = SizeAlign.first.getQuantity();
2993 unsigned TyAlign = SizeAlign.second.getQuantity();
2995 llvm::Value *Tmp = CGF.CreateMemTemp(Ty);
2996 CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, 8, false);
2999 } else if (neededSSE == 1) {
3000 RegAddr = CGF.Builder.CreateGEP(RegAddr, fp_offset);
3001 RegAddr = CGF.Builder.CreateBitCast(RegAddr,
3002 llvm::PointerType::getUnqual(LTy));
3004 assert(neededSSE == 2 && "Invalid number of needed registers!");
3005 // SSE registers are spaced 16 bytes apart in the register save
3006 // area, we need to collect the two eightbytes together.
3007 llvm::Value *RegAddrLo = CGF.Builder.CreateGEP(RegAddr, fp_offset);
3008 llvm::Value *RegAddrHi = CGF.Builder.CreateConstGEP1_32(RegAddrLo, 16);
3009 llvm::Type *DoubleTy = CGF.DoubleTy;
3010 llvm::Type *DblPtrTy =
3011 llvm::PointerType::getUnqual(DoubleTy);
3012 llvm::StructType *ST = llvm::StructType::get(DoubleTy, DoubleTy, nullptr);
3013 llvm::Value *V, *Tmp = CGF.CreateMemTemp(Ty);
3014 Tmp = CGF.Builder.CreateBitCast(Tmp, ST->getPointerTo());
3015 V = CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegAddrLo,
3017 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(ST, Tmp, 0));
3018 V = CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegAddrHi,
3020 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(ST, Tmp, 1));
3021 RegAddr = CGF.Builder.CreateBitCast(Tmp,
3022 llvm::PointerType::getUnqual(LTy));
3025 // AMD64-ABI 3.5.7p5: Step 5. Set:
3026 // l->gp_offset = l->gp_offset + num_gp * 8
3027 // l->fp_offset = l->fp_offset + num_fp * 16.
3029 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8);
3030 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset),
3034 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16);
3035 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset),
3038 CGF.EmitBranch(ContBlock);
3040 // Emit code to load the value if it was passed in memory.
3042 CGF.EmitBlock(InMemBlock);
3043 llvm::Value *MemAddr = EmitVAArgFromMemory(VAListAddr, Ty, CGF);
3045 // Return the appropriate result.
3047 CGF.EmitBlock(ContBlock);
3048 llvm::PHINode *ResAddr = CGF.Builder.CreatePHI(RegAddr->getType(), 2,
3050 ResAddr->addIncoming(RegAddr, InRegBlock);
3051 ResAddr->addIncoming(MemAddr, InMemBlock);
3055 ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
3056 bool IsReturnType) const {
3058 if (Ty->isVoidType())
3059 return ABIArgInfo::getIgnore();
3061 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3062 Ty = EnumTy->getDecl()->getIntegerType();
3064 TypeInfo Info = getContext().getTypeInfo(Ty);
3065 uint64_t Width = Info.Width;
3066 unsigned Align = getContext().toCharUnitsFromBits(Info.Align).getQuantity();
3068 const RecordType *RT = Ty->getAs<RecordType>();
3070 if (!IsReturnType) {
3071 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI()))
3072 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
3075 if (RT->getDecl()->hasFlexibleArrayMember())
3076 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
3079 // vectorcall adds the concept of a homogenous vector aggregate, similar to
3081 const Type *Base = nullptr;
3082 uint64_t NumElts = 0;
3083 if (FreeSSERegs && isHomogeneousAggregate(Ty, Base, NumElts)) {
3084 if (FreeSSERegs >= NumElts) {
3085 FreeSSERegs -= NumElts;
3086 if (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())
3087 return ABIArgInfo::getDirect();
3088 return ABIArgInfo::getExpand();
3090 return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3094 if (Ty->isMemberPointerType()) {
3095 // If the member pointer is represented by an LLVM int or ptr, pass it
3097 llvm::Type *LLTy = CGT.ConvertType(Ty);
3098 if (LLTy->isPointerTy() || LLTy->isIntegerTy())
3099 return ABIArgInfo::getDirect();
3102 if (RT || Ty->isAnyComplexType() || Ty->isMemberPointerType()) {
3103 // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
3104 // not 1, 2, 4, or 8 bytes, must be passed by reference."
3105 if (Width > 64 || !llvm::isPowerOf2_64(Width))
3106 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
3108 // Otherwise, coerce it to a small integer.
3109 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width));
3112 // Bool type is always extended to the ABI, other builtin types are not
3114 const BuiltinType *BT = Ty->getAs<BuiltinType>();
3115 if (BT && BT->getKind() == BuiltinType::Bool)
3116 return ABIArgInfo::getExtend();
3118 // Mingw64 GCC uses the old 80 bit extended precision floating point unit. It
3119 // passes them indirectly through memory.
3120 if (IsMingw64 && BT && BT->getKind() == BuiltinType::LongDouble) {
3121 const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
3122 if (LDF == &llvm::APFloat::x87DoubleExtended)
3123 return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3126 return ABIArgInfo::getDirect();
3129 void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3131 FI.getCallingConvention() == llvm::CallingConv::X86_VectorCall;
3133 // We can use up to 4 SSE return registers with vectorcall.
3134 unsigned FreeSSERegs = IsVectorCall ? 4 : 0;
3135 if (!getCXXABI().classifyReturnType(FI))
3136 FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true);
3138 // We can use up to 6 SSE register parameters with vectorcall.
3139 FreeSSERegs = IsVectorCall ? 6 : 0;
3140 for (auto &I : FI.arguments())
3141 I.info = classify(I.type, FreeSSERegs, false);
3144 llvm::Value *WinX86_64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
3145 CodeGenFunction &CGF) const {
3146 llvm::Type *BPP = CGF.Int8PtrPtrTy;
3148 CGBuilderTy &Builder = CGF.Builder;
3149 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP,
3151 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur");
3153 llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
3154 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy);
3157 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, 8);
3158 llvm::Value *NextAddr =
3159 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset),
3161 Builder.CreateStore(NextAddr, VAListAddrAsBPP);
3168 /// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
3169 class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
3171 PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
3173 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
3174 CodeGenFunction &CGF) const override;
3177 class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
3179 PPC32TargetCodeGenInfo(CodeGenTypes &CGT)
3180 : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT)) {}
3182 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
3183 // This is recovered from gcc output.
3184 return 1; // r1 is the dedicated stack pointer
3187 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3188 llvm::Value *Address) const override;
3193 llvm::Value *PPC32_SVR4_ABIInfo::EmitVAArg(llvm::Value *VAListAddr,
3195 CodeGenFunction &CGF) const {
3196 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
3197 // TODO: Implement this. For now ignore.
3202 bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;
3204 Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType();
3205 llvm::Type *CharPtr = CGF.Int8PtrTy;
3206 llvm::Type *CharPtrPtr = CGF.Int8PtrPtrTy;
3208 CGBuilderTy &Builder = CGF.Builder;
3209 llvm::Value *GPRPtr = Builder.CreateBitCast(VAListAddr, CharPtr, "gprptr");
3210 llvm::Value *GPRPtrAsInt = Builder.CreatePtrToInt(GPRPtr, CGF.Int32Ty);
3211 llvm::Value *FPRPtrAsInt =
3212 Builder.CreateAdd(GPRPtrAsInt, Builder.getInt32(1));
3213 llvm::Value *FPRPtr = Builder.CreateIntToPtr(FPRPtrAsInt, CharPtr);
3214 llvm::Value *OverflowAreaPtrAsInt =
3215 Builder.CreateAdd(FPRPtrAsInt, Builder.getInt32(3));
3216 llvm::Value *OverflowAreaPtr =
3217 Builder.CreateIntToPtr(OverflowAreaPtrAsInt, CharPtrPtr);
3218 llvm::Value *RegsaveAreaPtrAsInt =
3219 Builder.CreateAdd(OverflowAreaPtrAsInt, Builder.getInt32(4));
3220 llvm::Value *RegsaveAreaPtr =
3221 Builder.CreateIntToPtr(RegsaveAreaPtrAsInt, CharPtrPtr);
3222 llvm::Value *GPR = Builder.CreateLoad(GPRPtr, false, "gpr");
3223 // Align GPR when TY is i64.
3225 llvm::Value *GPRAnd = Builder.CreateAnd(GPR, Builder.getInt8(1));
3226 llvm::Value *CC64 = Builder.CreateICmpEQ(GPRAnd, Builder.getInt8(1));
3227 llvm::Value *GPRPlusOne = Builder.CreateAdd(GPR, Builder.getInt8(1));
3228 GPR = Builder.CreateSelect(CC64, GPRPlusOne, GPR);
3230 llvm::Value *FPR = Builder.CreateLoad(FPRPtr, false, "fpr");
3231 llvm::Value *OverflowArea =
3232 Builder.CreateLoad(OverflowAreaPtr, false, "overflow_area");
3233 llvm::Value *OverflowAreaAsInt =
3234 Builder.CreatePtrToInt(OverflowArea, CGF.Int32Ty);
3235 llvm::Value *RegsaveArea =
3236 Builder.CreateLoad(RegsaveAreaPtr, false, "regsave_area");
3237 llvm::Value *RegsaveAreaAsInt =
3238 Builder.CreatePtrToInt(RegsaveArea, CGF.Int32Ty);
3241 Builder.CreateICmpULT(isInt ? GPR : FPR, Builder.getInt8(8), "cond");
3243 llvm::Value *RegConstant =
3244 Builder.CreateMul(isInt ? GPR : FPR, Builder.getInt8(isInt ? 4 : 8));
3246 llvm::Value *OurReg = Builder.CreateAdd(
3247 RegsaveAreaAsInt, Builder.CreateSExt(RegConstant, CGF.Int32Ty));
3249 if (Ty->isFloatingType())
3250 OurReg = Builder.CreateAdd(OurReg, Builder.getInt32(32));
3252 llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
3253 llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
3254 llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
3256 Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
3258 CGF.EmitBlock(UsingRegs);
3260 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
3261 llvm::Value *Result1 = Builder.CreateIntToPtr(OurReg, PTy);
3262 // Increase the GPR/FPR indexes.
3264 GPR = Builder.CreateAdd(GPR, Builder.getInt8(isI64 ? 2 : 1));
3265 Builder.CreateStore(GPR, GPRPtr);
3267 FPR = Builder.CreateAdd(FPR, Builder.getInt8(1));
3268 Builder.CreateStore(FPR, FPRPtr);
3270 CGF.EmitBranch(Cont);
3272 CGF.EmitBlock(UsingOverflow);
3274 // Increase the overflow area.
3275 llvm::Value *Result2 = Builder.CreateIntToPtr(OverflowAreaAsInt, PTy);
3277 Builder.CreateAdd(OverflowAreaAsInt, Builder.getInt32(isInt ? 4 : 8));
3278 Builder.CreateStore(Builder.CreateIntToPtr(OverflowAreaAsInt, CharPtr),
3280 CGF.EmitBranch(Cont);
3282 CGF.EmitBlock(Cont);
3284 llvm::PHINode *Result = CGF.Builder.CreatePHI(PTy, 2, "vaarg.addr");
3285 Result->addIncoming(Result1, UsingRegs);
3286 Result->addIncoming(Result2, UsingOverflow);
3288 if (Ty->isAggregateType()) {
3289 llvm::Value *AGGPtr = Builder.CreateBitCast(Result, CharPtrPtr, "aggrptr");
3290 return Builder.CreateLoad(AGGPtr, false, "aggr");
3297 PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3298 llvm::Value *Address) const {
3299 // This is calculated from the LLVM and GCC tables and verified
3300 // against gcc output. AFAIK all ABIs use the same encoding.
3302 CodeGen::CGBuilderTy &Builder = CGF.Builder;
3304 llvm::IntegerType *i8 = CGF.Int8Ty;
3305 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
3306 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
3307 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
3309 // 0-31: r0-31, the 4-byte general-purpose registers
3310 AssignToArrayRange(Builder, Address, Four8, 0, 31);
3312 // 32-63: fp0-31, the 8-byte floating-point registers
3313 AssignToArrayRange(Builder, Address, Eight8, 32, 63);
3315 // 64-76 are various 4-byte special-purpose registers:
3322 AssignToArrayRange(Builder, Address, Four8, 64, 76);
3324 // 77-108: v0-31, the 16-byte vector registers
3325 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
3332 AssignToArrayRange(Builder, Address, Four8, 109, 113);
3340 /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
3341 class PPC64_SVR4_ABIInfo : public DefaultABIInfo {
3349 static const unsigned GPRBits = 64;
3353 // A vector of float or double will be promoted to <4 x f32> or <4 x f64> and
3354 // will be passed in a QPX register.
3355 bool IsQPXVectorTy(const Type *Ty) const {
3359 if (const VectorType *VT = Ty->getAs<VectorType>()) {
3360 unsigned NumElements = VT->getNumElements();
3361 if (NumElements == 1)
3364 if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) {
3365 if (getContext().getTypeSize(Ty) <= 256)
3367 } else if (VT->getElementType()->
3368 isSpecificBuiltinType(BuiltinType::Float)) {
3369 if (getContext().getTypeSize(Ty) <= 128)
3377 bool IsQPXVectorTy(QualType Ty) const {
3378 return IsQPXVectorTy(Ty.getTypePtr());
3382 PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX)
3383 : DefaultABIInfo(CGT), Kind(Kind), HasQPX(HasQPX) {}
3385 bool isPromotableTypeForABI(QualType Ty) const;
3386 bool isAlignedParamType(QualType Ty, bool &Align32) const;
3388 ABIArgInfo classifyReturnType(QualType RetTy) const;
3389 ABIArgInfo classifyArgumentType(QualType Ty) const;
3391 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
3392 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
3393 uint64_t Members) const override;
3395 // TODO: We can add more logic to computeInfo to improve performance.
3396 // Example: For aggregate arguments that fit in a register, we could
3397 // use getDirectInReg (as is done below for structs containing a single
3398 // floating-point value) to avoid pushing them to memory on function
3399 // entry. This would require changing the logic in PPCISelLowering
3400 // when lowering the parameters in the caller and args in the callee.
3401 void computeInfo(CGFunctionInfo &FI) const override {
3402 if (!getCXXABI().classifyReturnType(FI))
3403 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
3404 for (auto &I : FI.arguments()) {
3405 // We rely on the default argument classification for the most part.
3406 // One exception: An aggregate containing a single floating-point
3407 // or vector item must be passed in a register if one is available.
3408 const Type *T = isSingleElementStruct(I.type, getContext());
3410 const BuiltinType *BT = T->getAs<BuiltinType>();
3411 if (IsQPXVectorTy(T) ||
3412 (T->isVectorType() && getContext().getTypeSize(T) == 128) ||
3413 (BT && BT->isFloatingPoint())) {
3415 I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
3419 I.info = classifyArgumentType(I.type);
3423 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
3424 CodeGenFunction &CGF) const override;
3427 class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
3430 PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT,
3431 PPC64_SVR4_ABIInfo::ABIKind Kind, bool HasQPX)
3432 : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT, Kind, HasQPX)) {}
3434 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
3435 // This is recovered from gcc output.
3436 return 1; // r1 is the dedicated stack pointer
3439 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3440 llvm::Value *Address) const override;
3443 class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
3445 PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
3447 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
3448 // This is recovered from gcc output.
3449 return 1; // r1 is the dedicated stack pointer
3452 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3453 llvm::Value *Address) const override;
3458 // Return true if the ABI requires Ty to be passed sign- or zero-
3459 // extended to 64 bits.
3461 PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
3462 // Treat an enum type as its underlying type.
3463 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3464 Ty = EnumTy->getDecl()->getIntegerType();
3466 // Promotable integer types are required to be promoted by the ABI.
3467 if (Ty->isPromotableIntegerType())
3470 // In addition to the usual promotable integer types, we also need to
3471 // extend all 32-bit types, since the ABI requires promotion to 64 bits.
3472 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
3473 switch (BT->getKind()) {
3474 case BuiltinType::Int:
3475 case BuiltinType::UInt:
3484 /// isAlignedParamType - Determine whether a type requires 16-byte
3485 /// alignment in the parameter area.
3487 PPC64_SVR4_ABIInfo::isAlignedParamType(QualType Ty, bool &Align32) const {
3490 // Complex types are passed just like their elements.
3491 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
3492 Ty = CTy->getElementType();
3494 // Only vector types of size 16 bytes need alignment (larger types are
3495 // passed via reference, smaller types are not aligned).
3496 if (IsQPXVectorTy(Ty)) {
3497 if (getContext().getTypeSize(Ty) > 128)
3501 } else if (Ty->isVectorType()) {
3502 return getContext().getTypeSize(Ty) == 128;
3505 // For single-element float/vector structs, we consider the whole type
3506 // to have the same alignment requirements as its single element.
3507 const Type *AlignAsType = nullptr;
3508 const Type *EltType = isSingleElementStruct(Ty, getContext());
3510 const BuiltinType *BT = EltType->getAs<BuiltinType>();
3511 if (IsQPXVectorTy(EltType) || (EltType->isVectorType() &&
3512 getContext().getTypeSize(EltType) == 128) ||
3513 (BT && BT->isFloatingPoint()))
3514 AlignAsType = EltType;
3517 // Likewise for ELFv2 homogeneous aggregates.
3518 const Type *Base = nullptr;
3519 uint64_t Members = 0;
3520 if (!AlignAsType && Kind == ELFv2 &&
3521 isAggregateTypeForABI(Ty) && isHomogeneousAggregate(Ty, Base, Members))
3524 // With special case aggregates, only vector base types need alignment.
3525 if (AlignAsType && IsQPXVectorTy(AlignAsType)) {
3526 if (getContext().getTypeSize(AlignAsType) > 128)
3530 } else if (AlignAsType) {
3531 return AlignAsType->isVectorType();
3534 // Otherwise, we only need alignment for any aggregate type that
3535 // has an alignment requirement of >= 16 bytes.
3536 if (isAggregateTypeForABI(Ty) && getContext().getTypeAlign(Ty) >= 128) {
3537 if (HasQPX && getContext().getTypeAlign(Ty) >= 256)
3545 /// isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous
3546 /// aggregate. Base is set to the base element type, and Members is set
3547 /// to the number of base elements.
3548 bool ABIInfo::isHomogeneousAggregate(QualType Ty, const Type *&Base,
3549 uint64_t &Members) const {
3550 if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
3551 uint64_t NElements = AT->getSize().getZExtValue();
3554 if (!isHomogeneousAggregate(AT->getElementType(), Base, Members))
3556 Members *= NElements;
3557 } else if (const RecordType *RT = Ty->getAs<RecordType>()) {
3558 const RecordDecl *RD = RT->getDecl();
3559 if (RD->hasFlexibleArrayMember())
3564 // If this is a C++ record, check the bases first.
3565 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
3566 for (const auto &I : CXXRD->bases()) {
3567 // Ignore empty records.
3568 if (isEmptyRecord(getContext(), I.getType(), true))
3571 uint64_t FldMembers;
3572 if (!isHomogeneousAggregate(I.getType(), Base, FldMembers))
3575 Members += FldMembers;
3579 for (const auto *FD : RD->fields()) {
3580 // Ignore (non-zero arrays of) empty records.
3581 QualType FT = FD->getType();
3582 while (const ConstantArrayType *AT =
3583 getContext().getAsConstantArrayType(FT)) {
3584 if (AT->getSize().getZExtValue() == 0)
3586 FT = AT->getElementType();
3588 if (isEmptyRecord(getContext(), FT, true))
3591 // For compatibility with GCC, ignore empty bitfields in C++ mode.
3592 if (getContext().getLangOpts().CPlusPlus &&
3593 FD->isBitField() && FD->getBitWidthValue(getContext()) == 0)
3596 uint64_t FldMembers;
3597 if (!isHomogeneousAggregate(FD->getType(), Base, FldMembers))
3600 Members = (RD->isUnion() ?
3601 std::max(Members, FldMembers) : Members + FldMembers);
3607 // Ensure there is no padding.
3608 if (getContext().getTypeSize(Base) * Members !=
3609 getContext().getTypeSize(Ty))
3613 if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
3615 Ty = CT->getElementType();
3618 // Most ABIs only support float, double, and some vector type widths.
3619 if (!isHomogeneousAggregateBaseType(Ty))
3622 // The base type must be the same for all members. Types that
3623 // agree in both total size and mode (float vs. vector) are
3624 // treated as being equivalent here.
3625 const Type *TyPtr = Ty.getTypePtr();
3629 if (Base->isVectorType() != TyPtr->isVectorType() ||
3630 getContext().getTypeSize(Base) != getContext().getTypeSize(TyPtr))
3633 return Members > 0 && isHomogeneousAggregateSmallEnough(Base, Members);
3636 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
3637 // Homogeneous aggregates for ELFv2 must have base types of float,
3638 // double, long double, or 128-bit vectors.
3639 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
3640 if (BT->getKind() == BuiltinType::Float ||
3641 BT->getKind() == BuiltinType::Double ||
3642 BT->getKind() == BuiltinType::LongDouble)
3645 if (const VectorType *VT = Ty->getAs<VectorType>()) {
3646 if (getContext().getTypeSize(VT) == 128 || IsQPXVectorTy(Ty))
3652 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
3653 const Type *Base, uint64_t Members) const {
3654 // Vector types require one register, floating point types require one
3655 // or two registers depending on their size.
3657 Base->isVectorType() ? 1 : (getContext().getTypeSize(Base) + 63) / 64;
3659 // Homogeneous Aggregates may occupy at most 8 registers.
3660 return Members * NumRegs <= 8;
3664 PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
3665 Ty = useFirstFieldIfTransparentUnion(Ty);
3667 if (Ty->isAnyComplexType())
3668 return ABIArgInfo::getDirect();
3670 // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
3671 // or via reference (larger than 16 bytes).
3672 if (Ty->isVectorType() && !IsQPXVectorTy(Ty)) {
3673 uint64_t Size = getContext().getTypeSize(Ty);
3675 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
3676 else if (Size < 128) {
3677 llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
3678 return ABIArgInfo::getDirect(CoerceTy);
3682 if (isAggregateTypeForABI(Ty)) {
3683 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
3684 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
3687 uint64_t ABIAlign = isAlignedParamType(Ty, Align32) ?
3688 (Align32 ? 32 : 16) : 8;
3689 uint64_t TyAlign = getContext().getTypeAlign(Ty) / 8;
3691 // ELFv2 homogeneous aggregates are passed as array types.
3692 const Type *Base = nullptr;
3693 uint64_t Members = 0;
3694 if (Kind == ELFv2 &&
3695 isHomogeneousAggregate(Ty, Base, Members)) {
3696 llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
3697 llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
3698 return ABIArgInfo::getDirect(CoerceTy);
3701 // If an aggregate may end up fully in registers, we do not
3702 // use the ByVal method, but pass the aggregate as array.
3703 // This is usually beneficial since we avoid forcing the
3704 // back-end to store the argument to memory.
3705 uint64_t Bits = getContext().getTypeSize(Ty);
3706 if (Bits > 0 && Bits <= 8 * GPRBits) {
3707 llvm::Type *CoerceTy;
3709 // Types up to 8 bytes are passed as integer type (which will be
3710 // properly aligned in the argument save area doubleword).
3711 if (Bits <= GPRBits)
3712 CoerceTy = llvm::IntegerType::get(getVMContext(),
3713 llvm::RoundUpToAlignment(Bits, 8));
3714 // Larger types are passed as arrays, with the base type selected
3715 // according to the required alignment in the save area.
3717 uint64_t RegBits = ABIAlign * 8;
3718 uint64_t NumRegs = llvm::RoundUpToAlignment(Bits, RegBits) / RegBits;
3719 llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits);
3720 CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);
3723 return ABIArgInfo::getDirect(CoerceTy);
3726 // All other aggregates are passed ByVal.
3727 return ABIArgInfo::getIndirect(ABIAlign, /*ByVal=*/true,
3728 /*Realign=*/TyAlign > ABIAlign);
3731 return (isPromotableTypeForABI(Ty) ?
3732 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
3736 PPC64_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {
3737 if (RetTy->isVoidType())
3738 return ABIArgInfo::getIgnore();
3740 if (RetTy->isAnyComplexType())
3741 return ABIArgInfo::getDirect();
3743 // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
3744 // or via reference (larger than 16 bytes).
3745 if (RetTy->isVectorType() && !IsQPXVectorTy(RetTy)) {
3746 uint64_t Size = getContext().getTypeSize(RetTy);
3748 return ABIArgInfo::getIndirect(0);
3749 else if (Size < 128) {
3750 llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
3751 return ABIArgInfo::getDirect(CoerceTy);
3755 if (isAggregateTypeForABI(RetTy)) {
3756 // ELFv2 homogeneous aggregates are returned as array types.
3757 const Type *Base = nullptr;
3758 uint64_t Members = 0;
3759 if (Kind == ELFv2 &&
3760 isHomogeneousAggregate(RetTy, Base, Members)) {
3761 llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
3762 llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
3763 return ABIArgInfo::getDirect(CoerceTy);
3766 // ELFv2 small aggregates are returned in up to two registers.
3767 uint64_t Bits = getContext().getTypeSize(RetTy);
3768 if (Kind == ELFv2 && Bits <= 2 * GPRBits) {
3770 return ABIArgInfo::getIgnore();
3772 llvm::Type *CoerceTy;
3773 if (Bits > GPRBits) {
3774 CoerceTy = llvm::IntegerType::get(getVMContext(), GPRBits);
3775 CoerceTy = llvm::StructType::get(CoerceTy, CoerceTy, nullptr);
3777 CoerceTy = llvm::IntegerType::get(getVMContext(),
3778 llvm::RoundUpToAlignment(Bits, 8));
3779 return ABIArgInfo::getDirect(CoerceTy);
3782 // All other aggregates are returned indirectly.
3783 return ABIArgInfo::getIndirect(0);
3786 return (isPromotableTypeForABI(RetTy) ?
3787 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
3790 // Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
3791 llvm::Value *PPC64_SVR4_ABIInfo::EmitVAArg(llvm::Value *VAListAddr,
3793 CodeGenFunction &CGF) const {
3794 llvm::Type *BP = CGF.Int8PtrTy;
3795 llvm::Type *BPP = CGF.Int8PtrPtrTy;
3797 CGBuilderTy &Builder = CGF.Builder;
3798 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap");
3799 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur");
3801 // Handle types that require 16-byte alignment in the parameter save area.
3803 if (isAlignedParamType(Ty, Align32)) {
3804 llvm::Value *AddrAsInt = Builder.CreatePtrToInt(Addr, CGF.Int64Ty);
3805 AddrAsInt = Builder.CreateAdd(AddrAsInt,
3806 Builder.getInt64(Align32 ? 31 : 15));
3807 AddrAsInt = Builder.CreateAnd(AddrAsInt,
3808 Builder.getInt64(Align32 ? -32 : -16));
3809 Addr = Builder.CreateIntToPtr(AddrAsInt, BP, "ap.align");
3812 // Update the va_list pointer. The pointer should be bumped by the
3813 // size of the object. We can trust getTypeSize() except for a complex
3814 // type whose base type is smaller than a doubleword. For these, the
3815 // size of the object is 16 bytes; see below for further explanation.
3816 unsigned SizeInBytes = CGF.getContext().getTypeSize(Ty) / 8;
3818 unsigned CplxBaseSize = 0;
3820 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
3821 BaseTy = CTy->getElementType();
3822 CplxBaseSize = CGF.getContext().getTypeSize(BaseTy) / 8;
3823 if (CplxBaseSize < 8)
3827 unsigned Offset = llvm::RoundUpToAlignment(SizeInBytes, 8);
3828 llvm::Value *NextAddr =
3829 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int64Ty, Offset),
3831 Builder.CreateStore(NextAddr, VAListAddrAsBPP);
3833 // If we have a complex type and the base type is smaller than 8 bytes,
3834 // the ABI calls for the real and imaginary parts to be right-adjusted
3835 // in separate doublewords. However, Clang expects us to produce a
3836 // pointer to a structure with the two parts packed tightly. So generate
3837 // loads of the real and imaginary parts relative to the va_list pointer,
3838 // and store them to a temporary structure.
3839 if (CplxBaseSize && CplxBaseSize < 8) {
3840 llvm::Value *RealAddr = Builder.CreatePtrToInt(Addr, CGF.Int64Ty);
3841 llvm::Value *ImagAddr = RealAddr;
3842 if (CGF.CGM.getDataLayout().isBigEndian()) {
3844 Builder.CreateAdd(RealAddr, Builder.getInt64(8 - CplxBaseSize));
3846 Builder.CreateAdd(ImagAddr, Builder.getInt64(16 - CplxBaseSize));
3848 ImagAddr = Builder.CreateAdd(ImagAddr, Builder.getInt64(8));
3850 llvm::Type *PBaseTy = llvm::PointerType::getUnqual(CGF.ConvertType(BaseTy));
3851 RealAddr = Builder.CreateIntToPtr(RealAddr, PBaseTy);
3852 ImagAddr = Builder.CreateIntToPtr(ImagAddr, PBaseTy);
3853 llvm::Value *Real = Builder.CreateLoad(RealAddr, false, ".vareal");
3854 llvm::Value *Imag = Builder.CreateLoad(ImagAddr, false, ".vaimag");
3855 llvm::AllocaInst *Ptr =
3856 CGF.CreateTempAlloca(CGT.ConvertTypeForMem(Ty), "vacplx");
3857 llvm::Value *RealPtr =
3858 Builder.CreateStructGEP(Ptr->getAllocatedType(), Ptr, 0, ".real");
3859 llvm::Value *ImagPtr =
3860 Builder.CreateStructGEP(Ptr->getAllocatedType(), Ptr, 1, ".imag");
3861 Builder.CreateStore(Real, RealPtr, false);
3862 Builder.CreateStore(Imag, ImagPtr, false);
3866 // If the argument is smaller than 8 bytes, it is right-adjusted in
3867 // its doubleword slot. Adjust the pointer to pick it up from the
3869 if (SizeInBytes < 8 && CGF.CGM.getDataLayout().isBigEndian()) {
3870 llvm::Value *AddrAsInt = Builder.CreatePtrToInt(Addr, CGF.Int64Ty);
3871 AddrAsInt = Builder.CreateAdd(AddrAsInt, Builder.getInt64(8 - SizeInBytes));
3872 Addr = Builder.CreateIntToPtr(AddrAsInt, BP);
3875 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
3876 return Builder.CreateBitCast(Addr, PTy);
3880 PPC64_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3881 llvm::Value *Address) {
3882 // This is calculated from the LLVM and GCC tables and verified
3883 // against gcc output. AFAIK all ABIs use the same encoding.
3885 CodeGen::CGBuilderTy &Builder = CGF.Builder;
3887 llvm::IntegerType *i8 = CGF.Int8Ty;
3888 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
3889 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
3890 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
3892 // 0-31: r0-31, the 8-byte general-purpose registers
3893 AssignToArrayRange(Builder, Address, Eight8, 0, 31);
3895 // 32-63: fp0-31, the 8-byte floating-point registers
3896 AssignToArrayRange(Builder, Address, Eight8, 32, 63);
3898 // 64-76 are various 4-byte special-purpose registers:
3905 AssignToArrayRange(Builder, Address, Four8, 64, 76);
3907 // 77-108: v0-31, the 16-byte vector registers
3908 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
3915 AssignToArrayRange(Builder, Address, Four8, 109, 113);
3921 PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
3922 CodeGen::CodeGenFunction &CGF,
3923 llvm::Value *Address) const {
3925 return PPC64_initDwarfEHRegSizeTable(CGF, Address);
3929 PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3930 llvm::Value *Address) const {
3932 return PPC64_initDwarfEHRegSizeTable(CGF, Address);
3935 //===----------------------------------------------------------------------===//
3936 // AArch64 ABI Implementation
3937 //===----------------------------------------------------------------------===//
3941 class AArch64ABIInfo : public ABIInfo {
3952 AArch64ABIInfo(CodeGenTypes &CGT, ABIKind Kind) : ABIInfo(CGT), Kind(Kind) {}
3955 ABIKind getABIKind() const { return Kind; }
3956 bool isDarwinPCS() const { return Kind == DarwinPCS; }
3958 ABIArgInfo classifyReturnType(QualType RetTy) const;
3959 ABIArgInfo classifyArgumentType(QualType RetTy) const;
3960 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
3961 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
3962 uint64_t Members) const override;
3964 bool isIllegalVectorType(QualType Ty) const;
3966 void computeInfo(CGFunctionInfo &FI) const override {
3967 if (!getCXXABI().classifyReturnType(FI))
3968 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
3970 for (auto &it : FI.arguments())
3971 it.info = classifyArgumentType(it.type);
3974 llvm::Value *EmitDarwinVAArg(llvm::Value *VAListAddr, QualType Ty,
3975 CodeGenFunction &CGF) const;
3977 llvm::Value *EmitAAPCSVAArg(llvm::Value *VAListAddr, QualType Ty,
3978 CodeGenFunction &CGF) const;
3980 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
3981 CodeGenFunction &CGF) const override {
3982 return isDarwinPCS() ? EmitDarwinVAArg(VAListAddr, Ty, CGF)
3983 : EmitAAPCSVAArg(VAListAddr, Ty, CGF);
3987 class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
3989 AArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind Kind)
3990 : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
3992 StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
3993 return "mov\tfp, fp\t\t; marker for objc_retainAutoreleaseReturnValue";
3996 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4000 bool doesReturnSlotInterfereWithArgs() const override { return false; }
4004 ABIArgInfo AArch64ABIInfo::classifyArgumentType(QualType Ty) const {
4005 Ty = useFirstFieldIfTransparentUnion(Ty);
4007 // Handle illegal vector types here.
4008 if (isIllegalVectorType(Ty)) {
4009 uint64_t Size = getContext().getTypeSize(Ty);
4011 llvm::Type *ResType = llvm::Type::getInt32Ty(getVMContext());
4012 return ABIArgInfo::getDirect(ResType);
4015 llvm::Type *ResType =
4016 llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 2);
4017 return ABIArgInfo::getDirect(ResType);
4020 llvm::Type *ResType =
4021 llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 4);
4022 return ABIArgInfo::getDirect(ResType);
4024 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
4027 if (!isAggregateTypeForABI(Ty)) {
4028 // Treat an enum type as its underlying type.
4029 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4030 Ty = EnumTy->getDecl()->getIntegerType();
4032 return (Ty->isPromotableIntegerType() && isDarwinPCS()
4033 ? ABIArgInfo::getExtend()
4034 : ABIArgInfo::getDirect());
4037 // Structures with either a non-trivial destructor or a non-trivial
4038 // copy constructor are always indirect.
4039 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
4040 return ABIArgInfo::getIndirect(0, /*ByVal=*/RAA ==
4041 CGCXXABI::RAA_DirectInMemory);
4044 // Empty records are always ignored on Darwin, but actually passed in C++ mode
4045 // elsewhere for GNU compatibility.
4046 if (isEmptyRecord(getContext(), Ty, true)) {
4047 if (!getContext().getLangOpts().CPlusPlus || isDarwinPCS())
4048 return ABIArgInfo::getIgnore();
4050 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
4053 // Homogeneous Floating-point Aggregates (HFAs) need to be expanded.
4054 const Type *Base = nullptr;
4055 uint64_t Members = 0;
4056 if (isHomogeneousAggregate(Ty, Base, Members)) {
4057 return ABIArgInfo::getDirect(
4058 llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members));
4061 // Aggregates <= 16 bytes are passed directly in registers or on the stack.
4062 uint64_t Size = getContext().getTypeSize(Ty);
4064 unsigned Alignment = getContext().getTypeAlign(Ty);
4065 Size = 64 * ((Size + 63) / 64); // round up to multiple of 8 bytes
4067 // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
4068 // For aggregates with 16-byte alignment, we use i128.
4069 if (Alignment < 128 && Size == 128) {
4070 llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
4071 return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
4073 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
4076 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
4079 ABIArgInfo AArch64ABIInfo::classifyReturnType(QualType RetTy) const {
4080 if (RetTy->isVoidType())
4081 return ABIArgInfo::getIgnore();
4083 // Large vector types should be returned via memory.
4084 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128)
4085 return ABIArgInfo::getIndirect(0);
4087 if (!isAggregateTypeForABI(RetTy)) {
4088 // Treat an enum type as its underlying type.
4089 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
4090 RetTy = EnumTy->getDecl()->getIntegerType();
4092 return (RetTy->isPromotableIntegerType() && isDarwinPCS()
4093 ? ABIArgInfo::getExtend()
4094 : ABIArgInfo::getDirect());
4097 if (isEmptyRecord(getContext(), RetTy, true))
4098 return ABIArgInfo::getIgnore();
4100 const Type *Base = nullptr;
4101 uint64_t Members = 0;
4102 if (isHomogeneousAggregate(RetTy, Base, Members))
4103 // Homogeneous Floating-point Aggregates (HFAs) are returned directly.
4104 return ABIArgInfo::getDirect();
4106 // Aggregates <= 16 bytes are returned directly in registers or on the stack.
4107 uint64_t Size = getContext().getTypeSize(RetTy);
4109 unsigned Alignment = getContext().getTypeAlign(RetTy);
4110 Size = 64 * ((Size + 63) / 64); // round up to multiple of 8 bytes
4112 // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
4113 // For aggregates with 16-byte alignment, we use i128.
4114 if (Alignment < 128 && Size == 128) {
4115 llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
4116 return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
4118 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
4121 return ABIArgInfo::getIndirect(0);
4124 /// isIllegalVectorType - check whether the vector type is legal for AArch64.
4125 bool AArch64ABIInfo::isIllegalVectorType(QualType Ty) const {
4126 if (const VectorType *VT = Ty->getAs<VectorType>()) {
4127 // Check whether VT is legal.
4128 unsigned NumElements = VT->getNumElements();
4129 uint64_t Size = getContext().getTypeSize(VT);
4130 // NumElements should be power of 2 between 1 and 16.
4131 if ((NumElements & (NumElements - 1)) != 0 || NumElements > 16)
4133 return Size != 64 && (Size != 128 || NumElements == 1);
4138 bool AArch64ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
4139 // Homogeneous aggregates for AAPCS64 must have base types of a floating
4140 // point type or a short-vector type. This is the same as the 32-bit ABI,
4141 // but with the difference that any floating-point type is allowed,
4142 // including __fp16.
4143 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4144 if (BT->isFloatingPoint())
4146 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
4147 unsigned VecSize = getContext().getTypeSize(VT);
4148 if (VecSize == 64 || VecSize == 128)
4154 bool AArch64ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
4155 uint64_t Members) const {
4156 return Members <= 4;
4159 llvm::Value *AArch64ABIInfo::EmitAAPCSVAArg(llvm::Value *VAListAddr,
4161 CodeGenFunction &CGF) const {
4162 ABIArgInfo AI = classifyArgumentType(Ty);
4163 bool IsIndirect = AI.isIndirect();
4165 llvm::Type *BaseTy = CGF.ConvertType(Ty);
4167 BaseTy = llvm::PointerType::getUnqual(BaseTy);
4168 else if (AI.getCoerceToType())
4169 BaseTy = AI.getCoerceToType();
4171 unsigned NumRegs = 1;
4172 if (llvm::ArrayType *ArrTy = dyn_cast<llvm::ArrayType>(BaseTy)) {
4173 BaseTy = ArrTy->getElementType();
4174 NumRegs = ArrTy->getNumElements();
4176 bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy();
4178 // The AArch64 va_list type and handling is specified in the Procedure Call
4179 // Standard, section B.4:
4189 llvm::BasicBlock *MaybeRegBlock = CGF.createBasicBlock("vaarg.maybe_reg");
4190 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
4191 llvm::BasicBlock *OnStackBlock = CGF.createBasicBlock("vaarg.on_stack");
4192 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
4193 auto &Ctx = CGF.getContext();
4195 llvm::Value *reg_offs_p = nullptr, *reg_offs = nullptr;
4197 int RegSize = IsIndirect ? 8 : getContext().getTypeSize(Ty) / 8;
4199 // 3 is the field number of __gr_offs
4201 CGF.Builder.CreateStructGEP(nullptr, VAListAddr, 3, "gr_offs_p");
4202 reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "gr_offs");
4203 reg_top_index = 1; // field number for __gr_top
4204 RegSize = llvm::RoundUpToAlignment(RegSize, 8);
4206 // 4 is the field number of __vr_offs.
4208 CGF.Builder.CreateStructGEP(nullptr, VAListAddr, 4, "vr_offs_p");
4209 reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "vr_offs");
4210 reg_top_index = 2; // field number for __vr_top
4211 RegSize = 16 * NumRegs;
4214 //=======================================
4215 // Find out where argument was passed
4216 //=======================================
4218 // If reg_offs >= 0 we're already using the stack for this type of
4219 // argument. We don't want to keep updating reg_offs (in case it overflows,
4220 // though anyone passing 2GB of arguments, each at most 16 bytes, deserves
4221 // whatever they get).
4222 llvm::Value *UsingStack = nullptr;
4223 UsingStack = CGF.Builder.CreateICmpSGE(
4224 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, 0));
4226 CGF.Builder.CreateCondBr(UsingStack, OnStackBlock, MaybeRegBlock);
4228 // Otherwise, at least some kind of argument could go in these registers, the
4229 // question is whether this particular type is too big.
4230 CGF.EmitBlock(MaybeRegBlock);
4232 // Integer arguments may need to correct register alignment (for example a
4233 // "struct { __int128 a; };" gets passed in x_2N, x_{2N+1}). In this case we
4234 // align __gr_offs to calculate the potential address.
4235 if (!IsFPR && !IsIndirect && Ctx.getTypeAlign(Ty) > 64) {
4236 int Align = Ctx.getTypeAlign(Ty) / 8;
4238 reg_offs = CGF.Builder.CreateAdd(
4239 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, Align - 1),
4241 reg_offs = CGF.Builder.CreateAnd(
4242 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, -Align),
4246 // Update the gr_offs/vr_offs pointer for next call to va_arg on this va_list.
4247 llvm::Value *NewOffset = nullptr;
4248 NewOffset = CGF.Builder.CreateAdd(
4249 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs");
4250 CGF.Builder.CreateStore(NewOffset, reg_offs_p);
4252 // Now we're in a position to decide whether this argument really was in
4253 // registers or not.
4254 llvm::Value *InRegs = nullptr;
4255 InRegs = CGF.Builder.CreateICmpSLE(
4256 NewOffset, llvm::ConstantInt::get(CGF.Int32Ty, 0), "inreg");
4258 CGF.Builder.CreateCondBr(InRegs, InRegBlock, OnStackBlock);
4260 //=======================================
4261 // Argument was in registers
4262 //=======================================
4264 // Now we emit the code for if the argument was originally passed in
4265 // registers. First start the appropriate block:
4266 CGF.EmitBlock(InRegBlock);
4268 llvm::Value *reg_top_p = nullptr, *reg_top = nullptr;
4269 reg_top_p = CGF.Builder.CreateStructGEP(nullptr, VAListAddr, reg_top_index,
4271 reg_top = CGF.Builder.CreateLoad(reg_top_p, "reg_top");
4272 llvm::Value *BaseAddr = CGF.Builder.CreateGEP(reg_top, reg_offs);
4273 llvm::Value *RegAddr = nullptr;
4274 llvm::Type *MemTy = llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty));
4277 // If it's been passed indirectly (actually a struct), whatever we find from
4278 // stored registers or on the stack will actually be a struct **.
4279 MemTy = llvm::PointerType::getUnqual(MemTy);
4282 const Type *Base = nullptr;
4283 uint64_t NumMembers = 0;
4284 bool IsHFA = isHomogeneousAggregate(Ty, Base, NumMembers);
4285 if (IsHFA && NumMembers > 1) {
4286 // Homogeneous aggregates passed in registers will have their elements split
4287 // and stored 16-bytes apart regardless of size (they're notionally in qN,
4288 // qN+1, ...). We reload and store into a temporary local variable
4290 assert(!IsIndirect && "Homogeneous aggregates should be passed directly");
4291 llvm::Type *BaseTy = CGF.ConvertType(QualType(Base, 0));
4292 llvm::Type *HFATy = llvm::ArrayType::get(BaseTy, NumMembers);
4293 llvm::AllocaInst *Tmp = CGF.CreateTempAlloca(HFATy);
4296 if (CGF.CGM.getDataLayout().isBigEndian() && Ctx.getTypeSize(Base) < 128)
4297 Offset = 16 - Ctx.getTypeSize(Base) / 8;
4298 for (unsigned i = 0; i < NumMembers; ++i) {
4299 llvm::Value *BaseOffset =
4300 llvm::ConstantInt::get(CGF.Int32Ty, 16 * i + Offset);
4301 llvm::Value *LoadAddr = CGF.Builder.CreateGEP(BaseAddr, BaseOffset);
4302 LoadAddr = CGF.Builder.CreateBitCast(
4303 LoadAddr, llvm::PointerType::getUnqual(BaseTy));
4304 llvm::Value *StoreAddr =
4305 CGF.Builder.CreateStructGEP(Tmp->getAllocatedType(), Tmp, i);
4307 llvm::Value *Elem = CGF.Builder.CreateLoad(LoadAddr);
4308 CGF.Builder.CreateStore(Elem, StoreAddr);
4311 RegAddr = CGF.Builder.CreateBitCast(Tmp, MemTy);
4313 // Otherwise the object is contiguous in memory
4314 unsigned BeAlign = reg_top_index == 2 ? 16 : 8;
4315 if (CGF.CGM.getDataLayout().isBigEndian() &&
4316 (IsHFA || !isAggregateTypeForABI(Ty)) &&
4317 Ctx.getTypeSize(Ty) < (BeAlign * 8)) {
4318 int Offset = BeAlign - Ctx.getTypeSize(Ty) / 8;
4319 BaseAddr = CGF.Builder.CreatePtrToInt(BaseAddr, CGF.Int64Ty);
4321 BaseAddr = CGF.Builder.CreateAdd(
4322 BaseAddr, llvm::ConstantInt::get(CGF.Int64Ty, Offset), "align_be");
4324 BaseAddr = CGF.Builder.CreateIntToPtr(BaseAddr, CGF.Int8PtrTy);
4327 RegAddr = CGF.Builder.CreateBitCast(BaseAddr, MemTy);
4330 CGF.EmitBranch(ContBlock);
4332 //=======================================
4333 // Argument was on the stack
4334 //=======================================
4335 CGF.EmitBlock(OnStackBlock);
4337 llvm::Value *stack_p = nullptr, *OnStackAddr = nullptr;
4338 stack_p = CGF.Builder.CreateStructGEP(nullptr, VAListAddr, 0, "stack_p");
4339 OnStackAddr = CGF.Builder.CreateLoad(stack_p, "stack");
4341 // Again, stack arguments may need realigmnent. In this case both integer and
4342 // floating-point ones might be affected.
4343 if (!IsIndirect && Ctx.getTypeAlign(Ty) > 64) {
4344 int Align = Ctx.getTypeAlign(Ty) / 8;
4346 OnStackAddr = CGF.Builder.CreatePtrToInt(OnStackAddr, CGF.Int64Ty);
4348 OnStackAddr = CGF.Builder.CreateAdd(
4349 OnStackAddr, llvm::ConstantInt::get(CGF.Int64Ty, Align - 1),
4351 OnStackAddr = CGF.Builder.CreateAnd(
4352 OnStackAddr, llvm::ConstantInt::get(CGF.Int64Ty, -Align),
4355 OnStackAddr = CGF.Builder.CreateIntToPtr(OnStackAddr, CGF.Int8PtrTy);
4362 StackSize = Ctx.getTypeSize(Ty) / 8;
4364 // All stack slots are 8 bytes
4365 StackSize = llvm::RoundUpToAlignment(StackSize, 8);
4367 llvm::Value *StackSizeC = llvm::ConstantInt::get(CGF.Int32Ty, StackSize);
4368 llvm::Value *NewStack =
4369 CGF.Builder.CreateGEP(OnStackAddr, StackSizeC, "new_stack");
4371 // Write the new value of __stack for the next call to va_arg
4372 CGF.Builder.CreateStore(NewStack, stack_p);
4374 if (CGF.CGM.getDataLayout().isBigEndian() && !isAggregateTypeForABI(Ty) &&
4375 Ctx.getTypeSize(Ty) < 64) {
4376 int Offset = 8 - Ctx.getTypeSize(Ty) / 8;
4377 OnStackAddr = CGF.Builder.CreatePtrToInt(OnStackAddr, CGF.Int64Ty);
4379 OnStackAddr = CGF.Builder.CreateAdd(
4380 OnStackAddr, llvm::ConstantInt::get(CGF.Int64Ty, Offset), "align_be");
4382 OnStackAddr = CGF.Builder.CreateIntToPtr(OnStackAddr, CGF.Int8PtrTy);
4385 OnStackAddr = CGF.Builder.CreateBitCast(OnStackAddr, MemTy);
4387 CGF.EmitBranch(ContBlock);
4389 //=======================================
4391 //=======================================
4392 CGF.EmitBlock(ContBlock);
4394 llvm::PHINode *ResAddr = CGF.Builder.CreatePHI(MemTy, 2, "vaarg.addr");
4395 ResAddr->addIncoming(RegAddr, InRegBlock);
4396 ResAddr->addIncoming(OnStackAddr, OnStackBlock);
4399 return CGF.Builder.CreateLoad(ResAddr, "vaarg.addr");
4404 llvm::Value *AArch64ABIInfo::EmitDarwinVAArg(llvm::Value *VAListAddr,
4406 CodeGenFunction &CGF) const {
4407 // We do not support va_arg for aggregates or illegal vector types.
4408 // Lower VAArg here for these cases and use the LLVM va_arg instruction for
4410 if (!isAggregateTypeForABI(Ty) && !isIllegalVectorType(Ty))
4413 uint64_t Size = CGF.getContext().getTypeSize(Ty) / 8;
4414 uint64_t Align = CGF.getContext().getTypeAlign(Ty) / 8;
4416 const Type *Base = nullptr;
4417 uint64_t Members = 0;
4418 bool isHA = isHomogeneousAggregate(Ty, Base, Members);
4420 bool isIndirect = false;
4421 // Arguments bigger than 16 bytes which aren't homogeneous aggregates should
4422 // be passed indirectly.
4423 if (Size > 16 && !isHA) {
4429 llvm::Type *BP = llvm::Type::getInt8PtrTy(CGF.getLLVMContext());
4430 llvm::Type *BPP = llvm::PointerType::getUnqual(BP);
4432 CGBuilderTy &Builder = CGF.Builder;
4433 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap");
4434 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur");
4436 if (isEmptyRecord(getContext(), Ty, true)) {
4437 // These are ignored for parameter passing purposes.
4438 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
4439 return Builder.CreateBitCast(Addr, PTy);
4442 const uint64_t MinABIAlign = 8;
4443 if (Align > MinABIAlign) {
4444 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, Align - 1);
4445 Addr = Builder.CreateGEP(Addr, Offset);
4446 llvm::Value *AsInt = Builder.CreatePtrToInt(Addr, CGF.Int64Ty);
4447 llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int64Ty, ~(Align - 1));
4448 llvm::Value *Aligned = Builder.CreateAnd(AsInt, Mask);
4449 Addr = Builder.CreateIntToPtr(Aligned, BP, "ap.align");
4452 uint64_t Offset = llvm::RoundUpToAlignment(Size, MinABIAlign);
4453 llvm::Value *NextAddr = Builder.CreateGEP(
4454 Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset), "ap.next");
4455 Builder.CreateStore(NextAddr, VAListAddrAsBPP);
4458 Addr = Builder.CreateLoad(Builder.CreateBitCast(Addr, BPP));
4459 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
4460 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy);
4465 //===----------------------------------------------------------------------===//
4466 // ARM ABI Implementation
4467 //===----------------------------------------------------------------------===//
4471 class ARMABIInfo : public ABIInfo {
4483 ARMABIInfo(CodeGenTypes &CGT, ABIKind _Kind) : ABIInfo(CGT), Kind(_Kind) {
4487 bool isEABI() const {
4488 switch (getTarget().getTriple().getEnvironment()) {
4489 case llvm::Triple::Android:
4490 case llvm::Triple::EABI:
4491 case llvm::Triple::EABIHF:
4492 case llvm::Triple::GNUEABI:
4493 case llvm::Triple::GNUEABIHF:
4500 bool isEABIHF() const {
4501 switch (getTarget().getTriple().getEnvironment()) {
4502 case llvm::Triple::EABIHF:
4503 case llvm::Triple::GNUEABIHF:
4510 ABIKind getABIKind() const { return Kind; }
4513 ABIArgInfo classifyReturnType(QualType RetTy, bool isVariadic) const;
4514 ABIArgInfo classifyArgumentType(QualType RetTy, bool isVariadic) const;
4515 bool isIllegalVectorType(QualType Ty) const;
4517 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4518 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4519 uint64_t Members) const override;
4521 void computeInfo(CGFunctionInfo &FI) const override;
4523 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
4524 CodeGenFunction &CGF) const override;
4526 llvm::CallingConv::ID getLLVMDefaultCC() const;
4527 llvm::CallingConv::ID getABIDefaultCC() const;
4531 class ARMTargetCodeGenInfo : public TargetCodeGenInfo {
4533 ARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
4534 :TargetCodeGenInfo(new ARMABIInfo(CGT, K)) {}
4536 const ARMABIInfo &getABIInfo() const {
4537 return static_cast<const ARMABIInfo&>(TargetCodeGenInfo::getABIInfo());
4540 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4544 StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
4545 return "mov\tr7, r7\t\t@ marker for objc_retainAutoreleaseReturnValue";
4548 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4549 llvm::Value *Address) const override {
4550 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
4552 // 0-15 are the 16 integer registers.
4553 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 15);
4557 unsigned getSizeOfUnwindException() const override {
4558 if (getABIInfo().isEABI()) return 88;
4559 return TargetCodeGenInfo::getSizeOfUnwindException();
4562 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
4563 CodeGen::CodeGenModule &CGM) const override {
4564 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D);
4568 const ARMInterruptAttr *Attr = FD->getAttr<ARMInterruptAttr>();
4573 switch (Attr->getInterrupt()) {
4574 case ARMInterruptAttr::Generic: Kind = ""; break;
4575 case ARMInterruptAttr::IRQ: Kind = "IRQ"; break;
4576 case ARMInterruptAttr::FIQ: Kind = "FIQ"; break;
4577 case ARMInterruptAttr::SWI: Kind = "SWI"; break;
4578 case ARMInterruptAttr::ABORT: Kind = "ABORT"; break;
4579 case ARMInterruptAttr::UNDEF: Kind = "UNDEF"; break;
4582 llvm::Function *Fn = cast<llvm::Function>(GV);
4584 Fn->addFnAttr("interrupt", Kind);
4586 if (cast<ARMABIInfo>(getABIInfo()).getABIKind() == ARMABIInfo::APCS)
4589 // AAPCS guarantees that sp will be 8-byte aligned on any public interface,
4590 // however this is not necessarily true on taking any interrupt. Instruct
4591 // the backend to perform a realignment as part of the function prologue.
4592 llvm::AttrBuilder B;
4593 B.addStackAlignmentAttr(8);
4594 Fn->addAttributes(llvm::AttributeSet::FunctionIndex,
4595 llvm::AttributeSet::get(CGM.getLLVMContext(),
4596 llvm::AttributeSet::FunctionIndex,
4601 class WindowsARMTargetCodeGenInfo : public ARMTargetCodeGenInfo {
4602 void addStackProbeSizeTargetAttribute(const Decl *D, llvm::GlobalValue *GV,
4603 CodeGen::CodeGenModule &CGM) const;
4606 WindowsARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
4607 : ARMTargetCodeGenInfo(CGT, K) {}
4609 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
4610 CodeGen::CodeGenModule &CGM) const override;
4613 void WindowsARMTargetCodeGenInfo::addStackProbeSizeTargetAttribute(
4614 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
4615 if (!isa<FunctionDecl>(D))
4617 if (CGM.getCodeGenOpts().StackProbeSize == 4096)
4620 llvm::Function *F = cast<llvm::Function>(GV);
4621 F->addFnAttr("stack-probe-size",
4622 llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
4625 void WindowsARMTargetCodeGenInfo::setTargetAttributes(
4626 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
4627 ARMTargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
4628 addStackProbeSizeTargetAttribute(D, GV, CGM);
4632 void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const {
4633 if (!getCXXABI().classifyReturnType(FI))
4634 FI.getReturnInfo() =
4635 classifyReturnType(FI.getReturnType(), FI.isVariadic());
4637 for (auto &I : FI.arguments())
4638 I.info = classifyArgumentType(I.type, FI.isVariadic());
4640 // Always honor user-specified calling convention.
4641 if (FI.getCallingConvention() != llvm::CallingConv::C)
4644 llvm::CallingConv::ID cc = getRuntimeCC();
4645 if (cc != llvm::CallingConv::C)
4646 FI.setEffectiveCallingConvention(cc);
4649 /// Return the default calling convention that LLVM will use.
4650 llvm::CallingConv::ID ARMABIInfo::getLLVMDefaultCC() const {
4651 // The default calling convention that LLVM will infer.
4653 return llvm::CallingConv::ARM_AAPCS_VFP;
4655 return llvm::CallingConv::ARM_AAPCS;
4657 return llvm::CallingConv::ARM_APCS;
4660 /// Return the calling convention that our ABI would like us to use
4661 /// as the C calling convention.
4662 llvm::CallingConv::ID ARMABIInfo::getABIDefaultCC() const {
4663 switch (getABIKind()) {
4664 case APCS: return llvm::CallingConv::ARM_APCS;
4665 case AAPCS: return llvm::CallingConv::ARM_AAPCS;
4666 case AAPCS_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
4668 llvm_unreachable("bad ABI kind");
4671 void ARMABIInfo::setCCs() {
4672 assert(getRuntimeCC() == llvm::CallingConv::C);
4674 // Don't muddy up the IR with a ton of explicit annotations if
4675 // they'd just match what LLVM will infer from the triple.
4676 llvm::CallingConv::ID abiCC = getABIDefaultCC();
4677 if (abiCC != getLLVMDefaultCC())
4680 BuiltinCC = (getABIKind() == APCS ?
4681 llvm::CallingConv::ARM_APCS : llvm::CallingConv::ARM_AAPCS);
4684 ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty,
4685 bool isVariadic) const {
4686 // 6.1.2.1 The following argument types are VFP CPRCs:
4687 // A single-precision floating-point type (including promoted
4688 // half-precision types); A double-precision floating-point type;
4689 // A 64-bit or 128-bit containerized vector type; Homogeneous Aggregate
4690 // with a Base Type of a single- or double-precision floating-point type,
4691 // 64-bit containerized vectors or 128-bit containerized vectors with one
4692 // to four Elements.
4693 bool IsEffectivelyAAPCS_VFP = getABIKind() == AAPCS_VFP && !isVariadic;
4695 Ty = useFirstFieldIfTransparentUnion(Ty);
4697 // Handle illegal vector types here.
4698 if (isIllegalVectorType(Ty)) {
4699 uint64_t Size = getContext().getTypeSize(Ty);
4701 llvm::Type *ResType =
4702 llvm::Type::getInt32Ty(getVMContext());
4703 return ABIArgInfo::getDirect(ResType);
4706 llvm::Type *ResType = llvm::VectorType::get(
4707 llvm::Type::getInt32Ty(getVMContext()), 2);
4708 return ABIArgInfo::getDirect(ResType);
4711 llvm::Type *ResType = llvm::VectorType::get(
4712 llvm::Type::getInt32Ty(getVMContext()), 4);
4713 return ABIArgInfo::getDirect(ResType);
4715 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
4718 if (!isAggregateTypeForABI(Ty)) {
4719 // Treat an enum type as its underlying type.
4720 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
4721 Ty = EnumTy->getDecl()->getIntegerType();
4724 return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend()
4725 : ABIArgInfo::getDirect());
4728 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
4729 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
4732 // Ignore empty records.
4733 if (isEmptyRecord(getContext(), Ty, true))
4734 return ABIArgInfo::getIgnore();
4736 if (IsEffectivelyAAPCS_VFP) {
4737 // Homogeneous Aggregates need to be expanded when we can fit the aggregate
4738 // into VFP registers.
4739 const Type *Base = nullptr;
4740 uint64_t Members = 0;
4741 if (isHomogeneousAggregate(Ty, Base, Members)) {
4742 assert(Base && "Base class should be set for homogeneous aggregate");
4743 // Base can be a floating-point or a vector.
4744 return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
4748 // Support byval for ARM.
4749 // The ABI alignment for APCS is 4-byte and for AAPCS at least 4-byte and at
4750 // most 8-byte. We realign the indirect argument if type alignment is bigger
4751 // than ABI alignment.
4752 uint64_t ABIAlign = 4;
4753 uint64_t TyAlign = getContext().getTypeAlign(Ty) / 8;
4754 if (getABIKind() == ARMABIInfo::AAPCS_VFP ||
4755 getABIKind() == ARMABIInfo::AAPCS)
4756 ABIAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8);
4758 if (getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(64)) {
4759 return ABIArgInfo::getIndirect(ABIAlign, /*ByVal=*/true,
4760 /*Realign=*/TyAlign > ABIAlign);
4763 // Otherwise, pass by coercing to a structure of the appropriate size.
4766 // FIXME: Try to match the types of the arguments more accurately where
4768 if (getContext().getTypeAlign(Ty) <= 32) {
4769 ElemTy = llvm::Type::getInt32Ty(getVMContext());
4770 SizeRegs = (getContext().getTypeSize(Ty) + 31) / 32;
4772 ElemTy = llvm::Type::getInt64Ty(getVMContext());
4773 SizeRegs = (getContext().getTypeSize(Ty) + 63) / 64;
4776 return ABIArgInfo::getDirect(llvm::ArrayType::get(ElemTy, SizeRegs));
4779 static bool isIntegerLikeType(QualType Ty, ASTContext &Context,
4780 llvm::LLVMContext &VMContext) {
4781 // APCS, C Language Calling Conventions, Non-Simple Return Values: A structure
4782 // is called integer-like if its size is less than or equal to one word, and
4783 // the offset of each of its addressable sub-fields is zero.
4785 uint64_t Size = Context.getTypeSize(Ty);
4787 // Check that the type fits in a word.
4791 // FIXME: Handle vector types!
4792 if (Ty->isVectorType())
4795 // Float types are never treated as "integer like".
4796 if (Ty->isRealFloatingType())
4799 // If this is a builtin or pointer type then it is ok.
4800 if (Ty->getAs<BuiltinType>() || Ty->isPointerType())
4803 // Small complex integer types are "integer like".
4804 if (const ComplexType *CT = Ty->getAs<ComplexType>())
4805 return isIntegerLikeType(CT->getElementType(), Context, VMContext);
4807 // Single element and zero sized arrays should be allowed, by the definition
4808 // above, but they are not.
4810 // Otherwise, it must be a record type.
4811 const RecordType *RT = Ty->getAs<RecordType>();
4812 if (!RT) return false;
4814 // Ignore records with flexible arrays.
4815 const RecordDecl *RD = RT->getDecl();
4816 if (RD->hasFlexibleArrayMember())
4819 // Check that all sub-fields are at offset 0, and are themselves "integer
4821 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
4823 bool HadField = false;
4825 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
4826 i != e; ++i, ++idx) {
4827 const FieldDecl *FD = *i;
4829 // Bit-fields are not addressable, we only need to verify they are "integer
4830 // like". We still have to disallow a subsequent non-bitfield, for example:
4831 // struct { int : 0; int x }
4832 // is non-integer like according to gcc.
4833 if (FD->isBitField()) {
4837 if (!isIntegerLikeType(FD->getType(), Context, VMContext))
4843 // Check if this field is at offset 0.
4844 if (Layout.getFieldOffset(idx) != 0)
4847 if (!isIntegerLikeType(FD->getType(), Context, VMContext))
4850 // Only allow at most one field in a structure. This doesn't match the
4851 // wording above, but follows gcc in situations with a field following an
4853 if (!RD->isUnion()) {
4864 ABIArgInfo ARMABIInfo::classifyReturnType(QualType RetTy,
4865 bool isVariadic) const {
4866 bool IsEffectivelyAAPCS_VFP = getABIKind() == AAPCS_VFP && !isVariadic;
4868 if (RetTy->isVoidType())
4869 return ABIArgInfo::getIgnore();
4871 // Large vector types should be returned via memory.
4872 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128) {
4873 return ABIArgInfo::getIndirect(0);
4876 if (!isAggregateTypeForABI(RetTy)) {
4877 // Treat an enum type as its underlying type.
4878 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
4879 RetTy = EnumTy->getDecl()->getIntegerType();
4881 return RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend()
4882 : ABIArgInfo::getDirect();
4885 // Are we following APCS?
4886 if (getABIKind() == APCS) {
4887 if (isEmptyRecord(getContext(), RetTy, false))
4888 return ABIArgInfo::getIgnore();
4890 // Complex types are all returned as packed integers.
4892 // FIXME: Consider using 2 x vector types if the back end handles them
4894 if (RetTy->isAnyComplexType())
4895 return ABIArgInfo::getDirect(llvm::IntegerType::get(
4896 getVMContext(), getContext().getTypeSize(RetTy)));
4898 // Integer like structures are returned in r0.
4899 if (isIntegerLikeType(RetTy, getContext(), getVMContext())) {
4900 // Return in the smallest viable integer type.
4901 uint64_t Size = getContext().getTypeSize(RetTy);
4903 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
4905 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
4906 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
4909 // Otherwise return in memory.
4910 return ABIArgInfo::getIndirect(0);
4913 // Otherwise this is an AAPCS variant.
4915 if (isEmptyRecord(getContext(), RetTy, true))
4916 return ABIArgInfo::getIgnore();
4918 // Check for homogeneous aggregates with AAPCS-VFP.
4919 if (IsEffectivelyAAPCS_VFP) {
4920 const Type *Base = nullptr;
4922 if (isHomogeneousAggregate(RetTy, Base, Members)) {
4923 assert(Base && "Base class should be set for homogeneous aggregate");
4924 // Homogeneous Aggregates are returned directly.
4925 return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
4929 // Aggregates <= 4 bytes are returned in r0; other aggregates
4930 // are returned indirectly.
4931 uint64_t Size = getContext().getTypeSize(RetTy);
4933 if (getDataLayout().isBigEndian())
4934 // Return in 32 bit integer integer type (as if loaded by LDR, AAPCS 5.4)
4935 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
4937 // Return in the smallest viable integer type.
4939 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
4941 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
4942 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
4945 return ABIArgInfo::getIndirect(0);
4948 /// isIllegalVector - check whether Ty is an illegal vector type.
4949 bool ARMABIInfo::isIllegalVectorType(QualType Ty) const {
4950 if (const VectorType *VT = Ty->getAs<VectorType>()) {
4951 // Check whether VT is legal.
4952 unsigned NumElements = VT->getNumElements();
4953 uint64_t Size = getContext().getTypeSize(VT);
4954 // NumElements should be power of 2.
4955 if ((NumElements & (NumElements - 1)) != 0)
4957 // Size should be greater than 32 bits.
4963 bool ARMABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
4964 // Homogeneous aggregates for AAPCS-VFP must have base types of float,
4965 // double, or 64-bit or 128-bit vectors.
4966 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4967 if (BT->getKind() == BuiltinType::Float ||
4968 BT->getKind() == BuiltinType::Double ||
4969 BT->getKind() == BuiltinType::LongDouble)
4971 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
4972 unsigned VecSize = getContext().getTypeSize(VT);
4973 if (VecSize == 64 || VecSize == 128)
4979 bool ARMABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
4980 uint64_t Members) const {
4981 return Members <= 4;
4984 llvm::Value *ARMABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
4985 CodeGenFunction &CGF) const {
4986 llvm::Type *BP = CGF.Int8PtrTy;
4987 llvm::Type *BPP = CGF.Int8PtrPtrTy;
4989 CGBuilderTy &Builder = CGF.Builder;
4990 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap");
4991 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur");
4993 if (isEmptyRecord(getContext(), Ty, true)) {
4994 // These are ignored for parameter passing purposes.
4995 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
4996 return Builder.CreateBitCast(Addr, PTy);
4999 uint64_t Size = CGF.getContext().getTypeSize(Ty) / 8;
5000 uint64_t TyAlign = CGF.getContext().getTypeAlign(Ty) / 8;
5001 bool IsIndirect = false;
5003 // The ABI alignment for 64-bit or 128-bit vectors is 8 for AAPCS and 4 for
5004 // APCS. For AAPCS, the ABI alignment is at least 4-byte and at most 8-byte.
5005 if (getABIKind() == ARMABIInfo::AAPCS_VFP ||
5006 getABIKind() == ARMABIInfo::AAPCS)
5007 TyAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8);
5010 // Use indirect if size of the illegal vector is bigger than 16 bytes.
5011 if (isIllegalVectorType(Ty) && Size > 16) {
5017 // Handle address alignment for ABI alignment > 4 bytes.
5019 assert((TyAlign & (TyAlign - 1)) == 0 &&
5020 "Alignment is not power of 2!");
5021 llvm::Value *AddrAsInt = Builder.CreatePtrToInt(Addr, CGF.Int32Ty);
5022 AddrAsInt = Builder.CreateAdd(AddrAsInt, Builder.getInt32(TyAlign - 1));
5023 AddrAsInt = Builder.CreateAnd(AddrAsInt, Builder.getInt32(~(TyAlign - 1)));
5024 Addr = Builder.CreateIntToPtr(AddrAsInt, BP, "ap.align");
5028 llvm::RoundUpToAlignment(Size, 4);
5029 llvm::Value *NextAddr =
5030 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset),
5032 Builder.CreateStore(NextAddr, VAListAddrAsBPP);
5035 Addr = Builder.CreateLoad(Builder.CreateBitCast(Addr, BPP));
5036 else if (TyAlign < CGF.getContext().getTypeAlign(Ty) / 8) {
5037 // We can't directly cast ap.cur to pointer to a vector type, since ap.cur
5038 // may not be correctly aligned for the vector type. We create an aligned
5039 // temporary space and copy the content over from ap.cur to the temporary
5040 // space. This is necessary if the natural alignment of the type is greater
5041 // than the ABI alignment.
5042 llvm::Type *I8PtrTy = Builder.getInt8PtrTy();
5043 CharUnits CharSize = getContext().getTypeSizeInChars(Ty);
5044 llvm::Value *AlignedTemp = CGF.CreateTempAlloca(CGF.ConvertType(Ty),
5046 llvm::Value *Dst = Builder.CreateBitCast(AlignedTemp, I8PtrTy);
5047 llvm::Value *Src = Builder.CreateBitCast(Addr, I8PtrTy);
5048 Builder.CreateMemCpy(Dst, Src,
5049 llvm::ConstantInt::get(CGF.IntPtrTy, CharSize.getQuantity()),
5051 Addr = AlignedTemp; //The content is in aligned location.
5054 llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
5055 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy);
5060 //===----------------------------------------------------------------------===//
5061 // NVPTX ABI Implementation
5062 //===----------------------------------------------------------------------===//
5066 class NVPTXABIInfo : public ABIInfo {
5068 NVPTXABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
5070 ABIArgInfo classifyReturnType(QualType RetTy) const;
5071 ABIArgInfo classifyArgumentType(QualType Ty) const;
5073 void computeInfo(CGFunctionInfo &FI) const override;
5074 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
5075 CodeGenFunction &CFG) const override;
5078 class NVPTXTargetCodeGenInfo : public TargetCodeGenInfo {
5080 NVPTXTargetCodeGenInfo(CodeGenTypes &CGT)
5081 : TargetCodeGenInfo(new NVPTXABIInfo(CGT)) {}
5083 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5084 CodeGen::CodeGenModule &M) const override;
5086 // Adds a NamedMDNode with F, Name, and Operand as operands, and adds the
5087 // resulting MDNode to the nvvm.annotations MDNode.
5088 static void addNVVMMetadata(llvm::Function *F, StringRef Name, int Operand);
5091 ABIArgInfo NVPTXABIInfo::classifyReturnType(QualType RetTy) const {
5092 if (RetTy->isVoidType())
5093 return ABIArgInfo::getIgnore();
5095 // note: this is different from default ABI
5096 if (!RetTy->isScalarType())
5097 return ABIArgInfo::getDirect();
5099 // Treat an enum type as its underlying type.
5100 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5101 RetTy = EnumTy->getDecl()->getIntegerType();
5103 return (RetTy->isPromotableIntegerType() ?
5104 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
5107 ABIArgInfo NVPTXABIInfo::classifyArgumentType(QualType Ty) const {
5108 // Treat an enum type as its underlying type.
5109 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
5110 Ty = EnumTy->getDecl()->getIntegerType();
5112 // Return aggregates type as indirect by value
5113 if (isAggregateTypeForABI(Ty))
5114 return ABIArgInfo::getIndirect(0, /* byval */ true);
5116 return (Ty->isPromotableIntegerType() ?
5117 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
5120 void NVPTXABIInfo::computeInfo(CGFunctionInfo &FI) const {
5121 if (!getCXXABI().classifyReturnType(FI))
5122 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
5123 for (auto &I : FI.arguments())
5124 I.info = classifyArgumentType(I.type);
5126 // Always honor user-specified calling convention.
5127 if (FI.getCallingConvention() != llvm::CallingConv::C)
5130 FI.setEffectiveCallingConvention(getRuntimeCC());
5133 llvm::Value *NVPTXABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
5134 CodeGenFunction &CFG) const {
5135 llvm_unreachable("NVPTX does not support varargs");
5138 void NVPTXTargetCodeGenInfo::
5139 setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5140 CodeGen::CodeGenModule &M) const{
5141 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D);
5144 llvm::Function *F = cast<llvm::Function>(GV);
5146 // Perform special handling in OpenCL mode
5147 if (M.getLangOpts().OpenCL) {
5148 // Use OpenCL function attributes to check for kernel functions
5149 // By default, all functions are device functions
5150 if (FD->hasAttr<OpenCLKernelAttr>()) {
5151 // OpenCL __kernel functions get kernel metadata
5152 // Create !{<func-ref>, metadata !"kernel", i32 1} node
5153 addNVVMMetadata(F, "kernel", 1);
5154 // And kernel functions are not subject to inlining
5155 F->addFnAttr(llvm::Attribute::NoInline);
5159 // Perform special handling in CUDA mode.
5160 if (M.getLangOpts().CUDA) {
5161 // CUDA __global__ functions get a kernel metadata entry. Since
5162 // __global__ functions cannot be called from the device, we do not
5163 // need to set the noinline attribute.
5164 if (FD->hasAttr<CUDAGlobalAttr>()) {
5165 // Create !{<func-ref>, metadata !"kernel", i32 1} node
5166 addNVVMMetadata(F, "kernel", 1);
5168 if (CUDALaunchBoundsAttr *Attr = FD->getAttr<CUDALaunchBoundsAttr>()) {
5169 // Create !{<func-ref>, metadata !"maxntidx", i32 <val>} node
5170 llvm::APSInt MaxThreads(32);
5171 MaxThreads = Attr->getMaxThreads()->EvaluateKnownConstInt(M.getContext());
5173 addNVVMMetadata(F, "maxntidx", MaxThreads.getExtValue());
5175 // min blocks is an optional argument for CUDALaunchBoundsAttr. If it was
5176 // not specified in __launch_bounds__ or if the user specified a 0 value,
5177 // we don't have to add a PTX directive.
5178 if (Attr->getMinBlocks()) {
5179 llvm::APSInt MinBlocks(32);
5180 MinBlocks = Attr->getMinBlocks()->EvaluateKnownConstInt(M.getContext());
5182 // Create !{<func-ref>, metadata !"minctasm", i32 <val>} node
5183 addNVVMMetadata(F, "minctasm", MinBlocks.getExtValue());
5189 void NVPTXTargetCodeGenInfo::addNVVMMetadata(llvm::Function *F, StringRef Name,
5191 llvm::Module *M = F->getParent();
5192 llvm::LLVMContext &Ctx = M->getContext();
5194 // Get "nvvm.annotations" metadata node
5195 llvm::NamedMDNode *MD = M->getOrInsertNamedMetadata("nvvm.annotations");
5197 llvm::Metadata *MDVals[] = {
5198 llvm::ConstantAsMetadata::get(F), llvm::MDString::get(Ctx, Name),
5199 llvm::ConstantAsMetadata::get(
5200 llvm::ConstantInt::get(llvm::Type::getInt32Ty(Ctx), Operand))};
5201 // Append metadata to nvvm.annotations
5202 MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
5206 //===----------------------------------------------------------------------===//
5207 // SystemZ ABI Implementation
5208 //===----------------------------------------------------------------------===//
5212 class SystemZABIInfo : public ABIInfo {
5216 SystemZABIInfo(CodeGenTypes &CGT, bool HV)
5217 : ABIInfo(CGT), HasVector(HV) {}
5219 bool isPromotableIntegerType(QualType Ty) const;
5220 bool isCompoundType(QualType Ty) const;
5221 bool isVectorArgumentType(QualType Ty) const;
5222 bool isFPArgumentType(QualType Ty) const;
5223 QualType GetSingleElementType(QualType Ty) const;
5225 ABIArgInfo classifyReturnType(QualType RetTy) const;
5226 ABIArgInfo classifyArgumentType(QualType ArgTy) const;
5228 void computeInfo(CGFunctionInfo &FI) const override {
5229 if (!getCXXABI().classifyReturnType(FI))
5230 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
5231 for (auto &I : FI.arguments())
5232 I.info = classifyArgumentType(I.type);
5235 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
5236 CodeGenFunction &CGF) const override;
5239 class SystemZTargetCodeGenInfo : public TargetCodeGenInfo {
5241 SystemZTargetCodeGenInfo(CodeGenTypes &CGT, bool HasVector)
5242 : TargetCodeGenInfo(new SystemZABIInfo(CGT, HasVector)) {}
5247 bool SystemZABIInfo::isPromotableIntegerType(QualType Ty) const {
5248 // Treat an enum type as its underlying type.
5249 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
5250 Ty = EnumTy->getDecl()->getIntegerType();
5252 // Promotable integer types are required to be promoted by the ABI.
5253 if (Ty->isPromotableIntegerType())
5256 // 32-bit values must also be promoted.
5257 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
5258 switch (BT->getKind()) {
5259 case BuiltinType::Int:
5260 case BuiltinType::UInt:
5268 bool SystemZABIInfo::isCompoundType(QualType Ty) const {
5269 return (Ty->isAnyComplexType() ||
5270 Ty->isVectorType() ||
5271 isAggregateTypeForABI(Ty));
5274 bool SystemZABIInfo::isVectorArgumentType(QualType Ty) const {
5275 return (HasVector &&
5276 Ty->isVectorType() &&
5277 getContext().getTypeSize(Ty) <= 128);
5280 bool SystemZABIInfo::isFPArgumentType(QualType Ty) const {
5281 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
5282 switch (BT->getKind()) {
5283 case BuiltinType::Float:
5284 case BuiltinType::Double:
5293 QualType SystemZABIInfo::GetSingleElementType(QualType Ty) const {
5294 if (const RecordType *RT = Ty->getAsStructureType()) {
5295 const RecordDecl *RD = RT->getDecl();
5298 // If this is a C++ record, check the bases first.
5299 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
5300 for (const auto &I : CXXRD->bases()) {
5301 QualType Base = I.getType();
5303 // Empty bases don't affect things either way.
5304 if (isEmptyRecord(getContext(), Base, true))
5307 if (!Found.isNull())
5309 Found = GetSingleElementType(Base);
5312 // Check the fields.
5313 for (const auto *FD : RD->fields()) {
5314 // For compatibility with GCC, ignore empty bitfields in C++ mode.
5315 // Unlike isSingleElementStruct(), empty structure and array fields
5316 // do count. So do anonymous bitfields that aren't zero-sized.
5317 if (getContext().getLangOpts().CPlusPlus &&
5318 FD->isBitField() && FD->getBitWidthValue(getContext()) == 0)
5321 // Unlike isSingleElementStruct(), arrays do not count.
5322 // Nested structures still do though.
5323 if (!Found.isNull())
5325 Found = GetSingleElementType(FD->getType());
5328 // Unlike isSingleElementStruct(), trailing padding is allowed.
5329 // An 8-byte aligned struct s { float f; } is passed as a double.
5330 if (!Found.isNull())
5337 llvm::Value *SystemZABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
5338 CodeGenFunction &CGF) const {
5339 // Assume that va_list type is correct; should be pointer to LLVM type:
5343 // i8 *__overflow_arg_area;
5344 // i8 *__reg_save_area;
5347 // Every non-vector argument occupies 8 bytes and is passed by preference
5348 // in either GPRs or FPRs. Vector arguments occupy 8 or 16 bytes and are
5349 // always passed on the stack.
5350 Ty = CGF.getContext().getCanonicalType(Ty);
5351 llvm::Type *ArgTy = CGF.ConvertTypeForMem(Ty);
5352 llvm::Type *APTy = llvm::PointerType::getUnqual(ArgTy);
5353 ABIArgInfo AI = classifyArgumentType(Ty);
5354 bool IsIndirect = AI.isIndirect();
5355 bool InFPRs = false;
5356 bool IsVector = false;
5357 unsigned UnpaddedBitSize;
5359 APTy = llvm::PointerType::getUnqual(APTy);
5360 UnpaddedBitSize = 64;
5362 if (AI.getCoerceToType())
5363 ArgTy = AI.getCoerceToType();
5364 InFPRs = ArgTy->isFloatTy() || ArgTy->isDoubleTy();
5365 IsVector = ArgTy->isVectorTy();
5366 UnpaddedBitSize = getContext().getTypeSize(Ty);
5368 unsigned PaddedBitSize = (IsVector && UnpaddedBitSize > 64) ? 128 : 64;
5369 assert((UnpaddedBitSize <= PaddedBitSize) && "Invalid argument size.");
5371 unsigned PaddedSize = PaddedBitSize / 8;
5372 unsigned Padding = (PaddedBitSize - UnpaddedBitSize) / 8;
5374 llvm::Type *IndexTy = CGF.Int64Ty;
5375 llvm::Value *PaddedSizeV = llvm::ConstantInt::get(IndexTy, PaddedSize);
5378 // Work out the address of a vector argument on the stack.
5379 // Vector arguments are always passed in the high bits of a
5380 // single (8 byte) or double (16 byte) stack slot.
5381 llvm::Value *OverflowArgAreaPtr =
5382 CGF.Builder.CreateStructGEP(nullptr, VAListAddr, 2,
5383 "overflow_arg_area_ptr");
5384 llvm::Value *OverflowArgArea =
5385 CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area");
5386 llvm::Value *MemAddr =
5387 CGF.Builder.CreateBitCast(OverflowArgArea, APTy, "mem_addr");
5389 // Update overflow_arg_area_ptr pointer
5390 llvm::Value *NewOverflowArgArea =
5391 CGF.Builder.CreateGEP(OverflowArgArea, PaddedSizeV, "overflow_arg_area");
5392 CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
5397 unsigned MaxRegs, RegCountField, RegSaveIndex, RegPadding;
5399 MaxRegs = 4; // Maximum of 4 FPR arguments
5400 RegCountField = 1; // __fpr
5401 RegSaveIndex = 16; // save offset for f0
5402 RegPadding = 0; // floats are passed in the high bits of an FPR
5404 MaxRegs = 5; // Maximum of 5 GPR arguments
5405 RegCountField = 0; // __gpr
5406 RegSaveIndex = 2; // save offset for r2
5407 RegPadding = Padding; // values are passed in the low bits of a GPR
5410 llvm::Value *RegCountPtr = CGF.Builder.CreateStructGEP(
5411 nullptr, VAListAddr, RegCountField, "reg_count_ptr");
5412 llvm::Value *RegCount = CGF.Builder.CreateLoad(RegCountPtr, "reg_count");
5413 llvm::Value *MaxRegsV = llvm::ConstantInt::get(IndexTy, MaxRegs);
5414 llvm::Value *InRegs = CGF.Builder.CreateICmpULT(RegCount, MaxRegsV,
5417 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
5418 llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
5419 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
5420 CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
5422 // Emit code to load the value if it was passed in registers.
5423 CGF.EmitBlock(InRegBlock);
5425 // Work out the address of an argument register.
5426 llvm::Value *ScaledRegCount =
5427 CGF.Builder.CreateMul(RegCount, PaddedSizeV, "scaled_reg_count");
5428 llvm::Value *RegBase =
5429 llvm::ConstantInt::get(IndexTy, RegSaveIndex * PaddedSize + RegPadding);
5430 llvm::Value *RegOffset =
5431 CGF.Builder.CreateAdd(ScaledRegCount, RegBase, "reg_offset");
5432 llvm::Value *RegSaveAreaPtr =
5433 CGF.Builder.CreateStructGEP(nullptr, VAListAddr, 3, "reg_save_area_ptr");
5434 llvm::Value *RegSaveArea =
5435 CGF.Builder.CreateLoad(RegSaveAreaPtr, "reg_save_area");
5436 llvm::Value *RawRegAddr =
5437 CGF.Builder.CreateGEP(RegSaveArea, RegOffset, "raw_reg_addr");
5438 llvm::Value *RegAddr =
5439 CGF.Builder.CreateBitCast(RawRegAddr, APTy, "reg_addr");
5441 // Update the register count
5442 llvm::Value *One = llvm::ConstantInt::get(IndexTy, 1);
5443 llvm::Value *NewRegCount =
5444 CGF.Builder.CreateAdd(RegCount, One, "reg_count");
5445 CGF.Builder.CreateStore(NewRegCount, RegCountPtr);
5446 CGF.EmitBranch(ContBlock);
5448 // Emit code to load the value if it was passed in memory.
5449 CGF.EmitBlock(InMemBlock);
5451 // Work out the address of a stack argument.
5452 llvm::Value *OverflowArgAreaPtr = CGF.Builder.CreateStructGEP(
5453 nullptr, VAListAddr, 2, "overflow_arg_area_ptr");
5454 llvm::Value *OverflowArgArea =
5455 CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area");
5456 llvm::Value *PaddingV = llvm::ConstantInt::get(IndexTy, Padding);
5457 llvm::Value *RawMemAddr =
5458 CGF.Builder.CreateGEP(OverflowArgArea, PaddingV, "raw_mem_addr");
5459 llvm::Value *MemAddr =
5460 CGF.Builder.CreateBitCast(RawMemAddr, APTy, "mem_addr");
5462 // Update overflow_arg_area_ptr pointer
5463 llvm::Value *NewOverflowArgArea =
5464 CGF.Builder.CreateGEP(OverflowArgArea, PaddedSizeV, "overflow_arg_area");
5465 CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
5466 CGF.EmitBranch(ContBlock);
5468 // Return the appropriate result.
5469 CGF.EmitBlock(ContBlock);
5470 llvm::PHINode *ResAddr = CGF.Builder.CreatePHI(APTy, 2, "va_arg.addr");
5471 ResAddr->addIncoming(RegAddr, InRegBlock);
5472 ResAddr->addIncoming(MemAddr, InMemBlock);
5475 return CGF.Builder.CreateLoad(ResAddr, "indirect_arg");
5480 ABIArgInfo SystemZABIInfo::classifyReturnType(QualType RetTy) const {
5481 if (RetTy->isVoidType())
5482 return ABIArgInfo::getIgnore();
5483 if (isVectorArgumentType(RetTy))
5484 return ABIArgInfo::getDirect();
5485 if (isCompoundType(RetTy) || getContext().getTypeSize(RetTy) > 64)
5486 return ABIArgInfo::getIndirect(0);
5487 return (isPromotableIntegerType(RetTy) ?
5488 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
5491 ABIArgInfo SystemZABIInfo::classifyArgumentType(QualType Ty) const {
5492 // Handle the generic C++ ABI.
5493 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
5494 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
5496 // Integers and enums are extended to full register width.
5497 if (isPromotableIntegerType(Ty))
5498 return ABIArgInfo::getExtend();
5500 // Handle vector types and vector-like structure types. Note that
5501 // as opposed to float-like structure types, we do not allow any
5502 // padding for vector-like structures, so verify the sizes match.
5503 uint64_t Size = getContext().getTypeSize(Ty);
5504 QualType SingleElementTy = GetSingleElementType(Ty);
5505 if (isVectorArgumentType(SingleElementTy) &&
5506 getContext().getTypeSize(SingleElementTy) == Size)
5507 return ABIArgInfo::getDirect(CGT.ConvertType(SingleElementTy));
5509 // Values that are not 1, 2, 4 or 8 bytes in size are passed indirectly.
5510 if (Size != 8 && Size != 16 && Size != 32 && Size != 64)
5511 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
5513 // Handle small structures.
5514 if (const RecordType *RT = Ty->getAs<RecordType>()) {
5515 // Structures with flexible arrays have variable length, so really
5516 // fail the size test above.
5517 const RecordDecl *RD = RT->getDecl();
5518 if (RD->hasFlexibleArrayMember())
5519 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
5521 // The structure is passed as an unextended integer, a float, or a double.
5523 if (isFPArgumentType(SingleElementTy)) {
5524 assert(Size == 32 || Size == 64);
5526 PassTy = llvm::Type::getFloatTy(getVMContext());
5528 PassTy = llvm::Type::getDoubleTy(getVMContext());
5530 PassTy = llvm::IntegerType::get(getVMContext(), Size);
5531 return ABIArgInfo::getDirect(PassTy);
5534 // Non-structure compounds are passed indirectly.
5535 if (isCompoundType(Ty))
5536 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
5538 return ABIArgInfo::getDirect(nullptr);
5541 //===----------------------------------------------------------------------===//
5542 // MSP430 ABI Implementation
5543 //===----------------------------------------------------------------------===//
5547 class MSP430TargetCodeGenInfo : public TargetCodeGenInfo {
5549 MSP430TargetCodeGenInfo(CodeGenTypes &CGT)
5550 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
5551 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5552 CodeGen::CodeGenModule &M) const override;
5557 void MSP430TargetCodeGenInfo::setTargetAttributes(const Decl *D,
5558 llvm::GlobalValue *GV,
5559 CodeGen::CodeGenModule &M) const {
5560 if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) {
5561 if (const MSP430InterruptAttr *attr = FD->getAttr<MSP430InterruptAttr>()) {
5562 // Handle 'interrupt' attribute:
5563 llvm::Function *F = cast<llvm::Function>(GV);
5565 // Step 1: Set ISR calling convention.
5566 F->setCallingConv(llvm::CallingConv::MSP430_INTR);
5568 // Step 2: Add attributes goodness.
5569 F->addFnAttr(llvm::Attribute::NoInline);
5571 // Step 3: Emit ISR vector alias.
5572 unsigned Num = attr->getNumber() / 2;
5573 llvm::GlobalAlias::create(llvm::Function::ExternalLinkage,
5574 "__isr_" + Twine(Num), F);
5579 //===----------------------------------------------------------------------===//
5580 // MIPS ABI Implementation. This works for both little-endian and
5581 // big-endian variants.
5582 //===----------------------------------------------------------------------===//
5585 class MipsABIInfo : public ABIInfo {
5587 unsigned MinABIStackAlignInBytes, StackAlignInBytes;
5588 void CoerceToIntArgs(uint64_t TySize,
5589 SmallVectorImpl<llvm::Type *> &ArgList) const;
5590 llvm::Type* HandleAggregates(QualType Ty, uint64_t TySize) const;
5591 llvm::Type* returnAggregateInRegs(QualType RetTy, uint64_t Size) const;
5592 llvm::Type* getPaddingType(uint64_t Align, uint64_t Offset) const;
5594 MipsABIInfo(CodeGenTypes &CGT, bool _IsO32) :
5595 ABIInfo(CGT), IsO32(_IsO32), MinABIStackAlignInBytes(IsO32 ? 4 : 8),
5596 StackAlignInBytes(IsO32 ? 8 : 16) {}
5598 ABIArgInfo classifyReturnType(QualType RetTy) const;
5599 ABIArgInfo classifyArgumentType(QualType RetTy, uint64_t &Offset) const;
5600 void computeInfo(CGFunctionInfo &FI) const override;
5601 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
5602 CodeGenFunction &CGF) const override;
5603 bool shouldSignExtUnsignedType(QualType Ty) const override;
5606 class MIPSTargetCodeGenInfo : public TargetCodeGenInfo {
5607 unsigned SizeOfUnwindException;
5609 MIPSTargetCodeGenInfo(CodeGenTypes &CGT, bool IsO32)
5610 : TargetCodeGenInfo(new MipsABIInfo(CGT, IsO32)),
5611 SizeOfUnwindException(IsO32 ? 24 : 32) {}
5613 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
5617 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5618 CodeGen::CodeGenModule &CGM) const override {
5619 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D);
5621 llvm::Function *Fn = cast<llvm::Function>(GV);
5622 if (FD->hasAttr<Mips16Attr>()) {
5623 Fn->addFnAttr("mips16");
5625 else if (FD->hasAttr<NoMips16Attr>()) {
5626 Fn->addFnAttr("nomips16");
5630 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5631 llvm::Value *Address) const override;
5633 unsigned getSizeOfUnwindException() const override {
5634 return SizeOfUnwindException;
5639 void MipsABIInfo::CoerceToIntArgs(
5640 uint64_t TySize, SmallVectorImpl<llvm::Type *> &ArgList) const {
5641 llvm::IntegerType *IntTy =
5642 llvm::IntegerType::get(getVMContext(), MinABIStackAlignInBytes * 8);
5644 // Add (TySize / MinABIStackAlignInBytes) args of IntTy.
5645 for (unsigned N = TySize / (MinABIStackAlignInBytes * 8); N; --N)
5646 ArgList.push_back(IntTy);
5648 // If necessary, add one more integer type to ArgList.
5649 unsigned R = TySize % (MinABIStackAlignInBytes * 8);
5652 ArgList.push_back(llvm::IntegerType::get(getVMContext(), R));
5655 // In N32/64, an aligned double precision floating point field is passed in
5657 llvm::Type* MipsABIInfo::HandleAggregates(QualType Ty, uint64_t TySize) const {
5658 SmallVector<llvm::Type*, 8> ArgList, IntArgList;
5661 CoerceToIntArgs(TySize, ArgList);
5662 return llvm::StructType::get(getVMContext(), ArgList);
5665 if (Ty->isComplexType())
5666 return CGT.ConvertType(Ty);
5668 const RecordType *RT = Ty->getAs<RecordType>();
5670 // Unions/vectors are passed in integer registers.
5671 if (!RT || !RT->isStructureOrClassType()) {
5672 CoerceToIntArgs(TySize, ArgList);
5673 return llvm::StructType::get(getVMContext(), ArgList);
5676 const RecordDecl *RD = RT->getDecl();
5677 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
5678 assert(!(TySize % 8) && "Size of structure must be multiple of 8.");
5680 uint64_t LastOffset = 0;
5682 llvm::IntegerType *I64 = llvm::IntegerType::get(getVMContext(), 64);
5684 // Iterate over fields in the struct/class and check if there are any aligned
5686 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
5687 i != e; ++i, ++idx) {
5688 const QualType Ty = i->getType();
5689 const BuiltinType *BT = Ty->getAs<BuiltinType>();
5691 if (!BT || BT->getKind() != BuiltinType::Double)
5694 uint64_t Offset = Layout.getFieldOffset(idx);
5695 if (Offset % 64) // Ignore doubles that are not aligned.
5698 // Add ((Offset - LastOffset) / 64) args of type i64.
5699 for (unsigned j = (Offset - LastOffset) / 64; j > 0; --j)
5700 ArgList.push_back(I64);
5703 ArgList.push_back(llvm::Type::getDoubleTy(getVMContext()));
5704 LastOffset = Offset + 64;
5707 CoerceToIntArgs(TySize - LastOffset, IntArgList);
5708 ArgList.append(IntArgList.begin(), IntArgList.end());
5710 return llvm::StructType::get(getVMContext(), ArgList);
5713 llvm::Type *MipsABIInfo::getPaddingType(uint64_t OrigOffset,
5714 uint64_t Offset) const {
5715 if (OrigOffset + MinABIStackAlignInBytes > Offset)
5718 return llvm::IntegerType::get(getVMContext(), (Offset - OrigOffset) * 8);
5722 MipsABIInfo::classifyArgumentType(QualType Ty, uint64_t &Offset) const {
5723 Ty = useFirstFieldIfTransparentUnion(Ty);
5725 uint64_t OrigOffset = Offset;
5726 uint64_t TySize = getContext().getTypeSize(Ty);
5727 uint64_t Align = getContext().getTypeAlign(Ty) / 8;
5729 Align = std::min(std::max(Align, (uint64_t)MinABIStackAlignInBytes),
5730 (uint64_t)StackAlignInBytes);
5731 unsigned CurrOffset = llvm::RoundUpToAlignment(Offset, Align);
5732 Offset = CurrOffset + llvm::RoundUpToAlignment(TySize, Align * 8) / 8;
5734 if (isAggregateTypeForABI(Ty) || Ty->isVectorType()) {
5735 // Ignore empty aggregates.
5737 return ABIArgInfo::getIgnore();
5739 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
5740 Offset = OrigOffset + MinABIStackAlignInBytes;
5741 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
5744 // If we have reached here, aggregates are passed directly by coercing to
5745 // another structure type. Padding is inserted if the offset of the
5746 // aggregate is unaligned.
5747 ABIArgInfo ArgInfo =
5748 ABIArgInfo::getDirect(HandleAggregates(Ty, TySize), 0,
5749 getPaddingType(OrigOffset, CurrOffset));
5750 ArgInfo.setInReg(true);
5754 // Treat an enum type as its underlying type.
5755 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
5756 Ty = EnumTy->getDecl()->getIntegerType();
5758 // All integral types are promoted to the GPR width.
5759 if (Ty->isIntegralOrEnumerationType())
5760 return ABIArgInfo::getExtend();
5762 return ABIArgInfo::getDirect(
5763 nullptr, 0, IsO32 ? nullptr : getPaddingType(OrigOffset, CurrOffset));
5767 MipsABIInfo::returnAggregateInRegs(QualType RetTy, uint64_t Size) const {
5768 const RecordType *RT = RetTy->getAs<RecordType>();
5769 SmallVector<llvm::Type*, 8> RTList;
5771 if (RT && RT->isStructureOrClassType()) {
5772 const RecordDecl *RD = RT->getDecl();
5773 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
5774 unsigned FieldCnt = Layout.getFieldCount();
5776 // N32/64 returns struct/classes in floating point registers if the
5777 // following conditions are met:
5778 // 1. The size of the struct/class is no larger than 128-bit.
5779 // 2. The struct/class has one or two fields all of which are floating
5781 // 3. The offset of the first field is zero (this follows what gcc does).
5783 // Any other composite results are returned in integer registers.
5785 if (FieldCnt && (FieldCnt <= 2) && !Layout.getFieldOffset(0)) {
5786 RecordDecl::field_iterator b = RD->field_begin(), e = RD->field_end();
5787 for (; b != e; ++b) {
5788 const BuiltinType *BT = b->getType()->getAs<BuiltinType>();
5790 if (!BT || !BT->isFloatingPoint())
5793 RTList.push_back(CGT.ConvertType(b->getType()));
5797 return llvm::StructType::get(getVMContext(), RTList,
5798 RD->hasAttr<PackedAttr>());
5804 CoerceToIntArgs(Size, RTList);
5805 return llvm::StructType::get(getVMContext(), RTList);
5808 ABIArgInfo MipsABIInfo::classifyReturnType(QualType RetTy) const {
5809 uint64_t Size = getContext().getTypeSize(RetTy);
5811 if (RetTy->isVoidType())
5812 return ABIArgInfo::getIgnore();
5814 // O32 doesn't treat zero-sized structs differently from other structs.
5815 // However, N32/N64 ignores zero sized return values.
5816 if (!IsO32 && Size == 0)
5817 return ABIArgInfo::getIgnore();
5819 if (isAggregateTypeForABI(RetTy) || RetTy->isVectorType()) {
5821 if (RetTy->isAnyComplexType())
5822 return ABIArgInfo::getDirect();
5824 // O32 returns integer vectors in registers and N32/N64 returns all small
5825 // aggregates in registers.
5827 (RetTy->isVectorType() && !RetTy->hasFloatingRepresentation())) {
5828 ABIArgInfo ArgInfo =
5829 ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size));
5830 ArgInfo.setInReg(true);
5835 return ABIArgInfo::getIndirect(0);
5838 // Treat an enum type as its underlying type.
5839 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5840 RetTy = EnumTy->getDecl()->getIntegerType();
5842 return (RetTy->isPromotableIntegerType() ?
5843 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
5846 void MipsABIInfo::computeInfo(CGFunctionInfo &FI) const {
5847 ABIArgInfo &RetInfo = FI.getReturnInfo();
5848 if (!getCXXABI().classifyReturnType(FI))
5849 RetInfo = classifyReturnType(FI.getReturnType());
5851 // Check if a pointer to an aggregate is passed as a hidden argument.
5852 uint64_t Offset = RetInfo.isIndirect() ? MinABIStackAlignInBytes : 0;
5854 for (auto &I : FI.arguments())
5855 I.info = classifyArgumentType(I.type, Offset);
5858 llvm::Value* MipsABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
5859 CodeGenFunction &CGF) const {
5860 llvm::Type *BP = CGF.Int8PtrTy;
5861 llvm::Type *BPP = CGF.Int8PtrPtrTy;
5863 // Integer arguments are promoted to 32-bit on O32 and 64-bit on N32/N64.
5864 // Pointers are also promoted in the same way but this only matters for N32.
5865 unsigned SlotSizeInBits = IsO32 ? 32 : 64;
5866 unsigned PtrWidth = getTarget().getPointerWidth(0);
5867 if ((Ty->isIntegerType() &&
5868 CGF.getContext().getIntWidth(Ty) < SlotSizeInBits) ||
5869 (Ty->isPointerType() && PtrWidth < SlotSizeInBits)) {
5870 Ty = CGF.getContext().getIntTypeForBitwidth(SlotSizeInBits,
5871 Ty->isSignedIntegerType());
5874 CGBuilderTy &Builder = CGF.Builder;
5875 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap");
5876 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur");
5878 std::min(getContext().getTypeAlign(Ty) / 8, StackAlignInBytes);
5879 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
5880 llvm::Value *AddrTyped;
5881 llvm::IntegerType *IntTy = (PtrWidth == 32) ? CGF.Int32Ty : CGF.Int64Ty;
5883 if (TypeAlign > MinABIStackAlignInBytes) {
5884 llvm::Value *AddrAsInt = CGF.Builder.CreatePtrToInt(Addr, IntTy);
5885 llvm::Value *Inc = llvm::ConstantInt::get(IntTy, TypeAlign - 1);
5886 llvm::Value *Mask = llvm::ConstantInt::get(IntTy, -TypeAlign);
5887 llvm::Value *Add = CGF.Builder.CreateAdd(AddrAsInt, Inc);
5888 llvm::Value *And = CGF.Builder.CreateAnd(Add, Mask);
5889 AddrTyped = CGF.Builder.CreateIntToPtr(And, PTy);
5892 AddrTyped = Builder.CreateBitCast(Addr, PTy);
5894 llvm::Value *AlignedAddr = Builder.CreateBitCast(AddrTyped, BP);
5895 TypeAlign = std::max((unsigned)TypeAlign, MinABIStackAlignInBytes);
5896 unsigned ArgSizeInBits = CGF.getContext().getTypeSize(Ty);
5897 uint64_t Offset = llvm::RoundUpToAlignment(ArgSizeInBits / 8, TypeAlign);
5898 llvm::Value *NextAddr =
5899 Builder.CreateGEP(AlignedAddr, llvm::ConstantInt::get(IntTy, Offset),
5901 Builder.CreateStore(NextAddr, VAListAddrAsBPP);
5906 bool MipsABIInfo::shouldSignExtUnsignedType(QualType Ty) const {
5907 int TySize = getContext().getTypeSize(Ty);
5909 // MIPS64 ABI requires unsigned 32 bit integers to be sign extended.
5910 if (Ty->isUnsignedIntegerOrEnumerationType() && TySize == 32)
5917 MIPSTargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5918 llvm::Value *Address) const {
5919 // This information comes from gcc's implementation, which seems to
5920 // as canonical as it gets.
5922 // Everything on MIPS is 4 bytes. Double-precision FP registers
5923 // are aliased to pairs of single-precision FP registers.
5924 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
5926 // 0-31 are the general purpose registers, $0 - $31.
5927 // 32-63 are the floating-point registers, $f0 - $f31.
5928 // 64 and 65 are the multiply/divide registers, $hi and $lo.
5929 // 66 is the (notional, I think) register for signal-handler return.
5930 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 65);
5932 // 67-74 are the floating-point status registers, $fcc0 - $fcc7.
5933 // They are one bit wide and ignored here.
5935 // 80-111 are the coprocessor 0 registers, $c0r0 - $c0r31.
5936 // (coprocessor 1 is the FP unit)
5937 // 112-143 are the coprocessor 2 registers, $c2r0 - $c2r31.
5938 // 144-175 are the coprocessor 3 registers, $c3r0 - $c3r31.
5939 // 176-181 are the DSP accumulator registers.
5940 AssignToArrayRange(CGF.Builder, Address, Four8, 80, 181);
5944 //===----------------------------------------------------------------------===//
5945 // TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults.
5946 // Currently subclassed only to implement custom OpenCL C function attribute
5948 //===----------------------------------------------------------------------===//
5952 class TCETargetCodeGenInfo : public DefaultTargetCodeGenInfo {
5954 TCETargetCodeGenInfo(CodeGenTypes &CGT)
5955 : DefaultTargetCodeGenInfo(CGT) {}
5957 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5958 CodeGen::CodeGenModule &M) const override;
5961 void TCETargetCodeGenInfo::setTargetAttributes(
5962 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
5963 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D);
5966 llvm::Function *F = cast<llvm::Function>(GV);
5968 if (M.getLangOpts().OpenCL) {
5969 if (FD->hasAttr<OpenCLKernelAttr>()) {
5970 // OpenCL C Kernel functions are not subject to inlining
5971 F->addFnAttr(llvm::Attribute::NoInline);
5972 const ReqdWorkGroupSizeAttr *Attr = FD->getAttr<ReqdWorkGroupSizeAttr>();
5974 // Convert the reqd_work_group_size() attributes to metadata.
5975 llvm::LLVMContext &Context = F->getContext();
5976 llvm::NamedMDNode *OpenCLMetadata =
5977 M.getModule().getOrInsertNamedMetadata(
5978 "opencl.kernel_wg_size_info");
5980 SmallVector<llvm::Metadata *, 5> Operands;
5981 Operands.push_back(llvm::ConstantAsMetadata::get(F));
5984 llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
5985 M.Int32Ty, llvm::APInt(32, Attr->getXDim()))));
5987 llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
5988 M.Int32Ty, llvm::APInt(32, Attr->getYDim()))));
5990 llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
5991 M.Int32Ty, llvm::APInt(32, Attr->getZDim()))));
5993 // Add a boolean constant operand for "required" (true) or "hint"
5994 // (false) for implementing the work_group_size_hint attr later.
5995 // Currently always true as the hint is not yet implemented.
5997 llvm::ConstantAsMetadata::get(llvm::ConstantInt::getTrue(Context)));
5998 OpenCLMetadata->addOperand(llvm::MDNode::get(Context, Operands));
6006 //===----------------------------------------------------------------------===//
6007 // Hexagon ABI Implementation
6008 //===----------------------------------------------------------------------===//
6012 class HexagonABIInfo : public ABIInfo {
6016 HexagonABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
6020 ABIArgInfo classifyReturnType(QualType RetTy) const;
6021 ABIArgInfo classifyArgumentType(QualType RetTy) const;
6023 void computeInfo(CGFunctionInfo &FI) const override;
6025 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
6026 CodeGenFunction &CGF) const override;
6029 class HexagonTargetCodeGenInfo : public TargetCodeGenInfo {
6031 HexagonTargetCodeGenInfo(CodeGenTypes &CGT)
6032 :TargetCodeGenInfo(new HexagonABIInfo(CGT)) {}
6034 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
6041 void HexagonABIInfo::computeInfo(CGFunctionInfo &FI) const {
6042 if (!getCXXABI().classifyReturnType(FI))
6043 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
6044 for (auto &I : FI.arguments())
6045 I.info = classifyArgumentType(I.type);
6048 ABIArgInfo HexagonABIInfo::classifyArgumentType(QualType Ty) const {
6049 if (!isAggregateTypeForABI(Ty)) {
6050 // Treat an enum type as its underlying type.
6051 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6052 Ty = EnumTy->getDecl()->getIntegerType();
6054 return (Ty->isPromotableIntegerType() ?
6055 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6058 // Ignore empty records.
6059 if (isEmptyRecord(getContext(), Ty, true))
6060 return ABIArgInfo::getIgnore();
6062 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
6063 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
6065 uint64_t Size = getContext().getTypeSize(Ty);
6067 return ABIArgInfo::getIndirect(0, /*ByVal=*/true);
6068 // Pass in the smallest viable integer type.
6070 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
6072 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6074 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
6076 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
6079 ABIArgInfo HexagonABIInfo::classifyReturnType(QualType RetTy) const {
6080 if (RetTy->isVoidType())
6081 return ABIArgInfo::getIgnore();
6083 // Large vector types should be returned via memory.
6084 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 64)
6085 return ABIArgInfo::getIndirect(0);
6087 if (!isAggregateTypeForABI(RetTy)) {
6088 // Treat an enum type as its underlying type.
6089 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
6090 RetTy = EnumTy->getDecl()->getIntegerType();
6092 return (RetTy->isPromotableIntegerType() ?
6093 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6096 if (isEmptyRecord(getContext(), RetTy, true))
6097 return ABIArgInfo::getIgnore();
6099 // Aggregates <= 8 bytes are returned in r0; other aggregates
6100 // are returned indirectly.
6101 uint64_t Size = getContext().getTypeSize(RetTy);
6103 // Return in the smallest viable integer type.
6105 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
6107 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
6109 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6110 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
6113 return ABIArgInfo::getIndirect(0, /*ByVal=*/true);
6116 llvm::Value *HexagonABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
6117 CodeGenFunction &CGF) const {
6118 // FIXME: Need to handle alignment
6119 llvm::Type *BPP = CGF.Int8PtrPtrTy;
6121 CGBuilderTy &Builder = CGF.Builder;
6122 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP,
6124 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur");
6126 llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
6127 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy);
6130 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, 4);
6131 llvm::Value *NextAddr =
6132 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset),
6134 Builder.CreateStore(NextAddr, VAListAddrAsBPP);
6139 //===----------------------------------------------------------------------===//
6140 // AMDGPU ABI Implementation
6141 //===----------------------------------------------------------------------===//
6145 class AMDGPUTargetCodeGenInfo : public TargetCodeGenInfo {
6147 AMDGPUTargetCodeGenInfo(CodeGenTypes &CGT)
6148 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
6149 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6150 CodeGen::CodeGenModule &M) const override;
6155 void AMDGPUTargetCodeGenInfo::setTargetAttributes(
6157 llvm::GlobalValue *GV,
6158 CodeGen::CodeGenModule &M) const {
6159 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D);
6163 if (const auto Attr = FD->getAttr<AMDGPUNumVGPRAttr>()) {
6164 llvm::Function *F = cast<llvm::Function>(GV);
6165 uint32_t NumVGPR = Attr->getNumVGPR();
6167 F->addFnAttr("amdgpu_num_vgpr", llvm::utostr(NumVGPR));
6170 if (const auto Attr = FD->getAttr<AMDGPUNumSGPRAttr>()) {
6171 llvm::Function *F = cast<llvm::Function>(GV);
6172 unsigned NumSGPR = Attr->getNumSGPR();
6174 F->addFnAttr("amdgpu_num_sgpr", llvm::utostr(NumSGPR));
6179 //===----------------------------------------------------------------------===//
6180 // SPARC v9 ABI Implementation.
6181 // Based on the SPARC Compliance Definition version 2.4.1.
6183 // Function arguments a mapped to a nominal "parameter array" and promoted to
6184 // registers depending on their type. Each argument occupies 8 or 16 bytes in
6185 // the array, structs larger than 16 bytes are passed indirectly.
6187 // One case requires special care:
6194 // When a struct mixed is passed by value, it only occupies 8 bytes in the
6195 // parameter array, but the int is passed in an integer register, and the float
6196 // is passed in a floating point register. This is represented as two arguments
6197 // with the LLVM IR inreg attribute:
6199 // declare void f(i32 inreg %i, float inreg %f)
6201 // The code generator will only allocate 4 bytes from the parameter array for
6202 // the inreg arguments. All other arguments are allocated a multiple of 8
6206 class SparcV9ABIInfo : public ABIInfo {
6208 SparcV9ABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
6211 ABIArgInfo classifyType(QualType RetTy, unsigned SizeLimit) const;
6212 void computeInfo(CGFunctionInfo &FI) const override;
6213 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
6214 CodeGenFunction &CGF) const override;
6216 // Coercion type builder for structs passed in registers. The coercion type
6217 // serves two purposes:
6219 // 1. Pad structs to a multiple of 64 bits, so they are passed 'left-aligned'
6221 // 2. Expose aligned floating point elements as first-level elements, so the
6222 // code generator knows to pass them in floating point registers.
6224 // We also compute the InReg flag which indicates that the struct contains
6225 // aligned 32-bit floats.
6227 struct CoerceBuilder {
6228 llvm::LLVMContext &Context;
6229 const llvm::DataLayout &DL;
6230 SmallVector<llvm::Type*, 8> Elems;
6234 CoerceBuilder(llvm::LLVMContext &c, const llvm::DataLayout &dl)
6235 : Context(c), DL(dl), Size(0), InReg(false) {}
6237 // Pad Elems with integers until Size is ToSize.
6238 void pad(uint64_t ToSize) {
6239 assert(ToSize >= Size && "Cannot remove elements");
6243 // Finish the current 64-bit word.
6244 uint64_t Aligned = llvm::RoundUpToAlignment(Size, 64);
6245 if (Aligned > Size && Aligned <= ToSize) {
6246 Elems.push_back(llvm::IntegerType::get(Context, Aligned - Size));
6250 // Add whole 64-bit words.
6251 while (Size + 64 <= ToSize) {
6252 Elems.push_back(llvm::Type::getInt64Ty(Context));
6256 // Final in-word padding.
6257 if (Size < ToSize) {
6258 Elems.push_back(llvm::IntegerType::get(Context, ToSize - Size));
6263 // Add a floating point element at Offset.
6264 void addFloat(uint64_t Offset, llvm::Type *Ty, unsigned Bits) {
6265 // Unaligned floats are treated as integers.
6268 // The InReg flag is only required if there are any floats < 64 bits.
6272 Elems.push_back(Ty);
6273 Size = Offset + Bits;
6276 // Add a struct type to the coercion type, starting at Offset (in bits).
6277 void addStruct(uint64_t Offset, llvm::StructType *StrTy) {
6278 const llvm::StructLayout *Layout = DL.getStructLayout(StrTy);
6279 for (unsigned i = 0, e = StrTy->getNumElements(); i != e; ++i) {
6280 llvm::Type *ElemTy = StrTy->getElementType(i);
6281 uint64_t ElemOffset = Offset + Layout->getElementOffsetInBits(i);
6282 switch (ElemTy->getTypeID()) {
6283 case llvm::Type::StructTyID:
6284 addStruct(ElemOffset, cast<llvm::StructType>(ElemTy));
6286 case llvm::Type::FloatTyID:
6287 addFloat(ElemOffset, ElemTy, 32);
6289 case llvm::Type::DoubleTyID:
6290 addFloat(ElemOffset, ElemTy, 64);
6292 case llvm::Type::FP128TyID:
6293 addFloat(ElemOffset, ElemTy, 128);
6295 case llvm::Type::PointerTyID:
6296 if (ElemOffset % 64 == 0) {
6298 Elems.push_back(ElemTy);
6308 // Check if Ty is a usable substitute for the coercion type.
6309 bool isUsableType(llvm::StructType *Ty) const {
6310 return llvm::makeArrayRef(Elems) == Ty->elements();
6313 // Get the coercion type as a literal struct type.
6314 llvm::Type *getType() const {
6315 if (Elems.size() == 1)
6316 return Elems.front();
6318 return llvm::StructType::get(Context, Elems);
6322 } // end anonymous namespace
6325 SparcV9ABIInfo::classifyType(QualType Ty, unsigned SizeLimit) const {
6326 if (Ty->isVoidType())
6327 return ABIArgInfo::getIgnore();
6329 uint64_t Size = getContext().getTypeSize(Ty);
6331 // Anything too big to fit in registers is passed with an explicit indirect
6332 // pointer / sret pointer.
6333 if (Size > SizeLimit)
6334 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
6336 // Treat an enum type as its underlying type.
6337 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6338 Ty = EnumTy->getDecl()->getIntegerType();
6340 // Integer types smaller than a register are extended.
6341 if (Size < 64 && Ty->isIntegerType())
6342 return ABIArgInfo::getExtend();
6344 // Other non-aggregates go in registers.
6345 if (!isAggregateTypeForABI(Ty))
6346 return ABIArgInfo::getDirect();
6348 // If a C++ object has either a non-trivial copy constructor or a non-trivial
6349 // destructor, it is passed with an explicit indirect pointer / sret pointer.
6350 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
6351 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
6353 // This is a small aggregate type that should be passed in registers.
6354 // Build a coercion type from the LLVM struct type.
6355 llvm::StructType *StrTy = dyn_cast<llvm::StructType>(CGT.ConvertType(Ty));
6357 return ABIArgInfo::getDirect();
6359 CoerceBuilder CB(getVMContext(), getDataLayout());
6360 CB.addStruct(0, StrTy);
6361 CB.pad(llvm::RoundUpToAlignment(CB.DL.getTypeSizeInBits(StrTy), 64));
6363 // Try to use the original type for coercion.
6364 llvm::Type *CoerceTy = CB.isUsableType(StrTy) ? StrTy : CB.getType();
6367 return ABIArgInfo::getDirectInReg(CoerceTy);
6369 return ABIArgInfo::getDirect(CoerceTy);
6372 llvm::Value *SparcV9ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
6373 CodeGenFunction &CGF) const {
6374 ABIArgInfo AI = classifyType(Ty, 16 * 8);
6375 llvm::Type *ArgTy = CGT.ConvertType(Ty);
6376 if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
6377 AI.setCoerceToType(ArgTy);
6379 llvm::Type *BPP = CGF.Int8PtrPtrTy;
6380 CGBuilderTy &Builder = CGF.Builder;
6381 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap");
6382 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur");
6383 llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
6384 llvm::Value *ArgAddr;
6387 switch (AI.getKind()) {
6388 case ABIArgInfo::Expand:
6389 case ABIArgInfo::InAlloca:
6390 llvm_unreachable("Unsupported ABI kind for va_arg");
6392 case ABIArgInfo::Extend:
6395 .CreateConstGEP1_32(Addr, 8 - getDataLayout().getTypeAllocSize(ArgTy),
6399 case ABIArgInfo::Direct:
6400 Stride = getDataLayout().getTypeAllocSize(AI.getCoerceToType());
6404 case ABIArgInfo::Indirect:
6406 ArgAddr = Builder.CreateBitCast(Addr,
6407 llvm::PointerType::getUnqual(ArgPtrTy),
6409 ArgAddr = Builder.CreateLoad(ArgAddr, "indirect.arg");
6412 case ABIArgInfo::Ignore:
6413 return llvm::UndefValue::get(ArgPtrTy);
6417 Addr = Builder.CreateConstGEP1_32(Addr, Stride, "ap.next");
6418 Builder.CreateStore(Addr, VAListAddrAsBPP);
6420 return Builder.CreatePointerCast(ArgAddr, ArgPtrTy, "arg.addr");
6423 void SparcV9ABIInfo::computeInfo(CGFunctionInfo &FI) const {
6424 FI.getReturnInfo() = classifyType(FI.getReturnType(), 32 * 8);
6425 for (auto &I : FI.arguments())
6426 I.info = classifyType(I.type, 16 * 8);
6430 class SparcV9TargetCodeGenInfo : public TargetCodeGenInfo {
6432 SparcV9TargetCodeGenInfo(CodeGenTypes &CGT)
6433 : TargetCodeGenInfo(new SparcV9ABIInfo(CGT)) {}
6435 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
6439 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
6440 llvm::Value *Address) const override;
6442 } // end anonymous namespace
6445 SparcV9TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
6446 llvm::Value *Address) const {
6447 // This is calculated from the LLVM and GCC tables and verified
6448 // against gcc output. AFAIK all ABIs use the same encoding.
6450 CodeGen::CGBuilderTy &Builder = CGF.Builder;
6452 llvm::IntegerType *i8 = CGF.Int8Ty;
6453 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
6454 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
6456 // 0-31: the 8-byte general-purpose registers
6457 AssignToArrayRange(Builder, Address, Eight8, 0, 31);
6459 // 32-63: f0-31, the 4-byte floating-point registers
6460 AssignToArrayRange(Builder, Address, Four8, 32, 63);
6470 AssignToArrayRange(Builder, Address, Eight8, 64, 71);
6472 // 72-87: d0-15, the 8-byte floating-point registers
6473 AssignToArrayRange(Builder, Address, Eight8, 72, 87);
6479 //===----------------------------------------------------------------------===//
6480 // XCore ABI Implementation
6481 //===----------------------------------------------------------------------===//
6485 /// A SmallStringEnc instance is used to build up the TypeString by passing
6486 /// it by reference between functions that append to it.
6487 typedef llvm::SmallString<128> SmallStringEnc;
6489 /// TypeStringCache caches the meta encodings of Types.
6491 /// The reason for caching TypeStrings is two fold:
6492 /// 1. To cache a type's encoding for later uses;
6493 /// 2. As a means to break recursive member type inclusion.
6495 /// A cache Entry can have a Status of:
6496 /// NonRecursive: The type encoding is not recursive;
6497 /// Recursive: The type encoding is recursive;
6498 /// Incomplete: An incomplete TypeString;
6499 /// IncompleteUsed: An incomplete TypeString that has been used in a
6500 /// Recursive type encoding.
6502 /// A NonRecursive entry will have all of its sub-members expanded as fully
6503 /// as possible. Whilst it may contain types which are recursive, the type
6504 /// itself is not recursive and thus its encoding may be safely used whenever
6505 /// the type is encountered.
6507 /// A Recursive entry will have all of its sub-members expanded as fully as
6508 /// possible. The type itself is recursive and it may contain other types which
6509 /// are recursive. The Recursive encoding must not be used during the expansion
6510 /// of a recursive type's recursive branch. For simplicity the code uses
6511 /// IncompleteCount to reject all usage of Recursive encodings for member types.
6513 /// An Incomplete entry is always a RecordType and only encodes its
6514 /// identifier e.g. "s(S){}". Incomplete 'StubEnc' entries are ephemeral and
6515 /// are placed into the cache during type expansion as a means to identify and
6516 /// handle recursive inclusion of types as sub-members. If there is recursion
6517 /// the entry becomes IncompleteUsed.
6519 /// During the expansion of a RecordType's members:
6521 /// If the cache contains a NonRecursive encoding for the member type, the
6522 /// cached encoding is used;
6524 /// If the cache contains a Recursive encoding for the member type, the
6525 /// cached encoding is 'Swapped' out, as it may be incorrect, and...
6527 /// If the member is a RecordType, an Incomplete encoding is placed into the
6528 /// cache to break potential recursive inclusion of itself as a sub-member;
6530 /// Once a member RecordType has been expanded, its temporary incomplete
6531 /// entry is removed from the cache. If a Recursive encoding was swapped out
6532 /// it is swapped back in;
6534 /// If an incomplete entry is used to expand a sub-member, the incomplete
6535 /// entry is marked as IncompleteUsed. The cache keeps count of how many
6536 /// IncompleteUsed entries it currently contains in IncompleteUsedCount;
6538 /// If a member's encoding is found to be a NonRecursive or Recursive viz:
6539 /// IncompleteUsedCount==0, the member's encoding is added to the cache.
6540 /// Else the member is part of a recursive type and thus the recursion has
6541 /// been exited too soon for the encoding to be correct for the member.
6543 class TypeStringCache {
6544 enum Status {NonRecursive, Recursive, Incomplete, IncompleteUsed};
6546 std::string Str; // The encoded TypeString for the type.
6547 enum Status State; // Information about the encoding in 'Str'.
6548 std::string Swapped; // A temporary place holder for a Recursive encoding
6549 // during the expansion of RecordType's members.
6551 std::map<const IdentifierInfo *, struct Entry> Map;
6552 unsigned IncompleteCount; // Number of Incomplete entries in the Map.
6553 unsigned IncompleteUsedCount; // Number of IncompleteUsed entries in the Map.
6555 TypeStringCache() : IncompleteCount(0), IncompleteUsedCount(0) {};
6556 void addIncomplete(const IdentifierInfo *ID, std::string StubEnc);
6557 bool removeIncomplete(const IdentifierInfo *ID);
6558 void addIfComplete(const IdentifierInfo *ID, StringRef Str,
6560 StringRef lookupStr(const IdentifierInfo *ID);
6563 /// TypeString encodings for enum & union fields must be order.
6564 /// FieldEncoding is a helper for this ordering process.
6565 class FieldEncoding {
6569 FieldEncoding(bool b, SmallStringEnc &e) : HasName(b), Enc(e.c_str()) {};
6570 StringRef str() {return Enc.c_str();};
6571 bool operator<(const FieldEncoding &rhs) const {
6572 if (HasName != rhs.HasName) return HasName;
6573 return Enc < rhs.Enc;
6577 class XCoreABIInfo : public DefaultABIInfo {
6579 XCoreABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
6580 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
6581 CodeGenFunction &CGF) const override;
6584 class XCoreTargetCodeGenInfo : public TargetCodeGenInfo {
6585 mutable TypeStringCache TSC;
6587 XCoreTargetCodeGenInfo(CodeGenTypes &CGT)
6588 :TargetCodeGenInfo(new XCoreABIInfo(CGT)) {}
6589 void emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
6590 CodeGen::CodeGenModule &M) const override;
6593 } // End anonymous namespace.
6595 llvm::Value *XCoreABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
6596 CodeGenFunction &CGF) const {
6597 CGBuilderTy &Builder = CGF.Builder;
6600 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr,
6602 llvm::Value *AP = Builder.CreateLoad(VAListAddrAsBPP);
6604 // Handle the argument.
6605 ABIArgInfo AI = classifyArgumentType(Ty);
6606 llvm::Type *ArgTy = CGT.ConvertType(Ty);
6607 if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
6608 AI.setCoerceToType(ArgTy);
6609 llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
6611 uint64_t ArgSize = 0;
6612 switch (AI.getKind()) {
6613 case ABIArgInfo::Expand:
6614 case ABIArgInfo::InAlloca:
6615 llvm_unreachable("Unsupported ABI kind for va_arg");
6616 case ABIArgInfo::Ignore:
6617 Val = llvm::UndefValue::get(ArgPtrTy);
6620 case ABIArgInfo::Extend:
6621 case ABIArgInfo::Direct:
6622 Val = Builder.CreatePointerCast(AP, ArgPtrTy);
6623 ArgSize = getDataLayout().getTypeAllocSize(AI.getCoerceToType());
6627 case ABIArgInfo::Indirect:
6628 llvm::Value *ArgAddr;
6629 ArgAddr = Builder.CreateBitCast(AP, llvm::PointerType::getUnqual(ArgPtrTy));
6630 ArgAddr = Builder.CreateLoad(ArgAddr);
6631 Val = Builder.CreatePointerCast(ArgAddr, ArgPtrTy);
6636 // Increment the VAList.
6638 llvm::Value *APN = Builder.CreateConstGEP1_32(AP, ArgSize);
6639 Builder.CreateStore(APN, VAListAddrAsBPP);
6644 /// During the expansion of a RecordType, an incomplete TypeString is placed
6645 /// into the cache as a means to identify and break recursion.
6646 /// If there is a Recursive encoding in the cache, it is swapped out and will
6647 /// be reinserted by removeIncomplete().
6648 /// All other types of encoding should have been used rather than arriving here.
6649 void TypeStringCache::addIncomplete(const IdentifierInfo *ID,
6650 std::string StubEnc) {
6654 assert( (E.Str.empty() || E.State == Recursive) &&
6655 "Incorrectly use of addIncomplete");
6656 assert(!StubEnc.empty() && "Passing an empty string to addIncomplete()");
6657 E.Swapped.swap(E.Str); // swap out the Recursive
6658 E.Str.swap(StubEnc);
6659 E.State = Incomplete;
6663 /// Once the RecordType has been expanded, the temporary incomplete TypeString
6664 /// must be removed from the cache.
6665 /// If a Recursive was swapped out by addIncomplete(), it will be replaced.
6666 /// Returns true if the RecordType was defined recursively.
6667 bool TypeStringCache::removeIncomplete(const IdentifierInfo *ID) {
6670 auto I = Map.find(ID);
6671 assert(I != Map.end() && "Entry not present");
6672 Entry &E = I->second;
6673 assert( (E.State == Incomplete ||
6674 E.State == IncompleteUsed) &&
6675 "Entry must be an incomplete type");
6676 bool IsRecursive = false;
6677 if (E.State == IncompleteUsed) {
6678 // We made use of our Incomplete encoding, thus we are recursive.
6680 --IncompleteUsedCount;
6682 if (E.Swapped.empty())
6685 // Swap the Recursive back.
6686 E.Swapped.swap(E.Str);
6688 E.State = Recursive;
6694 /// Add the encoded TypeString to the cache only if it is NonRecursive or
6695 /// Recursive (viz: all sub-members were expanded as fully as possible).
6696 void TypeStringCache::addIfComplete(const IdentifierInfo *ID, StringRef Str,
6698 if (!ID || IncompleteUsedCount)
6699 return; // No key or it is is an incomplete sub-type so don't add.
6701 if (IsRecursive && !E.Str.empty()) {
6702 assert(E.State==Recursive && E.Str.size() == Str.size() &&
6703 "This is not the same Recursive entry");
6704 // The parent container was not recursive after all, so we could have used
6705 // this Recursive sub-member entry after all, but we assumed the worse when
6706 // we started viz: IncompleteCount!=0.
6709 assert(E.Str.empty() && "Entry already present");
6711 E.State = IsRecursive? Recursive : NonRecursive;
6714 /// Return a cached TypeString encoding for the ID. If there isn't one, or we
6715 /// are recursively expanding a type (IncompleteCount != 0) and the cached
6716 /// encoding is Recursive, return an empty StringRef.
6717 StringRef TypeStringCache::lookupStr(const IdentifierInfo *ID) {
6719 return StringRef(); // We have no key.
6720 auto I = Map.find(ID);
6722 return StringRef(); // We have no encoding.
6723 Entry &E = I->second;
6724 if (E.State == Recursive && IncompleteCount)
6725 return StringRef(); // We don't use Recursive encodings for member types.
6727 if (E.State == Incomplete) {
6728 // The incomplete type is being used to break out of recursion.
6729 E.State = IncompleteUsed;
6730 ++IncompleteUsedCount;
6732 return E.Str.c_str();
6735 /// The XCore ABI includes a type information section that communicates symbol
6736 /// type information to the linker. The linker uses this information to verify
6737 /// safety/correctness of things such as array bound and pointers et al.
6738 /// The ABI only requires C (and XC) language modules to emit TypeStrings.
6739 /// This type information (TypeString) is emitted into meta data for all global
6740 /// symbols: definitions, declarations, functions & variables.
6742 /// The TypeString carries type, qualifier, name, size & value details.
6743 /// Please see 'Tools Development Guide' section 2.16.2 for format details:
6744 /// https://www.xmos.com/download/public/Tools-Development-Guide%28X9114A%29.pdf
6745 /// The output is tested by test/CodeGen/xcore-stringtype.c.
6747 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
6748 CodeGen::CodeGenModule &CGM, TypeStringCache &TSC);
6750 /// XCore uses emitTargetMD to emit TypeString metadata for global symbols.
6751 void XCoreTargetCodeGenInfo::emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
6752 CodeGen::CodeGenModule &CGM) const {
6754 if (getTypeString(Enc, D, CGM, TSC)) {
6755 llvm::LLVMContext &Ctx = CGM.getModule().getContext();
6756 llvm::SmallVector<llvm::Metadata *, 2> MDVals;
6757 MDVals.push_back(llvm::ConstantAsMetadata::get(GV));
6758 MDVals.push_back(llvm::MDString::get(Ctx, Enc.str()));
6759 llvm::NamedMDNode *MD =
6760 CGM.getModule().getOrInsertNamedMetadata("xcore.typestrings");
6761 MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
6765 static bool appendType(SmallStringEnc &Enc, QualType QType,
6766 const CodeGen::CodeGenModule &CGM,
6767 TypeStringCache &TSC);
6769 /// Helper function for appendRecordType().
6770 /// Builds a SmallVector containing the encoded field types in declaration
6772 static bool extractFieldType(SmallVectorImpl<FieldEncoding> &FE,
6773 const RecordDecl *RD,
6774 const CodeGen::CodeGenModule &CGM,
6775 TypeStringCache &TSC) {
6776 for (const auto *Field : RD->fields()) {
6779 Enc += Field->getName();
6781 if (Field->isBitField()) {
6783 llvm::raw_svector_ostream OS(Enc);
6785 OS << Field->getBitWidthValue(CGM.getContext());
6789 if (!appendType(Enc, Field->getType(), CGM, TSC))
6791 if (Field->isBitField())
6794 FE.emplace_back(!Field->getName().empty(), Enc);
6799 /// Appends structure and union types to Enc and adds encoding to cache.
6800 /// Recursively calls appendType (via extractFieldType) for each field.
6801 /// Union types have their fields ordered according to the ABI.
6802 static bool appendRecordType(SmallStringEnc &Enc, const RecordType *RT,
6803 const CodeGen::CodeGenModule &CGM,
6804 TypeStringCache &TSC, const IdentifierInfo *ID) {
6805 // Append the cached TypeString if we have one.
6806 StringRef TypeString = TSC.lookupStr(ID);
6807 if (!TypeString.empty()) {
6812 // Start to emit an incomplete TypeString.
6813 size_t Start = Enc.size();
6814 Enc += (RT->isUnionType()? 'u' : 's');
6817 Enc += ID->getName();
6820 // We collect all encoded fields and order as necessary.
6821 bool IsRecursive = false;
6822 const RecordDecl *RD = RT->getDecl()->getDefinition();
6823 if (RD && !RD->field_empty()) {
6824 // An incomplete TypeString stub is placed in the cache for this RecordType
6825 // so that recursive calls to this RecordType will use it whilst building a
6826 // complete TypeString for this RecordType.
6827 SmallVector<FieldEncoding, 16> FE;
6828 std::string StubEnc(Enc.substr(Start).str());
6829 StubEnc += '}'; // StubEnc now holds a valid incomplete TypeString.
6830 TSC.addIncomplete(ID, std::move(StubEnc));
6831 if (!extractFieldType(FE, RD, CGM, TSC)) {
6832 (void) TSC.removeIncomplete(ID);
6835 IsRecursive = TSC.removeIncomplete(ID);
6836 // The ABI requires unions to be sorted but not structures.
6837 // See FieldEncoding::operator< for sort algorithm.
6838 if (RT->isUnionType())
6839 std::sort(FE.begin(), FE.end());
6840 // We can now complete the TypeString.
6841 unsigned E = FE.size();
6842 for (unsigned I = 0; I != E; ++I) {
6849 TSC.addIfComplete(ID, Enc.substr(Start), IsRecursive);
6853 /// Appends enum types to Enc and adds the encoding to the cache.
6854 static bool appendEnumType(SmallStringEnc &Enc, const EnumType *ET,
6855 TypeStringCache &TSC,
6856 const IdentifierInfo *ID) {
6857 // Append the cached TypeString if we have one.
6858 StringRef TypeString = TSC.lookupStr(ID);
6859 if (!TypeString.empty()) {
6864 size_t Start = Enc.size();
6867 Enc += ID->getName();
6870 // We collect all encoded enumerations and order them alphanumerically.
6871 if (const EnumDecl *ED = ET->getDecl()->getDefinition()) {
6872 SmallVector<FieldEncoding, 16> FE;
6873 for (auto I = ED->enumerator_begin(), E = ED->enumerator_end(); I != E;
6875 SmallStringEnc EnumEnc;
6877 EnumEnc += I->getName();
6879 I->getInitVal().toString(EnumEnc);
6881 FE.push_back(FieldEncoding(!I->getName().empty(), EnumEnc));
6883 std::sort(FE.begin(), FE.end());
6884 unsigned E = FE.size();
6885 for (unsigned I = 0; I != E; ++I) {
6892 TSC.addIfComplete(ID, Enc.substr(Start), false);
6896 /// Appends type's qualifier to Enc.
6897 /// This is done prior to appending the type's encoding.
6898 static void appendQualifier(SmallStringEnc &Enc, QualType QT) {
6899 // Qualifiers are emitted in alphabetical order.
6900 static const char *Table[] = {"","c:","r:","cr:","v:","cv:","rv:","crv:"};
6902 if (QT.isConstQualified())
6904 if (QT.isRestrictQualified())
6906 if (QT.isVolatileQualified())
6908 Enc += Table[Lookup];
6911 /// Appends built-in types to Enc.
6912 static bool appendBuiltinType(SmallStringEnc &Enc, const BuiltinType *BT) {
6913 const char *EncType;
6914 switch (BT->getKind()) {
6915 case BuiltinType::Void:
6918 case BuiltinType::Bool:
6921 case BuiltinType::Char_U:
6924 case BuiltinType::UChar:
6927 case BuiltinType::SChar:
6930 case BuiltinType::UShort:
6933 case BuiltinType::Short:
6936 case BuiltinType::UInt:
6939 case BuiltinType::Int:
6942 case BuiltinType::ULong:
6945 case BuiltinType::Long:
6948 case BuiltinType::ULongLong:
6951 case BuiltinType::LongLong:
6954 case BuiltinType::Float:
6957 case BuiltinType::Double:
6960 case BuiltinType::LongDouble:
6970 /// Appends a pointer encoding to Enc before calling appendType for the pointee.
6971 static bool appendPointerType(SmallStringEnc &Enc, const PointerType *PT,
6972 const CodeGen::CodeGenModule &CGM,
6973 TypeStringCache &TSC) {
6975 if (!appendType(Enc, PT->getPointeeType(), CGM, TSC))
6981 /// Appends array encoding to Enc before calling appendType for the element.
6982 static bool appendArrayType(SmallStringEnc &Enc, QualType QT,
6983 const ArrayType *AT,
6984 const CodeGen::CodeGenModule &CGM,
6985 TypeStringCache &TSC, StringRef NoSizeEnc) {
6986 if (AT->getSizeModifier() != ArrayType::Normal)
6989 if (const ConstantArrayType *CAT = dyn_cast<ConstantArrayType>(AT))
6990 CAT->getSize().toStringUnsigned(Enc);
6992 Enc += NoSizeEnc; // Global arrays use "*", otherwise it is "".
6994 // The Qualifiers should be attached to the type rather than the array.
6995 appendQualifier(Enc, QT);
6996 if (!appendType(Enc, AT->getElementType(), CGM, TSC))
7002 /// Appends a function encoding to Enc, calling appendType for the return type
7003 /// and the arguments.
7004 static bool appendFunctionType(SmallStringEnc &Enc, const FunctionType *FT,
7005 const CodeGen::CodeGenModule &CGM,
7006 TypeStringCache &TSC) {
7008 if (!appendType(Enc, FT->getReturnType(), CGM, TSC))
7011 if (const FunctionProtoType *FPT = FT->getAs<FunctionProtoType>()) {
7012 // N.B. we are only interested in the adjusted param types.
7013 auto I = FPT->param_type_begin();
7014 auto E = FPT->param_type_end();
7017 if (!appendType(Enc, *I, CGM, TSC))
7023 if (FPT->isVariadic())
7026 if (FPT->isVariadic())
7036 /// Handles the type's qualifier before dispatching a call to handle specific
7038 static bool appendType(SmallStringEnc &Enc, QualType QType,
7039 const CodeGen::CodeGenModule &CGM,
7040 TypeStringCache &TSC) {
7042 QualType QT = QType.getCanonicalType();
7044 if (const ArrayType *AT = QT->getAsArrayTypeUnsafe())
7045 // The Qualifiers should be attached to the type rather than the array.
7046 // Thus we don't call appendQualifier() here.
7047 return appendArrayType(Enc, QT, AT, CGM, TSC, "");
7049 appendQualifier(Enc, QT);
7051 if (const BuiltinType *BT = QT->getAs<BuiltinType>())
7052 return appendBuiltinType(Enc, BT);
7054 if (const PointerType *PT = QT->getAs<PointerType>())
7055 return appendPointerType(Enc, PT, CGM, TSC);
7057 if (const EnumType *ET = QT->getAs<EnumType>())
7058 return appendEnumType(Enc, ET, TSC, QT.getBaseTypeIdentifier());
7060 if (const RecordType *RT = QT->getAsStructureType())
7061 return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
7063 if (const RecordType *RT = QT->getAsUnionType())
7064 return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
7066 if (const FunctionType *FT = QT->getAs<FunctionType>())
7067 return appendFunctionType(Enc, FT, CGM, TSC);
7072 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
7073 CodeGen::CodeGenModule &CGM, TypeStringCache &TSC) {
7077 if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) {
7078 if (FD->getLanguageLinkage() != CLanguageLinkage)
7080 return appendType(Enc, FD->getType(), CGM, TSC);
7083 if (const VarDecl *VD = dyn_cast<VarDecl>(D)) {
7084 if (VD->getLanguageLinkage() != CLanguageLinkage)
7086 QualType QT = VD->getType().getCanonicalType();
7087 if (const ArrayType *AT = QT->getAsArrayTypeUnsafe()) {
7088 // Global ArrayTypes are given a size of '*' if the size is unknown.
7089 // The Qualifiers should be attached to the type rather than the array.
7090 // Thus we don't call appendQualifier() here.
7091 return appendArrayType(Enc, QT, AT, CGM, TSC, "*");
7093 return appendType(Enc, QT, CGM, TSC);
7099 //===----------------------------------------------------------------------===//
7101 //===----------------------------------------------------------------------===//
7103 const llvm::Triple &CodeGenModule::getTriple() const {
7104 return getTarget().getTriple();
7107 bool CodeGenModule::supportsCOMDAT() const {
7108 return !getTriple().isOSBinFormatMachO();
7111 const TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() {
7112 if (TheTargetCodeGenInfo)
7113 return *TheTargetCodeGenInfo;
7115 const llvm::Triple &Triple = getTarget().getTriple();
7116 switch (Triple.getArch()) {
7118 return *(TheTargetCodeGenInfo = new DefaultTargetCodeGenInfo(Types));
7120 case llvm::Triple::le32:
7121 return *(TheTargetCodeGenInfo = new PNaClTargetCodeGenInfo(Types));
7122 case llvm::Triple::mips:
7123 case llvm::Triple::mipsel:
7124 if (Triple.getOS() == llvm::Triple::NaCl)
7125 return *(TheTargetCodeGenInfo = new PNaClTargetCodeGenInfo(Types));
7126 return *(TheTargetCodeGenInfo = new MIPSTargetCodeGenInfo(Types, true));
7128 case llvm::Triple::mips64:
7129 case llvm::Triple::mips64el:
7130 return *(TheTargetCodeGenInfo = new MIPSTargetCodeGenInfo(Types, false));
7132 case llvm::Triple::aarch64:
7133 case llvm::Triple::aarch64_be: {
7134 AArch64ABIInfo::ABIKind Kind = AArch64ABIInfo::AAPCS;
7135 if (getTarget().getABI() == "darwinpcs")
7136 Kind = AArch64ABIInfo::DarwinPCS;
7138 return *(TheTargetCodeGenInfo = new AArch64TargetCodeGenInfo(Types, Kind));
7141 case llvm::Triple::arm:
7142 case llvm::Triple::armeb:
7143 case llvm::Triple::thumb:
7144 case llvm::Triple::thumbeb:
7146 if (Triple.getOS() == llvm::Triple::Win32) {
7147 TheTargetCodeGenInfo =
7148 new WindowsARMTargetCodeGenInfo(Types, ARMABIInfo::AAPCS_VFP);
7149 return *TheTargetCodeGenInfo;
7152 ARMABIInfo::ABIKind Kind = ARMABIInfo::AAPCS;
7153 if (getTarget().getABI() == "apcs-gnu")
7154 Kind = ARMABIInfo::APCS;
7155 else if (CodeGenOpts.FloatABI == "hard" ||
7156 (CodeGenOpts.FloatABI != "soft" &&
7157 Triple.getEnvironment() == llvm::Triple::GNUEABIHF))
7158 Kind = ARMABIInfo::AAPCS_VFP;
7160 return *(TheTargetCodeGenInfo = new ARMTargetCodeGenInfo(Types, Kind));
7163 case llvm::Triple::ppc:
7164 return *(TheTargetCodeGenInfo = new PPC32TargetCodeGenInfo(Types));
7165 case llvm::Triple::ppc64:
7166 if (Triple.isOSBinFormatELF()) {
7167 PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv1;
7168 if (getTarget().getABI() == "elfv2")
7169 Kind = PPC64_SVR4_ABIInfo::ELFv2;
7170 bool HasQPX = getTarget().getABI() == "elfv1-qpx";
7172 return *(TheTargetCodeGenInfo =
7173 new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX));
7175 return *(TheTargetCodeGenInfo = new PPC64TargetCodeGenInfo(Types));
7176 case llvm::Triple::ppc64le: {
7177 assert(Triple.isOSBinFormatELF() && "PPC64 LE non-ELF not supported!");
7178 PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv2;
7179 if (getTarget().getABI() == "elfv1" || getTarget().getABI() == "elfv1-qpx")
7180 Kind = PPC64_SVR4_ABIInfo::ELFv1;
7181 bool HasQPX = getTarget().getABI() == "elfv1-qpx";
7183 return *(TheTargetCodeGenInfo =
7184 new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX));
7187 case llvm::Triple::nvptx:
7188 case llvm::Triple::nvptx64:
7189 return *(TheTargetCodeGenInfo = new NVPTXTargetCodeGenInfo(Types));
7191 case llvm::Triple::msp430:
7192 return *(TheTargetCodeGenInfo = new MSP430TargetCodeGenInfo(Types));
7194 case llvm::Triple::systemz: {
7195 bool HasVector = getTarget().getABI() == "vector";
7196 return *(TheTargetCodeGenInfo = new SystemZTargetCodeGenInfo(Types,
7200 case llvm::Triple::tce:
7201 return *(TheTargetCodeGenInfo = new TCETargetCodeGenInfo(Types));
7203 case llvm::Triple::x86: {
7204 bool IsDarwinVectorABI = Triple.isOSDarwin();
7205 bool IsSmallStructInRegABI =
7206 X86_32TargetCodeGenInfo::isStructReturnInRegABI(Triple, CodeGenOpts);
7207 bool IsWin32FloatStructABI = Triple.isOSWindows() && !Triple.isOSCygMing();
7209 if (Triple.getOS() == llvm::Triple::Win32) {
7210 return *(TheTargetCodeGenInfo = new WinX86_32TargetCodeGenInfo(
7211 Types, IsDarwinVectorABI, IsSmallStructInRegABI,
7212 IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters));
7214 return *(TheTargetCodeGenInfo = new X86_32TargetCodeGenInfo(
7215 Types, IsDarwinVectorABI, IsSmallStructInRegABI,
7216 IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters));
7220 case llvm::Triple::x86_64: {
7221 StringRef ABI = getTarget().getABI();
7222 X86AVXABILevel AVXLevel = (ABI == "avx512" ? X86AVXABILevel::AVX512 :
7223 ABI == "avx" ? X86AVXABILevel::AVX :
7224 X86AVXABILevel::None);
7226 switch (Triple.getOS()) {
7227 case llvm::Triple::Win32:
7228 return *(TheTargetCodeGenInfo =
7229 new WinX86_64TargetCodeGenInfo(Types, AVXLevel));
7230 case llvm::Triple::PS4:
7231 return *(TheTargetCodeGenInfo =
7232 new PS4TargetCodeGenInfo(Types, AVXLevel));
7234 return *(TheTargetCodeGenInfo =
7235 new X86_64TargetCodeGenInfo(Types, AVXLevel));
7238 case llvm::Triple::hexagon:
7239 return *(TheTargetCodeGenInfo = new HexagonTargetCodeGenInfo(Types));
7240 case llvm::Triple::r600:
7241 return *(TheTargetCodeGenInfo = new AMDGPUTargetCodeGenInfo(Types));
7242 case llvm::Triple::amdgcn:
7243 return *(TheTargetCodeGenInfo = new AMDGPUTargetCodeGenInfo(Types));
7244 case llvm::Triple::sparcv9:
7245 return *(TheTargetCodeGenInfo = new SparcV9TargetCodeGenInfo(Types));
7246 case llvm::Triple::xcore:
7247 return *(TheTargetCodeGenInfo = new XCoreTargetCodeGenInfo(Types));