1 //===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // These classes wrap the information about a call or function
11 // definition used to handle ABI compliancy.
13 //===----------------------------------------------------------------------===//
15 #include "TargetInfo.h"
19 #include "CodeGenFunction.h"
20 #include "clang/AST/RecordLayout.h"
21 #include "clang/CodeGen/CGFunctionInfo.h"
22 #include "clang/CodeGen/SwiftCallingConv.h"
23 #include "clang/Frontend/CodeGenOptions.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/Triple.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Type.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include <algorithm> // std::sort
31 using namespace clang;
32 using namespace CodeGen;
34 // Helper for coercing an aggregate argument or return value into an integer
35 // array of the same size (including padding) and alignment. This alternate
36 // coercion happens only for the RenderScript ABI and can be removed after
37 // runtimes that rely on it are no longer supported.
39 // RenderScript assumes that the size of the argument / return value in the IR
40 // is the same as the size of the corresponding qualified type. This helper
41 // coerces the aggregate type into an array of the same size (including
42 // padding). This coercion is used in lieu of expansion of struct members or
43 // other canonical coercions that return a coerced-type of larger size.
45 // Ty - The argument / return value type
46 // Context - The associated ASTContext
47 // LLVMContext - The associated LLVMContext
48 static ABIArgInfo coerceToIntArray(QualType Ty,
50 llvm::LLVMContext &LLVMContext) {
51 // Alignment and Size are measured in bits.
52 const uint64_t Size = Context.getTypeSize(Ty);
53 const uint64_t Alignment = Context.getTypeAlign(Ty);
54 llvm::Type *IntType = llvm::Type::getIntNTy(LLVMContext, Alignment);
55 const uint64_t NumElements = (Size + Alignment - 1) / Alignment;
56 return ABIArgInfo::getDirect(llvm::ArrayType::get(IntType, NumElements));
59 static void AssignToArrayRange(CodeGen::CGBuilderTy &Builder,
64 // Alternatively, we could emit this as a loop in the source.
65 for (unsigned I = FirstIndex; I <= LastIndex; ++I) {
67 Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I);
68 Builder.CreateAlignedStore(Value, Cell, CharUnits::One());
72 static bool isAggregateTypeForABI(QualType T) {
73 return !CodeGenFunction::hasScalarEvaluationKind(T) ||
74 T->isMemberFunctionPointerType();
78 ABIInfo::getNaturalAlignIndirect(QualType Ty, bool ByRef, bool Realign,
79 llvm::Type *Padding) const {
80 return ABIArgInfo::getIndirect(getContext().getTypeAlignInChars(Ty),
81 ByRef, Realign, Padding);
85 ABIInfo::getNaturalAlignIndirectInReg(QualType Ty, bool Realign) const {
86 return ABIArgInfo::getIndirectInReg(getContext().getTypeAlignInChars(Ty),
87 /*ByRef*/ false, Realign);
90 Address ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
92 return Address::invalid();
95 ABIInfo::~ABIInfo() {}
97 /// Does the given lowering require more than the given number of
98 /// registers when expanded?
100 /// This is intended to be the basis of a reasonable basic implementation
101 /// of should{Pass,Return}IndirectlyForSwift.
103 /// For most targets, a limit of four total registers is reasonable; this
104 /// limits the amount of code required in order to move around the value
105 /// in case it wasn't produced immediately prior to the call by the caller
106 /// (or wasn't produced in exactly the right registers) or isn't used
107 /// immediately within the callee. But some targets may need to further
108 /// limit the register count due to an inability to support that many
109 /// return registers.
110 static bool occupiesMoreThan(CodeGenTypes &cgt,
111 ArrayRef<llvm::Type*> scalarTypes,
112 unsigned maxAllRegisters) {
113 unsigned intCount = 0, fpCount = 0;
114 for (llvm::Type *type : scalarTypes) {
115 if (type->isPointerTy()) {
117 } else if (auto intTy = dyn_cast<llvm::IntegerType>(type)) {
118 auto ptrWidth = cgt.getTarget().getPointerWidth(0);
119 intCount += (intTy->getBitWidth() + ptrWidth - 1) / ptrWidth;
121 assert(type->isVectorTy() || type->isFloatingPointTy());
126 return (intCount + fpCount > maxAllRegisters);
129 bool SwiftABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize,
131 unsigned numElts) const {
132 // The default implementation of this assumes that the target guarantees
133 // 128-bit SIMD support but nothing more.
134 return (vectorSize.getQuantity() > 8 && vectorSize.getQuantity() <= 16);
137 static CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT,
139 const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl());
141 return CGCXXABI::RAA_Default;
142 return CXXABI.getRecordArgABI(RD);
145 static CGCXXABI::RecordArgABI getRecordArgABI(QualType T,
147 const RecordType *RT = T->getAs<RecordType>();
149 return CGCXXABI::RAA_Default;
150 return getRecordArgABI(RT, CXXABI);
153 /// Pass transparent unions as if they were the type of the first element. Sema
154 /// should ensure that all elements of the union have the same "machine type".
155 static QualType useFirstFieldIfTransparentUnion(QualType Ty) {
156 if (const RecordType *UT = Ty->getAsUnionType()) {
157 const RecordDecl *UD = UT->getDecl();
158 if (UD->hasAttr<TransparentUnionAttr>()) {
159 assert(!UD->field_empty() && "sema created an empty transparent union");
160 return UD->field_begin()->getType();
166 CGCXXABI &ABIInfo::getCXXABI() const {
167 return CGT.getCXXABI();
170 ASTContext &ABIInfo::getContext() const {
171 return CGT.getContext();
174 llvm::LLVMContext &ABIInfo::getVMContext() const {
175 return CGT.getLLVMContext();
178 const llvm::DataLayout &ABIInfo::getDataLayout() const {
179 return CGT.getDataLayout();
182 const TargetInfo &ABIInfo::getTarget() const {
183 return CGT.getTarget();
186 bool ABIInfo:: isAndroid() const { return getTarget().getTriple().isAndroid(); }
188 bool ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
192 bool ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
193 uint64_t Members) const {
197 bool ABIInfo::shouldSignExtUnsignedType(QualType Ty) const {
201 LLVM_DUMP_METHOD void ABIArgInfo::dump() const {
202 raw_ostream &OS = llvm::errs();
203 OS << "(ABIArgInfo Kind=";
206 OS << "Direct Type=";
207 if (llvm::Type *Ty = getCoerceToType())
219 OS << "InAlloca Offset=" << getInAllocaFieldIndex();
222 OS << "Indirect Align=" << getIndirectAlign().getQuantity()
223 << " ByVal=" << getIndirectByVal()
224 << " Realign=" << getIndirectRealign();
229 case CoerceAndExpand:
230 OS << "CoerceAndExpand Type=";
231 getCoerceAndExpandType()->print(OS);
237 // Dynamically round a pointer up to a multiple of the given alignment.
238 static llvm::Value *emitRoundPointerUpToAlignment(CodeGenFunction &CGF,
241 llvm::Value *PtrAsInt = Ptr;
242 // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align;
243 PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
244 PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
245 llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1));
246 PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
247 llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity()));
248 PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt,
250 Ptr->getName() + ".aligned");
254 /// Emit va_arg for a platform using the common void* representation,
255 /// where arguments are simply emitted in an array of slots on the stack.
257 /// This version implements the core direct-value passing rules.
259 /// \param SlotSize - The size and alignment of a stack slot.
260 /// Each argument will be allocated to a multiple of this number of
261 /// slots, and all the slots will be aligned to this value.
262 /// \param AllowHigherAlign - The slot alignment is not a cap;
263 /// an argument type with an alignment greater than the slot size
264 /// will be emitted on a higher-alignment address, potentially
265 /// leaving one or more empty slots behind as padding. If this
266 /// is false, the returned address might be less-aligned than
268 static Address emitVoidPtrDirectVAArg(CodeGenFunction &CGF,
270 llvm::Type *DirectTy,
271 CharUnits DirectSize,
272 CharUnits DirectAlign,
274 bool AllowHigherAlign) {
275 // Cast the element type to i8* if necessary. Some platforms define
276 // va_list as a struct containing an i8* instead of just an i8*.
277 if (VAListAddr.getElementType() != CGF.Int8PtrTy)
278 VAListAddr = CGF.Builder.CreateElementBitCast(VAListAddr, CGF.Int8PtrTy);
280 llvm::Value *Ptr = CGF.Builder.CreateLoad(VAListAddr, "argp.cur");
282 // If the CC aligns values higher than the slot size, do so if needed.
283 Address Addr = Address::invalid();
284 if (AllowHigherAlign && DirectAlign > SlotSize) {
285 Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign),
288 Addr = Address(Ptr, SlotSize);
291 // Advance the pointer past the argument, then store that back.
292 CharUnits FullDirectSize = DirectSize.alignTo(SlotSize);
293 llvm::Value *NextPtr =
294 CGF.Builder.CreateConstInBoundsByteGEP(Addr.getPointer(), FullDirectSize,
296 CGF.Builder.CreateStore(NextPtr, VAListAddr);
298 // If the argument is smaller than a slot, and this is a big-endian
299 // target, the argument will be right-adjusted in its slot.
300 if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() &&
301 !DirectTy->isStructTy()) {
302 Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize);
305 Addr = CGF.Builder.CreateElementBitCast(Addr, DirectTy);
309 /// Emit va_arg for a platform using the common void* representation,
310 /// where arguments are simply emitted in an array of slots on the stack.
312 /// \param IsIndirect - Values of this type are passed indirectly.
313 /// \param ValueInfo - The size and alignment of this type, generally
314 /// computed with getContext().getTypeInfoInChars(ValueTy).
315 /// \param SlotSizeAndAlign - The size and alignment of a stack slot.
316 /// Each argument will be allocated to a multiple of this number of
317 /// slots, and all the slots will be aligned to this value.
318 /// \param AllowHigherAlign - The slot alignment is not a cap;
319 /// an argument type with an alignment greater than the slot size
320 /// will be emitted on a higher-alignment address, potentially
321 /// leaving one or more empty slots behind as padding.
322 static Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr,
323 QualType ValueTy, bool IsIndirect,
324 std::pair<CharUnits, CharUnits> ValueInfo,
325 CharUnits SlotSizeAndAlign,
326 bool AllowHigherAlign) {
327 // The size and alignment of the value that was passed directly.
328 CharUnits DirectSize, DirectAlign;
330 DirectSize = CGF.getPointerSize();
331 DirectAlign = CGF.getPointerAlign();
333 DirectSize = ValueInfo.first;
334 DirectAlign = ValueInfo.second;
337 // Cast the address we've calculated to the right type.
338 llvm::Type *DirectTy = CGF.ConvertTypeForMem(ValueTy);
340 DirectTy = DirectTy->getPointerTo(0);
342 Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy,
343 DirectSize, DirectAlign,
348 Addr = Address(CGF.Builder.CreateLoad(Addr), ValueInfo.second);
355 static Address emitMergePHI(CodeGenFunction &CGF,
356 Address Addr1, llvm::BasicBlock *Block1,
357 Address Addr2, llvm::BasicBlock *Block2,
358 const llvm::Twine &Name = "") {
359 assert(Addr1.getType() == Addr2.getType());
360 llvm::PHINode *PHI = CGF.Builder.CreatePHI(Addr1.getType(), 2, Name);
361 PHI->addIncoming(Addr1.getPointer(), Block1);
362 PHI->addIncoming(Addr2.getPointer(), Block2);
363 CharUnits Align = std::min(Addr1.getAlignment(), Addr2.getAlignment());
364 return Address(PHI, Align);
367 TargetCodeGenInfo::~TargetCodeGenInfo() { delete Info; }
369 // If someone can figure out a general rule for this, that would be great.
370 // It's probably just doomed to be platform-dependent, though.
371 unsigned TargetCodeGenInfo::getSizeOfUnwindException() const {
373 // x86-64 FreeBSD, Linux, Darwin
374 // x86-32 FreeBSD, Linux, Darwin
375 // PowerPC Linux, Darwin
376 // ARM Darwin (*not* EABI)
381 bool TargetCodeGenInfo::isNoProtoCallVariadic(const CallArgList &args,
382 const FunctionNoProtoType *fnType) const {
383 // The following conventions are known to require this to be false:
386 // For everything else, we just prefer false unless we opt out.
391 TargetCodeGenInfo::getDependentLibraryOption(llvm::StringRef Lib,
392 llvm::SmallString<24> &Opt) const {
393 // This assumes the user is passing a library name like "rt" instead of a
394 // filename like "librt.a/so", and that they don't care whether it's static or
400 unsigned TargetCodeGenInfo::getOpenCLKernelCallingConv() const {
401 // OpenCL kernels are called via an explicit runtime API with arguments
402 // set with clSetKernelArg(), not as normal sub-functions.
403 // Return SPIR_KERNEL by default as the kernel calling convention to
404 // ensure the fingerprint is fixed such way that each OpenCL argument
405 // gets one matching argument in the produced kernel function argument
406 // list to enable feasible implementation of clSetKernelArg() with
407 // aggregates etc. In case we would use the default C calling conv here,
408 // clSetKernelArg() might break depending on the target-specific
409 // conventions; different targets might split structs passed as values
410 // to multiple function arguments etc.
411 return llvm::CallingConv::SPIR_KERNEL;
414 llvm::Constant *TargetCodeGenInfo::getNullPointer(const CodeGen::CodeGenModule &CGM,
415 llvm::PointerType *T, QualType QT) const {
416 return llvm::ConstantPointerNull::get(T);
419 unsigned TargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
420 const VarDecl *D) const {
421 assert(!CGM.getLangOpts().OpenCL &&
422 !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
423 "Address space agnostic languages only");
424 return D ? D->getType().getAddressSpace()
425 : static_cast<unsigned>(LangAS::Default);
428 llvm::Value *TargetCodeGenInfo::performAddrSpaceCast(
429 CodeGen::CodeGenFunction &CGF, llvm::Value *Src, unsigned SrcAddr,
430 unsigned DestAddr, llvm::Type *DestTy, bool isNonNull) const {
431 // Since target may map different address spaces in AST to the same address
432 // space, an address space conversion may end up as a bitcast.
433 if (auto *C = dyn_cast<llvm::Constant>(Src))
434 return performAddrSpaceCast(CGF.CGM, C, SrcAddr, DestAddr, DestTy);
435 return CGF.Builder.CreatePointerBitCastOrAddrSpaceCast(Src, DestTy);
439 TargetCodeGenInfo::performAddrSpaceCast(CodeGenModule &CGM, llvm::Constant *Src,
440 unsigned SrcAddr, unsigned DestAddr,
441 llvm::Type *DestTy) const {
442 // Since target may map different address spaces in AST to the same address
443 // space, an address space conversion may end up as a bitcast.
444 return llvm::ConstantExpr::getPointerCast(Src, DestTy);
447 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays);
449 /// isEmptyField - Return true iff a the field is "empty", that is it
450 /// is an unnamed bit-field or an (array of) empty record(s).
451 static bool isEmptyField(ASTContext &Context, const FieldDecl *FD,
453 if (FD->isUnnamedBitfield())
456 QualType FT = FD->getType();
458 // Constant arrays of empty records count as empty, strip them off.
459 // Constant arrays of zero length always count as empty.
461 while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
462 if (AT->getSize() == 0)
464 FT = AT->getElementType();
467 const RecordType *RT = FT->getAs<RecordType>();
471 // C++ record fields are never empty, at least in the Itanium ABI.
473 // FIXME: We should use a predicate for whether this behavior is true in the
475 if (isa<CXXRecordDecl>(RT->getDecl()))
478 return isEmptyRecord(Context, FT, AllowArrays);
481 /// isEmptyRecord - Return true iff a structure contains only empty
482 /// fields. Note that a structure with a flexible array member is not
483 /// considered empty.
484 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) {
485 const RecordType *RT = T->getAs<RecordType>();
488 const RecordDecl *RD = RT->getDecl();
489 if (RD->hasFlexibleArrayMember())
492 // If this is a C++ record, check the bases first.
493 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
494 for (const auto &I : CXXRD->bases())
495 if (!isEmptyRecord(Context, I.getType(), true))
498 for (const auto *I : RD->fields())
499 if (!isEmptyField(Context, I, AllowArrays))
504 /// isSingleElementStruct - Determine if a structure is a "single
505 /// element struct", i.e. it has exactly one non-empty field or
506 /// exactly one field which is itself a single element
507 /// struct. Structures with flexible array members are never
508 /// considered single element structs.
510 /// \return The field declaration for the single non-empty field, if
512 static const Type *isSingleElementStruct(QualType T, ASTContext &Context) {
513 const RecordType *RT = T->getAs<RecordType>();
517 const RecordDecl *RD = RT->getDecl();
518 if (RD->hasFlexibleArrayMember())
521 const Type *Found = nullptr;
523 // If this is a C++ record, check the bases first.
524 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
525 for (const auto &I : CXXRD->bases()) {
526 // Ignore empty records.
527 if (isEmptyRecord(Context, I.getType(), true))
530 // If we already found an element then this isn't a single-element struct.
534 // If this is non-empty and not a single element struct, the composite
535 // cannot be a single element struct.
536 Found = isSingleElementStruct(I.getType(), Context);
542 // Check for single element.
543 for (const auto *FD : RD->fields()) {
544 QualType FT = FD->getType();
546 // Ignore empty fields.
547 if (isEmptyField(Context, FD, true))
550 // If we already found an element then this isn't a single-element
555 // Treat single element arrays as the element.
556 while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
557 if (AT->getSize().getZExtValue() != 1)
559 FT = AT->getElementType();
562 if (!isAggregateTypeForABI(FT)) {
563 Found = FT.getTypePtr();
565 Found = isSingleElementStruct(FT, Context);
571 // We don't consider a struct a single-element struct if it has
572 // padding beyond the element type.
573 if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T))
580 Address EmitVAArgInstr(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
581 const ABIArgInfo &AI) {
582 // This default implementation defers to the llvm backend's va_arg
583 // instruction. It can handle only passing arguments directly
584 // (typically only handled in the backend for primitive types), or
585 // aggregates passed indirectly by pointer (NOTE: if the "byval"
586 // flag has ABI impact in the callee, this implementation cannot
589 // Only a few cases are covered here at the moment -- those needed
590 // by the default abi.
593 if (AI.isIndirect()) {
594 assert(!AI.getPaddingType() &&
595 "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
597 !AI.getIndirectRealign() &&
598 "Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!");
600 auto TyInfo = CGF.getContext().getTypeInfoInChars(Ty);
601 CharUnits TyAlignForABI = TyInfo.second;
604 llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty));
606 CGF.Builder.CreateVAArg(VAListAddr.getPointer(), BaseTy);
607 return Address(Addr, TyAlignForABI);
609 assert((AI.isDirect() || AI.isExtend()) &&
610 "Unexpected ArgInfo Kind in generic VAArg emitter!");
612 assert(!AI.getInReg() &&
613 "Unexpected InReg seen in arginfo in generic VAArg emitter!");
614 assert(!AI.getPaddingType() &&
615 "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
616 assert(!AI.getDirectOffset() &&
617 "Unexpected DirectOffset seen in arginfo in generic VAArg emitter!");
618 assert(!AI.getCoerceToType() &&
619 "Unexpected CoerceToType seen in arginfo in generic VAArg emitter!");
621 Address Temp = CGF.CreateMemTemp(Ty, "varet");
622 Val = CGF.Builder.CreateVAArg(VAListAddr.getPointer(), CGF.ConvertType(Ty));
623 CGF.Builder.CreateStore(Val, Temp);
628 /// DefaultABIInfo - The default implementation for ABI specific
629 /// details. This implementation provides information which results in
630 /// self-consistent and sensible LLVM IR generation, but does not
631 /// conform to any particular ABI.
632 class DefaultABIInfo : public ABIInfo {
634 DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
636 ABIArgInfo classifyReturnType(QualType RetTy) const;
637 ABIArgInfo classifyArgumentType(QualType RetTy) const;
639 void computeInfo(CGFunctionInfo &FI) const override {
640 if (!getCXXABI().classifyReturnType(FI))
641 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
642 for (auto &I : FI.arguments())
643 I.info = classifyArgumentType(I.type);
646 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
647 QualType Ty) const override {
648 return EmitVAArgInstr(CGF, VAListAddr, Ty, classifyArgumentType(Ty));
652 class DefaultTargetCodeGenInfo : public TargetCodeGenInfo {
654 DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
655 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
658 ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty) const {
659 Ty = useFirstFieldIfTransparentUnion(Ty);
661 if (isAggregateTypeForABI(Ty)) {
662 // Records with non-trivial destructors/copy-constructors should not be
664 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
665 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
667 return getNaturalAlignIndirect(Ty);
670 // Treat an enum type as its underlying type.
671 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
672 Ty = EnumTy->getDecl()->getIntegerType();
674 return (Ty->isPromotableIntegerType() ?
675 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
678 ABIArgInfo DefaultABIInfo::classifyReturnType(QualType RetTy) const {
679 if (RetTy->isVoidType())
680 return ABIArgInfo::getIgnore();
682 if (isAggregateTypeForABI(RetTy))
683 return getNaturalAlignIndirect(RetTy);
685 // Treat an enum type as its underlying type.
686 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
687 RetTy = EnumTy->getDecl()->getIntegerType();
689 return (RetTy->isPromotableIntegerType() ?
690 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
693 //===----------------------------------------------------------------------===//
694 // WebAssembly ABI Implementation
696 // This is a very simple ABI that relies a lot on DefaultABIInfo.
697 //===----------------------------------------------------------------------===//
699 class WebAssemblyABIInfo final : public DefaultABIInfo {
701 explicit WebAssemblyABIInfo(CodeGen::CodeGenTypes &CGT)
702 : DefaultABIInfo(CGT) {}
705 ABIArgInfo classifyReturnType(QualType RetTy) const;
706 ABIArgInfo classifyArgumentType(QualType Ty) const;
708 // DefaultABIInfo's classifyReturnType and classifyArgumentType are
709 // non-virtual, but computeInfo and EmitVAArg are virtual, so we
711 void computeInfo(CGFunctionInfo &FI) const override {
712 if (!getCXXABI().classifyReturnType(FI))
713 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
714 for (auto &Arg : FI.arguments())
715 Arg.info = classifyArgumentType(Arg.type);
718 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
719 QualType Ty) const override;
722 class WebAssemblyTargetCodeGenInfo final : public TargetCodeGenInfo {
724 explicit WebAssemblyTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
725 : TargetCodeGenInfo(new WebAssemblyABIInfo(CGT)) {}
728 /// \brief Classify argument of given type \p Ty.
729 ABIArgInfo WebAssemblyABIInfo::classifyArgumentType(QualType Ty) const {
730 Ty = useFirstFieldIfTransparentUnion(Ty);
732 if (isAggregateTypeForABI(Ty)) {
733 // Records with non-trivial destructors/copy-constructors should not be
735 if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
736 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
737 // Ignore empty structs/unions.
738 if (isEmptyRecord(getContext(), Ty, true))
739 return ABIArgInfo::getIgnore();
740 // Lower single-element structs to just pass a regular value. TODO: We
741 // could do reasonable-size multiple-element structs too, using getExpand(),
742 // though watch out for things like bitfields.
743 if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
744 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
747 // Otherwise just do the default thing.
748 return DefaultABIInfo::classifyArgumentType(Ty);
751 ABIArgInfo WebAssemblyABIInfo::classifyReturnType(QualType RetTy) const {
752 if (isAggregateTypeForABI(RetTy)) {
753 // Records with non-trivial destructors/copy-constructors should not be
754 // returned by value.
755 if (!getRecordArgABI(RetTy, getCXXABI())) {
756 // Ignore empty structs/unions.
757 if (isEmptyRecord(getContext(), RetTy, true))
758 return ABIArgInfo::getIgnore();
759 // Lower single-element structs to just return a regular value. TODO: We
760 // could do reasonable-size multiple-element structs too, using
761 // ABIArgInfo::getDirect().
762 if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
763 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
767 // Otherwise just do the default thing.
768 return DefaultABIInfo::classifyReturnType(RetTy);
771 Address WebAssemblyABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
773 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect=*/ false,
774 getContext().getTypeInfoInChars(Ty),
775 CharUnits::fromQuantity(4),
776 /*AllowHigherAlign=*/ true);
779 //===----------------------------------------------------------------------===//
780 // le32/PNaCl bitcode ABI Implementation
782 // This is a simplified version of the x86_32 ABI. Arguments and return values
783 // are always passed on the stack.
784 //===----------------------------------------------------------------------===//
786 class PNaClABIInfo : public ABIInfo {
788 PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
790 ABIArgInfo classifyReturnType(QualType RetTy) const;
791 ABIArgInfo classifyArgumentType(QualType RetTy) const;
793 void computeInfo(CGFunctionInfo &FI) const override;
794 Address EmitVAArg(CodeGenFunction &CGF,
795 Address VAListAddr, QualType Ty) const override;
798 class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
800 PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
801 : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {}
804 void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
805 if (!getCXXABI().classifyReturnType(FI))
806 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
808 for (auto &I : FI.arguments())
809 I.info = classifyArgumentType(I.type);
812 Address PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
814 // The PNaCL ABI is a bit odd, in that varargs don't use normal
815 // function classification. Structs get passed directly for varargs
816 // functions, through a rewriting transform in
817 // pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows
818 // this target to actually support a va_arg instructions with an
819 // aggregate type, unlike other targets.
820 return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
823 /// \brief Classify argument of given type \p Ty.
824 ABIArgInfo PNaClABIInfo::classifyArgumentType(QualType Ty) const {
825 if (isAggregateTypeForABI(Ty)) {
826 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
827 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
828 return getNaturalAlignIndirect(Ty);
829 } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
830 // Treat an enum type as its underlying type.
831 Ty = EnumTy->getDecl()->getIntegerType();
832 } else if (Ty->isFloatingType()) {
833 // Floating-point types don't go inreg.
834 return ABIArgInfo::getDirect();
837 return (Ty->isPromotableIntegerType() ?
838 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
841 ABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const {
842 if (RetTy->isVoidType())
843 return ABIArgInfo::getIgnore();
845 // In the PNaCl ABI we always return records/structures on the stack.
846 if (isAggregateTypeForABI(RetTy))
847 return getNaturalAlignIndirect(RetTy);
849 // Treat an enum type as its underlying type.
850 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
851 RetTy = EnumTy->getDecl()->getIntegerType();
853 return (RetTy->isPromotableIntegerType() ?
854 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
857 /// IsX86_MMXType - Return true if this is an MMX type.
858 bool IsX86_MMXType(llvm::Type *IRType) {
859 // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
860 return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
861 cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
862 IRType->getScalarSizeInBits() != 64;
865 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
866 StringRef Constraint,
868 if ((Constraint == "y" || Constraint == "&y") && Ty->isVectorTy()) {
869 if (cast<llvm::VectorType>(Ty)->getBitWidth() != 64) {
870 // Invalid MMX constraint
874 return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
877 // No operation needed
881 /// Returns true if this type can be passed in SSE registers with the
882 /// X86_VectorCall calling convention. Shared between x86_32 and x86_64.
883 static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) {
884 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
885 if (BT->isFloatingPoint() && BT->getKind() != BuiltinType::Half)
887 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
888 // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX
889 // registers specially.
890 unsigned VecSize = Context.getTypeSize(VT);
891 if (VecSize == 128 || VecSize == 256 || VecSize == 512)
897 /// Returns true if this aggregate is small enough to be passed in SSE registers
898 /// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64.
899 static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) {
900 return NumMembers <= 4;
903 /// Returns a Homogeneous Vector Aggregate ABIArgInfo, used in X86.
904 static ABIArgInfo getDirectX86Hva(llvm::Type* T = nullptr) {
905 auto AI = ABIArgInfo::getDirect(T);
907 AI.setCanBeFlattened(false);
911 //===----------------------------------------------------------------------===//
912 // X86-32 ABI Implementation
913 //===----------------------------------------------------------------------===//
915 /// \brief Similar to llvm::CCState, but for Clang.
917 CCState(unsigned CC) : CC(CC), FreeRegs(0), FreeSSERegs(0) {}
921 unsigned FreeSSERegs;
925 // Vectorcall only allows the first 6 parameters to be passed in registers.
926 VectorcallMaxParamNumAsReg = 6
929 /// X86_32ABIInfo - The X86-32 ABI information.
930 class X86_32ABIInfo : public SwiftABIInfo {
936 static const unsigned MinABIStackAlignInBytes = 4;
938 bool IsDarwinVectorABI;
939 bool IsRetSmallStructInRegABI;
940 bool IsWin32StructABI;
943 unsigned DefaultNumRegisterParameters;
945 static bool isRegisterSize(unsigned Size) {
946 return (Size == 8 || Size == 16 || Size == 32 || Size == 64);
949 bool isHomogeneousAggregateBaseType(QualType Ty) const override {
950 // FIXME: Assumes vectorcall is in use.
951 return isX86VectorTypeForVectorCall(getContext(), Ty);
954 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
955 uint64_t NumMembers) const override {
956 // FIXME: Assumes vectorcall is in use.
957 return isX86VectorCallAggregateSmallEnough(NumMembers);
960 bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const;
962 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
963 /// such that the argument will be passed in memory.
964 ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
966 ABIArgInfo getIndirectReturnResult(QualType Ty, CCState &State) const;
968 /// \brief Return the alignment to use for the given type on the stack.
969 unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const;
971 Class classify(QualType Ty) const;
972 ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
973 ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
975 /// \brief Updates the number of available free registers, returns
976 /// true if any registers were allocated.
977 bool updateFreeRegs(QualType Ty, CCState &State) const;
979 bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
980 bool &NeedsPadding) const;
981 bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const;
983 bool canExpandIndirectArgument(QualType Ty) const;
985 /// \brief Rewrite the function info so that all memory arguments use
987 void rewriteWithInAlloca(CGFunctionInfo &FI) const;
989 void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
990 CharUnits &StackOffset, ABIArgInfo &Info,
991 QualType Type) const;
992 void computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
993 bool &UsedInAlloca) const;
997 void computeInfo(CGFunctionInfo &FI) const override;
998 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
999 QualType Ty) const override;
1001 X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1002 bool RetSmallStructInRegABI, bool Win32StructABI,
1003 unsigned NumRegisterParameters, bool SoftFloatABI)
1004 : SwiftABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
1005 IsRetSmallStructInRegABI(RetSmallStructInRegABI),
1006 IsWin32StructABI(Win32StructABI),
1007 IsSoftFloatABI(SoftFloatABI),
1008 IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()),
1009 DefaultNumRegisterParameters(NumRegisterParameters) {}
1011 bool shouldPassIndirectlyForSwift(CharUnits totalSize,
1012 ArrayRef<llvm::Type*> scalars,
1013 bool asReturnValue) const override {
1014 // LLVM's x86-32 lowering currently only assigns up to three
1015 // integer registers and three fp registers. Oddly, it'll use up to
1016 // four vector registers for vectors, but those can overlap with the
1017 // scalar registers.
1018 return occupiesMoreThan(CGT, scalars, /*total*/ 3);
1021 bool isSwiftErrorInRegister() const override {
1022 // x86-32 lowering does not support passing swifterror in a register.
1027 class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
1029 X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1030 bool RetSmallStructInRegABI, bool Win32StructABI,
1031 unsigned NumRegisterParameters, bool SoftFloatABI)
1032 : TargetCodeGenInfo(new X86_32ABIInfo(
1033 CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
1034 NumRegisterParameters, SoftFloatABI)) {}
1036 static bool isStructReturnInRegABI(
1037 const llvm::Triple &Triple, const CodeGenOptions &Opts);
1039 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
1040 CodeGen::CodeGenModule &CGM) const override;
1042 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
1043 // Darwin uses different dwarf register numbers for EH.
1044 if (CGM.getTarget().getTriple().isOSDarwin()) return 5;
1048 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1049 llvm::Value *Address) const override;
1051 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
1052 StringRef Constraint,
1053 llvm::Type* Ty) const override {
1054 return X86AdjustInlineAsmType(CGF, Constraint, Ty);
1057 void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue,
1058 std::string &Constraints,
1059 std::vector<llvm::Type *> &ResultRegTypes,
1060 std::vector<llvm::Type *> &ResultTruncRegTypes,
1061 std::vector<LValue> &ResultRegDests,
1062 std::string &AsmString,
1063 unsigned NumOutputs) const override;
1066 getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
1067 unsigned Sig = (0xeb << 0) | // jmp rel8
1068 (0x06 << 8) | // .+0x08
1071 return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
1074 StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
1075 return "movl\t%ebp, %ebp"
1076 "\t\t## marker for objc_retainAutoreleaseReturnValue";
1082 /// Rewrite input constraint references after adding some output constraints.
1083 /// In the case where there is one output and one input and we add one output,
1084 /// we need to replace all operand references greater than or equal to 1:
1087 /// The result will be:
1090 static void rewriteInputConstraintReferences(unsigned FirstIn,
1091 unsigned NumNewOuts,
1092 std::string &AsmString) {
1094 llvm::raw_string_ostream OS(Buf);
1096 while (Pos < AsmString.size()) {
1097 size_t DollarStart = AsmString.find('$', Pos);
1098 if (DollarStart == std::string::npos)
1099 DollarStart = AsmString.size();
1100 size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart);
1101 if (DollarEnd == std::string::npos)
1102 DollarEnd = AsmString.size();
1103 OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
1105 size_t NumDollars = DollarEnd - DollarStart;
1106 if (NumDollars % 2 != 0 && Pos < AsmString.size()) {
1107 // We have an operand reference.
1108 size_t DigitStart = Pos;
1109 size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart);
1110 if (DigitEnd == std::string::npos)
1111 DigitEnd = AsmString.size();
1112 StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
1113 unsigned OperandIndex;
1114 if (!OperandStr.getAsInteger(10, OperandIndex)) {
1115 if (OperandIndex >= FirstIn)
1116 OperandIndex += NumNewOuts;
1124 AsmString = std::move(OS.str());
1127 /// Add output constraints for EAX:EDX because they are return registers.
1128 void X86_32TargetCodeGenInfo::addReturnRegisterOutputs(
1129 CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints,
1130 std::vector<llvm::Type *> &ResultRegTypes,
1131 std::vector<llvm::Type *> &ResultTruncRegTypes,
1132 std::vector<LValue> &ResultRegDests, std::string &AsmString,
1133 unsigned NumOutputs) const {
1134 uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType());
1136 // Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is
1138 if (!Constraints.empty())
1140 if (RetWidth <= 32) {
1141 Constraints += "={eax}";
1142 ResultRegTypes.push_back(CGF.Int32Ty);
1144 // Use the 'A' constraint for EAX:EDX.
1145 Constraints += "=A";
1146 ResultRegTypes.push_back(CGF.Int64Ty);
1149 // Truncate EAX or EAX:EDX to an integer of the appropriate size.
1150 llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth);
1151 ResultTruncRegTypes.push_back(CoerceTy);
1153 // Coerce the integer by bitcasting the return slot pointer.
1154 ReturnSlot.setAddress(CGF.Builder.CreateBitCast(ReturnSlot.getAddress(),
1155 CoerceTy->getPointerTo()));
1156 ResultRegDests.push_back(ReturnSlot);
1158 rewriteInputConstraintReferences(NumOutputs, 1, AsmString);
1161 /// shouldReturnTypeInRegister - Determine if the given type should be
1162 /// returned in a register (for the Darwin and MCU ABI).
1163 bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
1164 ASTContext &Context) const {
1165 uint64_t Size = Context.getTypeSize(Ty);
1167 // For i386, type must be register sized.
1168 // For the MCU ABI, it only needs to be <= 8-byte
1169 if ((IsMCUABI && Size > 64) || (!IsMCUABI && !isRegisterSize(Size)))
1172 if (Ty->isVectorType()) {
1173 // 64- and 128- bit vectors inside structures are not returned in
1175 if (Size == 64 || Size == 128)
1181 // If this is a builtin, pointer, enum, complex type, member pointer, or
1182 // member function pointer it is ok.
1183 if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() ||
1184 Ty->isAnyComplexType() || Ty->isEnumeralType() ||
1185 Ty->isBlockPointerType() || Ty->isMemberPointerType())
1188 // Arrays are treated like records.
1189 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty))
1190 return shouldReturnTypeInRegister(AT->getElementType(), Context);
1192 // Otherwise, it must be a record type.
1193 const RecordType *RT = Ty->getAs<RecordType>();
1194 if (!RT) return false;
1196 // FIXME: Traverse bases here too.
1198 // Structure types are passed in register if all fields would be
1199 // passed in a register.
1200 for (const auto *FD : RT->getDecl()->fields()) {
1201 // Empty fields are ignored.
1202 if (isEmptyField(Context, FD, true))
1205 // Check fields recursively.
1206 if (!shouldReturnTypeInRegister(FD->getType(), Context))
1212 static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) {
1213 // Treat complex types as the element type.
1214 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
1215 Ty = CTy->getElementType();
1217 // Check for a type which we know has a simple scalar argument-passing
1218 // convention without any padding. (We're specifically looking for 32
1219 // and 64-bit integer and integer-equivalents, float, and double.)
1220 if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() &&
1221 !Ty->isEnumeralType() && !Ty->isBlockPointerType())
1224 uint64_t Size = Context.getTypeSize(Ty);
1225 return Size == 32 || Size == 64;
1228 static bool addFieldSizes(ASTContext &Context, const RecordDecl *RD,
1230 for (const auto *FD : RD->fields()) {
1231 // Scalar arguments on the stack get 4 byte alignment on x86. If the
1232 // argument is smaller than 32-bits, expanding the struct will create
1233 // alignment padding.
1234 if (!is32Or64BitBasicType(FD->getType(), Context))
1237 // FIXME: Reject bit-fields wholesale; there are two problems, we don't know
1238 // how to expand them yet, and the predicate for telling if a bitfield still
1239 // counts as "basic" is more complicated than what we were doing previously.
1240 if (FD->isBitField())
1243 Size += Context.getTypeSize(FD->getType());
1248 static bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD,
1250 // Don't do this if there are any non-empty bases.
1251 for (const CXXBaseSpecifier &Base : RD->bases()) {
1252 if (!addBaseAndFieldSizes(Context, Base.getType()->getAsCXXRecordDecl(),
1256 if (!addFieldSizes(Context, RD, Size))
1261 /// Test whether an argument type which is to be passed indirectly (on the
1262 /// stack) would have the equivalent layout if it was expanded into separate
1263 /// arguments. If so, we prefer to do the latter to avoid inhibiting
1265 bool X86_32ABIInfo::canExpandIndirectArgument(QualType Ty) const {
1266 // We can only expand structure types.
1267 const RecordType *RT = Ty->getAs<RecordType>();
1270 const RecordDecl *RD = RT->getDecl();
1272 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
1273 if (!IsWin32StructABI) {
1274 // On non-Windows, we have to conservatively match our old bitcode
1275 // prototypes in order to be ABI-compatible at the bitcode level.
1276 if (!CXXRD->isCLike())
1279 // Don't do this for dynamic classes.
1280 if (CXXRD->isDynamicClass())
1283 if (!addBaseAndFieldSizes(getContext(), CXXRD, Size))
1286 if (!addFieldSizes(getContext(), RD, Size))
1290 // We can do this if there was no alignment padding.
1291 return Size == getContext().getTypeSize(Ty);
1294 ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(QualType RetTy, CCState &State) const {
1295 // If the return value is indirect, then the hidden argument is consuming one
1296 // integer register.
1297 if (State.FreeRegs) {
1300 return getNaturalAlignIndirectInReg(RetTy);
1302 return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
1305 ABIArgInfo X86_32ABIInfo::classifyReturnType(QualType RetTy,
1306 CCState &State) const {
1307 if (RetTy->isVoidType())
1308 return ABIArgInfo::getIgnore();
1310 const Type *Base = nullptr;
1311 uint64_t NumElts = 0;
1312 if ((State.CC == llvm::CallingConv::X86_VectorCall ||
1313 State.CC == llvm::CallingConv::X86_RegCall) &&
1314 isHomogeneousAggregate(RetTy, Base, NumElts)) {
1315 // The LLVM struct type for such an aggregate should lower properly.
1316 return ABIArgInfo::getDirect();
1319 if (const VectorType *VT = RetTy->getAs<VectorType>()) {
1320 // On Darwin, some vectors are returned in registers.
1321 if (IsDarwinVectorABI) {
1322 uint64_t Size = getContext().getTypeSize(RetTy);
1324 // 128-bit vectors are a special case; they are returned in
1325 // registers and we need to make sure to pick a type the LLVM
1326 // backend will like.
1328 return ABIArgInfo::getDirect(llvm::VectorType::get(
1329 llvm::Type::getInt64Ty(getVMContext()), 2));
1331 // Always return in register if it fits in a general purpose
1332 // register, or if it is 64 bits and has a single element.
1333 if ((Size == 8 || Size == 16 || Size == 32) ||
1334 (Size == 64 && VT->getNumElements() == 1))
1335 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1338 return getIndirectReturnResult(RetTy, State);
1341 return ABIArgInfo::getDirect();
1344 if (isAggregateTypeForABI(RetTy)) {
1345 if (const RecordType *RT = RetTy->getAs<RecordType>()) {
1346 // Structures with flexible arrays are always indirect.
1347 if (RT->getDecl()->hasFlexibleArrayMember())
1348 return getIndirectReturnResult(RetTy, State);
1351 // If specified, structs and unions are always indirect.
1352 if (!IsRetSmallStructInRegABI && !RetTy->isAnyComplexType())
1353 return getIndirectReturnResult(RetTy, State);
1355 // Ignore empty structs/unions.
1356 if (isEmptyRecord(getContext(), RetTy, true))
1357 return ABIArgInfo::getIgnore();
1359 // Small structures which are register sized are generally returned
1361 if (shouldReturnTypeInRegister(RetTy, getContext())) {
1362 uint64_t Size = getContext().getTypeSize(RetTy);
1364 // As a special-case, if the struct is a "single-element" struct, and
1365 // the field is of type "float" or "double", return it in a
1366 // floating-point register. (MSVC does not apply this special case.)
1367 // We apply a similar transformation for pointer types to improve the
1368 // quality of the generated IR.
1369 if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
1370 if ((!IsWin32StructABI && SeltTy->isRealFloatingType())
1371 || SeltTy->hasPointerRepresentation())
1372 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
1374 // FIXME: We should be able to narrow this integer in cases with dead
1376 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size));
1379 return getIndirectReturnResult(RetTy, State);
1382 // Treat an enum type as its underlying type.
1383 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
1384 RetTy = EnumTy->getDecl()->getIntegerType();
1386 return (RetTy->isPromotableIntegerType() ?
1387 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
1390 static bool isSSEVectorType(ASTContext &Context, QualType Ty) {
1391 return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128;
1394 static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) {
1395 const RecordType *RT = Ty->getAs<RecordType>();
1398 const RecordDecl *RD = RT->getDecl();
1400 // If this is a C++ record, check the bases first.
1401 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
1402 for (const auto &I : CXXRD->bases())
1403 if (!isRecordWithSSEVectorType(Context, I.getType()))
1406 for (const auto *i : RD->fields()) {
1407 QualType FT = i->getType();
1409 if (isSSEVectorType(Context, FT))
1412 if (isRecordWithSSEVectorType(Context, FT))
1419 unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty,
1420 unsigned Align) const {
1421 // Otherwise, if the alignment is less than or equal to the minimum ABI
1422 // alignment, just use the default; the backend will handle this.
1423 if (Align <= MinABIStackAlignInBytes)
1424 return 0; // Use default alignment.
1426 // On non-Darwin, the stack type alignment is always 4.
1427 if (!IsDarwinVectorABI) {
1428 // Set explicit alignment, since we may need to realign the top.
1429 return MinABIStackAlignInBytes;
1432 // Otherwise, if the type contains an SSE vector type, the alignment is 16.
1433 if (Align >= 16 && (isSSEVectorType(getContext(), Ty) ||
1434 isRecordWithSSEVectorType(getContext(), Ty)))
1437 return MinABIStackAlignInBytes;
1440 ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal,
1441 CCState &State) const {
1443 if (State.FreeRegs) {
1444 --State.FreeRegs; // Non-byval indirects just use one pointer.
1446 return getNaturalAlignIndirectInReg(Ty);
1448 return getNaturalAlignIndirect(Ty, false);
1451 // Compute the byval alignment.
1452 unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
1453 unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign);
1454 if (StackAlign == 0)
1455 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true);
1457 // If the stack alignment is less than the type alignment, realign the
1459 bool Realign = TypeAlign > StackAlign;
1460 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(StackAlign),
1461 /*ByVal=*/true, Realign);
1464 X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const {
1465 const Type *T = isSingleElementStruct(Ty, getContext());
1467 T = Ty.getTypePtr();
1469 if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
1470 BuiltinType::Kind K = BT->getKind();
1471 if (K == BuiltinType::Float || K == BuiltinType::Double)
1477 bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const {
1478 if (!IsSoftFloatABI) {
1479 Class C = classify(Ty);
1484 unsigned Size = getContext().getTypeSize(Ty);
1485 unsigned SizeInRegs = (Size + 31) / 32;
1487 if (SizeInRegs == 0)
1491 if (SizeInRegs > State.FreeRegs) {
1496 // The MCU psABI allows passing parameters in-reg even if there are
1497 // earlier parameters that are passed on the stack. Also,
1498 // it does not allow passing >8-byte structs in-register,
1499 // even if there are 3 free registers available.
1500 if (SizeInRegs > State.FreeRegs || SizeInRegs > 2)
1504 State.FreeRegs -= SizeInRegs;
1508 bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State,
1510 bool &NeedsPadding) const {
1511 // On Windows, aggregates other than HFAs are never passed in registers, and
1512 // they do not consume register slots. Homogenous floating-point aggregates
1513 // (HFAs) have already been dealt with at this point.
1514 if (IsWin32StructABI && isAggregateTypeForABI(Ty))
1517 NeedsPadding = false;
1520 if (!updateFreeRegs(Ty, State))
1526 if (State.CC == llvm::CallingConv::X86_FastCall ||
1527 State.CC == llvm::CallingConv::X86_VectorCall ||
1528 State.CC == llvm::CallingConv::X86_RegCall) {
1529 if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs)
1530 NeedsPadding = true;
1538 bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const {
1539 if (!updateFreeRegs(Ty, State))
1545 if (State.CC == llvm::CallingConv::X86_FastCall ||
1546 State.CC == llvm::CallingConv::X86_VectorCall ||
1547 State.CC == llvm::CallingConv::X86_RegCall) {
1548 if (getContext().getTypeSize(Ty) > 32)
1551 return (Ty->isIntegralOrEnumerationType() || Ty->isPointerType() ||
1552 Ty->isReferenceType());
1558 ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
1559 CCState &State) const {
1560 // FIXME: Set alignment on indirect arguments.
1562 Ty = useFirstFieldIfTransparentUnion(Ty);
1564 // Check with the C++ ABI first.
1565 const RecordType *RT = Ty->getAs<RecordType>();
1567 CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
1568 if (RAA == CGCXXABI::RAA_Indirect) {
1569 return getIndirectResult(Ty, false, State);
1570 } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
1571 // The field index doesn't matter, we'll fix it up later.
1572 return ABIArgInfo::getInAlloca(/*FieldIndex=*/0);
1576 // Regcall uses the concept of a homogenous vector aggregate, similar
1577 // to other targets.
1578 const Type *Base = nullptr;
1579 uint64_t NumElts = 0;
1580 if (State.CC == llvm::CallingConv::X86_RegCall &&
1581 isHomogeneousAggregate(Ty, Base, NumElts)) {
1583 if (State.FreeSSERegs >= NumElts) {
1584 State.FreeSSERegs -= NumElts;
1585 if (Ty->isBuiltinType() || Ty->isVectorType())
1586 return ABIArgInfo::getDirect();
1587 return ABIArgInfo::getExpand();
1589 return getIndirectResult(Ty, /*ByVal=*/false, State);
1592 if (isAggregateTypeForABI(Ty)) {
1593 // Structures with flexible arrays are always indirect.
1594 // FIXME: This should not be byval!
1595 if (RT && RT->getDecl()->hasFlexibleArrayMember())
1596 return getIndirectResult(Ty, true, State);
1598 // Ignore empty structs/unions on non-Windows.
1599 if (!IsWin32StructABI && isEmptyRecord(getContext(), Ty, true))
1600 return ABIArgInfo::getIgnore();
1602 llvm::LLVMContext &LLVMContext = getVMContext();
1603 llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
1604 bool NeedsPadding = false;
1606 if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
1607 unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
1608 SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
1609 llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
1611 return ABIArgInfo::getDirectInReg(Result);
1613 return ABIArgInfo::getDirect(Result);
1615 llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr;
1617 // Expand small (<= 128-bit) record types when we know that the stack layout
1618 // of those arguments will match the struct. This is important because the
1619 // LLVM backend isn't smart enough to remove byval, which inhibits many
1621 // Don't do this for the MCU if there are still free integer registers
1622 // (see X86_64 ABI for full explanation).
1623 if (getContext().getTypeSize(Ty) <= 4 * 32 &&
1624 (!IsMCUABI || State.FreeRegs == 0) && canExpandIndirectArgument(Ty))
1625 return ABIArgInfo::getExpandWithPadding(
1626 State.CC == llvm::CallingConv::X86_FastCall ||
1627 State.CC == llvm::CallingConv::X86_VectorCall ||
1628 State.CC == llvm::CallingConv::X86_RegCall,
1631 return getIndirectResult(Ty, true, State);
1634 if (const VectorType *VT = Ty->getAs<VectorType>()) {
1635 // On Darwin, some vectors are passed in memory, we handle this by passing
1636 // it as an i8/i16/i32/i64.
1637 if (IsDarwinVectorABI) {
1638 uint64_t Size = getContext().getTypeSize(Ty);
1639 if ((Size == 8 || Size == 16 || Size == 32) ||
1640 (Size == 64 && VT->getNumElements() == 1))
1641 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1645 if (IsX86_MMXType(CGT.ConvertType(Ty)))
1646 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
1648 return ABIArgInfo::getDirect();
1652 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
1653 Ty = EnumTy->getDecl()->getIntegerType();
1655 bool InReg = shouldPrimitiveUseInReg(Ty, State);
1657 if (Ty->isPromotableIntegerType()) {
1659 return ABIArgInfo::getExtendInReg();
1660 return ABIArgInfo::getExtend();
1664 return ABIArgInfo::getDirectInReg();
1665 return ABIArgInfo::getDirect();
1668 void X86_32ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
1669 bool &UsedInAlloca) const {
1670 // Vectorcall x86 works subtly different than in x64, so the format is
1671 // a bit different than the x64 version. First, all vector types (not HVAs)
1672 // are assigned, with the first 6 ending up in the YMM0-5 or XMM0-5 registers.
1673 // This differs from the x64 implementation, where the first 6 by INDEX get
1675 // After that, integers AND HVAs are assigned Left to Right in the same pass.
1676 // Integers are passed as ECX/EDX if one is available (in order). HVAs will
1677 // first take up the remaining YMM/XMM registers. If insufficient registers
1678 // remain but an integer register (ECX/EDX) is available, it will be passed
1679 // in that, else, on the stack.
1680 for (auto &I : FI.arguments()) {
1681 // First pass do all the vector types.
1682 const Type *Base = nullptr;
1683 uint64_t NumElts = 0;
1684 const QualType& Ty = I.type;
1685 if ((Ty->isVectorType() || Ty->isBuiltinType()) &&
1686 isHomogeneousAggregate(Ty, Base, NumElts)) {
1687 if (State.FreeSSERegs >= NumElts) {
1688 State.FreeSSERegs -= NumElts;
1689 I.info = ABIArgInfo::getDirect();
1691 I.info = classifyArgumentType(Ty, State);
1693 UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1697 for (auto &I : FI.arguments()) {
1698 // Second pass, do the rest!
1699 const Type *Base = nullptr;
1700 uint64_t NumElts = 0;
1701 const QualType& Ty = I.type;
1702 bool IsHva = isHomogeneousAggregate(Ty, Base, NumElts);
1704 if (IsHva && !Ty->isVectorType() && !Ty->isBuiltinType()) {
1705 // Assign true HVAs (non vector/native FP types).
1706 if (State.FreeSSERegs >= NumElts) {
1707 State.FreeSSERegs -= NumElts;
1708 I.info = getDirectX86Hva();
1710 I.info = getIndirectResult(Ty, /*ByVal=*/false, State);
1712 } else if (!IsHva) {
1713 // Assign all Non-HVAs, so this will exclude Vector/FP args.
1714 I.info = classifyArgumentType(Ty, State);
1715 UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1720 void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
1721 CCState State(FI.getCallingConvention());
1724 else if (State.CC == llvm::CallingConv::X86_FastCall)
1726 else if (State.CC == llvm::CallingConv::X86_VectorCall) {
1728 State.FreeSSERegs = 6;
1729 } else if (FI.getHasRegParm())
1730 State.FreeRegs = FI.getRegParm();
1731 else if (State.CC == llvm::CallingConv::X86_RegCall) {
1733 State.FreeSSERegs = 8;
1735 State.FreeRegs = DefaultNumRegisterParameters;
1737 if (!getCXXABI().classifyReturnType(FI)) {
1738 FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), State);
1739 } else if (FI.getReturnInfo().isIndirect()) {
1740 // The C++ ABI is not aware of register usage, so we have to check if the
1741 // return value was sret and put it in a register ourselves if appropriate.
1742 if (State.FreeRegs) {
1743 --State.FreeRegs; // The sret parameter consumes a register.
1745 FI.getReturnInfo().setInReg(true);
1749 // The chain argument effectively gives us another free register.
1750 if (FI.isChainCall())
1753 bool UsedInAlloca = false;
1754 if (State.CC == llvm::CallingConv::X86_VectorCall) {
1755 computeVectorCallArgs(FI, State, UsedInAlloca);
1757 // If not vectorcall, revert to normal behavior.
1758 for (auto &I : FI.arguments()) {
1759 I.info = classifyArgumentType(I.type, State);
1760 UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1764 // If we needed to use inalloca for any argument, do a second pass and rewrite
1765 // all the memory arguments to use inalloca.
1767 rewriteWithInAlloca(FI);
1771 X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1772 CharUnits &StackOffset, ABIArgInfo &Info,
1773 QualType Type) const {
1774 // Arguments are always 4-byte-aligned.
1775 CharUnits FieldAlign = CharUnits::fromQuantity(4);
1777 assert(StackOffset.isMultipleOf(FieldAlign) && "unaligned inalloca struct");
1778 Info = ABIArgInfo::getInAlloca(FrameFields.size());
1779 FrameFields.push_back(CGT.ConvertTypeForMem(Type));
1780 StackOffset += getContext().getTypeSizeInChars(Type);
1782 // Insert padding bytes to respect alignment.
1783 CharUnits FieldEnd = StackOffset;
1784 StackOffset = FieldEnd.alignTo(FieldAlign);
1785 if (StackOffset != FieldEnd) {
1786 CharUnits NumBytes = StackOffset - FieldEnd;
1787 llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
1788 Ty = llvm::ArrayType::get(Ty, NumBytes.getQuantity());
1789 FrameFields.push_back(Ty);
1793 static bool isArgInAlloca(const ABIArgInfo &Info) {
1794 // Leave ignored and inreg arguments alone.
1795 switch (Info.getKind()) {
1796 case ABIArgInfo::InAlloca:
1798 case ABIArgInfo::Indirect:
1799 assert(Info.getIndirectByVal());
1801 case ABIArgInfo::Ignore:
1803 case ABIArgInfo::Direct:
1804 case ABIArgInfo::Extend:
1805 if (Info.getInReg())
1808 case ABIArgInfo::Expand:
1809 case ABIArgInfo::CoerceAndExpand:
1810 // These are aggregate types which are never passed in registers when
1811 // inalloca is involved.
1814 llvm_unreachable("invalid enum");
1817 void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
1818 assert(IsWin32StructABI && "inalloca only supported on win32");
1820 // Build a packed struct type for all of the arguments in memory.
1821 SmallVector<llvm::Type *, 6> FrameFields;
1823 // The stack alignment is always 4.
1824 CharUnits StackAlign = CharUnits::fromQuantity(4);
1826 CharUnits StackOffset;
1827 CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end();
1829 // Put 'this' into the struct before 'sret', if necessary.
1831 FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
1832 ABIArgInfo &Ret = FI.getReturnInfo();
1833 if (Ret.isIndirect() && Ret.isSRetAfterThis() && !IsThisCall &&
1834 isArgInAlloca(I->info)) {
1835 addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1839 // Put the sret parameter into the inalloca struct if it's in memory.
1840 if (Ret.isIndirect() && !Ret.getInReg()) {
1841 CanQualType PtrTy = getContext().getPointerType(FI.getReturnType());
1842 addFieldToArgStruct(FrameFields, StackOffset, Ret, PtrTy);
1843 // On Windows, the hidden sret parameter is always returned in eax.
1844 Ret.setInAllocaSRet(IsWin32StructABI);
1847 // Skip the 'this' parameter in ecx.
1851 // Put arguments passed in memory into the struct.
1852 for (; I != E; ++I) {
1853 if (isArgInAlloca(I->info))
1854 addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1857 FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
1862 Address X86_32ABIInfo::EmitVAArg(CodeGenFunction &CGF,
1863 Address VAListAddr, QualType Ty) const {
1865 auto TypeInfo = getContext().getTypeInfoInChars(Ty);
1867 // x86-32 changes the alignment of certain arguments on the stack.
1869 // Just messing with TypeInfo like this works because we never pass
1870 // anything indirectly.
1871 TypeInfo.second = CharUnits::fromQuantity(
1872 getTypeStackAlignInBytes(Ty, TypeInfo.second.getQuantity()));
1874 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
1875 TypeInfo, CharUnits::fromQuantity(4),
1876 /*AllowHigherAlign*/ true);
1879 bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
1880 const llvm::Triple &Triple, const CodeGenOptions &Opts) {
1881 assert(Triple.getArch() == llvm::Triple::x86);
1883 switch (Opts.getStructReturnConvention()) {
1884 case CodeGenOptions::SRCK_Default:
1886 case CodeGenOptions::SRCK_OnStack: // -fpcc-struct-return
1888 case CodeGenOptions::SRCK_InRegs: // -freg-struct-return
1892 if (Triple.isOSDarwin() || Triple.isOSIAMCU())
1895 switch (Triple.getOS()) {
1896 case llvm::Triple::DragonFly:
1897 case llvm::Triple::FreeBSD:
1898 case llvm::Triple::OpenBSD:
1899 case llvm::Triple::Bitrig:
1900 case llvm::Triple::Win32:
1907 void X86_32TargetCodeGenInfo::setTargetAttributes(const Decl *D,
1908 llvm::GlobalValue *GV,
1909 CodeGen::CodeGenModule &CGM) const {
1910 if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
1911 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1912 // Get the LLVM function.
1913 llvm::Function *Fn = cast<llvm::Function>(GV);
1915 // Now add the 'alignstack' attribute with a value of 16.
1916 llvm::AttrBuilder B;
1917 B.addStackAlignmentAttr(16);
1918 Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
1920 if (FD->hasAttr<AnyX86InterruptAttr>()) {
1921 llvm::Function *Fn = cast<llvm::Function>(GV);
1922 Fn->setCallingConv(llvm::CallingConv::X86_INTR);
1927 bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
1928 CodeGen::CodeGenFunction &CGF,
1929 llvm::Value *Address) const {
1930 CodeGen::CGBuilderTy &Builder = CGF.Builder;
1932 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
1934 // 0-7 are the eight integer registers; the order is different
1935 // on Darwin (for EH), but the range is the same.
1937 AssignToArrayRange(Builder, Address, Four8, 0, 8);
1939 if (CGF.CGM.getTarget().getTriple().isOSDarwin()) {
1940 // 12-16 are st(0..4). Not sure why we stop at 4.
1941 // These have size 16, which is sizeof(long double) on
1942 // platforms with 8-byte alignment for that type.
1943 llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
1944 AssignToArrayRange(Builder, Address, Sixteen8, 12, 16);
1947 // 9 is %eflags, which doesn't get a size on Darwin for some
1949 Builder.CreateAlignedStore(
1950 Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9),
1953 // 11-16 are st(0..5). Not sure why we stop at 5.
1954 // These have size 12, which is sizeof(long double) on
1955 // platforms with 4-byte alignment for that type.
1956 llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12);
1957 AssignToArrayRange(Builder, Address, Twelve8, 11, 16);
1963 //===----------------------------------------------------------------------===//
1964 // X86-64 ABI Implementation
1965 //===----------------------------------------------------------------------===//
1969 /// The AVX ABI level for X86 targets.
1970 enum class X86AVXABILevel {
1976 /// \p returns the size in bits of the largest (native) vector for \p AVXLevel.
1977 static unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) {
1979 case X86AVXABILevel::AVX512:
1981 case X86AVXABILevel::AVX:
1983 case X86AVXABILevel::None:
1986 llvm_unreachable("Unknown AVXLevel");
1989 /// X86_64ABIInfo - The X86_64 ABI information.
1990 class X86_64ABIInfo : public SwiftABIInfo {
2002 /// merge - Implement the X86_64 ABI merging algorithm.
2004 /// Merge an accumulating classification \arg Accum with a field
2005 /// classification \arg Field.
2007 /// \param Accum - The accumulating classification. This should
2008 /// always be either NoClass or the result of a previous merge
2009 /// call. In addition, this should never be Memory (the caller
2010 /// should just return Memory for the aggregate).
2011 static Class merge(Class Accum, Class Field);
2013 /// postMerge - Implement the X86_64 ABI post merging algorithm.
2015 /// Post merger cleanup, reduces a malformed Hi and Lo pair to
2016 /// final MEMORY or SSE classes when necessary.
2018 /// \param AggregateSize - The size of the current aggregate in
2019 /// the classification process.
2021 /// \param Lo - The classification for the parts of the type
2022 /// residing in the low word of the containing object.
2024 /// \param Hi - The classification for the parts of the type
2025 /// residing in the higher words of the containing object.
2027 void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
2029 /// classify - Determine the x86_64 register classes in which the
2030 /// given type T should be passed.
2032 /// \param Lo - The classification for the parts of the type
2033 /// residing in the low word of the containing object.
2035 /// \param Hi - The classification for the parts of the type
2036 /// residing in the high word of the containing object.
2038 /// \param OffsetBase - The bit offset of this type in the
2039 /// containing object. Some parameters are classified different
2040 /// depending on whether they straddle an eightbyte boundary.
2042 /// \param isNamedArg - Whether the argument in question is a "named"
2043 /// argument, as used in AMD64-ABI 3.5.7.
2045 /// If a word is unused its result will be NoClass; if a type should
2046 /// be passed in Memory then at least the classification of \arg Lo
2049 /// The \arg Lo class will be NoClass iff the argument is ignored.
2051 /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
2052 /// also be ComplexX87.
2053 void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
2054 bool isNamedArg) const;
2056 llvm::Type *GetByteVectorType(QualType Ty) const;
2057 llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType,
2058 unsigned IROffset, QualType SourceTy,
2059 unsigned SourceOffset) const;
2060 llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType,
2061 unsigned IROffset, QualType SourceTy,
2062 unsigned SourceOffset) const;
2064 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2065 /// such that the argument will be returned in memory.
2066 ABIArgInfo getIndirectReturnResult(QualType Ty) const;
2068 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2069 /// such that the argument will be passed in memory.
2071 /// \param freeIntRegs - The number of free integer registers remaining
2073 ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const;
2075 ABIArgInfo classifyReturnType(QualType RetTy) const;
2077 ABIArgInfo classifyArgumentType(QualType Ty, unsigned freeIntRegs,
2078 unsigned &neededInt, unsigned &neededSSE,
2079 bool isNamedArg) const;
2081 ABIArgInfo classifyRegCallStructType(QualType Ty, unsigned &NeededInt,
2082 unsigned &NeededSSE) const;
2084 ABIArgInfo classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
2085 unsigned &NeededSSE) const;
2087 bool IsIllegalVectorType(QualType Ty) const;
2089 /// The 0.98 ABI revision clarified a lot of ambiguities,
2090 /// unfortunately in ways that were not always consistent with
2091 /// certain previous compilers. In particular, platforms which
2092 /// required strict binary compatibility with older versions of GCC
2093 /// may need to exempt themselves.
2094 bool honorsRevision0_98() const {
2095 return !getTarget().getTriple().isOSDarwin();
2098 /// GCC classifies <1 x long long> as SSE but compatibility with older clang
2099 // compilers require us to classify it as INTEGER.
2100 bool classifyIntegerMMXAsSSE() const {
2101 const llvm::Triple &Triple = getTarget().getTriple();
2102 if (Triple.isOSDarwin() || Triple.getOS() == llvm::Triple::PS4)
2104 if (Triple.isOSFreeBSD() && Triple.getOSMajorVersion() >= 10)
2109 X86AVXABILevel AVXLevel;
2110 // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on
2112 bool Has64BitPointers;
2115 X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) :
2116 SwiftABIInfo(CGT), AVXLevel(AVXLevel),
2117 Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) {
2120 bool isPassedUsingAVXType(QualType type) const {
2121 unsigned neededInt, neededSSE;
2122 // The freeIntRegs argument doesn't matter here.
2123 ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE,
2124 /*isNamedArg*/true);
2125 if (info.isDirect()) {
2126 llvm::Type *ty = info.getCoerceToType();
2127 if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty))
2128 return (vectorTy->getBitWidth() > 128);
2133 void computeInfo(CGFunctionInfo &FI) const override;
2135 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2136 QualType Ty) const override;
2137 Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
2138 QualType Ty) const override;
2140 bool has64BitPointers() const {
2141 return Has64BitPointers;
2144 bool shouldPassIndirectlyForSwift(CharUnits totalSize,
2145 ArrayRef<llvm::Type*> scalars,
2146 bool asReturnValue) const override {
2147 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2149 bool isSwiftErrorInRegister() const override {
2154 /// WinX86_64ABIInfo - The Windows X86_64 ABI information.
2155 class WinX86_64ABIInfo : public SwiftABIInfo {
2157 WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT)
2158 : SwiftABIInfo(CGT),
2159 IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {}
2161 void computeInfo(CGFunctionInfo &FI) const override;
2163 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2164 QualType Ty) const override;
2166 bool isHomogeneousAggregateBaseType(QualType Ty) const override {
2167 // FIXME: Assumes vectorcall is in use.
2168 return isX86VectorTypeForVectorCall(getContext(), Ty);
2171 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
2172 uint64_t NumMembers) const override {
2173 // FIXME: Assumes vectorcall is in use.
2174 return isX86VectorCallAggregateSmallEnough(NumMembers);
2177 bool shouldPassIndirectlyForSwift(CharUnits totalSize,
2178 ArrayRef<llvm::Type *> scalars,
2179 bool asReturnValue) const override {
2180 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2183 bool isSwiftErrorInRegister() const override {
2188 ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs, bool IsReturnType,
2189 bool IsVectorCall, bool IsRegCall) const;
2190 ABIArgInfo reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
2191 const ABIArgInfo ¤t) const;
2192 void computeVectorCallArgs(CGFunctionInfo &FI, unsigned FreeSSERegs,
2193 bool IsVectorCall, bool IsRegCall) const;
2198 class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2200 X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2201 : TargetCodeGenInfo(new X86_64ABIInfo(CGT, AVXLevel)) {}
2203 const X86_64ABIInfo &getABIInfo() const {
2204 return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo());
2207 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2211 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2212 llvm::Value *Address) const override {
2213 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2215 // 0-15 are the 16 integer registers.
2217 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2221 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
2222 StringRef Constraint,
2223 llvm::Type* Ty) const override {
2224 return X86AdjustInlineAsmType(CGF, Constraint, Ty);
2227 bool isNoProtoCallVariadic(const CallArgList &args,
2228 const FunctionNoProtoType *fnType) const override {
2229 // The default CC on x86-64 sets %al to the number of SSA
2230 // registers used, and GCC sets this when calling an unprototyped
2231 // function, so we override the default behavior. However, don't do
2232 // that when AVX types are involved: the ABI explicitly states it is
2233 // undefined, and it doesn't work in practice because of how the ABI
2234 // defines varargs anyway.
2235 if (fnType->getCallConv() == CC_C) {
2236 bool HasAVXType = false;
2237 for (CallArgList::const_iterator
2238 it = args.begin(), ie = args.end(); it != ie; ++it) {
2239 if (getABIInfo().isPassedUsingAVXType(it->Ty)) {
2249 return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType);
2253 getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
2255 if (getABIInfo().has64BitPointers())
2256 Sig = (0xeb << 0) | // jmp rel8
2257 (0x0a << 8) | // .+0x0c
2261 Sig = (0xeb << 0) | // jmp rel8
2262 (0x06 << 8) | // .+0x08
2265 return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
2268 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2269 CodeGen::CodeGenModule &CGM) const override {
2270 if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2271 if (FD->hasAttr<AnyX86InterruptAttr>()) {
2272 llvm::Function *Fn = cast<llvm::Function>(GV);
2273 Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2279 class PS4TargetCodeGenInfo : public X86_64TargetCodeGenInfo {
2281 PS4TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2282 : X86_64TargetCodeGenInfo(CGT, AVXLevel) {}
2284 void getDependentLibraryOption(llvm::StringRef Lib,
2285 llvm::SmallString<24> &Opt) const override {
2287 // If the argument contains a space, enclose it in quotes.
2288 if (Lib.find(" ") != StringRef::npos)
2289 Opt += "\"" + Lib.str() + "\"";
2295 static std::string qualifyWindowsLibrary(llvm::StringRef Lib) {
2296 // If the argument does not end in .lib, automatically add the suffix.
2297 // If the argument contains a space, enclose it in quotes.
2298 // This matches the behavior of MSVC.
2299 bool Quote = (Lib.find(" ") != StringRef::npos);
2300 std::string ArgStr = Quote ? "\"" : "";
2302 if (!Lib.endswith_lower(".lib"))
2304 ArgStr += Quote ? "\"" : "";
2308 class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
2310 WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2311 bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
2312 unsigned NumRegisterParameters)
2313 : X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
2314 Win32StructABI, NumRegisterParameters, false) {}
2316 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2317 CodeGen::CodeGenModule &CGM) const override;
2319 void getDependentLibraryOption(llvm::StringRef Lib,
2320 llvm::SmallString<24> &Opt) const override {
2321 Opt = "/DEFAULTLIB:";
2322 Opt += qualifyWindowsLibrary(Lib);
2325 void getDetectMismatchOption(llvm::StringRef Name,
2326 llvm::StringRef Value,
2327 llvm::SmallString<32> &Opt) const override {
2328 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2332 static void addStackProbeSizeTargetAttribute(const Decl *D,
2333 llvm::GlobalValue *GV,
2334 CodeGen::CodeGenModule &CGM) {
2335 if (D && isa<FunctionDecl>(D)) {
2336 if (CGM.getCodeGenOpts().StackProbeSize != 4096) {
2337 llvm::Function *Fn = cast<llvm::Function>(GV);
2339 Fn->addFnAttr("stack-probe-size",
2340 llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
2345 void WinX86_32TargetCodeGenInfo::setTargetAttributes(const Decl *D,
2346 llvm::GlobalValue *GV,
2347 CodeGen::CodeGenModule &CGM) const {
2348 X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2350 addStackProbeSizeTargetAttribute(D, GV, CGM);
2353 class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2355 WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2356 X86AVXABILevel AVXLevel)
2357 : TargetCodeGenInfo(new WinX86_64ABIInfo(CGT)) {}
2359 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2360 CodeGen::CodeGenModule &CGM) const override;
2362 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2366 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2367 llvm::Value *Address) const override {
2368 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2370 // 0-15 are the 16 integer registers.
2372 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2376 void getDependentLibraryOption(llvm::StringRef Lib,
2377 llvm::SmallString<24> &Opt) const override {
2378 Opt = "/DEFAULTLIB:";
2379 Opt += qualifyWindowsLibrary(Lib);
2382 void getDetectMismatchOption(llvm::StringRef Name,
2383 llvm::StringRef Value,
2384 llvm::SmallString<32> &Opt) const override {
2385 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2389 void WinX86_64TargetCodeGenInfo::setTargetAttributes(const Decl *D,
2390 llvm::GlobalValue *GV,
2391 CodeGen::CodeGenModule &CGM) const {
2392 TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2394 if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2395 if (FD->hasAttr<AnyX86InterruptAttr>()) {
2396 llvm::Function *Fn = cast<llvm::Function>(GV);
2397 Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2401 addStackProbeSizeTargetAttribute(D, GV, CGM);
2405 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
2407 // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
2409 // (a) If one of the classes is Memory, the whole argument is passed in
2412 // (b) If X87UP is not preceded by X87, the whole argument is passed in
2415 // (c) If the size of the aggregate exceeds two eightbytes and the first
2416 // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
2417 // argument is passed in memory. NOTE: This is necessary to keep the
2418 // ABI working for processors that don't support the __m256 type.
2420 // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
2422 // Some of these are enforced by the merging logic. Others can arise
2423 // only with unions; for example:
2424 // union { _Complex double; unsigned; }
2426 // Note that clauses (b) and (c) were added in 0.98.
2430 if (Hi == X87Up && Lo != X87 && honorsRevision0_98())
2432 if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp))
2434 if (Hi == SSEUp && Lo != SSE)
2438 X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) {
2439 // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
2440 // classified recursively so that always two fields are
2441 // considered. The resulting class is calculated according to
2442 // the classes of the fields in the eightbyte:
2444 // (a) If both classes are equal, this is the resulting class.
2446 // (b) If one of the classes is NO_CLASS, the resulting class is
2449 // (c) If one of the classes is MEMORY, the result is the MEMORY
2452 // (d) If one of the classes is INTEGER, the result is the
2455 // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class,
2456 // MEMORY is used as class.
2458 // (f) Otherwise class SSE is used.
2460 // Accum should never be memory (we should have returned) or
2461 // ComplexX87 (because this cannot be passed in a structure).
2462 assert((Accum != Memory && Accum != ComplexX87) &&
2463 "Invalid accumulated classification during merge.");
2464 if (Accum == Field || Field == NoClass)
2466 if (Field == Memory)
2468 if (Accum == NoClass)
2470 if (Accum == Integer || Field == Integer)
2472 if (Field == X87 || Field == X87Up || Field == ComplexX87 ||
2473 Accum == X87 || Accum == X87Up)
2478 void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase,
2479 Class &Lo, Class &Hi, bool isNamedArg) const {
2480 // FIXME: This code can be simplified by introducing a simple value class for
2481 // Class pairs with appropriate constructor methods for the various
2484 // FIXME: Some of the split computations are wrong; unaligned vectors
2485 // shouldn't be passed in registers for example, so there is no chance they
2486 // can straddle an eightbyte. Verify & simplify.
2490 Class &Current = OffsetBase < 64 ? Lo : Hi;
2493 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
2494 BuiltinType::Kind k = BT->getKind();
2496 if (k == BuiltinType::Void) {
2498 } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) {
2501 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
2503 } else if (k == BuiltinType::Float || k == BuiltinType::Double) {
2505 } else if (k == BuiltinType::LongDouble) {
2506 const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2507 if (LDF == &llvm::APFloat::IEEEquad()) {
2510 } else if (LDF == &llvm::APFloat::x87DoubleExtended()) {
2513 } else if (LDF == &llvm::APFloat::IEEEdouble()) {
2516 llvm_unreachable("unexpected long double representation!");
2518 // FIXME: _Decimal32 and _Decimal64 are SSE.
2519 // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
2523 if (const EnumType *ET = Ty->getAs<EnumType>()) {
2524 // Classify the underlying integer type.
2525 classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
2529 if (Ty->hasPointerRepresentation()) {
2534 if (Ty->isMemberPointerType()) {
2535 if (Ty->isMemberFunctionPointerType()) {
2536 if (Has64BitPointers) {
2537 // If Has64BitPointers, this is an {i64, i64}, so classify both
2541 // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
2542 // straddles an eightbyte boundary, Hi should be classified as well.
2543 uint64_t EB_FuncPtr = (OffsetBase) / 64;
2544 uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
2545 if (EB_FuncPtr != EB_ThisAdj) {
2557 if (const VectorType *VT = Ty->getAs<VectorType>()) {
2558 uint64_t Size = getContext().getTypeSize(VT);
2559 if (Size == 1 || Size == 8 || Size == 16 || Size == 32) {
2560 // gcc passes the following as integer:
2561 // 4 bytes - <4 x char>, <2 x short>, <1 x int>, <1 x float>
2562 // 2 bytes - <2 x char>, <1 x short>
2563 // 1 byte - <1 x char>
2566 // If this type crosses an eightbyte boundary, it should be
2568 uint64_t EB_Lo = (OffsetBase) / 64;
2569 uint64_t EB_Hi = (OffsetBase + Size - 1) / 64;
2572 } else if (Size == 64) {
2573 QualType ElementType = VT->getElementType();
2575 // gcc passes <1 x double> in memory. :(
2576 if (ElementType->isSpecificBuiltinType(BuiltinType::Double))
2579 // gcc passes <1 x long long> as SSE but clang used to unconditionally
2580 // pass them as integer. For platforms where clang is the de facto
2581 // platform compiler, we must continue to use integer.
2582 if (!classifyIntegerMMXAsSSE() &&
2583 (ElementType->isSpecificBuiltinType(BuiltinType::LongLong) ||
2584 ElementType->isSpecificBuiltinType(BuiltinType::ULongLong) ||
2585 ElementType->isSpecificBuiltinType(BuiltinType::Long) ||
2586 ElementType->isSpecificBuiltinType(BuiltinType::ULong)))
2591 // If this type crosses an eightbyte boundary, it should be
2593 if (OffsetBase && OffsetBase != 64)
2595 } else if (Size == 128 ||
2596 (isNamedArg && Size <= getNativeVectorSizeForAVXABI(AVXLevel))) {
2597 // Arguments of 256-bits are split into four eightbyte chunks. The
2598 // least significant one belongs to class SSE and all the others to class
2599 // SSEUP. The original Lo and Hi design considers that types can't be
2600 // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
2601 // This design isn't correct for 256-bits, but since there're no cases
2602 // where the upper parts would need to be inspected, avoid adding
2603 // complexity and just consider Hi to match the 64-256 part.
2605 // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
2606 // registers if they are "named", i.e. not part of the "..." of a
2607 // variadic function.
2609 // Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are
2610 // split into eight eightbyte chunks, one SSE and seven SSEUP.
2617 if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
2618 QualType ET = getContext().getCanonicalType(CT->getElementType());
2620 uint64_t Size = getContext().getTypeSize(Ty);
2621 if (ET->isIntegralOrEnumerationType()) {
2624 else if (Size <= 128)
2626 } else if (ET == getContext().FloatTy) {
2628 } else if (ET == getContext().DoubleTy) {
2630 } else if (ET == getContext().LongDoubleTy) {
2631 const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2632 if (LDF == &llvm::APFloat::IEEEquad())
2634 else if (LDF == &llvm::APFloat::x87DoubleExtended())
2635 Current = ComplexX87;
2636 else if (LDF == &llvm::APFloat::IEEEdouble())
2639 llvm_unreachable("unexpected long double representation!");
2642 // If this complex type crosses an eightbyte boundary then it
2644 uint64_t EB_Real = (OffsetBase) / 64;
2645 uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64;
2646 if (Hi == NoClass && EB_Real != EB_Imag)
2652 if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
2653 // Arrays are treated like structures.
2655 uint64_t Size = getContext().getTypeSize(Ty);
2657 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2658 // than eight eightbytes, ..., it has class MEMORY.
2662 // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
2663 // fields, it has class MEMORY.
2665 // Only need to check alignment of array base.
2666 if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
2669 // Otherwise implement simplified merge. We could be smarter about
2670 // this, but it isn't worth it and would be harder to verify.
2672 uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
2673 uint64_t ArraySize = AT->getSize().getZExtValue();
2675 // The only case a 256-bit wide vector could be used is when the array
2676 // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2677 // to work for sizes wider than 128, early check and fallback to memory.
2680 (Size != EltSize || Size > getNativeVectorSizeForAVXABI(AVXLevel)))
2683 for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) {
2684 Class FieldLo, FieldHi;
2685 classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
2686 Lo = merge(Lo, FieldLo);
2687 Hi = merge(Hi, FieldHi);
2688 if (Lo == Memory || Hi == Memory)
2692 postMerge(Size, Lo, Hi);
2693 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
2697 if (const RecordType *RT = Ty->getAs<RecordType>()) {
2698 uint64_t Size = getContext().getTypeSize(Ty);
2700 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2701 // than eight eightbytes, ..., it has class MEMORY.
2705 // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
2706 // copy constructor or a non-trivial destructor, it is passed by invisible
2708 if (getRecordArgABI(RT, getCXXABI()))
2711 const RecordDecl *RD = RT->getDecl();
2713 // Assume variable sized types are passed in memory.
2714 if (RD->hasFlexibleArrayMember())
2717 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
2719 // Reset Lo class, this will be recomputed.
2722 // If this is a C++ record, classify the bases first.
2723 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2724 for (const auto &I : CXXRD->bases()) {
2725 assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2726 "Unexpected base class!");
2727 const CXXRecordDecl *Base =
2728 cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
2730 // Classify this field.
2732 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
2733 // single eightbyte, each is classified separately. Each eightbyte gets
2734 // initialized to class NO_CLASS.
2735 Class FieldLo, FieldHi;
2737 OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base));
2738 classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
2739 Lo = merge(Lo, FieldLo);
2740 Hi = merge(Hi, FieldHi);
2741 if (Lo == Memory || Hi == Memory) {
2742 postMerge(Size, Lo, Hi);
2748 // Classify the fields one at a time, merging the results.
2750 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2751 i != e; ++i, ++idx) {
2752 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2753 bool BitField = i->isBitField();
2755 // Ignore padding bit-fields.
2756 if (BitField && i->isUnnamedBitfield())
2759 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
2760 // four eightbytes, or it contains unaligned fields, it has class MEMORY.
2762 // The only case a 256-bit wide vector could be used is when the struct
2763 // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2764 // to work for sizes wider than 128, early check and fallback to memory.
2766 if (Size > 128 && (Size != getContext().getTypeSize(i->getType()) ||
2767 Size > getNativeVectorSizeForAVXABI(AVXLevel))) {
2769 postMerge(Size, Lo, Hi);
2772 // Note, skip this test for bit-fields, see below.
2773 if (!BitField && Offset % getContext().getTypeAlign(i->getType())) {
2775 postMerge(Size, Lo, Hi);
2779 // Classify this field.
2781 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
2782 // exceeds a single eightbyte, each is classified
2783 // separately. Each eightbyte gets initialized to class
2785 Class FieldLo, FieldHi;
2787 // Bit-fields require special handling, they do not force the
2788 // structure to be passed in memory even if unaligned, and
2789 // therefore they can straddle an eightbyte.
2791 assert(!i->isUnnamedBitfield());
2792 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2793 uint64_t Size = i->getBitWidthValue(getContext());
2795 uint64_t EB_Lo = Offset / 64;
2796 uint64_t EB_Hi = (Offset + Size - 1) / 64;
2799 assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes.");
2804 FieldHi = EB_Hi ? Integer : NoClass;
2807 classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
2808 Lo = merge(Lo, FieldLo);
2809 Hi = merge(Hi, FieldHi);
2810 if (Lo == Memory || Hi == Memory)
2814 postMerge(Size, Lo, Hi);
2818 ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const {
2819 // If this is a scalar LLVM value then assume LLVM will pass it in the right
2821 if (!isAggregateTypeForABI(Ty)) {
2822 // Treat an enum type as its underlying type.
2823 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2824 Ty = EnumTy->getDecl()->getIntegerType();
2826 return (Ty->isPromotableIntegerType() ?
2827 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
2830 return getNaturalAlignIndirect(Ty);
2833 bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const {
2834 if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
2835 uint64_t Size = getContext().getTypeSize(VecTy);
2836 unsigned LargestVector = getNativeVectorSizeForAVXABI(AVXLevel);
2837 if (Size <= 64 || Size > LargestVector)
2844 ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty,
2845 unsigned freeIntRegs) const {
2846 // If this is a scalar LLVM value then assume LLVM will pass it in the right
2849 // This assumption is optimistic, as there could be free registers available
2850 // when we need to pass this argument in memory, and LLVM could try to pass
2851 // the argument in the free register. This does not seem to happen currently,
2852 // but this code would be much safer if we could mark the argument with
2853 // 'onstack'. See PR12193.
2854 if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty)) {
2855 // Treat an enum type as its underlying type.
2856 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2857 Ty = EnumTy->getDecl()->getIntegerType();
2859 return (Ty->isPromotableIntegerType() ?
2860 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
2863 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
2864 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
2866 // Compute the byval alignment. We specify the alignment of the byval in all
2867 // cases so that the mid-level optimizer knows the alignment of the byval.
2868 unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U);
2870 // Attempt to avoid passing indirect results using byval when possible. This
2871 // is important for good codegen.
2873 // We do this by coercing the value into a scalar type which the backend can
2874 // handle naturally (i.e., without using byval).
2876 // For simplicity, we currently only do this when we have exhausted all of the
2877 // free integer registers. Doing this when there are free integer registers
2878 // would require more care, as we would have to ensure that the coerced value
2879 // did not claim the unused register. That would require either reording the
2880 // arguments to the function (so that any subsequent inreg values came first),
2881 // or only doing this optimization when there were no following arguments that
2884 // We currently expect it to be rare (particularly in well written code) for
2885 // arguments to be passed on the stack when there are still free integer
2886 // registers available (this would typically imply large structs being passed
2887 // by value), so this seems like a fair tradeoff for now.
2889 // We can revisit this if the backend grows support for 'onstack' parameter
2890 // attributes. See PR12193.
2891 if (freeIntRegs == 0) {
2892 uint64_t Size = getContext().getTypeSize(Ty);
2894 // If this type fits in an eightbyte, coerce it into the matching integral
2895 // type, which will end up on the stack (with alignment 8).
2896 if (Align == 8 && Size <= 64)
2897 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
2901 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align));
2904 /// The ABI specifies that a value should be passed in a full vector XMM/YMM
2905 /// register. Pick an LLVM IR type that will be passed as a vector register.
2906 llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const {
2907 // Wrapper structs/arrays that only contain vectors are passed just like
2908 // vectors; strip them off if present.
2909 if (const Type *InnerTy = isSingleElementStruct(Ty, getContext()))
2910 Ty = QualType(InnerTy, 0);
2912 llvm::Type *IRType = CGT.ConvertType(Ty);
2913 if (isa<llvm::VectorType>(IRType) ||
2914 IRType->getTypeID() == llvm::Type::FP128TyID)
2917 // We couldn't find the preferred IR vector type for 'Ty'.
2918 uint64_t Size = getContext().getTypeSize(Ty);
2919 assert((Size == 128 || Size == 256 || Size == 512) && "Invalid type found!");
2921 // Return a LLVM IR vector type based on the size of 'Ty'.
2922 return llvm::VectorType::get(llvm::Type::getDoubleTy(getVMContext()),
2926 /// BitsContainNoUserData - Return true if the specified [start,end) bit range
2927 /// is known to either be off the end of the specified type or being in
2928 /// alignment padding. The user type specified is known to be at most 128 bits
2929 /// in size, and have passed through X86_64ABIInfo::classify with a successful
2930 /// classification that put one of the two halves in the INTEGER class.
2932 /// It is conservatively correct to return false.
2933 static bool BitsContainNoUserData(QualType Ty, unsigned StartBit,
2934 unsigned EndBit, ASTContext &Context) {
2935 // If the bytes being queried are off the end of the type, there is no user
2936 // data hiding here. This handles analysis of builtins, vectors and other
2937 // types that don't contain interesting padding.
2938 unsigned TySize = (unsigned)Context.getTypeSize(Ty);
2939 if (TySize <= StartBit)
2942 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) {
2943 unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
2944 unsigned NumElts = (unsigned)AT->getSize().getZExtValue();
2946 // Check each element to see if the element overlaps with the queried range.
2947 for (unsigned i = 0; i != NumElts; ++i) {
2948 // If the element is after the span we care about, then we're done..
2949 unsigned EltOffset = i*EltSize;
2950 if (EltOffset >= EndBit) break;
2952 unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0;
2953 if (!BitsContainNoUserData(AT->getElementType(), EltStart,
2954 EndBit-EltOffset, Context))
2957 // If it overlaps no elements, then it is safe to process as padding.
2961 if (const RecordType *RT = Ty->getAs<RecordType>()) {
2962 const RecordDecl *RD = RT->getDecl();
2963 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
2965 // If this is a C++ record, check the bases first.
2966 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2967 for (const auto &I : CXXRD->bases()) {
2968 assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2969 "Unexpected base class!");
2970 const CXXRecordDecl *Base =
2971 cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
2973 // If the base is after the span we care about, ignore it.
2974 unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base));
2975 if (BaseOffset >= EndBit) continue;
2977 unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0;
2978 if (!BitsContainNoUserData(I.getType(), BaseStart,
2979 EndBit-BaseOffset, Context))
2984 // Verify that no field has data that overlaps the region of interest. Yes
2985 // this could be sped up a lot by being smarter about queried fields,
2986 // however we're only looking at structs up to 16 bytes, so we don't care
2989 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2990 i != e; ++i, ++idx) {
2991 unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx);
2993 // If we found a field after the region we care about, then we're done.
2994 if (FieldOffset >= EndBit) break;
2996 unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0;
2997 if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
3002 // If nothing in this record overlapped the area of interest, then we're
3010 /// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a
3011 /// float member at the specified offset. For example, {int,{float}} has a
3012 /// float at offset 4. It is conservatively correct for this routine to return
3014 static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset,
3015 const llvm::DataLayout &TD) {
3016 // Base case if we find a float.
3017 if (IROffset == 0 && IRType->isFloatTy())
3020 // If this is a struct, recurse into the field at the specified offset.
3021 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3022 const llvm::StructLayout *SL = TD.getStructLayout(STy);
3023 unsigned Elt = SL->getElementContainingOffset(IROffset);
3024 IROffset -= SL->getElementOffset(Elt);
3025 return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD);
3028 // If this is an array, recurse into the field at the specified offset.
3029 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3030 llvm::Type *EltTy = ATy->getElementType();
3031 unsigned EltSize = TD.getTypeAllocSize(EltTy);
3032 IROffset -= IROffset/EltSize*EltSize;
3033 return ContainsFloatAtOffset(EltTy, IROffset, TD);
3040 /// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
3041 /// low 8 bytes of an XMM register, corresponding to the SSE class.
3042 llvm::Type *X86_64ABIInfo::
3043 GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3044 QualType SourceTy, unsigned SourceOffset) const {
3045 // The only three choices we have are either double, <2 x float>, or float. We
3046 // pass as float if the last 4 bytes is just padding. This happens for
3047 // structs that contain 3 floats.
3048 if (BitsContainNoUserData(SourceTy, SourceOffset*8+32,
3049 SourceOffset*8+64, getContext()))
3050 return llvm::Type::getFloatTy(getVMContext());
3052 // We want to pass as <2 x float> if the LLVM IR type contains a float at
3053 // offset+0 and offset+4. Walk the LLVM IR type to find out if this is the
3055 if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) &&
3056 ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout()))
3057 return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2);
3059 return llvm::Type::getDoubleTy(getVMContext());
3063 /// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
3064 /// an 8-byte GPR. This means that we either have a scalar or we are talking
3065 /// about the high or low part of an up-to-16-byte struct. This routine picks
3066 /// the best LLVM IR type to represent this, which may be i64 or may be anything
3067 /// else that the backend will pass in a GPR that works better (e.g. i8, %foo*,
3070 /// PrefType is an LLVM IR type that corresponds to (part of) the IR type for
3071 /// the source type. IROffset is an offset in bytes into the LLVM IR type that
3072 /// the 8-byte value references. PrefType may be null.
3074 /// SourceTy is the source-level type for the entire argument. SourceOffset is
3075 /// an offset into this that we're processing (which is always either 0 or 8).
3077 llvm::Type *X86_64ABIInfo::
3078 GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3079 QualType SourceTy, unsigned SourceOffset) const {
3080 // If we're dealing with an un-offset LLVM IR type, then it means that we're
3081 // returning an 8-byte unit starting with it. See if we can safely use it.
3082 if (IROffset == 0) {
3083 // Pointers and int64's always fill the 8-byte unit.
3084 if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) ||
3085 IRType->isIntegerTy(64))
3088 // If we have a 1/2/4-byte integer, we can use it only if the rest of the
3089 // goodness in the source type is just tail padding. This is allowed to
3090 // kick in for struct {double,int} on the int, but not on
3091 // struct{double,int,int} because we wouldn't return the second int. We
3092 // have to do this analysis on the source type because we can't depend on
3093 // unions being lowered a specific way etc.
3094 if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) ||
3095 IRType->isIntegerTy(32) ||
3096 (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) {
3097 unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 :
3098 cast<llvm::IntegerType>(IRType)->getBitWidth();
3100 if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth,
3101 SourceOffset*8+64, getContext()))
3106 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3107 // If this is a struct, recurse into the field at the specified offset.
3108 const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy);
3109 if (IROffset < SL->getSizeInBytes()) {
3110 unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
3111 IROffset -= SL->getElementOffset(FieldIdx);
3113 return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
3114 SourceTy, SourceOffset);
3118 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3119 llvm::Type *EltTy = ATy->getElementType();
3120 unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
3121 unsigned EltOffset = IROffset/EltSize*EltSize;
3122 return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
3126 // Okay, we don't have any better idea of what to pass, so we pass this in an
3127 // integer register that isn't too big to fit the rest of the struct.
3128 unsigned TySizeInBytes =
3129 (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity();
3131 assert(TySizeInBytes != SourceOffset && "Empty field?");
3133 // It is always safe to classify this as an integer type up to i64 that
3134 // isn't larger than the structure.
3135 return llvm::IntegerType::get(getVMContext(),
3136 std::min(TySizeInBytes-SourceOffset, 8U)*8);
3140 /// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
3141 /// be used as elements of a two register pair to pass or return, return a
3142 /// first class aggregate to represent them. For example, if the low part of
3143 /// a by-value argument should be passed as i32* and the high part as float,
3144 /// return {i32*, float}.
3146 GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi,
3147 const llvm::DataLayout &TD) {
3148 // In order to correctly satisfy the ABI, we need to the high part to start
3149 // at offset 8. If the high and low parts we inferred are both 4-byte types
3150 // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have
3151 // the second element at offset 8. Check for this:
3152 unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo);
3153 unsigned HiAlign = TD.getABITypeAlignment(Hi);
3154 unsigned HiStart = llvm::alignTo(LoSize, HiAlign);
3155 assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!");
3157 // To handle this, we have to increase the size of the low part so that the
3158 // second element will start at an 8 byte offset. We can't increase the size
3159 // of the second element because it might make us access off the end of the
3162 // There are usually two sorts of types the ABI generation code can produce
3163 // for the low part of a pair that aren't 8 bytes in size: float or
3164 // i8/i16/i32. This can also include pointers when they are 32-bit (X32 and
3166 // Promote these to a larger type.
3167 if (Lo->isFloatTy())
3168 Lo = llvm::Type::getDoubleTy(Lo->getContext());
3170 assert((Lo->isIntegerTy() || Lo->isPointerTy())
3171 && "Invalid/unknown lo type");
3172 Lo = llvm::Type::getInt64Ty(Lo->getContext());
3176 llvm::StructType *Result = llvm::StructType::get(Lo, Hi);
3178 // Verify that the second element is at an 8-byte offset.
3179 assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
3180 "Invalid x86-64 argument pair!");
3184 ABIArgInfo X86_64ABIInfo::
3185 classifyReturnType(QualType RetTy) const {
3186 // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
3187 // classification algorithm.
3188 X86_64ABIInfo::Class Lo, Hi;
3189 classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);
3191 // Check some invariants.
3192 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3193 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3195 llvm::Type *ResType = nullptr;
3199 return ABIArgInfo::getIgnore();
3200 // If the low part is just padding, it takes no register, leave ResType
3202 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3203 "Unknown missing lo part");
3208 llvm_unreachable("Invalid classification for lo word.");
3210 // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
3213 return getIndirectReturnResult(RetTy);
3215 // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
3216 // available register of the sequence %rax, %rdx is used.
3218 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3220 // If we have a sign or zero extended integer, make sure to return Extend
3221 // so that the parameter gets the right LLVM IR attributes.
3222 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3223 // Treat an enum type as its underlying type.
3224 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
3225 RetTy = EnumTy->getDecl()->getIntegerType();
3227 if (RetTy->isIntegralOrEnumerationType() &&
3228 RetTy->isPromotableIntegerType())
3229 return ABIArgInfo::getExtend();
3233 // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
3234 // available SSE register of the sequence %xmm0, %xmm1 is used.
3236 ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3239 // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
3240 // returned on the X87 stack in %st0 as 80-bit x87 number.
3242 ResType = llvm::Type::getX86_FP80Ty(getVMContext());
3245 // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
3246 // part of the value is returned in %st0 and the imaginary part in
3249 assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.");
3250 ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()),
3251 llvm::Type::getX86_FP80Ty(getVMContext()));
3255 llvm::Type *HighPart = nullptr;
3257 // Memory was handled previously and X87 should
3258 // never occur as a hi class.
3261 llvm_unreachable("Invalid classification for hi word.");
3263 case ComplexX87: // Previously handled.
3268 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3269 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3270 return ABIArgInfo::getDirect(HighPart, 8);
3273 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3274 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3275 return ABIArgInfo::getDirect(HighPart, 8);
3278 // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
3279 // is passed in the next available eightbyte chunk if the last used
3282 // SSEUP should always be preceded by SSE, just widen.
3284 assert(Lo == SSE && "Unexpected SSEUp classification.");
3285 ResType = GetByteVectorType(RetTy);
3288 // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
3289 // returned together with the previous X87 value in %st0.
3291 // If X87Up is preceded by X87, we don't need to do
3292 // anything. However, in some cases with unions it may not be
3293 // preceded by X87. In such situations we follow gcc and pass the
3294 // extra bits in an SSE reg.
3296 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3297 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3298 return ABIArgInfo::getDirect(HighPart, 8);
3303 // If a high part was specified, merge it together with the low part. It is
3304 // known to pass in the high eightbyte of the result. We do this by forming a
3305 // first class struct aggregate with the high and low part: {low, high}
3307 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3309 return ABIArgInfo::getDirect(ResType);
3312 ABIArgInfo X86_64ABIInfo::classifyArgumentType(
3313 QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE,
3317 Ty = useFirstFieldIfTransparentUnion(Ty);
3319 X86_64ABIInfo::Class Lo, Hi;
3320 classify(Ty, 0, Lo, Hi, isNamedArg);
3322 // Check some invariants.
3323 // FIXME: Enforce these by construction.
3324 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3325 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3329 llvm::Type *ResType = nullptr;
3333 return ABIArgInfo::getIgnore();
3334 // If the low part is just padding, it takes no register, leave ResType
3336 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3337 "Unknown missing lo part");
3340 // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
3344 // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
3345 // COMPLEX_X87, it is passed in memory.
3348 if (getRecordArgABI(Ty, getCXXABI()) == CGCXXABI::RAA_Indirect)
3350 return getIndirectResult(Ty, freeIntRegs);
3354 llvm_unreachable("Invalid classification for lo word.");
3356 // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
3357 // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
3362 // Pick an 8-byte type based on the preferred type.
3363 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);
3365 // If we have a sign or zero extended integer, make sure to return Extend
3366 // so that the parameter gets the right LLVM IR attributes.
3367 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3368 // Treat an enum type as its underlying type.
3369 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3370 Ty = EnumTy->getDecl()->getIntegerType();
3372 if (Ty->isIntegralOrEnumerationType() &&
3373 Ty->isPromotableIntegerType())
3374 return ABIArgInfo::getExtend();
3379 // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
3380 // available SSE register is used, the registers are taken in the
3381 // order from %xmm0 to %xmm7.
3383 llvm::Type *IRType = CGT.ConvertType(Ty);
3384 ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);
3390 llvm::Type *HighPart = nullptr;
3392 // Memory was handled previously, ComplexX87 and X87 should
3393 // never occur as hi classes, and X87Up must be preceded by X87,
3394 // which is passed in memory.
3398 llvm_unreachable("Invalid classification for hi word.");
3400 case NoClass: break;
3404 // Pick an 8-byte type based on the preferred type.
3405 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3407 if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3408 return ABIArgInfo::getDirect(HighPart, 8);
3411 // X87Up generally doesn't occur here (long double is passed in
3412 // memory), except in situations involving unions.
3415 HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3417 if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3418 return ABIArgInfo::getDirect(HighPart, 8);
3423 // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
3424 // eightbyte is passed in the upper half of the last used SSE
3425 // register. This only happens when 128-bit vectors are passed.
3427 assert(Lo == SSE && "Unexpected SSEUp classification");
3428 ResType = GetByteVectorType(Ty);
3432 // If a high part was specified, merge it together with the low part. It is
3433 // known to pass in the high eightbyte of the result. We do this by forming a
3434 // first class struct aggregate with the high and low part: {low, high}
3436 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3438 return ABIArgInfo::getDirect(ResType);
3442 X86_64ABIInfo::classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
3443 unsigned &NeededSSE) const {
3444 auto RT = Ty->getAs<RecordType>();
3445 assert(RT && "classifyRegCallStructType only valid with struct types");
3447 if (RT->getDecl()->hasFlexibleArrayMember())
3448 return getIndirectReturnResult(Ty);
3451 if (auto CXXRD = dyn_cast<CXXRecordDecl>(RT->getDecl())) {
3452 if (CXXRD->isDynamicClass()) {
3453 NeededInt = NeededSSE = 0;
3454 return getIndirectReturnResult(Ty);
3457 for (const auto &I : CXXRD->bases())
3458 if (classifyRegCallStructTypeImpl(I.getType(), NeededInt, NeededSSE)
3460 NeededInt = NeededSSE = 0;
3461 return getIndirectReturnResult(Ty);
3466 for (const auto *FD : RT->getDecl()->fields()) {
3467 if (FD->getType()->isRecordType() && !FD->getType()->isUnionType()) {
3468 if (classifyRegCallStructTypeImpl(FD->getType(), NeededInt, NeededSSE)
3470 NeededInt = NeededSSE = 0;
3471 return getIndirectReturnResult(Ty);
3474 unsigned LocalNeededInt, LocalNeededSSE;
3475 if (classifyArgumentType(FD->getType(), UINT_MAX, LocalNeededInt,
3476 LocalNeededSSE, true)
3478 NeededInt = NeededSSE = 0;
3479 return getIndirectReturnResult(Ty);
3481 NeededInt += LocalNeededInt;
3482 NeededSSE += LocalNeededSSE;
3486 return ABIArgInfo::getDirect();
3489 ABIArgInfo X86_64ABIInfo::classifyRegCallStructType(QualType Ty,
3490 unsigned &NeededInt,
3491 unsigned &NeededSSE) const {
3496 return classifyRegCallStructTypeImpl(Ty, NeededInt, NeededSSE);
3499 void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3501 bool IsRegCall = FI.getCallingConvention() == llvm::CallingConv::X86_RegCall;
3503 // Keep track of the number of assigned registers.
3504 unsigned FreeIntRegs = IsRegCall ? 11 : 6;
3505 unsigned FreeSSERegs = IsRegCall ? 16 : 8;
3506 unsigned NeededInt, NeededSSE;
3508 if (IsRegCall && FI.getReturnType()->getTypePtr()->isRecordType() &&
3509 !FI.getReturnType()->getTypePtr()->isUnionType()) {
3510 FI.getReturnInfo() =
3511 classifyRegCallStructType(FI.getReturnType(), NeededInt, NeededSSE);
3512 if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3513 FreeIntRegs -= NeededInt;
3514 FreeSSERegs -= NeededSSE;
3516 FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3518 } else if (!getCXXABI().classifyReturnType(FI))
3519 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
3521 // If the return value is indirect, then the hidden argument is consuming one
3522 // integer register.
3523 if (FI.getReturnInfo().isIndirect())
3526 // The chain argument effectively gives us another free register.
3527 if (FI.isChainCall())
3530 unsigned NumRequiredArgs = FI.getNumRequiredArgs();
3531 // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
3532 // get assigned (in left-to-right order) for passing as follows...
3534 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
3535 it != ie; ++it, ++ArgNo) {
3536 bool IsNamedArg = ArgNo < NumRequiredArgs;
3538 if (IsRegCall && it->type->isStructureOrClassType())
3539 it->info = classifyRegCallStructType(it->type, NeededInt, NeededSSE);
3541 it->info = classifyArgumentType(it->type, FreeIntRegs, NeededInt,
3542 NeededSSE, IsNamedArg);
3544 // AMD64-ABI 3.2.3p3: If there are no registers available for any
3545 // eightbyte of an argument, the whole argument is passed on the
3546 // stack. If registers have already been assigned for some
3547 // eightbytes of such an argument, the assignments get reverted.
3548 if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3549 FreeIntRegs -= NeededInt;
3550 FreeSSERegs -= NeededSSE;
3552 it->info = getIndirectResult(it->type, FreeIntRegs);
3557 static Address EmitX86_64VAArgFromMemory(CodeGenFunction &CGF,
3558 Address VAListAddr, QualType Ty) {
3559 Address overflow_arg_area_p = CGF.Builder.CreateStructGEP(
3560 VAListAddr, 2, CharUnits::fromQuantity(8), "overflow_arg_area_p");
3561 llvm::Value *overflow_arg_area =
3562 CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area");
3564 // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
3565 // byte boundary if alignment needed by type exceeds 8 byte boundary.
3566 // It isn't stated explicitly in the standard, but in practice we use
3567 // alignment greater than 16 where necessary.
3568 CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
3569 if (Align > CharUnits::fromQuantity(8)) {
3570 overflow_arg_area = emitRoundPointerUpToAlignment(CGF, overflow_arg_area,
3574 // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
3575 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3577 CGF.Builder.CreateBitCast(overflow_arg_area,
3578 llvm::PointerType::getUnqual(LTy));
3580 // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
3581 // l->overflow_arg_area + sizeof(type).
3582 // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
3583 // an 8 byte boundary.
3585 uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8;
3586 llvm::Value *Offset =
3587 llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7);
3588 overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset,
3589 "overflow_arg_area.next");
3590 CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);
3592 // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
3593 return Address(Res, Align);
3596 Address X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3597 QualType Ty) const {
3598 // Assume that va_list type is correct; should be pointer to LLVM type:
3602 // i8* overflow_arg_area;
3603 // i8* reg_save_area;
3605 unsigned neededInt, neededSSE;
3607 Ty = getContext().getCanonicalType(Ty);
3608 ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
3609 /*isNamedArg*/false);
3611 // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
3612 // in the registers. If not go to step 7.
3613 if (!neededInt && !neededSSE)
3614 return EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3616 // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
3617 // general purpose registers needed to pass type and num_fp to hold
3618 // the number of floating point registers needed.
3620 // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
3621 // registers. In the case: l->gp_offset > 48 - num_gp * 8 or
3622 // l->fp_offset > 304 - num_fp * 16 go to step 7.
3624 // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of
3625 // register save space).
3627 llvm::Value *InRegs = nullptr;
3628 Address gp_offset_p = Address::invalid(), fp_offset_p = Address::invalid();
3629 llvm::Value *gp_offset = nullptr, *fp_offset = nullptr;
3632 CGF.Builder.CreateStructGEP(VAListAddr, 0, CharUnits::Zero(),
3634 gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset");
3635 InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
3636 InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp");
3641 CGF.Builder.CreateStructGEP(VAListAddr, 1, CharUnits::fromQuantity(4),
3643 fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset");
3644 llvm::Value *FitsInFP =
3645 llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
3646 FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp");
3647 InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP;
3650 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
3651 llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
3652 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
3653 CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
3655 // Emit code to load the value if it was passed in registers.
3657 CGF.EmitBlock(InRegBlock);
3659 // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
3660 // an offset of l->gp_offset and/or l->fp_offset. This may require
3661 // copying to a temporary location in case the parameter is passed
3662 // in different register classes or requires an alignment greater
3663 // than 8 for general purpose registers and 16 for XMM registers.
3665 // FIXME: This really results in shameful code when we end up needing to
3666 // collect arguments from different places; often what should result in a
3667 // simple assembling of a structure from scattered addresses has many more
3668 // loads than necessary. Can we clean this up?
3669 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3670 llvm::Value *RegSaveArea = CGF.Builder.CreateLoad(
3671 CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(16)),
3674 Address RegAddr = Address::invalid();
3675 if (neededInt && neededSSE) {
3677 assert(AI.isDirect() && "Unexpected ABI info for mixed regs");
3678 llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType());
3679 Address Tmp = CGF.CreateMemTemp(Ty);
3680 Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3681 assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs");
3682 llvm::Type *TyLo = ST->getElementType(0);
3683 llvm::Type *TyHi = ST->getElementType(1);
3684 assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&
3685 "Unexpected ABI info for mixed regs");
3686 llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo);
3687 llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi);
3688 llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegSaveArea, gp_offset);
3689 llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegSaveArea, fp_offset);
3690 llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? FPAddr : GPAddr;
3691 llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? GPAddr : FPAddr;
3693 // Copy the first element.
3694 // FIXME: Our choice of alignment here and below is probably pessimistic.
3695 llvm::Value *V = CGF.Builder.CreateAlignedLoad(
3696 TyLo, CGF.Builder.CreateBitCast(RegLoAddr, PTyLo),
3697 CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyLo)));
3698 CGF.Builder.CreateStore(V,
3699 CGF.Builder.CreateStructGEP(Tmp, 0, CharUnits::Zero()));
3701 // Copy the second element.
3702 V = CGF.Builder.CreateAlignedLoad(
3703 TyHi, CGF.Builder.CreateBitCast(RegHiAddr, PTyHi),
3704 CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyHi)));
3705 CharUnits Offset = CharUnits::fromQuantity(
3706 getDataLayout().getStructLayout(ST)->getElementOffset(1));
3707 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1, Offset));
3709 RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3710 } else if (neededInt) {
3711 RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, gp_offset),
3712 CharUnits::fromQuantity(8));
3713 RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3715 // Copy to a temporary if necessary to ensure the appropriate alignment.
3716 std::pair<CharUnits, CharUnits> SizeAlign =
3717 getContext().getTypeInfoInChars(Ty);
3718 uint64_t TySize = SizeAlign.first.getQuantity();
3719 CharUnits TyAlign = SizeAlign.second;
3721 // Copy into a temporary if the type is more aligned than the
3722 // register save area.
3723 if (TyAlign.getQuantity() > 8) {
3724 Address Tmp = CGF.CreateMemTemp(Ty);
3725 CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false);
3729 } else if (neededSSE == 1) {
3730 RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3731 CharUnits::fromQuantity(16));
3732 RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3734 assert(neededSSE == 2 && "Invalid number of needed registers!");
3735 // SSE registers are spaced 16 bytes apart in the register save
3736 // area, we need to collect the two eightbytes together.
3737 // The ABI isn't explicit about this, but it seems reasonable
3738 // to assume that the slots are 16-byte aligned, since the stack is
3739 // naturally 16-byte aligned and the prologue is expected to store
3740 // all the SSE registers to the RSA.
3741 Address RegAddrLo = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3742 CharUnits::fromQuantity(16));
3744 CGF.Builder.CreateConstInBoundsByteGEP(RegAddrLo,
3745 CharUnits::fromQuantity(16));
3746 llvm::Type *DoubleTy = CGF.DoubleTy;
3747 llvm::StructType *ST = llvm::StructType::get(DoubleTy, DoubleTy);
3749 Address Tmp = CGF.CreateMemTemp(Ty);
3750 Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3751 V = CGF.Builder.CreateLoad(
3752 CGF.Builder.CreateElementBitCast(RegAddrLo, DoubleTy));
3753 CGF.Builder.CreateStore(V,
3754 CGF.Builder.CreateStructGEP(Tmp, 0, CharUnits::Zero()));
3755 V = CGF.Builder.CreateLoad(
3756 CGF.Builder.CreateElementBitCast(RegAddrHi, DoubleTy));
3757 CGF.Builder.CreateStore(V,
3758 CGF.Builder.CreateStructGEP(Tmp, 1, CharUnits::fromQuantity(8)));
3760 RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3763 // AMD64-ABI 3.5.7p5: Step 5. Set:
3764 // l->gp_offset = l->gp_offset + num_gp * 8
3765 // l->fp_offset = l->fp_offset + num_fp * 16.
3767 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8);
3768 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset),
3772 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16);
3773 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset),
3776 CGF.EmitBranch(ContBlock);
3778 // Emit code to load the value if it was passed in memory.
3780 CGF.EmitBlock(InMemBlock);
3781 Address MemAddr = EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3783 // Return the appropriate result.
3785 CGF.EmitBlock(ContBlock);
3786 Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, MemAddr, InMemBlock,
3791 Address X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
3792 QualType Ty) const {
3793 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
3794 CGF.getContext().getTypeInfoInChars(Ty),
3795 CharUnits::fromQuantity(8),
3796 /*allowHigherAlign*/ false);
3800 WinX86_64ABIInfo::reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
3801 const ABIArgInfo ¤t) const {
3802 // Assumes vectorCall calling convention.
3803 const Type *Base = nullptr;
3804 uint64_t NumElts = 0;
3806 if (!Ty->isBuiltinType() && !Ty->isVectorType() &&
3807 isHomogeneousAggregate(Ty, Base, NumElts) && FreeSSERegs >= NumElts) {
3808 FreeSSERegs -= NumElts;
3809 return getDirectX86Hva();
3814 ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
3815 bool IsReturnType, bool IsVectorCall,
3816 bool IsRegCall) const {
3818 if (Ty->isVoidType())
3819 return ABIArgInfo::getIgnore();
3821 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3822 Ty = EnumTy->getDecl()->getIntegerType();
3824 TypeInfo Info = getContext().getTypeInfo(Ty);
3825 uint64_t Width = Info.Width;
3826 CharUnits Align = getContext().toCharUnitsFromBits(Info.Align);
3828 const RecordType *RT = Ty->getAs<RecordType>();
3830 if (!IsReturnType) {
3831 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI()))
3832 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
3835 if (RT->getDecl()->hasFlexibleArrayMember())
3836 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3840 const Type *Base = nullptr;
3841 uint64_t NumElts = 0;
3842 // vectorcall adds the concept of a homogenous vector aggregate, similar to
3844 if ((IsVectorCall || IsRegCall) &&
3845 isHomogeneousAggregate(Ty, Base, NumElts)) {
3847 if (FreeSSERegs >= NumElts) {
3848 FreeSSERegs -= NumElts;
3849 if (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())
3850 return ABIArgInfo::getDirect();
3851 return ABIArgInfo::getExpand();
3853 return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3854 } else if (IsVectorCall) {
3855 if (FreeSSERegs >= NumElts &&
3856 (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())) {
3857 FreeSSERegs -= NumElts;
3858 return ABIArgInfo::getDirect();
3859 } else if (IsReturnType) {
3860 return ABIArgInfo::getExpand();
3861 } else if (!Ty->isBuiltinType() && !Ty->isVectorType()) {
3862 // HVAs are delayed and reclassified in the 2nd step.
3863 return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3868 if (Ty->isMemberPointerType()) {
3869 // If the member pointer is represented by an LLVM int or ptr, pass it
3871 llvm::Type *LLTy = CGT.ConvertType(Ty);
3872 if (LLTy->isPointerTy() || LLTy->isIntegerTy())
3873 return ABIArgInfo::getDirect();
3876 if (RT || Ty->isAnyComplexType() || Ty->isMemberPointerType()) {
3877 // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
3878 // not 1, 2, 4, or 8 bytes, must be passed by reference."
3879 if (Width > 64 || !llvm::isPowerOf2_64(Width))
3880 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3882 // Otherwise, coerce it to a small integer.
3883 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width));
3886 // Bool type is always extended to the ABI, other builtin types are not
3888 const BuiltinType *BT = Ty->getAs<BuiltinType>();
3889 if (BT && BT->getKind() == BuiltinType::Bool)
3890 return ABIArgInfo::getExtend();
3892 // Mingw64 GCC uses the old 80 bit extended precision floating point unit. It
3893 // passes them indirectly through memory.
3894 if (IsMingw64 && BT && BT->getKind() == BuiltinType::LongDouble) {
3895 const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
3896 if (LDF == &llvm::APFloat::x87DoubleExtended())
3897 return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3900 return ABIArgInfo::getDirect();
3903 void WinX86_64ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI,
3904 unsigned FreeSSERegs,
3906 bool IsRegCall) const {
3908 for (auto &I : FI.arguments()) {
3909 // Vectorcall in x64 only permits the first 6 arguments to be passed
3910 // as XMM/YMM registers.
3911 if (Count < VectorcallMaxParamNumAsReg)
3912 I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
3914 // Since these cannot be passed in registers, pretend no registers
3916 unsigned ZeroSSERegsAvail = 0;
3917 I.info = classify(I.type, /*FreeSSERegs=*/ZeroSSERegsAvail, false,
3918 IsVectorCall, IsRegCall);
3923 for (auto &I : FI.arguments()) {
3924 I.info = reclassifyHvaArgType(I.type, FreeSSERegs, I.info);
3928 void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3930 FI.getCallingConvention() == llvm::CallingConv::X86_VectorCall;
3931 bool IsRegCall = FI.getCallingConvention() == llvm::CallingConv::X86_RegCall;
3933 unsigned FreeSSERegs = 0;
3935 // We can use up to 4 SSE return registers with vectorcall.
3937 } else if (IsRegCall) {
3938 // RegCall gives us 16 SSE registers.
3942 if (!getCXXABI().classifyReturnType(FI))
3943 FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true,
3944 IsVectorCall, IsRegCall);
3947 // We can use up to 6 SSE register parameters with vectorcall.
3949 } else if (IsRegCall) {
3950 // RegCall gives us 16 SSE registers, we can reuse the return registers.
3955 computeVectorCallArgs(FI, FreeSSERegs, IsVectorCall, IsRegCall);
3957 for (auto &I : FI.arguments())
3958 I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
3963 Address WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3964 QualType Ty) const {
3966 bool IsIndirect = false;
3968 // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
3969 // not 1, 2, 4, or 8 bytes, must be passed by reference."
3970 if (isAggregateTypeForABI(Ty) || Ty->isMemberPointerType()) {
3971 uint64_t Width = getContext().getTypeSize(Ty);
3972 IsIndirect = Width > 64 || !llvm::isPowerOf2_64(Width);
3975 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
3976 CGF.getContext().getTypeInfoInChars(Ty),
3977 CharUnits::fromQuantity(8),
3978 /*allowHigherAlign*/ false);
3983 /// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
3984 class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
3985 bool IsSoftFloatABI;
3987 PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI)
3988 : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI) {}
3990 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3991 QualType Ty) const override;
3994 class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
3996 PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI)
3997 : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI)) {}
3999 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4000 // This is recovered from gcc output.
4001 return 1; // r1 is the dedicated stack pointer
4004 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4005 llvm::Value *Address) const override;
4010 // TODO: this implementation is now likely redundant with
4011 // DefaultABIInfo::EmitVAArg.
4012 Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
4013 QualType Ty) const {
4014 const unsigned OverflowLimit = 8;
4015 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4016 // TODO: Implement this. For now ignore.
4018 return Address::invalid(); // FIXME?
4021 // struct __va_list_tag {
4022 // unsigned char gpr;
4023 // unsigned char fpr;
4024 // unsigned short reserved;
4025 // void *overflow_arg_area;
4026 // void *reg_save_area;
4029 bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;
4031 Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType();
4032 bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(Ty) == 64;
4034 // All aggregates are passed indirectly? That doesn't seem consistent
4035 // with the argument-lowering code.
4036 bool isIndirect = Ty->isAggregateType();
4038 CGBuilderTy &Builder = CGF.Builder;
4040 // The calling convention either uses 1-2 GPRs or 1 FPR.
4041 Address NumRegsAddr = Address::invalid();
4042 if (isInt || IsSoftFloatABI) {
4043 NumRegsAddr = Builder.CreateStructGEP(VAList, 0, CharUnits::Zero(), "gpr");
4045 NumRegsAddr = Builder.CreateStructGEP(VAList, 1, CharUnits::One(), "fpr");
4048 llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs");
4050 // "Align" the register count when TY is i64.
4051 if (isI64 || (isF64 && IsSoftFloatABI)) {
4052 NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1));
4053 NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U));
4057 Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond");
4059 llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
4060 llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
4061 llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
4063 Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
4065 llvm::Type *DirectTy = CGF.ConvertType(Ty);
4066 if (isIndirect) DirectTy = DirectTy->getPointerTo(0);
4068 // Case 1: consume registers.
4069 Address RegAddr = Address::invalid();
4071 CGF.EmitBlock(UsingRegs);
4073 Address RegSaveAreaPtr =
4074 Builder.CreateStructGEP(VAList, 4, CharUnits::fromQuantity(8));
4075 RegAddr = Address(Builder.CreateLoad(RegSaveAreaPtr),
4076 CharUnits::fromQuantity(8));
4077 assert(RegAddr.getElementType() == CGF.Int8Ty);
4079 // Floating-point registers start after the general-purpose registers.
4080 if (!(isInt || IsSoftFloatABI)) {
4081 RegAddr = Builder.CreateConstInBoundsByteGEP(RegAddr,
4082 CharUnits::fromQuantity(32));
4085 // Get the address of the saved value by scaling the number of
4086 // registers we've used by the number of
4087 CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8);
4088 llvm::Value *RegOffset =
4089 Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity()));
4090 RegAddr = Address(Builder.CreateInBoundsGEP(CGF.Int8Ty,
4091 RegAddr.getPointer(), RegOffset),
4092 RegAddr.getAlignment().alignmentOfArrayElement(RegSize));
4093 RegAddr = Builder.CreateElementBitCast(RegAddr, DirectTy);
4095 // Increase the used-register count.
4097 Builder.CreateAdd(NumRegs,
4098 Builder.getInt8((isI64 || (isF64 && IsSoftFloatABI)) ? 2 : 1));
4099 Builder.CreateStore(NumRegs, NumRegsAddr);
4101 CGF.EmitBranch(Cont);
4104 // Case 2: consume space in the overflow area.
4105 Address MemAddr = Address::invalid();
4107 CGF.EmitBlock(UsingOverflow);
4109 Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr);
4111 // Everything in the overflow area is rounded up to a size of at least 4.
4112 CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4);
4116 auto TypeInfo = CGF.getContext().getTypeInfoInChars(Ty);
4117 Size = TypeInfo.first.alignTo(OverflowAreaAlign);
4119 Size = CGF.getPointerSize();
4122 Address OverflowAreaAddr =
4123 Builder.CreateStructGEP(VAList, 3, CharUnits::fromQuantity(4));
4124 Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr, "argp.cur"),
4126 // Round up address of argument to alignment
4127 CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
4128 if (Align > OverflowAreaAlign) {
4129 llvm::Value *Ptr = OverflowArea.getPointer();
4130 OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),
4134 MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy);
4136 // Increase the overflow area.
4137 OverflowArea = Builder.CreateConstInBoundsByteGEP(OverflowArea, Size);
4138 Builder.CreateStore(OverflowArea.getPointer(), OverflowAreaAddr);
4139 CGF.EmitBranch(Cont);
4142 CGF.EmitBlock(Cont);
4144 // Merge the cases with a phi.
4145 Address Result = emitMergePHI(CGF, RegAddr, UsingRegs, MemAddr, UsingOverflow,
4148 // Load the pointer if the argument was passed indirectly.
4150 Result = Address(Builder.CreateLoad(Result, "aggr"),
4151 getContext().getTypeAlignInChars(Ty));
4158 PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4159 llvm::Value *Address) const {
4160 // This is calculated from the LLVM and GCC tables and verified
4161 // against gcc output. AFAIK all ABIs use the same encoding.
4163 CodeGen::CGBuilderTy &Builder = CGF.Builder;
4165 llvm::IntegerType *i8 = CGF.Int8Ty;
4166 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4167 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4168 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4170 // 0-31: r0-31, the 4-byte general-purpose registers
4171 AssignToArrayRange(Builder, Address, Four8, 0, 31);
4173 // 32-63: fp0-31, the 8-byte floating-point registers
4174 AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4176 // 64-76 are various 4-byte special-purpose registers:
4183 AssignToArrayRange(Builder, Address, Four8, 64, 76);
4185 // 77-108: v0-31, the 16-byte vector registers
4186 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4193 AssignToArrayRange(Builder, Address, Four8, 109, 113);
4201 /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
4202 class PPC64_SVR4_ABIInfo : public ABIInfo {
4210 static const unsigned GPRBits = 64;
4213 bool IsSoftFloatABI;
4215 // A vector of float or double will be promoted to <4 x f32> or <4 x f64> and
4216 // will be passed in a QPX register.
4217 bool IsQPXVectorTy(const Type *Ty) const {
4221 if (const VectorType *VT = Ty->getAs<VectorType>()) {
4222 unsigned NumElements = VT->getNumElements();
4223 if (NumElements == 1)
4226 if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) {
4227 if (getContext().getTypeSize(Ty) <= 256)
4229 } else if (VT->getElementType()->
4230 isSpecificBuiltinType(BuiltinType::Float)) {
4231 if (getContext().getTypeSize(Ty) <= 128)
4239 bool IsQPXVectorTy(QualType Ty) const {
4240 return IsQPXVectorTy(Ty.getTypePtr());
4244 PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
4246 : ABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
4247 IsSoftFloatABI(SoftFloatABI) {}
4249 bool isPromotableTypeForABI(QualType Ty) const;
4250 CharUnits getParamTypeAlignment(QualType Ty) const;
4252 ABIArgInfo classifyReturnType(QualType RetTy) const;
4253 ABIArgInfo classifyArgumentType(QualType Ty) const;
4255 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4256 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4257 uint64_t Members) const override;
4259 // TODO: We can add more logic to computeInfo to improve performance.
4260 // Example: For aggregate arguments that fit in a register, we could
4261 // use getDirectInReg (as is done below for structs containing a single
4262 // floating-point value) to avoid pushing them to memory on function
4263 // entry. This would require changing the logic in PPCISelLowering
4264 // when lowering the parameters in the caller and args in the callee.
4265 void computeInfo(CGFunctionInfo &FI) const override {
4266 if (!getCXXABI().classifyReturnType(FI))
4267 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
4268 for (auto &I : FI.arguments()) {
4269 // We rely on the default argument classification for the most part.
4270 // One exception: An aggregate containing a single floating-point
4271 // or vector item must be passed in a register if one is available.
4272 const Type *T = isSingleElementStruct(I.type, getContext());
4274 const BuiltinType *BT = T->getAs<BuiltinType>();
4275 if (IsQPXVectorTy(T) ||
4276 (T->isVectorType() && getContext().getTypeSize(T) == 128) ||
4277 (BT && BT->isFloatingPoint())) {
4279 I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
4283 I.info = classifyArgumentType(I.type);
4287 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4288 QualType Ty) const override;
4291 class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
4294 PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT,
4295 PPC64_SVR4_ABIInfo::ABIKind Kind, bool HasQPX,
4297 : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT, Kind, HasQPX,
4300 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4301 // This is recovered from gcc output.
4302 return 1; // r1 is the dedicated stack pointer
4305 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4306 llvm::Value *Address) const override;
4309 class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
4311 PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
4313 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4314 // This is recovered from gcc output.
4315 return 1; // r1 is the dedicated stack pointer
4318 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4319 llvm::Value *Address) const override;
4324 // Return true if the ABI requires Ty to be passed sign- or zero-
4325 // extended to 64 bits.
4327 PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
4328 // Treat an enum type as its underlying type.
4329 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4330 Ty = EnumTy->getDecl()->getIntegerType();
4332 // Promotable integer types are required to be promoted by the ABI.
4333 if (Ty->isPromotableIntegerType())
4336 // In addition to the usual promotable integer types, we also need to
4337 // extend all 32-bit types, since the ABI requires promotion to 64 bits.
4338 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
4339 switch (BT->getKind()) {
4340 case BuiltinType::Int:
4341 case BuiltinType::UInt:
4350 /// isAlignedParamType - Determine whether a type requires 16-byte or
4351 /// higher alignment in the parameter area. Always returns at least 8.
4352 CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4353 // Complex types are passed just like their elements.
4354 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4355 Ty = CTy->getElementType();
4357 // Only vector types of size 16 bytes need alignment (larger types are
4358 // passed via reference, smaller types are not aligned).
4359 if (IsQPXVectorTy(Ty)) {
4360 if (getContext().getTypeSize(Ty) > 128)
4361 return CharUnits::fromQuantity(32);
4363 return CharUnits::fromQuantity(16);
4364 } else if (Ty->isVectorType()) {
4365 return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);
4368 // For single-element float/vector structs, we consider the whole type
4369 // to have the same alignment requirements as its single element.
4370 const Type *AlignAsType = nullptr;
4371 const Type *EltType = isSingleElementStruct(Ty, getContext());
4373 const BuiltinType *BT = EltType->getAs<BuiltinType>();
4374 if (IsQPXVectorTy(EltType) || (EltType->isVectorType() &&
4375 getContext().getTypeSize(EltType) == 128) ||
4376 (BT && BT->isFloatingPoint()))
4377 AlignAsType = EltType;
4380 // Likewise for ELFv2 homogeneous aggregates.
4381 const Type *Base = nullptr;
4382 uint64_t Members = 0;
4383 if (!AlignAsType && Kind == ELFv2 &&
4384 isAggregateTypeForABI(Ty) && isHomogeneousAggregate(Ty, Base, Members))
4387 // With special case aggregates, only vector base types need alignment.
4388 if (AlignAsType && IsQPXVectorTy(AlignAsType)) {
4389 if (getContext().getTypeSize(AlignAsType) > 128)
4390 return CharUnits::fromQuantity(32);
4392 return CharUnits::fromQuantity(16);
4393 } else if (AlignAsType) {
4394 return CharUnits::fromQuantity(AlignAsType->isVectorType() ? 16 : 8);
4397 // Otherwise, we only need alignment for any aggregate type that
4398 // has an alignment requirement of >= 16 bytes.
4399 if (isAggregateTypeForABI(Ty) && getContext().getTypeAlign(Ty) >= 128) {
4400 if (HasQPX && getContext().getTypeAlign(Ty) >= 256)
4401 return CharUnits::fromQuantity(32);
4402 return CharUnits::fromQuantity(16);
4405 return CharUnits::fromQuantity(8);
4408 /// isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous
4409 /// aggregate. Base is set to the base element type, and Members is set
4410 /// to the number of base elements.
4411 bool ABIInfo::isHomogeneousAggregate(QualType Ty, const Type *&Base,
4412 uint64_t &Members) const {
4413 if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
4414 uint64_t NElements = AT->getSize().getZExtValue();
4417 if (!isHomogeneousAggregate(AT->getElementType(), Base, Members))
4419 Members *= NElements;
4420 } else if (const RecordType *RT = Ty->getAs<RecordType>()) {
4421 const RecordDecl *RD = RT->getDecl();
4422 if (RD->hasFlexibleArrayMember())
4427 // If this is a C++ record, check the bases first.
4428 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
4429 for (const auto &I : CXXRD->bases()) {
4430 // Ignore empty records.
4431 if (isEmptyRecord(getContext(), I.getType(), true))
4434 uint64_t FldMembers;
4435 if (!isHomogeneousAggregate(I.getType(), Base, FldMembers))
4438 Members += FldMembers;
4442 for (const auto *FD : RD->fields()) {
4443 // Ignore (non-zero arrays of) empty records.
4444 QualType FT = FD->getType();
4445 while (const ConstantArrayType *AT =
4446 getContext().getAsConstantArrayType(FT)) {
4447 if (AT->getSize().getZExtValue() == 0)
4449 FT = AT->getElementType();
4451 if (isEmptyRecord(getContext(), FT, true))
4454 // For compatibility with GCC, ignore empty bitfields in C++ mode.
4455 if (getContext().getLangOpts().CPlusPlus &&
4456 FD->isBitField() && FD->getBitWidthValue(getContext()) == 0)
4459 uint64_t FldMembers;
4460 if (!isHomogeneousAggregate(FD->getType(), Base, FldMembers))
4463 Members = (RD->isUnion() ?
4464 std::max(Members, FldMembers) : Members + FldMembers);
4470 // Ensure there is no padding.
4471 if (getContext().getTypeSize(Base) * Members !=
4472 getContext().getTypeSize(Ty))
4476 if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
4478 Ty = CT->getElementType();
4481 // Most ABIs only support float, double, and some vector type widths.
4482 if (!isHomogeneousAggregateBaseType(Ty))
4485 // The base type must be the same for all members. Types that
4486 // agree in both total size and mode (float vs. vector) are
4487 // treated as being equivalent here.
4488 const Type *TyPtr = Ty.getTypePtr();
4491 // If it's a non-power-of-2 vector, its size is already a power-of-2,
4492 // so make sure to widen it explicitly.
4493 if (const VectorType *VT = Base->getAs<VectorType>()) {
4494 QualType EltTy = VT->getElementType();
4495 unsigned NumElements =
4496 getContext().getTypeSize(VT) / getContext().getTypeSize(EltTy);
4498 .getVectorType(EltTy, NumElements, VT->getVectorKind())
4503 if (Base->isVectorType() != TyPtr->isVectorType() ||
4504 getContext().getTypeSize(Base) != getContext().getTypeSize(TyPtr))
4507 return Members > 0 && isHomogeneousAggregateSmallEnough(Base, Members);
4510 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
4511 // Homogeneous aggregates for ELFv2 must have base types of float,
4512 // double, long double, or 128-bit vectors.
4513 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4514 if (BT->getKind() == BuiltinType::Float ||
4515 BT->getKind() == BuiltinType::Double ||
4516 BT->getKind() == BuiltinType::LongDouble) {
4522 if (const VectorType *VT = Ty->getAs<VectorType>()) {
4523 if (getContext().getTypeSize(VT) == 128 || IsQPXVectorTy(Ty))
4529 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
4530 const Type *Base, uint64_t Members) const {
4531 // Vector types require one register, floating point types require one
4532 // or two registers depending on their size.
4534 Base->isVectorType() ? 1 : (getContext().getTypeSize(Base) + 63) / 64;
4536 // Homogeneous Aggregates may occupy at most 8 registers.
4537 return Members * NumRegs <= 8;
4541 PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
4542 Ty = useFirstFieldIfTransparentUnion(Ty);
4544 if (Ty->isAnyComplexType())
4545 return ABIArgInfo::getDirect();
4547 // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
4548 // or via reference (larger than 16 bytes).
4549 if (Ty->isVectorType() && !IsQPXVectorTy(Ty)) {
4550 uint64_t Size = getContext().getTypeSize(Ty);
4552 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4553 else if (Size < 128) {
4554 llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4555 return ABIArgInfo::getDirect(CoerceTy);
4559 if (isAggregateTypeForABI(Ty)) {
4560 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
4561 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
4563 uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity();
4564 uint64_t TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();
4566 // ELFv2 homogeneous aggregates are passed as array types.
4567 const Type *Base = nullptr;
4568 uint64_t Members = 0;
4569 if (Kind == ELFv2 &&
4570 isHomogeneousAggregate(Ty, Base, Members)) {
4571 llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4572 llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4573 return ABIArgInfo::getDirect(CoerceTy);
4576 // If an aggregate may end up fully in registers, we do not
4577 // use the ByVal method, but pass the aggregate as array.
4578 // This is usually beneficial since we avoid forcing the
4579 // back-end to store the argument to memory.
4580 uint64_t Bits = getContext().getTypeSize(Ty);
4581 if (Bits > 0 && Bits <= 8 * GPRBits) {
4582 llvm::Type *CoerceTy;
4584 // Types up to 8 bytes are passed as integer type (which will be
4585 // properly aligned in the argument save area doubleword).
4586 if (Bits <= GPRBits)
4588 llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4589 // Larger types are passed as arrays, with the base type selected
4590 // according to the required alignment in the save area.
4592 uint64_t RegBits = ABIAlign * 8;
4593 uint64_t NumRegs = llvm::alignTo(Bits, RegBits) / RegBits;
4594 llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits);
4595 CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);
4598 return ABIArgInfo::getDirect(CoerceTy);
4601 // All other aggregates are passed ByVal.
4602 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(ABIAlign),
4604 /*Realign=*/TyAlign > ABIAlign);
4607 return (isPromotableTypeForABI(Ty) ?
4608 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
4612 PPC64_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {
4613 if (RetTy->isVoidType())
4614 return ABIArgInfo::getIgnore();
4616 if (RetTy->isAnyComplexType())
4617 return ABIArgInfo::getDirect();
4619 // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
4620 // or via reference (larger than 16 bytes).
4621 if (RetTy->isVectorType() && !IsQPXVectorTy(RetTy)) {
4622 uint64_t Size = getContext().getTypeSize(RetTy);
4624 return getNaturalAlignIndirect(RetTy);
4625 else if (Size < 128) {
4626 llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4627 return ABIArgInfo::getDirect(CoerceTy);
4631 if (isAggregateTypeForABI(RetTy)) {
4632 // ELFv2 homogeneous aggregates are returned as array types.
4633 const Type *Base = nullptr;
4634 uint64_t Members = 0;
4635 if (Kind == ELFv2 &&
4636 isHomogeneousAggregate(RetTy, Base, Members)) {
4637 llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4638 llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4639 return ABIArgInfo::getDirect(CoerceTy);
4642 // ELFv2 small aggregates are returned in up to two registers.
4643 uint64_t Bits = getContext().getTypeSize(RetTy);
4644 if (Kind == ELFv2 && Bits <= 2 * GPRBits) {
4646 return ABIArgInfo::getIgnore();
4648 llvm::Type *CoerceTy;
4649 if (Bits > GPRBits) {
4650 CoerceTy = llvm::IntegerType::get(getVMContext(), GPRBits);
4651 CoerceTy = llvm::StructType::get(CoerceTy, CoerceTy);
4654 llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4655 return ABIArgInfo::getDirect(CoerceTy);
4658 // All other aggregates are returned indirectly.
4659 return getNaturalAlignIndirect(RetTy);
4662 return (isPromotableTypeForABI(RetTy) ?
4663 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
4666 // Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
4667 Address PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4668 QualType Ty) const {
4669 auto TypeInfo = getContext().getTypeInfoInChars(Ty);
4670 TypeInfo.second = getParamTypeAlignment(Ty);
4672 CharUnits SlotSize = CharUnits::fromQuantity(8);
4674 // If we have a complex type and the base type is smaller than 8 bytes,
4675 // the ABI calls for the real and imaginary parts to be right-adjusted
4676 // in separate doublewords. However, Clang expects us to produce a
4677 // pointer to a structure with the two parts packed tightly. So generate
4678 // loads of the real and imaginary parts relative to the va_list pointer,
4679 // and store them to a temporary structure.
4680 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4681 CharUnits EltSize = TypeInfo.first / 2;
4682 if (EltSize < SlotSize) {
4683 Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty,
4684 SlotSize * 2, SlotSize,
4685 SlotSize, /*AllowHigher*/ true);
4687 Address RealAddr = Addr;
4688 Address ImagAddr = RealAddr;
4689 if (CGF.CGM.getDataLayout().isBigEndian()) {
4690 RealAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr,
4691 SlotSize - EltSize);
4692 ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(ImagAddr,
4693 2 * SlotSize - EltSize);
4695 ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize);
4698 llvm::Type *EltTy = CGF.ConvertTypeForMem(CTy->getElementType());
4699 RealAddr = CGF.Builder.CreateElementBitCast(RealAddr, EltTy);
4700 ImagAddr = CGF.Builder.CreateElementBitCast(ImagAddr, EltTy);
4701 llvm::Value *Real = CGF.Builder.CreateLoad(RealAddr, ".vareal");
4702 llvm::Value *Imag = CGF.Builder.CreateLoad(ImagAddr, ".vaimag");
4704 Address Temp = CGF.CreateMemTemp(Ty, "vacplx");
4705 CGF.EmitStoreOfComplex({Real, Imag}, CGF.MakeAddrLValue(Temp, Ty),
4711 // Otherwise, just use the general rule.
4712 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
4713 TypeInfo, SlotSize, /*AllowHigher*/ true);
4717 PPC64_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4718 llvm::Value *Address) {
4719 // This is calculated from the LLVM and GCC tables and verified
4720 // against gcc output. AFAIK all ABIs use the same encoding.
4722 CodeGen::CGBuilderTy &Builder = CGF.Builder;
4724 llvm::IntegerType *i8 = CGF.Int8Ty;
4725 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4726 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4727 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4729 // 0-31: r0-31, the 8-byte general-purpose registers
4730 AssignToArrayRange(Builder, Address, Eight8, 0, 31);
4732 // 32-63: fp0-31, the 8-byte floating-point registers
4733 AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4735 // 64-67 are various 8-byte special-purpose registers:
4740 AssignToArrayRange(Builder, Address, Eight8, 64, 67);
4742 // 68-76 are various 4-byte special-purpose registers:
4745 AssignToArrayRange(Builder, Address, Four8, 68, 76);
4747 // 77-108: v0-31, the 16-byte vector registers
4748 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4758 AssignToArrayRange(Builder, Address, Eight8, 109, 116);
4764 PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
4765 CodeGen::CodeGenFunction &CGF,
4766 llvm::Value *Address) const {
4768 return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4772 PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4773 llvm::Value *Address) const {
4775 return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4778 //===----------------------------------------------------------------------===//
4779 // AArch64 ABI Implementation
4780 //===----------------------------------------------------------------------===//
4784 class AArch64ABIInfo : public SwiftABIInfo {
4796 AArch64ABIInfo(CodeGenTypes &CGT, ABIKind Kind)
4797 : SwiftABIInfo(CGT), Kind(Kind) {}
4800 ABIKind getABIKind() const { return Kind; }
4801 bool isDarwinPCS() const { return Kind == DarwinPCS; }
4803 ABIArgInfo classifyReturnType(QualType RetTy) const;
4804 ABIArgInfo classifyArgumentType(QualType RetTy) const;
4805 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4806 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4807 uint64_t Members) const override;
4809 bool isIllegalVectorType(QualType Ty) const;
4811 void computeInfo(CGFunctionInfo &FI) const override {
4812 if (!getCXXABI().classifyReturnType(FI))
4813 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
4815 for (auto &it : FI.arguments())
4816 it.info = classifyArgumentType(it.type);
4819 Address EmitDarwinVAArg(Address VAListAddr, QualType Ty,
4820 CodeGenFunction &CGF) const;
4822 Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
4823 CodeGenFunction &CGF) const;
4825 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4826 QualType Ty) const override {
4827 return Kind == Win64 ? EmitMSVAArg(CGF, VAListAddr, Ty)
4828 : isDarwinPCS() ? EmitDarwinVAArg(VAListAddr, Ty, CGF)
4829 : EmitAAPCSVAArg(VAListAddr, Ty, CGF);
4832 Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
4833 QualType Ty) const override;
4835 bool shouldPassIndirectlyForSwift(CharUnits totalSize,
4836 ArrayRef<llvm::Type*> scalars,
4837 bool asReturnValue) const override {
4838 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
4840 bool isSwiftErrorInRegister() const override {
4844 bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
4845 unsigned elts) const override;
4848 class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
4850 AArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind Kind)
4851 : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
4853 StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
4854 return "mov\tfp, fp\t\t# marker for objc_retainAutoreleaseReturnValue";
4857 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4861 bool doesReturnSlotInterfereWithArgs() const override { return false; }
4865 ABIArgInfo AArch64ABIInfo::classifyArgumentType(QualType Ty) const {
4866 Ty = useFirstFieldIfTransparentUnion(Ty);
4868 // Handle illegal vector types here.
4869 if (isIllegalVectorType(Ty)) {
4870 uint64_t Size = getContext().getTypeSize(Ty);
4871 // Android promotes <2 x i8> to i16, not i32
4872 if (isAndroid() && (Size <= 16)) {
4873 llvm::Type *ResType = llvm::Type::getInt16Ty(getVMContext());
4874 return ABIArgInfo::getDirect(ResType);
4877 llvm::Type *ResType = llvm::Type::getInt32Ty(getVMContext());
4878 return ABIArgInfo::getDirect(ResType);
4881 llvm::Type *ResType =
4882 llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 2);
4883 return ABIArgInfo::getDirect(ResType);
4886 llvm::Type *ResType =
4887 llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 4);
4888 return ABIArgInfo::getDirect(ResType);
4890 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4893 if (!isAggregateTypeForABI(Ty)) {
4894 // Treat an enum type as its underlying type.
4895 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4896 Ty = EnumTy->getDecl()->getIntegerType();
4898 return (Ty->isPromotableIntegerType() && isDarwinPCS()
4899 ? ABIArgInfo::getExtend()
4900 : ABIArgInfo::getDirect());
4903 // Structures with either a non-trivial destructor or a non-trivial
4904 // copy constructor are always indirect.
4905 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
4906 return getNaturalAlignIndirect(Ty, /*ByVal=*/RAA ==
4907 CGCXXABI::RAA_DirectInMemory);
4910 // Empty records are always ignored on Darwin, but actually passed in C++ mode
4911 // elsewhere for GNU compatibility.
4912 uint64_t Size = getContext().getTypeSize(Ty);
4913 bool IsEmpty = isEmptyRecord(getContext(), Ty, true);
4914 if (IsEmpty || Size == 0) {
4915 if (!getContext().getLangOpts().CPlusPlus || isDarwinPCS())
4916 return ABIArgInfo::getIgnore();
4918 // GNU C mode. The only argument that gets ignored is an empty one with size
4920 if (IsEmpty && Size == 0)
4921 return ABIArgInfo::getIgnore();
4922 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
4925 // Homogeneous Floating-point Aggregates (HFAs) need to be expanded.
4926 const Type *Base = nullptr;
4927 uint64_t Members = 0;
4928 if (isHomogeneousAggregate(Ty, Base, Members)) {
4929 return ABIArgInfo::getDirect(
4930 llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members));
4933 // Aggregates <= 16 bytes are passed directly in registers or on the stack.
4935 // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
4936 // same size and alignment.
4937 if (getTarget().isRenderScriptTarget()) {
4938 return coerceToIntArray(Ty, getContext(), getVMContext());
4940 unsigned Alignment = getContext().getTypeAlign(Ty);
4941 Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes
4943 // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
4944 // For aggregates with 16-byte alignment, we use i128.
4945 if (Alignment < 128 && Size == 128) {
4946 llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
4947 return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
4949 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
4952 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4955 ABIArgInfo AArch64ABIInfo::classifyReturnType(QualType RetTy) const {
4956 if (RetTy->isVoidType())
4957 return ABIArgInfo::getIgnore();
4959 // Large vector types should be returned via memory.
4960 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128)
4961 return getNaturalAlignIndirect(RetTy);
4963 if (!isAggregateTypeForABI(RetTy)) {
4964 // Treat an enum type as its underlying type.
4965 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
4966 RetTy = EnumTy->getDecl()->getIntegerType();
4968 return (RetTy->isPromotableIntegerType() && isDarwinPCS()
4969 ? ABIArgInfo::getExtend()
4970 : ABIArgInfo::getDirect());
4973 uint64_t Size = getContext().getTypeSize(RetTy);
4974 if (isEmptyRecord(getContext(), RetTy, true) || Size == 0)
4975 return ABIArgInfo::getIgnore();
4977 const Type *Base = nullptr;
4978 uint64_t Members = 0;
4979 if (isHomogeneousAggregate(RetTy, Base, Members))
4980 // Homogeneous Floating-point Aggregates (HFAs) are returned directly.
4981 return ABIArgInfo::getDirect();
4983 // Aggregates <= 16 bytes are returned directly in registers or on the stack.
4985 // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
4986 // same size and alignment.
4987 if (getTarget().isRenderScriptTarget()) {
4988 return coerceToIntArray(RetTy, getContext(), getVMContext());
4990 unsigned Alignment = getContext().getTypeAlign(RetTy);
4991 Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes
4993 // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
4994 // For aggregates with 16-byte alignment, we use i128.
4995 if (Alignment < 128 && Size == 128) {
4996 llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
4997 return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
4999 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
5002 return getNaturalAlignIndirect(RetTy);
5005 /// isIllegalVectorType - check whether the vector type is legal for AArch64.
5006 bool AArch64ABIInfo::isIllegalVectorType(QualType Ty) const {
5007 if (const VectorType *VT = Ty->getAs<VectorType>()) {
5008 // Check whether VT is legal.
5009 unsigned NumElements = VT->getNumElements();
5010 uint64_t Size = getContext().getTypeSize(VT);
5011 // NumElements should be power of 2.
5012 if (!llvm::isPowerOf2_32(NumElements))
5014 return Size != 64 && (Size != 128 || NumElements == 1);
5019 bool AArch64ABIInfo::isLegalVectorTypeForSwift(CharUnits totalSize,
5021 unsigned elts) const {
5022 if (!llvm::isPowerOf2_32(elts))
5024 if (totalSize.getQuantity() != 8 &&
5025 (totalSize.getQuantity() != 16 || elts == 1))
5030 bool AArch64ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
5031 // Homogeneous aggregates for AAPCS64 must have base types of a floating
5032 // point type or a short-vector type. This is the same as the 32-bit ABI,
5033 // but with the difference that any floating-point type is allowed,
5034 // including __fp16.
5035 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
5036 if (BT->isFloatingPoint())
5038 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
5039 unsigned VecSize = getContext().getTypeSize(VT);
5040 if (VecSize == 64 || VecSize == 128)
5046 bool AArch64ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
5047 uint64_t Members) const {
5048 return Members <= 4;
5051 Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr,
5053 CodeGenFunction &CGF) const {
5054 ABIArgInfo AI = classifyArgumentType(Ty);
5055 bool IsIndirect = AI.isIndirect();
5057 llvm::Type *BaseTy = CGF.ConvertType(Ty);
5059 BaseTy = llvm::PointerType::getUnqual(BaseTy);
5060 else if (AI.getCoerceToType())
5061 BaseTy = AI.getCoerceToType();
5063 unsigned NumRegs = 1;
5064 if (llvm::ArrayType *ArrTy = dyn_cast<llvm::ArrayType>(BaseTy)) {
5065 BaseTy = ArrTy->getElementType();
5066 NumRegs = ArrTy->getNumElements();
5068 bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy();
5070 // The AArch64 va_list type and handling is specified in the Procedure Call
5071 // Standard, section B.4:
5081 llvm::BasicBlock *MaybeRegBlock = CGF.createBasicBlock("vaarg.maybe_reg");
5082 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
5083 llvm::BasicBlock *OnStackBlock = CGF.createBasicBlock("vaarg.on_stack");
5084 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
5086 auto TyInfo = getContext().getTypeInfoInChars(Ty);
5087 CharUnits TyAlign = TyInfo.second;
5089 Address reg_offs_p = Address::invalid();
5090 llvm::Value *reg_offs = nullptr;
5092 CharUnits reg_top_offset;
5093 int RegSize = IsIndirect ? 8 : TyInfo.first.getQuantity();
5095 // 3 is the field number of __gr_offs
5097 CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(24),
5099 reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "gr_offs");
5100 reg_top_index = 1; // field number for __gr_top
5101 reg_top_offset = CharUnits::fromQuantity(8);
5102 RegSize = llvm::alignTo(RegSize, 8);
5104 // 4 is the field number of __vr_offs.
5106 CGF.Builder.CreateStructGEP(VAListAddr, 4, CharUnits::fromQuantity(28),
5108 reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "vr_offs");
5109 reg_top_index = 2; // field number for __vr_top
5110 reg_top_offset = CharUnits::fromQuantity(16);
5111 RegSize = 16 * NumRegs;
5114 //=======================================
5115 // Find out where argument was passed
5116 //=======================================
5118 // If reg_offs >= 0 we're already using the stack for this type of
5119 // argument. We don't want to keep updating reg_offs (in case it overflows,
5120 // though anyone passing 2GB of arguments, each at most 16 bytes, deserves
5121 // whatever they get).
5122 llvm::Value *UsingStack = nullptr;
5123 UsingStack = CGF.Builder.CreateICmpSGE(
5124 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, 0));
5126 CGF.Builder.CreateCondBr(UsingStack, OnStackBlock, MaybeRegBlock);
5128 // Otherwise, at least some kind of argument could go in these registers, the
5129 // question is whether this particular type is too big.
5130 CGF.EmitBlock(MaybeRegBlock);
5132 // Integer arguments may need to correct register alignment (for example a
5133 // "struct { __int128 a; };" gets passed in x_2N, x_{2N+1}). In this case we
5134 // align __gr_offs to calculate the potential address.
5135 if (!IsFPR && !IsIndirect && TyAlign.getQuantity() > 8) {
5136 int Align = TyAlign.getQuantity();
5138 reg_offs = CGF.Builder.CreateAdd(
5139 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, Align - 1),
5141 reg_offs = CGF.Builder.CreateAnd(
5142 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, -Align),
5146 // Update the gr_offs/vr_offs pointer for next call to va_arg on this va_list.
5147 // The fact that this is done unconditionally reflects the fact that
5148 // allocating an argument to the stack also uses up all the remaining
5149 // registers of the appropriate kind.
5150 llvm::Value *NewOffset = nullptr;
5151 NewOffset = CGF.Builder.CreateAdd(
5152 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs");
5153 CGF.Builder.CreateStore(NewOffset, reg_offs_p);
5155 // Now we're in a position to decide whether this argument really was in
5156 // registers or not.
5157 llvm::Value *InRegs = nullptr;
5158 InRegs = CGF.Builder.CreateICmpSLE(
5159 NewOffset, llvm::ConstantInt::get(CGF.Int32Ty, 0), "inreg");
5161 CGF.Builder.CreateCondBr(InRegs, InRegBlock, OnStackBlock);
5163 //=======================================
5164 // Argument was in registers
5165 //=======================================
5167 // Now we emit the code for if the argument was originally passed in
5168 // registers. First start the appropriate block:
5169 CGF.EmitBlock(InRegBlock);
5171 llvm::Value *reg_top = nullptr;
5172 Address reg_top_p = CGF.Builder.CreateStructGEP(VAListAddr, reg_top_index,
5173 reg_top_offset, "reg_top_p");
5174 reg_top = CGF.Builder.CreateLoad(reg_top_p, "reg_top");
5175 Address BaseAddr(CGF.Builder.CreateInBoundsGEP(reg_top, reg_offs),
5176 CharUnits::fromQuantity(IsFPR ? 16 : 8));
5177 Address RegAddr = Address::invalid();
5178 llvm::Type *MemTy = CGF.ConvertTypeForMem(Ty);
5181 // If it's been passed indirectly (actually a struct), whatever we find from
5182 // stored registers or on the stack will actually be a struct **.
5183 MemTy = llvm::PointerType::getUnqual(MemTy);
5186 const Type *Base = nullptr;
5187 uint64_t NumMembers = 0;
5188 bool IsHFA = isHomogeneousAggregate(Ty, Base, NumMembers);
5189 if (IsHFA && NumMembers > 1) {
5190 // Homogeneous aggregates passed in registers will have their elements split
5191 // and stored 16-bytes apart regardless of size (they're notionally in qN,
5192 // qN+1, ...). We reload and store into a temporary local variable
5194 assert(!IsIndirect && "Homogeneous aggregates should be passed directly");
5195 auto BaseTyInfo = getContext().getTypeInfoInChars(QualType(Base, 0));
5196 llvm::Type *BaseTy = CGF.ConvertType(QualType(Base, 0));
5197 llvm::Type *HFATy = llvm::ArrayType::get(BaseTy, NumMembers);
5198 Address Tmp = CGF.CreateTempAlloca(HFATy,
5199 std::max(TyAlign, BaseTyInfo.second));
5201 // On big-endian platforms, the value will be right-aligned in its slot.
5203 if (CGF.CGM.getDataLayout().isBigEndian() &&
5204 BaseTyInfo.first.getQuantity() < 16)
5205 Offset = 16 - BaseTyInfo.first.getQuantity();
5207 for (unsigned i = 0; i < NumMembers; ++i) {
5208 CharUnits BaseOffset = CharUnits::fromQuantity(16 * i + Offset);
5210 CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, BaseOffset);
5211 LoadAddr = CGF.Builder.CreateElementBitCast(LoadAddr, BaseTy);
5214 CGF.Builder.CreateConstArrayGEP(Tmp, i, BaseTyInfo.first);
5216 llvm::Value *Elem = CGF.Builder.CreateLoad(LoadAddr);
5217 CGF.Builder.CreateStore(Elem, StoreAddr);
5220 RegAddr = CGF.Builder.CreateElementBitCast(Tmp, MemTy);
5222 // Otherwise the object is contiguous in memory.
5224 // It might be right-aligned in its slot.
5225 CharUnits SlotSize = BaseAddr.getAlignment();
5226 if (CGF.CGM.getDataLayout().isBigEndian() && !IsIndirect &&
5227 (IsHFA || !isAggregateTypeForABI(Ty)) &&
5228 TyInfo.first < SlotSize) {
5229 CharUnits Offset = SlotSize - TyInfo.first;
5230 BaseAddr = CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, Offset);
5233 RegAddr = CGF.Builder.CreateElementBitCast(BaseAddr, MemTy);
5236 CGF.EmitBranch(ContBlock);
5238 //=======================================
5239 // Argument was on the stack
5240 //=======================================
5241 CGF.EmitBlock(OnStackBlock);
5243 Address stack_p = CGF.Builder.CreateStructGEP(VAListAddr, 0,
5244 CharUnits::Zero(), "stack_p");
5245 llvm::Value *OnStackPtr = CGF.Builder.CreateLoad(stack_p, "stack");
5247 // Again, stack arguments may need realignment. In this case both integer and
5248 // floating-point ones might be affected.
5249 if (!IsIndirect && TyAlign.getQuantity() > 8) {
5250 int Align = TyAlign.getQuantity();
5252 OnStackPtr = CGF.Builder.CreatePtrToInt(OnStackPtr, CGF.Int64Ty);
5254 OnStackPtr = CGF.Builder.CreateAdd(
5255 OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, Align - 1),
5257 OnStackPtr = CGF.Builder.CreateAnd(
5258 OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, -Align),
5261 OnStackPtr = CGF.Builder.CreateIntToPtr(OnStackPtr, CGF.Int8PtrTy);
5263 Address OnStackAddr(OnStackPtr,
5264 std::max(CharUnits::fromQuantity(8), TyAlign));
5266 // All stack slots are multiples of 8 bytes.
5267 CharUnits StackSlotSize = CharUnits::fromQuantity(8);
5268 CharUnits StackSize;
5270 StackSize = StackSlotSize;
5272 StackSize = TyInfo.first.alignTo(StackSlotSize);
5274 llvm::Value *StackSizeC = CGF.Builder.getSize(StackSize);
5275 llvm::Value *NewStack =
5276 CGF.Builder.CreateInBoundsGEP(OnStackPtr, StackSizeC, "new_stack");
5278 // Write the new value of __stack for the next call to va_arg
5279 CGF.Builder.CreateStore(NewStack, stack_p);
5281 if (CGF.CGM.getDataLayout().isBigEndian() && !isAggregateTypeForABI(Ty) &&
5282 TyInfo.first < StackSlotSize) {
5283 CharUnits Offset = StackSlotSize - TyInfo.first;
5284 OnStackAddr = CGF.Builder.CreateConstInBoundsByteGEP(OnStackAddr, Offset);
5287 OnStackAddr = CGF.Builder.CreateElementBitCast(OnStackAddr, MemTy);
5289 CGF.EmitBranch(ContBlock);
5291 //=======================================
5293 //=======================================
5294 CGF.EmitBlock(ContBlock);
5296 Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
5297 OnStackAddr, OnStackBlock, "vaargs.addr");
5300 return Address(CGF.Builder.CreateLoad(ResAddr, "vaarg.addr"),
5306 Address AArch64ABIInfo::EmitDarwinVAArg(Address VAListAddr, QualType Ty,
5307 CodeGenFunction &CGF) const {
5308 // The backend's lowering doesn't support va_arg for aggregates or
5309 // illegal vector types. Lower VAArg here for these cases and use
5310 // the LLVM va_arg instruction for everything else.
5311 if (!isAggregateTypeForABI(Ty) && !isIllegalVectorType(Ty))
5312 return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
5314 CharUnits SlotSize = CharUnits::fromQuantity(8);
5316 // Empty records are ignored for parameter passing purposes.
5317 if (isEmptyRecord(getContext(), Ty, true)) {
5318 Address Addr(CGF.Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize);
5319 Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
5323 // The size of the actual thing passed, which might end up just
5324 // being a pointer for indirect types.
5325 auto TyInfo = getContext().getTypeInfoInChars(Ty);
5327 // Arguments bigger than 16 bytes which aren't homogeneous
5328 // aggregates should be passed indirectly.
5329 bool IsIndirect = false;
5330 if (TyInfo.first.getQuantity() > 16) {
5331 const Type *Base = nullptr;
5332 uint64_t Members = 0;
5333 IsIndirect = !isHomogeneousAggregate(Ty, Base, Members);
5336 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
5337 TyInfo, SlotSize, /*AllowHigherAlign*/ true);
5340 Address AArch64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
5341 QualType Ty) const {
5342 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
5343 CGF.getContext().getTypeInfoInChars(Ty),
5344 CharUnits::fromQuantity(8),
5345 /*allowHigherAlign*/ false);
5348 //===----------------------------------------------------------------------===//
5349 // ARM ABI Implementation
5350 //===----------------------------------------------------------------------===//
5354 class ARMABIInfo : public SwiftABIInfo {
5367 ARMABIInfo(CodeGenTypes &CGT, ABIKind _Kind)
5368 : SwiftABIInfo(CGT), Kind(_Kind) {
5372 bool isEABI() const {
5373 switch (getTarget().getTriple().getEnvironment()) {
5374 case llvm::Triple::Android:
5375 case llvm::Triple::EABI:
5376 case llvm::Triple::EABIHF:
5377 case llvm::Triple::GNUEABI:
5378 case llvm::Triple::GNUEABIHF:
5379 case llvm::Triple::MuslEABI:
5380 case llvm::Triple::MuslEABIHF:
5387 bool isEABIHF() const {
5388 switch (getTarget().getTriple().getEnvironment()) {
5389 case llvm::Triple::EABIHF:
5390 case llvm::Triple::GNUEABIHF:
5391 case llvm::Triple::MuslEABIHF:
5398 ABIKind getABIKind() const { return Kind; }
5401 ABIArgInfo classifyReturnType(QualType RetTy, bool isVariadic) const;
5402 ABIArgInfo classifyArgumentType(QualType RetTy, bool isVariadic) const;
5403 bool isIllegalVectorType(QualType Ty) const;
5405 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
5406 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
5407 uint64_t Members) const override;
5409 void computeInfo(CGFunctionInfo &FI) const override;
5411 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5412 QualType Ty) const override;
5414 llvm::CallingConv::ID getLLVMDefaultCC() const;
5415 llvm::CallingConv::ID getABIDefaultCC() const;
5418 bool shouldPassIndirectlyForSwift(CharUnits totalSize,
5419 ArrayRef<llvm::Type*> scalars,
5420 bool asReturnValue) const override {
5421 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
5423 bool isSwiftErrorInRegister() const override {
5426 bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
5427 unsigned elts) const override;
5430 class ARMTargetCodeGenInfo : public TargetCodeGenInfo {
5432 ARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5433 :TargetCodeGenInfo(new ARMABIInfo(CGT, K)) {}
5435 const ARMABIInfo &getABIInfo() const {
5436 return static_cast<const ARMABIInfo&>(TargetCodeGenInfo::getABIInfo());
5439 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5443 StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
5444 return "mov\tr7, r7\t\t@ marker for objc_retainAutoreleaseReturnValue";
5447 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5448 llvm::Value *Address) const override {
5449 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
5451 // 0-15 are the 16 integer registers.
5452 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 15);
5456 unsigned getSizeOfUnwindException() const override {
5457 if (getABIInfo().isEABI()) return 88;
5458 return TargetCodeGenInfo::getSizeOfUnwindException();
5461 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5462 CodeGen::CodeGenModule &CGM) const override {
5463 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
5467 const ARMInterruptAttr *Attr = FD->getAttr<ARMInterruptAttr>();
5472 switch (Attr->getInterrupt()) {
5473 case ARMInterruptAttr::Generic: Kind = ""; break;
5474 case ARMInterruptAttr::IRQ: Kind = "IRQ"; break;
5475 case ARMInterruptAttr::FIQ: Kind = "FIQ"; break;
5476 case ARMInterruptAttr::SWI: Kind = "SWI"; break;
5477 case ARMInterruptAttr::ABORT: Kind = "ABORT"; break;
5478 case ARMInterruptAttr::UNDEF: Kind = "UNDEF"; break;
5481 llvm::Function *Fn = cast<llvm::Function>(GV);
5483 Fn->addFnAttr("interrupt", Kind);
5485 ARMABIInfo::ABIKind ABI = cast<ARMABIInfo>(getABIInfo()).getABIKind();
5486 if (ABI == ARMABIInfo::APCS)
5489 // AAPCS guarantees that sp will be 8-byte aligned on any public interface,
5490 // however this is not necessarily true on taking any interrupt. Instruct
5491 // the backend to perform a realignment as part of the function prologue.
5492 llvm::AttrBuilder B;
5493 B.addStackAlignmentAttr(8);
5494 Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
5498 class WindowsARMTargetCodeGenInfo : public ARMTargetCodeGenInfo {
5500 WindowsARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5501 : ARMTargetCodeGenInfo(CGT, K) {}
5503 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5504 CodeGen::CodeGenModule &CGM) const override;
5506 void getDependentLibraryOption(llvm::StringRef Lib,
5507 llvm::SmallString<24> &Opt) const override {
5508 Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
5511 void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
5512 llvm::SmallString<32> &Opt) const override {
5513 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
5517 void WindowsARMTargetCodeGenInfo::setTargetAttributes(
5518 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
5519 ARMTargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
5520 addStackProbeSizeTargetAttribute(D, GV, CGM);
5524 void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const {
5525 if (!getCXXABI().classifyReturnType(FI))
5526 FI.getReturnInfo() =
5527 classifyReturnType(FI.getReturnType(), FI.isVariadic());
5529 for (auto &I : FI.arguments())
5530 I.info = classifyArgumentType(I.type, FI.isVariadic());
5532 // Always honor user-specified calling convention.
5533 if (FI.getCallingConvention() != llvm::CallingConv::C)
5536 llvm::CallingConv::ID cc = getRuntimeCC();
5537 if (cc != llvm::CallingConv::C)
5538 FI.setEffectiveCallingConvention(cc);
5541 /// Return the default calling convention that LLVM will use.
5542 llvm::CallingConv::ID ARMABIInfo::getLLVMDefaultCC() const {
5543 // The default calling convention that LLVM will infer.
5544 if (isEABIHF() || getTarget().getTriple().isWatchABI())
5545 return llvm::CallingConv::ARM_AAPCS_VFP;
5547 return llvm::CallingConv::ARM_AAPCS;
5549 return llvm::CallingConv::ARM_APCS;
5552 /// Return the calling convention that our ABI would like us to use
5553 /// as the C calling convention.
5554 llvm::CallingConv::ID ARMABIInfo::getABIDefaultCC() const {
5555 switch (getABIKind()) {
5556 case APCS: return llvm::CallingConv::ARM_APCS;
5557 case AAPCS: return llvm::CallingConv::ARM_AAPCS;
5558 case AAPCS_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
5559 case AAPCS16_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
5561 llvm_unreachable("bad ABI kind");
5564 void ARMABIInfo::setCCs() {
5565 assert(getRuntimeCC() == llvm::CallingConv::C);
5567 // Don't muddy up the IR with a ton of explicit annotations if
5568 // they'd just match what LLVM will infer from the triple.
5569 llvm::CallingConv::ID abiCC = getABIDefaultCC();
5570 if (abiCC != getLLVMDefaultCC())
5573 // AAPCS apparently requires runtime support functions to be soft-float, but
5574 // that's almost certainly for historic reasons (Thumb1 not supporting VFP
5575 // most likely). It's more convenient for AAPCS16_VFP to be hard-float.
5576 switch (getABIKind()) {
5579 if (abiCC != getLLVMDefaultCC())
5584 BuiltinCC = llvm::CallingConv::ARM_AAPCS;
5589 ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty,
5590 bool isVariadic) const {
5591 // 6.1.2.1 The following argument types are VFP CPRCs:
5592 // A single-precision floating-point type (including promoted
5593 // half-precision types); A double-precision floating-point type;
5594 // A 64-bit or 128-bit containerized vector type; Homogeneous Aggregate
5595 // with a Base Type of a single- or double-precision floating-point type,
5596 // 64-bit containerized vectors or 128-bit containerized vectors with one
5597 // to four Elements.
5598 bool IsEffectivelyAAPCS_VFP = getABIKind() == AAPCS_VFP && !isVariadic;
5600 Ty = useFirstFieldIfTransparentUnion(Ty);
5602 // Handle illegal vector types here.
5603 if (isIllegalVectorType(Ty)) {
5604 uint64_t Size = getContext().getTypeSize(Ty);
5606 llvm::Type *ResType =
5607 llvm::Type::getInt32Ty(getVMContext());
5608 return ABIArgInfo::getDirect(ResType);
5611 llvm::Type *ResType = llvm::VectorType::get(
5612 llvm::Type::getInt32Ty(getVMContext()), 2);
5613 return ABIArgInfo::getDirect(ResType);
5616 llvm::Type *ResType = llvm::VectorType::get(
5617 llvm::Type::getInt32Ty(getVMContext()), 4);
5618 return ABIArgInfo::getDirect(ResType);
5620 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5623 // __fp16 gets passed as if it were an int or float, but with the top 16 bits
5624 // unspecified. This is not done for OpenCL as it handles the half type
5625 // natively, and does not need to interwork with AAPCS code.
5626 if (Ty->isHalfType() && !getContext().getLangOpts().NativeHalfArgsAndReturns) {
5627 llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
5628 llvm::Type::getFloatTy(getVMContext()) :
5629 llvm::Type::getInt32Ty(getVMContext());
5630 return ABIArgInfo::getDirect(ResType);
5633 if (!isAggregateTypeForABI(Ty)) {
5634 // Treat an enum type as its underlying type.
5635 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
5636 Ty = EnumTy->getDecl()->getIntegerType();
5639 return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend()
5640 : ABIArgInfo::getDirect());
5643 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
5644 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
5647 // Ignore empty records.
5648 if (isEmptyRecord(getContext(), Ty, true))
5649 return ABIArgInfo::getIgnore();
5651 if (IsEffectivelyAAPCS_VFP) {
5652 // Homogeneous Aggregates need to be expanded when we can fit the aggregate
5653 // into VFP registers.
5654 const Type *Base = nullptr;
5655 uint64_t Members = 0;
5656 if (isHomogeneousAggregate(Ty, Base, Members)) {
5657 assert(Base && "Base class should be set for homogeneous aggregate");
5658 // Base can be a floating-point or a vector.
5659 return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
5661 } else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) {
5662 // WatchOS does have homogeneous aggregates. Note that we intentionally use
5663 // this convention even for a variadic function: the backend will use GPRs
5665 const Type *Base = nullptr;
5666 uint64_t Members = 0;
5667 if (isHomogeneousAggregate(Ty, Base, Members)) {
5668 assert(Base && Members <= 4 && "unexpected homogeneous aggregate");
5670 llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members);
5671 return ABIArgInfo::getDirect(Ty, 0, nullptr, false);
5675 if (getABIKind() == ARMABIInfo::AAPCS16_VFP &&
5676 getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(16)) {
5677 // WatchOS is adopting the 64-bit AAPCS rule on composite types: if they're
5678 // bigger than 128-bits, they get placed in space allocated by the caller,
5679 // and a pointer is passed.
5680 return ABIArgInfo::getIndirect(
5681 CharUnits::fromQuantity(getContext().getTypeAlign(Ty) / 8), false);
5684 // Support byval for ARM.
5685 // The ABI alignment for APCS is 4-byte and for AAPCS at least 4-byte and at
5686 // most 8-byte. We realign the indirect argument if type alignment is bigger
5687 // than ABI alignment.
5688 uint64_t ABIAlign = 4;
5689 uint64_t TyAlign = getContext().getTypeAlign(Ty) / 8;
5690 if (getABIKind() == ARMABIInfo::AAPCS_VFP ||
5691 getABIKind() == ARMABIInfo::AAPCS)
5692 ABIAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8);
5694 if (getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(64)) {
5695 assert(getABIKind() != ARMABIInfo::AAPCS16_VFP && "unexpected byval");
5696 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(ABIAlign),
5698 /*Realign=*/TyAlign > ABIAlign);
5701 // On RenderScript, coerce Aggregates <= 64 bytes to an integer array of
5702 // same size and alignment.
5703 if (getTarget().isRenderScriptTarget()) {
5704 return coerceToIntArray(Ty, getContext(), getVMContext());
5707 // Otherwise, pass by coercing to a structure of the appropriate size.
5710 // FIXME: Try to match the types of the arguments more accurately where
5712 if (getContext().getTypeAlign(Ty) <= 32) {
5713 ElemTy = llvm::Type::getInt32Ty(getVMContext());
5714 SizeRegs = (getContext().getTypeSize(Ty) + 31) / 32;
5716 ElemTy = llvm::Type::getInt64Ty(getVMContext());
5717 SizeRegs = (getContext().getTypeSize(Ty) + 63) / 64;
5720 return ABIArgInfo::getDirect(llvm::ArrayType::get(ElemTy, SizeRegs));
5723 static bool isIntegerLikeType(QualType Ty, ASTContext &Context,
5724 llvm::LLVMContext &VMContext) {
5725 // APCS, C Language Calling Conventions, Non-Simple Return Values: A structure
5726 // is called integer-like if its size is less than or equal to one word, and
5727 // the offset of each of its addressable sub-fields is zero.
5729 uint64_t Size = Context.getTypeSize(Ty);
5731 // Check that the type fits in a word.
5735 // FIXME: Handle vector types!
5736 if (Ty->isVectorType())
5739 // Float types are never treated as "integer like".
5740 if (Ty->isRealFloatingType())
5743 // If this is a builtin or pointer type then it is ok.
5744 if (Ty->getAs<BuiltinType>() || Ty->isPointerType())
5747 // Small complex integer types are "integer like".
5748 if (const ComplexType *CT = Ty->getAs<ComplexType>())
5749 return isIntegerLikeType(CT->getElementType(), Context, VMContext);
5751 // Single element and zero sized arrays should be allowed, by the definition
5752 // above, but they are not.
5754 // Otherwise, it must be a record type.
5755 const RecordType *RT = Ty->getAs<RecordType>();
5756 if (!RT) return false;
5758 // Ignore records with flexible arrays.
5759 const RecordDecl *RD = RT->getDecl();
5760 if (RD->hasFlexibleArrayMember())
5763 // Check that all sub-fields are at offset 0, and are themselves "integer
5765 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
5767 bool HadField = false;
5769 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
5770 i != e; ++i, ++idx) {
5771 const FieldDecl *FD = *i;
5773 // Bit-fields are not addressable, we only need to verify they are "integer
5774 // like". We still have to disallow a subsequent non-bitfield, for example:
5775 // struct { int : 0; int x }
5776 // is non-integer like according to gcc.
5777 if (FD->isBitField()) {
5781 if (!isIntegerLikeType(FD->getType(), Context, VMContext))
5787 // Check if this field is at offset 0.
5788 if (Layout.getFieldOffset(idx) != 0)
5791 if (!isIntegerLikeType(FD->getType(), Context, VMContext))
5794 // Only allow at most one field in a structure. This doesn't match the
5795 // wording above, but follows gcc in situations with a field following an
5797 if (!RD->isUnion()) {
5808 ABIArgInfo ARMABIInfo::classifyReturnType(QualType RetTy,
5809 bool isVariadic) const {
5810 bool IsEffectivelyAAPCS_VFP =
5811 (getABIKind() == AAPCS_VFP || getABIKind() == AAPCS16_VFP) && !isVariadic;
5813 if (RetTy->isVoidType())
5814 return ABIArgInfo::getIgnore();
5816 // Large vector types should be returned via memory.
5817 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128) {
5818 return getNaturalAlignIndirect(RetTy);
5821 // __fp16 gets returned as if it were an int or float, but with the top 16
5822 // bits unspecified. This is not done for OpenCL as it handles the half type
5823 // natively, and does not need to interwork with AAPCS code.
5824 if (RetTy->isHalfType() && !getContext().getLangOpts().NativeHalfArgsAndReturns) {
5825 llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
5826 llvm::Type::getFloatTy(getVMContext()) :
5827 llvm::Type::getInt32Ty(getVMContext());
5828 return ABIArgInfo::getDirect(ResType);
5831 if (!isAggregateTypeForABI(RetTy)) {
5832 // Treat an enum type as its underlying type.
5833 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5834 RetTy = EnumTy->getDecl()->getIntegerType();
5836 return RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend()
5837 : ABIArgInfo::getDirect();
5840 // Are we following APCS?
5841 if (getABIKind() == APCS) {
5842 if (isEmptyRecord(getContext(), RetTy, false))
5843 return ABIArgInfo::getIgnore();
5845 // Complex types are all returned as packed integers.
5847 // FIXME: Consider using 2 x vector types if the back end handles them
5849 if (RetTy->isAnyComplexType())
5850 return ABIArgInfo::getDirect(llvm::IntegerType::get(
5851 getVMContext(), getContext().getTypeSize(RetTy)));
5853 // Integer like structures are returned in r0.
5854 if (isIntegerLikeType(RetTy, getContext(), getVMContext())) {
5855 // Return in the smallest viable integer type.
5856 uint64_t Size = getContext().getTypeSize(RetTy);
5858 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
5860 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
5861 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
5864 // Otherwise return in memory.
5865 return getNaturalAlignIndirect(RetTy);
5868 // Otherwise this is an AAPCS variant.
5870 if (isEmptyRecord(getContext(), RetTy, true))
5871 return ABIArgInfo::getIgnore();
5873 // Check for homogeneous aggregates with AAPCS-VFP.
5874 if (IsEffectivelyAAPCS_VFP) {
5875 const Type *Base = nullptr;
5876 uint64_t Members = 0;
5877 if (isHomogeneousAggregate(RetTy, Base, Members)) {
5878 assert(Base && "Base class should be set for homogeneous aggregate");
5879 // Homogeneous Aggregates are returned directly.
5880 return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
5884 // Aggregates <= 4 bytes are returned in r0; other aggregates
5885 // are returned indirectly.
5886 uint64_t Size = getContext().getTypeSize(RetTy);
5888 // On RenderScript, coerce Aggregates <= 4 bytes to an integer array of
5889 // same size and alignment.
5890 if (getTarget().isRenderScriptTarget()) {
5891 return coerceToIntArray(RetTy, getContext(), getVMContext());
5893 if (getDataLayout().isBigEndian())
5894 // Return in 32 bit integer integer type (as if loaded by LDR, AAPCS 5.4)
5895 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
5897 // Return in the smallest viable integer type.
5899 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
5901 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
5902 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
5903 } else if (Size <= 128 && getABIKind() == AAPCS16_VFP) {
5904 llvm::Type *Int32Ty = llvm::Type::getInt32Ty(getVMContext());
5905 llvm::Type *CoerceTy =
5906 llvm::ArrayType::get(Int32Ty, llvm::alignTo(Size, 32) / 32);
5907 return ABIArgInfo::getDirect(CoerceTy);
5910 return getNaturalAlignIndirect(RetTy);
5913 /// isIllegalVector - check whether Ty is an illegal vector type.
5914 bool ARMABIInfo::isIllegalVectorType(QualType Ty) const {
5915 if (const VectorType *VT = Ty->getAs<VectorType> ()) {
5917 // Android shipped using Clang 3.1, which supported a slightly different
5918 // vector ABI. The primary differences were that 3-element vector types
5919 // were legal, and so were sub 32-bit vectors (i.e. <2 x i8>). This path
5920 // accepts that legacy behavior for Android only.
5921 // Check whether VT is legal.
5922 unsigned NumElements = VT->getNumElements();
5923 // NumElements should be power of 2 or equal to 3.
5924 if (!llvm::isPowerOf2_32(NumElements) && NumElements != 3)
5927 // Check whether VT is legal.
5928 unsigned NumElements = VT->getNumElements();
5929 uint64_t Size = getContext().getTypeSize(VT);
5930 // NumElements should be power of 2.
5931 if (!llvm::isPowerOf2_32(NumElements))
5933 // Size should be greater than 32 bits.
5940 bool ARMABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize,
5942 unsigned numElts) const {
5943 if (!llvm::isPowerOf2_32(numElts))
5945 unsigned size = getDataLayout().getTypeStoreSizeInBits(eltTy);
5948 if (vectorSize.getQuantity() != 8 &&
5949 (vectorSize.getQuantity() != 16 || numElts == 1))
5954 bool ARMABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
5955 // Homogeneous aggregates for AAPCS-VFP must have base types of float,
5956 // double, or 64-bit or 128-bit vectors.
5957 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
5958 if (BT->getKind() == BuiltinType::Float ||
5959 BT->getKind() == BuiltinType::Double ||
5960 BT->getKind() == BuiltinType::LongDouble)
5962 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
5963 unsigned VecSize = getContext().getTypeSize(VT);
5964 if (VecSize == 64 || VecSize == 128)
5970 bool ARMABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
5971 uint64_t Members) const {
5972 return Members <= 4;
5975 Address ARMABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5976 QualType Ty) const {
5977 CharUnits SlotSize = CharUnits::fromQuantity(4);
5979 // Empty records are ignored for parameter passing purposes.
5980 if (isEmptyRecord(getContext(), Ty, true)) {
5981 Address Addr(CGF.Builder.CreateLoad(VAListAddr), SlotSize);
5982 Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
5986 auto TyInfo = getContext().getTypeInfoInChars(Ty);
5987 CharUnits TyAlignForABI = TyInfo.second;
5989 // Use indirect if size of the illegal vector is bigger than 16 bytes.
5990 bool IsIndirect = false;
5991 const Type *Base = nullptr;
5992 uint64_t Members = 0;
5993 if (TyInfo.first > CharUnits::fromQuantity(16) && isIllegalVectorType(Ty)) {
5996 // ARMv7k passes structs bigger than 16 bytes indirectly, in space
5997 // allocated by the caller.
5998 } else if (TyInfo.first > CharUnits::fromQuantity(16) &&
5999 getABIKind() == ARMABIInfo::AAPCS16_VFP &&
6000 !isHomogeneousAggregate(Ty, Base, Members)) {
6003 // Otherwise, bound the type's ABI alignment.
6004 // The ABI alignment for 64-bit or 128-bit vectors is 8 for AAPCS and 4 for
6005 // APCS. For AAPCS, the ABI alignment is at least 4-byte and at most 8-byte.
6006 // Our callers should be prepared to handle an under-aligned address.
6007 } else if (getABIKind() == ARMABIInfo::AAPCS_VFP ||
6008 getABIKind() == ARMABIInfo::AAPCS) {
6009 TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
6010 TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(8));
6011 } else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) {
6012 // ARMv7k allows type alignment up to 16 bytes.
6013 TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
6014 TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(16));
6016 TyAlignForABI = CharUnits::fromQuantity(4);
6018 TyInfo.second = TyAlignForABI;
6020 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, TyInfo,
6021 SlotSize, /*AllowHigherAlign*/ true);
6024 //===----------------------------------------------------------------------===//
6025 // NVPTX ABI Implementation
6026 //===----------------------------------------------------------------------===//
6030 class NVPTXABIInfo : public ABIInfo {
6032 NVPTXABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
6034 ABIArgInfo classifyReturnType(QualType RetTy) const;
6035 ABIArgInfo classifyArgumentType(QualType Ty) const;
6037 void computeInfo(CGFunctionInfo &FI) const override;
6038 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6039 QualType Ty) const override;
6042 class NVPTXTargetCodeGenInfo : public TargetCodeGenInfo {
6044 NVPTXTargetCodeGenInfo(CodeGenTypes &CGT)
6045 : TargetCodeGenInfo(new NVPTXABIInfo(CGT)) {}
6047 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6048 CodeGen::CodeGenModule &M) const override;
6050 // Adds a NamedMDNode with F, Name, and Operand as operands, and adds the
6051 // resulting MDNode to the nvvm.annotations MDNode.
6052 static void addNVVMMetadata(llvm::Function *F, StringRef Name, int Operand);
6055 ABIArgInfo NVPTXABIInfo::classifyReturnType(QualType RetTy) const {
6056 if (RetTy->isVoidType())
6057 return ABIArgInfo::getIgnore();
6059 // note: this is different from default ABI
6060 if (!RetTy->isScalarType())
6061 return ABIArgInfo::getDirect();
6063 // Treat an enum type as its underlying type.
6064 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
6065 RetTy = EnumTy->getDecl()->getIntegerType();
6067 return (RetTy->isPromotableIntegerType() ?
6068 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6071 ABIArgInfo NVPTXABIInfo::classifyArgumentType(QualType Ty) const {
6072 // Treat an enum type as its underlying type.
6073 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6074 Ty = EnumTy->getDecl()->getIntegerType();
6076 // Return aggregates type as indirect by value
6077 if (isAggregateTypeForABI(Ty))
6078 return getNaturalAlignIndirect(Ty, /* byval */ true);
6080 return (Ty->isPromotableIntegerType() ?
6081 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6084 void NVPTXABIInfo::computeInfo(CGFunctionInfo &FI) const {
6085 if (!getCXXABI().classifyReturnType(FI))
6086 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
6087 for (auto &I : FI.arguments())
6088 I.info = classifyArgumentType(I.type);
6090 // Always honor user-specified calling convention.
6091 if (FI.getCallingConvention() != llvm::CallingConv::C)
6094 FI.setEffectiveCallingConvention(getRuntimeCC());
6097 Address NVPTXABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6098 QualType Ty) const {
6099 llvm_unreachable("NVPTX does not support varargs");
6102 void NVPTXTargetCodeGenInfo::
6103 setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6104 CodeGen::CodeGenModule &M) const{
6105 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
6108 llvm::Function *F = cast<llvm::Function>(GV);
6110 // Perform special handling in OpenCL mode
6111 if (M.getLangOpts().OpenCL) {
6112 // Use OpenCL function attributes to check for kernel functions
6113 // By default, all functions are device functions
6114 if (FD->hasAttr<OpenCLKernelAttr>()) {
6115 // OpenCL __kernel functions get kernel metadata
6116 // Create !{<func-ref>, metadata !"kernel", i32 1} node
6117 addNVVMMetadata(F, "kernel", 1);
6118 // And kernel functions are not subject to inlining
6119 F->addFnAttr(llvm::Attribute::NoInline);
6123 // Perform special handling in CUDA mode.
6124 if (M.getLangOpts().CUDA) {
6125 // CUDA __global__ functions get a kernel metadata entry. Since
6126 // __global__ functions cannot be called from the device, we do not
6127 // need to set the noinline attribute.
6128 if (FD->hasAttr<CUDAGlobalAttr>()) {
6129 // Create !{<func-ref>, metadata !"kernel", i32 1} node
6130 addNVVMMetadata(F, "kernel", 1);
6132 if (CUDALaunchBoundsAttr *Attr = FD->getAttr<CUDALaunchBoundsAttr>()) {
6133 // Create !{<func-ref>, metadata !"maxntidx", i32 <val>} node
6134 llvm::APSInt MaxThreads(32);
6135 MaxThreads = Attr->getMaxThreads()->EvaluateKnownConstInt(M.getContext());
6137 addNVVMMetadata(F, "maxntidx", MaxThreads.getExtValue());
6139 // min blocks is an optional argument for CUDALaunchBoundsAttr. If it was
6140 // not specified in __launch_bounds__ or if the user specified a 0 value,
6141 // we don't have to add a PTX directive.
6142 if (Attr->getMinBlocks()) {
6143 llvm::APSInt MinBlocks(32);
6144 MinBlocks = Attr->getMinBlocks()->EvaluateKnownConstInt(M.getContext());
6146 // Create !{<func-ref>, metadata !"minctasm", i32 <val>} node
6147 addNVVMMetadata(F, "minctasm", MinBlocks.getExtValue());
6153 void NVPTXTargetCodeGenInfo::addNVVMMetadata(llvm::Function *F, StringRef Name,
6155 llvm::Module *M = F->getParent();
6156 llvm::LLVMContext &Ctx = M->getContext();
6158 // Get "nvvm.annotations" metadata node
6159 llvm::NamedMDNode *MD = M->getOrInsertNamedMetadata("nvvm.annotations");
6161 llvm::Metadata *MDVals[] = {
6162 llvm::ConstantAsMetadata::get(F), llvm::MDString::get(Ctx, Name),
6163 llvm::ConstantAsMetadata::get(
6164 llvm::ConstantInt::get(llvm::Type::getInt32Ty(Ctx), Operand))};
6165 // Append metadata to nvvm.annotations
6166 MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
6170 //===----------------------------------------------------------------------===//
6171 // SystemZ ABI Implementation
6172 //===----------------------------------------------------------------------===//
6176 class SystemZABIInfo : public SwiftABIInfo {
6180 SystemZABIInfo(CodeGenTypes &CGT, bool HV)
6181 : SwiftABIInfo(CGT), HasVector(HV) {}
6183 bool isPromotableIntegerType(QualType Ty) const;
6184 bool isCompoundType(QualType Ty) const;
6185 bool isVectorArgumentType(QualType Ty) const;
6186 bool isFPArgumentType(QualType Ty) const;
6187 QualType GetSingleElementType(QualType Ty) const;
6189 ABIArgInfo classifyReturnType(QualType RetTy) const;
6190 ABIArgInfo classifyArgumentType(QualType ArgTy) const;
6192 void computeInfo(CGFunctionInfo &FI) const override {
6193 if (!getCXXABI().classifyReturnType(FI))
6194 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
6195 for (auto &I : FI.arguments())
6196 I.info = classifyArgumentType(I.type);
6199 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6200 QualType Ty) const override;
6202 bool shouldPassIndirectlyForSwift(CharUnits totalSize,
6203 ArrayRef<llvm::Type*> scalars,
6204 bool asReturnValue) const override {
6205 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
6207 bool isSwiftErrorInRegister() const override {
6212 class SystemZTargetCodeGenInfo : public TargetCodeGenInfo {
6214 SystemZTargetCodeGenInfo(CodeGenTypes &CGT, bool HasVector)
6215 : TargetCodeGenInfo(new SystemZABIInfo(CGT, HasVector)) {}
6220 bool SystemZABIInfo::isPromotableIntegerType(QualType Ty) const {
6221 // Treat an enum type as its underlying type.
6222 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6223 Ty = EnumTy->getDecl()->getIntegerType();
6225 // Promotable integer types are required to be promoted by the ABI.
6226 if (Ty->isPromotableIntegerType())
6229 // 32-bit values must also be promoted.
6230 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
6231 switch (BT->getKind()) {
6232 case BuiltinType::Int:
6233 case BuiltinType::UInt:
6241 bool SystemZABIInfo::isCompoundType(QualType Ty) const {
6242 return (Ty->isAnyComplexType() ||
6243 Ty->isVectorType() ||
6244 isAggregateTypeForABI(Ty));
6247 bool SystemZABIInfo::isVectorArgumentType(QualType Ty) const {
6248 return (HasVector &&
6249 Ty->isVectorType() &&
6250 getContext().getTypeSize(Ty) <= 128);
6253 bool SystemZABIInfo::isFPArgumentType(QualType Ty) const {
6254 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
6255 switch (BT->getKind()) {
6256 case BuiltinType::Float:
6257 case BuiltinType::Double:
6266 QualType SystemZABIInfo::GetSingleElementType(QualType Ty) const {
6267 if (const RecordType *RT = Ty->getAsStructureType()) {
6268 const RecordDecl *RD = RT->getDecl();
6271 // If this is a C++ record, check the bases first.
6272 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
6273 for (const auto &I : CXXRD->bases()) {
6274 QualType Base = I.getType();
6276 // Empty bases don't affect things either way.
6277 if (isEmptyRecord(getContext(), Base, true))
6280 if (!Found.isNull())
6282 Found = GetSingleElementType(Base);
6285 // Check the fields.
6286 for (const auto *FD : RD->fields()) {
6287 // For compatibility with GCC, ignore empty bitfields in C++ mode.
6288 // Unlike isSingleElementStruct(), empty structure and array fields
6289 // do count. So do anonymous bitfields that aren't zero-sized.
6290 if (getContext().getLangOpts().CPlusPlus &&
6291 FD->isBitField() && FD->getBitWidthValue(getContext()) == 0)
6294 // Unlike isSingleElementStruct(), arrays do not count.
6295 // Nested structures still do though.
6296 if (!Found.isNull())
6298 Found = GetSingleElementType(FD->getType());
6301 // Unlike isSingleElementStruct(), trailing padding is allowed.
6302 // An 8-byte aligned struct s { float f; } is passed as a double.
6303 if (!Found.isNull())
6310 Address SystemZABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6311 QualType Ty) const {
6312 // Assume that va_list type is correct; should be pointer to LLVM type:
6316 // i8 *__overflow_arg_area;
6317 // i8 *__reg_save_area;
6320 // Every non-vector argument occupies 8 bytes and is passed by preference
6321 // in either GPRs or FPRs. Vector arguments occupy 8 or 16 bytes and are
6322 // always passed on the stack.
6323 Ty = getContext().getCanonicalType(Ty);
6324 auto TyInfo = getContext().getTypeInfoInChars(Ty);
6325 llvm::Type *ArgTy = CGF.ConvertTypeForMem(Ty);
6326 llvm::Type *DirectTy = ArgTy;
6327 ABIArgInfo AI = classifyArgumentType(Ty);
6328 bool IsIndirect = AI.isIndirect();
6329 bool InFPRs = false;
6330 bool IsVector = false;
6331 CharUnits UnpaddedSize;
6332 CharUnits DirectAlign;
6334 DirectTy = llvm::PointerType::getUnqual(DirectTy);
6335 UnpaddedSize = DirectAlign = CharUnits::fromQuantity(8);
6337 if (AI.getCoerceToType())
6338 ArgTy = AI.getCoerceToType();
6339 InFPRs = ArgTy->isFloatTy() || ArgTy->isDoubleTy();
6340 IsVector = ArgTy->isVectorTy();
6341 UnpaddedSize = TyInfo.first;
6342 DirectAlign = TyInfo.second;
6344 CharUnits PaddedSize = CharUnits::fromQuantity(8);
6345 if (IsVector && UnpaddedSize > PaddedSize)
6346 PaddedSize = CharUnits::fromQuantity(16);
6347 assert((UnpaddedSize <= PaddedSize) && "Invalid argument size.");
6349 CharUnits Padding = (PaddedSize - UnpaddedSize);
6351 llvm::Type *IndexTy = CGF.Int64Ty;
6352 llvm::Value *PaddedSizeV =
6353 llvm::ConstantInt::get(IndexTy, PaddedSize.getQuantity());
6356 // Work out the address of a vector argument on the stack.
6357 // Vector arguments are always passed in the high bits of a
6358 // single (8 byte) or double (16 byte) stack slot.
6359 Address OverflowArgAreaPtr =
6360 CGF.Builder.CreateStructGEP(VAListAddr, 2, CharUnits::fromQuantity(16),
6361 "overflow_arg_area_ptr");
6362 Address OverflowArgArea =
6363 Address(CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"),
6366 CGF.Builder.CreateElementBitCast(OverflowArgArea, DirectTy, "mem_addr");
6368 // Update overflow_arg_area_ptr pointer
6369 llvm::Value *NewOverflowArgArea =
6370 CGF.Builder.CreateGEP(OverflowArgArea.getPointer(), PaddedSizeV,
6371 "overflow_arg_area");
6372 CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
6377 assert(PaddedSize.getQuantity() == 8);
6379 unsigned MaxRegs, RegCountField, RegSaveIndex;
6380 CharUnits RegPadding;
6382 MaxRegs = 4; // Maximum of 4 FPR arguments
6383 RegCountField = 1; // __fpr
6384 RegSaveIndex = 16; // save offset for f0
6385 RegPadding = CharUnits(); // floats are passed in the high bits of an FPR
6387 MaxRegs = 5; // Maximum of 5 GPR arguments
6388 RegCountField = 0; // __gpr
6389 RegSaveIndex = 2; // save offset for r2
6390 RegPadding = Padding; // values are passed in the low bits of a GPR
6393 Address RegCountPtr = CGF.Builder.CreateStructGEP(
6394 VAListAddr, RegCountField, RegCountField * CharUnits::fromQuantity(8),
6396 llvm::Value *RegCount = CGF.Builder.CreateLoad(RegCountPtr, "reg_count");
6397 llvm::Value *MaxRegsV = llvm::ConstantInt::get(IndexTy, MaxRegs);
6398 llvm::Value *InRegs = CGF.Builder.CreateICmpULT(RegCount, MaxRegsV,
6401 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
6402 llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
6403 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
6404 CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
6406 // Emit code to load the value if it was passed in registers.
6407 CGF.EmitBlock(InRegBlock);
6409 // Work out the address of an argument register.
6410 llvm::Value *ScaledRegCount =
6411 CGF.Builder.CreateMul(RegCount, PaddedSizeV, "scaled_reg_count");
6412 llvm::Value *RegBase =
6413 llvm::ConstantInt::get(IndexTy, RegSaveIndex * PaddedSize.getQuantity()
6414 + RegPadding.getQuantity());
6415 llvm::Value *RegOffset =
6416 CGF.Builder.CreateAdd(ScaledRegCount, RegBase, "reg_offset");
6417 Address RegSaveAreaPtr =
6418 CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(24),
6419 "reg_save_area_ptr");
6420 llvm::Value *RegSaveArea =
6421 CGF.Builder.CreateLoad(RegSaveAreaPtr, "reg_save_area");
6422 Address RawRegAddr(CGF.Builder.CreateGEP(RegSaveArea, RegOffset,
6426 CGF.Builder.CreateElementBitCast(RawRegAddr, DirectTy, "reg_addr");
6428 // Update the register count
6429 llvm::Value *One = llvm::ConstantInt::get(IndexTy, 1);
6430 llvm::Value *NewRegCount =
6431 CGF.Builder.CreateAdd(RegCount, One, "reg_count");
6432 CGF.Builder.CreateStore(NewRegCount, RegCountPtr);
6433 CGF.EmitBranch(ContBlock);
6435 // Emit code to load the value if it was passed in memory.
6436 CGF.EmitBlock(InMemBlock);
6438 // Work out the address of a stack argument.
6439 Address OverflowArgAreaPtr = CGF.Builder.CreateStructGEP(
6440 VAListAddr, 2, CharUnits::fromQuantity(16), "overflow_arg_area_ptr");
6441 Address OverflowArgArea =
6442 Address(CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"),
6444 Address RawMemAddr =
6445 CGF.Builder.CreateConstByteGEP(OverflowArgArea, Padding, "raw_mem_addr");
6447 CGF.Builder.CreateElementBitCast(RawMemAddr, DirectTy, "mem_addr");
6449 // Update overflow_arg_area_ptr pointer
6450 llvm::Value *NewOverflowArgArea =
6451 CGF.Builder.CreateGEP(OverflowArgArea.getPointer(), PaddedSizeV,
6452 "overflow_arg_area");
6453 CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
6454 CGF.EmitBranch(ContBlock);
6456 // Return the appropriate result.
6457 CGF.EmitBlock(ContBlock);
6458 Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
6459 MemAddr, InMemBlock, "va_arg.addr");
6462 ResAddr = Address(CGF.Builder.CreateLoad(ResAddr, "indirect_arg"),
6468 ABIArgInfo SystemZABIInfo::classifyReturnType(QualType RetTy) const {
6469 if (RetTy->isVoidType())
6470 return ABIArgInfo::getIgnore();
6471 if (isVectorArgumentType(RetTy))
6472 return ABIArgInfo::getDirect();
6473 if (isCompoundType(RetTy) || getContext().getTypeSize(RetTy) > 64)
6474 return getNaturalAlignIndirect(RetTy);
6475 return (isPromotableIntegerType(RetTy) ?
6476 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6479 ABIArgInfo SystemZABIInfo::classifyArgumentType(QualType Ty) const {
6480 // Handle the generic C++ ABI.
6481 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
6482 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
6484 // Integers and enums are extended to full register width.
6485 if (isPromotableIntegerType(Ty))
6486 return ABIArgInfo::getExtend();
6488 // Handle vector types and vector-like structure types. Note that
6489 // as opposed to float-like structure types, we do not allow any
6490 // padding for vector-like structures, so verify the sizes match.
6491 uint64_t Size = getContext().getTypeSize(Ty);
6492 QualType SingleElementTy = GetSingleElementType(Ty);
6493 if (isVectorArgumentType(SingleElementTy) &&
6494 getContext().getTypeSize(SingleElementTy) == Size)
6495 return ABIArgInfo::getDirect(CGT.ConvertType(SingleElementTy));
6497 // Values that are not 1, 2, 4 or 8 bytes in size are passed indirectly.
6498 if (Size != 8 && Size != 16 && Size != 32 && Size != 64)
6499 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6501 // Handle small structures.
6502 if (const RecordType *RT = Ty->getAs<RecordType>()) {
6503 // Structures with flexible arrays have variable length, so really
6504 // fail the size test above.
6505 const RecordDecl *RD = RT->getDecl();
6506 if (RD->hasFlexibleArrayMember())
6507 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6509 // The structure is passed as an unextended integer, a float, or a double.
6511 if (isFPArgumentType(SingleElementTy)) {
6512 assert(Size == 32 || Size == 64);
6514 PassTy = llvm::Type::getFloatTy(getVMContext());
6516 PassTy = llvm::Type::getDoubleTy(getVMContext());
6518 PassTy = llvm::IntegerType::get(getVMContext(), Size);
6519 return ABIArgInfo::getDirect(PassTy);
6522 // Non-structure compounds are passed indirectly.
6523 if (isCompoundType(Ty))
6524 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6526 return ABIArgInfo::getDirect(nullptr);
6529 //===----------------------------------------------------------------------===//
6530 // MSP430 ABI Implementation
6531 //===----------------------------------------------------------------------===//
6535 class MSP430TargetCodeGenInfo : public TargetCodeGenInfo {
6537 MSP430TargetCodeGenInfo(CodeGenTypes &CGT)
6538 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
6539 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6540 CodeGen::CodeGenModule &M) const override;
6545 void MSP430TargetCodeGenInfo::setTargetAttributes(const Decl *D,
6546 llvm::GlobalValue *GV,
6547 CodeGen::CodeGenModule &M) const {
6548 if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
6549 if (const MSP430InterruptAttr *attr = FD->getAttr<MSP430InterruptAttr>()) {
6550 // Handle 'interrupt' attribute:
6551 llvm::Function *F = cast<llvm::Function>(GV);
6553 // Step 1: Set ISR calling convention.
6554 F->setCallingConv(llvm::CallingConv::MSP430_INTR);
6556 // Step 2: Add attributes goodness.
6557 F->addFnAttr(llvm::Attribute::NoInline);
6559 // Step 3: Emit ISR vector alias.
6560 unsigned Num = attr->getNumber() / 2;
6561 llvm::GlobalAlias::create(llvm::Function::ExternalLinkage,
6562 "__isr_" + Twine(Num), F);
6567 //===----------------------------------------------------------------------===//
6568 // MIPS ABI Implementation. This works for both little-endian and
6569 // big-endian variants.
6570 //===----------------------------------------------------------------------===//
6573 class MipsABIInfo : public ABIInfo {
6575 unsigned MinABIStackAlignInBytes, StackAlignInBytes;
6576 void CoerceToIntArgs(uint64_t TySize,
6577 SmallVectorImpl<llvm::Type *> &ArgList) const;
6578 llvm::Type* HandleAggregates(QualType Ty, uint64_t TySize) const;
6579 llvm::Type* returnAggregateInRegs(QualType RetTy, uint64_t Size) const;
6580 llvm::Type* getPaddingType(uint64_t Align, uint64_t Offset) const;
6582 MipsABIInfo(CodeGenTypes &CGT, bool _IsO32) :
6583 ABIInfo(CGT), IsO32(_IsO32), MinABIStackAlignInBytes(IsO32 ? 4 : 8),
6584 StackAlignInBytes(IsO32 ? 8 : 16) {}
6586 ABIArgInfo classifyReturnType(QualType RetTy) const;
6587 ABIArgInfo classifyArgumentType(QualType RetTy, uint64_t &Offset) const;
6588 void computeInfo(CGFunctionInfo &FI) const override;
6589 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6590 QualType Ty) const override;
6591 bool shouldSignExtUnsignedType(QualType Ty) const override;
6594 class MIPSTargetCodeGenInfo : public TargetCodeGenInfo {
6595 unsigned SizeOfUnwindException;
6597 MIPSTargetCodeGenInfo(CodeGenTypes &CGT, bool IsO32)
6598 : TargetCodeGenInfo(new MipsABIInfo(CGT, IsO32)),
6599 SizeOfUnwindException(IsO32 ? 24 : 32) {}
6601 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
6605 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6606 CodeGen::CodeGenModule &CGM) const override {
6607 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
6609 llvm::Function *Fn = cast<llvm::Function>(GV);
6610 if (FD->hasAttr<Mips16Attr>()) {
6611 Fn->addFnAttr("mips16");
6613 else if (FD->hasAttr<NoMips16Attr>()) {
6614 Fn->addFnAttr("nomips16");
6617 if (FD->hasAttr<MicroMipsAttr>())
6618 Fn->addFnAttr("micromips");
6619 else if (FD->hasAttr<NoMicroMipsAttr>())
6620 Fn->addFnAttr("nomicromips");
6622 const MipsInterruptAttr *Attr = FD->getAttr<MipsInterruptAttr>();
6627 switch (Attr->getInterrupt()) {
6628 case MipsInterruptAttr::eic: Kind = "eic"; break;
6629 case MipsInterruptAttr::sw0: Kind = "sw0"; break;
6630 case MipsInterruptAttr::sw1: Kind = "sw1"; break;
6631 case MipsInterruptAttr::hw0: Kind = "hw0"; break;
6632 case MipsInterruptAttr::hw1: Kind = "hw1"; break;
6633 case MipsInterruptAttr::hw2: Kind = "hw2"; break;
6634 case MipsInterruptAttr::hw3: Kind = "hw3"; break;
6635 case MipsInterruptAttr::hw4: Kind = "hw4"; break;
6636 case MipsInterruptAttr::hw5: Kind = "hw5"; break;
6639 Fn->addFnAttr("interrupt", Kind);
6643 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
6644 llvm::Value *Address) const override;
6646 unsigned getSizeOfUnwindException() const override {
6647 return SizeOfUnwindException;
6652 void MipsABIInfo::CoerceToIntArgs(
6653 uint64_t TySize, SmallVectorImpl<llvm::Type *> &ArgList) const {
6654 llvm::IntegerType *IntTy =
6655 llvm::IntegerType::get(getVMContext(), MinABIStackAlignInBytes * 8);
6657 // Add (TySize / MinABIStackAlignInBytes) args of IntTy.
6658 for (unsigned N = TySize / (MinABIStackAlignInBytes * 8); N; --N)
6659 ArgList.push_back(IntTy);
6661 // If necessary, add one more integer type to ArgList.
6662 unsigned R = TySize % (MinABIStackAlignInBytes * 8);
6665 ArgList.push_back(llvm::IntegerType::get(getVMContext(), R));
6668 // In N32/64, an aligned double precision floating point field is passed in
6670 llvm::Type* MipsABIInfo::HandleAggregates(QualType Ty, uint64_t TySize) const {
6671 SmallVector<llvm::Type*, 8> ArgList, IntArgList;
6674 CoerceToIntArgs(TySize, ArgList);
6675 return llvm::StructType::get(getVMContext(), ArgList);
6678 if (Ty->isComplexType())
6679 return CGT.ConvertType(Ty);
6681 const RecordType *RT = Ty->getAs<RecordType>();
6683 // Unions/vectors are passed in integer registers.
6684 if (!RT || !RT->isStructureOrClassType()) {
6685 CoerceToIntArgs(TySize, ArgList);
6686 return llvm::StructType::get(getVMContext(), ArgList);
6689 const RecordDecl *RD = RT->getDecl();
6690 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
6691 assert(!(TySize % 8) && "Size of structure must be multiple of 8.");
6693 uint64_t LastOffset = 0;
6695 llvm::IntegerType *I64 = llvm::IntegerType::get(getVMContext(), 64);
6697 // Iterate over fields in the struct/class and check if there are any aligned
6699 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
6700 i != e; ++i, ++idx) {
6701 const QualType Ty = i->getType();
6702 const BuiltinType *BT = Ty->getAs<BuiltinType>();
6704 if (!BT || BT->getKind() != BuiltinType::Double)
6707 uint64_t Offset = Layout.getFieldOffset(idx);
6708 if (Offset % 64) // Ignore doubles that are not aligned.
6711 // Add ((Offset - LastOffset) / 64) args of type i64.
6712 for (unsigned j = (Offset - LastOffset) / 64; j > 0; --j)
6713 ArgList.push_back(I64);
6716 ArgList.push_back(llvm::Type::getDoubleTy(getVMContext()));
6717 LastOffset = Offset + 64;
6720 CoerceToIntArgs(TySize - LastOffset, IntArgList);
6721 ArgList.append(IntArgList.begin(), IntArgList.end());
6723 return llvm::StructType::get(getVMContext(), ArgList);
6726 llvm::Type *MipsABIInfo::getPaddingType(uint64_t OrigOffset,
6727 uint64_t Offset) const {
6728 if (OrigOffset + MinABIStackAlignInBytes > Offset)
6731 return llvm::IntegerType::get(getVMContext(), (Offset - OrigOffset) * 8);
6735 MipsABIInfo::classifyArgumentType(QualType Ty, uint64_t &Offset) const {
6736 Ty = useFirstFieldIfTransparentUnion(Ty);
6738 uint64_t OrigOffset = Offset;
6739 uint64_t TySize = getContext().getTypeSize(Ty);
6740 uint64_t Align = getContext().getTypeAlign(Ty) / 8;
6742 Align = std::min(std::max(Align, (uint64_t)MinABIStackAlignInBytes),
6743 (uint64_t)StackAlignInBytes);
6744 unsigned CurrOffset = llvm::alignTo(Offset, Align);
6745 Offset = CurrOffset + llvm::alignTo(TySize, Align * 8) / 8;
6747 if (isAggregateTypeForABI(Ty) || Ty->isVectorType()) {
6748 // Ignore empty aggregates.
6750 return ABIArgInfo::getIgnore();
6752 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
6753 Offset = OrigOffset + MinABIStackAlignInBytes;
6754 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
6757 // Use indirect if the aggregate cannot fit into registers for
6758 // passing arguments according to the ABI
6759 unsigned Threshold = IsO32 ? 16 : 64;
6761 if(getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(Threshold))
6762 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align), true,
6763 getContext().getTypeAlign(Ty) / 8 > Align);
6765 // If we have reached here, aggregates are passed directly by coercing to
6766 // another structure type. Padding is inserted if the offset of the
6767 // aggregate is unaligned.
6768 ABIArgInfo ArgInfo =
6769 ABIArgInfo::getDirect(HandleAggregates(Ty, TySize), 0,
6770 getPaddingType(OrigOffset, CurrOffset));
6771 ArgInfo.setInReg(true);
6775 // Treat an enum type as its underlying type.
6776 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6777 Ty = EnumTy->getDecl()->getIntegerType();
6779 // All integral types are promoted to the GPR width.
6780 if (Ty->isIntegralOrEnumerationType())
6781 return ABIArgInfo::getExtend();
6783 return ABIArgInfo::getDirect(
6784 nullptr, 0, IsO32 ? nullptr : getPaddingType(OrigOffset, CurrOffset));
6788 MipsABIInfo::returnAggregateInRegs(QualType RetTy, uint64_t Size) const {
6789 const RecordType *RT = RetTy->getAs<RecordType>();
6790 SmallVector<llvm::Type*, 8> RTList;
6792 if (RT && RT->isStructureOrClassType()) {
6793 const RecordDecl *RD = RT->getDecl();
6794 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
6795 unsigned FieldCnt = Layout.getFieldCount();
6797 // N32/64 returns struct/classes in floating point registers if the
6798 // following conditions are met:
6799 // 1. The size of the struct/class is no larger than 128-bit.
6800 // 2. The struct/class has one or two fields all of which are floating
6802 // 3. The offset of the first field is zero (this follows what gcc does).
6804 // Any other composite results are returned in integer registers.
6806 if (FieldCnt && (FieldCnt <= 2) && !Layout.getFieldOffset(0)) {
6807 RecordDecl::field_iterator b = RD->field_begin(), e = RD->field_end();
6808 for (; b != e; ++b) {
6809 const BuiltinType *BT = b->getType()->getAs<BuiltinType>();
6811 if (!BT || !BT->isFloatingPoint())
6814 RTList.push_back(CGT.ConvertType(b->getType()));
6818 return llvm::StructType::get(getVMContext(), RTList,
6819 RD->hasAttr<PackedAttr>());
6825 CoerceToIntArgs(Size, RTList);
6826 return llvm::StructType::get(getVMContext(), RTList);
6829 ABIArgInfo MipsABIInfo::classifyReturnType(QualType RetTy) const {
6830 uint64_t Size = getContext().getTypeSize(RetTy);
6832 if (RetTy->isVoidType())
6833 return ABIArgInfo::getIgnore();
6835 // O32 doesn't treat zero-sized structs differently from other structs.
6836 // However, N32/N64 ignores zero sized return values.
6837 if (!IsO32 && Size == 0)
6838 return ABIArgInfo::getIgnore();
6840 if (isAggregateTypeForABI(RetTy) || RetTy->isVectorType()) {
6842 if (RetTy->isAnyComplexType())
6843 return ABIArgInfo::getDirect();
6845 // O32 returns integer vectors in registers and N32/N64 returns all small
6846 // aggregates in registers.
6848 (RetTy->isVectorType() && !RetTy->hasFloatingRepresentation())) {
6849 ABIArgInfo ArgInfo =
6850 ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size));
6851 ArgInfo.setInReg(true);
6856 return getNaturalAlignIndirect(RetTy);
6859 // Treat an enum type as its underlying type.
6860 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
6861 RetTy = EnumTy->getDecl()->getIntegerType();
6863 return (RetTy->isPromotableIntegerType() ?
6864 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6867 void MipsABIInfo::computeInfo(CGFunctionInfo &FI) const {
6868 ABIArgInfo &RetInfo = FI.getReturnInfo();
6869 if (!getCXXABI().classifyReturnType(FI))
6870 RetInfo = classifyReturnType(FI.getReturnType());
6872 // Check if a pointer to an aggregate is passed as a hidden argument.
6873 uint64_t Offset = RetInfo.isIndirect() ? MinABIStackAlignInBytes : 0;
6875 for (auto &I : FI.arguments())
6876 I.info = classifyArgumentType(I.type, Offset);
6879 Address MipsABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6880 QualType OrigTy) const {
6881 QualType Ty = OrigTy;
6883 // Integer arguments are promoted to 32-bit on O32 and 64-bit on N32/N64.
6884 // Pointers are also promoted in the same way but this only matters for N32.
6885 unsigned SlotSizeInBits = IsO32 ? 32 : 64;
6886 unsigned PtrWidth = getTarget().getPointerWidth(0);
6887 bool DidPromote = false;
6888 if ((Ty->isIntegerType() &&
6889 getContext().getIntWidth(Ty) < SlotSizeInBits) ||
6890 (Ty->isPointerType() && PtrWidth < SlotSizeInBits)) {
6892 Ty = getContext().getIntTypeForBitwidth(SlotSizeInBits,
6893 Ty->isSignedIntegerType());
6896 auto TyInfo = getContext().getTypeInfoInChars(Ty);
6898 // The alignment of things in the argument area is never larger than
6899 // StackAlignInBytes.
6901 std::min(TyInfo.second, CharUnits::fromQuantity(StackAlignInBytes));
6903 // MinABIStackAlignInBytes is the size of argument slots on the stack.
6904 CharUnits ArgSlotSize = CharUnits::fromQuantity(MinABIStackAlignInBytes);
6906 Address Addr = emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
6907 TyInfo, ArgSlotSize, /*AllowHigherAlign*/ true);
6910 // If there was a promotion, "unpromote" into a temporary.
6911 // TODO: can we just use a pointer into a subset of the original slot?
6913 Address Temp = CGF.CreateMemTemp(OrigTy, "vaarg.promotion-temp");
6914 llvm::Value *Promoted = CGF.Builder.CreateLoad(Addr);
6916 // Truncate down to the right width.
6917 llvm::Type *IntTy = (OrigTy->isIntegerType() ? Temp.getElementType()
6919 llvm::Value *V = CGF.Builder.CreateTrunc(Promoted, IntTy);
6920 if (OrigTy->isPointerType())
6921 V = CGF.Builder.CreateIntToPtr(V, Temp.getElementType());
6923 CGF.Builder.CreateStore(V, Temp);
6930 bool MipsABIInfo::shouldSignExtUnsignedType(QualType Ty) const {
6931 int TySize = getContext().getTypeSize(Ty);
6933 // MIPS64 ABI requires unsigned 32 bit integers to be sign extended.
6934 if (Ty->isUnsignedIntegerOrEnumerationType() && TySize == 32)
6941 MIPSTargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
6942 llvm::Value *Address) const {
6943 // This information comes from gcc's implementation, which seems to
6944 // as canonical as it gets.
6946 // Everything on MIPS is 4 bytes. Double-precision FP registers
6947 // are aliased to pairs of single-precision FP registers.
6948 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
6950 // 0-31 are the general purpose registers, $0 - $31.
6951 // 32-63 are the floating-point registers, $f0 - $f31.
6952 // 64 and 65 are the multiply/divide registers, $hi and $lo.
6953 // 66 is the (notional, I think) register for signal-handler return.
6954 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 65);
6956 // 67-74 are the floating-point status registers, $fcc0 - $fcc7.
6957 // They are one bit wide and ignored here.
6959 // 80-111 are the coprocessor 0 registers, $c0r0 - $c0r31.
6960 // (coprocessor 1 is the FP unit)
6961 // 112-143 are the coprocessor 2 registers, $c2r0 - $c2r31.
6962 // 144-175 are the coprocessor 3 registers, $c3r0 - $c3r31.
6963 // 176-181 are the DSP accumulator registers.
6964 AssignToArrayRange(CGF.Builder, Address, Four8, 80, 181);
6968 //===----------------------------------------------------------------------===//
6969 // AVR ABI Implementation.
6970 //===----------------------------------------------------------------------===//
6973 class AVRTargetCodeGenInfo : public TargetCodeGenInfo {
6975 AVRTargetCodeGenInfo(CodeGenTypes &CGT)
6976 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) { }
6978 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6979 CodeGen::CodeGenModule &CGM) const override {
6980 const auto *FD = dyn_cast_or_null<FunctionDecl>(D);
6982 auto *Fn = cast<llvm::Function>(GV);
6984 if (FD->getAttr<AVRInterruptAttr>())
6985 Fn->addFnAttr("interrupt");
6987 if (FD->getAttr<AVRSignalAttr>())
6988 Fn->addFnAttr("signal");
6993 //===----------------------------------------------------------------------===//
6994 // TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults.
6995 // Currently subclassed only to implement custom OpenCL C function attribute
6997 //===----------------------------------------------------------------------===//
7001 class TCETargetCodeGenInfo : public DefaultTargetCodeGenInfo {
7003 TCETargetCodeGenInfo(CodeGenTypes &CGT)
7004 : DefaultTargetCodeGenInfo(CGT) {}
7006 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
7007 CodeGen::CodeGenModule &M) const override;
7010 void TCETargetCodeGenInfo::setTargetAttributes(
7011 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
7012 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
7015 llvm::Function *F = cast<llvm::Function>(GV);
7017 if (M.getLangOpts().OpenCL) {
7018 if (FD->hasAttr<OpenCLKernelAttr>()) {
7019 // OpenCL C Kernel functions are not subject to inlining
7020 F->addFnAttr(llvm::Attribute::NoInline);
7021 const ReqdWorkGroupSizeAttr *Attr = FD->getAttr<ReqdWorkGroupSizeAttr>();
7023 // Convert the reqd_work_group_size() attributes to metadata.
7024 llvm::LLVMContext &Context = F->getContext();
7025 llvm::NamedMDNode *OpenCLMetadata =
7026 M.getModule().getOrInsertNamedMetadata(
7027 "opencl.kernel_wg_size_info");
7029 SmallVector<llvm::Metadata *, 5> Operands;
7030 Operands.push_back(llvm::ConstantAsMetadata::get(F));
7033 llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
7034 M.Int32Ty, llvm::APInt(32, Attr->getXDim()))));
7036 llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
7037 M.Int32Ty, llvm::APInt(32, Attr->getYDim()))));
7039 llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
7040 M.Int32Ty, llvm::APInt(32, Attr->getZDim()))));
7042 // Add a boolean constant operand for "required" (true) or "hint"
7043 // (false) for implementing the work_group_size_hint attr later.
7044 // Currently always true as the hint is not yet implemented.
7046 llvm::ConstantAsMetadata::get(llvm::ConstantInt::getTrue(Context)));
7047 OpenCLMetadata->addOperand(llvm::MDNode::get(Context, Operands));
7055 //===----------------------------------------------------------------------===//
7056 // Hexagon ABI Implementation
7057 //===----------------------------------------------------------------------===//
7061 class HexagonABIInfo : public ABIInfo {
7065 HexagonABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
7069 ABIArgInfo classifyReturnType(QualType RetTy) const;
7070 ABIArgInfo classifyArgumentType(QualType RetTy) const;
7072 void computeInfo(CGFunctionInfo &FI) const override;
7074 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7075 QualType Ty) const override;
7078 class HexagonTargetCodeGenInfo : public TargetCodeGenInfo {
7080 HexagonTargetCodeGenInfo(CodeGenTypes &CGT)
7081 :TargetCodeGenInfo(new HexagonABIInfo(CGT)) {}
7083 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
7090 void HexagonABIInfo::computeInfo(CGFunctionInfo &FI) const {
7091 if (!getCXXABI().classifyReturnType(FI))
7092 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
7093 for (auto &I : FI.arguments())
7094 I.info = classifyArgumentType(I.type);
7097 ABIArgInfo HexagonABIInfo::classifyArgumentType(QualType Ty) const {
7098 if (!isAggregateTypeForABI(Ty)) {
7099 // Treat an enum type as its underlying type.
7100 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
7101 Ty = EnumTy->getDecl()->getIntegerType();
7103 return (Ty->isPromotableIntegerType() ?
7104 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
7107 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
7108 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
7110 // Ignore empty records.
7111 if (isEmptyRecord(getContext(), Ty, true))
7112 return ABIArgInfo::getIgnore();
7114 uint64_t Size = getContext().getTypeSize(Ty);
7116 return getNaturalAlignIndirect(Ty, /*ByVal=*/true);
7117 // Pass in the smallest viable integer type.
7119 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
7121 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7123 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7125 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
7128 ABIArgInfo HexagonABIInfo::classifyReturnType(QualType RetTy) const {
7129 if (RetTy->isVoidType())
7130 return ABIArgInfo::getIgnore();
7132 // Large vector types should be returned via memory.
7133 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 64)
7134 return getNaturalAlignIndirect(RetTy);
7136 if (!isAggregateTypeForABI(RetTy)) {
7137 // Treat an enum type as its underlying type.
7138 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
7139 RetTy = EnumTy->getDecl()->getIntegerType();
7141 return (RetTy->isPromotableIntegerType() ?
7142 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
7145 if (isEmptyRecord(getContext(), RetTy, true))
7146 return ABIArgInfo::getIgnore();
7148 // Aggregates <= 8 bytes are returned in r0; other aggregates
7149 // are returned indirectly.
7150 uint64_t Size = getContext().getTypeSize(RetTy);
7152 // Return in the smallest viable integer type.
7154 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
7156 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7158 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7159 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
7162 return getNaturalAlignIndirect(RetTy, /*ByVal=*/true);
7165 Address HexagonABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7166 QualType Ty) const {
7167 // FIXME: Someone needs to audit that this handle alignment correctly.
7168 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
7169 getContext().getTypeInfoInChars(Ty),
7170 CharUnits::fromQuantity(4),
7171 /*AllowHigherAlign*/ true);
7174 //===----------------------------------------------------------------------===//
7175 // Lanai ABI Implementation
7176 //===----------------------------------------------------------------------===//
7179 class LanaiABIInfo : public DefaultABIInfo {
7181 LanaiABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
7183 bool shouldUseInReg(QualType Ty, CCState &State) const;
7185 void computeInfo(CGFunctionInfo &FI) const override {
7186 CCState State(FI.getCallingConvention());
7187 // Lanai uses 4 registers to pass arguments unless the function has the
7188 // regparm attribute set.
7189 if (FI.getHasRegParm()) {
7190 State.FreeRegs = FI.getRegParm();
7195 if (!getCXXABI().classifyReturnType(FI))
7196 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
7197 for (auto &I : FI.arguments())
7198 I.info = classifyArgumentType(I.type, State);
7201 ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
7202 ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
7204 } // end anonymous namespace
7206 bool LanaiABIInfo::shouldUseInReg(QualType Ty, CCState &State) const {
7207 unsigned Size = getContext().getTypeSize(Ty);
7208 unsigned SizeInRegs = llvm::alignTo(Size, 32U) / 32U;
7210 if (SizeInRegs == 0)
7213 if (SizeInRegs > State.FreeRegs) {
7218 State.FreeRegs -= SizeInRegs;
7223 ABIArgInfo LanaiABIInfo::getIndirectResult(QualType Ty, bool ByVal,
7224 CCState &State) const {
7226 if (State.FreeRegs) {
7227 --State.FreeRegs; // Non-byval indirects just use one pointer.
7228 return getNaturalAlignIndirectInReg(Ty);
7230 return getNaturalAlignIndirect(Ty, false);
7233 // Compute the byval alignment.
7234 const unsigned MinABIStackAlignInBytes = 4;
7235 unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
7236 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true,
7237 /*Realign=*/TypeAlign >
7238 MinABIStackAlignInBytes);
7241 ABIArgInfo LanaiABIInfo::classifyArgumentType(QualType Ty,
7242 CCState &State) const {
7243 // Check with the C++ ABI first.
7244 const RecordType *RT = Ty->getAs<RecordType>();
7246 CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
7247 if (RAA == CGCXXABI::RAA_Indirect) {
7248 return getIndirectResult(Ty, /*ByVal=*/false, State);
7249 } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
7250 return getNaturalAlignIndirect(Ty, /*ByRef=*/true);
7254 if (isAggregateTypeForABI(Ty)) {
7255 // Structures with flexible arrays are always indirect.
7256 if (RT && RT->getDecl()->hasFlexibleArrayMember())
7257 return getIndirectResult(Ty, /*ByVal=*/true, State);
7259 // Ignore empty structs/unions.
7260 if (isEmptyRecord(getContext(), Ty, true))
7261 return ABIArgInfo::getIgnore();
7263 llvm::LLVMContext &LLVMContext = getVMContext();
7264 unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
7265 if (SizeInRegs <= State.FreeRegs) {
7266 llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
7267 SmallVector<llvm::Type *, 3> Elements(SizeInRegs, Int32);
7268 llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
7269 State.FreeRegs -= SizeInRegs;
7270 return ABIArgInfo::getDirectInReg(Result);
7274 return getIndirectResult(Ty, true, State);
7277 // Treat an enum type as its underlying type.
7278 if (const auto *EnumTy = Ty->getAs<EnumType>())
7279 Ty = EnumTy->getDecl()->getIntegerType();
7281 bool InReg = shouldUseInReg(Ty, State);
7282 if (Ty->isPromotableIntegerType()) {
7284 return ABIArgInfo::getDirectInReg();
7285 return ABIArgInfo::getExtend();
7288 return ABIArgInfo::getDirectInReg();
7289 return ABIArgInfo::getDirect();
7293 class LanaiTargetCodeGenInfo : public TargetCodeGenInfo {
7295 LanaiTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
7296 : TargetCodeGenInfo(new LanaiABIInfo(CGT)) {}
7300 //===----------------------------------------------------------------------===//
7301 // AMDGPU ABI Implementation
7302 //===----------------------------------------------------------------------===//
7306 class AMDGPUABIInfo final : public DefaultABIInfo {
7308 explicit AMDGPUABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
7311 ABIArgInfo classifyArgumentType(QualType Ty) const;
7313 void computeInfo(CGFunctionInfo &FI) const override;
7316 void AMDGPUABIInfo::computeInfo(CGFunctionInfo &FI) const {
7317 if (!getCXXABI().classifyReturnType(FI))
7318 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
7320 unsigned CC = FI.getCallingConvention();
7321 for (auto &Arg : FI.arguments())
7322 if (CC == llvm::CallingConv::AMDGPU_KERNEL)
7323 Arg.info = classifyArgumentType(Arg.type);
7325 Arg.info = DefaultABIInfo::classifyArgumentType(Arg.type);
7328 /// \brief Classify argument of given type \p Ty.
7329 ABIArgInfo AMDGPUABIInfo::classifyArgumentType(QualType Ty) const {
7330 llvm::StructType *StrTy = dyn_cast<llvm::StructType>(CGT.ConvertType(Ty));
7332 return DefaultABIInfo::classifyArgumentType(Ty);
7335 // Coerce single element structs to its element.
7336 if (StrTy->getNumElements() == 1) {
7337 return ABIArgInfo::getDirect();
7340 // If we set CanBeFlattened to true, CodeGen will expand the struct to its
7341 // individual elements, which confuses the Clover OpenCL backend; therefore we
7342 // have to set it to false here. Other args of getDirect() are just defaults.
7343 return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
7346 class AMDGPUTargetCodeGenInfo : public TargetCodeGenInfo {
7348 AMDGPUTargetCodeGenInfo(CodeGenTypes &CGT)
7349 : TargetCodeGenInfo(new AMDGPUABIInfo(CGT)) {}
7350 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
7351 CodeGen::CodeGenModule &M) const override;
7352 unsigned getOpenCLKernelCallingConv() const override;
7354 llvm::Constant *getNullPointer(const CodeGen::CodeGenModule &CGM,
7355 llvm::PointerType *T, QualType QT) const override;
7357 unsigned getASTAllocaAddressSpace() const override {
7358 return LangAS::FirstTargetAddressSpace +
7359 getABIInfo().getDataLayout().getAllocaAddrSpace();
7361 unsigned getGlobalVarAddressSpace(CodeGenModule &CGM,
7362 const VarDecl *D) const override;
7366 void AMDGPUTargetCodeGenInfo::setTargetAttributes(
7368 llvm::GlobalValue *GV,
7369 CodeGen::CodeGenModule &M) const {
7370 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
7374 llvm::Function *F = cast<llvm::Function>(GV);
7376 const auto *ReqdWGS = M.getLangOpts().OpenCL ?
7377 FD->getAttr<ReqdWorkGroupSizeAttr>() : nullptr;
7378 const auto *FlatWGS = FD->getAttr<AMDGPUFlatWorkGroupSizeAttr>();
7379 if (ReqdWGS || FlatWGS) {
7380 unsigned Min = FlatWGS ? FlatWGS->getMin() : 0;
7381 unsigned Max = FlatWGS ? FlatWGS->getMax() : 0;
7382 if (ReqdWGS && Min == 0 && Max == 0)
7383 Min = Max = ReqdWGS->getXDim() * ReqdWGS->getYDim() * ReqdWGS->getZDim();
7386 assert(Min <= Max && "Min must be less than or equal Max");
7388 std::string AttrVal = llvm::utostr(Min) + "," + llvm::utostr(Max);
7389 F->addFnAttr("amdgpu-flat-work-group-size", AttrVal);
7391 assert(Max == 0 && "Max must be zero");
7394 if (const auto *Attr = FD->getAttr<AMDGPUWavesPerEUAttr>()) {
7395 unsigned Min = Attr->getMin();
7396 unsigned Max = Attr->getMax();
7399 assert((Max == 0 || Min <= Max) && "Min must be less than or equal Max");
7401 std::string AttrVal = llvm::utostr(Min);
7403 AttrVal = AttrVal + "," + llvm::utostr(Max);
7404 F->addFnAttr("amdgpu-waves-per-eu", AttrVal);
7406 assert(Max == 0 && "Max must be zero");
7409 if (const auto *Attr = FD->getAttr<AMDGPUNumSGPRAttr>()) {
7410 unsigned NumSGPR = Attr->getNumSGPR();
7413 F->addFnAttr("amdgpu-num-sgpr", llvm::utostr(NumSGPR));
7416 if (const auto *Attr = FD->getAttr<AMDGPUNumVGPRAttr>()) {
7417 uint32_t NumVGPR = Attr->getNumVGPR();
7420 F->addFnAttr("amdgpu-num-vgpr", llvm::utostr(NumVGPR));
7424 unsigned AMDGPUTargetCodeGenInfo::getOpenCLKernelCallingConv() const {
7425 return llvm::CallingConv::AMDGPU_KERNEL;
7428 // Currently LLVM assumes null pointers always have value 0,
7429 // which results in incorrectly transformed IR. Therefore, instead of
7430 // emitting null pointers in private and local address spaces, a null
7431 // pointer in generic address space is emitted which is casted to a
7432 // pointer in local or private address space.
7433 llvm::Constant *AMDGPUTargetCodeGenInfo::getNullPointer(
7434 const CodeGen::CodeGenModule &CGM, llvm::PointerType *PT,
7435 QualType QT) const {
7436 if (CGM.getContext().getTargetNullPointerValue(QT) == 0)
7437 return llvm::ConstantPointerNull::get(PT);
7439 auto &Ctx = CGM.getContext();
7440 auto NPT = llvm::PointerType::get(PT->getElementType(),
7441 Ctx.getTargetAddressSpace(LangAS::opencl_generic));
7442 return llvm::ConstantExpr::getAddrSpaceCast(
7443 llvm::ConstantPointerNull::get(NPT), PT);
7447 AMDGPUTargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
7448 const VarDecl *D) const {
7449 assert(!CGM.getLangOpts().OpenCL &&
7450 !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
7451 "Address space agnostic languages only");
7452 unsigned DefaultGlobalAS =
7453 LangAS::FirstTargetAddressSpace +
7454 CGM.getContext().getTargetAddressSpace(LangAS::opencl_global);
7456 return DefaultGlobalAS;
7458 unsigned AddrSpace = D->getType().getAddressSpace();
7459 assert(AddrSpace == LangAS::Default ||
7460 AddrSpace >= LangAS::FirstTargetAddressSpace);
7461 if (AddrSpace != LangAS::Default)
7464 if (CGM.isTypeConstant(D->getType(), false)) {
7465 if (auto ConstAS = CGM.getTarget().getConstantAddressSpace())
7466 return ConstAS.getValue();
7468 return DefaultGlobalAS;
7471 //===----------------------------------------------------------------------===//
7472 // SPARC v8 ABI Implementation.
7473 // Based on the SPARC Compliance Definition version 2.4.1.
7475 // Ensures that complex values are passed in registers.
7478 class SparcV8ABIInfo : public DefaultABIInfo {
7480 SparcV8ABIInfo(CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
7483 ABIArgInfo classifyReturnType(QualType RetTy) const;
7484 void computeInfo(CGFunctionInfo &FI) const override;
7486 } // end anonymous namespace
7490 SparcV8ABIInfo::classifyReturnType(QualType Ty) const {
7491 if (Ty->isAnyComplexType()) {
7492 return ABIArgInfo::getDirect();
7495 return DefaultABIInfo::classifyReturnType(Ty);
7499 void SparcV8ABIInfo::computeInfo(CGFunctionInfo &FI) const {
7501 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
7502 for (auto &Arg : FI.arguments())
7503 Arg.info = classifyArgumentType(Arg.type);
7507 class SparcV8TargetCodeGenInfo : public TargetCodeGenInfo {
7509 SparcV8TargetCodeGenInfo(CodeGenTypes &CGT)
7510 : TargetCodeGenInfo(new SparcV8ABIInfo(CGT)) {}
7512 } // end anonymous namespace
7514 //===----------------------------------------------------------------------===//
7515 // SPARC v9 ABI Implementation.
7516 // Based on the SPARC Compliance Definition version 2.4.1.
7518 // Function arguments a mapped to a nominal "parameter array" and promoted to
7519 // registers depending on their type. Each argument occupies 8 or 16 bytes in
7520 // the array, structs larger than 16 bytes are passed indirectly.
7522 // One case requires special care:
7529 // When a struct mixed is passed by value, it only occupies 8 bytes in the
7530 // parameter array, but the int is passed in an integer register, and the float
7531 // is passed in a floating point register. This is represented as two arguments
7532 // with the LLVM IR inreg attribute:
7534 // declare void f(i32 inreg %i, float inreg %f)
7536 // The code generator will only allocate 4 bytes from the parameter array for
7537 // the inreg arguments. All other arguments are allocated a multiple of 8
7541 class SparcV9ABIInfo : public ABIInfo {
7543 SparcV9ABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
7546 ABIArgInfo classifyType(QualType RetTy, unsigned SizeLimit) const;
7547 void computeInfo(CGFunctionInfo &FI) const override;
7548 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7549 QualType Ty) const override;
7551 // Coercion type builder for structs passed in registers. The coercion type
7552 // serves two purposes:
7554 // 1. Pad structs to a multiple of 64 bits, so they are passed 'left-aligned'
7556 // 2. Expose aligned floating point elements as first-level elements, so the
7557 // code generator knows to pass them in floating point registers.
7559 // We also compute the InReg flag which indicates that the struct contains
7560 // aligned 32-bit floats.
7562 struct CoerceBuilder {
7563 llvm::LLVMContext &Context;
7564 const llvm::DataLayout &DL;
7565 SmallVector<llvm::Type*, 8> Elems;
7569 CoerceBuilder(llvm::LLVMContext &c, const llvm::DataLayout &dl)
7570 : Context(c), DL(dl), Size(0), InReg(false) {}
7572 // Pad Elems with integers until Size is ToSize.
7573 void pad(uint64_t ToSize) {
7574 assert(ToSize >= Size && "Cannot remove elements");
7578 // Finish the current 64-bit word.
7579 uint64_t Aligned = llvm::alignTo(Size, 64);
7580 if (Aligned > Size && Aligned <= ToSize) {
7581 Elems.push_back(llvm::IntegerType::get(Context, Aligned - Size));
7585 // Add whole 64-bit words.
7586 while (Size + 64 <= ToSize) {
7587 Elems.push_back(llvm::Type::getInt64Ty(Context));
7591 // Final in-word padding.
7592 if (Size < ToSize) {
7593 Elems.push_back(llvm::IntegerType::get(Context, ToSize - Size));
7598 // Add a floating point element at Offset.
7599 void addFloat(uint64_t Offset, llvm::Type *Ty, unsigned Bits) {
7600 // Unaligned floats are treated as integers.
7603 // The InReg flag is only required if there are any floats < 64 bits.
7607 Elems.push_back(Ty);
7608 Size = Offset + Bits;
7611 // Add a struct type to the coercion type, starting at Offset (in bits).
7612 void addStruct(uint64_t Offset, llvm::StructType *StrTy) {
7613 const llvm::StructLayout *Layout = DL.getStructLayout(StrTy);
7614 for (unsigned i = 0, e = StrTy->getNumElements(); i != e; ++i) {
7615 llvm::Type *ElemTy = StrTy->getElementType(i);
7616 uint64_t ElemOffset = Offset + Layout->getElementOffsetInBits(i);
7617 switch (ElemTy->getTypeID()) {
7618 case llvm::Type::StructTyID:
7619 addStruct(ElemOffset, cast<llvm::StructType>(ElemTy));
7621 case llvm::Type::FloatTyID:
7622 addFloat(ElemOffset, ElemTy, 32);
7624 case llvm::Type::DoubleTyID:
7625 addFloat(ElemOffset, ElemTy, 64);
7627 case llvm::Type::FP128TyID:
7628 addFloat(ElemOffset, ElemTy, 128);
7630 case llvm::Type::PointerTyID:
7631 if (ElemOffset % 64 == 0) {
7633 Elems.push_back(ElemTy);
7643 // Check if Ty is a usable substitute for the coercion type.
7644 bool isUsableType(llvm::StructType *Ty) const {
7645 return llvm::makeArrayRef(Elems) == Ty->elements();
7648 // Get the coercion type as a literal struct type.
7649 llvm::Type *getType() const {
7650 if (Elems.size() == 1)
7651 return Elems.front();
7653 return llvm::StructType::get(Context, Elems);
7657 } // end anonymous namespace
7660 SparcV9ABIInfo::classifyType(QualType Ty, unsigned SizeLimit) const {
7661 if (Ty->isVoidType())
7662 return ABIArgInfo::getIgnore();
7664 uint64_t Size = getContext().getTypeSize(Ty);
7666 // Anything too big to fit in registers is passed with an explicit indirect
7667 // pointer / sret pointer.
7668 if (Size > SizeLimit)
7669 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
7671 // Treat an enum type as its underlying type.
7672 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
7673 Ty = EnumTy->getDecl()->getIntegerType();
7675 // Integer types smaller than a register are extended.
7676 if (Size < 64 && Ty->isIntegerType())
7677 return ABIArgInfo::getExtend();
7679 // Other non-aggregates go in registers.
7680 if (!isAggregateTypeForABI(Ty))
7681 return ABIArgInfo::getDirect();
7683 // If a C++ object has either a non-trivial copy constructor or a non-trivial
7684 // destructor, it is passed with an explicit indirect pointer / sret pointer.
7685 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
7686 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
7688 // This is a small aggregate type that should be passed in registers.
7689 // Build a coercion type from the LLVM struct type.
7690 llvm::StructType *StrTy = dyn_cast<llvm::StructType>(CGT.ConvertType(Ty));
7692 return ABIArgInfo::getDirect();
7694 CoerceBuilder CB(getVMContext(), getDataLayout());
7695 CB.addStruct(0, StrTy);
7696 CB.pad(llvm::alignTo(CB.DL.getTypeSizeInBits(StrTy), 64));
7698 // Try to use the original type for coercion.
7699 llvm::Type *CoerceTy = CB.isUsableType(StrTy) ? StrTy : CB.getType();
7702 return ABIArgInfo::getDirectInReg(CoerceTy);
7704 return ABIArgInfo::getDirect(CoerceTy);
7707 Address SparcV9ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7708 QualType Ty) const {
7709 ABIArgInfo AI = classifyType(Ty, 16 * 8);
7710 llvm::Type *ArgTy = CGT.ConvertType(Ty);
7711 if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
7712 AI.setCoerceToType(ArgTy);
7714 CharUnits SlotSize = CharUnits::fromQuantity(8);
7716 CGBuilderTy &Builder = CGF.Builder;
7717 Address Addr(Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize);
7718 llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
7720 auto TypeInfo = getContext().getTypeInfoInChars(Ty);
7722 Address ArgAddr = Address::invalid();
7724 switch (AI.getKind()) {
7725 case ABIArgInfo::Expand:
7726 case ABIArgInfo::CoerceAndExpand:
7727 case ABIArgInfo::InAlloca:
7728 llvm_unreachable("Unsupported ABI kind for va_arg");
7730 case ABIArgInfo::Extend: {
7732 CharUnits Offset = SlotSize - TypeInfo.first;
7733 ArgAddr = Builder.CreateConstInBoundsByteGEP(Addr, Offset, "extend");
7737 case ABIArgInfo::Direct: {
7738 auto AllocSize = getDataLayout().getTypeAllocSize(AI.getCoerceToType());
7739 Stride = CharUnits::fromQuantity(AllocSize).alignTo(SlotSize);
7744 case ABIArgInfo::Indirect:
7746 ArgAddr = Builder.CreateElementBitCast(Addr, ArgPtrTy, "indirect");
7747 ArgAddr = Address(Builder.CreateLoad(ArgAddr, "indirect.arg"),
7751 case ABIArgInfo::Ignore:
7752 return Address(llvm::UndefValue::get(ArgPtrTy), TypeInfo.second);
7756 llvm::Value *NextPtr =
7757 Builder.CreateConstInBoundsByteGEP(Addr.getPointer(), Stride, "ap.next");
7758 Builder.CreateStore(NextPtr, VAListAddr);
7760 return Builder.CreateBitCast(ArgAddr, ArgPtrTy, "arg.addr");
7763 void SparcV9ABIInfo::computeInfo(CGFunctionInfo &FI) const {
7764 FI.getReturnInfo() = classifyType(FI.getReturnType(), 32 * 8);
7765 for (auto &I : FI.arguments())
7766 I.info = classifyType(I.type, 16 * 8);
7770 class SparcV9TargetCodeGenInfo : public TargetCodeGenInfo {
7772 SparcV9TargetCodeGenInfo(CodeGenTypes &CGT)
7773 : TargetCodeGenInfo(new SparcV9ABIInfo(CGT)) {}
7775 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
7779 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
7780 llvm::Value *Address) const override;
7782 } // end anonymous namespace
7785 SparcV9TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
7786 llvm::Value *Address) const {
7787 // This is calculated from the LLVM and GCC tables and verified
7788 // against gcc output. AFAIK all ABIs use the same encoding.
7790 CodeGen::CGBuilderTy &Builder = CGF.Builder;
7792 llvm::IntegerType *i8 = CGF.Int8Ty;
7793 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
7794 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
7796 // 0-31: the 8-byte general-purpose registers
7797 AssignToArrayRange(Builder, Address, Eight8, 0, 31);
7799 // 32-63: f0-31, the 4-byte floating-point registers
7800 AssignToArrayRange(Builder, Address, Four8, 32, 63);
7810 AssignToArrayRange(Builder, Address, Eight8, 64, 71);
7812 // 72-87: d0-15, the 8-byte floating-point registers
7813 AssignToArrayRange(Builder, Address, Eight8, 72, 87);
7819 //===----------------------------------------------------------------------===//
7820 // XCore ABI Implementation
7821 //===----------------------------------------------------------------------===//
7825 /// A SmallStringEnc instance is used to build up the TypeString by passing
7826 /// it by reference between functions that append to it.
7827 typedef llvm::SmallString<128> SmallStringEnc;
7829 /// TypeStringCache caches the meta encodings of Types.
7831 /// The reason for caching TypeStrings is two fold:
7832 /// 1. To cache a type's encoding for later uses;
7833 /// 2. As a means to break recursive member type inclusion.
7835 /// A cache Entry can have a Status of:
7836 /// NonRecursive: The type encoding is not recursive;
7837 /// Recursive: The type encoding is recursive;
7838 /// Incomplete: An incomplete TypeString;
7839 /// IncompleteUsed: An incomplete TypeString that has been used in a
7840 /// Recursive type encoding.
7842 /// A NonRecursive entry will have all of its sub-members expanded as fully
7843 /// as possible. Whilst it may contain types which are recursive, the type
7844 /// itself is not recursive and thus its encoding may be safely used whenever
7845 /// the type is encountered.
7847 /// A Recursive entry will have all of its sub-members expanded as fully as
7848 /// possible. The type itself is recursive and it may contain other types which
7849 /// are recursive. The Recursive encoding must not be used during the expansion
7850 /// of a recursive type's recursive branch. For simplicity the code uses
7851 /// IncompleteCount to reject all usage of Recursive encodings for member types.
7853 /// An Incomplete entry is always a RecordType and only encodes its
7854 /// identifier e.g. "s(S){}". Incomplete 'StubEnc' entries are ephemeral and
7855 /// are placed into the cache during type expansion as a means to identify and
7856 /// handle recursive inclusion of types as sub-members. If there is recursion
7857 /// the entry becomes IncompleteUsed.
7859 /// During the expansion of a RecordType's members:
7861 /// If the cache contains a NonRecursive encoding for the member type, the
7862 /// cached encoding is used;
7864 /// If the cache contains a Recursive encoding for the member type, the
7865 /// cached encoding is 'Swapped' out, as it may be incorrect, and...
7867 /// If the member is a RecordType, an Incomplete encoding is placed into the
7868 /// cache to break potential recursive inclusion of itself as a sub-member;
7870 /// Once a member RecordType has been expanded, its temporary incomplete
7871 /// entry is removed from the cache. If a Recursive encoding was swapped out
7872 /// it is swapped back in;
7874 /// If an incomplete entry is used to expand a sub-member, the incomplete
7875 /// entry is marked as IncompleteUsed. The cache keeps count of how many
7876 /// IncompleteUsed entries it currently contains in IncompleteUsedCount;
7878 /// If a member's encoding is found to be a NonRecursive or Recursive viz:
7879 /// IncompleteUsedCount==0, the member's encoding is added to the cache.
7880 /// Else the member is part of a recursive type and thus the recursion has
7881 /// been exited too soon for the encoding to be correct for the member.
7883 class TypeStringCache {
7884 enum Status {NonRecursive, Recursive, Incomplete, IncompleteUsed};
7886 std::string Str; // The encoded TypeString for the type.
7887 enum Status State; // Information about the encoding in 'Str'.
7888 std::string Swapped; // A temporary place holder for a Recursive encoding
7889 // during the expansion of RecordType's members.
7891 std::map<const IdentifierInfo *, struct Entry> Map;
7892 unsigned IncompleteCount; // Number of Incomplete entries in the Map.
7893 unsigned IncompleteUsedCount; // Number of IncompleteUsed entries in the Map.
7895 TypeStringCache() : IncompleteCount(0), IncompleteUsedCount(0) {}
7896 void addIncomplete(const IdentifierInfo *ID, std::string StubEnc);
7897 bool removeIncomplete(const IdentifierInfo *ID);
7898 void addIfComplete(const IdentifierInfo *ID, StringRef Str,
7900 StringRef lookupStr(const IdentifierInfo *ID);
7903 /// TypeString encodings for enum & union fields must be order.
7904 /// FieldEncoding is a helper for this ordering process.
7905 class FieldEncoding {
7909 FieldEncoding(bool b, SmallStringEnc &e) : HasName(b), Enc(e.c_str()) {}
7910 StringRef str() { return Enc; }
7911 bool operator<(const FieldEncoding &rhs) const {
7912 if (HasName != rhs.HasName) return HasName;
7913 return Enc < rhs.Enc;
7917 class XCoreABIInfo : public DefaultABIInfo {
7919 XCoreABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
7920 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7921 QualType Ty) const override;
7924 class XCoreTargetCodeGenInfo : public TargetCodeGenInfo {
7925 mutable TypeStringCache TSC;
7927 XCoreTargetCodeGenInfo(CodeGenTypes &CGT)
7928 :TargetCodeGenInfo(new XCoreABIInfo(CGT)) {}
7929 void emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
7930 CodeGen::CodeGenModule &M) const override;
7933 } // End anonymous namespace.
7935 // TODO: this implementation is likely now redundant with the default
7937 Address XCoreABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7938 QualType Ty) const {
7939 CGBuilderTy &Builder = CGF.Builder;
7942 CharUnits SlotSize = CharUnits::fromQuantity(4);
7943 Address AP(Builder.CreateLoad(VAListAddr), SlotSize);
7945 // Handle the argument.
7946 ABIArgInfo AI = classifyArgumentType(Ty);
7947 CharUnits TypeAlign = getContext().getTypeAlignInChars(Ty);
7948 llvm::Type *ArgTy = CGT.ConvertType(Ty);
7949 if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
7950 AI.setCoerceToType(ArgTy);
7951 llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
7953 Address Val = Address::invalid();
7954 CharUnits ArgSize = CharUnits::Zero();
7955 switch (AI.getKind()) {
7956 case ABIArgInfo::Expand:
7957 case ABIArgInfo::CoerceAndExpand:
7958 case ABIArgInfo::InAlloca:
7959 llvm_unreachable("Unsupported ABI kind for va_arg");
7960 case ABIArgInfo::Ignore:
7961 Val = Address(llvm::UndefValue::get(ArgPtrTy), TypeAlign);
7962 ArgSize = CharUnits::Zero();
7964 case ABIArgInfo::Extend:
7965 case ABIArgInfo::Direct:
7966 Val = Builder.CreateBitCast(AP, ArgPtrTy);
7967 ArgSize = CharUnits::fromQuantity(
7968 getDataLayout().getTypeAllocSize(AI.getCoerceToType()));
7969 ArgSize = ArgSize.alignTo(SlotSize);
7971 case ABIArgInfo::Indirect:
7972 Val = Builder.CreateElementBitCast(AP, ArgPtrTy);
7973 Val = Address(Builder.CreateLoad(Val), TypeAlign);
7978 // Increment the VAList.
7979 if (!ArgSize.isZero()) {
7981 Builder.CreateConstInBoundsByteGEP(AP.getPointer(), ArgSize);
7982 Builder.CreateStore(APN, VAListAddr);
7988 /// During the expansion of a RecordType, an incomplete TypeString is placed
7989 /// into the cache as a means to identify and break recursion.
7990 /// If there is a Recursive encoding in the cache, it is swapped out and will
7991 /// be reinserted by removeIncomplete().
7992 /// All other types of encoding should have been used rather than arriving here.
7993 void TypeStringCache::addIncomplete(const IdentifierInfo *ID,
7994 std::string StubEnc) {
7998 assert( (E.Str.empty() || E.State == Recursive) &&
7999 "Incorrectly use of addIncomplete");
8000 assert(!StubEnc.empty() && "Passing an empty string to addIncomplete()");
8001 E.Swapped.swap(E.Str); // swap out the Recursive
8002 E.Str.swap(StubEnc);
8003 E.State = Incomplete;
8007 /// Once the RecordType has been expanded, the temporary incomplete TypeString
8008 /// must be removed from the cache.
8009 /// If a Recursive was swapped out by addIncomplete(), it will be replaced.
8010 /// Returns true if the RecordType was defined recursively.
8011 bool TypeStringCache::removeIncomplete(const IdentifierInfo *ID) {
8014 auto I = Map.find(ID);
8015 assert(I != Map.end() && "Entry not present");
8016 Entry &E = I->second;
8017 assert( (E.State == Incomplete ||
8018 E.State == IncompleteUsed) &&
8019 "Entry must be an incomplete type");
8020 bool IsRecursive = false;
8021 if (E.State == IncompleteUsed) {
8022 // We made use of our Incomplete encoding, thus we are recursive.
8024 --IncompleteUsedCount;
8026 if (E.Swapped.empty())
8029 // Swap the Recursive back.
8030 E.Swapped.swap(E.Str);
8032 E.State = Recursive;
8038 /// Add the encoded TypeString to the cache only if it is NonRecursive or
8039 /// Recursive (viz: all sub-members were expanded as fully as possible).
8040 void TypeStringCache::addIfComplete(const IdentifierInfo *ID, StringRef Str,
8042 if (!ID || IncompleteUsedCount)
8043 return; // No key or it is is an incomplete sub-type so don't add.
8045 if (IsRecursive && !E.Str.empty()) {
8046 assert(E.State==Recursive && E.Str.size() == Str.size() &&
8047 "This is not the same Recursive entry");
8048 // The parent container was not recursive after all, so we could have used
8049 // this Recursive sub-member entry after all, but we assumed the worse when
8050 // we started viz: IncompleteCount!=0.
8053 assert(E.Str.empty() && "Entry already present");
8055 E.State = IsRecursive? Recursive : NonRecursive;
8058 /// Return a cached TypeString encoding for the ID. If there isn't one, or we
8059 /// are recursively expanding a type (IncompleteCount != 0) and the cached
8060 /// encoding is Recursive, return an empty StringRef.
8061 StringRef TypeStringCache::lookupStr(const IdentifierInfo *ID) {
8063 return StringRef(); // We have no key.
8064 auto I = Map.find(ID);
8066 return StringRef(); // We have no encoding.
8067 Entry &E = I->second;
8068 if (E.State == Recursive && IncompleteCount)
8069 return StringRef(); // We don't use Recursive encodings for member types.
8071 if (E.State == Incomplete) {
8072 // The incomplete type is being used to break out of recursion.
8073 E.State = IncompleteUsed;
8074 ++IncompleteUsedCount;
8079 /// The XCore ABI includes a type information section that communicates symbol
8080 /// type information to the linker. The linker uses this information to verify
8081 /// safety/correctness of things such as array bound and pointers et al.
8082 /// The ABI only requires C (and XC) language modules to emit TypeStrings.
8083 /// This type information (TypeString) is emitted into meta data for all global
8084 /// symbols: definitions, declarations, functions & variables.
8086 /// The TypeString carries type, qualifier, name, size & value details.
8087 /// Please see 'Tools Development Guide' section 2.16.2 for format details:
8088 /// https://www.xmos.com/download/public/Tools-Development-Guide%28X9114A%29.pdf
8089 /// The output is tested by test/CodeGen/xcore-stringtype.c.
8091 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
8092 CodeGen::CodeGenModule &CGM, TypeStringCache &TSC);
8094 /// XCore uses emitTargetMD to emit TypeString metadata for global symbols.
8095 void XCoreTargetCodeGenInfo::emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
8096 CodeGen::CodeGenModule &CGM) const {
8098 if (getTypeString(Enc, D, CGM, TSC)) {
8099 llvm::LLVMContext &Ctx = CGM.getModule().getContext();
8100 llvm::Metadata *MDVals[] = {llvm::ConstantAsMetadata::get(GV),
8101 llvm::MDString::get(Ctx, Enc.str())};
8102 llvm::NamedMDNode *MD =
8103 CGM.getModule().getOrInsertNamedMetadata("xcore.typestrings");
8104 MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
8108 //===----------------------------------------------------------------------===//
8109 // SPIR ABI Implementation
8110 //===----------------------------------------------------------------------===//
8113 class SPIRTargetCodeGenInfo : public TargetCodeGenInfo {
8115 SPIRTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
8116 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
8117 unsigned getOpenCLKernelCallingConv() const override;
8120 } // End anonymous namespace.
8124 void computeSPIRKernelABIInfo(CodeGenModule &CGM, CGFunctionInfo &FI) {
8125 DefaultABIInfo SPIRABI(CGM.getTypes());
8126 SPIRABI.computeInfo(FI);
8131 unsigned SPIRTargetCodeGenInfo::getOpenCLKernelCallingConv() const {
8132 return llvm::CallingConv::SPIR_KERNEL;
8135 static bool appendType(SmallStringEnc &Enc, QualType QType,
8136 const CodeGen::CodeGenModule &CGM,
8137 TypeStringCache &TSC);
8139 /// Helper function for appendRecordType().
8140 /// Builds a SmallVector containing the encoded field types in declaration
8142 static bool extractFieldType(SmallVectorImpl<FieldEncoding> &FE,
8143 const RecordDecl *RD,
8144 const CodeGen::CodeGenModule &CGM,
8145 TypeStringCache &TSC) {
8146 for (const auto *Field : RD->fields()) {
8149 Enc += Field->getName();
8151 if (Field->isBitField()) {
8153 llvm::raw_svector_ostream OS(Enc);
8154 OS << Field->getBitWidthValue(CGM.getContext());
8157 if (!appendType(Enc, Field->getType(), CGM, TSC))
8159 if (Field->isBitField())
8162 FE.emplace_back(!Field->getName().empty(), Enc);
8167 /// Appends structure and union types to Enc and adds encoding to cache.
8168 /// Recursively calls appendType (via extractFieldType) for each field.
8169 /// Union types have their fields ordered according to the ABI.
8170 static bool appendRecordType(SmallStringEnc &Enc, const RecordType *RT,
8171 const CodeGen::CodeGenModule &CGM,
8172 TypeStringCache &TSC, const IdentifierInfo *ID) {
8173 // Append the cached TypeString if we have one.
8174 StringRef TypeString = TSC.lookupStr(ID);
8175 if (!TypeString.empty()) {
8180 // Start to emit an incomplete TypeString.
8181 size_t Start = Enc.size();
8182 Enc += (RT->isUnionType()? 'u' : 's');
8185 Enc += ID->getName();
8188 // We collect all encoded fields and order as necessary.
8189 bool IsRecursive = false;
8190 const RecordDecl *RD = RT->getDecl()->getDefinition();
8191 if (RD && !RD->field_empty()) {
8192 // An incomplete TypeString stub is placed in the cache for this RecordType
8193 // so that recursive calls to this RecordType will use it whilst building a
8194 // complete TypeString for this RecordType.
8195 SmallVector<FieldEncoding, 16> FE;
8196 std::string StubEnc(Enc.substr(Start).str());
8197 StubEnc += '}'; // StubEnc now holds a valid incomplete TypeString.
8198 TSC.addIncomplete(ID, std::move(StubEnc));
8199 if (!extractFieldType(FE, RD, CGM, TSC)) {
8200 (void) TSC.removeIncomplete(ID);
8203 IsRecursive = TSC.removeIncomplete(ID);
8204 // The ABI requires unions to be sorted but not structures.
8205 // See FieldEncoding::operator< for sort algorithm.
8206 if (RT->isUnionType())
8207 std::sort(FE.begin(), FE.end());
8208 // We can now complete the TypeString.
8209 unsigned E = FE.size();
8210 for (unsigned I = 0; I != E; ++I) {
8217 TSC.addIfComplete(ID, Enc.substr(Start), IsRecursive);
8221 /// Appends enum types to Enc and adds the encoding to the cache.
8222 static bool appendEnumType(SmallStringEnc &Enc, const EnumType *ET,
8223 TypeStringCache &TSC,
8224 const IdentifierInfo *ID) {
8225 // Append the cached TypeString if we have one.
8226 StringRef TypeString = TSC.lookupStr(ID);
8227 if (!TypeString.empty()) {
8232 size_t Start = Enc.size();
8235 Enc += ID->getName();
8238 // We collect all encoded enumerations and order them alphanumerically.
8239 if (const EnumDecl *ED = ET->getDecl()->getDefinition()) {
8240 SmallVector<FieldEncoding, 16> FE;
8241 for (auto I = ED->enumerator_begin(), E = ED->enumerator_end(); I != E;
8243 SmallStringEnc EnumEnc;
8245 EnumEnc += I->getName();
8247 I->getInitVal().toString(EnumEnc);
8249 FE.push_back(FieldEncoding(!I->getName().empty(), EnumEnc));
8251 std::sort(FE.begin(), FE.end());
8252 unsigned E = FE.size();
8253 for (unsigned I = 0; I != E; ++I) {
8260 TSC.addIfComplete(ID, Enc.substr(Start), false);
8264 /// Appends type's qualifier to Enc.
8265 /// This is done prior to appending the type's encoding.
8266 static void appendQualifier(SmallStringEnc &Enc, QualType QT) {
8267 // Qualifiers are emitted in alphabetical order.
8268 static const char *const Table[]={"","c:","r:","cr:","v:","cv:","rv:","crv:"};
8270 if (QT.isConstQualified())
8272 if (QT.isRestrictQualified())
8274 if (QT.isVolatileQualified())
8276 Enc += Table[Lookup];
8279 /// Appends built-in types to Enc.
8280 static bool appendBuiltinType(SmallStringEnc &Enc, const BuiltinType *BT) {
8281 const char *EncType;
8282 switch (BT->getKind()) {
8283 case BuiltinType::Void:
8286 case BuiltinType::Bool:
8289 case BuiltinType::Char_U:
8292 case BuiltinType::UChar:
8295 case BuiltinType::SChar:
8298 case BuiltinType::UShort:
8301 case BuiltinType::Short:
8304 case BuiltinType::UInt:
8307 case BuiltinType::Int:
8310 case BuiltinType::ULong:
8313 case BuiltinType::Long:
8316 case BuiltinType::ULongLong:
8319 case BuiltinType::LongLong:
8322 case BuiltinType::Float:
8325 case BuiltinType::Double:
8328 case BuiltinType::LongDouble:
8338 /// Appends a pointer encoding to Enc before calling appendType for the pointee.
8339 static bool appendPointerType(SmallStringEnc &Enc, const PointerType *PT,
8340 const CodeGen::CodeGenModule &CGM,
8341 TypeStringCache &TSC) {
8343 if (!appendType(Enc, PT->getPointeeType(), CGM, TSC))
8349 /// Appends array encoding to Enc before calling appendType for the element.
8350 static bool appendArrayType(SmallStringEnc &Enc, QualType QT,
8351 const ArrayType *AT,
8352 const CodeGen::CodeGenModule &CGM,
8353 TypeStringCache &TSC, StringRef NoSizeEnc) {
8354 if (AT->getSizeModifier() != ArrayType::Normal)
8357 if (const ConstantArrayType *CAT = dyn_cast<ConstantArrayType>(AT))
8358 CAT->getSize().toStringUnsigned(Enc);
8360 Enc += NoSizeEnc; // Global arrays use "*", otherwise it is "".
8362 // The Qualifiers should be attached to the type rather than the array.
8363 appendQualifier(Enc, QT);
8364 if (!appendType(Enc, AT->getElementType(), CGM, TSC))
8370 /// Appends a function encoding to Enc, calling appendType for the return type
8371 /// and the arguments.
8372 static bool appendFunctionType(SmallStringEnc &Enc, const FunctionType *FT,
8373 const CodeGen::CodeGenModule &CGM,
8374 TypeStringCache &TSC) {
8376 if (!appendType(Enc, FT->getReturnType(), CGM, TSC))
8379 if (const FunctionProtoType *FPT = FT->getAs<FunctionProtoType>()) {
8380 // N.B. we are only interested in the adjusted param types.
8381 auto I = FPT->param_type_begin();
8382 auto E = FPT->param_type_end();
8385 if (!appendType(Enc, *I, CGM, TSC))
8391 if (FPT->isVariadic())
8394 if (FPT->isVariadic())
8404 /// Handles the type's qualifier before dispatching a call to handle specific
8406 static bool appendType(SmallStringEnc &Enc, QualType QType,
8407 const CodeGen::CodeGenModule &CGM,
8408 TypeStringCache &TSC) {
8410 QualType QT = QType.getCanonicalType();
8412 if (const ArrayType *AT = QT->getAsArrayTypeUnsafe())
8413 // The Qualifiers should be attached to the type rather than the array.
8414 // Thus we don't call appendQualifier() here.
8415 return appendArrayType(Enc, QT, AT, CGM, TSC, "");
8417 appendQualifier(Enc, QT);
8419 if (const BuiltinType *BT = QT->getAs<BuiltinType>())
8420 return appendBuiltinType(Enc, BT);
8422 if (const PointerType *PT = QT->getAs<PointerType>())
8423 return appendPointerType(Enc, PT, CGM, TSC);
8425 if (const EnumType *ET = QT->getAs<EnumType>())
8426 return appendEnumType(Enc, ET, TSC, QT.getBaseTypeIdentifier());
8428 if (const RecordType *RT = QT->getAsStructureType())
8429 return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
8431 if (const RecordType *RT = QT->getAsUnionType())
8432 return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
8434 if (const FunctionType *FT = QT->getAs<FunctionType>())
8435 return appendFunctionType(Enc, FT, CGM, TSC);
8440 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
8441 CodeGen::CodeGenModule &CGM, TypeStringCache &TSC) {
8445 if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) {
8446 if (FD->getLanguageLinkage() != CLanguageLinkage)
8448 return appendType(Enc, FD->getType(), CGM, TSC);
8451 if (const VarDecl *VD = dyn_cast<VarDecl>(D)) {
8452 if (VD->getLanguageLinkage() != CLanguageLinkage)
8454 QualType QT = VD->getType().getCanonicalType();
8455 if (const ArrayType *AT = QT->getAsArrayTypeUnsafe()) {
8456 // Global ArrayTypes are given a size of '*' if the size is unknown.
8457 // The Qualifiers should be attached to the type rather than the array.
8458 // Thus we don't call appendQualifier() here.
8459 return appendArrayType(Enc, QT, AT, CGM, TSC, "*");
8461 return appendType(Enc, QT, CGM, TSC);
8467 //===----------------------------------------------------------------------===//
8469 //===----------------------------------------------------------------------===//
8471 bool CodeGenModule::supportsCOMDAT() const {
8472 return getTriple().supportsCOMDAT();
8475 const TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() {
8476 if (TheTargetCodeGenInfo)
8477 return *TheTargetCodeGenInfo;
8479 // Helper to set the unique_ptr while still keeping the return value.
8480 auto SetCGInfo = [&](TargetCodeGenInfo *P) -> const TargetCodeGenInfo & {
8481 this->TheTargetCodeGenInfo.reset(P);
8485 const llvm::Triple &Triple = getTarget().getTriple();
8486 switch (Triple.getArch()) {
8488 return SetCGInfo(new DefaultTargetCodeGenInfo(Types));
8490 case llvm::Triple::le32:
8491 return SetCGInfo(new PNaClTargetCodeGenInfo(Types));
8492 case llvm::Triple::mips:
8493 case llvm::Triple::mipsel:
8494 if (Triple.getOS() == llvm::Triple::NaCl)
8495 return SetCGInfo(new PNaClTargetCodeGenInfo(Types));
8496 return SetCGInfo(new MIPSTargetCodeGenInfo(Types, true));
8498 case llvm::Triple::mips64:
8499 case llvm::Triple::mips64el:
8500 return SetCGInfo(new MIPSTargetCodeGenInfo(Types, false));
8502 case llvm::Triple::avr:
8503 return SetCGInfo(new AVRTargetCodeGenInfo(Types));
8505 case llvm::Triple::aarch64:
8506 case llvm::Triple::aarch64_be: {
8507 AArch64ABIInfo::ABIKind Kind = AArch64ABIInfo::AAPCS;
8508 if (getTarget().getABI() == "darwinpcs")
8509 Kind = AArch64ABIInfo::DarwinPCS;
8510 else if (Triple.isOSWindows())
8511 Kind = AArch64ABIInfo::Win64;
8513 return SetCGInfo(new AArch64TargetCodeGenInfo(Types, Kind));
8516 case llvm::Triple::wasm32:
8517 case llvm::Triple::wasm64:
8518 return SetCGInfo(new WebAssemblyTargetCodeGenInfo(Types));
8520 case llvm::Triple::arm:
8521 case llvm::Triple::armeb:
8522 case llvm::Triple::thumb:
8523 case llvm::Triple::thumbeb: {
8524 if (Triple.getOS() == llvm::Triple::Win32) {
8526 new WindowsARMTargetCodeGenInfo(Types, ARMABIInfo::AAPCS_VFP));
8529 ARMABIInfo::ABIKind Kind = ARMABIInfo::AAPCS;
8530 StringRef ABIStr = getTarget().getABI();
8531 if (ABIStr == "apcs-gnu")
8532 Kind = ARMABIInfo::APCS;
8533 else if (ABIStr == "aapcs16")
8534 Kind = ARMABIInfo::AAPCS16_VFP;
8535 else if (CodeGenOpts.FloatABI == "hard" ||
8536 (CodeGenOpts.FloatABI != "soft" &&
8537 (Triple.getEnvironment() == llvm::Triple::GNUEABIHF ||
8538 Triple.getEnvironment() == llvm::Triple::MuslEABIHF ||
8539 Triple.getEnvironment() == llvm::Triple::EABIHF)))
8540 Kind = ARMABIInfo::AAPCS_VFP;
8542 return SetCGInfo(new ARMTargetCodeGenInfo(Types, Kind));
8545 case llvm::Triple::ppc:
8547 new PPC32TargetCodeGenInfo(Types, CodeGenOpts.FloatABI == "soft"));
8548 case llvm::Triple::ppc64:
8549 if (Triple.isOSBinFormatELF()) {
8550 PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv1;
8551 if (getTarget().getABI() == "elfv2")
8552 Kind = PPC64_SVR4_ABIInfo::ELFv2;
8553 bool HasQPX = getTarget().getABI() == "elfv1-qpx";
8554 bool IsSoftFloat = CodeGenOpts.FloatABI == "soft";
8556 return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX,
8559 return SetCGInfo(new PPC64TargetCodeGenInfo(Types));
8560 case llvm::Triple::ppc64le: {
8561 assert(Triple.isOSBinFormatELF() && "PPC64 LE non-ELF not supported!");
8562 PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv2;
8563 if (getTarget().getABI() == "elfv1" || getTarget().getABI() == "elfv1-qpx")
8564 Kind = PPC64_SVR4_ABIInfo::ELFv1;
8565 bool HasQPX = getTarget().getABI() == "elfv1-qpx";
8566 bool IsSoftFloat = CodeGenOpts.FloatABI == "soft";
8568 return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX,
8572 case llvm::Triple::nvptx:
8573 case llvm::Triple::nvptx64:
8574 return SetCGInfo(new NVPTXTargetCodeGenInfo(Types));
8576 case llvm::Triple::msp430:
8577 return SetCGInfo(new MSP430TargetCodeGenInfo(Types));
8579 case llvm::Triple::systemz: {
8580 bool HasVector = getTarget().getABI() == "vector";
8581 return SetCGInfo(new SystemZTargetCodeGenInfo(Types, HasVector));
8584 case llvm::Triple::tce:
8585 case llvm::Triple::tcele:
8586 return SetCGInfo(new TCETargetCodeGenInfo(Types));
8588 case llvm::Triple::x86: {
8589 bool IsDarwinVectorABI = Triple.isOSDarwin();
8590 bool RetSmallStructInRegABI =
8591 X86_32TargetCodeGenInfo::isStructReturnInRegABI(Triple, CodeGenOpts);
8592 bool IsWin32FloatStructABI = Triple.isOSWindows() && !Triple.isOSCygMing();
8594 if (Triple.getOS() == llvm::Triple::Win32) {
8595 return SetCGInfo(new WinX86_32TargetCodeGenInfo(
8596 Types, IsDarwinVectorABI, RetSmallStructInRegABI,
8597 IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters));
8599 return SetCGInfo(new X86_32TargetCodeGenInfo(
8600 Types, IsDarwinVectorABI, RetSmallStructInRegABI,
8601 IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters,
8602 CodeGenOpts.FloatABI == "soft"));
8606 case llvm::Triple::x86_64: {
8607 StringRef ABI = getTarget().getABI();
8608 X86AVXABILevel AVXLevel =
8610 ? X86AVXABILevel::AVX512
8611 : ABI == "avx" ? X86AVXABILevel::AVX : X86AVXABILevel::None);
8613 switch (Triple.getOS()) {
8614 case llvm::Triple::Win32:
8615 return SetCGInfo(new WinX86_64TargetCodeGenInfo(Types, AVXLevel));
8616 case llvm::Triple::PS4:
8617 return SetCGInfo(new PS4TargetCodeGenInfo(Types, AVXLevel));
8619 return SetCGInfo(new X86_64TargetCodeGenInfo(Types, AVXLevel));
8622 case llvm::Triple::hexagon:
8623 return SetCGInfo(new HexagonTargetCodeGenInfo(Types));
8624 case llvm::Triple::lanai:
8625 return SetCGInfo(new LanaiTargetCodeGenInfo(Types));
8626 case llvm::Triple::r600:
8627 return SetCGInfo(new AMDGPUTargetCodeGenInfo(Types));
8628 case llvm::Triple::amdgcn:
8629 return SetCGInfo(new AMDGPUTargetCodeGenInfo(Types));
8630 case llvm::Triple::sparc:
8631 return SetCGInfo(new SparcV8TargetCodeGenInfo(Types));
8632 case llvm::Triple::sparcv9:
8633 return SetCGInfo(new SparcV9TargetCodeGenInfo(Types));
8634 case llvm::Triple::xcore:
8635 return SetCGInfo(new XCoreTargetCodeGenInfo(Types));
8636 case llvm::Triple::spir:
8637 case llvm::Triple::spir64:
8638 return SetCGInfo(new SPIRTargetCodeGenInfo(Types));