1 //===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // These classes wrap the information about a call or function
11 // definition used to handle ABI compliancy.
13 //===----------------------------------------------------------------------===//
15 #include "TargetInfo.h"
20 #include "CodeGenFunction.h"
21 #include "clang/AST/RecordLayout.h"
22 #include "clang/CodeGen/CGFunctionInfo.h"
23 #include "clang/CodeGen/SwiftCallingConv.h"
24 #include "clang/Frontend/CodeGenOptions.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/ADT/Twine.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include <algorithm> // std::sort
34 using namespace clang;
35 using namespace CodeGen;
37 // Helper for coercing an aggregate argument or return value into an integer
38 // array of the same size (including padding) and alignment. This alternate
39 // coercion happens only for the RenderScript ABI and can be removed after
40 // runtimes that rely on it are no longer supported.
42 // RenderScript assumes that the size of the argument / return value in the IR
43 // is the same as the size of the corresponding qualified type. This helper
44 // coerces the aggregate type into an array of the same size (including
45 // padding). This coercion is used in lieu of expansion of struct members or
46 // other canonical coercions that return a coerced-type of larger size.
48 // Ty - The argument / return value type
49 // Context - The associated ASTContext
50 // LLVMContext - The associated LLVMContext
51 static ABIArgInfo coerceToIntArray(QualType Ty,
53 llvm::LLVMContext &LLVMContext) {
54 // Alignment and Size are measured in bits.
55 const uint64_t Size = Context.getTypeSize(Ty);
56 const uint64_t Alignment = Context.getTypeAlign(Ty);
57 llvm::Type *IntType = llvm::Type::getIntNTy(LLVMContext, Alignment);
58 const uint64_t NumElements = (Size + Alignment - 1) / Alignment;
59 return ABIArgInfo::getDirect(llvm::ArrayType::get(IntType, NumElements));
62 static void AssignToArrayRange(CodeGen::CGBuilderTy &Builder,
67 // Alternatively, we could emit this as a loop in the source.
68 for (unsigned I = FirstIndex; I <= LastIndex; ++I) {
70 Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I);
71 Builder.CreateAlignedStore(Value, Cell, CharUnits::One());
75 static bool isAggregateTypeForABI(QualType T) {
76 return !CodeGenFunction::hasScalarEvaluationKind(T) ||
77 T->isMemberFunctionPointerType();
81 ABIInfo::getNaturalAlignIndirect(QualType Ty, bool ByRef, bool Realign,
82 llvm::Type *Padding) const {
83 return ABIArgInfo::getIndirect(getContext().getTypeAlignInChars(Ty),
84 ByRef, Realign, Padding);
88 ABIInfo::getNaturalAlignIndirectInReg(QualType Ty, bool Realign) const {
89 return ABIArgInfo::getIndirectInReg(getContext().getTypeAlignInChars(Ty),
90 /*ByRef*/ false, Realign);
93 Address ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
95 return Address::invalid();
98 ABIInfo::~ABIInfo() {}
100 /// Does the given lowering require more than the given number of
101 /// registers when expanded?
103 /// This is intended to be the basis of a reasonable basic implementation
104 /// of should{Pass,Return}IndirectlyForSwift.
106 /// For most targets, a limit of four total registers is reasonable; this
107 /// limits the amount of code required in order to move around the value
108 /// in case it wasn't produced immediately prior to the call by the caller
109 /// (or wasn't produced in exactly the right registers) or isn't used
110 /// immediately within the callee. But some targets may need to further
111 /// limit the register count due to an inability to support that many
112 /// return registers.
113 static bool occupiesMoreThan(CodeGenTypes &cgt,
114 ArrayRef<llvm::Type*> scalarTypes,
115 unsigned maxAllRegisters) {
116 unsigned intCount = 0, fpCount = 0;
117 for (llvm::Type *type : scalarTypes) {
118 if (type->isPointerTy()) {
120 } else if (auto intTy = dyn_cast<llvm::IntegerType>(type)) {
121 auto ptrWidth = cgt.getTarget().getPointerWidth(0);
122 intCount += (intTy->getBitWidth() + ptrWidth - 1) / ptrWidth;
124 assert(type->isVectorTy() || type->isFloatingPointTy());
129 return (intCount + fpCount > maxAllRegisters);
132 bool SwiftABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize,
134 unsigned numElts) const {
135 // The default implementation of this assumes that the target guarantees
136 // 128-bit SIMD support but nothing more.
137 return (vectorSize.getQuantity() > 8 && vectorSize.getQuantity() <= 16);
140 static CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT,
142 const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl());
144 if (!RT->getDecl()->canPassInRegisters())
145 return CGCXXABI::RAA_Indirect;
146 return CGCXXABI::RAA_Default;
148 return CXXABI.getRecordArgABI(RD);
151 static CGCXXABI::RecordArgABI getRecordArgABI(QualType T,
153 const RecordType *RT = T->getAs<RecordType>();
155 return CGCXXABI::RAA_Default;
156 return getRecordArgABI(RT, CXXABI);
159 static bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
160 const ABIInfo &Info) {
161 QualType Ty = FI.getReturnType();
163 if (const auto *RT = Ty->getAs<RecordType>())
164 if (!isa<CXXRecordDecl>(RT->getDecl()) &&
165 !RT->getDecl()->canPassInRegisters()) {
166 FI.getReturnInfo() = Info.getNaturalAlignIndirect(Ty);
170 return CXXABI.classifyReturnType(FI);
173 /// Pass transparent unions as if they were the type of the first element. Sema
174 /// should ensure that all elements of the union have the same "machine type".
175 static QualType useFirstFieldIfTransparentUnion(QualType Ty) {
176 if (const RecordType *UT = Ty->getAsUnionType()) {
177 const RecordDecl *UD = UT->getDecl();
178 if (UD->hasAttr<TransparentUnionAttr>()) {
179 assert(!UD->field_empty() && "sema created an empty transparent union");
180 return UD->field_begin()->getType();
186 CGCXXABI &ABIInfo::getCXXABI() const {
187 return CGT.getCXXABI();
190 ASTContext &ABIInfo::getContext() const {
191 return CGT.getContext();
194 llvm::LLVMContext &ABIInfo::getVMContext() const {
195 return CGT.getLLVMContext();
198 const llvm::DataLayout &ABIInfo::getDataLayout() const {
199 return CGT.getDataLayout();
202 const TargetInfo &ABIInfo::getTarget() const {
203 return CGT.getTarget();
206 const CodeGenOptions &ABIInfo::getCodeGenOpts() const {
207 return CGT.getCodeGenOpts();
210 bool ABIInfo::isAndroid() const { return getTarget().getTriple().isAndroid(); }
212 bool ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
216 bool ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
217 uint64_t Members) const {
221 LLVM_DUMP_METHOD void ABIArgInfo::dump() const {
222 raw_ostream &OS = llvm::errs();
223 OS << "(ABIArgInfo Kind=";
226 OS << "Direct Type=";
227 if (llvm::Type *Ty = getCoerceToType())
239 OS << "InAlloca Offset=" << getInAllocaFieldIndex();
242 OS << "Indirect Align=" << getIndirectAlign().getQuantity()
243 << " ByVal=" << getIndirectByVal()
244 << " Realign=" << getIndirectRealign();
249 case CoerceAndExpand:
250 OS << "CoerceAndExpand Type=";
251 getCoerceAndExpandType()->print(OS);
257 // Dynamically round a pointer up to a multiple of the given alignment.
258 static llvm::Value *emitRoundPointerUpToAlignment(CodeGenFunction &CGF,
261 llvm::Value *PtrAsInt = Ptr;
262 // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align;
263 PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
264 PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
265 llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1));
266 PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
267 llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity()));
268 PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt,
270 Ptr->getName() + ".aligned");
274 /// Emit va_arg for a platform using the common void* representation,
275 /// where arguments are simply emitted in an array of slots on the stack.
277 /// This version implements the core direct-value passing rules.
279 /// \param SlotSize - The size and alignment of a stack slot.
280 /// Each argument will be allocated to a multiple of this number of
281 /// slots, and all the slots will be aligned to this value.
282 /// \param AllowHigherAlign - The slot alignment is not a cap;
283 /// an argument type with an alignment greater than the slot size
284 /// will be emitted on a higher-alignment address, potentially
285 /// leaving one or more empty slots behind as padding. If this
286 /// is false, the returned address might be less-aligned than
288 static Address emitVoidPtrDirectVAArg(CodeGenFunction &CGF,
290 llvm::Type *DirectTy,
291 CharUnits DirectSize,
292 CharUnits DirectAlign,
294 bool AllowHigherAlign) {
295 // Cast the element type to i8* if necessary. Some platforms define
296 // va_list as a struct containing an i8* instead of just an i8*.
297 if (VAListAddr.getElementType() != CGF.Int8PtrTy)
298 VAListAddr = CGF.Builder.CreateElementBitCast(VAListAddr, CGF.Int8PtrTy);
300 llvm::Value *Ptr = CGF.Builder.CreateLoad(VAListAddr, "argp.cur");
302 // If the CC aligns values higher than the slot size, do so if needed.
303 Address Addr = Address::invalid();
304 if (AllowHigherAlign && DirectAlign > SlotSize) {
305 Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign),
308 Addr = Address(Ptr, SlotSize);
311 // Advance the pointer past the argument, then store that back.
312 CharUnits FullDirectSize = DirectSize.alignTo(SlotSize);
313 llvm::Value *NextPtr =
314 CGF.Builder.CreateConstInBoundsByteGEP(Addr.getPointer(), FullDirectSize,
316 CGF.Builder.CreateStore(NextPtr, VAListAddr);
318 // If the argument is smaller than a slot, and this is a big-endian
319 // target, the argument will be right-adjusted in its slot.
320 if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() &&
321 !DirectTy->isStructTy()) {
322 Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize);
325 Addr = CGF.Builder.CreateElementBitCast(Addr, DirectTy);
329 /// Emit va_arg for a platform using the common void* representation,
330 /// where arguments are simply emitted in an array of slots on the stack.
332 /// \param IsIndirect - Values of this type are passed indirectly.
333 /// \param ValueInfo - The size and alignment of this type, generally
334 /// computed with getContext().getTypeInfoInChars(ValueTy).
335 /// \param SlotSizeAndAlign - The size and alignment of a stack slot.
336 /// Each argument will be allocated to a multiple of this number of
337 /// slots, and all the slots will be aligned to this value.
338 /// \param AllowHigherAlign - The slot alignment is not a cap;
339 /// an argument type with an alignment greater than the slot size
340 /// will be emitted on a higher-alignment address, potentially
341 /// leaving one or more empty slots behind as padding.
342 static Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr,
343 QualType ValueTy, bool IsIndirect,
344 std::pair<CharUnits, CharUnits> ValueInfo,
345 CharUnits SlotSizeAndAlign,
346 bool AllowHigherAlign) {
347 // The size and alignment of the value that was passed directly.
348 CharUnits DirectSize, DirectAlign;
350 DirectSize = CGF.getPointerSize();
351 DirectAlign = CGF.getPointerAlign();
353 DirectSize = ValueInfo.first;
354 DirectAlign = ValueInfo.second;
357 // Cast the address we've calculated to the right type.
358 llvm::Type *DirectTy = CGF.ConvertTypeForMem(ValueTy);
360 DirectTy = DirectTy->getPointerTo(0);
362 Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy,
363 DirectSize, DirectAlign,
368 Addr = Address(CGF.Builder.CreateLoad(Addr), ValueInfo.second);
375 static Address emitMergePHI(CodeGenFunction &CGF,
376 Address Addr1, llvm::BasicBlock *Block1,
377 Address Addr2, llvm::BasicBlock *Block2,
378 const llvm::Twine &Name = "") {
379 assert(Addr1.getType() == Addr2.getType());
380 llvm::PHINode *PHI = CGF.Builder.CreatePHI(Addr1.getType(), 2, Name);
381 PHI->addIncoming(Addr1.getPointer(), Block1);
382 PHI->addIncoming(Addr2.getPointer(), Block2);
383 CharUnits Align = std::min(Addr1.getAlignment(), Addr2.getAlignment());
384 return Address(PHI, Align);
387 TargetCodeGenInfo::~TargetCodeGenInfo() { delete Info; }
389 // If someone can figure out a general rule for this, that would be great.
390 // It's probably just doomed to be platform-dependent, though.
391 unsigned TargetCodeGenInfo::getSizeOfUnwindException() const {
393 // x86-64 FreeBSD, Linux, Darwin
394 // x86-32 FreeBSD, Linux, Darwin
395 // PowerPC Linux, Darwin
396 // ARM Darwin (*not* EABI)
401 bool TargetCodeGenInfo::isNoProtoCallVariadic(const CallArgList &args,
402 const FunctionNoProtoType *fnType) const {
403 // The following conventions are known to require this to be false:
406 // For everything else, we just prefer false unless we opt out.
411 TargetCodeGenInfo::getDependentLibraryOption(llvm::StringRef Lib,
412 llvm::SmallString<24> &Opt) const {
413 // This assumes the user is passing a library name like "rt" instead of a
414 // filename like "librt.a/so", and that they don't care whether it's static or
420 unsigned TargetCodeGenInfo::getOpenCLKernelCallingConv() const {
421 // OpenCL kernels are called via an explicit runtime API with arguments
422 // set with clSetKernelArg(), not as normal sub-functions.
423 // Return SPIR_KERNEL by default as the kernel calling convention to
424 // ensure the fingerprint is fixed such way that each OpenCL argument
425 // gets one matching argument in the produced kernel function argument
426 // list to enable feasible implementation of clSetKernelArg() with
427 // aggregates etc. In case we would use the default C calling conv here,
428 // clSetKernelArg() might break depending on the target-specific
429 // conventions; different targets might split structs passed as values
430 // to multiple function arguments etc.
431 return llvm::CallingConv::SPIR_KERNEL;
434 llvm::Constant *TargetCodeGenInfo::getNullPointer(const CodeGen::CodeGenModule &CGM,
435 llvm::PointerType *T, QualType QT) const {
436 return llvm::ConstantPointerNull::get(T);
439 LangAS TargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
440 const VarDecl *D) const {
441 assert(!CGM.getLangOpts().OpenCL &&
442 !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
443 "Address space agnostic languages only");
444 return D ? D->getType().getAddressSpace() : LangAS::Default;
447 llvm::Value *TargetCodeGenInfo::performAddrSpaceCast(
448 CodeGen::CodeGenFunction &CGF, llvm::Value *Src, LangAS SrcAddr,
449 LangAS DestAddr, llvm::Type *DestTy, bool isNonNull) const {
450 // Since target may map different address spaces in AST to the same address
451 // space, an address space conversion may end up as a bitcast.
452 if (auto *C = dyn_cast<llvm::Constant>(Src))
453 return performAddrSpaceCast(CGF.CGM, C, SrcAddr, DestAddr, DestTy);
454 return CGF.Builder.CreatePointerBitCastOrAddrSpaceCast(Src, DestTy);
458 TargetCodeGenInfo::performAddrSpaceCast(CodeGenModule &CGM, llvm::Constant *Src,
459 LangAS SrcAddr, LangAS DestAddr,
460 llvm::Type *DestTy) const {
461 // Since target may map different address spaces in AST to the same address
462 // space, an address space conversion may end up as a bitcast.
463 return llvm::ConstantExpr::getPointerCast(Src, DestTy);
467 TargetCodeGenInfo::getLLVMSyncScopeID(SyncScope S, llvm::LLVMContext &C) const {
468 return C.getOrInsertSyncScopeID(""); /* default sync scope */
471 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays);
473 /// isEmptyField - Return true iff a the field is "empty", that is it
474 /// is an unnamed bit-field or an (array of) empty record(s).
475 static bool isEmptyField(ASTContext &Context, const FieldDecl *FD,
477 if (FD->isUnnamedBitfield())
480 QualType FT = FD->getType();
482 // Constant arrays of empty records count as empty, strip them off.
483 // Constant arrays of zero length always count as empty.
485 while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
486 if (AT->getSize() == 0)
488 FT = AT->getElementType();
491 const RecordType *RT = FT->getAs<RecordType>();
495 // C++ record fields are never empty, at least in the Itanium ABI.
497 // FIXME: We should use a predicate for whether this behavior is true in the
499 if (isa<CXXRecordDecl>(RT->getDecl()))
502 return isEmptyRecord(Context, FT, AllowArrays);
505 /// isEmptyRecord - Return true iff a structure contains only empty
506 /// fields. Note that a structure with a flexible array member is not
507 /// considered empty.
508 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) {
509 const RecordType *RT = T->getAs<RecordType>();
512 const RecordDecl *RD = RT->getDecl();
513 if (RD->hasFlexibleArrayMember())
516 // If this is a C++ record, check the bases first.
517 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
518 for (const auto &I : CXXRD->bases())
519 if (!isEmptyRecord(Context, I.getType(), true))
522 for (const auto *I : RD->fields())
523 if (!isEmptyField(Context, I, AllowArrays))
528 /// isSingleElementStruct - Determine if a structure is a "single
529 /// element struct", i.e. it has exactly one non-empty field or
530 /// exactly one field which is itself a single element
531 /// struct. Structures with flexible array members are never
532 /// considered single element structs.
534 /// \return The field declaration for the single non-empty field, if
536 static const Type *isSingleElementStruct(QualType T, ASTContext &Context) {
537 const RecordType *RT = T->getAs<RecordType>();
541 const RecordDecl *RD = RT->getDecl();
542 if (RD->hasFlexibleArrayMember())
545 const Type *Found = nullptr;
547 // If this is a C++ record, check the bases first.
548 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
549 for (const auto &I : CXXRD->bases()) {
550 // Ignore empty records.
551 if (isEmptyRecord(Context, I.getType(), true))
554 // If we already found an element then this isn't a single-element struct.
558 // If this is non-empty and not a single element struct, the composite
559 // cannot be a single element struct.
560 Found = isSingleElementStruct(I.getType(), Context);
566 // Check for single element.
567 for (const auto *FD : RD->fields()) {
568 QualType FT = FD->getType();
570 // Ignore empty fields.
571 if (isEmptyField(Context, FD, true))
574 // If we already found an element then this isn't a single-element
579 // Treat single element arrays as the element.
580 while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
581 if (AT->getSize().getZExtValue() != 1)
583 FT = AT->getElementType();
586 if (!isAggregateTypeForABI(FT)) {
587 Found = FT.getTypePtr();
589 Found = isSingleElementStruct(FT, Context);
595 // We don't consider a struct a single-element struct if it has
596 // padding beyond the element type.
597 if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T))
604 Address EmitVAArgInstr(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
605 const ABIArgInfo &AI) {
606 // This default implementation defers to the llvm backend's va_arg
607 // instruction. It can handle only passing arguments directly
608 // (typically only handled in the backend for primitive types), or
609 // aggregates passed indirectly by pointer (NOTE: if the "byval"
610 // flag has ABI impact in the callee, this implementation cannot
613 // Only a few cases are covered here at the moment -- those needed
614 // by the default abi.
617 if (AI.isIndirect()) {
618 assert(!AI.getPaddingType() &&
619 "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
621 !AI.getIndirectRealign() &&
622 "Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!");
624 auto TyInfo = CGF.getContext().getTypeInfoInChars(Ty);
625 CharUnits TyAlignForABI = TyInfo.second;
628 llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty));
630 CGF.Builder.CreateVAArg(VAListAddr.getPointer(), BaseTy);
631 return Address(Addr, TyAlignForABI);
633 assert((AI.isDirect() || AI.isExtend()) &&
634 "Unexpected ArgInfo Kind in generic VAArg emitter!");
636 assert(!AI.getInReg() &&
637 "Unexpected InReg seen in arginfo in generic VAArg emitter!");
638 assert(!AI.getPaddingType() &&
639 "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
640 assert(!AI.getDirectOffset() &&
641 "Unexpected DirectOffset seen in arginfo in generic VAArg emitter!");
642 assert(!AI.getCoerceToType() &&
643 "Unexpected CoerceToType seen in arginfo in generic VAArg emitter!");
645 Address Temp = CGF.CreateMemTemp(Ty, "varet");
646 Val = CGF.Builder.CreateVAArg(VAListAddr.getPointer(), CGF.ConvertType(Ty));
647 CGF.Builder.CreateStore(Val, Temp);
652 /// DefaultABIInfo - The default implementation for ABI specific
653 /// details. This implementation provides information which results in
654 /// self-consistent and sensible LLVM IR generation, but does not
655 /// conform to any particular ABI.
656 class DefaultABIInfo : public ABIInfo {
658 DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
660 ABIArgInfo classifyReturnType(QualType RetTy) const;
661 ABIArgInfo classifyArgumentType(QualType RetTy) const;
663 void computeInfo(CGFunctionInfo &FI) const override {
664 if (!getCXXABI().classifyReturnType(FI))
665 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
666 for (auto &I : FI.arguments())
667 I.info = classifyArgumentType(I.type);
670 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
671 QualType Ty) const override {
672 return EmitVAArgInstr(CGF, VAListAddr, Ty, classifyArgumentType(Ty));
676 class DefaultTargetCodeGenInfo : public TargetCodeGenInfo {
678 DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
679 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
682 ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty) const {
683 Ty = useFirstFieldIfTransparentUnion(Ty);
685 if (isAggregateTypeForABI(Ty)) {
686 // Records with non-trivial destructors/copy-constructors should not be
688 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
689 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
691 return getNaturalAlignIndirect(Ty);
694 // Treat an enum type as its underlying type.
695 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
696 Ty = EnumTy->getDecl()->getIntegerType();
698 return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty)
699 : ABIArgInfo::getDirect());
702 ABIArgInfo DefaultABIInfo::classifyReturnType(QualType RetTy) const {
703 if (RetTy->isVoidType())
704 return ABIArgInfo::getIgnore();
706 if (isAggregateTypeForABI(RetTy))
707 return getNaturalAlignIndirect(RetTy);
709 // Treat an enum type as its underlying type.
710 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
711 RetTy = EnumTy->getDecl()->getIntegerType();
713 return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
714 : ABIArgInfo::getDirect());
717 //===----------------------------------------------------------------------===//
718 // WebAssembly ABI Implementation
720 // This is a very simple ABI that relies a lot on DefaultABIInfo.
721 //===----------------------------------------------------------------------===//
723 class WebAssemblyABIInfo final : public DefaultABIInfo {
725 explicit WebAssemblyABIInfo(CodeGen::CodeGenTypes &CGT)
726 : DefaultABIInfo(CGT) {}
729 ABIArgInfo classifyReturnType(QualType RetTy) const;
730 ABIArgInfo classifyArgumentType(QualType Ty) const;
732 // DefaultABIInfo's classifyReturnType and classifyArgumentType are
733 // non-virtual, but computeInfo and EmitVAArg are virtual, so we
735 void computeInfo(CGFunctionInfo &FI) const override {
736 if (!getCXXABI().classifyReturnType(FI))
737 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
738 for (auto &Arg : FI.arguments())
739 Arg.info = classifyArgumentType(Arg.type);
742 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
743 QualType Ty) const override;
746 class WebAssemblyTargetCodeGenInfo final : public TargetCodeGenInfo {
748 explicit WebAssemblyTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
749 : TargetCodeGenInfo(new WebAssemblyABIInfo(CGT)) {}
751 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
752 CodeGen::CodeGenModule &CGM) const override {
753 if (auto *FD = dyn_cast_or_null<FunctionDecl>(D)) {
754 llvm::Function *Fn = cast<llvm::Function>(GV);
755 if (!FD->doesThisDeclarationHaveABody() && !FD->hasPrototype())
756 Fn->addFnAttr("no-prototype");
761 /// Classify argument of given type \p Ty.
762 ABIArgInfo WebAssemblyABIInfo::classifyArgumentType(QualType Ty) const {
763 Ty = useFirstFieldIfTransparentUnion(Ty);
765 if (isAggregateTypeForABI(Ty)) {
766 // Records with non-trivial destructors/copy-constructors should not be
768 if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
769 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
770 // Ignore empty structs/unions.
771 if (isEmptyRecord(getContext(), Ty, true))
772 return ABIArgInfo::getIgnore();
773 // Lower single-element structs to just pass a regular value. TODO: We
774 // could do reasonable-size multiple-element structs too, using getExpand(),
775 // though watch out for things like bitfields.
776 if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
777 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
780 // Otherwise just do the default thing.
781 return DefaultABIInfo::classifyArgumentType(Ty);
784 ABIArgInfo WebAssemblyABIInfo::classifyReturnType(QualType RetTy) const {
785 if (isAggregateTypeForABI(RetTy)) {
786 // Records with non-trivial destructors/copy-constructors should not be
787 // returned by value.
788 if (!getRecordArgABI(RetTy, getCXXABI())) {
789 // Ignore empty structs/unions.
790 if (isEmptyRecord(getContext(), RetTy, true))
791 return ABIArgInfo::getIgnore();
792 // Lower single-element structs to just return a regular value. TODO: We
793 // could do reasonable-size multiple-element structs too, using
794 // ABIArgInfo::getDirect().
795 if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
796 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
800 // Otherwise just do the default thing.
801 return DefaultABIInfo::classifyReturnType(RetTy);
804 Address WebAssemblyABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
806 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect=*/ false,
807 getContext().getTypeInfoInChars(Ty),
808 CharUnits::fromQuantity(4),
809 /*AllowHigherAlign=*/ true);
812 //===----------------------------------------------------------------------===//
813 // le32/PNaCl bitcode ABI Implementation
815 // This is a simplified version of the x86_32 ABI. Arguments and return values
816 // are always passed on the stack.
817 //===----------------------------------------------------------------------===//
819 class PNaClABIInfo : public ABIInfo {
821 PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
823 ABIArgInfo classifyReturnType(QualType RetTy) const;
824 ABIArgInfo classifyArgumentType(QualType RetTy) const;
826 void computeInfo(CGFunctionInfo &FI) const override;
827 Address EmitVAArg(CodeGenFunction &CGF,
828 Address VAListAddr, QualType Ty) const override;
831 class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
833 PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
834 : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {}
837 void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
838 if (!getCXXABI().classifyReturnType(FI))
839 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
841 for (auto &I : FI.arguments())
842 I.info = classifyArgumentType(I.type);
845 Address PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
847 // The PNaCL ABI is a bit odd, in that varargs don't use normal
848 // function classification. Structs get passed directly for varargs
849 // functions, through a rewriting transform in
850 // pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows
851 // this target to actually support a va_arg instructions with an
852 // aggregate type, unlike other targets.
853 return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
856 /// Classify argument of given type \p Ty.
857 ABIArgInfo PNaClABIInfo::classifyArgumentType(QualType Ty) const {
858 if (isAggregateTypeForABI(Ty)) {
859 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
860 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
861 return getNaturalAlignIndirect(Ty);
862 } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
863 // Treat an enum type as its underlying type.
864 Ty = EnumTy->getDecl()->getIntegerType();
865 } else if (Ty->isFloatingType()) {
866 // Floating-point types don't go inreg.
867 return ABIArgInfo::getDirect();
870 return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty)
871 : ABIArgInfo::getDirect());
874 ABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const {
875 if (RetTy->isVoidType())
876 return ABIArgInfo::getIgnore();
878 // In the PNaCl ABI we always return records/structures on the stack.
879 if (isAggregateTypeForABI(RetTy))
880 return getNaturalAlignIndirect(RetTy);
882 // Treat an enum type as its underlying type.
883 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
884 RetTy = EnumTy->getDecl()->getIntegerType();
886 return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
887 : ABIArgInfo::getDirect());
890 /// IsX86_MMXType - Return true if this is an MMX type.
891 bool IsX86_MMXType(llvm::Type *IRType) {
892 // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
893 return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
894 cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
895 IRType->getScalarSizeInBits() != 64;
898 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
899 StringRef Constraint,
901 bool IsMMXCons = llvm::StringSwitch<bool>(Constraint)
902 .Cases("y", "&y", "^Ym", true)
904 if (IsMMXCons && Ty->isVectorTy()) {
905 if (cast<llvm::VectorType>(Ty)->getBitWidth() != 64) {
906 // Invalid MMX constraint
910 return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
913 // No operation needed
917 /// Returns true if this type can be passed in SSE registers with the
918 /// X86_VectorCall calling convention. Shared between x86_32 and x86_64.
919 static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) {
920 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
921 if (BT->isFloatingPoint() && BT->getKind() != BuiltinType::Half) {
922 if (BT->getKind() == BuiltinType::LongDouble) {
923 if (&Context.getTargetInfo().getLongDoubleFormat() ==
924 &llvm::APFloat::x87DoubleExtended())
929 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
930 // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX
931 // registers specially.
932 unsigned VecSize = Context.getTypeSize(VT);
933 if (VecSize == 128 || VecSize == 256 || VecSize == 512)
939 /// Returns true if this aggregate is small enough to be passed in SSE registers
940 /// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64.
941 static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) {
942 return NumMembers <= 4;
945 /// Returns a Homogeneous Vector Aggregate ABIArgInfo, used in X86.
946 static ABIArgInfo getDirectX86Hva(llvm::Type* T = nullptr) {
947 auto AI = ABIArgInfo::getDirect(T);
949 AI.setCanBeFlattened(false);
953 //===----------------------------------------------------------------------===//
954 // X86-32 ABI Implementation
955 //===----------------------------------------------------------------------===//
957 /// Similar to llvm::CCState, but for Clang.
959 CCState(unsigned CC) : CC(CC), FreeRegs(0), FreeSSERegs(0) {}
963 unsigned FreeSSERegs;
967 // Vectorcall only allows the first 6 parameters to be passed in registers.
968 VectorcallMaxParamNumAsReg = 6
971 /// X86_32ABIInfo - The X86-32 ABI information.
972 class X86_32ABIInfo : public SwiftABIInfo {
978 static const unsigned MinABIStackAlignInBytes = 4;
980 bool IsDarwinVectorABI;
981 bool IsRetSmallStructInRegABI;
982 bool IsWin32StructABI;
985 unsigned DefaultNumRegisterParameters;
987 static bool isRegisterSize(unsigned Size) {
988 return (Size == 8 || Size == 16 || Size == 32 || Size == 64);
991 bool isHomogeneousAggregateBaseType(QualType Ty) const override {
992 // FIXME: Assumes vectorcall is in use.
993 return isX86VectorTypeForVectorCall(getContext(), Ty);
996 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
997 uint64_t NumMembers) const override {
998 // FIXME: Assumes vectorcall is in use.
999 return isX86VectorCallAggregateSmallEnough(NumMembers);
1002 bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const;
1004 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1005 /// such that the argument will be passed in memory.
1006 ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
1008 ABIArgInfo getIndirectReturnResult(QualType Ty, CCState &State) const;
1010 /// Return the alignment to use for the given type on the stack.
1011 unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const;
1013 Class classify(QualType Ty) const;
1014 ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
1015 ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
1017 /// Updates the number of available free registers, returns
1018 /// true if any registers were allocated.
1019 bool updateFreeRegs(QualType Ty, CCState &State) const;
1021 bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
1022 bool &NeedsPadding) const;
1023 bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const;
1025 bool canExpandIndirectArgument(QualType Ty) const;
1027 /// Rewrite the function info so that all memory arguments use
1029 void rewriteWithInAlloca(CGFunctionInfo &FI) const;
1031 void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1032 CharUnits &StackOffset, ABIArgInfo &Info,
1033 QualType Type) const;
1034 void computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
1035 bool &UsedInAlloca) const;
1039 void computeInfo(CGFunctionInfo &FI) const override;
1040 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1041 QualType Ty) const override;
1043 X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1044 bool RetSmallStructInRegABI, bool Win32StructABI,
1045 unsigned NumRegisterParameters, bool SoftFloatABI)
1046 : SwiftABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
1047 IsRetSmallStructInRegABI(RetSmallStructInRegABI),
1048 IsWin32StructABI(Win32StructABI),
1049 IsSoftFloatABI(SoftFloatABI),
1050 IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()),
1051 DefaultNumRegisterParameters(NumRegisterParameters) {}
1053 bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
1054 bool asReturnValue) const override {
1055 // LLVM's x86-32 lowering currently only assigns up to three
1056 // integer registers and three fp registers. Oddly, it'll use up to
1057 // four vector registers for vectors, but those can overlap with the
1058 // scalar registers.
1059 return occupiesMoreThan(CGT, scalars, /*total*/ 3);
1062 bool isSwiftErrorInRegister() const override {
1063 // x86-32 lowering does not support passing swifterror in a register.
1068 class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
1070 X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1071 bool RetSmallStructInRegABI, bool Win32StructABI,
1072 unsigned NumRegisterParameters, bool SoftFloatABI)
1073 : TargetCodeGenInfo(new X86_32ABIInfo(
1074 CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
1075 NumRegisterParameters, SoftFloatABI)) {}
1077 static bool isStructReturnInRegABI(
1078 const llvm::Triple &Triple, const CodeGenOptions &Opts);
1080 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
1081 CodeGen::CodeGenModule &CGM) const override;
1083 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
1084 // Darwin uses different dwarf register numbers for EH.
1085 if (CGM.getTarget().getTriple().isOSDarwin()) return 5;
1089 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1090 llvm::Value *Address) const override;
1092 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
1093 StringRef Constraint,
1094 llvm::Type* Ty) const override {
1095 return X86AdjustInlineAsmType(CGF, Constraint, Ty);
1098 void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue,
1099 std::string &Constraints,
1100 std::vector<llvm::Type *> &ResultRegTypes,
1101 std::vector<llvm::Type *> &ResultTruncRegTypes,
1102 std::vector<LValue> &ResultRegDests,
1103 std::string &AsmString,
1104 unsigned NumOutputs) const override;
1107 getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
1108 unsigned Sig = (0xeb << 0) | // jmp rel8
1109 (0x06 << 8) | // .+0x08
1112 return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
1115 StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
1116 return "movl\t%ebp, %ebp"
1117 "\t\t// marker for objc_retainAutoreleaseReturnValue";
1123 /// Rewrite input constraint references after adding some output constraints.
1124 /// In the case where there is one output and one input and we add one output,
1125 /// we need to replace all operand references greater than or equal to 1:
1128 /// The result will be:
1131 static void rewriteInputConstraintReferences(unsigned FirstIn,
1132 unsigned NumNewOuts,
1133 std::string &AsmString) {
1135 llvm::raw_string_ostream OS(Buf);
1137 while (Pos < AsmString.size()) {
1138 size_t DollarStart = AsmString.find('$', Pos);
1139 if (DollarStart == std::string::npos)
1140 DollarStart = AsmString.size();
1141 size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart);
1142 if (DollarEnd == std::string::npos)
1143 DollarEnd = AsmString.size();
1144 OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
1146 size_t NumDollars = DollarEnd - DollarStart;
1147 if (NumDollars % 2 != 0 && Pos < AsmString.size()) {
1148 // We have an operand reference.
1149 size_t DigitStart = Pos;
1150 size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart);
1151 if (DigitEnd == std::string::npos)
1152 DigitEnd = AsmString.size();
1153 StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
1154 unsigned OperandIndex;
1155 if (!OperandStr.getAsInteger(10, OperandIndex)) {
1156 if (OperandIndex >= FirstIn)
1157 OperandIndex += NumNewOuts;
1165 AsmString = std::move(OS.str());
1168 /// Add output constraints for EAX:EDX because they are return registers.
1169 void X86_32TargetCodeGenInfo::addReturnRegisterOutputs(
1170 CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints,
1171 std::vector<llvm::Type *> &ResultRegTypes,
1172 std::vector<llvm::Type *> &ResultTruncRegTypes,
1173 std::vector<LValue> &ResultRegDests, std::string &AsmString,
1174 unsigned NumOutputs) const {
1175 uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType());
1177 // Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is
1179 if (!Constraints.empty())
1181 if (RetWidth <= 32) {
1182 Constraints += "={eax}";
1183 ResultRegTypes.push_back(CGF.Int32Ty);
1185 // Use the 'A' constraint for EAX:EDX.
1186 Constraints += "=A";
1187 ResultRegTypes.push_back(CGF.Int64Ty);
1190 // Truncate EAX or EAX:EDX to an integer of the appropriate size.
1191 llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth);
1192 ResultTruncRegTypes.push_back(CoerceTy);
1194 // Coerce the integer by bitcasting the return slot pointer.
1195 ReturnSlot.setAddress(CGF.Builder.CreateBitCast(ReturnSlot.getAddress(),
1196 CoerceTy->getPointerTo()));
1197 ResultRegDests.push_back(ReturnSlot);
1199 rewriteInputConstraintReferences(NumOutputs, 1, AsmString);
1202 /// shouldReturnTypeInRegister - Determine if the given type should be
1203 /// returned in a register (for the Darwin and MCU ABI).
1204 bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
1205 ASTContext &Context) const {
1206 uint64_t Size = Context.getTypeSize(Ty);
1208 // For i386, type must be register sized.
1209 // For the MCU ABI, it only needs to be <= 8-byte
1210 if ((IsMCUABI && Size > 64) || (!IsMCUABI && !isRegisterSize(Size)))
1213 if (Ty->isVectorType()) {
1214 // 64- and 128- bit vectors inside structures are not returned in
1216 if (Size == 64 || Size == 128)
1222 // If this is a builtin, pointer, enum, complex type, member pointer, or
1223 // member function pointer it is ok.
1224 if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() ||
1225 Ty->isAnyComplexType() || Ty->isEnumeralType() ||
1226 Ty->isBlockPointerType() || Ty->isMemberPointerType())
1229 // Arrays are treated like records.
1230 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty))
1231 return shouldReturnTypeInRegister(AT->getElementType(), Context);
1233 // Otherwise, it must be a record type.
1234 const RecordType *RT = Ty->getAs<RecordType>();
1235 if (!RT) return false;
1237 // FIXME: Traverse bases here too.
1239 // Structure types are passed in register if all fields would be
1240 // passed in a register.
1241 for (const auto *FD : RT->getDecl()->fields()) {
1242 // Empty fields are ignored.
1243 if (isEmptyField(Context, FD, true))
1246 // Check fields recursively.
1247 if (!shouldReturnTypeInRegister(FD->getType(), Context))
1253 static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) {
1254 // Treat complex types as the element type.
1255 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
1256 Ty = CTy->getElementType();
1258 // Check for a type which we know has a simple scalar argument-passing
1259 // convention without any padding. (We're specifically looking for 32
1260 // and 64-bit integer and integer-equivalents, float, and double.)
1261 if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() &&
1262 !Ty->isEnumeralType() && !Ty->isBlockPointerType())
1265 uint64_t Size = Context.getTypeSize(Ty);
1266 return Size == 32 || Size == 64;
1269 static bool addFieldSizes(ASTContext &Context, const RecordDecl *RD,
1271 for (const auto *FD : RD->fields()) {
1272 // Scalar arguments on the stack get 4 byte alignment on x86. If the
1273 // argument is smaller than 32-bits, expanding the struct will create
1274 // alignment padding.
1275 if (!is32Or64BitBasicType(FD->getType(), Context))
1278 // FIXME: Reject bit-fields wholesale; there are two problems, we don't know
1279 // how to expand them yet, and the predicate for telling if a bitfield still
1280 // counts as "basic" is more complicated than what we were doing previously.
1281 if (FD->isBitField())
1284 Size += Context.getTypeSize(FD->getType());
1289 static bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD,
1291 // Don't do this if there are any non-empty bases.
1292 for (const CXXBaseSpecifier &Base : RD->bases()) {
1293 if (!addBaseAndFieldSizes(Context, Base.getType()->getAsCXXRecordDecl(),
1297 if (!addFieldSizes(Context, RD, Size))
1302 /// Test whether an argument type which is to be passed indirectly (on the
1303 /// stack) would have the equivalent layout if it was expanded into separate
1304 /// arguments. If so, we prefer to do the latter to avoid inhibiting
1306 bool X86_32ABIInfo::canExpandIndirectArgument(QualType Ty) const {
1307 // We can only expand structure types.
1308 const RecordType *RT = Ty->getAs<RecordType>();
1311 const RecordDecl *RD = RT->getDecl();
1313 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
1314 if (!IsWin32StructABI) {
1315 // On non-Windows, we have to conservatively match our old bitcode
1316 // prototypes in order to be ABI-compatible at the bitcode level.
1317 if (!CXXRD->isCLike())
1320 // Don't do this for dynamic classes.
1321 if (CXXRD->isDynamicClass())
1324 if (!addBaseAndFieldSizes(getContext(), CXXRD, Size))
1327 if (!addFieldSizes(getContext(), RD, Size))
1331 // We can do this if there was no alignment padding.
1332 return Size == getContext().getTypeSize(Ty);
1335 ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(QualType RetTy, CCState &State) const {
1336 // If the return value is indirect, then the hidden argument is consuming one
1337 // integer register.
1338 if (State.FreeRegs) {
1341 return getNaturalAlignIndirectInReg(RetTy);
1343 return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
1346 ABIArgInfo X86_32ABIInfo::classifyReturnType(QualType RetTy,
1347 CCState &State) const {
1348 if (RetTy->isVoidType())
1349 return ABIArgInfo::getIgnore();
1351 const Type *Base = nullptr;
1352 uint64_t NumElts = 0;
1353 if ((State.CC == llvm::CallingConv::X86_VectorCall ||
1354 State.CC == llvm::CallingConv::X86_RegCall) &&
1355 isHomogeneousAggregate(RetTy, Base, NumElts)) {
1356 // The LLVM struct type for such an aggregate should lower properly.
1357 return ABIArgInfo::getDirect();
1360 if (const VectorType *VT = RetTy->getAs<VectorType>()) {
1361 // On Darwin, some vectors are returned in registers.
1362 if (IsDarwinVectorABI) {
1363 uint64_t Size = getContext().getTypeSize(RetTy);
1365 // 128-bit vectors are a special case; they are returned in
1366 // registers and we need to make sure to pick a type the LLVM
1367 // backend will like.
1369 return ABIArgInfo::getDirect(llvm::VectorType::get(
1370 llvm::Type::getInt64Ty(getVMContext()), 2));
1372 // Always return in register if it fits in a general purpose
1373 // register, or if it is 64 bits and has a single element.
1374 if ((Size == 8 || Size == 16 || Size == 32) ||
1375 (Size == 64 && VT->getNumElements() == 1))
1376 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1379 return getIndirectReturnResult(RetTy, State);
1382 return ABIArgInfo::getDirect();
1385 if (isAggregateTypeForABI(RetTy)) {
1386 if (const RecordType *RT = RetTy->getAs<RecordType>()) {
1387 // Structures with flexible arrays are always indirect.
1388 if (RT->getDecl()->hasFlexibleArrayMember())
1389 return getIndirectReturnResult(RetTy, State);
1392 // If specified, structs and unions are always indirect.
1393 if (!IsRetSmallStructInRegABI && !RetTy->isAnyComplexType())
1394 return getIndirectReturnResult(RetTy, State);
1396 // Ignore empty structs/unions.
1397 if (isEmptyRecord(getContext(), RetTy, true))
1398 return ABIArgInfo::getIgnore();
1400 // Small structures which are register sized are generally returned
1402 if (shouldReturnTypeInRegister(RetTy, getContext())) {
1403 uint64_t Size = getContext().getTypeSize(RetTy);
1405 // As a special-case, if the struct is a "single-element" struct, and
1406 // the field is of type "float" or "double", return it in a
1407 // floating-point register. (MSVC does not apply this special case.)
1408 // We apply a similar transformation for pointer types to improve the
1409 // quality of the generated IR.
1410 if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
1411 if ((!IsWin32StructABI && SeltTy->isRealFloatingType())
1412 || SeltTy->hasPointerRepresentation())
1413 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
1415 // FIXME: We should be able to narrow this integer in cases with dead
1417 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size));
1420 return getIndirectReturnResult(RetTy, State);
1423 // Treat an enum type as its underlying type.
1424 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
1425 RetTy = EnumTy->getDecl()->getIntegerType();
1427 return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
1428 : ABIArgInfo::getDirect());
1431 static bool isSSEVectorType(ASTContext &Context, QualType Ty) {
1432 return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128;
1435 static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) {
1436 const RecordType *RT = Ty->getAs<RecordType>();
1439 const RecordDecl *RD = RT->getDecl();
1441 // If this is a C++ record, check the bases first.
1442 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
1443 for (const auto &I : CXXRD->bases())
1444 if (!isRecordWithSSEVectorType(Context, I.getType()))
1447 for (const auto *i : RD->fields()) {
1448 QualType FT = i->getType();
1450 if (isSSEVectorType(Context, FT))
1453 if (isRecordWithSSEVectorType(Context, FT))
1460 unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty,
1461 unsigned Align) const {
1462 // Otherwise, if the alignment is less than or equal to the minimum ABI
1463 // alignment, just use the default; the backend will handle this.
1464 if (Align <= MinABIStackAlignInBytes)
1465 return 0; // Use default alignment.
1467 // On non-Darwin, the stack type alignment is always 4.
1468 if (!IsDarwinVectorABI) {
1469 // Set explicit alignment, since we may need to realign the top.
1470 return MinABIStackAlignInBytes;
1473 // Otherwise, if the type contains an SSE vector type, the alignment is 16.
1474 if (Align >= 16 && (isSSEVectorType(getContext(), Ty) ||
1475 isRecordWithSSEVectorType(getContext(), Ty)))
1478 return MinABIStackAlignInBytes;
1481 ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal,
1482 CCState &State) const {
1484 if (State.FreeRegs) {
1485 --State.FreeRegs; // Non-byval indirects just use one pointer.
1487 return getNaturalAlignIndirectInReg(Ty);
1489 return getNaturalAlignIndirect(Ty, false);
1492 // Compute the byval alignment.
1493 unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
1494 unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign);
1495 if (StackAlign == 0)
1496 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true);
1498 // If the stack alignment is less than the type alignment, realign the
1500 bool Realign = TypeAlign > StackAlign;
1501 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(StackAlign),
1502 /*ByVal=*/true, Realign);
1505 X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const {
1506 const Type *T = isSingleElementStruct(Ty, getContext());
1508 T = Ty.getTypePtr();
1510 if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
1511 BuiltinType::Kind K = BT->getKind();
1512 if (K == BuiltinType::Float || K == BuiltinType::Double)
1518 bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const {
1519 if (!IsSoftFloatABI) {
1520 Class C = classify(Ty);
1525 unsigned Size = getContext().getTypeSize(Ty);
1526 unsigned SizeInRegs = (Size + 31) / 32;
1528 if (SizeInRegs == 0)
1532 if (SizeInRegs > State.FreeRegs) {
1537 // The MCU psABI allows passing parameters in-reg even if there are
1538 // earlier parameters that are passed on the stack. Also,
1539 // it does not allow passing >8-byte structs in-register,
1540 // even if there are 3 free registers available.
1541 if (SizeInRegs > State.FreeRegs || SizeInRegs > 2)
1545 State.FreeRegs -= SizeInRegs;
1549 bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State,
1551 bool &NeedsPadding) const {
1552 // On Windows, aggregates other than HFAs are never passed in registers, and
1553 // they do not consume register slots. Homogenous floating-point aggregates
1554 // (HFAs) have already been dealt with at this point.
1555 if (IsWin32StructABI && isAggregateTypeForABI(Ty))
1558 NeedsPadding = false;
1561 if (!updateFreeRegs(Ty, State))
1567 if (State.CC == llvm::CallingConv::X86_FastCall ||
1568 State.CC == llvm::CallingConv::X86_VectorCall ||
1569 State.CC == llvm::CallingConv::X86_RegCall) {
1570 if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs)
1571 NeedsPadding = true;
1579 bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const {
1580 if (!updateFreeRegs(Ty, State))
1586 if (State.CC == llvm::CallingConv::X86_FastCall ||
1587 State.CC == llvm::CallingConv::X86_VectorCall ||
1588 State.CC == llvm::CallingConv::X86_RegCall) {
1589 if (getContext().getTypeSize(Ty) > 32)
1592 return (Ty->isIntegralOrEnumerationType() || Ty->isPointerType() ||
1593 Ty->isReferenceType());
1599 ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
1600 CCState &State) const {
1601 // FIXME: Set alignment on indirect arguments.
1603 Ty = useFirstFieldIfTransparentUnion(Ty);
1605 // Check with the C++ ABI first.
1606 const RecordType *RT = Ty->getAs<RecordType>();
1608 CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
1609 if (RAA == CGCXXABI::RAA_Indirect) {
1610 return getIndirectResult(Ty, false, State);
1611 } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
1612 // The field index doesn't matter, we'll fix it up later.
1613 return ABIArgInfo::getInAlloca(/*FieldIndex=*/0);
1617 // Regcall uses the concept of a homogenous vector aggregate, similar
1618 // to other targets.
1619 const Type *Base = nullptr;
1620 uint64_t NumElts = 0;
1621 if (State.CC == llvm::CallingConv::X86_RegCall &&
1622 isHomogeneousAggregate(Ty, Base, NumElts)) {
1624 if (State.FreeSSERegs >= NumElts) {
1625 State.FreeSSERegs -= NumElts;
1626 if (Ty->isBuiltinType() || Ty->isVectorType())
1627 return ABIArgInfo::getDirect();
1628 return ABIArgInfo::getExpand();
1630 return getIndirectResult(Ty, /*ByVal=*/false, State);
1633 if (isAggregateTypeForABI(Ty)) {
1634 // Structures with flexible arrays are always indirect.
1635 // FIXME: This should not be byval!
1636 if (RT && RT->getDecl()->hasFlexibleArrayMember())
1637 return getIndirectResult(Ty, true, State);
1639 // Ignore empty structs/unions on non-Windows.
1640 if (!IsWin32StructABI && isEmptyRecord(getContext(), Ty, true))
1641 return ABIArgInfo::getIgnore();
1643 llvm::LLVMContext &LLVMContext = getVMContext();
1644 llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
1645 bool NeedsPadding = false;
1647 if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
1648 unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
1649 SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
1650 llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
1652 return ABIArgInfo::getDirectInReg(Result);
1654 return ABIArgInfo::getDirect(Result);
1656 llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr;
1658 // Expand small (<= 128-bit) record types when we know that the stack layout
1659 // of those arguments will match the struct. This is important because the
1660 // LLVM backend isn't smart enough to remove byval, which inhibits many
1662 // Don't do this for the MCU if there are still free integer registers
1663 // (see X86_64 ABI for full explanation).
1664 if (getContext().getTypeSize(Ty) <= 4 * 32 &&
1665 (!IsMCUABI || State.FreeRegs == 0) && canExpandIndirectArgument(Ty))
1666 return ABIArgInfo::getExpandWithPadding(
1667 State.CC == llvm::CallingConv::X86_FastCall ||
1668 State.CC == llvm::CallingConv::X86_VectorCall ||
1669 State.CC == llvm::CallingConv::X86_RegCall,
1672 return getIndirectResult(Ty, true, State);
1675 if (const VectorType *VT = Ty->getAs<VectorType>()) {
1676 // On Darwin, some vectors are passed in memory, we handle this by passing
1677 // it as an i8/i16/i32/i64.
1678 if (IsDarwinVectorABI) {
1679 uint64_t Size = getContext().getTypeSize(Ty);
1680 if ((Size == 8 || Size == 16 || Size == 32) ||
1681 (Size == 64 && VT->getNumElements() == 1))
1682 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1686 if (IsX86_MMXType(CGT.ConvertType(Ty)))
1687 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
1689 return ABIArgInfo::getDirect();
1693 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
1694 Ty = EnumTy->getDecl()->getIntegerType();
1696 bool InReg = shouldPrimitiveUseInReg(Ty, State);
1698 if (Ty->isPromotableIntegerType()) {
1700 return ABIArgInfo::getExtendInReg(Ty);
1701 return ABIArgInfo::getExtend(Ty);
1705 return ABIArgInfo::getDirectInReg();
1706 return ABIArgInfo::getDirect();
1709 void X86_32ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
1710 bool &UsedInAlloca) const {
1711 // Vectorcall x86 works subtly different than in x64, so the format is
1712 // a bit different than the x64 version. First, all vector types (not HVAs)
1713 // are assigned, with the first 6 ending up in the YMM0-5 or XMM0-5 registers.
1714 // This differs from the x64 implementation, where the first 6 by INDEX get
1716 // After that, integers AND HVAs are assigned Left to Right in the same pass.
1717 // Integers are passed as ECX/EDX if one is available (in order). HVAs will
1718 // first take up the remaining YMM/XMM registers. If insufficient registers
1719 // remain but an integer register (ECX/EDX) is available, it will be passed
1720 // in that, else, on the stack.
1721 for (auto &I : FI.arguments()) {
1722 // First pass do all the vector types.
1723 const Type *Base = nullptr;
1724 uint64_t NumElts = 0;
1725 const QualType& Ty = I.type;
1726 if ((Ty->isVectorType() || Ty->isBuiltinType()) &&
1727 isHomogeneousAggregate(Ty, Base, NumElts)) {
1728 if (State.FreeSSERegs >= NumElts) {
1729 State.FreeSSERegs -= NumElts;
1730 I.info = ABIArgInfo::getDirect();
1732 I.info = classifyArgumentType(Ty, State);
1734 UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1738 for (auto &I : FI.arguments()) {
1739 // Second pass, do the rest!
1740 const Type *Base = nullptr;
1741 uint64_t NumElts = 0;
1742 const QualType& Ty = I.type;
1743 bool IsHva = isHomogeneousAggregate(Ty, Base, NumElts);
1745 if (IsHva && !Ty->isVectorType() && !Ty->isBuiltinType()) {
1746 // Assign true HVAs (non vector/native FP types).
1747 if (State.FreeSSERegs >= NumElts) {
1748 State.FreeSSERegs -= NumElts;
1749 I.info = getDirectX86Hva();
1751 I.info = getIndirectResult(Ty, /*ByVal=*/false, State);
1753 } else if (!IsHva) {
1754 // Assign all Non-HVAs, so this will exclude Vector/FP args.
1755 I.info = classifyArgumentType(Ty, State);
1756 UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1761 void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
1762 CCState State(FI.getCallingConvention());
1765 else if (State.CC == llvm::CallingConv::X86_FastCall)
1767 else if (State.CC == llvm::CallingConv::X86_VectorCall) {
1769 State.FreeSSERegs = 6;
1770 } else if (FI.getHasRegParm())
1771 State.FreeRegs = FI.getRegParm();
1772 else if (State.CC == llvm::CallingConv::X86_RegCall) {
1774 State.FreeSSERegs = 8;
1776 State.FreeRegs = DefaultNumRegisterParameters;
1778 if (!::classifyReturnType(getCXXABI(), FI, *this)) {
1779 FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), State);
1780 } else if (FI.getReturnInfo().isIndirect()) {
1781 // The C++ ABI is not aware of register usage, so we have to check if the
1782 // return value was sret and put it in a register ourselves if appropriate.
1783 if (State.FreeRegs) {
1784 --State.FreeRegs; // The sret parameter consumes a register.
1786 FI.getReturnInfo().setInReg(true);
1790 // The chain argument effectively gives us another free register.
1791 if (FI.isChainCall())
1794 bool UsedInAlloca = false;
1795 if (State.CC == llvm::CallingConv::X86_VectorCall) {
1796 computeVectorCallArgs(FI, State, UsedInAlloca);
1798 // If not vectorcall, revert to normal behavior.
1799 for (auto &I : FI.arguments()) {
1800 I.info = classifyArgumentType(I.type, State);
1801 UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1805 // If we needed to use inalloca for any argument, do a second pass and rewrite
1806 // all the memory arguments to use inalloca.
1808 rewriteWithInAlloca(FI);
1812 X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1813 CharUnits &StackOffset, ABIArgInfo &Info,
1814 QualType Type) const {
1815 // Arguments are always 4-byte-aligned.
1816 CharUnits FieldAlign = CharUnits::fromQuantity(4);
1818 assert(StackOffset.isMultipleOf(FieldAlign) && "unaligned inalloca struct");
1819 Info = ABIArgInfo::getInAlloca(FrameFields.size());
1820 FrameFields.push_back(CGT.ConvertTypeForMem(Type));
1821 StackOffset += getContext().getTypeSizeInChars(Type);
1823 // Insert padding bytes to respect alignment.
1824 CharUnits FieldEnd = StackOffset;
1825 StackOffset = FieldEnd.alignTo(FieldAlign);
1826 if (StackOffset != FieldEnd) {
1827 CharUnits NumBytes = StackOffset - FieldEnd;
1828 llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
1829 Ty = llvm::ArrayType::get(Ty, NumBytes.getQuantity());
1830 FrameFields.push_back(Ty);
1834 static bool isArgInAlloca(const ABIArgInfo &Info) {
1835 // Leave ignored and inreg arguments alone.
1836 switch (Info.getKind()) {
1837 case ABIArgInfo::InAlloca:
1839 case ABIArgInfo::Indirect:
1840 assert(Info.getIndirectByVal());
1842 case ABIArgInfo::Ignore:
1844 case ABIArgInfo::Direct:
1845 case ABIArgInfo::Extend:
1846 if (Info.getInReg())
1849 case ABIArgInfo::Expand:
1850 case ABIArgInfo::CoerceAndExpand:
1851 // These are aggregate types which are never passed in registers when
1852 // inalloca is involved.
1855 llvm_unreachable("invalid enum");
1858 void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
1859 assert(IsWin32StructABI && "inalloca only supported on win32");
1861 // Build a packed struct type for all of the arguments in memory.
1862 SmallVector<llvm::Type *, 6> FrameFields;
1864 // The stack alignment is always 4.
1865 CharUnits StackAlign = CharUnits::fromQuantity(4);
1867 CharUnits StackOffset;
1868 CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end();
1870 // Put 'this' into the struct before 'sret', if necessary.
1872 FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
1873 ABIArgInfo &Ret = FI.getReturnInfo();
1874 if (Ret.isIndirect() && Ret.isSRetAfterThis() && !IsThisCall &&
1875 isArgInAlloca(I->info)) {
1876 addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1880 // Put the sret parameter into the inalloca struct if it's in memory.
1881 if (Ret.isIndirect() && !Ret.getInReg()) {
1882 CanQualType PtrTy = getContext().getPointerType(FI.getReturnType());
1883 addFieldToArgStruct(FrameFields, StackOffset, Ret, PtrTy);
1884 // On Windows, the hidden sret parameter is always returned in eax.
1885 Ret.setInAllocaSRet(IsWin32StructABI);
1888 // Skip the 'this' parameter in ecx.
1892 // Put arguments passed in memory into the struct.
1893 for (; I != E; ++I) {
1894 if (isArgInAlloca(I->info))
1895 addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1898 FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
1903 Address X86_32ABIInfo::EmitVAArg(CodeGenFunction &CGF,
1904 Address VAListAddr, QualType Ty) const {
1906 auto TypeInfo = getContext().getTypeInfoInChars(Ty);
1908 // x86-32 changes the alignment of certain arguments on the stack.
1910 // Just messing with TypeInfo like this works because we never pass
1911 // anything indirectly.
1912 TypeInfo.second = CharUnits::fromQuantity(
1913 getTypeStackAlignInBytes(Ty, TypeInfo.second.getQuantity()));
1915 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
1916 TypeInfo, CharUnits::fromQuantity(4),
1917 /*AllowHigherAlign*/ true);
1920 bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
1921 const llvm::Triple &Triple, const CodeGenOptions &Opts) {
1922 assert(Triple.getArch() == llvm::Triple::x86);
1924 switch (Opts.getStructReturnConvention()) {
1925 case CodeGenOptions::SRCK_Default:
1927 case CodeGenOptions::SRCK_OnStack: // -fpcc-struct-return
1929 case CodeGenOptions::SRCK_InRegs: // -freg-struct-return
1933 if (Triple.isOSDarwin() || Triple.isOSIAMCU())
1936 switch (Triple.getOS()) {
1937 case llvm::Triple::DragonFly:
1938 case llvm::Triple::FreeBSD:
1939 case llvm::Triple::OpenBSD:
1940 case llvm::Triple::Win32:
1947 void X86_32TargetCodeGenInfo::setTargetAttributes(
1948 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
1949 if (GV->isDeclaration())
1951 if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
1952 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1953 llvm::Function *Fn = cast<llvm::Function>(GV);
1954 Fn->addFnAttr("stackrealign");
1956 if (FD->hasAttr<AnyX86InterruptAttr>()) {
1957 llvm::Function *Fn = cast<llvm::Function>(GV);
1958 Fn->setCallingConv(llvm::CallingConv::X86_INTR);
1963 bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
1964 CodeGen::CodeGenFunction &CGF,
1965 llvm::Value *Address) const {
1966 CodeGen::CGBuilderTy &Builder = CGF.Builder;
1968 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
1970 // 0-7 are the eight integer registers; the order is different
1971 // on Darwin (for EH), but the range is the same.
1973 AssignToArrayRange(Builder, Address, Four8, 0, 8);
1975 if (CGF.CGM.getTarget().getTriple().isOSDarwin()) {
1976 // 12-16 are st(0..4). Not sure why we stop at 4.
1977 // These have size 16, which is sizeof(long double) on
1978 // platforms with 8-byte alignment for that type.
1979 llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
1980 AssignToArrayRange(Builder, Address, Sixteen8, 12, 16);
1983 // 9 is %eflags, which doesn't get a size on Darwin for some
1985 Builder.CreateAlignedStore(
1986 Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9),
1989 // 11-16 are st(0..5). Not sure why we stop at 5.
1990 // These have size 12, which is sizeof(long double) on
1991 // platforms with 4-byte alignment for that type.
1992 llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12);
1993 AssignToArrayRange(Builder, Address, Twelve8, 11, 16);
1999 //===----------------------------------------------------------------------===//
2000 // X86-64 ABI Implementation
2001 //===----------------------------------------------------------------------===//
2005 /// The AVX ABI level for X86 targets.
2006 enum class X86AVXABILevel {
2012 /// \p returns the size in bits of the largest (native) vector for \p AVXLevel.
2013 static unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) {
2015 case X86AVXABILevel::AVX512:
2017 case X86AVXABILevel::AVX:
2019 case X86AVXABILevel::None:
2022 llvm_unreachable("Unknown AVXLevel");
2025 /// X86_64ABIInfo - The X86_64 ABI information.
2026 class X86_64ABIInfo : public SwiftABIInfo {
2038 /// merge - Implement the X86_64 ABI merging algorithm.
2040 /// Merge an accumulating classification \arg Accum with a field
2041 /// classification \arg Field.
2043 /// \param Accum - The accumulating classification. This should
2044 /// always be either NoClass or the result of a previous merge
2045 /// call. In addition, this should never be Memory (the caller
2046 /// should just return Memory for the aggregate).
2047 static Class merge(Class Accum, Class Field);
2049 /// postMerge - Implement the X86_64 ABI post merging algorithm.
2051 /// Post merger cleanup, reduces a malformed Hi and Lo pair to
2052 /// final MEMORY or SSE classes when necessary.
2054 /// \param AggregateSize - The size of the current aggregate in
2055 /// the classification process.
2057 /// \param Lo - The classification for the parts of the type
2058 /// residing in the low word of the containing object.
2060 /// \param Hi - The classification for the parts of the type
2061 /// residing in the higher words of the containing object.
2063 void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
2065 /// classify - Determine the x86_64 register classes in which the
2066 /// given type T should be passed.
2068 /// \param Lo - The classification for the parts of the type
2069 /// residing in the low word of the containing object.
2071 /// \param Hi - The classification for the parts of the type
2072 /// residing in the high word of the containing object.
2074 /// \param OffsetBase - The bit offset of this type in the
2075 /// containing object. Some parameters are classified different
2076 /// depending on whether they straddle an eightbyte boundary.
2078 /// \param isNamedArg - Whether the argument in question is a "named"
2079 /// argument, as used in AMD64-ABI 3.5.7.
2081 /// If a word is unused its result will be NoClass; if a type should
2082 /// be passed in Memory then at least the classification of \arg Lo
2085 /// The \arg Lo class will be NoClass iff the argument is ignored.
2087 /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
2088 /// also be ComplexX87.
2089 void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
2090 bool isNamedArg) const;
2092 llvm::Type *GetByteVectorType(QualType Ty) const;
2093 llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType,
2094 unsigned IROffset, QualType SourceTy,
2095 unsigned SourceOffset) const;
2096 llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType,
2097 unsigned IROffset, QualType SourceTy,
2098 unsigned SourceOffset) const;
2100 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2101 /// such that the argument will be returned in memory.
2102 ABIArgInfo getIndirectReturnResult(QualType Ty) const;
2104 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2105 /// such that the argument will be passed in memory.
2107 /// \param freeIntRegs - The number of free integer registers remaining
2109 ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const;
2111 ABIArgInfo classifyReturnType(QualType RetTy) const;
2113 ABIArgInfo classifyArgumentType(QualType Ty, unsigned freeIntRegs,
2114 unsigned &neededInt, unsigned &neededSSE,
2115 bool isNamedArg) const;
2117 ABIArgInfo classifyRegCallStructType(QualType Ty, unsigned &NeededInt,
2118 unsigned &NeededSSE) const;
2120 ABIArgInfo classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
2121 unsigned &NeededSSE) const;
2123 bool IsIllegalVectorType(QualType Ty) const;
2125 /// The 0.98 ABI revision clarified a lot of ambiguities,
2126 /// unfortunately in ways that were not always consistent with
2127 /// certain previous compilers. In particular, platforms which
2128 /// required strict binary compatibility with older versions of GCC
2129 /// may need to exempt themselves.
2130 bool honorsRevision0_98() const {
2131 return !getTarget().getTriple().isOSDarwin();
2134 /// GCC classifies <1 x long long> as SSE but some platform ABIs choose to
2135 /// classify it as INTEGER (for compatibility with older clang compilers).
2136 bool classifyIntegerMMXAsSSE() const {
2137 // Clang <= 3.8 did not do this.
2138 if (getContext().getLangOpts().getClangABICompat() <=
2139 LangOptions::ClangABI::Ver3_8)
2142 const llvm::Triple &Triple = getTarget().getTriple();
2143 if (Triple.isOSDarwin() || Triple.getOS() == llvm::Triple::PS4)
2145 if (Triple.isOSFreeBSD() && Triple.getOSMajorVersion() >= 10)
2150 X86AVXABILevel AVXLevel;
2151 // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on
2153 bool Has64BitPointers;
2156 X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) :
2157 SwiftABIInfo(CGT), AVXLevel(AVXLevel),
2158 Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) {
2161 bool isPassedUsingAVXType(QualType type) const {
2162 unsigned neededInt, neededSSE;
2163 // The freeIntRegs argument doesn't matter here.
2164 ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE,
2165 /*isNamedArg*/true);
2166 if (info.isDirect()) {
2167 llvm::Type *ty = info.getCoerceToType();
2168 if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty))
2169 return (vectorTy->getBitWidth() > 128);
2174 void computeInfo(CGFunctionInfo &FI) const override;
2176 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2177 QualType Ty) const override;
2178 Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
2179 QualType Ty) const override;
2181 bool has64BitPointers() const {
2182 return Has64BitPointers;
2185 bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
2186 bool asReturnValue) const override {
2187 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2189 bool isSwiftErrorInRegister() const override {
2194 /// WinX86_64ABIInfo - The Windows X86_64 ABI information.
2195 class WinX86_64ABIInfo : public SwiftABIInfo {
2197 WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT)
2198 : SwiftABIInfo(CGT),
2199 IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {}
2201 void computeInfo(CGFunctionInfo &FI) const override;
2203 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2204 QualType Ty) const override;
2206 bool isHomogeneousAggregateBaseType(QualType Ty) const override {
2207 // FIXME: Assumes vectorcall is in use.
2208 return isX86VectorTypeForVectorCall(getContext(), Ty);
2211 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
2212 uint64_t NumMembers) const override {
2213 // FIXME: Assumes vectorcall is in use.
2214 return isX86VectorCallAggregateSmallEnough(NumMembers);
2217 bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type *> scalars,
2218 bool asReturnValue) const override {
2219 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2222 bool isSwiftErrorInRegister() const override {
2227 ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs, bool IsReturnType,
2228 bool IsVectorCall, bool IsRegCall) const;
2229 ABIArgInfo reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
2230 const ABIArgInfo ¤t) const;
2231 void computeVectorCallArgs(CGFunctionInfo &FI, unsigned FreeSSERegs,
2232 bool IsVectorCall, bool IsRegCall) const;
2237 class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2239 X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2240 : TargetCodeGenInfo(new X86_64ABIInfo(CGT, AVXLevel)) {}
2242 const X86_64ABIInfo &getABIInfo() const {
2243 return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo());
2246 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2250 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2251 llvm::Value *Address) const override {
2252 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2254 // 0-15 are the 16 integer registers.
2256 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2260 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
2261 StringRef Constraint,
2262 llvm::Type* Ty) const override {
2263 return X86AdjustInlineAsmType(CGF, Constraint, Ty);
2266 bool isNoProtoCallVariadic(const CallArgList &args,
2267 const FunctionNoProtoType *fnType) const override {
2268 // The default CC on x86-64 sets %al to the number of SSA
2269 // registers used, and GCC sets this when calling an unprototyped
2270 // function, so we override the default behavior. However, don't do
2271 // that when AVX types are involved: the ABI explicitly states it is
2272 // undefined, and it doesn't work in practice because of how the ABI
2273 // defines varargs anyway.
2274 if (fnType->getCallConv() == CC_C) {
2275 bool HasAVXType = false;
2276 for (CallArgList::const_iterator
2277 it = args.begin(), ie = args.end(); it != ie; ++it) {
2278 if (getABIInfo().isPassedUsingAVXType(it->Ty)) {
2288 return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType);
2292 getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
2293 unsigned Sig = (0xeb << 0) | // jmp rel8
2294 (0x06 << 8) | // .+0x08
2297 return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
2300 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2301 CodeGen::CodeGenModule &CGM) const override {
2302 if (GV->isDeclaration())
2304 if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2305 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2306 llvm::Function *Fn = cast<llvm::Function>(GV);
2307 Fn->addFnAttr("stackrealign");
2309 if (FD->hasAttr<AnyX86InterruptAttr>()) {
2310 llvm::Function *Fn = cast<llvm::Function>(GV);
2311 Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2317 class PS4TargetCodeGenInfo : public X86_64TargetCodeGenInfo {
2319 PS4TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2320 : X86_64TargetCodeGenInfo(CGT, AVXLevel) {}
2322 void getDependentLibraryOption(llvm::StringRef Lib,
2323 llvm::SmallString<24> &Opt) const override {
2325 // If the argument contains a space, enclose it in quotes.
2326 if (Lib.find(" ") != StringRef::npos)
2327 Opt += "\"" + Lib.str() + "\"";
2333 static std::string qualifyWindowsLibrary(llvm::StringRef Lib) {
2334 // If the argument does not end in .lib, automatically add the suffix.
2335 // If the argument contains a space, enclose it in quotes.
2336 // This matches the behavior of MSVC.
2337 bool Quote = (Lib.find(" ") != StringRef::npos);
2338 std::string ArgStr = Quote ? "\"" : "";
2340 if (!Lib.endswith_lower(".lib"))
2342 ArgStr += Quote ? "\"" : "";
2346 class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
2348 WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2349 bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
2350 unsigned NumRegisterParameters)
2351 : X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
2352 Win32StructABI, NumRegisterParameters, false) {}
2354 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2355 CodeGen::CodeGenModule &CGM) const override;
2357 void getDependentLibraryOption(llvm::StringRef Lib,
2358 llvm::SmallString<24> &Opt) const override {
2359 Opt = "/DEFAULTLIB:";
2360 Opt += qualifyWindowsLibrary(Lib);
2363 void getDetectMismatchOption(llvm::StringRef Name,
2364 llvm::StringRef Value,
2365 llvm::SmallString<32> &Opt) const override {
2366 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2370 static void addStackProbeTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2371 CodeGen::CodeGenModule &CGM) {
2372 if (llvm::Function *Fn = dyn_cast_or_null<llvm::Function>(GV)) {
2374 if (CGM.getCodeGenOpts().StackProbeSize != 4096)
2375 Fn->addFnAttr("stack-probe-size",
2376 llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
2377 if (CGM.getCodeGenOpts().NoStackArgProbe)
2378 Fn->addFnAttr("no-stack-arg-probe");
2382 void WinX86_32TargetCodeGenInfo::setTargetAttributes(
2383 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2384 X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2385 if (GV->isDeclaration())
2387 addStackProbeTargetAttributes(D, GV, CGM);
2390 class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2392 WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2393 X86AVXABILevel AVXLevel)
2394 : TargetCodeGenInfo(new WinX86_64ABIInfo(CGT)) {}
2396 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2397 CodeGen::CodeGenModule &CGM) const override;
2399 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2403 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2404 llvm::Value *Address) const override {
2405 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2407 // 0-15 are the 16 integer registers.
2409 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2413 void getDependentLibraryOption(llvm::StringRef Lib,
2414 llvm::SmallString<24> &Opt) const override {
2415 Opt = "/DEFAULTLIB:";
2416 Opt += qualifyWindowsLibrary(Lib);
2419 void getDetectMismatchOption(llvm::StringRef Name,
2420 llvm::StringRef Value,
2421 llvm::SmallString<32> &Opt) const override {
2422 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2426 void WinX86_64TargetCodeGenInfo::setTargetAttributes(
2427 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2428 TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2429 if (GV->isDeclaration())
2431 if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2432 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2433 llvm::Function *Fn = cast<llvm::Function>(GV);
2434 Fn->addFnAttr("stackrealign");
2436 if (FD->hasAttr<AnyX86InterruptAttr>()) {
2437 llvm::Function *Fn = cast<llvm::Function>(GV);
2438 Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2442 addStackProbeTargetAttributes(D, GV, CGM);
2446 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
2448 // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
2450 // (a) If one of the classes is Memory, the whole argument is passed in
2453 // (b) If X87UP is not preceded by X87, the whole argument is passed in
2456 // (c) If the size of the aggregate exceeds two eightbytes and the first
2457 // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
2458 // argument is passed in memory. NOTE: This is necessary to keep the
2459 // ABI working for processors that don't support the __m256 type.
2461 // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
2463 // Some of these are enforced by the merging logic. Others can arise
2464 // only with unions; for example:
2465 // union { _Complex double; unsigned; }
2467 // Note that clauses (b) and (c) were added in 0.98.
2471 if (Hi == X87Up && Lo != X87 && honorsRevision0_98())
2473 if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp))
2475 if (Hi == SSEUp && Lo != SSE)
2479 X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) {
2480 // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
2481 // classified recursively so that always two fields are
2482 // considered. The resulting class is calculated according to
2483 // the classes of the fields in the eightbyte:
2485 // (a) If both classes are equal, this is the resulting class.
2487 // (b) If one of the classes is NO_CLASS, the resulting class is
2490 // (c) If one of the classes is MEMORY, the result is the MEMORY
2493 // (d) If one of the classes is INTEGER, the result is the
2496 // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class,
2497 // MEMORY is used as class.
2499 // (f) Otherwise class SSE is used.
2501 // Accum should never be memory (we should have returned) or
2502 // ComplexX87 (because this cannot be passed in a structure).
2503 assert((Accum != Memory && Accum != ComplexX87) &&
2504 "Invalid accumulated classification during merge.");
2505 if (Accum == Field || Field == NoClass)
2507 if (Field == Memory)
2509 if (Accum == NoClass)
2511 if (Accum == Integer || Field == Integer)
2513 if (Field == X87 || Field == X87Up || Field == ComplexX87 ||
2514 Accum == X87 || Accum == X87Up)
2519 void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase,
2520 Class &Lo, Class &Hi, bool isNamedArg) const {
2521 // FIXME: This code can be simplified by introducing a simple value class for
2522 // Class pairs with appropriate constructor methods for the various
2525 // FIXME: Some of the split computations are wrong; unaligned vectors
2526 // shouldn't be passed in registers for example, so there is no chance they
2527 // can straddle an eightbyte. Verify & simplify.
2531 Class &Current = OffsetBase < 64 ? Lo : Hi;
2534 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
2535 BuiltinType::Kind k = BT->getKind();
2537 if (k == BuiltinType::Void) {
2539 } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) {
2542 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
2544 } else if (k == BuiltinType::Float || k == BuiltinType::Double) {
2546 } else if (k == BuiltinType::LongDouble) {
2547 const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2548 if (LDF == &llvm::APFloat::IEEEquad()) {
2551 } else if (LDF == &llvm::APFloat::x87DoubleExtended()) {
2554 } else if (LDF == &llvm::APFloat::IEEEdouble()) {
2557 llvm_unreachable("unexpected long double representation!");
2559 // FIXME: _Decimal32 and _Decimal64 are SSE.
2560 // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
2564 if (const EnumType *ET = Ty->getAs<EnumType>()) {
2565 // Classify the underlying integer type.
2566 classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
2570 if (Ty->hasPointerRepresentation()) {
2575 if (Ty->isMemberPointerType()) {
2576 if (Ty->isMemberFunctionPointerType()) {
2577 if (Has64BitPointers) {
2578 // If Has64BitPointers, this is an {i64, i64}, so classify both
2582 // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
2583 // straddles an eightbyte boundary, Hi should be classified as well.
2584 uint64_t EB_FuncPtr = (OffsetBase) / 64;
2585 uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
2586 if (EB_FuncPtr != EB_ThisAdj) {
2598 if (const VectorType *VT = Ty->getAs<VectorType>()) {
2599 uint64_t Size = getContext().getTypeSize(VT);
2600 if (Size == 1 || Size == 8 || Size == 16 || Size == 32) {
2601 // gcc passes the following as integer:
2602 // 4 bytes - <4 x char>, <2 x short>, <1 x int>, <1 x float>
2603 // 2 bytes - <2 x char>, <1 x short>
2604 // 1 byte - <1 x char>
2607 // If this type crosses an eightbyte boundary, it should be
2609 uint64_t EB_Lo = (OffsetBase) / 64;
2610 uint64_t EB_Hi = (OffsetBase + Size - 1) / 64;
2613 } else if (Size == 64) {
2614 QualType ElementType = VT->getElementType();
2616 // gcc passes <1 x double> in memory. :(
2617 if (ElementType->isSpecificBuiltinType(BuiltinType::Double))
2620 // gcc passes <1 x long long> as SSE but clang used to unconditionally
2621 // pass them as integer. For platforms where clang is the de facto
2622 // platform compiler, we must continue to use integer.
2623 if (!classifyIntegerMMXAsSSE() &&
2624 (ElementType->isSpecificBuiltinType(BuiltinType::LongLong) ||
2625 ElementType->isSpecificBuiltinType(BuiltinType::ULongLong) ||
2626 ElementType->isSpecificBuiltinType(BuiltinType::Long) ||
2627 ElementType->isSpecificBuiltinType(BuiltinType::ULong)))
2632 // If this type crosses an eightbyte boundary, it should be
2634 if (OffsetBase && OffsetBase != 64)
2636 } else if (Size == 128 ||
2637 (isNamedArg && Size <= getNativeVectorSizeForAVXABI(AVXLevel))) {
2638 // Arguments of 256-bits are split into four eightbyte chunks. The
2639 // least significant one belongs to class SSE and all the others to class
2640 // SSEUP. The original Lo and Hi design considers that types can't be
2641 // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
2642 // This design isn't correct for 256-bits, but since there're no cases
2643 // where the upper parts would need to be inspected, avoid adding
2644 // complexity and just consider Hi to match the 64-256 part.
2646 // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
2647 // registers if they are "named", i.e. not part of the "..." of a
2648 // variadic function.
2650 // Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are
2651 // split into eight eightbyte chunks, one SSE and seven SSEUP.
2658 if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
2659 QualType ET = getContext().getCanonicalType(CT->getElementType());
2661 uint64_t Size = getContext().getTypeSize(Ty);
2662 if (ET->isIntegralOrEnumerationType()) {
2665 else if (Size <= 128)
2667 } else if (ET == getContext().FloatTy) {
2669 } else if (ET == getContext().DoubleTy) {
2671 } else if (ET == getContext().LongDoubleTy) {
2672 const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2673 if (LDF == &llvm::APFloat::IEEEquad())
2675 else if (LDF == &llvm::APFloat::x87DoubleExtended())
2676 Current = ComplexX87;
2677 else if (LDF == &llvm::APFloat::IEEEdouble())
2680 llvm_unreachable("unexpected long double representation!");
2683 // If this complex type crosses an eightbyte boundary then it
2685 uint64_t EB_Real = (OffsetBase) / 64;
2686 uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64;
2687 if (Hi == NoClass && EB_Real != EB_Imag)
2693 if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
2694 // Arrays are treated like structures.
2696 uint64_t Size = getContext().getTypeSize(Ty);
2698 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2699 // than eight eightbytes, ..., it has class MEMORY.
2703 // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
2704 // fields, it has class MEMORY.
2706 // Only need to check alignment of array base.
2707 if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
2710 // Otherwise implement simplified merge. We could be smarter about
2711 // this, but it isn't worth it and would be harder to verify.
2713 uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
2714 uint64_t ArraySize = AT->getSize().getZExtValue();
2716 // The only case a 256-bit wide vector could be used is when the array
2717 // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2718 // to work for sizes wider than 128, early check and fallback to memory.
2721 (Size != EltSize || Size > getNativeVectorSizeForAVXABI(AVXLevel)))
2724 for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) {
2725 Class FieldLo, FieldHi;
2726 classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
2727 Lo = merge(Lo, FieldLo);
2728 Hi = merge(Hi, FieldHi);
2729 if (Lo == Memory || Hi == Memory)
2733 postMerge(Size, Lo, Hi);
2734 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
2738 if (const RecordType *RT = Ty->getAs<RecordType>()) {
2739 uint64_t Size = getContext().getTypeSize(Ty);
2741 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2742 // than eight eightbytes, ..., it has class MEMORY.
2746 // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
2747 // copy constructor or a non-trivial destructor, it is passed by invisible
2749 if (getRecordArgABI(RT, getCXXABI()))
2752 const RecordDecl *RD = RT->getDecl();
2754 // Assume variable sized types are passed in memory.
2755 if (RD->hasFlexibleArrayMember())
2758 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
2760 // Reset Lo class, this will be recomputed.
2763 // If this is a C++ record, classify the bases first.
2764 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2765 for (const auto &I : CXXRD->bases()) {
2766 assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2767 "Unexpected base class!");
2768 const CXXRecordDecl *Base =
2769 cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
2771 // Classify this field.
2773 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
2774 // single eightbyte, each is classified separately. Each eightbyte gets
2775 // initialized to class NO_CLASS.
2776 Class FieldLo, FieldHi;
2778 OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base));
2779 classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
2780 Lo = merge(Lo, FieldLo);
2781 Hi = merge(Hi, FieldHi);
2782 if (Lo == Memory || Hi == Memory) {
2783 postMerge(Size, Lo, Hi);
2789 // Classify the fields one at a time, merging the results.
2791 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2792 i != e; ++i, ++idx) {
2793 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2794 bool BitField = i->isBitField();
2796 // Ignore padding bit-fields.
2797 if (BitField && i->isUnnamedBitfield())
2800 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
2801 // four eightbytes, or it contains unaligned fields, it has class MEMORY.
2803 // The only case a 256-bit wide vector could be used is when the struct
2804 // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2805 // to work for sizes wider than 128, early check and fallback to memory.
2807 if (Size > 128 && (Size != getContext().getTypeSize(i->getType()) ||
2808 Size > getNativeVectorSizeForAVXABI(AVXLevel))) {
2810 postMerge(Size, Lo, Hi);
2813 // Note, skip this test for bit-fields, see below.
2814 if (!BitField && Offset % getContext().getTypeAlign(i->getType())) {
2816 postMerge(Size, Lo, Hi);
2820 // Classify this field.
2822 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
2823 // exceeds a single eightbyte, each is classified
2824 // separately. Each eightbyte gets initialized to class
2826 Class FieldLo, FieldHi;
2828 // Bit-fields require special handling, they do not force the
2829 // structure to be passed in memory even if unaligned, and
2830 // therefore they can straddle an eightbyte.
2832 assert(!i->isUnnamedBitfield());
2833 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2834 uint64_t Size = i->getBitWidthValue(getContext());
2836 uint64_t EB_Lo = Offset / 64;
2837 uint64_t EB_Hi = (Offset + Size - 1) / 64;
2840 assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes.");
2845 FieldHi = EB_Hi ? Integer : NoClass;
2848 classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
2849 Lo = merge(Lo, FieldLo);
2850 Hi = merge(Hi, FieldHi);
2851 if (Lo == Memory || Hi == Memory)
2855 postMerge(Size, Lo, Hi);
2859 ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const {
2860 // If this is a scalar LLVM value then assume LLVM will pass it in the right
2862 if (!isAggregateTypeForABI(Ty)) {
2863 // Treat an enum type as its underlying type.
2864 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2865 Ty = EnumTy->getDecl()->getIntegerType();
2867 return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty)
2868 : ABIArgInfo::getDirect());
2871 return getNaturalAlignIndirect(Ty);
2874 bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const {
2875 if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
2876 uint64_t Size = getContext().getTypeSize(VecTy);
2877 unsigned LargestVector = getNativeVectorSizeForAVXABI(AVXLevel);
2878 if (Size <= 64 || Size > LargestVector)
2885 ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty,
2886 unsigned freeIntRegs) const {
2887 // If this is a scalar LLVM value then assume LLVM will pass it in the right
2890 // This assumption is optimistic, as there could be free registers available
2891 // when we need to pass this argument in memory, and LLVM could try to pass
2892 // the argument in the free register. This does not seem to happen currently,
2893 // but this code would be much safer if we could mark the argument with
2894 // 'onstack'. See PR12193.
2895 if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty)) {
2896 // Treat an enum type as its underlying type.
2897 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2898 Ty = EnumTy->getDecl()->getIntegerType();
2900 return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty)
2901 : ABIArgInfo::getDirect());
2904 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
2905 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
2907 // Compute the byval alignment. We specify the alignment of the byval in all
2908 // cases so that the mid-level optimizer knows the alignment of the byval.
2909 unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U);
2911 // Attempt to avoid passing indirect results using byval when possible. This
2912 // is important for good codegen.
2914 // We do this by coercing the value into a scalar type which the backend can
2915 // handle naturally (i.e., without using byval).
2917 // For simplicity, we currently only do this when we have exhausted all of the
2918 // free integer registers. Doing this when there are free integer registers
2919 // would require more care, as we would have to ensure that the coerced value
2920 // did not claim the unused register. That would require either reording the
2921 // arguments to the function (so that any subsequent inreg values came first),
2922 // or only doing this optimization when there were no following arguments that
2925 // We currently expect it to be rare (particularly in well written code) for
2926 // arguments to be passed on the stack when there are still free integer
2927 // registers available (this would typically imply large structs being passed
2928 // by value), so this seems like a fair tradeoff for now.
2930 // We can revisit this if the backend grows support for 'onstack' parameter
2931 // attributes. See PR12193.
2932 if (freeIntRegs == 0) {
2933 uint64_t Size = getContext().getTypeSize(Ty);
2935 // If this type fits in an eightbyte, coerce it into the matching integral
2936 // type, which will end up on the stack (with alignment 8).
2937 if (Align == 8 && Size <= 64)
2938 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
2942 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align));
2945 /// The ABI specifies that a value should be passed in a full vector XMM/YMM
2946 /// register. Pick an LLVM IR type that will be passed as a vector register.
2947 llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const {
2948 // Wrapper structs/arrays that only contain vectors are passed just like
2949 // vectors; strip them off if present.
2950 if (const Type *InnerTy = isSingleElementStruct(Ty, getContext()))
2951 Ty = QualType(InnerTy, 0);
2953 llvm::Type *IRType = CGT.ConvertType(Ty);
2954 if (isa<llvm::VectorType>(IRType) ||
2955 IRType->getTypeID() == llvm::Type::FP128TyID)
2958 // We couldn't find the preferred IR vector type for 'Ty'.
2959 uint64_t Size = getContext().getTypeSize(Ty);
2960 assert((Size == 128 || Size == 256 || Size == 512) && "Invalid type found!");
2962 // Return a LLVM IR vector type based on the size of 'Ty'.
2963 return llvm::VectorType::get(llvm::Type::getDoubleTy(getVMContext()),
2967 /// BitsContainNoUserData - Return true if the specified [start,end) bit range
2968 /// is known to either be off the end of the specified type or being in
2969 /// alignment padding. The user type specified is known to be at most 128 bits
2970 /// in size, and have passed through X86_64ABIInfo::classify with a successful
2971 /// classification that put one of the two halves in the INTEGER class.
2973 /// It is conservatively correct to return false.
2974 static bool BitsContainNoUserData(QualType Ty, unsigned StartBit,
2975 unsigned EndBit, ASTContext &Context) {
2976 // If the bytes being queried are off the end of the type, there is no user
2977 // data hiding here. This handles analysis of builtins, vectors and other
2978 // types that don't contain interesting padding.
2979 unsigned TySize = (unsigned)Context.getTypeSize(Ty);
2980 if (TySize <= StartBit)
2983 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) {
2984 unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
2985 unsigned NumElts = (unsigned)AT->getSize().getZExtValue();
2987 // Check each element to see if the element overlaps with the queried range.
2988 for (unsigned i = 0; i != NumElts; ++i) {
2989 // If the element is after the span we care about, then we're done..
2990 unsigned EltOffset = i*EltSize;
2991 if (EltOffset >= EndBit) break;
2993 unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0;
2994 if (!BitsContainNoUserData(AT->getElementType(), EltStart,
2995 EndBit-EltOffset, Context))
2998 // If it overlaps no elements, then it is safe to process as padding.
3002 if (const RecordType *RT = Ty->getAs<RecordType>()) {
3003 const RecordDecl *RD = RT->getDecl();
3004 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
3006 // If this is a C++ record, check the bases first.
3007 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
3008 for (const auto &I : CXXRD->bases()) {
3009 assert(!I.isVirtual() && !I.getType()->isDependentType() &&
3010 "Unexpected base class!");
3011 const CXXRecordDecl *Base =
3012 cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
3014 // If the base is after the span we care about, ignore it.
3015 unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base));
3016 if (BaseOffset >= EndBit) continue;
3018 unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0;
3019 if (!BitsContainNoUserData(I.getType(), BaseStart,
3020 EndBit-BaseOffset, Context))
3025 // Verify that no field has data that overlaps the region of interest. Yes
3026 // this could be sped up a lot by being smarter about queried fields,
3027 // however we're only looking at structs up to 16 bytes, so we don't care
3030 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
3031 i != e; ++i, ++idx) {
3032 unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx);
3034 // If we found a field after the region we care about, then we're done.
3035 if (FieldOffset >= EndBit) break;
3037 unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0;
3038 if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
3043 // If nothing in this record overlapped the area of interest, then we're
3051 /// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a
3052 /// float member at the specified offset. For example, {int,{float}} has a
3053 /// float at offset 4. It is conservatively correct for this routine to return
3055 static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset,
3056 const llvm::DataLayout &TD) {
3057 // Base case if we find a float.
3058 if (IROffset == 0 && IRType->isFloatTy())
3061 // If this is a struct, recurse into the field at the specified offset.
3062 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3063 const llvm::StructLayout *SL = TD.getStructLayout(STy);
3064 unsigned Elt = SL->getElementContainingOffset(IROffset);
3065 IROffset -= SL->getElementOffset(Elt);
3066 return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD);
3069 // If this is an array, recurse into the field at the specified offset.
3070 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3071 llvm::Type *EltTy = ATy->getElementType();
3072 unsigned EltSize = TD.getTypeAllocSize(EltTy);
3073 IROffset -= IROffset/EltSize*EltSize;
3074 return ContainsFloatAtOffset(EltTy, IROffset, TD);
3081 /// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
3082 /// low 8 bytes of an XMM register, corresponding to the SSE class.
3083 llvm::Type *X86_64ABIInfo::
3084 GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3085 QualType SourceTy, unsigned SourceOffset) const {
3086 // The only three choices we have are either double, <2 x float>, or float. We
3087 // pass as float if the last 4 bytes is just padding. This happens for
3088 // structs that contain 3 floats.
3089 if (BitsContainNoUserData(SourceTy, SourceOffset*8+32,
3090 SourceOffset*8+64, getContext()))
3091 return llvm::Type::getFloatTy(getVMContext());
3093 // We want to pass as <2 x float> if the LLVM IR type contains a float at
3094 // offset+0 and offset+4. Walk the LLVM IR type to find out if this is the
3096 if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) &&
3097 ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout()))
3098 return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2);
3100 return llvm::Type::getDoubleTy(getVMContext());
3104 /// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
3105 /// an 8-byte GPR. This means that we either have a scalar or we are talking
3106 /// about the high or low part of an up-to-16-byte struct. This routine picks
3107 /// the best LLVM IR type to represent this, which may be i64 or may be anything
3108 /// else that the backend will pass in a GPR that works better (e.g. i8, %foo*,
3111 /// PrefType is an LLVM IR type that corresponds to (part of) the IR type for
3112 /// the source type. IROffset is an offset in bytes into the LLVM IR type that
3113 /// the 8-byte value references. PrefType may be null.
3115 /// SourceTy is the source-level type for the entire argument. SourceOffset is
3116 /// an offset into this that we're processing (which is always either 0 or 8).
3118 llvm::Type *X86_64ABIInfo::
3119 GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3120 QualType SourceTy, unsigned SourceOffset) const {
3121 // If we're dealing with an un-offset LLVM IR type, then it means that we're
3122 // returning an 8-byte unit starting with it. See if we can safely use it.
3123 if (IROffset == 0) {
3124 // Pointers and int64's always fill the 8-byte unit.
3125 if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) ||
3126 IRType->isIntegerTy(64))
3129 // If we have a 1/2/4-byte integer, we can use it only if the rest of the
3130 // goodness in the source type is just tail padding. This is allowed to
3131 // kick in for struct {double,int} on the int, but not on
3132 // struct{double,int,int} because we wouldn't return the second int. We
3133 // have to do this analysis on the source type because we can't depend on
3134 // unions being lowered a specific way etc.
3135 if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) ||
3136 IRType->isIntegerTy(32) ||
3137 (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) {
3138 unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 :
3139 cast<llvm::IntegerType>(IRType)->getBitWidth();
3141 if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth,
3142 SourceOffset*8+64, getContext()))
3147 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3148 // If this is a struct, recurse into the field at the specified offset.
3149 const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy);
3150 if (IROffset < SL->getSizeInBytes()) {
3151 unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
3152 IROffset -= SL->getElementOffset(FieldIdx);
3154 return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
3155 SourceTy, SourceOffset);
3159 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3160 llvm::Type *EltTy = ATy->getElementType();
3161 unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
3162 unsigned EltOffset = IROffset/EltSize*EltSize;
3163 return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
3167 // Okay, we don't have any better idea of what to pass, so we pass this in an
3168 // integer register that isn't too big to fit the rest of the struct.
3169 unsigned TySizeInBytes =
3170 (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity();
3172 assert(TySizeInBytes != SourceOffset && "Empty field?");
3174 // It is always safe to classify this as an integer type up to i64 that
3175 // isn't larger than the structure.
3176 return llvm::IntegerType::get(getVMContext(),
3177 std::min(TySizeInBytes-SourceOffset, 8U)*8);
3181 /// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
3182 /// be used as elements of a two register pair to pass or return, return a
3183 /// first class aggregate to represent them. For example, if the low part of
3184 /// a by-value argument should be passed as i32* and the high part as float,
3185 /// return {i32*, float}.
3187 GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi,
3188 const llvm::DataLayout &TD) {
3189 // In order to correctly satisfy the ABI, we need to the high part to start
3190 // at offset 8. If the high and low parts we inferred are both 4-byte types
3191 // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have
3192 // the second element at offset 8. Check for this:
3193 unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo);
3194 unsigned HiAlign = TD.getABITypeAlignment(Hi);
3195 unsigned HiStart = llvm::alignTo(LoSize, HiAlign);
3196 assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!");
3198 // To handle this, we have to increase the size of the low part so that the
3199 // second element will start at an 8 byte offset. We can't increase the size
3200 // of the second element because it might make us access off the end of the
3203 // There are usually two sorts of types the ABI generation code can produce
3204 // for the low part of a pair that aren't 8 bytes in size: float or
3205 // i8/i16/i32. This can also include pointers when they are 32-bit (X32 and
3207 // Promote these to a larger type.
3208 if (Lo->isFloatTy())
3209 Lo = llvm::Type::getDoubleTy(Lo->getContext());
3211 assert((Lo->isIntegerTy() || Lo->isPointerTy())
3212 && "Invalid/unknown lo type");
3213 Lo = llvm::Type::getInt64Ty(Lo->getContext());
3217 llvm::StructType *Result = llvm::StructType::get(Lo, Hi);
3219 // Verify that the second element is at an 8-byte offset.
3220 assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
3221 "Invalid x86-64 argument pair!");
3225 ABIArgInfo X86_64ABIInfo::
3226 classifyReturnType(QualType RetTy) const {
3227 // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
3228 // classification algorithm.
3229 X86_64ABIInfo::Class Lo, Hi;
3230 classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);
3232 // Check some invariants.
3233 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3234 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3236 llvm::Type *ResType = nullptr;
3240 return ABIArgInfo::getIgnore();
3241 // If the low part is just padding, it takes no register, leave ResType
3243 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3244 "Unknown missing lo part");
3249 llvm_unreachable("Invalid classification for lo word.");
3251 // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
3254 return getIndirectReturnResult(RetTy);
3256 // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
3257 // available register of the sequence %rax, %rdx is used.
3259 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3261 // If we have a sign or zero extended integer, make sure to return Extend
3262 // so that the parameter gets the right LLVM IR attributes.
3263 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3264 // Treat an enum type as its underlying type.
3265 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
3266 RetTy = EnumTy->getDecl()->getIntegerType();
3268 if (RetTy->isIntegralOrEnumerationType() &&
3269 RetTy->isPromotableIntegerType())
3270 return ABIArgInfo::getExtend(RetTy);
3274 // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
3275 // available SSE register of the sequence %xmm0, %xmm1 is used.
3277 ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3280 // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
3281 // returned on the X87 stack in %st0 as 80-bit x87 number.
3283 ResType = llvm::Type::getX86_FP80Ty(getVMContext());
3286 // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
3287 // part of the value is returned in %st0 and the imaginary part in
3290 assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.");
3291 ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()),
3292 llvm::Type::getX86_FP80Ty(getVMContext()));
3296 llvm::Type *HighPart = nullptr;
3298 // Memory was handled previously and X87 should
3299 // never occur as a hi class.
3302 llvm_unreachable("Invalid classification for hi word.");
3304 case ComplexX87: // Previously handled.
3309 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3310 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3311 return ABIArgInfo::getDirect(HighPart, 8);
3314 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3315 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3316 return ABIArgInfo::getDirect(HighPart, 8);
3319 // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
3320 // is passed in the next available eightbyte chunk if the last used
3323 // SSEUP should always be preceded by SSE, just widen.
3325 assert(Lo == SSE && "Unexpected SSEUp classification.");
3326 ResType = GetByteVectorType(RetTy);
3329 // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
3330 // returned together with the previous X87 value in %st0.
3332 // If X87Up is preceded by X87, we don't need to do
3333 // anything. However, in some cases with unions it may not be
3334 // preceded by X87. In such situations we follow gcc and pass the
3335 // extra bits in an SSE reg.
3337 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3338 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3339 return ABIArgInfo::getDirect(HighPart, 8);
3344 // If a high part was specified, merge it together with the low part. It is
3345 // known to pass in the high eightbyte of the result. We do this by forming a
3346 // first class struct aggregate with the high and low part: {low, high}
3348 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3350 return ABIArgInfo::getDirect(ResType);
3353 ABIArgInfo X86_64ABIInfo::classifyArgumentType(
3354 QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE,
3358 Ty = useFirstFieldIfTransparentUnion(Ty);
3360 X86_64ABIInfo::Class Lo, Hi;
3361 classify(Ty, 0, Lo, Hi, isNamedArg);
3363 // Check some invariants.
3364 // FIXME: Enforce these by construction.
3365 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3366 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3370 llvm::Type *ResType = nullptr;
3374 return ABIArgInfo::getIgnore();
3375 // If the low part is just padding, it takes no register, leave ResType
3377 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3378 "Unknown missing lo part");
3381 // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
3385 // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
3386 // COMPLEX_X87, it is passed in memory.
3389 if (getRecordArgABI(Ty, getCXXABI()) == CGCXXABI::RAA_Indirect)
3391 return getIndirectResult(Ty, freeIntRegs);
3395 llvm_unreachable("Invalid classification for lo word.");
3397 // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
3398 // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
3403 // Pick an 8-byte type based on the preferred type.
3404 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);
3406 // If we have a sign or zero extended integer, make sure to return Extend
3407 // so that the parameter gets the right LLVM IR attributes.
3408 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3409 // Treat an enum type as its underlying type.
3410 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3411 Ty = EnumTy->getDecl()->getIntegerType();
3413 if (Ty->isIntegralOrEnumerationType() &&
3414 Ty->isPromotableIntegerType())
3415 return ABIArgInfo::getExtend(Ty);
3420 // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
3421 // available SSE register is used, the registers are taken in the
3422 // order from %xmm0 to %xmm7.
3424 llvm::Type *IRType = CGT.ConvertType(Ty);
3425 ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);
3431 llvm::Type *HighPart = nullptr;
3433 // Memory was handled previously, ComplexX87 and X87 should
3434 // never occur as hi classes, and X87Up must be preceded by X87,
3435 // which is passed in memory.
3439 llvm_unreachable("Invalid classification for hi word.");
3441 case NoClass: break;
3445 // Pick an 8-byte type based on the preferred type.
3446 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3448 if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3449 return ABIArgInfo::getDirect(HighPart, 8);
3452 // X87Up generally doesn't occur here (long double is passed in
3453 // memory), except in situations involving unions.
3456 HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3458 if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3459 return ABIArgInfo::getDirect(HighPart, 8);
3464 // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
3465 // eightbyte is passed in the upper half of the last used SSE
3466 // register. This only happens when 128-bit vectors are passed.
3468 assert(Lo == SSE && "Unexpected SSEUp classification");
3469 ResType = GetByteVectorType(Ty);
3473 // If a high part was specified, merge it together with the low part. It is
3474 // known to pass in the high eightbyte of the result. We do this by forming a
3475 // first class struct aggregate with the high and low part: {low, high}
3477 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3479 return ABIArgInfo::getDirect(ResType);
3483 X86_64ABIInfo::classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
3484 unsigned &NeededSSE) const {
3485 auto RT = Ty->getAs<RecordType>();
3486 assert(RT && "classifyRegCallStructType only valid with struct types");
3488 if (RT->getDecl()->hasFlexibleArrayMember())
3489 return getIndirectReturnResult(Ty);
3492 if (auto CXXRD = dyn_cast<CXXRecordDecl>(RT->getDecl())) {
3493 if (CXXRD->isDynamicClass()) {
3494 NeededInt = NeededSSE = 0;
3495 return getIndirectReturnResult(Ty);
3498 for (const auto &I : CXXRD->bases())
3499 if (classifyRegCallStructTypeImpl(I.getType(), NeededInt, NeededSSE)
3501 NeededInt = NeededSSE = 0;
3502 return getIndirectReturnResult(Ty);
3507 for (const auto *FD : RT->getDecl()->fields()) {
3508 if (FD->getType()->isRecordType() && !FD->getType()->isUnionType()) {
3509 if (classifyRegCallStructTypeImpl(FD->getType(), NeededInt, NeededSSE)
3511 NeededInt = NeededSSE = 0;
3512 return getIndirectReturnResult(Ty);
3515 unsigned LocalNeededInt, LocalNeededSSE;
3516 if (classifyArgumentType(FD->getType(), UINT_MAX, LocalNeededInt,
3517 LocalNeededSSE, true)
3519 NeededInt = NeededSSE = 0;
3520 return getIndirectReturnResult(Ty);
3522 NeededInt += LocalNeededInt;
3523 NeededSSE += LocalNeededSSE;
3527 return ABIArgInfo::getDirect();
3530 ABIArgInfo X86_64ABIInfo::classifyRegCallStructType(QualType Ty,
3531 unsigned &NeededInt,
3532 unsigned &NeededSSE) const {
3537 return classifyRegCallStructTypeImpl(Ty, NeededInt, NeededSSE);
3540 void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3542 const unsigned CallingConv = FI.getCallingConvention();
3543 // It is possible to force Win64 calling convention on any x86_64 target by
3544 // using __attribute__((ms_abi)). In such case to correctly emit Win64
3545 // compatible code delegate this call to WinX86_64ABIInfo::computeInfo.
3546 if (CallingConv == llvm::CallingConv::Win64) {
3547 WinX86_64ABIInfo Win64ABIInfo(CGT);
3548 Win64ABIInfo.computeInfo(FI);
3552 bool IsRegCall = CallingConv == llvm::CallingConv::X86_RegCall;
3554 // Keep track of the number of assigned registers.
3555 unsigned FreeIntRegs = IsRegCall ? 11 : 6;
3556 unsigned FreeSSERegs = IsRegCall ? 16 : 8;
3557 unsigned NeededInt, NeededSSE;
3559 if (!::classifyReturnType(getCXXABI(), FI, *this)) {
3560 if (IsRegCall && FI.getReturnType()->getTypePtr()->isRecordType() &&
3561 !FI.getReturnType()->getTypePtr()->isUnionType()) {
3562 FI.getReturnInfo() =
3563 classifyRegCallStructType(FI.getReturnType(), NeededInt, NeededSSE);
3564 if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3565 FreeIntRegs -= NeededInt;
3566 FreeSSERegs -= NeededSSE;
3568 FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3570 } else if (IsRegCall && FI.getReturnType()->getAs<ComplexType>()) {
3571 // Complex Long Double Type is passed in Memory when Regcall
3572 // calling convention is used.
3573 const ComplexType *CT = FI.getReturnType()->getAs<ComplexType>();
3574 if (getContext().getCanonicalType(CT->getElementType()) ==
3575 getContext().LongDoubleTy)
3576 FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3578 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
3581 // If the return value is indirect, then the hidden argument is consuming one
3582 // integer register.
3583 if (FI.getReturnInfo().isIndirect())
3586 // The chain argument effectively gives us another free register.
3587 if (FI.isChainCall())
3590 unsigned NumRequiredArgs = FI.getNumRequiredArgs();
3591 // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
3592 // get assigned (in left-to-right order) for passing as follows...
3594 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
3595 it != ie; ++it, ++ArgNo) {
3596 bool IsNamedArg = ArgNo < NumRequiredArgs;
3598 if (IsRegCall && it->type->isStructureOrClassType())
3599 it->info = classifyRegCallStructType(it->type, NeededInt, NeededSSE);
3601 it->info = classifyArgumentType(it->type, FreeIntRegs, NeededInt,
3602 NeededSSE, IsNamedArg);
3604 // AMD64-ABI 3.2.3p3: If there are no registers available for any
3605 // eightbyte of an argument, the whole argument is passed on the
3606 // stack. If registers have already been assigned for some
3607 // eightbytes of such an argument, the assignments get reverted.
3608 if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3609 FreeIntRegs -= NeededInt;
3610 FreeSSERegs -= NeededSSE;
3612 it->info = getIndirectResult(it->type, FreeIntRegs);
3617 static Address EmitX86_64VAArgFromMemory(CodeGenFunction &CGF,
3618 Address VAListAddr, QualType Ty) {
3619 Address overflow_arg_area_p = CGF.Builder.CreateStructGEP(
3620 VAListAddr, 2, CharUnits::fromQuantity(8), "overflow_arg_area_p");
3621 llvm::Value *overflow_arg_area =
3622 CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area");
3624 // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
3625 // byte boundary if alignment needed by type exceeds 8 byte boundary.
3626 // It isn't stated explicitly in the standard, but in practice we use
3627 // alignment greater than 16 where necessary.
3628 CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
3629 if (Align > CharUnits::fromQuantity(8)) {
3630 overflow_arg_area = emitRoundPointerUpToAlignment(CGF, overflow_arg_area,
3634 // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
3635 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3637 CGF.Builder.CreateBitCast(overflow_arg_area,
3638 llvm::PointerType::getUnqual(LTy));
3640 // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
3641 // l->overflow_arg_area + sizeof(type).
3642 // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
3643 // an 8 byte boundary.
3645 uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8;
3646 llvm::Value *Offset =
3647 llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7);
3648 overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset,
3649 "overflow_arg_area.next");
3650 CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);
3652 // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
3653 return Address(Res, Align);
3656 Address X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3657 QualType Ty) const {
3658 // Assume that va_list type is correct; should be pointer to LLVM type:
3662 // i8* overflow_arg_area;
3663 // i8* reg_save_area;
3665 unsigned neededInt, neededSSE;
3667 Ty = getContext().getCanonicalType(Ty);
3668 ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
3669 /*isNamedArg*/false);
3671 // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
3672 // in the registers. If not go to step 7.
3673 if (!neededInt && !neededSSE)
3674 return EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3676 // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
3677 // general purpose registers needed to pass type and num_fp to hold
3678 // the number of floating point registers needed.
3680 // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
3681 // registers. In the case: l->gp_offset > 48 - num_gp * 8 or
3682 // l->fp_offset > 304 - num_fp * 16 go to step 7.
3684 // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of
3685 // register save space).
3687 llvm::Value *InRegs = nullptr;
3688 Address gp_offset_p = Address::invalid(), fp_offset_p = Address::invalid();
3689 llvm::Value *gp_offset = nullptr, *fp_offset = nullptr;
3692 CGF.Builder.CreateStructGEP(VAListAddr, 0, CharUnits::Zero(),
3694 gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset");
3695 InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
3696 InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp");
3701 CGF.Builder.CreateStructGEP(VAListAddr, 1, CharUnits::fromQuantity(4),
3703 fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset");
3704 llvm::Value *FitsInFP =
3705 llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
3706 FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp");
3707 InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP;
3710 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
3711 llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
3712 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
3713 CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
3715 // Emit code to load the value if it was passed in registers.
3717 CGF.EmitBlock(InRegBlock);
3719 // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
3720 // an offset of l->gp_offset and/or l->fp_offset. This may require
3721 // copying to a temporary location in case the parameter is passed
3722 // in different register classes or requires an alignment greater
3723 // than 8 for general purpose registers and 16 for XMM registers.
3725 // FIXME: This really results in shameful code when we end up needing to
3726 // collect arguments from different places; often what should result in a
3727 // simple assembling of a structure from scattered addresses has many more
3728 // loads than necessary. Can we clean this up?
3729 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3730 llvm::Value *RegSaveArea = CGF.Builder.CreateLoad(
3731 CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(16)),
3734 Address RegAddr = Address::invalid();
3735 if (neededInt && neededSSE) {
3737 assert(AI.isDirect() && "Unexpected ABI info for mixed regs");
3738 llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType());
3739 Address Tmp = CGF.CreateMemTemp(Ty);
3740 Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3741 assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs");
3742 llvm::Type *TyLo = ST->getElementType(0);
3743 llvm::Type *TyHi = ST->getElementType(1);
3744 assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&
3745 "Unexpected ABI info for mixed regs");
3746 llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo);
3747 llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi);
3748 llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegSaveArea, gp_offset);
3749 llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegSaveArea, fp_offset);
3750 llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? FPAddr : GPAddr;
3751 llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? GPAddr : FPAddr;
3753 // Copy the first element.
3754 // FIXME: Our choice of alignment here and below is probably pessimistic.
3755 llvm::Value *V = CGF.Builder.CreateAlignedLoad(
3756 TyLo, CGF.Builder.CreateBitCast(RegLoAddr, PTyLo),
3757 CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyLo)));
3758 CGF.Builder.CreateStore(V,
3759 CGF.Builder.CreateStructGEP(Tmp, 0, CharUnits::Zero()));
3761 // Copy the second element.
3762 V = CGF.Builder.CreateAlignedLoad(
3763 TyHi, CGF.Builder.CreateBitCast(RegHiAddr, PTyHi),
3764 CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyHi)));
3765 CharUnits Offset = CharUnits::fromQuantity(
3766 getDataLayout().getStructLayout(ST)->getElementOffset(1));
3767 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1, Offset));
3769 RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3770 } else if (neededInt) {
3771 RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, gp_offset),
3772 CharUnits::fromQuantity(8));
3773 RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3775 // Copy to a temporary if necessary to ensure the appropriate alignment.
3776 std::pair<CharUnits, CharUnits> SizeAlign =
3777 getContext().getTypeInfoInChars(Ty);
3778 uint64_t TySize = SizeAlign.first.getQuantity();
3779 CharUnits TyAlign = SizeAlign.second;
3781 // Copy into a temporary if the type is more aligned than the
3782 // register save area.
3783 if (TyAlign.getQuantity() > 8) {
3784 Address Tmp = CGF.CreateMemTemp(Ty);
3785 CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false);
3789 } else if (neededSSE == 1) {
3790 RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3791 CharUnits::fromQuantity(16));
3792 RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3794 assert(neededSSE == 2 && "Invalid number of needed registers!");
3795 // SSE registers are spaced 16 bytes apart in the register save
3796 // area, we need to collect the two eightbytes together.
3797 // The ABI isn't explicit about this, but it seems reasonable
3798 // to assume that the slots are 16-byte aligned, since the stack is
3799 // naturally 16-byte aligned and the prologue is expected to store
3800 // all the SSE registers to the RSA.
3801 Address RegAddrLo = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3802 CharUnits::fromQuantity(16));
3804 CGF.Builder.CreateConstInBoundsByteGEP(RegAddrLo,
3805 CharUnits::fromQuantity(16));
3806 llvm::Type *ST = AI.canHaveCoerceToType()
3807 ? AI.getCoerceToType()
3808 : llvm::StructType::get(CGF.DoubleTy, CGF.DoubleTy);
3810 Address Tmp = CGF.CreateMemTemp(Ty);
3811 Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3812 V = CGF.Builder.CreateLoad(CGF.Builder.CreateElementBitCast(
3813 RegAddrLo, ST->getStructElementType(0)));
3814 CGF.Builder.CreateStore(V,
3815 CGF.Builder.CreateStructGEP(Tmp, 0, CharUnits::Zero()));
3816 V = CGF.Builder.CreateLoad(CGF.Builder.CreateElementBitCast(
3817 RegAddrHi, ST->getStructElementType(1)));
3818 CGF.Builder.CreateStore(V,
3819 CGF.Builder.CreateStructGEP(Tmp, 1, CharUnits::fromQuantity(8)));
3821 RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3824 // AMD64-ABI 3.5.7p5: Step 5. Set:
3825 // l->gp_offset = l->gp_offset + num_gp * 8
3826 // l->fp_offset = l->fp_offset + num_fp * 16.
3828 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8);
3829 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset),
3833 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16);
3834 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset),
3837 CGF.EmitBranch(ContBlock);
3839 // Emit code to load the value if it was passed in memory.
3841 CGF.EmitBlock(InMemBlock);
3842 Address MemAddr = EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3844 // Return the appropriate result.
3846 CGF.EmitBlock(ContBlock);
3847 Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, MemAddr, InMemBlock,
3852 Address X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
3853 QualType Ty) const {
3854 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
3855 CGF.getContext().getTypeInfoInChars(Ty),
3856 CharUnits::fromQuantity(8),
3857 /*allowHigherAlign*/ false);
3861 WinX86_64ABIInfo::reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
3862 const ABIArgInfo ¤t) const {
3863 // Assumes vectorCall calling convention.
3864 const Type *Base = nullptr;
3865 uint64_t NumElts = 0;
3867 if (!Ty->isBuiltinType() && !Ty->isVectorType() &&
3868 isHomogeneousAggregate(Ty, Base, NumElts) && FreeSSERegs >= NumElts) {
3869 FreeSSERegs -= NumElts;
3870 return getDirectX86Hva();
3875 ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
3876 bool IsReturnType, bool IsVectorCall,
3877 bool IsRegCall) const {
3879 if (Ty->isVoidType())
3880 return ABIArgInfo::getIgnore();
3882 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3883 Ty = EnumTy->getDecl()->getIntegerType();
3885 TypeInfo Info = getContext().getTypeInfo(Ty);
3886 uint64_t Width = Info.Width;
3887 CharUnits Align = getContext().toCharUnitsFromBits(Info.Align);
3889 const RecordType *RT = Ty->getAs<RecordType>();
3891 if (!IsReturnType) {
3892 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI()))
3893 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
3896 if (RT->getDecl()->hasFlexibleArrayMember())
3897 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3901 const Type *Base = nullptr;
3902 uint64_t NumElts = 0;
3903 // vectorcall adds the concept of a homogenous vector aggregate, similar to
3905 if ((IsVectorCall || IsRegCall) &&
3906 isHomogeneousAggregate(Ty, Base, NumElts)) {
3908 if (FreeSSERegs >= NumElts) {
3909 FreeSSERegs -= NumElts;
3910 if (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())
3911 return ABIArgInfo::getDirect();
3912 return ABIArgInfo::getExpand();
3914 return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3915 } else if (IsVectorCall) {
3916 if (FreeSSERegs >= NumElts &&
3917 (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())) {
3918 FreeSSERegs -= NumElts;
3919 return ABIArgInfo::getDirect();
3920 } else if (IsReturnType) {
3921 return ABIArgInfo::getExpand();
3922 } else if (!Ty->isBuiltinType() && !Ty->isVectorType()) {
3923 // HVAs are delayed and reclassified in the 2nd step.
3924 return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3929 if (Ty->isMemberPointerType()) {
3930 // If the member pointer is represented by an LLVM int or ptr, pass it
3932 llvm::Type *LLTy = CGT.ConvertType(Ty);
3933 if (LLTy->isPointerTy() || LLTy->isIntegerTy())
3934 return ABIArgInfo::getDirect();
3937 if (RT || Ty->isAnyComplexType() || Ty->isMemberPointerType()) {
3938 // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
3939 // not 1, 2, 4, or 8 bytes, must be passed by reference."
3940 if (Width > 64 || !llvm::isPowerOf2_64(Width))
3941 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3943 // Otherwise, coerce it to a small integer.
3944 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width));
3947 // Bool type is always extended to the ABI, other builtin types are not
3949 const BuiltinType *BT = Ty->getAs<BuiltinType>();
3950 if (BT && BT->getKind() == BuiltinType::Bool)
3951 return ABIArgInfo::getExtend(Ty);
3953 // Mingw64 GCC uses the old 80 bit extended precision floating point unit. It
3954 // passes them indirectly through memory.
3955 if (IsMingw64 && BT && BT->getKind() == BuiltinType::LongDouble) {
3956 const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
3957 if (LDF == &llvm::APFloat::x87DoubleExtended())
3958 return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3961 return ABIArgInfo::getDirect();
3964 void WinX86_64ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI,
3965 unsigned FreeSSERegs,
3967 bool IsRegCall) const {
3969 for (auto &I : FI.arguments()) {
3970 // Vectorcall in x64 only permits the first 6 arguments to be passed
3971 // as XMM/YMM registers.
3972 if (Count < VectorcallMaxParamNumAsReg)
3973 I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
3975 // Since these cannot be passed in registers, pretend no registers
3977 unsigned ZeroSSERegsAvail = 0;
3978 I.info = classify(I.type, /*FreeSSERegs=*/ZeroSSERegsAvail, false,
3979 IsVectorCall, IsRegCall);
3984 for (auto &I : FI.arguments()) {
3985 I.info = reclassifyHvaArgType(I.type, FreeSSERegs, I.info);
3989 void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3991 FI.getCallingConvention() == llvm::CallingConv::X86_VectorCall;
3992 bool IsRegCall = FI.getCallingConvention() == llvm::CallingConv::X86_RegCall;
3994 unsigned FreeSSERegs = 0;
3996 // We can use up to 4 SSE return registers with vectorcall.
3998 } else if (IsRegCall) {
3999 // RegCall gives us 16 SSE registers.
4003 if (!getCXXABI().classifyReturnType(FI))
4004 FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true,
4005 IsVectorCall, IsRegCall);
4008 // We can use up to 6 SSE register parameters with vectorcall.
4010 } else if (IsRegCall) {
4011 // RegCall gives us 16 SSE registers, we can reuse the return registers.
4016 computeVectorCallArgs(FI, FreeSSERegs, IsVectorCall, IsRegCall);
4018 for (auto &I : FI.arguments())
4019 I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
4024 Address WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4025 QualType Ty) const {
4027 bool IsIndirect = false;
4029 // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
4030 // not 1, 2, 4, or 8 bytes, must be passed by reference."
4031 if (isAggregateTypeForABI(Ty) || Ty->isMemberPointerType()) {
4032 uint64_t Width = getContext().getTypeSize(Ty);
4033 IsIndirect = Width > 64 || !llvm::isPowerOf2_64(Width);
4036 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
4037 CGF.getContext().getTypeInfoInChars(Ty),
4038 CharUnits::fromQuantity(8),
4039 /*allowHigherAlign*/ false);
4044 /// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
4045 class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
4046 bool IsSoftFloatABI;
4048 CharUnits getParamTypeAlignment(QualType Ty) const;
4051 PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI)
4052 : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI) {}
4054 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4055 QualType Ty) const override;
4058 class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
4060 PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI)
4061 : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI)) {}
4063 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4064 // This is recovered from gcc output.
4065 return 1; // r1 is the dedicated stack pointer
4068 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4069 llvm::Value *Address) const override;
4073 CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4074 // Complex types are passed just like their elements
4075 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4076 Ty = CTy->getElementType();
4078 if (Ty->isVectorType())
4079 return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16
4082 // For single-element float/vector structs, we consider the whole type
4083 // to have the same alignment requirements as its single element.
4084 const Type *AlignTy = nullptr;
4085 if (const Type *EltType = isSingleElementStruct(Ty, getContext())) {
4086 const BuiltinType *BT = EltType->getAs<BuiltinType>();
4087 if ((EltType->isVectorType() && getContext().getTypeSize(EltType) == 128) ||
4088 (BT && BT->isFloatingPoint()))
4093 return CharUnits::fromQuantity(AlignTy->isVectorType() ? 16 : 4);
4094 return CharUnits::fromQuantity(4);
4097 // TODO: this implementation is now likely redundant with
4098 // DefaultABIInfo::EmitVAArg.
4099 Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
4100 QualType Ty) const {
4101 if (getTarget().getTriple().isOSDarwin()) {
4102 auto TI = getContext().getTypeInfoInChars(Ty);
4103 TI.second = getParamTypeAlignment(Ty);
4105 CharUnits SlotSize = CharUnits::fromQuantity(4);
4106 return emitVoidPtrVAArg(CGF, VAList, Ty,
4107 classifyArgumentType(Ty).isIndirect(), TI, SlotSize,
4108 /*AllowHigherAlign=*/true);
4111 const unsigned OverflowLimit = 8;
4112 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4113 // TODO: Implement this. For now ignore.
4115 return Address::invalid(); // FIXME?
4118 // struct __va_list_tag {
4119 // unsigned char gpr;
4120 // unsigned char fpr;
4121 // unsigned short reserved;
4122 // void *overflow_arg_area;
4123 // void *reg_save_area;
4126 bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;
4128 Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType();
4129 bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(Ty) == 64;
4131 // All aggregates are passed indirectly? That doesn't seem consistent
4132 // with the argument-lowering code.
4133 bool isIndirect = Ty->isAggregateType();
4135 CGBuilderTy &Builder = CGF.Builder;
4137 // The calling convention either uses 1-2 GPRs or 1 FPR.
4138 Address NumRegsAddr = Address::invalid();
4139 if (isInt || IsSoftFloatABI) {
4140 NumRegsAddr = Builder.CreateStructGEP(VAList, 0, CharUnits::Zero(), "gpr");
4142 NumRegsAddr = Builder.CreateStructGEP(VAList, 1, CharUnits::One(), "fpr");
4145 llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs");
4147 // "Align" the register count when TY is i64.
4148 if (isI64 || (isF64 && IsSoftFloatABI)) {
4149 NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1));
4150 NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U));
4154 Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond");
4156 llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
4157 llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
4158 llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
4160 Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
4162 llvm::Type *DirectTy = CGF.ConvertType(Ty);
4163 if (isIndirect) DirectTy = DirectTy->getPointerTo(0);
4165 // Case 1: consume registers.
4166 Address RegAddr = Address::invalid();
4168 CGF.EmitBlock(UsingRegs);
4170 Address RegSaveAreaPtr =
4171 Builder.CreateStructGEP(VAList, 4, CharUnits::fromQuantity(8));
4172 RegAddr = Address(Builder.CreateLoad(RegSaveAreaPtr),
4173 CharUnits::fromQuantity(8));
4174 assert(RegAddr.getElementType() == CGF.Int8Ty);
4176 // Floating-point registers start after the general-purpose registers.
4177 if (!(isInt || IsSoftFloatABI)) {
4178 RegAddr = Builder.CreateConstInBoundsByteGEP(RegAddr,
4179 CharUnits::fromQuantity(32));
4182 // Get the address of the saved value by scaling the number of
4183 // registers we've used by the number of
4184 CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8);
4185 llvm::Value *RegOffset =
4186 Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity()));
4187 RegAddr = Address(Builder.CreateInBoundsGEP(CGF.Int8Ty,
4188 RegAddr.getPointer(), RegOffset),
4189 RegAddr.getAlignment().alignmentOfArrayElement(RegSize));
4190 RegAddr = Builder.CreateElementBitCast(RegAddr, DirectTy);
4192 // Increase the used-register count.
4194 Builder.CreateAdd(NumRegs,
4195 Builder.getInt8((isI64 || (isF64 && IsSoftFloatABI)) ? 2 : 1));
4196 Builder.CreateStore(NumRegs, NumRegsAddr);
4198 CGF.EmitBranch(Cont);
4201 // Case 2: consume space in the overflow area.
4202 Address MemAddr = Address::invalid();
4204 CGF.EmitBlock(UsingOverflow);
4206 Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr);
4208 // Everything in the overflow area is rounded up to a size of at least 4.
4209 CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4);
4213 auto TypeInfo = CGF.getContext().getTypeInfoInChars(Ty);
4214 Size = TypeInfo.first.alignTo(OverflowAreaAlign);
4216 Size = CGF.getPointerSize();
4219 Address OverflowAreaAddr =
4220 Builder.CreateStructGEP(VAList, 3, CharUnits::fromQuantity(4));
4221 Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr, "argp.cur"),
4223 // Round up address of argument to alignment
4224 CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
4225 if (Align > OverflowAreaAlign) {
4226 llvm::Value *Ptr = OverflowArea.getPointer();
4227 OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),
4231 MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy);
4233 // Increase the overflow area.
4234 OverflowArea = Builder.CreateConstInBoundsByteGEP(OverflowArea, Size);
4235 Builder.CreateStore(OverflowArea.getPointer(), OverflowAreaAddr);
4236 CGF.EmitBranch(Cont);
4239 CGF.EmitBlock(Cont);
4241 // Merge the cases with a phi.
4242 Address Result = emitMergePHI(CGF, RegAddr, UsingRegs, MemAddr, UsingOverflow,
4245 // Load the pointer if the argument was passed indirectly.
4247 Result = Address(Builder.CreateLoad(Result, "aggr"),
4248 getContext().getTypeAlignInChars(Ty));
4255 PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4256 llvm::Value *Address) const {
4257 // This is calculated from the LLVM and GCC tables and verified
4258 // against gcc output. AFAIK all ABIs use the same encoding.
4260 CodeGen::CGBuilderTy &Builder = CGF.Builder;
4262 llvm::IntegerType *i8 = CGF.Int8Ty;
4263 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4264 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4265 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4267 // 0-31: r0-31, the 4-byte general-purpose registers
4268 AssignToArrayRange(Builder, Address, Four8, 0, 31);
4270 // 32-63: fp0-31, the 8-byte floating-point registers
4271 AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4273 // 64-76 are various 4-byte special-purpose registers:
4280 AssignToArrayRange(Builder, Address, Four8, 64, 76);
4282 // 77-108: v0-31, the 16-byte vector registers
4283 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4290 AssignToArrayRange(Builder, Address, Four8, 109, 113);
4298 /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
4299 class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
4307 static const unsigned GPRBits = 64;
4310 bool IsSoftFloatABI;
4312 // A vector of float or double will be promoted to <4 x f32> or <4 x f64> and
4313 // will be passed in a QPX register.
4314 bool IsQPXVectorTy(const Type *Ty) const {
4318 if (const VectorType *VT = Ty->getAs<VectorType>()) {
4319 unsigned NumElements = VT->getNumElements();
4320 if (NumElements == 1)
4323 if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) {
4324 if (getContext().getTypeSize(Ty) <= 256)
4326 } else if (VT->getElementType()->
4327 isSpecificBuiltinType(BuiltinType::Float)) {
4328 if (getContext().getTypeSize(Ty) <= 128)
4336 bool IsQPXVectorTy(QualType Ty) const {
4337 return IsQPXVectorTy(Ty.getTypePtr());
4341 PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
4343 : SwiftABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
4344 IsSoftFloatABI(SoftFloatABI) {}
4346 bool isPromotableTypeForABI(QualType Ty) const;
4347 CharUnits getParamTypeAlignment(QualType Ty) const;
4349 ABIArgInfo classifyReturnType(QualType RetTy) const;
4350 ABIArgInfo classifyArgumentType(QualType Ty) const;
4352 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4353 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4354 uint64_t Members) const override;
4356 // TODO: We can add more logic to computeInfo to improve performance.
4357 // Example: For aggregate arguments that fit in a register, we could
4358 // use getDirectInReg (as is done below for structs containing a single
4359 // floating-point value) to avoid pushing them to memory on function
4360 // entry. This would require changing the logic in PPCISelLowering
4361 // when lowering the parameters in the caller and args in the callee.
4362 void computeInfo(CGFunctionInfo &FI) const override {
4363 if (!getCXXABI().classifyReturnType(FI))
4364 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
4365 for (auto &I : FI.arguments()) {
4366 // We rely on the default argument classification for the most part.
4367 // One exception: An aggregate containing a single floating-point
4368 // or vector item must be passed in a register if one is available.
4369 const Type *T = isSingleElementStruct(I.type, getContext());
4371 const BuiltinType *BT = T->getAs<BuiltinType>();
4372 if (IsQPXVectorTy(T) ||
4373 (T->isVectorType() && getContext().getTypeSize(T) == 128) ||
4374 (BT && BT->isFloatingPoint())) {
4376 I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
4380 I.info = classifyArgumentType(I.type);
4384 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4385 QualType Ty) const override;
4387 bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
4388 bool asReturnValue) const override {
4389 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
4392 bool isSwiftErrorInRegister() const override {
4397 class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
4400 PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT,
4401 PPC64_SVR4_ABIInfo::ABIKind Kind, bool HasQPX,
4403 : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT, Kind, HasQPX,
4406 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4407 // This is recovered from gcc output.
4408 return 1; // r1 is the dedicated stack pointer
4411 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4412 llvm::Value *Address) const override;
4415 class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
4417 PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
4419 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4420 // This is recovered from gcc output.
4421 return 1; // r1 is the dedicated stack pointer
4424 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4425 llvm::Value *Address) const override;
4430 // Return true if the ABI requires Ty to be passed sign- or zero-
4431 // extended to 64 bits.
4433 PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
4434 // Treat an enum type as its underlying type.
4435 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4436 Ty = EnumTy->getDecl()->getIntegerType();
4438 // Promotable integer types are required to be promoted by the ABI.
4439 if (Ty->isPromotableIntegerType())
4442 // In addition to the usual promotable integer types, we also need to
4443 // extend all 32-bit types, since the ABI requires promotion to 64 bits.
4444 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
4445 switch (BT->getKind()) {
4446 case BuiltinType::Int:
4447 case BuiltinType::UInt:
4456 /// isAlignedParamType - Determine whether a type requires 16-byte or
4457 /// higher alignment in the parameter area. Always returns at least 8.
4458 CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4459 // Complex types are passed just like their elements.
4460 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4461 Ty = CTy->getElementType();
4463 // Only vector types of size 16 bytes need alignment (larger types are
4464 // passed via reference, smaller types are not aligned).
4465 if (IsQPXVectorTy(Ty)) {
4466 if (getContext().getTypeSize(Ty) > 128)
4467 return CharUnits::fromQuantity(32);
4469 return CharUnits::fromQuantity(16);
4470 } else if (Ty->isVectorType()) {
4471 return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);
4474 // For single-element float/vector structs, we consider the whole type
4475 // to have the same alignment requirements as its single element.
4476 const Type *AlignAsType = nullptr;
4477 const Type *EltType = isSingleElementStruct(Ty, getContext());
4479 const BuiltinType *BT = EltType->getAs<BuiltinType>();
4480 if (IsQPXVectorTy(EltType) || (EltType->isVectorType() &&
4481 getContext().getTypeSize(EltType) == 128) ||
4482 (BT && BT->isFloatingPoint()))
4483 AlignAsType = EltType;
4486 // Likewise for ELFv2 homogeneous aggregates.
4487 const Type *Base = nullptr;
4488 uint64_t Members = 0;
4489 if (!AlignAsType && Kind == ELFv2 &&
4490 isAggregateTypeForABI(Ty) && isHomogeneousAggregate(Ty, Base, Members))
4493 // With special case aggregates, only vector base types need alignment.
4494 if (AlignAsType && IsQPXVectorTy(AlignAsType)) {
4495 if (getContext().getTypeSize(AlignAsType) > 128)
4496 return CharUnits::fromQuantity(32);
4498 return CharUnits::fromQuantity(16);
4499 } else if (AlignAsType) {
4500 return CharUnits::fromQuantity(AlignAsType->isVectorType() ? 16 : 8);
4503 // Otherwise, we only need alignment for any aggregate type that
4504 // has an alignment requirement of >= 16 bytes.
4505 if (isAggregateTypeForABI(Ty) && getContext().getTypeAlign(Ty) >= 128) {
4506 if (HasQPX && getContext().getTypeAlign(Ty) >= 256)
4507 return CharUnits::fromQuantity(32);
4508 return CharUnits::fromQuantity(16);
4511 return CharUnits::fromQuantity(8);
4514 /// isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous
4515 /// aggregate. Base is set to the base element type, and Members is set
4516 /// to the number of base elements.
4517 bool ABIInfo::isHomogeneousAggregate(QualType Ty, const Type *&Base,
4518 uint64_t &Members) const {
4519 if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
4520 uint64_t NElements = AT->getSize().getZExtValue();
4523 if (!isHomogeneousAggregate(AT->getElementType(), Base, Members))
4525 Members *= NElements;
4526 } else if (const RecordType *RT = Ty->getAs<RecordType>()) {
4527 const RecordDecl *RD = RT->getDecl();
4528 if (RD->hasFlexibleArrayMember())
4533 // If this is a C++ record, check the bases first.
4534 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
4535 for (const auto &I : CXXRD->bases()) {
4536 // Ignore empty records.
4537 if (isEmptyRecord(getContext(), I.getType(), true))
4540 uint64_t FldMembers;
4541 if (!isHomogeneousAggregate(I.getType(), Base, FldMembers))
4544 Members += FldMembers;
4548 for (const auto *FD : RD->fields()) {
4549 // Ignore (non-zero arrays of) empty records.
4550 QualType FT = FD->getType();
4551 while (const ConstantArrayType *AT =
4552 getContext().getAsConstantArrayType(FT)) {
4553 if (AT->getSize().getZExtValue() == 0)
4555 FT = AT->getElementType();
4557 if (isEmptyRecord(getContext(), FT, true))
4560 // For compatibility with GCC, ignore empty bitfields in C++ mode.
4561 if (getContext().getLangOpts().CPlusPlus &&
4562 FD->isZeroLengthBitField(getContext()))
4565 uint64_t FldMembers;
4566 if (!isHomogeneousAggregate(FD->getType(), Base, FldMembers))
4569 Members = (RD->isUnion() ?
4570 std::max(Members, FldMembers) : Members + FldMembers);
4576 // Ensure there is no padding.
4577 if (getContext().getTypeSize(Base) * Members !=
4578 getContext().getTypeSize(Ty))
4582 if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
4584 Ty = CT->getElementType();
4587 // Most ABIs only support float, double, and some vector type widths.
4588 if (!isHomogeneousAggregateBaseType(Ty))
4591 // The base type must be the same for all members. Types that
4592 // agree in both total size and mode (float vs. vector) are
4593 // treated as being equivalent here.
4594 const Type *TyPtr = Ty.getTypePtr();
4597 // If it's a non-power-of-2 vector, its size is already a power-of-2,
4598 // so make sure to widen it explicitly.
4599 if (const VectorType *VT = Base->getAs<VectorType>()) {
4600 QualType EltTy = VT->getElementType();
4601 unsigned NumElements =
4602 getContext().getTypeSize(VT) / getContext().getTypeSize(EltTy);
4604 .getVectorType(EltTy, NumElements, VT->getVectorKind())
4609 if (Base->isVectorType() != TyPtr->isVectorType() ||
4610 getContext().getTypeSize(Base) != getContext().getTypeSize(TyPtr))
4613 return Members > 0 && isHomogeneousAggregateSmallEnough(Base, Members);
4616 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
4617 // Homogeneous aggregates for ELFv2 must have base types of float,
4618 // double, long double, or 128-bit vectors.
4619 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4620 if (BT->getKind() == BuiltinType::Float ||
4621 BT->getKind() == BuiltinType::Double ||
4622 BT->getKind() == BuiltinType::LongDouble ||
4623 (getContext().getTargetInfo().hasFloat128Type() &&
4624 (BT->getKind() == BuiltinType::Float128))) {
4630 if (const VectorType *VT = Ty->getAs<VectorType>()) {
4631 if (getContext().getTypeSize(VT) == 128 || IsQPXVectorTy(Ty))
4637 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
4638 const Type *Base, uint64_t Members) const {
4639 // Vector and fp128 types require one register, other floating point types
4640 // require one or two registers depending on their size.
4642 ((getContext().getTargetInfo().hasFloat128Type() &&
4643 Base->isFloat128Type()) ||
4644 Base->isVectorType()) ? 1
4645 : (getContext().getTypeSize(Base) + 63) / 64;
4647 // Homogeneous Aggregates may occupy at most 8 registers.
4648 return Members * NumRegs <= 8;
4652 PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
4653 Ty = useFirstFieldIfTransparentUnion(Ty);
4655 if (Ty->isAnyComplexType())
4656 return ABIArgInfo::getDirect();
4658 // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
4659 // or via reference (larger than 16 bytes).
4660 if (Ty->isVectorType() && !IsQPXVectorTy(Ty)) {
4661 uint64_t Size = getContext().getTypeSize(Ty);
4663 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4664 else if (Size < 128) {
4665 llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4666 return ABIArgInfo::getDirect(CoerceTy);
4670 if (isAggregateTypeForABI(Ty)) {
4671 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
4672 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
4674 uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity();
4675 uint64_t TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();
4677 // ELFv2 homogeneous aggregates are passed as array types.
4678 const Type *Base = nullptr;
4679 uint64_t Members = 0;
4680 if (Kind == ELFv2 &&
4681 isHomogeneousAggregate(Ty, Base, Members)) {
4682 llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4683 llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4684 return ABIArgInfo::getDirect(CoerceTy);
4687 // If an aggregate may end up fully in registers, we do not
4688 // use the ByVal method, but pass the aggregate as array.
4689 // This is usually beneficial since we avoid forcing the
4690 // back-end to store the argument to memory.
4691 uint64_t Bits = getContext().getTypeSize(Ty);
4692 if (Bits > 0 && Bits <= 8 * GPRBits) {
4693 llvm::Type *CoerceTy;
4695 // Types up to 8 bytes are passed as integer type (which will be
4696 // properly aligned in the argument save area doubleword).
4697 if (Bits <= GPRBits)
4699 llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4700 // Larger types are passed as arrays, with the base type selected
4701 // according to the required alignment in the save area.
4703 uint64_t RegBits = ABIAlign * 8;
4704 uint64_t NumRegs = llvm::alignTo(Bits, RegBits) / RegBits;
4705 llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits);
4706 CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);
4709 return ABIArgInfo::getDirect(CoerceTy);
4712 // All other aggregates are passed ByVal.
4713 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(ABIAlign),
4715 /*Realign=*/TyAlign > ABIAlign);
4718 return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
4719 : ABIArgInfo::getDirect());
4723 PPC64_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {
4724 if (RetTy->isVoidType())
4725 return ABIArgInfo::getIgnore();
4727 if (RetTy->isAnyComplexType())
4728 return ABIArgInfo::getDirect();
4730 // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
4731 // or via reference (larger than 16 bytes).
4732 if (RetTy->isVectorType() && !IsQPXVectorTy(RetTy)) {
4733 uint64_t Size = getContext().getTypeSize(RetTy);
4735 return getNaturalAlignIndirect(RetTy);
4736 else if (Size < 128) {
4737 llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4738 return ABIArgInfo::getDirect(CoerceTy);
4742 if (isAggregateTypeForABI(RetTy)) {
4743 // ELFv2 homogeneous aggregates are returned as array types.
4744 const Type *Base = nullptr;
4745 uint64_t Members = 0;
4746 if (Kind == ELFv2 &&
4747 isHomogeneousAggregate(RetTy, Base, Members)) {
4748 llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4749 llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4750 return ABIArgInfo::getDirect(CoerceTy);
4753 // ELFv2 small aggregates are returned in up to two registers.
4754 uint64_t Bits = getContext().getTypeSize(RetTy);
4755 if (Kind == ELFv2 && Bits <= 2 * GPRBits) {
4757 return ABIArgInfo::getIgnore();
4759 llvm::Type *CoerceTy;
4760 if (Bits > GPRBits) {
4761 CoerceTy = llvm::IntegerType::get(getVMContext(), GPRBits);
4762 CoerceTy = llvm::StructType::get(CoerceTy, CoerceTy);
4765 llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4766 return ABIArgInfo::getDirect(CoerceTy);
4769 // All other aggregates are returned indirectly.
4770 return getNaturalAlignIndirect(RetTy);
4773 return (isPromotableTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
4774 : ABIArgInfo::getDirect());
4777 // Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
4778 Address PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4779 QualType Ty) const {
4780 auto TypeInfo = getContext().getTypeInfoInChars(Ty);
4781 TypeInfo.second = getParamTypeAlignment(Ty);
4783 CharUnits SlotSize = CharUnits::fromQuantity(8);
4785 // If we have a complex type and the base type is smaller than 8 bytes,
4786 // the ABI calls for the real and imaginary parts to be right-adjusted
4787 // in separate doublewords. However, Clang expects us to produce a
4788 // pointer to a structure with the two parts packed tightly. So generate
4789 // loads of the real and imaginary parts relative to the va_list pointer,
4790 // and store them to a temporary structure.
4791 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4792 CharUnits EltSize = TypeInfo.first / 2;
4793 if (EltSize < SlotSize) {
4794 Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty,
4795 SlotSize * 2, SlotSize,
4796 SlotSize, /*AllowHigher*/ true);
4798 Address RealAddr = Addr;
4799 Address ImagAddr = RealAddr;
4800 if (CGF.CGM.getDataLayout().isBigEndian()) {
4801 RealAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr,
4802 SlotSize - EltSize);
4803 ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(ImagAddr,
4804 2 * SlotSize - EltSize);
4806 ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize);
4809 llvm::Type *EltTy = CGF.ConvertTypeForMem(CTy->getElementType());
4810 RealAddr = CGF.Builder.CreateElementBitCast(RealAddr, EltTy);
4811 ImagAddr = CGF.Builder.CreateElementBitCast(ImagAddr, EltTy);
4812 llvm::Value *Real = CGF.Builder.CreateLoad(RealAddr, ".vareal");
4813 llvm::Value *Imag = CGF.Builder.CreateLoad(ImagAddr, ".vaimag");
4815 Address Temp = CGF.CreateMemTemp(Ty, "vacplx");
4816 CGF.EmitStoreOfComplex({Real, Imag}, CGF.MakeAddrLValue(Temp, Ty),
4822 // Otherwise, just use the general rule.
4823 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
4824 TypeInfo, SlotSize, /*AllowHigher*/ true);
4828 PPC64_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4829 llvm::Value *Address) {
4830 // This is calculated from the LLVM and GCC tables and verified
4831 // against gcc output. AFAIK all ABIs use the same encoding.
4833 CodeGen::CGBuilderTy &Builder = CGF.Builder;
4835 llvm::IntegerType *i8 = CGF.Int8Ty;
4836 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4837 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4838 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4840 // 0-31: r0-31, the 8-byte general-purpose registers
4841 AssignToArrayRange(Builder, Address, Eight8, 0, 31);
4843 // 32-63: fp0-31, the 8-byte floating-point registers
4844 AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4846 // 64-67 are various 8-byte special-purpose registers:
4851 AssignToArrayRange(Builder, Address, Eight8, 64, 67);
4853 // 68-76 are various 4-byte special-purpose registers:
4856 AssignToArrayRange(Builder, Address, Four8, 68, 76);
4858 // 77-108: v0-31, the 16-byte vector registers
4859 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4869 AssignToArrayRange(Builder, Address, Eight8, 109, 116);
4875 PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
4876 CodeGen::CodeGenFunction &CGF,
4877 llvm::Value *Address) const {
4879 return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4883 PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4884 llvm::Value *Address) const {
4886 return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4889 //===----------------------------------------------------------------------===//
4890 // AArch64 ABI Implementation
4891 //===----------------------------------------------------------------------===//
4895 class AArch64ABIInfo : public SwiftABIInfo {
4907 AArch64ABIInfo(CodeGenTypes &CGT, ABIKind Kind)
4908 : SwiftABIInfo(CGT), Kind(Kind) {}
4911 ABIKind getABIKind() const { return Kind; }
4912 bool isDarwinPCS() const { return Kind == DarwinPCS; }
4914 ABIArgInfo classifyReturnType(QualType RetTy) const;
4915 ABIArgInfo classifyArgumentType(QualType RetTy) const;
4916 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4917 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4918 uint64_t Members) const override;
4920 bool isIllegalVectorType(QualType Ty) const;
4922 void computeInfo(CGFunctionInfo &FI) const override {
4923 if (!::classifyReturnType(getCXXABI(), FI, *this))
4924 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
4926 for (auto &it : FI.arguments())
4927 it.info = classifyArgumentType(it.type);
4930 Address EmitDarwinVAArg(Address VAListAddr, QualType Ty,
4931 CodeGenFunction &CGF) const;
4933 Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
4934 CodeGenFunction &CGF) const;
4936 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4937 QualType Ty) const override {
4938 return Kind == Win64 ? EmitMSVAArg(CGF, VAListAddr, Ty)
4939 : isDarwinPCS() ? EmitDarwinVAArg(VAListAddr, Ty, CGF)
4940 : EmitAAPCSVAArg(VAListAddr, Ty, CGF);
4943 Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
4944 QualType Ty) const override;
4946 bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
4947 bool asReturnValue) const override {
4948 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
4950 bool isSwiftErrorInRegister() const override {
4954 bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
4955 unsigned elts) const override;
4958 class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
4960 AArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind Kind)
4961 : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
4963 StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
4964 return "mov\tfp, fp\t\t// marker for objc_retainAutoreleaseReturnValue";
4967 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4971 bool doesReturnSlotInterfereWithArgs() const override { return false; }
4974 class WindowsAArch64TargetCodeGenInfo : public AArch64TargetCodeGenInfo {
4976 WindowsAArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind K)
4977 : AArch64TargetCodeGenInfo(CGT, K) {}
4979 void getDependentLibraryOption(llvm::StringRef Lib,
4980 llvm::SmallString<24> &Opt) const override {
4981 Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
4984 void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
4985 llvm::SmallString<32> &Opt) const override {
4986 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
4991 ABIArgInfo AArch64ABIInfo::classifyArgumentType(QualType Ty) const {
4992 Ty = useFirstFieldIfTransparentUnion(Ty);
4994 // Handle illegal vector types here.
4995 if (isIllegalVectorType(Ty)) {
4996 uint64_t Size = getContext().getTypeSize(Ty);
4997 // Android promotes <2 x i8> to i16, not i32
4998 if (isAndroid() && (Size <= 16)) {
4999 llvm::Type *ResType = llvm::Type::getInt16Ty(getVMContext());
5000 return ABIArgInfo::getDirect(ResType);
5003 llvm::Type *ResType = llvm::Type::getInt32Ty(getVMContext());
5004 return ABIArgInfo::getDirect(ResType);
5007 llvm::Type *ResType =
5008 llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 2);
5009 return ABIArgInfo::getDirect(ResType);
5012 llvm::Type *ResType =
5013 llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 4);
5014 return ABIArgInfo::getDirect(ResType);
5016 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5019 if (!isAggregateTypeForABI(Ty)) {
5020 // Treat an enum type as its underlying type.
5021 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
5022 Ty = EnumTy->getDecl()->getIntegerType();
5024 return (Ty->isPromotableIntegerType() && isDarwinPCS()
5025 ? ABIArgInfo::getExtend(Ty)
5026 : ABIArgInfo::getDirect());
5029 // Structures with either a non-trivial destructor or a non-trivial
5030 // copy constructor are always indirect.
5031 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
5032 return getNaturalAlignIndirect(Ty, /*ByVal=*/RAA ==
5033 CGCXXABI::RAA_DirectInMemory);
5036 // Empty records are always ignored on Darwin, but actually passed in C++ mode
5037 // elsewhere for GNU compatibility.
5038 uint64_t Size = getContext().getTypeSize(Ty);
5039 bool IsEmpty = isEmptyRecord(getContext(), Ty, true);
5040 if (IsEmpty || Size == 0) {
5041 if (!getContext().getLangOpts().CPlusPlus || isDarwinPCS())
5042 return ABIArgInfo::getIgnore();
5044 // GNU C mode. The only argument that gets ignored is an empty one with size
5046 if (IsEmpty && Size == 0)
5047 return ABIArgInfo::getIgnore();
5048 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
5051 // Homogeneous Floating-point Aggregates (HFAs) need to be expanded.
5052 const Type *Base = nullptr;
5053 uint64_t Members = 0;
5054 if (isHomogeneousAggregate(Ty, Base, Members)) {
5055 return ABIArgInfo::getDirect(
5056 llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members));
5059 // Aggregates <= 16 bytes are passed directly in registers or on the stack.
5061 // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
5062 // same size and alignment.
5063 if (getTarget().isRenderScriptTarget()) {
5064 return coerceToIntArray(Ty, getContext(), getVMContext());
5067 if (Kind == AArch64ABIInfo::AAPCS) {
5068 Alignment = getContext().getTypeUnadjustedAlign(Ty);
5069 Alignment = Alignment < 128 ? 64 : 128;
5071 Alignment = getContext().getTypeAlign(Ty);
5073 Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes
5075 // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
5076 // For aggregates with 16-byte alignment, we use i128.
5077 if (Alignment < 128 && Size == 128) {
5078 llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
5079 return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
5081 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
5084 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5087 ABIArgInfo AArch64ABIInfo::classifyReturnType(QualType RetTy) const {
5088 if (RetTy->isVoidType())
5089 return ABIArgInfo::getIgnore();
5091 // Large vector types should be returned via memory.
5092 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128)
5093 return getNaturalAlignIndirect(RetTy);
5095 if (!isAggregateTypeForABI(RetTy)) {
5096 // Treat an enum type as its underlying type.
5097 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5098 RetTy = EnumTy->getDecl()->getIntegerType();
5100 return (RetTy->isPromotableIntegerType() && isDarwinPCS()
5101 ? ABIArgInfo::getExtend(RetTy)
5102 : ABIArgInfo::getDirect());
5105 uint64_t Size = getContext().getTypeSize(RetTy);
5106 if (isEmptyRecord(getContext(), RetTy, true) || Size == 0)
5107 return ABIArgInfo::getIgnore();
5109 const Type *Base = nullptr;
5110 uint64_t Members = 0;
5111 if (isHomogeneousAggregate(RetTy, Base, Members))
5112 // Homogeneous Floating-point Aggregates (HFAs) are returned directly.
5113 return ABIArgInfo::getDirect();
5115 // Aggregates <= 16 bytes are returned directly in registers or on the stack.
5117 // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
5118 // same size and alignment.
5119 if (getTarget().isRenderScriptTarget()) {
5120 return coerceToIntArray(RetTy, getContext(), getVMContext());
5122 unsigned Alignment = getContext().getTypeAlign(RetTy);
5123 Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes
5125 // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
5126 // For aggregates with 16-byte alignment, we use i128.
5127 if (Alignment < 128 && Size == 128) {
5128 llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
5129 return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
5131 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
5134 return getNaturalAlignIndirect(RetTy);
5137 /// isIllegalVectorType - check whether the vector type is legal for AArch64.
5138 bool AArch64ABIInfo::isIllegalVectorType(QualType Ty) const {
5139 if (const VectorType *VT = Ty->getAs<VectorType>()) {
5140 // Check whether VT is legal.
5141 unsigned NumElements = VT->getNumElements();
5142 uint64_t Size = getContext().getTypeSize(VT);
5143 // NumElements should be power of 2.
5144 if (!llvm::isPowerOf2_32(NumElements))
5146 return Size != 64 && (Size != 128 || NumElements == 1);
5151 bool AArch64ABIInfo::isLegalVectorTypeForSwift(CharUnits totalSize,
5153 unsigned elts) const {
5154 if (!llvm::isPowerOf2_32(elts))
5156 if (totalSize.getQuantity() != 8 &&
5157 (totalSize.getQuantity() != 16 || elts == 1))
5162 bool AArch64ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
5163 // Homogeneous aggregates for AAPCS64 must have base types of a floating
5164 // point type or a short-vector type. This is the same as the 32-bit ABI,
5165 // but with the difference that any floating-point type is allowed,
5166 // including __fp16.
5167 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
5168 if (BT->isFloatingPoint())
5170 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
5171 unsigned VecSize = getContext().getTypeSize(VT);
5172 if (VecSize == 64 || VecSize == 128)
5178 bool AArch64ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
5179 uint64_t Members) const {
5180 return Members <= 4;
5183 Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr,
5185 CodeGenFunction &CGF) const {
5186 ABIArgInfo AI = classifyArgumentType(Ty);
5187 bool IsIndirect = AI.isIndirect();
5189 llvm::Type *BaseTy = CGF.ConvertType(Ty);
5191 BaseTy = llvm::PointerType::getUnqual(BaseTy);
5192 else if (AI.getCoerceToType())
5193 BaseTy = AI.getCoerceToType();
5195 unsigned NumRegs = 1;
5196 if (llvm::ArrayType *ArrTy = dyn_cast<llvm::ArrayType>(BaseTy)) {
5197 BaseTy = ArrTy->getElementType();
5198 NumRegs = ArrTy->getNumElements();
5200 bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy();
5202 // The AArch64 va_list type and handling is specified in the Procedure Call
5203 // Standard, section B.4:
5213 llvm::BasicBlock *MaybeRegBlock = CGF.createBasicBlock("vaarg.maybe_reg");
5214 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
5215 llvm::BasicBlock *OnStackBlock = CGF.createBasicBlock("vaarg.on_stack");
5216 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
5218 auto TyInfo = getContext().getTypeInfoInChars(Ty);
5219 CharUnits TyAlign = TyInfo.second;
5221 Address reg_offs_p = Address::invalid();
5222 llvm::Value *reg_offs = nullptr;
5224 CharUnits reg_top_offset;
5225 int RegSize = IsIndirect ? 8 : TyInfo.first.getQuantity();
5227 // 3 is the field number of __gr_offs
5229 CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(24),
5231 reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "gr_offs");
5232 reg_top_index = 1; // field number for __gr_top
5233 reg_top_offset = CharUnits::fromQuantity(8);
5234 RegSize = llvm::alignTo(RegSize, 8);
5236 // 4 is the field number of __vr_offs.
5238 CGF.Builder.CreateStructGEP(VAListAddr, 4, CharUnits::fromQuantity(28),
5240 reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "vr_offs");
5241 reg_top_index = 2; // field number for __vr_top
5242 reg_top_offset = CharUnits::fromQuantity(16);
5243 RegSize = 16 * NumRegs;
5246 //=======================================
5247 // Find out where argument was passed
5248 //=======================================
5250 // If reg_offs >= 0 we're already using the stack for this type of
5251 // argument. We don't want to keep updating reg_offs (in case it overflows,
5252 // though anyone passing 2GB of arguments, each at most 16 bytes, deserves
5253 // whatever they get).
5254 llvm::Value *UsingStack = nullptr;
5255 UsingStack = CGF.Builder.CreateICmpSGE(
5256 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, 0));
5258 CGF.Builder.CreateCondBr(UsingStack, OnStackBlock, MaybeRegBlock);
5260 // Otherwise, at least some kind of argument could go in these registers, the
5261 // question is whether this particular type is too big.
5262 CGF.EmitBlock(MaybeRegBlock);
5264 // Integer arguments may need to correct register alignment (for example a
5265 // "struct { __int128 a; };" gets passed in x_2N, x_{2N+1}). In this case we
5266 // align __gr_offs to calculate the potential address.
5267 if (!IsFPR && !IsIndirect && TyAlign.getQuantity() > 8) {
5268 int Align = TyAlign.getQuantity();
5270 reg_offs = CGF.Builder.CreateAdd(
5271 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, Align - 1),
5273 reg_offs = CGF.Builder.CreateAnd(
5274 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, -Align),
5278 // Update the gr_offs/vr_offs pointer for next call to va_arg on this va_list.
5279 // The fact that this is done unconditionally reflects the fact that
5280 // allocating an argument to the stack also uses up all the remaining
5281 // registers of the appropriate kind.
5282 llvm::Value *NewOffset = nullptr;
5283 NewOffset = CGF.Builder.CreateAdd(
5284 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs");
5285 CGF.Builder.CreateStore(NewOffset, reg_offs_p);
5287 // Now we're in a position to decide whether this argument really was in
5288 // registers or not.
5289 llvm::Value *InRegs = nullptr;
5290 InRegs = CGF.Builder.CreateICmpSLE(
5291 NewOffset, llvm::ConstantInt::get(CGF.Int32Ty, 0), "inreg");
5293 CGF.Builder.CreateCondBr(InRegs, InRegBlock, OnStackBlock);
5295 //=======================================
5296 // Argument was in registers
5297 //=======================================
5299 // Now we emit the code for if the argument was originally passed in
5300 // registers. First start the appropriate block:
5301 CGF.EmitBlock(InRegBlock);
5303 llvm::Value *reg_top = nullptr;
5304 Address reg_top_p = CGF.Builder.CreateStructGEP(VAListAddr, reg_top_index,
5305 reg_top_offset, "reg_top_p");
5306 reg_top = CGF.Builder.CreateLoad(reg_top_p, "reg_top");
5307 Address BaseAddr(CGF.Builder.CreateInBoundsGEP(reg_top, reg_offs),
5308 CharUnits::fromQuantity(IsFPR ? 16 : 8));
5309 Address RegAddr = Address::invalid();
5310 llvm::Type *MemTy = CGF.ConvertTypeForMem(Ty);
5313 // If it's been passed indirectly (actually a struct), whatever we find from
5314 // stored registers or on the stack will actually be a struct **.
5315 MemTy = llvm::PointerType::getUnqual(MemTy);
5318 const Type *Base = nullptr;
5319 uint64_t NumMembers = 0;
5320 bool IsHFA = isHomogeneousAggregate(Ty, Base, NumMembers);
5321 if (IsHFA && NumMembers > 1) {
5322 // Homogeneous aggregates passed in registers will have their elements split
5323 // and stored 16-bytes apart regardless of size (they're notionally in qN,
5324 // qN+1, ...). We reload and store into a temporary local variable
5326 assert(!IsIndirect && "Homogeneous aggregates should be passed directly");
5327 auto BaseTyInfo = getContext().getTypeInfoInChars(QualType(Base, 0));
5328 llvm::Type *BaseTy = CGF.ConvertType(QualType(Base, 0));
5329 llvm::Type *HFATy = llvm::ArrayType::get(BaseTy, NumMembers);
5330 Address Tmp = CGF.CreateTempAlloca(HFATy,
5331 std::max(TyAlign, BaseTyInfo.second));
5333 // On big-endian platforms, the value will be right-aligned in its slot.
5335 if (CGF.CGM.getDataLayout().isBigEndian() &&
5336 BaseTyInfo.first.getQuantity() < 16)
5337 Offset = 16 - BaseTyInfo.first.getQuantity();
5339 for (unsigned i = 0; i < NumMembers; ++i) {
5340 CharUnits BaseOffset = CharUnits::fromQuantity(16 * i + Offset);
5342 CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, BaseOffset);
5343 LoadAddr = CGF.Builder.CreateElementBitCast(LoadAddr, BaseTy);
5346 CGF.Builder.CreateConstArrayGEP(Tmp, i, BaseTyInfo.first);
5348 llvm::Value *Elem = CGF.Builder.CreateLoad(LoadAddr);
5349 CGF.Builder.CreateStore(Elem, StoreAddr);
5352 RegAddr = CGF.Builder.CreateElementBitCast(Tmp, MemTy);
5354 // Otherwise the object is contiguous in memory.
5356 // It might be right-aligned in its slot.
5357 CharUnits SlotSize = BaseAddr.getAlignment();
5358 if (CGF.CGM.getDataLayout().isBigEndian() && !IsIndirect &&
5359 (IsHFA || !isAggregateTypeForABI(Ty)) &&
5360 TyInfo.first < SlotSize) {
5361 CharUnits Offset = SlotSize - TyInfo.first;
5362 BaseAddr = CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, Offset);
5365 RegAddr = CGF.Builder.CreateElementBitCast(BaseAddr, MemTy);
5368 CGF.EmitBranch(ContBlock);
5370 //=======================================
5371 // Argument was on the stack
5372 //=======================================
5373 CGF.EmitBlock(OnStackBlock);
5375 Address stack_p = CGF.Builder.CreateStructGEP(VAListAddr, 0,
5376 CharUnits::Zero(), "stack_p");
5377 llvm::Value *OnStackPtr = CGF.Builder.CreateLoad(stack_p, "stack");
5379 // Again, stack arguments may need realignment. In this case both integer and
5380 // floating-point ones might be affected.
5381 if (!IsIndirect && TyAlign.getQuantity() > 8) {
5382 int Align = TyAlign.getQuantity();
5384 OnStackPtr = CGF.Builder.CreatePtrToInt(OnStackPtr, CGF.Int64Ty);
5386 OnStackPtr = CGF.Builder.CreateAdd(
5387 OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, Align - 1),
5389 OnStackPtr = CGF.Builder.CreateAnd(
5390 OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, -Align),
5393 OnStackPtr = CGF.Builder.CreateIntToPtr(OnStackPtr, CGF.Int8PtrTy);
5395 Address OnStackAddr(OnStackPtr,
5396 std::max(CharUnits::fromQuantity(8), TyAlign));
5398 // All stack slots are multiples of 8 bytes.
5399 CharUnits StackSlotSize = CharUnits::fromQuantity(8);
5400 CharUnits StackSize;
5402 StackSize = StackSlotSize;
5404 StackSize = TyInfo.first.alignTo(StackSlotSize);
5406 llvm::Value *StackSizeC = CGF.Builder.getSize(StackSize);
5407 llvm::Value *NewStack =
5408 CGF.Builder.CreateInBoundsGEP(OnStackPtr, StackSizeC, "new_stack");
5410 // Write the new value of __stack for the next call to va_arg
5411 CGF.Builder.CreateStore(NewStack, stack_p);
5413 if (CGF.CGM.getDataLayout().isBigEndian() && !isAggregateTypeForABI(Ty) &&
5414 TyInfo.first < StackSlotSize) {
5415 CharUnits Offset = StackSlotSize - TyInfo.first;
5416 OnStackAddr = CGF.Builder.CreateConstInBoundsByteGEP(OnStackAddr, Offset);
5419 OnStackAddr = CGF.Builder.CreateElementBitCast(OnStackAddr, MemTy);
5421 CGF.EmitBranch(ContBlock);
5423 //=======================================
5425 //=======================================
5426 CGF.EmitBlock(ContBlock);
5428 Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
5429 OnStackAddr, OnStackBlock, "vaargs.addr");
5432 return Address(CGF.Builder.CreateLoad(ResAddr, "vaarg.addr"),
5438 Address AArch64ABIInfo::EmitDarwinVAArg(Address VAListAddr, QualType Ty,
5439 CodeGenFunction &CGF) const {
5440 // The backend's lowering doesn't support va_arg for aggregates or
5441 // illegal vector types. Lower VAArg here for these cases and use
5442 // the LLVM va_arg instruction for everything else.
5443 if (!isAggregateTypeForABI(Ty) && !isIllegalVectorType(Ty))
5444 return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
5446 CharUnits SlotSize = CharUnits::fromQuantity(8);
5448 // Empty records are ignored for parameter passing purposes.
5449 if (isEmptyRecord(getContext(), Ty, true)) {
5450 Address Addr(CGF.Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize);
5451 Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
5455 // The size of the actual thing passed, which might end up just
5456 // being a pointer for indirect types.
5457 auto TyInfo = getContext().getTypeInfoInChars(Ty);
5459 // Arguments bigger than 16 bytes which aren't homogeneous
5460 // aggregates should be passed indirectly.
5461 bool IsIndirect = false;
5462 if (TyInfo.first.getQuantity() > 16) {
5463 const Type *Base = nullptr;
5464 uint64_t Members = 0;
5465 IsIndirect = !isHomogeneousAggregate(Ty, Base, Members);
5468 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
5469 TyInfo, SlotSize, /*AllowHigherAlign*/ true);
5472 Address AArch64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
5473 QualType Ty) const {
5474 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
5475 CGF.getContext().getTypeInfoInChars(Ty),
5476 CharUnits::fromQuantity(8),
5477 /*allowHigherAlign*/ false);
5480 //===----------------------------------------------------------------------===//
5481 // ARM ABI Implementation
5482 //===----------------------------------------------------------------------===//
5486 class ARMABIInfo : public SwiftABIInfo {
5499 ARMABIInfo(CodeGenTypes &CGT, ABIKind _Kind)
5500 : SwiftABIInfo(CGT), Kind(_Kind) {
5504 bool isEABI() const {
5505 switch (getTarget().getTriple().getEnvironment()) {
5506 case llvm::Triple::Android:
5507 case llvm::Triple::EABI:
5508 case llvm::Triple::EABIHF:
5509 case llvm::Triple::GNUEABI:
5510 case llvm::Triple::GNUEABIHF:
5511 case llvm::Triple::MuslEABI:
5512 case llvm::Triple::MuslEABIHF:
5519 bool isEABIHF() const {
5520 switch (getTarget().getTriple().getEnvironment()) {
5521 case llvm::Triple::EABIHF:
5522 case llvm::Triple::GNUEABIHF:
5523 case llvm::Triple::MuslEABIHF:
5530 ABIKind getABIKind() const { return Kind; }
5533 ABIArgInfo classifyReturnType(QualType RetTy, bool isVariadic) const;
5534 ABIArgInfo classifyArgumentType(QualType RetTy, bool isVariadic) const;
5535 bool isIllegalVectorType(QualType Ty) const;
5537 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
5538 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
5539 uint64_t Members) const override;
5541 void computeInfo(CGFunctionInfo &FI) const override;
5543 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5544 QualType Ty) const override;
5546 llvm::CallingConv::ID getLLVMDefaultCC() const;
5547 llvm::CallingConv::ID getABIDefaultCC() const;
5550 bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
5551 bool asReturnValue) const override {
5552 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
5554 bool isSwiftErrorInRegister() const override {
5557 bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
5558 unsigned elts) const override;
5561 class ARMTargetCodeGenInfo : public TargetCodeGenInfo {
5563 ARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5564 :TargetCodeGenInfo(new ARMABIInfo(CGT, K)) {}
5566 const ARMABIInfo &getABIInfo() const {
5567 return static_cast<const ARMABIInfo&>(TargetCodeGenInfo::getABIInfo());
5570 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5574 StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
5575 return "mov\tr7, r7\t\t// marker for objc_retainAutoreleaseReturnValue";
5578 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5579 llvm::Value *Address) const override {
5580 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
5582 // 0-15 are the 16 integer registers.
5583 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 15);
5587 unsigned getSizeOfUnwindException() const override {
5588 if (getABIInfo().isEABI()) return 88;
5589 return TargetCodeGenInfo::getSizeOfUnwindException();
5592 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5593 CodeGen::CodeGenModule &CGM) const override {
5594 if (GV->isDeclaration())
5596 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
5600 const ARMInterruptAttr *Attr = FD->getAttr<ARMInterruptAttr>();
5605 switch (Attr->getInterrupt()) {
5606 case ARMInterruptAttr::Generic: Kind = ""; break;
5607 case ARMInterruptAttr::IRQ: Kind = "IRQ"; break;
5608 case ARMInterruptAttr::FIQ: Kind = "FIQ"; break;
5609 case ARMInterruptAttr::SWI: Kind = "SWI"; break;
5610 case ARMInterruptAttr::ABORT: Kind = "ABORT"; break;
5611 case ARMInterruptAttr::UNDEF: Kind = "UNDEF"; break;
5614 llvm::Function *Fn = cast<llvm::Function>(GV);
5616 Fn->addFnAttr("interrupt", Kind);
5618 ARMABIInfo::ABIKind ABI = cast<ARMABIInfo>(getABIInfo()).getABIKind();
5619 if (ABI == ARMABIInfo::APCS)
5622 // AAPCS guarantees that sp will be 8-byte aligned on any public interface,
5623 // however this is not necessarily true on taking any interrupt. Instruct
5624 // the backend to perform a realignment as part of the function prologue.
5625 llvm::AttrBuilder B;
5626 B.addStackAlignmentAttr(8);
5627 Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
5631 class WindowsARMTargetCodeGenInfo : public ARMTargetCodeGenInfo {
5633 WindowsARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5634 : ARMTargetCodeGenInfo(CGT, K) {}
5636 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5637 CodeGen::CodeGenModule &CGM) const override;
5639 void getDependentLibraryOption(llvm::StringRef Lib,
5640 llvm::SmallString<24> &Opt) const override {
5641 Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
5644 void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
5645 llvm::SmallString<32> &Opt) const override {
5646 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
5650 void WindowsARMTargetCodeGenInfo::setTargetAttributes(
5651 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
5652 ARMTargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
5653 if (GV->isDeclaration())
5655 addStackProbeTargetAttributes(D, GV, CGM);
5659 void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const {
5660 if (!::classifyReturnType(getCXXABI(), FI, *this))
5661 FI.getReturnInfo() =
5662 classifyReturnType(FI.getReturnType(), FI.isVariadic());
5664 for (auto &I : FI.arguments())
5665 I.info = classifyArgumentType(I.type, FI.isVariadic());
5667 // Always honor user-specified calling convention.
5668 if (FI.getCallingConvention() != llvm::CallingConv::C)
5671 llvm::CallingConv::ID cc = getRuntimeCC();
5672 if (cc != llvm::CallingConv::C)
5673 FI.setEffectiveCallingConvention(cc);
5676 /// Return the default calling convention that LLVM will use.
5677 llvm::CallingConv::ID ARMABIInfo::getLLVMDefaultCC() const {
5678 // The default calling convention that LLVM will infer.
5679 if (isEABIHF() || getTarget().getTriple().isWatchABI())
5680 return llvm::CallingConv::ARM_AAPCS_VFP;
5682 return llvm::CallingConv::ARM_AAPCS;
5684 return llvm::CallingConv::ARM_APCS;
5687 /// Return the calling convention that our ABI would like us to use
5688 /// as the C calling convention.
5689 llvm::CallingConv::ID ARMABIInfo::getABIDefaultCC() const {
5690 switch (getABIKind()) {
5691 case APCS: return llvm::CallingConv::ARM_APCS;
5692 case AAPCS: return llvm::CallingConv::ARM_AAPCS;
5693 case AAPCS_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
5694 case AAPCS16_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
5696 llvm_unreachable("bad ABI kind");
5699 void ARMABIInfo::setCCs() {
5700 assert(getRuntimeCC() == llvm::CallingConv::C);
5702 // Don't muddy up the IR with a ton of explicit annotations if
5703 // they'd just match what LLVM will infer from the triple.
5704 llvm::CallingConv::ID abiCC = getABIDefaultCC();
5705 if (abiCC != getLLVMDefaultCC())
5709 ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty,
5710 bool isVariadic) const {
5711 // 6.1.2.1 The following argument types are VFP CPRCs:
5712 // A single-precision floating-point type (including promoted
5713 // half-precision types); A double-precision floating-point type;
5714 // A 64-bit or 128-bit containerized vector type; Homogeneous Aggregate
5715 // with a Base Type of a single- or double-precision floating-point type,
5716 // 64-bit containerized vectors or 128-bit containerized vectors with one
5717 // to four Elements.
5718 bool IsEffectivelyAAPCS_VFP = getABIKind() == AAPCS_VFP && !isVariadic;
5720 Ty = useFirstFieldIfTransparentUnion(Ty);
5722 // Handle illegal vector types here.
5723 if (isIllegalVectorType(Ty)) {
5724 uint64_t Size = getContext().getTypeSize(Ty);
5726 llvm::Type *ResType =
5727 llvm::Type::getInt32Ty(getVMContext());
5728 return ABIArgInfo::getDirect(ResType);
5731 llvm::Type *ResType = llvm::VectorType::get(
5732 llvm::Type::getInt32Ty(getVMContext()), 2);
5733 return ABIArgInfo::getDirect(ResType);
5736 llvm::Type *ResType = llvm::VectorType::get(
5737 llvm::Type::getInt32Ty(getVMContext()), 4);
5738 return ABIArgInfo::getDirect(ResType);
5740 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5743 // _Float16 and __fp16 get passed as if it were an int or float, but with
5744 // the top 16 bits unspecified. This is not done for OpenCL as it handles the
5745 // half type natively, and does not need to interwork with AAPCS code.
5746 if ((Ty->isFloat16Type() || Ty->isHalfType()) &&
5747 !getContext().getLangOpts().NativeHalfArgsAndReturns) {
5748 llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
5749 llvm::Type::getFloatTy(getVMContext()) :
5750 llvm::Type::getInt32Ty(getVMContext());
5751 return ABIArgInfo::getDirect(ResType);
5754 if (!isAggregateTypeForABI(Ty)) {
5755 // Treat an enum type as its underlying type.
5756 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
5757 Ty = EnumTy->getDecl()->getIntegerType();
5760 return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty)
5761 : ABIArgInfo::getDirect());
5764 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
5765 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
5768 // Ignore empty records.
5769 if (isEmptyRecord(getContext(), Ty, true))
5770 return ABIArgInfo::getIgnore();
5772 if (IsEffectivelyAAPCS_VFP) {
5773 // Homogeneous Aggregates need to be expanded when we can fit the aggregate
5774 // into VFP registers.
5775 const Type *Base = nullptr;
5776 uint64_t Members = 0;
5777 if (isHomogeneousAggregate(Ty, Base, Members)) {
5778 assert(Base && "Base class should be set for homogeneous aggregate");
5779 // Base can be a floating-point or a vector.
5780 return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
5782 } else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) {
5783 // WatchOS does have homogeneous aggregates. Note that we intentionally use
5784 // this convention even for a variadic function: the backend will use GPRs
5786 const Type *Base = nullptr;
5787 uint64_t Members = 0;
5788 if (isHomogeneousAggregate(Ty, Base, Members)) {
5789 assert(Base && Members <= 4 && "unexpected homogeneous aggregate");
5791 llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members);
5792 return ABIArgInfo::getDirect(Ty, 0, nullptr, false);
5796 if (getABIKind() == ARMABIInfo::AAPCS16_VFP &&
5797 getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(16)) {
5798 // WatchOS is adopting the 64-bit AAPCS rule on composite types: if they're
5799 // bigger than 128-bits, they get placed in space allocated by the caller,
5800 // and a pointer is passed.
5801 return ABIArgInfo::getIndirect(
5802 CharUnits::fromQuantity(getContext().getTypeAlign(Ty) / 8), false);
5805 // Support byval for ARM.
5806 // The ABI alignment for APCS is 4-byte and for AAPCS at least 4-byte and at
5807 // most 8-byte. We realign the indirect argument if type alignment is bigger
5808 // than ABI alignment.
5809 uint64_t ABIAlign = 4;
5811 if (getABIKind() == ARMABIInfo::AAPCS_VFP ||
5812 getABIKind() == ARMABIInfo::AAPCS) {
5813 TyAlign = getContext().getTypeUnadjustedAlignInChars(Ty).getQuantity();
5814 ABIAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8);
5816 TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();
5818 if (getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(64)) {
5819 assert(getABIKind() != ARMABIInfo::AAPCS16_VFP && "unexpected byval");
5820 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(ABIAlign),
5822 /*Realign=*/TyAlign > ABIAlign);
5825 // On RenderScript, coerce Aggregates <= 64 bytes to an integer array of
5826 // same size and alignment.
5827 if (getTarget().isRenderScriptTarget()) {
5828 return coerceToIntArray(Ty, getContext(), getVMContext());
5831 // Otherwise, pass by coercing to a structure of the appropriate size.
5834 // FIXME: Try to match the types of the arguments more accurately where
5837 ElemTy = llvm::Type::getInt32Ty(getVMContext());
5838 SizeRegs = (getContext().getTypeSize(Ty) + 31) / 32;
5840 ElemTy = llvm::Type::getInt64Ty(getVMContext());
5841 SizeRegs = (getContext().getTypeSize(Ty) + 63) / 64;
5844 return ABIArgInfo::getDirect(llvm::ArrayType::get(ElemTy, SizeRegs));
5847 static bool isIntegerLikeType(QualType Ty, ASTContext &Context,
5848 llvm::LLVMContext &VMContext) {
5849 // APCS, C Language Calling Conventions, Non-Simple Return Values: A structure
5850 // is called integer-like if its size is less than or equal to one word, and
5851 // the offset of each of its addressable sub-fields is zero.
5853 uint64_t Size = Context.getTypeSize(Ty);
5855 // Check that the type fits in a word.
5859 // FIXME: Handle vector types!
5860 if (Ty->isVectorType())
5863 // Float types are never treated as "integer like".
5864 if (Ty->isRealFloatingType())
5867 // If this is a builtin or pointer type then it is ok.
5868 if (Ty->getAs<BuiltinType>() || Ty->isPointerType())
5871 // Small complex integer types are "integer like".
5872 if (const ComplexType *CT = Ty->getAs<ComplexType>())
5873 return isIntegerLikeType(CT->getElementType(), Context, VMContext);
5875 // Single element and zero sized arrays should be allowed, by the definition
5876 // above, but they are not.
5878 // Otherwise, it must be a record type.
5879 const RecordType *RT = Ty->getAs<RecordType>();
5880 if (!RT) return false;
5882 // Ignore records with flexible arrays.
5883 const RecordDecl *RD = RT->getDecl();
5884 if (RD->hasFlexibleArrayMember())
5887 // Check that all sub-fields are at offset 0, and are themselves "integer
5889 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
5891 bool HadField = false;
5893 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
5894 i != e; ++i, ++idx) {
5895 const FieldDecl *FD = *i;
5897 // Bit-fields are not addressable, we only need to verify they are "integer
5898 // like". We still have to disallow a subsequent non-bitfield, for example:
5899 // struct { int : 0; int x }
5900 // is non-integer like according to gcc.
5901 if (FD->isBitField()) {
5905 if (!isIntegerLikeType(FD->getType(), Context, VMContext))
5911 // Check if this field is at offset 0.
5912 if (Layout.getFieldOffset(idx) != 0)
5915 if (!isIntegerLikeType(FD->getType(), Context, VMContext))
5918 // Only allow at most one field in a structure. This doesn't match the
5919 // wording above, but follows gcc in situations with a field following an
5921 if (!RD->isUnion()) {
5932 ABIArgInfo ARMABIInfo::classifyReturnType(QualType RetTy,
5933 bool isVariadic) const {
5934 bool IsEffectivelyAAPCS_VFP =
5935 (getABIKind() == AAPCS_VFP || getABIKind() == AAPCS16_VFP) && !isVariadic;
5937 if (RetTy->isVoidType())
5938 return ABIArgInfo::getIgnore();
5940 // Large vector types should be returned via memory.
5941 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128) {
5942 return getNaturalAlignIndirect(RetTy);
5945 // _Float16 and __fp16 get returned as if it were an int or float, but with
5946 // the top 16 bits unspecified. This is not done for OpenCL as it handles the
5947 // half type natively, and does not need to interwork with AAPCS code.
5948 if ((RetTy->isFloat16Type() || RetTy->isHalfType()) &&
5949 !getContext().getLangOpts().NativeHalfArgsAndReturns) {
5950 llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
5951 llvm::Type::getFloatTy(getVMContext()) :
5952 llvm::Type::getInt32Ty(getVMContext());
5953 return ABIArgInfo::getDirect(ResType);
5956 if (!isAggregateTypeForABI(RetTy)) {
5957 // Treat an enum type as its underlying type.
5958 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5959 RetTy = EnumTy->getDecl()->getIntegerType();
5961 return RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
5962 : ABIArgInfo::getDirect();
5965 // Are we following APCS?
5966 if (getABIKind() == APCS) {
5967 if (isEmptyRecord(getContext(), RetTy, false))
5968 return ABIArgInfo::getIgnore();
5970 // Complex types are all returned as packed integers.
5972 // FIXME: Consider using 2 x vector types if the back end handles them
5974 if (RetTy->isAnyComplexType())
5975 return ABIArgInfo::getDirect(llvm::IntegerType::get(
5976 getVMContext(), getContext().getTypeSize(RetTy)));
5978 // Integer like structures are returned in r0.
5979 if (isIntegerLikeType(RetTy, getContext(), getVMContext())) {
5980 // Return in the smallest viable integer type.
5981 uint64_t Size = getContext().getTypeSize(RetTy);
5983 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
5985 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
5986 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
5989 // Otherwise return in memory.
5990 return getNaturalAlignIndirect(RetTy);
5993 // Otherwise this is an AAPCS variant.
5995 if (isEmptyRecord(getContext(), RetTy, true))
5996 return ABIArgInfo::getIgnore();
5998 // Check for homogeneous aggregates with AAPCS-VFP.
5999 if (IsEffectivelyAAPCS_VFP) {
6000 const Type *Base = nullptr;
6001 uint64_t Members = 0;
6002 if (isHomogeneousAggregate(RetTy, Base, Members)) {
6003 assert(Base && "Base class should be set for homogeneous aggregate");
6004 // Homogeneous Aggregates are returned directly.
6005 return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
6009 // Aggregates <= 4 bytes are returned in r0; other aggregates
6010 // are returned indirectly.
6011 uint64_t Size = getContext().getTypeSize(RetTy);
6013 // On RenderScript, coerce Aggregates <= 4 bytes to an integer array of
6014 // same size and alignment.
6015 if (getTarget().isRenderScriptTarget()) {
6016 return coerceToIntArray(RetTy, getContext(), getVMContext());
6018 if (getDataLayout().isBigEndian())
6019 // Return in 32 bit integer integer type (as if loaded by LDR, AAPCS 5.4)
6020 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6022 // Return in the smallest viable integer type.
6024 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
6026 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
6027 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6028 } else if (Size <= 128 && getABIKind() == AAPCS16_VFP) {
6029 llvm::Type *Int32Ty = llvm::Type::getInt32Ty(getVMContext());
6030 llvm::Type *CoerceTy =
6031 llvm::ArrayType::get(Int32Ty, llvm::alignTo(Size, 32) / 32);
6032 return ABIArgInfo::getDirect(CoerceTy);
6035 return getNaturalAlignIndirect(RetTy);
6038 /// isIllegalVector - check whether Ty is an illegal vector type.
6039 bool ARMABIInfo::isIllegalVectorType(QualType Ty) const {
6040 if (const VectorType *VT = Ty->getAs<VectorType> ()) {
6042 // Android shipped using Clang 3.1, which supported a slightly different
6043 // vector ABI. The primary differences were that 3-element vector types
6044 // were legal, and so were sub 32-bit vectors (i.e. <2 x i8>). This path
6045 // accepts that legacy behavior for Android only.
6046 // Check whether VT is legal.
6047 unsigned NumElements = VT->getNumElements();
6048 // NumElements should be power of 2 or equal to 3.
6049 if (!llvm::isPowerOf2_32(NumElements) && NumElements != 3)
6052 // Check whether VT is legal.
6053 unsigned NumElements = VT->getNumElements();
6054 uint64_t Size = getContext().getTypeSize(VT);
6055 // NumElements should be power of 2.
6056 if (!llvm::isPowerOf2_32(NumElements))
6058 // Size should be greater than 32 bits.
6065 bool ARMABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize,
6067 unsigned numElts) const {
6068 if (!llvm::isPowerOf2_32(numElts))
6070 unsigned size = getDataLayout().getTypeStoreSizeInBits(eltTy);
6073 if (vectorSize.getQuantity() != 8 &&
6074 (vectorSize.getQuantity() != 16 || numElts == 1))
6079 bool ARMABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
6080 // Homogeneous aggregates for AAPCS-VFP must have base types of float,
6081 // double, or 64-bit or 128-bit vectors.
6082 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
6083 if (BT->getKind() == BuiltinType::Float ||
6084 BT->getKind() == BuiltinType::Double ||
6085 BT->getKind() == BuiltinType::LongDouble)
6087 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
6088 unsigned VecSize = getContext().getTypeSize(VT);
6089 if (VecSize == 64 || VecSize == 128)
6095 bool ARMABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
6096 uint64_t Members) const {
6097 return Members <= 4;
6100 Address ARMABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6101 QualType Ty) const {
6102 CharUnits SlotSize = CharUnits::fromQuantity(4);
6104 // Empty records are ignored for parameter passing purposes.
6105 if (isEmptyRecord(getContext(), Ty, true)) {
6106 Address Addr(CGF.Builder.CreateLoad(VAListAddr), SlotSize);
6107 Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
6111 auto TyInfo = getContext().getTypeInfoInChars(Ty);
6112 CharUnits TyAlignForABI = TyInfo.second;
6114 // Use indirect if size of the illegal vector is bigger than 16 bytes.
6115 bool IsIndirect = false;
6116 const Type *Base = nullptr;
6117 uint64_t Members = 0;
6118 if (TyInfo.first > CharUnits::fromQuantity(16) && isIllegalVectorType(Ty)) {
6121 // ARMv7k passes structs bigger than 16 bytes indirectly, in space
6122 // allocated by the caller.
6123 } else if (TyInfo.first > CharUnits::fromQuantity(16) &&
6124 getABIKind() == ARMABIInfo::AAPCS16_VFP &&
6125 !isHomogeneousAggregate(Ty, Base, Members)) {
6128 // Otherwise, bound the type's ABI alignment.
6129 // The ABI alignment for 64-bit or 128-bit vectors is 8 for AAPCS and 4 for
6130 // APCS. For AAPCS, the ABI alignment is at least 4-byte and at most 8-byte.
6131 // Our callers should be prepared to handle an under-aligned address.
6132 } else if (getABIKind() == ARMABIInfo::AAPCS_VFP ||
6133 getABIKind() == ARMABIInfo::AAPCS) {
6134 TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
6135 TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(8));
6136 } else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) {
6137 // ARMv7k allows type alignment up to 16 bytes.
6138 TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
6139 TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(16));
6141 TyAlignForABI = CharUnits::fromQuantity(4);
6143 TyInfo.second = TyAlignForABI;
6145 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, TyInfo,
6146 SlotSize, /*AllowHigherAlign*/ true);
6149 //===----------------------------------------------------------------------===//
6150 // NVPTX ABI Implementation
6151 //===----------------------------------------------------------------------===//
6155 class NVPTXABIInfo : public ABIInfo {
6157 NVPTXABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
6159 ABIArgInfo classifyReturnType(QualType RetTy) const;
6160 ABIArgInfo classifyArgumentType(QualType Ty) const;
6162 void computeInfo(CGFunctionInfo &FI) const override;
6163 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6164 QualType Ty) const override;
6167 class NVPTXTargetCodeGenInfo : public TargetCodeGenInfo {
6169 NVPTXTargetCodeGenInfo(CodeGenTypes &CGT)
6170 : TargetCodeGenInfo(new NVPTXABIInfo(CGT)) {}
6172 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6173 CodeGen::CodeGenModule &M) const override;
6174 bool shouldEmitStaticExternCAliases() const override;
6177 // Adds a NamedMDNode with F, Name, and Operand as operands, and adds the
6178 // resulting MDNode to the nvvm.annotations MDNode.
6179 static void addNVVMMetadata(llvm::Function *F, StringRef Name, int Operand);
6182 ABIArgInfo NVPTXABIInfo::classifyReturnType(QualType RetTy) const {
6183 if (RetTy->isVoidType())
6184 return ABIArgInfo::getIgnore();
6186 // note: this is different from default ABI
6187 if (!RetTy->isScalarType())
6188 return ABIArgInfo::getDirect();
6190 // Treat an enum type as its underlying type.
6191 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
6192 RetTy = EnumTy->getDecl()->getIntegerType();
6194 return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
6195 : ABIArgInfo::getDirect());
6198 ABIArgInfo NVPTXABIInfo::classifyArgumentType(QualType Ty) const {
6199 // Treat an enum type as its underlying type.
6200 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6201 Ty = EnumTy->getDecl()->getIntegerType();
6203 // Return aggregates type as indirect by value
6204 if (isAggregateTypeForABI(Ty))
6205 return getNaturalAlignIndirect(Ty, /* byval */ true);
6207 return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty)
6208 : ABIArgInfo::getDirect());
6211 void NVPTXABIInfo::computeInfo(CGFunctionInfo &FI) const {
6212 if (!getCXXABI().classifyReturnType(FI))
6213 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
6214 for (auto &I : FI.arguments())
6215 I.info = classifyArgumentType(I.type);
6217 // Always honor user-specified calling convention.
6218 if (FI.getCallingConvention() != llvm::CallingConv::C)
6221 FI.setEffectiveCallingConvention(getRuntimeCC());
6224 Address NVPTXABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6225 QualType Ty) const {
6226 llvm_unreachable("NVPTX does not support varargs");
6229 void NVPTXTargetCodeGenInfo::setTargetAttributes(
6230 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
6231 if (GV->isDeclaration())
6233 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
6236 llvm::Function *F = cast<llvm::Function>(GV);
6238 // Perform special handling in OpenCL mode
6239 if (M.getLangOpts().OpenCL) {
6240 // Use OpenCL function attributes to check for kernel functions
6241 // By default, all functions are device functions
6242 if (FD->hasAttr<OpenCLKernelAttr>()) {
6243 // OpenCL __kernel functions get kernel metadata
6244 // Create !{<func-ref>, metadata !"kernel", i32 1} node
6245 addNVVMMetadata(F, "kernel", 1);
6246 // And kernel functions are not subject to inlining
6247 F->addFnAttr(llvm::Attribute::NoInline);
6251 // Perform special handling in CUDA mode.
6252 if (M.getLangOpts().CUDA) {
6253 // CUDA __global__ functions get a kernel metadata entry. Since
6254 // __global__ functions cannot be called from the device, we do not
6255 // need to set the noinline attribute.
6256 if (FD->hasAttr<CUDAGlobalAttr>()) {
6257 // Create !{<func-ref>, metadata !"kernel", i32 1} node
6258 addNVVMMetadata(F, "kernel", 1);
6260 if (CUDALaunchBoundsAttr *Attr = FD->getAttr<CUDALaunchBoundsAttr>()) {
6261 // Create !{<func-ref>, metadata !"maxntidx", i32 <val>} node
6262 llvm::APSInt MaxThreads(32);
6263 MaxThreads = Attr->getMaxThreads()->EvaluateKnownConstInt(M.getContext());
6265 addNVVMMetadata(F, "maxntidx", MaxThreads.getExtValue());
6267 // min blocks is an optional argument for CUDALaunchBoundsAttr. If it was
6268 // not specified in __launch_bounds__ or if the user specified a 0 value,
6269 // we don't have to add a PTX directive.
6270 if (Attr->getMinBlocks()) {
6271 llvm::APSInt MinBlocks(32);
6272 MinBlocks = Attr->getMinBlocks()->EvaluateKnownConstInt(M.getContext());
6274 // Create !{<func-ref>, metadata !"minctasm", i32 <val>} node
6275 addNVVMMetadata(F, "minctasm", MinBlocks.getExtValue());
6281 void NVPTXTargetCodeGenInfo::addNVVMMetadata(llvm::Function *F, StringRef Name,
6283 llvm::Module *M = F->getParent();
6284 llvm::LLVMContext &Ctx = M->getContext();
6286 // Get "nvvm.annotations" metadata node
6287 llvm::NamedMDNode *MD = M->getOrInsertNamedMetadata("nvvm.annotations");
6289 llvm::Metadata *MDVals[] = {
6290 llvm::ConstantAsMetadata::get(F), llvm::MDString::get(Ctx, Name),
6291 llvm::ConstantAsMetadata::get(
6292 llvm::ConstantInt::get(llvm::Type::getInt32Ty(Ctx), Operand))};
6293 // Append metadata to nvvm.annotations
6294 MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
6297 bool NVPTXTargetCodeGenInfo::shouldEmitStaticExternCAliases() const {
6302 //===----------------------------------------------------------------------===//
6303 // SystemZ ABI Implementation
6304 //===----------------------------------------------------------------------===//
6308 class SystemZABIInfo : public SwiftABIInfo {
6312 SystemZABIInfo(CodeGenTypes &CGT, bool HV)
6313 : SwiftABIInfo(CGT), HasVector(HV) {}
6315 bool isPromotableIntegerType(QualType Ty) const;
6316 bool isCompoundType(QualType Ty) const;
6317 bool isVectorArgumentType(QualType Ty) const;
6318 bool isFPArgumentType(QualType Ty) const;
6319 QualType GetSingleElementType(QualType Ty) const;
6321 ABIArgInfo classifyReturnType(QualType RetTy) const;
6322 ABIArgInfo classifyArgumentType(QualType ArgTy) const;
6324 void computeInfo(CGFunctionInfo &FI) const override {
6325 if (!getCXXABI().classifyReturnType(FI))
6326 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
6327 for (auto &I : FI.arguments())
6328 I.info = classifyArgumentType(I.type);
6331 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6332 QualType Ty) const override;
6334 bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
6335 bool asReturnValue) const override {
6336 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
6338 bool isSwiftErrorInRegister() const override {
6343 class SystemZTargetCodeGenInfo : public TargetCodeGenInfo {
6345 SystemZTargetCodeGenInfo(CodeGenTypes &CGT, bool HasVector)
6346 : TargetCodeGenInfo(new SystemZABIInfo(CGT, HasVector)) {}
6351 bool SystemZABIInfo::isPromotableIntegerType(QualType Ty) const {
6352 // Treat an enum type as its underlying type.
6353 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6354 Ty = EnumTy->getDecl()->getIntegerType();
6356 // Promotable integer types are required to be promoted by the ABI.
6357 if (Ty->isPromotableIntegerType())
6360 // 32-bit values must also be promoted.
6361 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
6362 switch (BT->getKind()) {
6363 case BuiltinType::Int:
6364 case BuiltinType::UInt:
6372 bool SystemZABIInfo::isCompoundType(QualType Ty) const {
6373 return (Ty->isAnyComplexType() ||
6374 Ty->isVectorType() ||
6375 isAggregateTypeForABI(Ty));
6378 bool SystemZABIInfo::isVectorArgumentType(QualType Ty) const {
6379 return (HasVector &&
6380 Ty->isVectorType() &&
6381 getContext().getTypeSize(Ty) <= 128);
6384 bool SystemZABIInfo::isFPArgumentType(QualType Ty) const {
6385 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
6386 switch (BT->getKind()) {
6387 case BuiltinType::Float:
6388 case BuiltinType::Double:
6397 QualType SystemZABIInfo::GetSingleElementType(QualType Ty) const {
6398 if (const RecordType *RT = Ty->getAsStructureType()) {
6399 const RecordDecl *RD = RT->getDecl();
6402 // If this is a C++ record, check the bases first.
6403 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
6404 for (const auto &I : CXXRD->bases()) {
6405 QualType Base = I.getType();
6407 // Empty bases don't affect things either way.
6408 if (isEmptyRecord(getContext(), Base, true))
6411 if (!Found.isNull())
6413 Found = GetSingleElementType(Base);
6416 // Check the fields.
6417 for (const auto *FD : RD->fields()) {
6418 // For compatibility with GCC, ignore empty bitfields in C++ mode.
6419 // Unlike isSingleElementStruct(), empty structure and array fields
6420 // do count. So do anonymous bitfields that aren't zero-sized.
6421 if (getContext().getLangOpts().CPlusPlus &&
6422 FD->isZeroLengthBitField(getContext()))
6425 // Unlike isSingleElementStruct(), arrays do not count.
6426 // Nested structures still do though.
6427 if (!Found.isNull())
6429 Found = GetSingleElementType(FD->getType());
6432 // Unlike isSingleElementStruct(), trailing padding is allowed.
6433 // An 8-byte aligned struct s { float f; } is passed as a double.
6434 if (!Found.isNull())
6441 Address SystemZABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6442 QualType Ty) const {
6443 // Assume that va_list type is correct; should be pointer to LLVM type:
6447 // i8 *__overflow_arg_area;
6448 // i8 *__reg_save_area;
6451 // Every non-vector argument occupies 8 bytes and is passed by preference
6452 // in either GPRs or FPRs. Vector arguments occupy 8 or 16 bytes and are
6453 // always passed on the stack.
6454 Ty = getContext().getCanonicalType(Ty);
6455 auto TyInfo = getContext().getTypeInfoInChars(Ty);
6456 llvm::Type *ArgTy = CGF.ConvertTypeForMem(Ty);
6457 llvm::Type *DirectTy = ArgTy;
6458 ABIArgInfo AI = classifyArgumentType(Ty);
6459 bool IsIndirect = AI.isIndirect();
6460 bool InFPRs = false;
6461 bool IsVector = false;
6462 CharUnits UnpaddedSize;
6463 CharUnits DirectAlign;
6465 DirectTy = llvm::PointerType::getUnqual(DirectTy);
6466 UnpaddedSize = DirectAlign = CharUnits::fromQuantity(8);
6468 if (AI.getCoerceToType())
6469 ArgTy = AI.getCoerceToType();
6470 InFPRs = ArgTy->isFloatTy() || ArgTy->isDoubleTy();
6471 IsVector = ArgTy->isVectorTy();
6472 UnpaddedSize = TyInfo.first;
6473 DirectAlign = TyInfo.second;
6475 CharUnits PaddedSize = CharUnits::fromQuantity(8);
6476 if (IsVector && UnpaddedSize > PaddedSize)
6477 PaddedSize = CharUnits::fromQuantity(16);
6478 assert((UnpaddedSize <= PaddedSize) && "Invalid argument size.");
6480 CharUnits Padding = (PaddedSize - UnpaddedSize);
6482 llvm::Type *IndexTy = CGF.Int64Ty;
6483 llvm::Value *PaddedSizeV =
6484 llvm::ConstantInt::get(IndexTy, PaddedSize.getQuantity());
6487 // Work out the address of a vector argument on the stack.
6488 // Vector arguments are always passed in the high bits of a
6489 // single (8 byte) or double (16 byte) stack slot.
6490 Address OverflowArgAreaPtr =
6491 CGF.Builder.CreateStructGEP(VAListAddr, 2, CharUnits::fromQuantity(16),
6492 "overflow_arg_area_ptr");
6493 Address OverflowArgArea =
6494 Address(CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"),
6497 CGF.Builder.CreateElementBitCast(OverflowArgArea, DirectTy, "mem_addr");
6499 // Update overflow_arg_area_ptr pointer
6500 llvm::Value *NewOverflowArgArea =
6501 CGF.Builder.CreateGEP(OverflowArgArea.getPointer(), PaddedSizeV,
6502 "overflow_arg_area");
6503 CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
6508 assert(PaddedSize.getQuantity() == 8);
6510 unsigned MaxRegs, RegCountField, RegSaveIndex;
6511 CharUnits RegPadding;
6513 MaxRegs = 4; // Maximum of 4 FPR arguments
6514 RegCountField = 1; // __fpr
6515 RegSaveIndex = 16; // save offset for f0
6516 RegPadding = CharUnits(); // floats are passed in the high bits of an FPR
6518 MaxRegs = 5; // Maximum of 5 GPR arguments
6519 RegCountField = 0; // __gpr
6520 RegSaveIndex = 2; // save offset for r2
6521 RegPadding = Padding; // values are passed in the low bits of a GPR
6524 Address RegCountPtr = CGF.Builder.CreateStructGEP(
6525 VAListAddr, RegCountField, RegCountField * CharUnits::fromQuantity(8),
6527 llvm::Value *RegCount = CGF.Builder.CreateLoad(RegCountPtr, "reg_count");
6528 llvm::Value *MaxRegsV = llvm::ConstantInt::get(IndexTy, MaxRegs);
6529 llvm::Value *InRegs = CGF.Builder.CreateICmpULT(RegCount, MaxRegsV,
6532 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
6533 llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
6534 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
6535 CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
6537 // Emit code to load the value if it was passed in registers.
6538 CGF.EmitBlock(InRegBlock);
6540 // Work out the address of an argument register.
6541 llvm::Value *ScaledRegCount =
6542 CGF.Builder.CreateMul(RegCount, PaddedSizeV, "scaled_reg_count");
6543 llvm::Value *RegBase =
6544 llvm::ConstantInt::get(IndexTy, RegSaveIndex * PaddedSize.getQuantity()
6545 + RegPadding.getQuantity());
6546 llvm::Value *RegOffset =
6547 CGF.Builder.CreateAdd(ScaledRegCount, RegBase, "reg_offset");
6548 Address RegSaveAreaPtr =
6549 CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(24),
6550 "reg_save_area_ptr");
6551 llvm::Value *RegSaveArea =
6552 CGF.Builder.CreateLoad(RegSaveAreaPtr, "reg_save_area");
6553 Address RawRegAddr(CGF.Builder.CreateGEP(RegSaveArea, RegOffset,
6557 CGF.Builder.CreateElementBitCast(RawRegAddr, DirectTy, "reg_addr");
6559 // Update the register count
6560 llvm::Value *One = llvm::ConstantInt::get(IndexTy, 1);
6561 llvm::Value *NewRegCount =
6562 CGF.Builder.CreateAdd(RegCount, One, "reg_count");
6563 CGF.Builder.CreateStore(NewRegCount, RegCountPtr);
6564 CGF.EmitBranch(ContBlock);
6566 // Emit code to load the value if it was passed in memory.
6567 CGF.EmitBlock(InMemBlock);
6569 // Work out the address of a stack argument.
6570 Address OverflowArgAreaPtr = CGF.Builder.CreateStructGEP(
6571 VAListAddr, 2, CharUnits::fromQuantity(16), "overflow_arg_area_ptr");
6572 Address OverflowArgArea =
6573 Address(CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"),
6575 Address RawMemAddr =
6576 CGF.Builder.CreateConstByteGEP(OverflowArgArea, Padding, "raw_mem_addr");
6578 CGF.Builder.CreateElementBitCast(RawMemAddr, DirectTy, "mem_addr");
6580 // Update overflow_arg_area_ptr pointer
6581 llvm::Value *NewOverflowArgArea =
6582 CGF.Builder.CreateGEP(OverflowArgArea.getPointer(), PaddedSizeV,
6583 "overflow_arg_area");
6584 CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
6585 CGF.EmitBranch(ContBlock);
6587 // Return the appropriate result.
6588 CGF.EmitBlock(ContBlock);
6589 Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
6590 MemAddr, InMemBlock, "va_arg.addr");
6593 ResAddr = Address(CGF.Builder.CreateLoad(ResAddr, "indirect_arg"),
6599 ABIArgInfo SystemZABIInfo::classifyReturnType(QualType RetTy) const {
6600 if (RetTy->isVoidType())
6601 return ABIArgInfo::getIgnore();
6602 if (isVectorArgumentType(RetTy))
6603 return ABIArgInfo::getDirect();
6604 if (isCompoundType(RetTy) || getContext().getTypeSize(RetTy) > 64)
6605 return getNaturalAlignIndirect(RetTy);
6606 return (isPromotableIntegerType(RetTy) ? ABIArgInfo::getExtend(RetTy)
6607 : ABIArgInfo::getDirect());
6610 ABIArgInfo SystemZABIInfo::classifyArgumentType(QualType Ty) const {
6611 // Handle the generic C++ ABI.
6612 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
6613 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
6615 // Integers and enums are extended to full register width.
6616 if (isPromotableIntegerType(Ty))
6617 return ABIArgInfo::getExtend(Ty);
6619 // Handle vector types and vector-like structure types. Note that
6620 // as opposed to float-like structure types, we do not allow any
6621 // padding for vector-like structures, so verify the sizes match.
6622 uint64_t Size = getContext().getTypeSize(Ty);
6623 QualType SingleElementTy = GetSingleElementType(Ty);
6624 if (isVectorArgumentType(SingleElementTy) &&
6625 getContext().getTypeSize(SingleElementTy) == Size)
6626 return ABIArgInfo::getDirect(CGT.ConvertType(SingleElementTy));
6628 // Values that are not 1, 2, 4 or 8 bytes in size are passed indirectly.
6629 if (Size != 8 && Size != 16 && Size != 32 && Size != 64)
6630 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6632 // Handle small structures.
6633 if (const RecordType *RT = Ty->getAs<RecordType>()) {
6634 // Structures with flexible arrays have variable length, so really
6635 // fail the size test above.
6636 const RecordDecl *RD = RT->getDecl();
6637 if (RD->hasFlexibleArrayMember())
6638 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6640 // The structure is passed as an unextended integer, a float, or a double.
6642 if (isFPArgumentType(SingleElementTy)) {
6643 assert(Size == 32 || Size == 64);
6645 PassTy = llvm::Type::getFloatTy(getVMContext());
6647 PassTy = llvm::Type::getDoubleTy(getVMContext());
6649 PassTy = llvm::IntegerType::get(getVMContext(), Size);
6650 return ABIArgInfo::getDirect(PassTy);
6653 // Non-structure compounds are passed indirectly.
6654 if (isCompoundType(Ty))
6655 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6657 return ABIArgInfo::getDirect(nullptr);
6660 //===----------------------------------------------------------------------===//
6661 // MSP430 ABI Implementation
6662 //===----------------------------------------------------------------------===//
6666 class MSP430TargetCodeGenInfo : public TargetCodeGenInfo {
6668 MSP430TargetCodeGenInfo(CodeGenTypes &CGT)
6669 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
6670 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6671 CodeGen::CodeGenModule &M) const override;
6676 void MSP430TargetCodeGenInfo::setTargetAttributes(
6677 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
6678 if (GV->isDeclaration())
6680 if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
6681 if (const MSP430InterruptAttr *attr = FD->getAttr<MSP430InterruptAttr>()) {
6682 // Handle 'interrupt' attribute:
6683 llvm::Function *F = cast<llvm::Function>(GV);
6685 // Step 1: Set ISR calling convention.
6686 F->setCallingConv(llvm::CallingConv::MSP430_INTR);
6688 // Step 2: Add attributes goodness.
6689 F->addFnAttr(llvm::Attribute::NoInline);
6691 // Step 3: Emit ISR vector alias.
6692 unsigned Num = attr->getNumber() / 2;
6693 llvm::GlobalAlias::create(llvm::Function::ExternalLinkage,
6694 "__isr_" + Twine(Num), F);
6699 //===----------------------------------------------------------------------===//
6700 // MIPS ABI Implementation. This works for both little-endian and
6701 // big-endian variants.
6702 //===----------------------------------------------------------------------===//
6705 class MipsABIInfo : public ABIInfo {
6707 unsigned MinABIStackAlignInBytes, StackAlignInBytes;
6708 void CoerceToIntArgs(uint64_t TySize,
6709 SmallVectorImpl<llvm::Type *> &ArgList) const;
6710 llvm::Type* HandleAggregates(QualType Ty, uint64_t TySize) const;
6711 llvm::Type* returnAggregateInRegs(QualType RetTy, uint64_t Size) const;
6712 llvm::Type* getPaddingType(uint64_t Align, uint64_t Offset) const;
6714 MipsABIInfo(CodeGenTypes &CGT, bool _IsO32) :
6715 ABIInfo(CGT), IsO32(_IsO32), MinABIStackAlignInBytes(IsO32 ? 4 : 8),
6716 StackAlignInBytes(IsO32 ? 8 : 16) {}
6718 ABIArgInfo classifyReturnType(QualType RetTy) const;
6719 ABIArgInfo classifyArgumentType(QualType RetTy, uint64_t &Offset) const;
6720 void computeInfo(CGFunctionInfo &FI) const override;
6721 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6722 QualType Ty) const override;
6723 ABIArgInfo extendType(QualType Ty) const;
6726 class MIPSTargetCodeGenInfo : public TargetCodeGenInfo {
6727 unsigned SizeOfUnwindException;
6729 MIPSTargetCodeGenInfo(CodeGenTypes &CGT, bool IsO32)
6730 : TargetCodeGenInfo(new MipsABIInfo(CGT, IsO32)),
6731 SizeOfUnwindException(IsO32 ? 24 : 32) {}
6733 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
6737 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6738 CodeGen::CodeGenModule &CGM) const override {
6739 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
6741 llvm::Function *Fn = cast<llvm::Function>(GV);
6743 if (FD->hasAttr<MipsLongCallAttr>())
6744 Fn->addFnAttr("long-call");
6745 else if (FD->hasAttr<MipsShortCallAttr>())
6746 Fn->addFnAttr("short-call");
6748 // Other attributes do not have a meaning for declarations.
6749 if (GV->isDeclaration())
6752 if (FD->hasAttr<Mips16Attr>()) {
6753 Fn->addFnAttr("mips16");
6755 else if (FD->hasAttr<NoMips16Attr>()) {
6756 Fn->addFnAttr("nomips16");
6759 if (FD->hasAttr<MicroMipsAttr>())
6760 Fn->addFnAttr("micromips");
6761 else if (FD->hasAttr<NoMicroMipsAttr>())
6762 Fn->addFnAttr("nomicromips");
6764 const MipsInterruptAttr *Attr = FD->getAttr<MipsInterruptAttr>();
6769 switch (Attr->getInterrupt()) {
6770 case MipsInterruptAttr::eic: Kind = "eic"; break;
6771 case MipsInterruptAttr::sw0: Kind = "sw0"; break;
6772 case MipsInterruptAttr::sw1: Kind = "sw1"; break;
6773 case MipsInterruptAttr::hw0: Kind = "hw0"; break;
6774 case MipsInterruptAttr::hw1: Kind = "hw1"; break;
6775 case MipsInterruptAttr::hw2: Kind = "hw2"; break;
6776 case MipsInterruptAttr::hw3: Kind = "hw3"; break;
6777 case MipsInterruptAttr::hw4: Kind = "hw4"; break;
6778 case MipsInterruptAttr::hw5: Kind = "hw5"; break;
6781 Fn->addFnAttr("interrupt", Kind);
6785 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
6786 llvm::Value *Address) const override;
6788 unsigned getSizeOfUnwindException() const override {
6789 return SizeOfUnwindException;
6794 void MipsABIInfo::CoerceToIntArgs(
6795 uint64_t TySize, SmallVectorImpl<llvm::Type *> &ArgList) const {
6796 llvm::IntegerType *IntTy =
6797 llvm::IntegerType::get(getVMContext(), MinABIStackAlignInBytes * 8);
6799 // Add (TySize / MinABIStackAlignInBytes) args of IntTy.
6800 for (unsigned N = TySize / (MinABIStackAlignInBytes * 8); N; --N)
6801 ArgList.push_back(IntTy);
6803 // If necessary, add one more integer type to ArgList.
6804 unsigned R = TySize % (MinABIStackAlignInBytes * 8);
6807 ArgList.push_back(llvm::IntegerType::get(getVMContext(), R));
6810 // In N32/64, an aligned double precision floating point field is passed in
6812 llvm::Type* MipsABIInfo::HandleAggregates(QualType Ty, uint64_t TySize) const {
6813 SmallVector<llvm::Type*, 8> ArgList, IntArgList;
6816 CoerceToIntArgs(TySize, ArgList);
6817 return llvm::StructType::get(getVMContext(), ArgList);
6820 if (Ty->isComplexType())
6821 return CGT.ConvertType(Ty);
6823 const RecordType *RT = Ty->getAs<RecordType>();
6825 // Unions/vectors are passed in integer registers.
6826 if (!RT || !RT->isStructureOrClassType()) {
6827 CoerceToIntArgs(TySize, ArgList);
6828 return llvm::StructType::get(getVMContext(), ArgList);
6831 const RecordDecl *RD = RT->getDecl();
6832 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
6833 assert(!(TySize % 8) && "Size of structure must be multiple of 8.");
6835 uint64_t LastOffset = 0;
6837 llvm::IntegerType *I64 = llvm::IntegerType::get(getVMContext(), 64);
6839 // Iterate over fields in the struct/class and check if there are any aligned
6841 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
6842 i != e; ++i, ++idx) {
6843 const QualType Ty = i->getType();
6844 const BuiltinType *BT = Ty->getAs<BuiltinType>();
6846 if (!BT || BT->getKind() != BuiltinType::Double)
6849 uint64_t Offset = Layout.getFieldOffset(idx);
6850 if (Offset % 64) // Ignore doubles that are not aligned.
6853 // Add ((Offset - LastOffset) / 64) args of type i64.
6854 for (unsigned j = (Offset - LastOffset) / 64; j > 0; --j)
6855 ArgList.push_back(I64);
6858 ArgList.push_back(llvm::Type::getDoubleTy(getVMContext()));
6859 LastOffset = Offset + 64;
6862 CoerceToIntArgs(TySize - LastOffset, IntArgList);
6863 ArgList.append(IntArgList.begin(), IntArgList.end());
6865 return llvm::StructType::get(getVMContext(), ArgList);
6868 llvm::Type *MipsABIInfo::getPaddingType(uint64_t OrigOffset,
6869 uint64_t Offset) const {
6870 if (OrigOffset + MinABIStackAlignInBytes > Offset)
6873 return llvm::IntegerType::get(getVMContext(), (Offset - OrigOffset) * 8);
6877 MipsABIInfo::classifyArgumentType(QualType Ty, uint64_t &Offset) const {
6878 Ty = useFirstFieldIfTransparentUnion(Ty);
6880 uint64_t OrigOffset = Offset;
6881 uint64_t TySize = getContext().getTypeSize(Ty);
6882 uint64_t Align = getContext().getTypeAlign(Ty) / 8;
6884 Align = std::min(std::max(Align, (uint64_t)MinABIStackAlignInBytes),
6885 (uint64_t)StackAlignInBytes);
6886 unsigned CurrOffset = llvm::alignTo(Offset, Align);
6887 Offset = CurrOffset + llvm::alignTo(TySize, Align * 8) / 8;
6889 if (isAggregateTypeForABI(Ty) || Ty->isVectorType()) {
6890 // Ignore empty aggregates.
6892 return ABIArgInfo::getIgnore();
6894 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
6895 Offset = OrigOffset + MinABIStackAlignInBytes;
6896 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
6899 // If we have reached here, aggregates are passed directly by coercing to
6900 // another structure type. Padding is inserted if the offset of the
6901 // aggregate is unaligned.
6902 ABIArgInfo ArgInfo =
6903 ABIArgInfo::getDirect(HandleAggregates(Ty, TySize), 0,
6904 getPaddingType(OrigOffset, CurrOffset));
6905 ArgInfo.setInReg(true);
6909 // Treat an enum type as its underlying type.
6910 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6911 Ty = EnumTy->getDecl()->getIntegerType();
6913 // All integral types are promoted to the GPR width.
6914 if (Ty->isIntegralOrEnumerationType())
6915 return extendType(Ty);
6917 return ABIArgInfo::getDirect(
6918 nullptr, 0, IsO32 ? nullptr : getPaddingType(OrigOffset, CurrOffset));
6922 MipsABIInfo::returnAggregateInRegs(QualType RetTy, uint64_t Size) const {
6923 const RecordType *RT = RetTy->getAs<RecordType>();
6924 SmallVector<llvm::Type*, 8> RTList;
6926 if (RT && RT->isStructureOrClassType()) {
6927 const RecordDecl *RD = RT->getDecl();
6928 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
6929 unsigned FieldCnt = Layout.getFieldCount();
6931 // N32/64 returns struct/classes in floating point registers if the
6932 // following conditions are met:
6933 // 1. The size of the struct/class is no larger than 128-bit.
6934 // 2. The struct/class has one or two fields all of which are floating
6936 // 3. The offset of the first field is zero (this follows what gcc does).
6938 // Any other composite results are returned in integer registers.
6940 if (FieldCnt && (FieldCnt <= 2) && !Layout.getFieldOffset(0)) {
6941 RecordDecl::field_iterator b = RD->field_begin(), e = RD->field_end();
6942 for (; b != e; ++b) {
6943 const BuiltinType *BT = b->getType()->getAs<BuiltinType>();
6945 if (!BT || !BT->isFloatingPoint())
6948 RTList.push_back(CGT.ConvertType(b->getType()));
6952 return llvm::StructType::get(getVMContext(), RTList,
6953 RD->hasAttr<PackedAttr>());
6959 CoerceToIntArgs(Size, RTList);
6960 return llvm::StructType::get(getVMContext(), RTList);
6963 ABIArgInfo MipsABIInfo::classifyReturnType(QualType RetTy) const {
6964 uint64_t Size = getContext().getTypeSize(RetTy);
6966 if (RetTy->isVoidType())
6967 return ABIArgInfo::getIgnore();
6969 // O32 doesn't treat zero-sized structs differently from other structs.
6970 // However, N32/N64 ignores zero sized return values.
6971 if (!IsO32 && Size == 0)
6972 return ABIArgInfo::getIgnore();
6974 if (isAggregateTypeForABI(RetTy) || RetTy->isVectorType()) {
6976 if (RetTy->isAnyComplexType())
6977 return ABIArgInfo::getDirect();
6979 // O32 returns integer vectors in registers and N32/N64 returns all small
6980 // aggregates in registers.
6982 (RetTy->isVectorType() && !RetTy->hasFloatingRepresentation())) {
6983 ABIArgInfo ArgInfo =
6984 ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size));
6985 ArgInfo.setInReg(true);
6990 return getNaturalAlignIndirect(RetTy);
6993 // Treat an enum type as its underlying type.
6994 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
6995 RetTy = EnumTy->getDecl()->getIntegerType();
6997 if (RetTy->isPromotableIntegerType())
6998 return ABIArgInfo::getExtend(RetTy);
7000 if ((RetTy->isUnsignedIntegerOrEnumerationType() ||
7001 RetTy->isSignedIntegerOrEnumerationType()) && Size == 32 && !IsO32)
7002 return ABIArgInfo::getSignExtend(RetTy);
7004 return ABIArgInfo::getDirect();
7007 void MipsABIInfo::computeInfo(CGFunctionInfo &FI) const {
7008 ABIArgInfo &RetInfo = FI.getReturnInfo();
7009 if (!getCXXABI().classifyReturnType(FI))
7010 RetInfo = classifyReturnType(FI.getReturnType());
7012 // Check if a pointer to an aggregate is passed as a hidden argument.
7013 uint64_t Offset = RetInfo.isIndirect() ? MinABIStackAlignInBytes : 0;
7015 for (auto &I : FI.arguments())
7016 I.info = classifyArgumentType(I.type, Offset);
7019 Address MipsABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7020 QualType OrigTy) const {
7021 QualType Ty = OrigTy;
7023 // Integer arguments are promoted to 32-bit on O32 and 64-bit on N32/N64.
7024 // Pointers are also promoted in the same way but this only matters for N32.
7025 unsigned SlotSizeInBits = IsO32 ? 32 : 64;
7026 unsigned PtrWidth = getTarget().getPointerWidth(0);
7027 bool DidPromote = false;
7028 if ((Ty->isIntegerType() &&
7029 getContext().getIntWidth(Ty) < SlotSizeInBits) ||
7030 (Ty->isPointerType() && PtrWidth < SlotSizeInBits)) {
7032 Ty = getContext().getIntTypeForBitwidth(SlotSizeInBits,
7033 Ty->isSignedIntegerType());
7036 auto TyInfo = getContext().getTypeInfoInChars(Ty);
7038 // The alignment of things in the argument area is never larger than
7039 // StackAlignInBytes.
7041 std::min(TyInfo.second, CharUnits::fromQuantity(StackAlignInBytes));
7043 // MinABIStackAlignInBytes is the size of argument slots on the stack.
7044 CharUnits ArgSlotSize = CharUnits::fromQuantity(MinABIStackAlignInBytes);
7046 Address Addr = emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
7047 TyInfo, ArgSlotSize, /*AllowHigherAlign*/ true);
7050 // If there was a promotion, "unpromote" into a temporary.
7051 // TODO: can we just use a pointer into a subset of the original slot?
7053 Address Temp = CGF.CreateMemTemp(OrigTy, "vaarg.promotion-temp");
7054 llvm::Value *Promoted = CGF.Builder.CreateLoad(Addr);
7056 // Truncate down to the right width.
7057 llvm::Type *IntTy = (OrigTy->isIntegerType() ? Temp.getElementType()
7059 llvm::Value *V = CGF.Builder.CreateTrunc(Promoted, IntTy);
7060 if (OrigTy->isPointerType())
7061 V = CGF.Builder.CreateIntToPtr(V, Temp.getElementType());
7063 CGF.Builder.CreateStore(V, Temp);
7070 ABIArgInfo MipsABIInfo::extendType(QualType Ty) const {
7071 int TySize = getContext().getTypeSize(Ty);
7073 // MIPS64 ABI requires unsigned 32 bit integers to be sign extended.
7074 if (Ty->isUnsignedIntegerOrEnumerationType() && TySize == 32)
7075 return ABIArgInfo::getSignExtend(Ty);
7077 return ABIArgInfo::getExtend(Ty);
7081 MIPSTargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
7082 llvm::Value *Address) const {
7083 // This information comes from gcc's implementation, which seems to
7084 // as canonical as it gets.
7086 // Everything on MIPS is 4 bytes. Double-precision FP registers
7087 // are aliased to pairs of single-precision FP registers.
7088 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
7090 // 0-31 are the general purpose registers, $0 - $31.
7091 // 32-63 are the floating-point registers, $f0 - $f31.
7092 // 64 and 65 are the multiply/divide registers, $hi and $lo.
7093 // 66 is the (notional, I think) register for signal-handler return.
7094 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 65);
7096 // 67-74 are the floating-point status registers, $fcc0 - $fcc7.
7097 // They are one bit wide and ignored here.
7099 // 80-111 are the coprocessor 0 registers, $c0r0 - $c0r31.
7100 // (coprocessor 1 is the FP unit)
7101 // 112-143 are the coprocessor 2 registers, $c2r0 - $c2r31.
7102 // 144-175 are the coprocessor 3 registers, $c3r0 - $c3r31.
7103 // 176-181 are the DSP accumulator registers.
7104 AssignToArrayRange(CGF.Builder, Address, Four8, 80, 181);
7108 //===----------------------------------------------------------------------===//
7109 // AVR ABI Implementation.
7110 //===----------------------------------------------------------------------===//
7113 class AVRTargetCodeGenInfo : public TargetCodeGenInfo {
7115 AVRTargetCodeGenInfo(CodeGenTypes &CGT)
7116 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) { }
7118 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
7119 CodeGen::CodeGenModule &CGM) const override {
7120 if (GV->isDeclaration())
7122 const auto *FD = dyn_cast_or_null<FunctionDecl>(D);
7124 auto *Fn = cast<llvm::Function>(GV);
7126 if (FD->getAttr<AVRInterruptAttr>())
7127 Fn->addFnAttr("interrupt");
7129 if (FD->getAttr<AVRSignalAttr>())
7130 Fn->addFnAttr("signal");
7135 //===----------------------------------------------------------------------===//
7136 // TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults.
7137 // Currently subclassed only to implement custom OpenCL C function attribute
7139 //===----------------------------------------------------------------------===//
7143 class TCETargetCodeGenInfo : public DefaultTargetCodeGenInfo {
7145 TCETargetCodeGenInfo(CodeGenTypes &CGT)
7146 : DefaultTargetCodeGenInfo(CGT) {}
7148 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
7149 CodeGen::CodeGenModule &M) const override;
7152 void TCETargetCodeGenInfo::setTargetAttributes(
7153 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
7154 if (GV->isDeclaration())
7156 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
7159 llvm::Function *F = cast<llvm::Function>(GV);
7161 if (M.getLangOpts().OpenCL) {
7162 if (FD->hasAttr<OpenCLKernelAttr>()) {
7163 // OpenCL C Kernel functions are not subject to inlining
7164 F->addFnAttr(llvm::Attribute::NoInline);
7165 const ReqdWorkGroupSizeAttr *Attr = FD->getAttr<ReqdWorkGroupSizeAttr>();
7167 // Convert the reqd_work_group_size() attributes to metadata.
7168 llvm::LLVMContext &Context = F->getContext();
7169 llvm::NamedMDNode *OpenCLMetadata =
7170 M.getModule().getOrInsertNamedMetadata(
7171 "opencl.kernel_wg_size_info");
7173 SmallVector<llvm::Metadata *, 5> Operands;
7174 Operands.push_back(llvm::ConstantAsMetadata::get(F));
7177 llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
7178 M.Int32Ty, llvm::APInt(32, Attr->getXDim()))));
7180 llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
7181 M.Int32Ty, llvm::APInt(32, Attr->getYDim()))));
7183 llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
7184 M.Int32Ty, llvm::APInt(32, Attr->getZDim()))));
7186 // Add a boolean constant operand for "required" (true) or "hint"
7187 // (false) for implementing the work_group_size_hint attr later.
7188 // Currently always true as the hint is not yet implemented.
7190 llvm::ConstantAsMetadata::get(llvm::ConstantInt::getTrue(Context)));
7191 OpenCLMetadata->addOperand(llvm::MDNode::get(Context, Operands));
7199 //===----------------------------------------------------------------------===//
7200 // Hexagon ABI Implementation
7201 //===----------------------------------------------------------------------===//
7205 class HexagonABIInfo : public ABIInfo {
7209 HexagonABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
7213 ABIArgInfo classifyReturnType(QualType RetTy) const;
7214 ABIArgInfo classifyArgumentType(QualType RetTy) const;
7216 void computeInfo(CGFunctionInfo &FI) const override;
7218 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7219 QualType Ty) const override;
7222 class HexagonTargetCodeGenInfo : public TargetCodeGenInfo {
7224 HexagonTargetCodeGenInfo(CodeGenTypes &CGT)
7225 :TargetCodeGenInfo(new HexagonABIInfo(CGT)) {}
7227 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
7234 void HexagonABIInfo::computeInfo(CGFunctionInfo &FI) const {
7235 if (!getCXXABI().classifyReturnType(FI))
7236 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
7237 for (auto &I : FI.arguments())
7238 I.info = classifyArgumentType(I.type);
7241 ABIArgInfo HexagonABIInfo::classifyArgumentType(QualType Ty) const {
7242 if (!isAggregateTypeForABI(Ty)) {
7243 // Treat an enum type as its underlying type.
7244 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
7245 Ty = EnumTy->getDecl()->getIntegerType();
7247 return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty)
7248 : ABIArgInfo::getDirect());
7251 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
7252 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
7254 // Ignore empty records.
7255 if (isEmptyRecord(getContext(), Ty, true))
7256 return ABIArgInfo::getIgnore();
7258 uint64_t Size = getContext().getTypeSize(Ty);
7260 return getNaturalAlignIndirect(Ty, /*ByVal=*/true);
7261 // Pass in the smallest viable integer type.
7263 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
7265 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7267 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7269 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
7272 ABIArgInfo HexagonABIInfo::classifyReturnType(QualType RetTy) const {
7273 if (RetTy->isVoidType())
7274 return ABIArgInfo::getIgnore();
7276 // Large vector types should be returned via memory.
7277 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 64)
7278 return getNaturalAlignIndirect(RetTy);
7280 if (!isAggregateTypeForABI(RetTy)) {
7281 // Treat an enum type as its underlying type.
7282 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
7283 RetTy = EnumTy->getDecl()->getIntegerType();
7285 return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
7286 : ABIArgInfo::getDirect());
7289 if (isEmptyRecord(getContext(), RetTy, true))
7290 return ABIArgInfo::getIgnore();
7292 // Aggregates <= 8 bytes are returned in r0; other aggregates
7293 // are returned indirectly.
7294 uint64_t Size = getContext().getTypeSize(RetTy);
7296 // Return in the smallest viable integer type.
7298 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
7300 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7302 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7303 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
7306 return getNaturalAlignIndirect(RetTy, /*ByVal=*/true);
7309 Address HexagonABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7310 QualType Ty) const {
7311 // FIXME: Someone needs to audit that this handle alignment correctly.
7312 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
7313 getContext().getTypeInfoInChars(Ty),
7314 CharUnits::fromQuantity(4),
7315 /*AllowHigherAlign*/ true);
7318 //===----------------------------------------------------------------------===//
7319 // Lanai ABI Implementation
7320 //===----------------------------------------------------------------------===//
7323 class LanaiABIInfo : public DefaultABIInfo {
7325 LanaiABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
7327 bool shouldUseInReg(QualType Ty, CCState &State) const;
7329 void computeInfo(CGFunctionInfo &FI) const override {
7330 CCState State(FI.getCallingConvention());
7331 // Lanai uses 4 registers to pass arguments unless the function has the
7332 // regparm attribute set.
7333 if (FI.getHasRegParm()) {
7334 State.FreeRegs = FI.getRegParm();
7339 if (!getCXXABI().classifyReturnType(FI))
7340 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
7341 for (auto &I : FI.arguments())
7342 I.info = classifyArgumentType(I.type, State);
7345 ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
7346 ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
7348 } // end anonymous namespace
7350 bool LanaiABIInfo::shouldUseInReg(QualType Ty, CCState &State) const {
7351 unsigned Size = getContext().getTypeSize(Ty);
7352 unsigned SizeInRegs = llvm::alignTo(Size, 32U) / 32U;
7354 if (SizeInRegs == 0)
7357 if (SizeInRegs > State.FreeRegs) {
7362 State.FreeRegs -= SizeInRegs;
7367 ABIArgInfo LanaiABIInfo::getIndirectResult(QualType Ty, bool ByVal,
7368 CCState &State) const {
7370 if (State.FreeRegs) {
7371 --State.FreeRegs; // Non-byval indirects just use one pointer.
7372 return getNaturalAlignIndirectInReg(Ty);
7374 return getNaturalAlignIndirect(Ty, false);
7377 // Compute the byval alignment.
7378 const unsigned MinABIStackAlignInBytes = 4;
7379 unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
7380 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true,
7381 /*Realign=*/TypeAlign >
7382 MinABIStackAlignInBytes);
7385 ABIArgInfo LanaiABIInfo::classifyArgumentType(QualType Ty,
7386 CCState &State) const {
7387 // Check with the C++ ABI first.
7388 const RecordType *RT = Ty->getAs<RecordType>();
7390 CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
7391 if (RAA == CGCXXABI::RAA_Indirect) {
7392 return getIndirectResult(Ty, /*ByVal=*/false, State);
7393 } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
7394 return getNaturalAlignIndirect(Ty, /*ByRef=*/true);
7398 if (isAggregateTypeForABI(Ty)) {
7399 // Structures with flexible arrays are always indirect.
7400 if (RT && RT->getDecl()->hasFlexibleArrayMember())
7401 return getIndirectResult(Ty, /*ByVal=*/true, State);
7403 // Ignore empty structs/unions.
7404 if (isEmptyRecord(getContext(), Ty, true))
7405 return ABIArgInfo::getIgnore();
7407 llvm::LLVMContext &LLVMContext = getVMContext();
7408 unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
7409 if (SizeInRegs <= State.FreeRegs) {
7410 llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
7411 SmallVector<llvm::Type *, 3> Elements(SizeInRegs, Int32);
7412 llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
7413 State.FreeRegs -= SizeInRegs;
7414 return ABIArgInfo::getDirectInReg(Result);
7418 return getIndirectResult(Ty, true, State);
7421 // Treat an enum type as its underlying type.
7422 if (const auto *EnumTy = Ty->getAs<EnumType>())
7423 Ty = EnumTy->getDecl()->getIntegerType();
7425 bool InReg = shouldUseInReg(Ty, State);
7426 if (Ty->isPromotableIntegerType()) {
7428 return ABIArgInfo::getDirectInReg();
7429 return ABIArgInfo::getExtend(Ty);
7432 return ABIArgInfo::getDirectInReg();
7433 return ABIArgInfo::getDirect();
7437 class LanaiTargetCodeGenInfo : public TargetCodeGenInfo {
7439 LanaiTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
7440 : TargetCodeGenInfo(new LanaiABIInfo(CGT)) {}
7444 //===----------------------------------------------------------------------===//
7445 // AMDGPU ABI Implementation
7446 //===----------------------------------------------------------------------===//
7450 class AMDGPUABIInfo final : public DefaultABIInfo {
7452 static const unsigned MaxNumRegsForArgsRet = 16;
7454 unsigned numRegsForType(QualType Ty) const;
7456 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
7457 bool isHomogeneousAggregateSmallEnough(const Type *Base,
7458 uint64_t Members) const override;
7461 explicit AMDGPUABIInfo(CodeGen::CodeGenTypes &CGT) :
7462 DefaultABIInfo(CGT) {}
7464 ABIArgInfo classifyReturnType(QualType RetTy) const;
7465 ABIArgInfo classifyKernelArgumentType(QualType Ty) const;
7466 ABIArgInfo classifyArgumentType(QualType Ty, unsigned &NumRegsLeft) const;
7468 void computeInfo(CGFunctionInfo &FI) const override;
7471 bool AMDGPUABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
7475 bool AMDGPUABIInfo::isHomogeneousAggregateSmallEnough(
7476 const Type *Base, uint64_t Members) const {
7477 uint32_t NumRegs = (getContext().getTypeSize(Base) + 31) / 32;
7479 // Homogeneous Aggregates may occupy at most 16 registers.
7480 return Members * NumRegs <= MaxNumRegsForArgsRet;
7483 /// Estimate number of registers the type will use when passed in registers.
7484 unsigned AMDGPUABIInfo::numRegsForType(QualType Ty) const {
7485 unsigned NumRegs = 0;
7487 if (const VectorType *VT = Ty->getAs<VectorType>()) {
7488 // Compute from the number of elements. The reported size is based on the
7489 // in-memory size, which includes the padding 4th element for 3-vectors.
7490 QualType EltTy = VT->getElementType();
7491 unsigned EltSize = getContext().getTypeSize(EltTy);
7493 // 16-bit element vectors should be passed as packed.
7495 return (VT->getNumElements() + 1) / 2;
7497 unsigned EltNumRegs = (EltSize + 31) / 32;
7498 return EltNumRegs * VT->getNumElements();
7501 if (const RecordType *RT = Ty->getAs<RecordType>()) {
7502 const RecordDecl *RD = RT->getDecl();
7503 assert(!RD->hasFlexibleArrayMember());
7505 for (const FieldDecl *Field : RD->fields()) {
7506 QualType FieldTy = Field->getType();
7507 NumRegs += numRegsForType(FieldTy);
7513 return (getContext().getTypeSize(Ty) + 31) / 32;
7516 void AMDGPUABIInfo::computeInfo(CGFunctionInfo &FI) const {
7517 llvm::CallingConv::ID CC = FI.getCallingConvention();
7519 if (!getCXXABI().classifyReturnType(FI))
7520 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
7522 unsigned NumRegsLeft = MaxNumRegsForArgsRet;
7523 for (auto &Arg : FI.arguments()) {
7524 if (CC == llvm::CallingConv::AMDGPU_KERNEL) {
7525 Arg.info = classifyKernelArgumentType(Arg.type);
7527 Arg.info = classifyArgumentType(Arg.type, NumRegsLeft);
7532 ABIArgInfo AMDGPUABIInfo::classifyReturnType(QualType RetTy) const {
7533 if (isAggregateTypeForABI(RetTy)) {
7534 // Records with non-trivial destructors/copy-constructors should not be
7535 // returned by value.
7536 if (!getRecordArgABI(RetTy, getCXXABI())) {
7537 // Ignore empty structs/unions.
7538 if (isEmptyRecord(getContext(), RetTy, true))
7539 return ABIArgInfo::getIgnore();
7541 // Lower single-element structs to just return a regular value.
7542 if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
7543 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
7545 if (const RecordType *RT = RetTy->getAs<RecordType>()) {
7546 const RecordDecl *RD = RT->getDecl();
7547 if (RD->hasFlexibleArrayMember())
7548 return DefaultABIInfo::classifyReturnType(RetTy);
7551 // Pack aggregates <= 4 bytes into single VGPR or pair.
7552 uint64_t Size = getContext().getTypeSize(RetTy);
7554 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7557 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7560 llvm::Type *I32Ty = llvm::Type::getInt32Ty(getVMContext());
7561 return ABIArgInfo::getDirect(llvm::ArrayType::get(I32Ty, 2));
7564 if (numRegsForType(RetTy) <= MaxNumRegsForArgsRet)
7565 return ABIArgInfo::getDirect();
7569 // Otherwise just do the default thing.
7570 return DefaultABIInfo::classifyReturnType(RetTy);
7573 /// For kernels all parameters are really passed in a special buffer. It doesn't
7574 /// make sense to pass anything byval, so everything must be direct.
7575 ABIArgInfo AMDGPUABIInfo::classifyKernelArgumentType(QualType Ty) const {
7576 Ty = useFirstFieldIfTransparentUnion(Ty);
7578 // TODO: Can we omit empty structs?
7580 // Coerce single element structs to its element.
7581 if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
7582 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
7584 // If we set CanBeFlattened to true, CodeGen will expand the struct to its
7585 // individual elements, which confuses the Clover OpenCL backend; therefore we
7586 // have to set it to false here. Other args of getDirect() are just defaults.
7587 return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
7590 ABIArgInfo AMDGPUABIInfo::classifyArgumentType(QualType Ty,
7591 unsigned &NumRegsLeft) const {
7592 assert(NumRegsLeft <= MaxNumRegsForArgsRet && "register estimate underflow");
7594 Ty = useFirstFieldIfTransparentUnion(Ty);
7596 if (isAggregateTypeForABI(Ty)) {
7597 // Records with non-trivial destructors/copy-constructors should not be
7599 if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
7600 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
7602 // Ignore empty structs/unions.
7603 if (isEmptyRecord(getContext(), Ty, true))
7604 return ABIArgInfo::getIgnore();
7606 // Lower single-element structs to just pass a regular value. TODO: We
7607 // could do reasonable-size multiple-element structs too, using getExpand(),
7608 // though watch out for things like bitfields.
7609 if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
7610 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
7612 if (const RecordType *RT = Ty->getAs<RecordType>()) {
7613 const RecordDecl *RD = RT->getDecl();
7614 if (RD->hasFlexibleArrayMember())
7615 return DefaultABIInfo::classifyArgumentType(Ty);
7618 // Pack aggregates <= 8 bytes into single VGPR or pair.
7619 uint64_t Size = getContext().getTypeSize(Ty);
7621 unsigned NumRegs = (Size + 31) / 32;
7622 NumRegsLeft -= std::min(NumRegsLeft, NumRegs);
7625 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7628 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7630 // XXX: Should this be i64 instead, and should the limit increase?
7631 llvm::Type *I32Ty = llvm::Type::getInt32Ty(getVMContext());
7632 return ABIArgInfo::getDirect(llvm::ArrayType::get(I32Ty, 2));
7635 if (NumRegsLeft > 0) {
7636 unsigned NumRegs = numRegsForType(Ty);
7637 if (NumRegsLeft >= NumRegs) {
7638 NumRegsLeft -= NumRegs;
7639 return ABIArgInfo::getDirect();
7644 // Otherwise just do the default thing.
7645 ABIArgInfo ArgInfo = DefaultABIInfo::classifyArgumentType(Ty);
7646 if (!ArgInfo.isIndirect()) {
7647 unsigned NumRegs = numRegsForType(Ty);
7648 NumRegsLeft -= std::min(NumRegs, NumRegsLeft);
7654 class AMDGPUTargetCodeGenInfo : public TargetCodeGenInfo {
7656 AMDGPUTargetCodeGenInfo(CodeGenTypes &CGT)
7657 : TargetCodeGenInfo(new AMDGPUABIInfo(CGT)) {}
7658 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
7659 CodeGen::CodeGenModule &M) const override;
7660 unsigned getOpenCLKernelCallingConv() const override;
7662 llvm::Constant *getNullPointer(const CodeGen::CodeGenModule &CGM,
7663 llvm::PointerType *T, QualType QT) const override;
7665 LangAS getASTAllocaAddressSpace() const override {
7666 return getLangASFromTargetAS(
7667 getABIInfo().getDataLayout().getAllocaAddrSpace());
7669 LangAS getGlobalVarAddressSpace(CodeGenModule &CGM,
7670 const VarDecl *D) const override;
7671 llvm::SyncScope::ID getLLVMSyncScopeID(SyncScope S,
7672 llvm::LLVMContext &C) const override;
7674 createEnqueuedBlockKernel(CodeGenFunction &CGF,
7675 llvm::Function *BlockInvokeFunc,
7676 llvm::Value *BlockLiteral) const override;
7677 bool shouldEmitStaticExternCAliases() const override;
7678 void setCUDAKernelCallingConvention(const FunctionType *&FT) const override;
7682 void AMDGPUTargetCodeGenInfo::setTargetAttributes(
7683 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
7684 if (GV->isDeclaration())
7686 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
7690 llvm::Function *F = cast<llvm::Function>(GV);
7692 const auto *ReqdWGS = M.getLangOpts().OpenCL ?
7693 FD->getAttr<ReqdWorkGroupSizeAttr>() : nullptr;
7695 if (M.getLangOpts().OpenCL && FD->hasAttr<OpenCLKernelAttr>() &&
7696 (M.getTriple().getOS() == llvm::Triple::AMDHSA))
7697 F->addFnAttr("amdgpu-implicitarg-num-bytes", "48");
7699 const auto *FlatWGS = FD->getAttr<AMDGPUFlatWorkGroupSizeAttr>();
7700 if (ReqdWGS || FlatWGS) {
7701 unsigned Min = FlatWGS ? FlatWGS->getMin() : 0;
7702 unsigned Max = FlatWGS ? FlatWGS->getMax() : 0;
7703 if (ReqdWGS && Min == 0 && Max == 0)
7704 Min = Max = ReqdWGS->getXDim() * ReqdWGS->getYDim() * ReqdWGS->getZDim();
7707 assert(Min <= Max && "Min must be less than or equal Max");
7709 std::string AttrVal = llvm::utostr(Min) + "," + llvm::utostr(Max);
7710 F->addFnAttr("amdgpu-flat-work-group-size", AttrVal);
7712 assert(Max == 0 && "Max must be zero");
7715 if (const auto *Attr = FD->getAttr<AMDGPUWavesPerEUAttr>()) {
7716 unsigned Min = Attr->getMin();
7717 unsigned Max = Attr->getMax();
7720 assert((Max == 0 || Min <= Max) && "Min must be less than or equal Max");
7722 std::string AttrVal = llvm::utostr(Min);
7724 AttrVal = AttrVal + "," + llvm::utostr(Max);
7725 F->addFnAttr("amdgpu-waves-per-eu", AttrVal);
7727 assert(Max == 0 && "Max must be zero");
7730 if (const auto *Attr = FD->getAttr<AMDGPUNumSGPRAttr>()) {
7731 unsigned NumSGPR = Attr->getNumSGPR();
7734 F->addFnAttr("amdgpu-num-sgpr", llvm::utostr(NumSGPR));
7737 if (const auto *Attr = FD->getAttr<AMDGPUNumVGPRAttr>()) {
7738 uint32_t NumVGPR = Attr->getNumVGPR();
7741 F->addFnAttr("amdgpu-num-vgpr", llvm::utostr(NumVGPR));
7745 unsigned AMDGPUTargetCodeGenInfo::getOpenCLKernelCallingConv() const {
7746 return llvm::CallingConv::AMDGPU_KERNEL;
7749 // Currently LLVM assumes null pointers always have value 0,
7750 // which results in incorrectly transformed IR. Therefore, instead of
7751 // emitting null pointers in private and local address spaces, a null
7752 // pointer in generic address space is emitted which is casted to a
7753 // pointer in local or private address space.
7754 llvm::Constant *AMDGPUTargetCodeGenInfo::getNullPointer(
7755 const CodeGen::CodeGenModule &CGM, llvm::PointerType *PT,
7756 QualType QT) const {
7757 if (CGM.getContext().getTargetNullPointerValue(QT) == 0)
7758 return llvm::ConstantPointerNull::get(PT);
7760 auto &Ctx = CGM.getContext();
7761 auto NPT = llvm::PointerType::get(PT->getElementType(),
7762 Ctx.getTargetAddressSpace(LangAS::opencl_generic));
7763 return llvm::ConstantExpr::getAddrSpaceCast(
7764 llvm::ConstantPointerNull::get(NPT), PT);
7768 AMDGPUTargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
7769 const VarDecl *D) const {
7770 assert(!CGM.getLangOpts().OpenCL &&
7771 !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
7772 "Address space agnostic languages only");
7773 LangAS DefaultGlobalAS = getLangASFromTargetAS(
7774 CGM.getContext().getTargetAddressSpace(LangAS::opencl_global));
7776 return DefaultGlobalAS;
7778 LangAS AddrSpace = D->getType().getAddressSpace();
7779 assert(AddrSpace == LangAS::Default || isTargetAddressSpace(AddrSpace));
7780 if (AddrSpace != LangAS::Default)
7783 if (CGM.isTypeConstant(D->getType(), false)) {
7784 if (auto ConstAS = CGM.getTarget().getConstantAddressSpace())
7785 return ConstAS.getValue();
7787 return DefaultGlobalAS;
7791 AMDGPUTargetCodeGenInfo::getLLVMSyncScopeID(SyncScope S,
7792 llvm::LLVMContext &C) const {
7795 case SyncScope::OpenCLWorkGroup:
7798 case SyncScope::OpenCLDevice:
7801 case SyncScope::OpenCLAllSVMDevices:
7804 case SyncScope::OpenCLSubGroup:
7807 return C.getOrInsertSyncScopeID(Name);
7810 bool AMDGPUTargetCodeGenInfo::shouldEmitStaticExternCAliases() const {
7814 void AMDGPUTargetCodeGenInfo::setCUDAKernelCallingConvention(
7815 const FunctionType *&FT) const {
7816 FT = getABIInfo().getContext().adjustFunctionType(
7817 FT, FT->getExtInfo().withCallingConv(CC_OpenCLKernel));
7820 //===----------------------------------------------------------------------===//
7821 // SPARC v8 ABI Implementation.
7822 // Based on the SPARC Compliance Definition version 2.4.1.
7824 // Ensures that complex values are passed in registers.
7827 class SparcV8ABIInfo : public DefaultABIInfo {
7829 SparcV8ABIInfo(CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
7832 ABIArgInfo classifyReturnType(QualType RetTy) const;
7833 void computeInfo(CGFunctionInfo &FI) const override;
7835 } // end anonymous namespace
7839 SparcV8ABIInfo::classifyReturnType(QualType Ty) const {
7840 if (Ty->isAnyComplexType()) {
7841 return ABIArgInfo::getDirect();
7844 return DefaultABIInfo::classifyReturnType(Ty);
7848 void SparcV8ABIInfo::computeInfo(CGFunctionInfo &FI) const {
7850 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
7851 for (auto &Arg : FI.arguments())
7852 Arg.info = classifyArgumentType(Arg.type);
7856 class SparcV8TargetCodeGenInfo : public TargetCodeGenInfo {
7858 SparcV8TargetCodeGenInfo(CodeGenTypes &CGT)
7859 : TargetCodeGenInfo(new SparcV8ABIInfo(CGT)) {}
7861 } // end anonymous namespace
7863 //===----------------------------------------------------------------------===//
7864 // SPARC v9 ABI Implementation.
7865 // Based on the SPARC Compliance Definition version 2.4.1.
7867 // Function arguments a mapped to a nominal "parameter array" and promoted to
7868 // registers depending on their type. Each argument occupies 8 or 16 bytes in
7869 // the array, structs larger than 16 bytes are passed indirectly.
7871 // One case requires special care:
7878 // When a struct mixed is passed by value, it only occupies 8 bytes in the
7879 // parameter array, but the int is passed in an integer register, and the float
7880 // is passed in a floating point register. This is represented as two arguments
7881 // with the LLVM IR inreg attribute:
7883 // declare void f(i32 inreg %i, float inreg %f)
7885 // The code generator will only allocate 4 bytes from the parameter array for
7886 // the inreg arguments. All other arguments are allocated a multiple of 8
7890 class SparcV9ABIInfo : public ABIInfo {
7892 SparcV9ABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
7895 ABIArgInfo classifyType(QualType RetTy, unsigned SizeLimit) const;
7896 void computeInfo(CGFunctionInfo &FI) const override;
7897 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7898 QualType Ty) const override;
7900 // Coercion type builder for structs passed in registers. The coercion type
7901 // serves two purposes:
7903 // 1. Pad structs to a multiple of 64 bits, so they are passed 'left-aligned'
7905 // 2. Expose aligned floating point elements as first-level elements, so the
7906 // code generator knows to pass them in floating point registers.
7908 // We also compute the InReg flag which indicates that the struct contains
7909 // aligned 32-bit floats.
7911 struct CoerceBuilder {
7912 llvm::LLVMContext &Context;
7913 const llvm::DataLayout &DL;
7914 SmallVector<llvm::Type*, 8> Elems;
7918 CoerceBuilder(llvm::LLVMContext &c, const llvm::DataLayout &dl)
7919 : Context(c), DL(dl), Size(0), InReg(false) {}
7921 // Pad Elems with integers until Size is ToSize.
7922 void pad(uint64_t ToSize) {
7923 assert(ToSize >= Size && "Cannot remove elements");
7927 // Finish the current 64-bit word.
7928 uint64_t Aligned = llvm::alignTo(Size, 64);
7929 if (Aligned > Size && Aligned <= ToSize) {
7930 Elems.push_back(llvm::IntegerType::get(Context, Aligned - Size));
7934 // Add whole 64-bit words.
7935 while (Size + 64 <= ToSize) {
7936 Elems.push_back(llvm::Type::getInt64Ty(Context));
7940 // Final in-word padding.
7941 if (Size < ToSize) {
7942 Elems.push_back(llvm::IntegerType::get(Context, ToSize - Size));
7947 // Add a floating point element at Offset.
7948 void addFloat(uint64_t Offset, llvm::Type *Ty, unsigned Bits) {
7949 // Unaligned floats are treated as integers.
7952 // The InReg flag is only required if there are any floats < 64 bits.
7956 Elems.push_back(Ty);
7957 Size = Offset + Bits;
7960 // Add a struct type to the coercion type, starting at Offset (in bits).
7961 void addStruct(uint64_t Offset, llvm::StructType *StrTy) {
7962 const llvm::StructLayout *Layout = DL.getStructLayout(StrTy);
7963 for (unsigned i = 0, e = StrTy->getNumElements(); i != e; ++i) {
7964 llvm::Type *ElemTy = StrTy->getElementType(i);
7965 uint64_t ElemOffset = Offset + Layout->getElementOffsetInBits(i);
7966 switch (ElemTy->getTypeID()) {
7967 case llvm::Type::StructTyID:
7968 addStruct(ElemOffset, cast<llvm::StructType>(ElemTy));
7970 case llvm::Type::FloatTyID:
7971 addFloat(ElemOffset, ElemTy, 32);
7973 case llvm::Type::DoubleTyID:
7974 addFloat(ElemOffset, ElemTy, 64);
7976 case llvm::Type::FP128TyID:
7977 addFloat(ElemOffset, ElemTy, 128);
7979 case llvm::Type::PointerTyID:
7980 if (ElemOffset % 64 == 0) {
7982 Elems.push_back(ElemTy);
7992 // Check if Ty is a usable substitute for the coercion type.
7993 bool isUsableType(llvm::StructType *Ty) const {
7994 return llvm::makeArrayRef(Elems) == Ty->elements();
7997 // Get the coercion type as a literal struct type.
7998 llvm::Type *getType() const {
7999 if (Elems.size() == 1)
8000 return Elems.front();
8002 return llvm::StructType::get(Context, Elems);
8006 } // end anonymous namespace
8009 SparcV9ABIInfo::classifyType(QualType Ty, unsigned SizeLimit) const {
8010 if (Ty->isVoidType())
8011 return ABIArgInfo::getIgnore();
8013 uint64_t Size = getContext().getTypeSize(Ty);
8015 // Anything too big to fit in registers is passed with an explicit indirect
8016 // pointer / sret pointer.
8017 if (Size > SizeLimit)
8018 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
8020 // Treat an enum type as its underlying type.
8021 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
8022 Ty = EnumTy->getDecl()->getIntegerType();
8024 // Integer types smaller than a register are extended.
8025 if (Size < 64 && Ty->isIntegerType())
8026 return ABIArgInfo::getExtend(Ty);
8028 // Other non-aggregates go in registers.
8029 if (!isAggregateTypeForABI(Ty))
8030 return ABIArgInfo::getDirect();
8032 // If a C++ object has either a non-trivial copy constructor or a non-trivial
8033 // destructor, it is passed with an explicit indirect pointer / sret pointer.
8034 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
8035 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
8037 // This is a small aggregate type that should be passed in registers.
8038 // Build a coercion type from the LLVM struct type.
8039 llvm::StructType *StrTy = dyn_cast<llvm::StructType>(CGT.ConvertType(Ty));
8041 return ABIArgInfo::getDirect();
8043 CoerceBuilder CB(getVMContext(), getDataLayout());
8044 CB.addStruct(0, StrTy);
8045 CB.pad(llvm::alignTo(CB.DL.getTypeSizeInBits(StrTy), 64));
8047 // Try to use the original type for coercion.
8048 llvm::Type *CoerceTy = CB.isUsableType(StrTy) ? StrTy : CB.getType();
8051 return ABIArgInfo::getDirectInReg(CoerceTy);
8053 return ABIArgInfo::getDirect(CoerceTy);
8056 Address SparcV9ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8057 QualType Ty) const {
8058 ABIArgInfo AI = classifyType(Ty, 16 * 8);
8059 llvm::Type *ArgTy = CGT.ConvertType(Ty);
8060 if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
8061 AI.setCoerceToType(ArgTy);
8063 CharUnits SlotSize = CharUnits::fromQuantity(8);
8065 CGBuilderTy &Builder = CGF.Builder;
8066 Address Addr(Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize);
8067 llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
8069 auto TypeInfo = getContext().getTypeInfoInChars(Ty);
8071 Address ArgAddr = Address::invalid();
8073 switch (AI.getKind()) {
8074 case ABIArgInfo::Expand:
8075 case ABIArgInfo::CoerceAndExpand:
8076 case ABIArgInfo::InAlloca:
8077 llvm_unreachable("Unsupported ABI kind for va_arg");
8079 case ABIArgInfo::Extend: {
8081 CharUnits Offset = SlotSize - TypeInfo.first;
8082 ArgAddr = Builder.CreateConstInBoundsByteGEP(Addr, Offset, "extend");
8086 case ABIArgInfo::Direct: {
8087 auto AllocSize = getDataLayout().getTypeAllocSize(AI.getCoerceToType());
8088 Stride = CharUnits::fromQuantity(AllocSize).alignTo(SlotSize);
8093 case ABIArgInfo::Indirect:
8095 ArgAddr = Builder.CreateElementBitCast(Addr, ArgPtrTy, "indirect");
8096 ArgAddr = Address(Builder.CreateLoad(ArgAddr, "indirect.arg"),
8100 case ABIArgInfo::Ignore:
8101 return Address(llvm::UndefValue::get(ArgPtrTy), TypeInfo.second);
8105 llvm::Value *NextPtr =
8106 Builder.CreateConstInBoundsByteGEP(Addr.getPointer(), Stride, "ap.next");
8107 Builder.CreateStore(NextPtr, VAListAddr);
8109 return Builder.CreateBitCast(ArgAddr, ArgPtrTy, "arg.addr");
8112 void SparcV9ABIInfo::computeInfo(CGFunctionInfo &FI) const {
8113 FI.getReturnInfo() = classifyType(FI.getReturnType(), 32 * 8);
8114 for (auto &I : FI.arguments())
8115 I.info = classifyType(I.type, 16 * 8);
8119 class SparcV9TargetCodeGenInfo : public TargetCodeGenInfo {
8121 SparcV9TargetCodeGenInfo(CodeGenTypes &CGT)
8122 : TargetCodeGenInfo(new SparcV9ABIInfo(CGT)) {}
8124 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
8128 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
8129 llvm::Value *Address) const override;
8131 } // end anonymous namespace
8134 SparcV9TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
8135 llvm::Value *Address) const {
8136 // This is calculated from the LLVM and GCC tables and verified
8137 // against gcc output. AFAIK all ABIs use the same encoding.
8139 CodeGen::CGBuilderTy &Builder = CGF.Builder;
8141 llvm::IntegerType *i8 = CGF.Int8Ty;
8142 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
8143 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
8145 // 0-31: the 8-byte general-purpose registers
8146 AssignToArrayRange(Builder, Address, Eight8, 0, 31);
8148 // 32-63: f0-31, the 4-byte floating-point registers
8149 AssignToArrayRange(Builder, Address, Four8, 32, 63);
8159 AssignToArrayRange(Builder, Address, Eight8, 64, 71);
8161 // 72-87: d0-15, the 8-byte floating-point registers
8162 AssignToArrayRange(Builder, Address, Eight8, 72, 87);
8168 //===----------------------------------------------------------------------===//
8169 // XCore ABI Implementation
8170 //===----------------------------------------------------------------------===//
8174 /// A SmallStringEnc instance is used to build up the TypeString by passing
8175 /// it by reference between functions that append to it.
8176 typedef llvm::SmallString<128> SmallStringEnc;
8178 /// TypeStringCache caches the meta encodings of Types.
8180 /// The reason for caching TypeStrings is two fold:
8181 /// 1. To cache a type's encoding for later uses;
8182 /// 2. As a means to break recursive member type inclusion.
8184 /// A cache Entry can have a Status of:
8185 /// NonRecursive: The type encoding is not recursive;
8186 /// Recursive: The type encoding is recursive;
8187 /// Incomplete: An incomplete TypeString;
8188 /// IncompleteUsed: An incomplete TypeString that has been used in a
8189 /// Recursive type encoding.
8191 /// A NonRecursive entry will have all of its sub-members expanded as fully
8192 /// as possible. Whilst it may contain types which are recursive, the type
8193 /// itself is not recursive and thus its encoding may be safely used whenever
8194 /// the type is encountered.
8196 /// A Recursive entry will have all of its sub-members expanded as fully as
8197 /// possible. The type itself is recursive and it may contain other types which
8198 /// are recursive. The Recursive encoding must not be used during the expansion
8199 /// of a recursive type's recursive branch. For simplicity the code uses
8200 /// IncompleteCount to reject all usage of Recursive encodings for member types.
8202 /// An Incomplete entry is always a RecordType and only encodes its
8203 /// identifier e.g. "s(S){}". Incomplete 'StubEnc' entries are ephemeral and
8204 /// are placed into the cache during type expansion as a means to identify and
8205 /// handle recursive inclusion of types as sub-members. If there is recursion
8206 /// the entry becomes IncompleteUsed.
8208 /// During the expansion of a RecordType's members:
8210 /// If the cache contains a NonRecursive encoding for the member type, the
8211 /// cached encoding is used;
8213 /// If the cache contains a Recursive encoding for the member type, the
8214 /// cached encoding is 'Swapped' out, as it may be incorrect, and...
8216 /// If the member is a RecordType, an Incomplete encoding is placed into the
8217 /// cache to break potential recursive inclusion of itself as a sub-member;
8219 /// Once a member RecordType has been expanded, its temporary incomplete
8220 /// entry is removed from the cache. If a Recursive encoding was swapped out
8221 /// it is swapped back in;
8223 /// If an incomplete entry is used to expand a sub-member, the incomplete
8224 /// entry is marked as IncompleteUsed. The cache keeps count of how many
8225 /// IncompleteUsed entries it currently contains in IncompleteUsedCount;
8227 /// If a member's encoding is found to be a NonRecursive or Recursive viz:
8228 /// IncompleteUsedCount==0, the member's encoding is added to the cache.
8229 /// Else the member is part of a recursive type and thus the recursion has
8230 /// been exited too soon for the encoding to be correct for the member.
8232 class TypeStringCache {
8233 enum Status {NonRecursive, Recursive, Incomplete, IncompleteUsed};
8235 std::string Str; // The encoded TypeString for the type.
8236 enum Status State; // Information about the encoding in 'Str'.
8237 std::string Swapped; // A temporary place holder for a Recursive encoding
8238 // during the expansion of RecordType's members.
8240 std::map<const IdentifierInfo *, struct Entry> Map;
8241 unsigned IncompleteCount; // Number of Incomplete entries in the Map.
8242 unsigned IncompleteUsedCount; // Number of IncompleteUsed entries in the Map.
8244 TypeStringCache() : IncompleteCount(0), IncompleteUsedCount(0) {}
8245 void addIncomplete(const IdentifierInfo *ID, std::string StubEnc);
8246 bool removeIncomplete(const IdentifierInfo *ID);
8247 void addIfComplete(const IdentifierInfo *ID, StringRef Str,
8249 StringRef lookupStr(const IdentifierInfo *ID);
8252 /// TypeString encodings for enum & union fields must be order.
8253 /// FieldEncoding is a helper for this ordering process.
8254 class FieldEncoding {
8258 FieldEncoding(bool b, SmallStringEnc &e) : HasName(b), Enc(e.c_str()) {}
8259 StringRef str() { return Enc; }
8260 bool operator<(const FieldEncoding &rhs) const {
8261 if (HasName != rhs.HasName) return HasName;
8262 return Enc < rhs.Enc;
8266 class XCoreABIInfo : public DefaultABIInfo {
8268 XCoreABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
8269 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8270 QualType Ty) const override;
8273 class XCoreTargetCodeGenInfo : public TargetCodeGenInfo {
8274 mutable TypeStringCache TSC;
8276 XCoreTargetCodeGenInfo(CodeGenTypes &CGT)
8277 :TargetCodeGenInfo(new XCoreABIInfo(CGT)) {}
8278 void emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
8279 CodeGen::CodeGenModule &M) const override;
8282 } // End anonymous namespace.
8284 // TODO: this implementation is likely now redundant with the default
8286 Address XCoreABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8287 QualType Ty) const {
8288 CGBuilderTy &Builder = CGF.Builder;
8291 CharUnits SlotSize = CharUnits::fromQuantity(4);
8292 Address AP(Builder.CreateLoad(VAListAddr), SlotSize);
8294 // Handle the argument.
8295 ABIArgInfo AI = classifyArgumentType(Ty);
8296 CharUnits TypeAlign = getContext().getTypeAlignInChars(Ty);
8297 llvm::Type *ArgTy = CGT.ConvertType(Ty);
8298 if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
8299 AI.setCoerceToType(ArgTy);
8300 llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
8302 Address Val = Address::invalid();
8303 CharUnits ArgSize = CharUnits::Zero();
8304 switch (AI.getKind()) {
8305 case ABIArgInfo::Expand:
8306 case ABIArgInfo::CoerceAndExpand:
8307 case ABIArgInfo::InAlloca:
8308 llvm_unreachable("Unsupported ABI kind for va_arg");
8309 case ABIArgInfo::Ignore:
8310 Val = Address(llvm::UndefValue::get(ArgPtrTy), TypeAlign);
8311 ArgSize = CharUnits::Zero();
8313 case ABIArgInfo::Extend:
8314 case ABIArgInfo::Direct:
8315 Val = Builder.CreateBitCast(AP, ArgPtrTy);
8316 ArgSize = CharUnits::fromQuantity(
8317 getDataLayout().getTypeAllocSize(AI.getCoerceToType()));
8318 ArgSize = ArgSize.alignTo(SlotSize);
8320 case ABIArgInfo::Indirect:
8321 Val = Builder.CreateElementBitCast(AP, ArgPtrTy);
8322 Val = Address(Builder.CreateLoad(Val), TypeAlign);
8327 // Increment the VAList.
8328 if (!ArgSize.isZero()) {
8330 Builder.CreateConstInBoundsByteGEP(AP.getPointer(), ArgSize);
8331 Builder.CreateStore(APN, VAListAddr);
8337 /// During the expansion of a RecordType, an incomplete TypeString is placed
8338 /// into the cache as a means to identify and break recursion.
8339 /// If there is a Recursive encoding in the cache, it is swapped out and will
8340 /// be reinserted by removeIncomplete().
8341 /// All other types of encoding should have been used rather than arriving here.
8342 void TypeStringCache::addIncomplete(const IdentifierInfo *ID,
8343 std::string StubEnc) {
8347 assert( (E.Str.empty() || E.State == Recursive) &&
8348 "Incorrectly use of addIncomplete");
8349 assert(!StubEnc.empty() && "Passing an empty string to addIncomplete()");
8350 E.Swapped.swap(E.Str); // swap out the Recursive
8351 E.Str.swap(StubEnc);
8352 E.State = Incomplete;
8356 /// Once the RecordType has been expanded, the temporary incomplete TypeString
8357 /// must be removed from the cache.
8358 /// If a Recursive was swapped out by addIncomplete(), it will be replaced.
8359 /// Returns true if the RecordType was defined recursively.
8360 bool TypeStringCache::removeIncomplete(const IdentifierInfo *ID) {
8363 auto I = Map.find(ID);
8364 assert(I != Map.end() && "Entry not present");
8365 Entry &E = I->second;
8366 assert( (E.State == Incomplete ||
8367 E.State == IncompleteUsed) &&
8368 "Entry must be an incomplete type");
8369 bool IsRecursive = false;
8370 if (E.State == IncompleteUsed) {
8371 // We made use of our Incomplete encoding, thus we are recursive.
8373 --IncompleteUsedCount;
8375 if (E.Swapped.empty())
8378 // Swap the Recursive back.
8379 E.Swapped.swap(E.Str);
8381 E.State = Recursive;
8387 /// Add the encoded TypeString to the cache only if it is NonRecursive or
8388 /// Recursive (viz: all sub-members were expanded as fully as possible).
8389 void TypeStringCache::addIfComplete(const IdentifierInfo *ID, StringRef Str,
8391 if (!ID || IncompleteUsedCount)
8392 return; // No key or it is is an incomplete sub-type so don't add.
8394 if (IsRecursive && !E.Str.empty()) {
8395 assert(E.State==Recursive && E.Str.size() == Str.size() &&
8396 "This is not the same Recursive entry");
8397 // The parent container was not recursive after all, so we could have used
8398 // this Recursive sub-member entry after all, but we assumed the worse when
8399 // we started viz: IncompleteCount!=0.
8402 assert(E.Str.empty() && "Entry already present");
8404 E.State = IsRecursive? Recursive : NonRecursive;
8407 /// Return a cached TypeString encoding for the ID. If there isn't one, or we
8408 /// are recursively expanding a type (IncompleteCount != 0) and the cached
8409 /// encoding is Recursive, return an empty StringRef.
8410 StringRef TypeStringCache::lookupStr(const IdentifierInfo *ID) {
8412 return StringRef(); // We have no key.
8413 auto I = Map.find(ID);
8415 return StringRef(); // We have no encoding.
8416 Entry &E = I->second;
8417 if (E.State == Recursive && IncompleteCount)
8418 return StringRef(); // We don't use Recursive encodings for member types.
8420 if (E.State == Incomplete) {
8421 // The incomplete type is being used to break out of recursion.
8422 E.State = IncompleteUsed;
8423 ++IncompleteUsedCount;
8428 /// The XCore ABI includes a type information section that communicates symbol
8429 /// type information to the linker. The linker uses this information to verify
8430 /// safety/correctness of things such as array bound and pointers et al.
8431 /// The ABI only requires C (and XC) language modules to emit TypeStrings.
8432 /// This type information (TypeString) is emitted into meta data for all global
8433 /// symbols: definitions, declarations, functions & variables.
8435 /// The TypeString carries type, qualifier, name, size & value details.
8436 /// Please see 'Tools Development Guide' section 2.16.2 for format details:
8437 /// https://www.xmos.com/download/public/Tools-Development-Guide%28X9114A%29.pdf
8438 /// The output is tested by test/CodeGen/xcore-stringtype.c.
8440 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
8441 CodeGen::CodeGenModule &CGM, TypeStringCache &TSC);
8443 /// XCore uses emitTargetMD to emit TypeString metadata for global symbols.
8444 void XCoreTargetCodeGenInfo::emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
8445 CodeGen::CodeGenModule &CGM) const {
8447 if (getTypeString(Enc, D, CGM, TSC)) {
8448 llvm::LLVMContext &Ctx = CGM.getModule().getContext();
8449 llvm::Metadata *MDVals[] = {llvm::ConstantAsMetadata::get(GV),
8450 llvm::MDString::get(Ctx, Enc.str())};
8451 llvm::NamedMDNode *MD =
8452 CGM.getModule().getOrInsertNamedMetadata("xcore.typestrings");
8453 MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
8457 //===----------------------------------------------------------------------===//
8458 // SPIR ABI Implementation
8459 //===----------------------------------------------------------------------===//
8462 class SPIRTargetCodeGenInfo : public TargetCodeGenInfo {
8464 SPIRTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
8465 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
8466 unsigned getOpenCLKernelCallingConv() const override;
8469 } // End anonymous namespace.
8473 void computeSPIRKernelABIInfo(CodeGenModule &CGM, CGFunctionInfo &FI) {
8474 DefaultABIInfo SPIRABI(CGM.getTypes());
8475 SPIRABI.computeInfo(FI);
8480 unsigned SPIRTargetCodeGenInfo::getOpenCLKernelCallingConv() const {
8481 return llvm::CallingConv::SPIR_KERNEL;
8484 static bool appendType(SmallStringEnc &Enc, QualType QType,
8485 const CodeGen::CodeGenModule &CGM,
8486 TypeStringCache &TSC);
8488 /// Helper function for appendRecordType().
8489 /// Builds a SmallVector containing the encoded field types in declaration
8491 static bool extractFieldType(SmallVectorImpl<FieldEncoding> &FE,
8492 const RecordDecl *RD,
8493 const CodeGen::CodeGenModule &CGM,
8494 TypeStringCache &TSC) {
8495 for (const auto *Field : RD->fields()) {
8498 Enc += Field->getName();
8500 if (Field->isBitField()) {
8502 llvm::raw_svector_ostream OS(Enc);
8503 OS << Field->getBitWidthValue(CGM.getContext());
8506 if (!appendType(Enc, Field->getType(), CGM, TSC))
8508 if (Field->isBitField())
8511 FE.emplace_back(!Field->getName().empty(), Enc);
8516 /// Appends structure and union types to Enc and adds encoding to cache.
8517 /// Recursively calls appendType (via extractFieldType) for each field.
8518 /// Union types have their fields ordered according to the ABI.
8519 static bool appendRecordType(SmallStringEnc &Enc, const RecordType *RT,
8520 const CodeGen::CodeGenModule &CGM,
8521 TypeStringCache &TSC, const IdentifierInfo *ID) {
8522 // Append the cached TypeString if we have one.
8523 StringRef TypeString = TSC.lookupStr(ID);
8524 if (!TypeString.empty()) {
8529 // Start to emit an incomplete TypeString.
8530 size_t Start = Enc.size();
8531 Enc += (RT->isUnionType()? 'u' : 's');
8534 Enc += ID->getName();
8537 // We collect all encoded fields and order as necessary.
8538 bool IsRecursive = false;
8539 const RecordDecl *RD = RT->getDecl()->getDefinition();
8540 if (RD && !RD->field_empty()) {
8541 // An incomplete TypeString stub is placed in the cache for this RecordType
8542 // so that recursive calls to this RecordType will use it whilst building a
8543 // complete TypeString for this RecordType.
8544 SmallVector<FieldEncoding, 16> FE;
8545 std::string StubEnc(Enc.substr(Start).str());
8546 StubEnc += '}'; // StubEnc now holds a valid incomplete TypeString.
8547 TSC.addIncomplete(ID, std::move(StubEnc));
8548 if (!extractFieldType(FE, RD, CGM, TSC)) {
8549 (void) TSC.removeIncomplete(ID);
8552 IsRecursive = TSC.removeIncomplete(ID);
8553 // The ABI requires unions to be sorted but not structures.
8554 // See FieldEncoding::operator< for sort algorithm.
8555 if (RT->isUnionType())
8556 llvm::sort(FE.begin(), FE.end());
8557 // We can now complete the TypeString.
8558 unsigned E = FE.size();
8559 for (unsigned I = 0; I != E; ++I) {
8566 TSC.addIfComplete(ID, Enc.substr(Start), IsRecursive);
8570 /// Appends enum types to Enc and adds the encoding to the cache.
8571 static bool appendEnumType(SmallStringEnc &Enc, const EnumType *ET,
8572 TypeStringCache &TSC,
8573 const IdentifierInfo *ID) {
8574 // Append the cached TypeString if we have one.
8575 StringRef TypeString = TSC.lookupStr(ID);
8576 if (!TypeString.empty()) {
8581 size_t Start = Enc.size();
8584 Enc += ID->getName();
8587 // We collect all encoded enumerations and order them alphanumerically.
8588 if (const EnumDecl *ED = ET->getDecl()->getDefinition()) {
8589 SmallVector<FieldEncoding, 16> FE;
8590 for (auto I = ED->enumerator_begin(), E = ED->enumerator_end(); I != E;
8592 SmallStringEnc EnumEnc;
8594 EnumEnc += I->getName();
8596 I->getInitVal().toString(EnumEnc);
8598 FE.push_back(FieldEncoding(!I->getName().empty(), EnumEnc));
8600 llvm::sort(FE.begin(), FE.end());
8601 unsigned E = FE.size();
8602 for (unsigned I = 0; I != E; ++I) {
8609 TSC.addIfComplete(ID, Enc.substr(Start), false);
8613 /// Appends type's qualifier to Enc.
8614 /// This is done prior to appending the type's encoding.
8615 static void appendQualifier(SmallStringEnc &Enc, QualType QT) {
8616 // Qualifiers are emitted in alphabetical order.
8617 static const char *const Table[]={"","c:","r:","cr:","v:","cv:","rv:","crv:"};
8619 if (QT.isConstQualified())
8621 if (QT.isRestrictQualified())
8623 if (QT.isVolatileQualified())
8625 Enc += Table[Lookup];
8628 /// Appends built-in types to Enc.
8629 static bool appendBuiltinType(SmallStringEnc &Enc, const BuiltinType *BT) {
8630 const char *EncType;
8631 switch (BT->getKind()) {
8632 case BuiltinType::Void:
8635 case BuiltinType::Bool:
8638 case BuiltinType::Char_U:
8641 case BuiltinType::UChar:
8644 case BuiltinType::SChar:
8647 case BuiltinType::UShort:
8650 case BuiltinType::Short:
8653 case BuiltinType::UInt:
8656 case BuiltinType::Int:
8659 case BuiltinType::ULong:
8662 case BuiltinType::Long:
8665 case BuiltinType::ULongLong:
8668 case BuiltinType::LongLong:
8671 case BuiltinType::Float:
8674 case BuiltinType::Double:
8677 case BuiltinType::LongDouble:
8687 /// Appends a pointer encoding to Enc before calling appendType for the pointee.
8688 static bool appendPointerType(SmallStringEnc &Enc, const PointerType *PT,
8689 const CodeGen::CodeGenModule &CGM,
8690 TypeStringCache &TSC) {
8692 if (!appendType(Enc, PT->getPointeeType(), CGM, TSC))
8698 /// Appends array encoding to Enc before calling appendType for the element.
8699 static bool appendArrayType(SmallStringEnc &Enc, QualType QT,
8700 const ArrayType *AT,
8701 const CodeGen::CodeGenModule &CGM,
8702 TypeStringCache &TSC, StringRef NoSizeEnc) {
8703 if (AT->getSizeModifier() != ArrayType::Normal)
8706 if (const ConstantArrayType *CAT = dyn_cast<ConstantArrayType>(AT))
8707 CAT->getSize().toStringUnsigned(Enc);
8709 Enc += NoSizeEnc; // Global arrays use "*", otherwise it is "".
8711 // The Qualifiers should be attached to the type rather than the array.
8712 appendQualifier(Enc, QT);
8713 if (!appendType(Enc, AT->getElementType(), CGM, TSC))
8719 /// Appends a function encoding to Enc, calling appendType for the return type
8720 /// and the arguments.
8721 static bool appendFunctionType(SmallStringEnc &Enc, const FunctionType *FT,
8722 const CodeGen::CodeGenModule &CGM,
8723 TypeStringCache &TSC) {
8725 if (!appendType(Enc, FT->getReturnType(), CGM, TSC))
8728 if (const FunctionProtoType *FPT = FT->getAs<FunctionProtoType>()) {
8729 // N.B. we are only interested in the adjusted param types.
8730 auto I = FPT->param_type_begin();
8731 auto E = FPT->param_type_end();
8734 if (!appendType(Enc, *I, CGM, TSC))
8740 if (FPT->isVariadic())
8743 if (FPT->isVariadic())
8753 /// Handles the type's qualifier before dispatching a call to handle specific
8755 static bool appendType(SmallStringEnc &Enc, QualType QType,
8756 const CodeGen::CodeGenModule &CGM,
8757 TypeStringCache &TSC) {
8759 QualType QT = QType.getCanonicalType();
8761 if (const ArrayType *AT = QT->getAsArrayTypeUnsafe())
8762 // The Qualifiers should be attached to the type rather than the array.
8763 // Thus we don't call appendQualifier() here.
8764 return appendArrayType(Enc, QT, AT, CGM, TSC, "");
8766 appendQualifier(Enc, QT);
8768 if (const BuiltinType *BT = QT->getAs<BuiltinType>())
8769 return appendBuiltinType(Enc, BT);
8771 if (const PointerType *PT = QT->getAs<PointerType>())
8772 return appendPointerType(Enc, PT, CGM, TSC);
8774 if (const EnumType *ET = QT->getAs<EnumType>())
8775 return appendEnumType(Enc, ET, TSC, QT.getBaseTypeIdentifier());
8777 if (const RecordType *RT = QT->getAsStructureType())
8778 return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
8780 if (const RecordType *RT = QT->getAsUnionType())
8781 return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
8783 if (const FunctionType *FT = QT->getAs<FunctionType>())
8784 return appendFunctionType(Enc, FT, CGM, TSC);
8789 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
8790 CodeGen::CodeGenModule &CGM, TypeStringCache &TSC) {
8794 if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) {
8795 if (FD->getLanguageLinkage() != CLanguageLinkage)
8797 return appendType(Enc, FD->getType(), CGM, TSC);
8800 if (const VarDecl *VD = dyn_cast<VarDecl>(D)) {
8801 if (VD->getLanguageLinkage() != CLanguageLinkage)
8803 QualType QT = VD->getType().getCanonicalType();
8804 if (const ArrayType *AT = QT->getAsArrayTypeUnsafe()) {
8805 // Global ArrayTypes are given a size of '*' if the size is unknown.
8806 // The Qualifiers should be attached to the type rather than the array.
8807 // Thus we don't call appendQualifier() here.
8808 return appendArrayType(Enc, QT, AT, CGM, TSC, "*");
8810 return appendType(Enc, QT, CGM, TSC);
8815 //===----------------------------------------------------------------------===//
8816 // RISCV ABI Implementation
8817 //===----------------------------------------------------------------------===//
8820 class RISCVABIInfo : public DefaultABIInfo {
8822 unsigned XLen; // Size of the integer ('x') registers in bits.
8823 static const int NumArgGPRs = 8;
8826 RISCVABIInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen)
8827 : DefaultABIInfo(CGT), XLen(XLen) {}
8829 // DefaultABIInfo's classifyReturnType and classifyArgumentType are
8830 // non-virtual, but computeInfo is virtual, so we overload it.
8831 void computeInfo(CGFunctionInfo &FI) const override;
8833 ABIArgInfo classifyArgumentType(QualType Ty, bool IsFixed,
8834 int &ArgGPRsLeft) const;
8835 ABIArgInfo classifyReturnType(QualType RetTy) const;
8837 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8838 QualType Ty) const override;
8840 ABIArgInfo extendType(QualType Ty) const;
8842 } // end anonymous namespace
8844 void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const {
8845 QualType RetTy = FI.getReturnType();
8846 if (!getCXXABI().classifyReturnType(FI))
8847 FI.getReturnInfo() = classifyReturnType(RetTy);
8849 // IsRetIndirect is true if classifyArgumentType indicated the value should
8850 // be passed indirect or if the type size is greater than 2*xlen. e.g. fp128
8851 // is passed direct in LLVM IR, relying on the backend lowering code to
8852 // rewrite the argument list and pass indirectly on RV32.
8853 bool IsRetIndirect = FI.getReturnInfo().getKind() == ABIArgInfo::Indirect ||
8854 getContext().getTypeSize(RetTy) > (2 * XLen);
8856 // We must track the number of GPRs used in order to conform to the RISC-V
8857 // ABI, as integer scalars passed in registers should have signext/zeroext
8858 // when promoted, but are anyext if passed on the stack. As GPR usage is
8859 // different for variadic arguments, we must also track whether we are
8860 // examining a vararg or not.
8861 int ArgGPRsLeft = IsRetIndirect ? NumArgGPRs - 1 : NumArgGPRs;
8862 int NumFixedArgs = FI.getNumRequiredArgs();
8865 for (auto &ArgInfo : FI.arguments()) {
8866 bool IsFixed = ArgNum < NumFixedArgs;
8867 ArgInfo.info = classifyArgumentType(ArgInfo.type, IsFixed, ArgGPRsLeft);
8872 ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed,
8873 int &ArgGPRsLeft) const {
8874 assert(ArgGPRsLeft <= NumArgGPRs && "Arg GPR tracking underflow");
8875 Ty = useFirstFieldIfTransparentUnion(Ty);
8877 // Structures with either a non-trivial destructor or a non-trivial
8878 // copy constructor are always passed indirectly.
8879 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
8882 return getNaturalAlignIndirect(Ty, /*ByVal=*/RAA ==
8883 CGCXXABI::RAA_DirectInMemory);
8886 // Ignore empty structs/unions.
8887 if (isEmptyRecord(getContext(), Ty, true))
8888 return ABIArgInfo::getIgnore();
8890 uint64_t Size = getContext().getTypeSize(Ty);
8891 uint64_t NeededAlign = getContext().getTypeAlign(Ty);
8892 bool MustUseStack = false;
8893 // Determine the number of GPRs needed to pass the current argument
8894 // according to the ABI. 2*XLen-aligned varargs are passed in "aligned"
8895 // register pairs, so may consume 3 registers.
8896 int NeededArgGPRs = 1;
8897 if (!IsFixed && NeededAlign == 2 * XLen)
8898 NeededArgGPRs = 2 + (ArgGPRsLeft % 2);
8899 else if (Size > XLen && Size <= 2 * XLen)
8902 if (NeededArgGPRs > ArgGPRsLeft) {
8903 MustUseStack = true;
8904 NeededArgGPRs = ArgGPRsLeft;
8907 ArgGPRsLeft -= NeededArgGPRs;
8909 if (!isAggregateTypeForABI(Ty) && !Ty->isVectorType()) {
8910 // Treat an enum type as its underlying type.
8911 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
8912 Ty = EnumTy->getDecl()->getIntegerType();
8914 // All integral types are promoted to XLen width, unless passed on the
8916 if (Size < XLen && Ty->isIntegralOrEnumerationType() && !MustUseStack) {
8917 return extendType(Ty);
8920 return ABIArgInfo::getDirect();
8923 // Aggregates which are <= 2*XLen will be passed in registers if possible,
8924 // so coerce to integers.
8925 if (Size <= 2 * XLen) {
8926 unsigned Alignment = getContext().getTypeAlign(Ty);
8928 // Use a single XLen int if possible, 2*XLen if 2*XLen alignment is
8929 // required, and a 2-element XLen array if only XLen alignment is required.
8931 return ABIArgInfo::getDirect(
8932 llvm::IntegerType::get(getVMContext(), XLen));
8933 } else if (Alignment == 2 * XLen) {
8934 return ABIArgInfo::getDirect(
8935 llvm::IntegerType::get(getVMContext(), 2 * XLen));
8937 return ABIArgInfo::getDirect(llvm::ArrayType::get(
8938 llvm::IntegerType::get(getVMContext(), XLen), 2));
8941 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
8944 ABIArgInfo RISCVABIInfo::classifyReturnType(QualType RetTy) const {
8945 if (RetTy->isVoidType())
8946 return ABIArgInfo::getIgnore();
8948 int ArgGPRsLeft = 2;
8950 // The rules for return and argument types are the same, so defer to
8951 // classifyArgumentType.
8952 return classifyArgumentType(RetTy, /*IsFixed=*/true, ArgGPRsLeft);
8955 Address RISCVABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8956 QualType Ty) const {
8957 CharUnits SlotSize = CharUnits::fromQuantity(XLen / 8);
8959 // Empty records are ignored for parameter passing purposes.
8960 if (isEmptyRecord(getContext(), Ty, true)) {
8961 Address Addr(CGF.Builder.CreateLoad(VAListAddr), SlotSize);
8962 Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
8966 std::pair<CharUnits, CharUnits> SizeAndAlign =
8967 getContext().getTypeInfoInChars(Ty);
8969 // Arguments bigger than 2*Xlen bytes are passed indirectly.
8970 bool IsIndirect = SizeAndAlign.first > 2 * SlotSize;
8972 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, SizeAndAlign,
8973 SlotSize, /*AllowHigherAlign=*/true);
8976 ABIArgInfo RISCVABIInfo::extendType(QualType Ty) const {
8977 int TySize = getContext().getTypeSize(Ty);
8978 // RV64 ABI requires unsigned 32 bit integers to be sign extended.
8979 if (XLen == 64 && Ty->isUnsignedIntegerOrEnumerationType() && TySize == 32)
8980 return ABIArgInfo::getSignExtend(Ty);
8981 return ABIArgInfo::getExtend(Ty);
8985 class RISCVTargetCodeGenInfo : public TargetCodeGenInfo {
8987 RISCVTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen)
8988 : TargetCodeGenInfo(new RISCVABIInfo(CGT, XLen)) {}
8990 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
8991 CodeGen::CodeGenModule &CGM) const override {
8992 const auto *FD = dyn_cast_or_null<FunctionDecl>(D);
8995 const auto *Attr = FD->getAttr<RISCVInterruptAttr>();
9000 switch (Attr->getInterrupt()) {
9001 case RISCVInterruptAttr::user: Kind = "user"; break;
9002 case RISCVInterruptAttr::supervisor: Kind = "supervisor"; break;
9003 case RISCVInterruptAttr::machine: Kind = "machine"; break;
9006 auto *Fn = cast<llvm::Function>(GV);
9008 Fn->addFnAttr("interrupt", Kind);
9013 //===----------------------------------------------------------------------===//
9015 //===----------------------------------------------------------------------===//
9017 bool CodeGenModule::supportsCOMDAT() const {
9018 return getTriple().supportsCOMDAT();
9021 const TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() {
9022 if (TheTargetCodeGenInfo)
9023 return *TheTargetCodeGenInfo;
9025 // Helper to set the unique_ptr while still keeping the return value.
9026 auto SetCGInfo = [&](TargetCodeGenInfo *P) -> const TargetCodeGenInfo & {
9027 this->TheTargetCodeGenInfo.reset(P);
9031 const llvm::Triple &Triple = getTarget().getTriple();
9032 switch (Triple.getArch()) {
9034 return SetCGInfo(new DefaultTargetCodeGenInfo(Types));
9036 case llvm::Triple::le32:
9037 return SetCGInfo(new PNaClTargetCodeGenInfo(Types));
9038 case llvm::Triple::mips:
9039 case llvm::Triple::mipsel:
9040 if (Triple.getOS() == llvm::Triple::NaCl)
9041 return SetCGInfo(new PNaClTargetCodeGenInfo(Types));
9042 return SetCGInfo(new MIPSTargetCodeGenInfo(Types, true));
9044 case llvm::Triple::mips64:
9045 case llvm::Triple::mips64el:
9046 return SetCGInfo(new MIPSTargetCodeGenInfo(Types, false));
9048 case llvm::Triple::avr:
9049 return SetCGInfo(new AVRTargetCodeGenInfo(Types));
9051 case llvm::Triple::aarch64:
9052 case llvm::Triple::aarch64_be: {
9053 AArch64ABIInfo::ABIKind Kind = AArch64ABIInfo::AAPCS;
9054 if (getTarget().getABI() == "darwinpcs")
9055 Kind = AArch64ABIInfo::DarwinPCS;
9056 else if (Triple.isOSWindows())
9058 new WindowsAArch64TargetCodeGenInfo(Types, AArch64ABIInfo::Win64));
9060 return SetCGInfo(new AArch64TargetCodeGenInfo(Types, Kind));
9063 case llvm::Triple::wasm32:
9064 case llvm::Triple::wasm64:
9065 return SetCGInfo(new WebAssemblyTargetCodeGenInfo(Types));
9067 case llvm::Triple::arm:
9068 case llvm::Triple::armeb:
9069 case llvm::Triple::thumb:
9070 case llvm::Triple::thumbeb: {
9071 if (Triple.getOS() == llvm::Triple::Win32) {
9073 new WindowsARMTargetCodeGenInfo(Types, ARMABIInfo::AAPCS_VFP));
9076 ARMABIInfo::ABIKind Kind = ARMABIInfo::AAPCS;
9077 StringRef ABIStr = getTarget().getABI();
9078 if (ABIStr == "apcs-gnu")
9079 Kind = ARMABIInfo::APCS;
9080 else if (ABIStr == "aapcs16")
9081 Kind = ARMABIInfo::AAPCS16_VFP;
9082 else if (CodeGenOpts.FloatABI == "hard" ||
9083 (CodeGenOpts.FloatABI != "soft" &&
9084 (Triple.getEnvironment() == llvm::Triple::GNUEABIHF ||
9085 Triple.getEnvironment() == llvm::Triple::MuslEABIHF ||
9086 Triple.getEnvironment() == llvm::Triple::EABIHF)))
9087 Kind = ARMABIInfo::AAPCS_VFP;
9089 return SetCGInfo(new ARMTargetCodeGenInfo(Types, Kind));
9092 case llvm::Triple::ppc:
9094 new PPC32TargetCodeGenInfo(Types, CodeGenOpts.FloatABI == "soft"));
9095 case llvm::Triple::ppc64:
9096 if (Triple.isOSBinFormatELF()) {
9097 PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv1;
9098 if (getTarget().getABI() == "elfv2")
9099 Kind = PPC64_SVR4_ABIInfo::ELFv2;
9100 bool HasQPX = getTarget().getABI() == "elfv1-qpx";
9101 bool IsSoftFloat = CodeGenOpts.FloatABI == "soft";
9103 return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX,
9106 return SetCGInfo(new PPC64TargetCodeGenInfo(Types));
9107 case llvm::Triple::ppc64le: {
9108 assert(Triple.isOSBinFormatELF() && "PPC64 LE non-ELF not supported!");
9109 PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv2;
9110 if (getTarget().getABI() == "elfv1" || getTarget().getABI() == "elfv1-qpx")
9111 Kind = PPC64_SVR4_ABIInfo::ELFv1;
9112 bool HasQPX = getTarget().getABI() == "elfv1-qpx";
9113 bool IsSoftFloat = CodeGenOpts.FloatABI == "soft";
9115 return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX,
9119 case llvm::Triple::nvptx:
9120 case llvm::Triple::nvptx64:
9121 return SetCGInfo(new NVPTXTargetCodeGenInfo(Types));
9123 case llvm::Triple::msp430:
9124 return SetCGInfo(new MSP430TargetCodeGenInfo(Types));
9126 case llvm::Triple::riscv32:
9127 return SetCGInfo(new RISCVTargetCodeGenInfo(Types, 32));
9128 case llvm::Triple::riscv64:
9129 return SetCGInfo(new RISCVTargetCodeGenInfo(Types, 64));
9131 case llvm::Triple::systemz: {
9132 bool HasVector = getTarget().getABI() == "vector";
9133 return SetCGInfo(new SystemZTargetCodeGenInfo(Types, HasVector));
9136 case llvm::Triple::tce:
9137 case llvm::Triple::tcele:
9138 return SetCGInfo(new TCETargetCodeGenInfo(Types));
9140 case llvm::Triple::x86: {
9141 bool IsDarwinVectorABI = Triple.isOSDarwin();
9142 bool RetSmallStructInRegABI =
9143 X86_32TargetCodeGenInfo::isStructReturnInRegABI(Triple, CodeGenOpts);
9144 bool IsWin32FloatStructABI = Triple.isOSWindows() && !Triple.isOSCygMing();
9146 if (Triple.getOS() == llvm::Triple::Win32) {
9147 return SetCGInfo(new WinX86_32TargetCodeGenInfo(
9148 Types, IsDarwinVectorABI, RetSmallStructInRegABI,
9149 IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters));
9151 return SetCGInfo(new X86_32TargetCodeGenInfo(
9152 Types, IsDarwinVectorABI, RetSmallStructInRegABI,
9153 IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters,
9154 CodeGenOpts.FloatABI == "soft"));
9158 case llvm::Triple::x86_64: {
9159 StringRef ABI = getTarget().getABI();
9160 X86AVXABILevel AVXLevel =
9162 ? X86AVXABILevel::AVX512
9163 : ABI == "avx" ? X86AVXABILevel::AVX : X86AVXABILevel::None);
9165 switch (Triple.getOS()) {
9166 case llvm::Triple::Win32:
9167 return SetCGInfo(new WinX86_64TargetCodeGenInfo(Types, AVXLevel));
9168 case llvm::Triple::PS4:
9169 return SetCGInfo(new PS4TargetCodeGenInfo(Types, AVXLevel));
9171 return SetCGInfo(new X86_64TargetCodeGenInfo(Types, AVXLevel));
9174 case llvm::Triple::hexagon:
9175 return SetCGInfo(new HexagonTargetCodeGenInfo(Types));
9176 case llvm::Triple::lanai:
9177 return SetCGInfo(new LanaiTargetCodeGenInfo(Types));
9178 case llvm::Triple::r600:
9179 return SetCGInfo(new AMDGPUTargetCodeGenInfo(Types));
9180 case llvm::Triple::amdgcn:
9181 return SetCGInfo(new AMDGPUTargetCodeGenInfo(Types));
9182 case llvm::Triple::sparc:
9183 return SetCGInfo(new SparcV8TargetCodeGenInfo(Types));
9184 case llvm::Triple::sparcv9:
9185 return SetCGInfo(new SparcV9TargetCodeGenInfo(Types));
9186 case llvm::Triple::xcore:
9187 return SetCGInfo(new XCoreTargetCodeGenInfo(Types));
9188 case llvm::Triple::spir:
9189 case llvm::Triple::spir64:
9190 return SetCGInfo(new SPIRTargetCodeGenInfo(Types));
9194 /// Create an OpenCL kernel for an enqueued block.
9196 /// The kernel has the same function type as the block invoke function. Its
9197 /// name is the name of the block invoke function postfixed with "_kernel".
9198 /// It simply calls the block invoke function then returns.
9200 TargetCodeGenInfo::createEnqueuedBlockKernel(CodeGenFunction &CGF,
9201 llvm::Function *Invoke,
9202 llvm::Value *BlockLiteral) const {
9203 auto *InvokeFT = Invoke->getFunctionType();
9204 llvm::SmallVector<llvm::Type *, 2> ArgTys;
9205 for (auto &P : InvokeFT->params())
9206 ArgTys.push_back(P);
9207 auto &C = CGF.getLLVMContext();
9208 std::string Name = Invoke->getName().str() + "_kernel";
9209 auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false);
9210 auto *F = llvm::Function::Create(FT, llvm::GlobalValue::InternalLinkage, Name,
9211 &CGF.CGM.getModule());
9212 auto IP = CGF.Builder.saveIP();
9213 auto *BB = llvm::BasicBlock::Create(C, "entry", F);
9214 auto &Builder = CGF.Builder;
9215 Builder.SetInsertPoint(BB);
9216 llvm::SmallVector<llvm::Value *, 2> Args;
9217 for (auto &A : F->args())
9219 Builder.CreateCall(Invoke, Args);
9220 Builder.CreateRetVoid();
9221 Builder.restoreIP(IP);
9225 /// Create an OpenCL kernel for an enqueued block.
9227 /// The type of the first argument (the block literal) is the struct type
9228 /// of the block literal instead of a pointer type. The first argument
9229 /// (block literal) is passed directly by value to the kernel. The kernel
9230 /// allocates the same type of struct on stack and stores the block literal
9231 /// to it and passes its pointer to the block invoke function. The kernel
9232 /// has "enqueued-block" function attribute and kernel argument metadata.
9233 llvm::Function *AMDGPUTargetCodeGenInfo::createEnqueuedBlockKernel(
9234 CodeGenFunction &CGF, llvm::Function *Invoke,
9235 llvm::Value *BlockLiteral) const {
9236 auto &Builder = CGF.Builder;
9237 auto &C = CGF.getLLVMContext();
9239 auto *BlockTy = BlockLiteral->getType()->getPointerElementType();
9240 auto *InvokeFT = Invoke->getFunctionType();
9241 llvm::SmallVector<llvm::Type *, 2> ArgTys;
9242 llvm::SmallVector<llvm::Metadata *, 8> AddressQuals;
9243 llvm::SmallVector<llvm::Metadata *, 8> AccessQuals;
9244 llvm::SmallVector<llvm::Metadata *, 8> ArgTypeNames;
9245 llvm::SmallVector<llvm::Metadata *, 8> ArgBaseTypeNames;
9246 llvm::SmallVector<llvm::Metadata *, 8> ArgTypeQuals;
9247 llvm::SmallVector<llvm::Metadata *, 8> ArgNames;
9249 ArgTys.push_back(BlockTy);
9250 ArgTypeNames.push_back(llvm::MDString::get(C, "__block_literal"));
9251 AddressQuals.push_back(llvm::ConstantAsMetadata::get(Builder.getInt32(0)));
9252 ArgBaseTypeNames.push_back(llvm::MDString::get(C, "__block_literal"));
9253 ArgTypeQuals.push_back(llvm::MDString::get(C, ""));
9254 AccessQuals.push_back(llvm::MDString::get(C, "none"));
9255 ArgNames.push_back(llvm::MDString::get(C, "block_literal"));
9256 for (unsigned I = 1, E = InvokeFT->getNumParams(); I < E; ++I) {
9257 ArgTys.push_back(InvokeFT->getParamType(I));
9258 ArgTypeNames.push_back(llvm::MDString::get(C, "void*"));
9259 AddressQuals.push_back(llvm::ConstantAsMetadata::get(Builder.getInt32(3)));
9260 AccessQuals.push_back(llvm::MDString::get(C, "none"));
9261 ArgBaseTypeNames.push_back(llvm::MDString::get(C, "void*"));
9262 ArgTypeQuals.push_back(llvm::MDString::get(C, ""));
9264 llvm::MDString::get(C, (Twine("local_arg") + Twine(I)).str()));
9266 std::string Name = Invoke->getName().str() + "_kernel";
9267 auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false);
9268 auto *F = llvm::Function::Create(FT, llvm::GlobalValue::InternalLinkage, Name,
9269 &CGF.CGM.getModule());
9270 F->addFnAttr("enqueued-block");
9271 auto IP = CGF.Builder.saveIP();
9272 auto *BB = llvm::BasicBlock::Create(C, "entry", F);
9273 Builder.SetInsertPoint(BB);
9274 unsigned BlockAlign = CGF.CGM.getDataLayout().getPrefTypeAlignment(BlockTy);
9275 auto *BlockPtr = Builder.CreateAlloca(BlockTy, nullptr);
9276 BlockPtr->setAlignment(BlockAlign);
9277 Builder.CreateAlignedStore(F->arg_begin(), BlockPtr, BlockAlign);
9278 auto *Cast = Builder.CreatePointerCast(BlockPtr, InvokeFT->getParamType(0));
9279 llvm::SmallVector<llvm::Value *, 2> Args;
9280 Args.push_back(Cast);
9281 for (auto I = F->arg_begin() + 1, E = F->arg_end(); I != E; ++I)
9283 Builder.CreateCall(Invoke, Args);
9284 Builder.CreateRetVoid();
9285 Builder.restoreIP(IP);
9287 F->setMetadata("kernel_arg_addr_space", llvm::MDNode::get(C, AddressQuals));
9288 F->setMetadata("kernel_arg_access_qual", llvm::MDNode::get(C, AccessQuals));
9289 F->setMetadata("kernel_arg_type", llvm::MDNode::get(C, ArgTypeNames));
9290 F->setMetadata("kernel_arg_base_type",
9291 llvm::MDNode::get(C, ArgBaseTypeNames));
9292 F->setMetadata("kernel_arg_type_qual", llvm::MDNode::get(C, ArgTypeQuals));
9293 if (CGF.CGM.getCodeGenOpts().EmitOpenCLArgMetadata)
9294 F->setMetadata("kernel_arg_name", llvm::MDNode::get(C, ArgNames));