1 //===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // These classes wrap the information about a call or function
11 // definition used to handle ABI compliancy.
13 //===----------------------------------------------------------------------===//
15 #include "TargetInfo.h"
19 #include "CodeGenFunction.h"
20 #include "clang/AST/RecordLayout.h"
21 #include "clang/CodeGen/CGFunctionInfo.h"
22 #include "clang/CodeGen/SwiftCallingConv.h"
23 #include "clang/Frontend/CodeGenOptions.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/Triple.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Type.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include <algorithm> // std::sort
31 using namespace clang;
32 using namespace CodeGen;
34 static void AssignToArrayRange(CodeGen::CGBuilderTy &Builder,
39 // Alternatively, we could emit this as a loop in the source.
40 for (unsigned I = FirstIndex; I <= LastIndex; ++I) {
42 Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I);
43 Builder.CreateAlignedStore(Value, Cell, CharUnits::One());
47 static bool isAggregateTypeForABI(QualType T) {
48 return !CodeGenFunction::hasScalarEvaluationKind(T) ||
49 T->isMemberFunctionPointerType();
53 ABIInfo::getNaturalAlignIndirect(QualType Ty, bool ByRef, bool Realign,
54 llvm::Type *Padding) const {
55 return ABIArgInfo::getIndirect(getContext().getTypeAlignInChars(Ty),
56 ByRef, Realign, Padding);
60 ABIInfo::getNaturalAlignIndirectInReg(QualType Ty, bool Realign) const {
61 return ABIArgInfo::getIndirectInReg(getContext().getTypeAlignInChars(Ty),
62 /*ByRef*/ false, Realign);
65 Address ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
67 return Address::invalid();
70 ABIInfo::~ABIInfo() {}
72 /// Does the given lowering require more than the given number of
73 /// registers when expanded?
75 /// This is intended to be the basis of a reasonable basic implementation
76 /// of should{Pass,Return}IndirectlyForSwift.
78 /// For most targets, a limit of four total registers is reasonable; this
79 /// limits the amount of code required in order to move around the value
80 /// in case it wasn't produced immediately prior to the call by the caller
81 /// (or wasn't produced in exactly the right registers) or isn't used
82 /// immediately within the callee. But some targets may need to further
83 /// limit the register count due to an inability to support that many
85 static bool occupiesMoreThan(CodeGenTypes &cgt,
86 ArrayRef<llvm::Type*> scalarTypes,
87 unsigned maxAllRegisters) {
88 unsigned intCount = 0, fpCount = 0;
89 for (llvm::Type *type : scalarTypes) {
90 if (type->isPointerTy()) {
92 } else if (auto intTy = dyn_cast<llvm::IntegerType>(type)) {
93 auto ptrWidth = cgt.getTarget().getPointerWidth(0);
94 intCount += (intTy->getBitWidth() + ptrWidth - 1) / ptrWidth;
96 assert(type->isVectorTy() || type->isFloatingPointTy());
101 return (intCount + fpCount > maxAllRegisters);
104 bool SwiftABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize,
106 unsigned numElts) const {
107 // The default implementation of this assumes that the target guarantees
108 // 128-bit SIMD support but nothing more.
109 return (vectorSize.getQuantity() > 8 && vectorSize.getQuantity() <= 16);
112 static CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT,
114 const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl());
116 return CGCXXABI::RAA_Default;
117 return CXXABI.getRecordArgABI(RD);
120 static CGCXXABI::RecordArgABI getRecordArgABI(QualType T,
122 const RecordType *RT = T->getAs<RecordType>();
124 return CGCXXABI::RAA_Default;
125 return getRecordArgABI(RT, CXXABI);
128 /// Pass transparent unions as if they were the type of the first element. Sema
129 /// should ensure that all elements of the union have the same "machine type".
130 static QualType useFirstFieldIfTransparentUnion(QualType Ty) {
131 if (const RecordType *UT = Ty->getAsUnionType()) {
132 const RecordDecl *UD = UT->getDecl();
133 if (UD->hasAttr<TransparentUnionAttr>()) {
134 assert(!UD->field_empty() && "sema created an empty transparent union");
135 return UD->field_begin()->getType();
141 CGCXXABI &ABIInfo::getCXXABI() const {
142 return CGT.getCXXABI();
145 ASTContext &ABIInfo::getContext() const {
146 return CGT.getContext();
149 llvm::LLVMContext &ABIInfo::getVMContext() const {
150 return CGT.getLLVMContext();
153 const llvm::DataLayout &ABIInfo::getDataLayout() const {
154 return CGT.getDataLayout();
157 const TargetInfo &ABIInfo::getTarget() const {
158 return CGT.getTarget();
161 bool ABIInfo:: isAndroid() const { return getTarget().getTriple().isAndroid(); }
163 bool ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
167 bool ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
168 uint64_t Members) const {
172 bool ABIInfo::shouldSignExtUnsignedType(QualType Ty) const {
176 LLVM_DUMP_METHOD void ABIArgInfo::dump() const {
177 raw_ostream &OS = llvm::errs();
178 OS << "(ABIArgInfo Kind=";
181 OS << "Direct Type=";
182 if (llvm::Type *Ty = getCoerceToType())
194 OS << "InAlloca Offset=" << getInAllocaFieldIndex();
197 OS << "Indirect Align=" << getIndirectAlign().getQuantity()
198 << " ByVal=" << getIndirectByVal()
199 << " Realign=" << getIndirectRealign();
204 case CoerceAndExpand:
205 OS << "CoerceAndExpand Type=";
206 getCoerceAndExpandType()->print(OS);
212 // Dynamically round a pointer up to a multiple of the given alignment.
213 static llvm::Value *emitRoundPointerUpToAlignment(CodeGenFunction &CGF,
216 llvm::Value *PtrAsInt = Ptr;
217 // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align;
218 PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
219 PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
220 llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1));
221 PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
222 llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity()));
223 PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt,
225 Ptr->getName() + ".aligned");
229 /// Emit va_arg for a platform using the common void* representation,
230 /// where arguments are simply emitted in an array of slots on the stack.
232 /// This version implements the core direct-value passing rules.
234 /// \param SlotSize - The size and alignment of a stack slot.
235 /// Each argument will be allocated to a multiple of this number of
236 /// slots, and all the slots will be aligned to this value.
237 /// \param AllowHigherAlign - The slot alignment is not a cap;
238 /// an argument type with an alignment greater than the slot size
239 /// will be emitted on a higher-alignment address, potentially
240 /// leaving one or more empty slots behind as padding. If this
241 /// is false, the returned address might be less-aligned than
243 static Address emitVoidPtrDirectVAArg(CodeGenFunction &CGF,
245 llvm::Type *DirectTy,
246 CharUnits DirectSize,
247 CharUnits DirectAlign,
249 bool AllowHigherAlign) {
250 // Cast the element type to i8* if necessary. Some platforms define
251 // va_list as a struct containing an i8* instead of just an i8*.
252 if (VAListAddr.getElementType() != CGF.Int8PtrTy)
253 VAListAddr = CGF.Builder.CreateElementBitCast(VAListAddr, CGF.Int8PtrTy);
255 llvm::Value *Ptr = CGF.Builder.CreateLoad(VAListAddr, "argp.cur");
257 // If the CC aligns values higher than the slot size, do so if needed.
258 Address Addr = Address::invalid();
259 if (AllowHigherAlign && DirectAlign > SlotSize) {
260 Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign),
263 Addr = Address(Ptr, SlotSize);
266 // Advance the pointer past the argument, then store that back.
267 CharUnits FullDirectSize = DirectSize.alignTo(SlotSize);
268 llvm::Value *NextPtr =
269 CGF.Builder.CreateConstInBoundsByteGEP(Addr.getPointer(), FullDirectSize,
271 CGF.Builder.CreateStore(NextPtr, VAListAddr);
273 // If the argument is smaller than a slot, and this is a big-endian
274 // target, the argument will be right-adjusted in its slot.
275 if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() &&
276 !DirectTy->isStructTy()) {
277 Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize);
280 Addr = CGF.Builder.CreateElementBitCast(Addr, DirectTy);
284 /// Emit va_arg for a platform using the common void* representation,
285 /// where arguments are simply emitted in an array of slots on the stack.
287 /// \param IsIndirect - Values of this type are passed indirectly.
288 /// \param ValueInfo - The size and alignment of this type, generally
289 /// computed with getContext().getTypeInfoInChars(ValueTy).
290 /// \param SlotSizeAndAlign - The size and alignment of a stack slot.
291 /// Each argument will be allocated to a multiple of this number of
292 /// slots, and all the slots will be aligned to this value.
293 /// \param AllowHigherAlign - The slot alignment is not a cap;
294 /// an argument type with an alignment greater than the slot size
295 /// will be emitted on a higher-alignment address, potentially
296 /// leaving one or more empty slots behind as padding.
297 static Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr,
298 QualType ValueTy, bool IsIndirect,
299 std::pair<CharUnits, CharUnits> ValueInfo,
300 CharUnits SlotSizeAndAlign,
301 bool AllowHigherAlign) {
302 // The size and alignment of the value that was passed directly.
303 CharUnits DirectSize, DirectAlign;
305 DirectSize = CGF.getPointerSize();
306 DirectAlign = CGF.getPointerAlign();
308 DirectSize = ValueInfo.first;
309 DirectAlign = ValueInfo.second;
312 // Cast the address we've calculated to the right type.
313 llvm::Type *DirectTy = CGF.ConvertTypeForMem(ValueTy);
315 DirectTy = DirectTy->getPointerTo(0);
317 Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy,
318 DirectSize, DirectAlign,
323 Addr = Address(CGF.Builder.CreateLoad(Addr), ValueInfo.second);
330 static Address emitMergePHI(CodeGenFunction &CGF,
331 Address Addr1, llvm::BasicBlock *Block1,
332 Address Addr2, llvm::BasicBlock *Block2,
333 const llvm::Twine &Name = "") {
334 assert(Addr1.getType() == Addr2.getType());
335 llvm::PHINode *PHI = CGF.Builder.CreatePHI(Addr1.getType(), 2, Name);
336 PHI->addIncoming(Addr1.getPointer(), Block1);
337 PHI->addIncoming(Addr2.getPointer(), Block2);
338 CharUnits Align = std::min(Addr1.getAlignment(), Addr2.getAlignment());
339 return Address(PHI, Align);
342 TargetCodeGenInfo::~TargetCodeGenInfo() { delete Info; }
344 // If someone can figure out a general rule for this, that would be great.
345 // It's probably just doomed to be platform-dependent, though.
346 unsigned TargetCodeGenInfo::getSizeOfUnwindException() const {
348 // x86-64 FreeBSD, Linux, Darwin
349 // x86-32 FreeBSD, Linux, Darwin
350 // PowerPC Linux, Darwin
351 // ARM Darwin (*not* EABI)
356 bool TargetCodeGenInfo::isNoProtoCallVariadic(const CallArgList &args,
357 const FunctionNoProtoType *fnType) const {
358 // The following conventions are known to require this to be false:
361 // For everything else, we just prefer false unless we opt out.
366 TargetCodeGenInfo::getDependentLibraryOption(llvm::StringRef Lib,
367 llvm::SmallString<24> &Opt) const {
368 // This assumes the user is passing a library name like "rt" instead of a
369 // filename like "librt.a/so", and that they don't care whether it's static or
375 unsigned TargetCodeGenInfo::getOpenCLKernelCallingConv() const {
376 return llvm::CallingConv::C;
378 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays);
380 /// isEmptyField - Return true iff a the field is "empty", that is it
381 /// is an unnamed bit-field or an (array of) empty record(s).
382 static bool isEmptyField(ASTContext &Context, const FieldDecl *FD,
384 if (FD->isUnnamedBitfield())
387 QualType FT = FD->getType();
389 // Constant arrays of empty records count as empty, strip them off.
390 // Constant arrays of zero length always count as empty.
392 while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
393 if (AT->getSize() == 0)
395 FT = AT->getElementType();
398 const RecordType *RT = FT->getAs<RecordType>();
402 // C++ record fields are never empty, at least in the Itanium ABI.
404 // FIXME: We should use a predicate for whether this behavior is true in the
406 if (isa<CXXRecordDecl>(RT->getDecl()))
409 return isEmptyRecord(Context, FT, AllowArrays);
412 /// isEmptyRecord - Return true iff a structure contains only empty
413 /// fields. Note that a structure with a flexible array member is not
414 /// considered empty.
415 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) {
416 const RecordType *RT = T->getAs<RecordType>();
419 const RecordDecl *RD = RT->getDecl();
420 if (RD->hasFlexibleArrayMember())
423 // If this is a C++ record, check the bases first.
424 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
425 for (const auto &I : CXXRD->bases())
426 if (!isEmptyRecord(Context, I.getType(), true))
429 for (const auto *I : RD->fields())
430 if (!isEmptyField(Context, I, AllowArrays))
435 /// isSingleElementStruct - Determine if a structure is a "single
436 /// element struct", i.e. it has exactly one non-empty field or
437 /// exactly one field which is itself a single element
438 /// struct. Structures with flexible array members are never
439 /// considered single element structs.
441 /// \return The field declaration for the single non-empty field, if
443 static const Type *isSingleElementStruct(QualType T, ASTContext &Context) {
444 const RecordType *RT = T->getAs<RecordType>();
448 const RecordDecl *RD = RT->getDecl();
449 if (RD->hasFlexibleArrayMember())
452 const Type *Found = nullptr;
454 // If this is a C++ record, check the bases first.
455 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
456 for (const auto &I : CXXRD->bases()) {
457 // Ignore empty records.
458 if (isEmptyRecord(Context, I.getType(), true))
461 // If we already found an element then this isn't a single-element struct.
465 // If this is non-empty and not a single element struct, the composite
466 // cannot be a single element struct.
467 Found = isSingleElementStruct(I.getType(), Context);
473 // Check for single element.
474 for (const auto *FD : RD->fields()) {
475 QualType FT = FD->getType();
477 // Ignore empty fields.
478 if (isEmptyField(Context, FD, true))
481 // If we already found an element then this isn't a single-element
486 // Treat single element arrays as the element.
487 while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
488 if (AT->getSize().getZExtValue() != 1)
490 FT = AT->getElementType();
493 if (!isAggregateTypeForABI(FT)) {
494 Found = FT.getTypePtr();
496 Found = isSingleElementStruct(FT, Context);
502 // We don't consider a struct a single-element struct if it has
503 // padding beyond the element type.
504 if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T))
511 Address EmitVAArgInstr(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
512 const ABIArgInfo &AI) {
513 // This default implementation defers to the llvm backend's va_arg
514 // instruction. It can handle only passing arguments directly
515 // (typically only handled in the backend for primitive types), or
516 // aggregates passed indirectly by pointer (NOTE: if the "byval"
517 // flag has ABI impact in the callee, this implementation cannot
520 // Only a few cases are covered here at the moment -- those needed
521 // by the default abi.
524 if (AI.isIndirect()) {
525 assert(!AI.getPaddingType() &&
526 "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
528 !AI.getIndirectRealign() &&
529 "Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!");
531 auto TyInfo = CGF.getContext().getTypeInfoInChars(Ty);
532 CharUnits TyAlignForABI = TyInfo.second;
535 llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty));
537 CGF.Builder.CreateVAArg(VAListAddr.getPointer(), BaseTy);
538 return Address(Addr, TyAlignForABI);
540 assert((AI.isDirect() || AI.isExtend()) &&
541 "Unexpected ArgInfo Kind in generic VAArg emitter!");
543 assert(!AI.getInReg() &&
544 "Unexpected InReg seen in arginfo in generic VAArg emitter!");
545 assert(!AI.getPaddingType() &&
546 "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
547 assert(!AI.getDirectOffset() &&
548 "Unexpected DirectOffset seen in arginfo in generic VAArg emitter!");
549 assert(!AI.getCoerceToType() &&
550 "Unexpected CoerceToType seen in arginfo in generic VAArg emitter!");
552 Address Temp = CGF.CreateMemTemp(Ty, "varet");
553 Val = CGF.Builder.CreateVAArg(VAListAddr.getPointer(), CGF.ConvertType(Ty));
554 CGF.Builder.CreateStore(Val, Temp);
559 /// DefaultABIInfo - The default implementation for ABI specific
560 /// details. This implementation provides information which results in
561 /// self-consistent and sensible LLVM IR generation, but does not
562 /// conform to any particular ABI.
563 class DefaultABIInfo : public ABIInfo {
565 DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
567 ABIArgInfo classifyReturnType(QualType RetTy) const;
568 ABIArgInfo classifyArgumentType(QualType RetTy) const;
570 void computeInfo(CGFunctionInfo &FI) const override {
571 if (!getCXXABI().classifyReturnType(FI))
572 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
573 for (auto &I : FI.arguments())
574 I.info = classifyArgumentType(I.type);
577 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
578 QualType Ty) const override {
579 return EmitVAArgInstr(CGF, VAListAddr, Ty, classifyArgumentType(Ty));
583 class DefaultTargetCodeGenInfo : public TargetCodeGenInfo {
585 DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
586 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
589 ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty) const {
590 Ty = useFirstFieldIfTransparentUnion(Ty);
592 if (isAggregateTypeForABI(Ty)) {
593 // Records with non-trivial destructors/copy-constructors should not be
595 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
596 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
598 return getNaturalAlignIndirect(Ty);
601 // Treat an enum type as its underlying type.
602 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
603 Ty = EnumTy->getDecl()->getIntegerType();
605 return (Ty->isPromotableIntegerType() ?
606 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
609 ABIArgInfo DefaultABIInfo::classifyReturnType(QualType RetTy) const {
610 if (RetTy->isVoidType())
611 return ABIArgInfo::getIgnore();
613 if (isAggregateTypeForABI(RetTy))
614 return getNaturalAlignIndirect(RetTy);
616 // Treat an enum type as its underlying type.
617 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
618 RetTy = EnumTy->getDecl()->getIntegerType();
620 return (RetTy->isPromotableIntegerType() ?
621 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
624 //===----------------------------------------------------------------------===//
625 // WebAssembly ABI Implementation
627 // This is a very simple ABI that relies a lot on DefaultABIInfo.
628 //===----------------------------------------------------------------------===//
630 class WebAssemblyABIInfo final : public DefaultABIInfo {
632 explicit WebAssemblyABIInfo(CodeGen::CodeGenTypes &CGT)
633 : DefaultABIInfo(CGT) {}
636 ABIArgInfo classifyReturnType(QualType RetTy) const;
637 ABIArgInfo classifyArgumentType(QualType Ty) const;
639 // DefaultABIInfo's classifyReturnType and classifyArgumentType are
640 // non-virtual, but computeInfo and EmitVAArg are virtual, so we
642 void computeInfo(CGFunctionInfo &FI) const override {
643 if (!getCXXABI().classifyReturnType(FI))
644 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
645 for (auto &Arg : FI.arguments())
646 Arg.info = classifyArgumentType(Arg.type);
649 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
650 QualType Ty) const override;
653 class WebAssemblyTargetCodeGenInfo final : public TargetCodeGenInfo {
655 explicit WebAssemblyTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
656 : TargetCodeGenInfo(new WebAssemblyABIInfo(CGT)) {}
659 /// \brief Classify argument of given type \p Ty.
660 ABIArgInfo WebAssemblyABIInfo::classifyArgumentType(QualType Ty) const {
661 Ty = useFirstFieldIfTransparentUnion(Ty);
663 if (isAggregateTypeForABI(Ty)) {
664 // Records with non-trivial destructors/copy-constructors should not be
666 if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
667 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
668 // Ignore empty structs/unions.
669 if (isEmptyRecord(getContext(), Ty, true))
670 return ABIArgInfo::getIgnore();
671 // Lower single-element structs to just pass a regular value. TODO: We
672 // could do reasonable-size multiple-element structs too, using getExpand(),
673 // though watch out for things like bitfields.
674 if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
675 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
678 // Otherwise just do the default thing.
679 return DefaultABIInfo::classifyArgumentType(Ty);
682 ABIArgInfo WebAssemblyABIInfo::classifyReturnType(QualType RetTy) const {
683 if (isAggregateTypeForABI(RetTy)) {
684 // Records with non-trivial destructors/copy-constructors should not be
685 // returned by value.
686 if (!getRecordArgABI(RetTy, getCXXABI())) {
687 // Ignore empty structs/unions.
688 if (isEmptyRecord(getContext(), RetTy, true))
689 return ABIArgInfo::getIgnore();
690 // Lower single-element structs to just return a regular value. TODO: We
691 // could do reasonable-size multiple-element structs too, using
692 // ABIArgInfo::getDirect().
693 if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
694 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
698 // Otherwise just do the default thing.
699 return DefaultABIInfo::classifyReturnType(RetTy);
702 Address WebAssemblyABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
704 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect=*/ false,
705 getContext().getTypeInfoInChars(Ty),
706 CharUnits::fromQuantity(4),
707 /*AllowHigherAlign=*/ true);
710 //===----------------------------------------------------------------------===//
711 // le32/PNaCl bitcode ABI Implementation
713 // This is a simplified version of the x86_32 ABI. Arguments and return values
714 // are always passed on the stack.
715 //===----------------------------------------------------------------------===//
717 class PNaClABIInfo : public ABIInfo {
719 PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
721 ABIArgInfo classifyReturnType(QualType RetTy) const;
722 ABIArgInfo classifyArgumentType(QualType RetTy) const;
724 void computeInfo(CGFunctionInfo &FI) const override;
725 Address EmitVAArg(CodeGenFunction &CGF,
726 Address VAListAddr, QualType Ty) const override;
729 class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
731 PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
732 : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {}
735 void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
736 if (!getCXXABI().classifyReturnType(FI))
737 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
739 for (auto &I : FI.arguments())
740 I.info = classifyArgumentType(I.type);
743 Address PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
745 // The PNaCL ABI is a bit odd, in that varargs don't use normal
746 // function classification. Structs get passed directly for varargs
747 // functions, through a rewriting transform in
748 // pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows
749 // this target to actually support a va_arg instructions with an
750 // aggregate type, unlike other targets.
751 return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
754 /// \brief Classify argument of given type \p Ty.
755 ABIArgInfo PNaClABIInfo::classifyArgumentType(QualType Ty) const {
756 if (isAggregateTypeForABI(Ty)) {
757 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
758 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
759 return getNaturalAlignIndirect(Ty);
760 } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
761 // Treat an enum type as its underlying type.
762 Ty = EnumTy->getDecl()->getIntegerType();
763 } else if (Ty->isFloatingType()) {
764 // Floating-point types don't go inreg.
765 return ABIArgInfo::getDirect();
768 return (Ty->isPromotableIntegerType() ?
769 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
772 ABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const {
773 if (RetTy->isVoidType())
774 return ABIArgInfo::getIgnore();
776 // In the PNaCl ABI we always return records/structures on the stack.
777 if (isAggregateTypeForABI(RetTy))
778 return getNaturalAlignIndirect(RetTy);
780 // Treat an enum type as its underlying type.
781 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
782 RetTy = EnumTy->getDecl()->getIntegerType();
784 return (RetTy->isPromotableIntegerType() ?
785 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
788 /// IsX86_MMXType - Return true if this is an MMX type.
789 bool IsX86_MMXType(llvm::Type *IRType) {
790 // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
791 return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
792 cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
793 IRType->getScalarSizeInBits() != 64;
796 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
797 StringRef Constraint,
799 if ((Constraint == "y" || Constraint == "&y") && Ty->isVectorTy()) {
800 if (cast<llvm::VectorType>(Ty)->getBitWidth() != 64) {
801 // Invalid MMX constraint
805 return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
808 // No operation needed
812 /// Returns true if this type can be passed in SSE registers with the
813 /// X86_VectorCall calling convention. Shared between x86_32 and x86_64.
814 static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) {
815 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
816 if (BT->isFloatingPoint() && BT->getKind() != BuiltinType::Half)
818 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
819 // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX
820 // registers specially.
821 unsigned VecSize = Context.getTypeSize(VT);
822 if (VecSize == 128 || VecSize == 256 || VecSize == 512)
828 /// Returns true if this aggregate is small enough to be passed in SSE registers
829 /// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64.
830 static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) {
831 return NumMembers <= 4;
834 //===----------------------------------------------------------------------===//
835 // X86-32 ABI Implementation
836 //===----------------------------------------------------------------------===//
838 /// \brief Similar to llvm::CCState, but for Clang.
840 CCState(unsigned CC) : CC(CC), FreeRegs(0), FreeSSERegs(0) {}
844 unsigned FreeSSERegs;
847 /// X86_32ABIInfo - The X86-32 ABI information.
848 class X86_32ABIInfo : public SwiftABIInfo {
854 static const unsigned MinABIStackAlignInBytes = 4;
856 bool IsDarwinVectorABI;
857 bool IsRetSmallStructInRegABI;
858 bool IsWin32StructABI;
861 unsigned DefaultNumRegisterParameters;
863 static bool isRegisterSize(unsigned Size) {
864 return (Size == 8 || Size == 16 || Size == 32 || Size == 64);
867 bool isHomogeneousAggregateBaseType(QualType Ty) const override {
868 // FIXME: Assumes vectorcall is in use.
869 return isX86VectorTypeForVectorCall(getContext(), Ty);
872 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
873 uint64_t NumMembers) const override {
874 // FIXME: Assumes vectorcall is in use.
875 return isX86VectorCallAggregateSmallEnough(NumMembers);
878 bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const;
880 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
881 /// such that the argument will be passed in memory.
882 ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
884 ABIArgInfo getIndirectReturnResult(QualType Ty, CCState &State) const;
886 /// \brief Return the alignment to use for the given type on the stack.
887 unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const;
889 Class classify(QualType Ty) const;
890 ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
891 ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
892 /// \brief Updates the number of available free registers, returns
893 /// true if any registers were allocated.
894 bool updateFreeRegs(QualType Ty, CCState &State) const;
896 bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
897 bool &NeedsPadding) const;
898 bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const;
900 bool canExpandIndirectArgument(QualType Ty) const;
902 /// \brief Rewrite the function info so that all memory arguments use
904 void rewriteWithInAlloca(CGFunctionInfo &FI) const;
906 void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
907 CharUnits &StackOffset, ABIArgInfo &Info,
908 QualType Type) const;
912 void computeInfo(CGFunctionInfo &FI) const override;
913 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
914 QualType Ty) const override;
916 X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
917 bool RetSmallStructInRegABI, bool Win32StructABI,
918 unsigned NumRegisterParameters, bool SoftFloatABI)
919 : SwiftABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
920 IsRetSmallStructInRegABI(RetSmallStructInRegABI),
921 IsWin32StructABI(Win32StructABI),
922 IsSoftFloatABI(SoftFloatABI),
923 IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()),
924 DefaultNumRegisterParameters(NumRegisterParameters) {}
926 bool shouldPassIndirectlyForSwift(CharUnits totalSize,
927 ArrayRef<llvm::Type*> scalars,
928 bool asReturnValue) const override {
929 // LLVM's x86-32 lowering currently only assigns up to three
930 // integer registers and three fp registers. Oddly, it'll use up to
931 // four vector registers for vectors, but those can overlap with the
933 return occupiesMoreThan(CGT, scalars, /*total*/ 3);
937 class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
939 X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
940 bool RetSmallStructInRegABI, bool Win32StructABI,
941 unsigned NumRegisterParameters, bool SoftFloatABI)
942 : TargetCodeGenInfo(new X86_32ABIInfo(
943 CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
944 NumRegisterParameters, SoftFloatABI)) {}
946 static bool isStructReturnInRegABI(
947 const llvm::Triple &Triple, const CodeGenOptions &Opts);
949 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
950 CodeGen::CodeGenModule &CGM) const override;
952 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
953 // Darwin uses different dwarf register numbers for EH.
954 if (CGM.getTarget().getTriple().isOSDarwin()) return 5;
958 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
959 llvm::Value *Address) const override;
961 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
962 StringRef Constraint,
963 llvm::Type* Ty) const override {
964 return X86AdjustInlineAsmType(CGF, Constraint, Ty);
967 void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue,
968 std::string &Constraints,
969 std::vector<llvm::Type *> &ResultRegTypes,
970 std::vector<llvm::Type *> &ResultTruncRegTypes,
971 std::vector<LValue> &ResultRegDests,
972 std::string &AsmString,
973 unsigned NumOutputs) const override;
976 getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
977 unsigned Sig = (0xeb << 0) | // jmp rel8
978 (0x06 << 8) | // .+0x08
981 return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
984 StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
985 return "movl\t%ebp, %ebp"
986 "\t\t## marker for objc_retainAutoreleaseReturnValue";
992 /// Rewrite input constraint references after adding some output constraints.
993 /// In the case where there is one output and one input and we add one output,
994 /// we need to replace all operand references greater than or equal to 1:
997 /// The result will be:
1000 static void rewriteInputConstraintReferences(unsigned FirstIn,
1001 unsigned NumNewOuts,
1002 std::string &AsmString) {
1004 llvm::raw_string_ostream OS(Buf);
1006 while (Pos < AsmString.size()) {
1007 size_t DollarStart = AsmString.find('$', Pos);
1008 if (DollarStart == std::string::npos)
1009 DollarStart = AsmString.size();
1010 size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart);
1011 if (DollarEnd == std::string::npos)
1012 DollarEnd = AsmString.size();
1013 OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
1015 size_t NumDollars = DollarEnd - DollarStart;
1016 if (NumDollars % 2 != 0 && Pos < AsmString.size()) {
1017 // We have an operand reference.
1018 size_t DigitStart = Pos;
1019 size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart);
1020 if (DigitEnd == std::string::npos)
1021 DigitEnd = AsmString.size();
1022 StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
1023 unsigned OperandIndex;
1024 if (!OperandStr.getAsInteger(10, OperandIndex)) {
1025 if (OperandIndex >= FirstIn)
1026 OperandIndex += NumNewOuts;
1034 AsmString = std::move(OS.str());
1037 /// Add output constraints for EAX:EDX because they are return registers.
1038 void X86_32TargetCodeGenInfo::addReturnRegisterOutputs(
1039 CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints,
1040 std::vector<llvm::Type *> &ResultRegTypes,
1041 std::vector<llvm::Type *> &ResultTruncRegTypes,
1042 std::vector<LValue> &ResultRegDests, std::string &AsmString,
1043 unsigned NumOutputs) const {
1044 uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType());
1046 // Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is
1048 if (!Constraints.empty())
1050 if (RetWidth <= 32) {
1051 Constraints += "={eax}";
1052 ResultRegTypes.push_back(CGF.Int32Ty);
1054 // Use the 'A' constraint for EAX:EDX.
1055 Constraints += "=A";
1056 ResultRegTypes.push_back(CGF.Int64Ty);
1059 // Truncate EAX or EAX:EDX to an integer of the appropriate size.
1060 llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth);
1061 ResultTruncRegTypes.push_back(CoerceTy);
1063 // Coerce the integer by bitcasting the return slot pointer.
1064 ReturnSlot.setAddress(CGF.Builder.CreateBitCast(ReturnSlot.getAddress(),
1065 CoerceTy->getPointerTo()));
1066 ResultRegDests.push_back(ReturnSlot);
1068 rewriteInputConstraintReferences(NumOutputs, 1, AsmString);
1071 /// shouldReturnTypeInRegister - Determine if the given type should be
1072 /// returned in a register (for the Darwin and MCU ABI).
1073 bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
1074 ASTContext &Context) const {
1075 uint64_t Size = Context.getTypeSize(Ty);
1077 // For i386, type must be register sized.
1078 // For the MCU ABI, it only needs to be <= 8-byte
1079 if ((IsMCUABI && Size > 64) || (!IsMCUABI && !isRegisterSize(Size)))
1082 if (Ty->isVectorType()) {
1083 // 64- and 128- bit vectors inside structures are not returned in
1085 if (Size == 64 || Size == 128)
1091 // If this is a builtin, pointer, enum, complex type, member pointer, or
1092 // member function pointer it is ok.
1093 if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() ||
1094 Ty->isAnyComplexType() || Ty->isEnumeralType() ||
1095 Ty->isBlockPointerType() || Ty->isMemberPointerType())
1098 // Arrays are treated like records.
1099 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty))
1100 return shouldReturnTypeInRegister(AT->getElementType(), Context);
1102 // Otherwise, it must be a record type.
1103 const RecordType *RT = Ty->getAs<RecordType>();
1104 if (!RT) return false;
1106 // FIXME: Traverse bases here too.
1108 // Structure types are passed in register if all fields would be
1109 // passed in a register.
1110 for (const auto *FD : RT->getDecl()->fields()) {
1111 // Empty fields are ignored.
1112 if (isEmptyField(Context, FD, true))
1115 // Check fields recursively.
1116 if (!shouldReturnTypeInRegister(FD->getType(), Context))
1122 static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) {
1123 // Treat complex types as the element type.
1124 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
1125 Ty = CTy->getElementType();
1127 // Check for a type which we know has a simple scalar argument-passing
1128 // convention without any padding. (We're specifically looking for 32
1129 // and 64-bit integer and integer-equivalents, float, and double.)
1130 if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() &&
1131 !Ty->isEnumeralType() && !Ty->isBlockPointerType())
1134 uint64_t Size = Context.getTypeSize(Ty);
1135 return Size == 32 || Size == 64;
1138 /// Test whether an argument type which is to be passed indirectly (on the
1139 /// stack) would have the equivalent layout if it was expanded into separate
1140 /// arguments. If so, we prefer to do the latter to avoid inhibiting
1142 bool X86_32ABIInfo::canExpandIndirectArgument(QualType Ty) const {
1143 // We can only expand structure types.
1144 const RecordType *RT = Ty->getAs<RecordType>();
1147 const RecordDecl *RD = RT->getDecl();
1148 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
1149 if (!IsWin32StructABI ) {
1150 // On non-Windows, we have to conservatively match our old bitcode
1151 // prototypes in order to be ABI-compatible at the bitcode level.
1152 if (!CXXRD->isCLike())
1155 // Don't do this for dynamic classes.
1156 if (CXXRD->isDynamicClass())
1158 // Don't do this if there are any non-empty bases.
1159 for (const CXXBaseSpecifier &Base : CXXRD->bases()) {
1160 if (!isEmptyRecord(getContext(), Base.getType(), /*AllowArrays=*/true))
1168 for (const auto *FD : RD->fields()) {
1169 // Scalar arguments on the stack get 4 byte alignment on x86. If the
1170 // argument is smaller than 32-bits, expanding the struct will create
1171 // alignment padding.
1172 if (!is32Or64BitBasicType(FD->getType(), getContext()))
1175 // FIXME: Reject bit-fields wholesale; there are two problems, we don't know
1176 // how to expand them yet, and the predicate for telling if a bitfield still
1177 // counts as "basic" is more complicated than what we were doing previously.
1178 if (FD->isBitField())
1181 Size += getContext().getTypeSize(FD->getType());
1184 // We can do this if there was no alignment padding.
1185 return Size == getContext().getTypeSize(Ty);
1188 ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(QualType RetTy, CCState &State) const {
1189 // If the return value is indirect, then the hidden argument is consuming one
1190 // integer register.
1191 if (State.FreeRegs) {
1194 return getNaturalAlignIndirectInReg(RetTy);
1196 return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
1199 ABIArgInfo X86_32ABIInfo::classifyReturnType(QualType RetTy,
1200 CCState &State) const {
1201 if (RetTy->isVoidType())
1202 return ABIArgInfo::getIgnore();
1204 const Type *Base = nullptr;
1205 uint64_t NumElts = 0;
1206 if (State.CC == llvm::CallingConv::X86_VectorCall &&
1207 isHomogeneousAggregate(RetTy, Base, NumElts)) {
1208 // The LLVM struct type for such an aggregate should lower properly.
1209 return ABIArgInfo::getDirect();
1212 if (const VectorType *VT = RetTy->getAs<VectorType>()) {
1213 // On Darwin, some vectors are returned in registers.
1214 if (IsDarwinVectorABI) {
1215 uint64_t Size = getContext().getTypeSize(RetTy);
1217 // 128-bit vectors are a special case; they are returned in
1218 // registers and we need to make sure to pick a type the LLVM
1219 // backend will like.
1221 return ABIArgInfo::getDirect(llvm::VectorType::get(
1222 llvm::Type::getInt64Ty(getVMContext()), 2));
1224 // Always return in register if it fits in a general purpose
1225 // register, or if it is 64 bits and has a single element.
1226 if ((Size == 8 || Size == 16 || Size == 32) ||
1227 (Size == 64 && VT->getNumElements() == 1))
1228 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1231 return getIndirectReturnResult(RetTy, State);
1234 return ABIArgInfo::getDirect();
1237 if (isAggregateTypeForABI(RetTy)) {
1238 if (const RecordType *RT = RetTy->getAs<RecordType>()) {
1239 // Structures with flexible arrays are always indirect.
1240 if (RT->getDecl()->hasFlexibleArrayMember())
1241 return getIndirectReturnResult(RetTy, State);
1244 // If specified, structs and unions are always indirect.
1245 if (!IsRetSmallStructInRegABI && !RetTy->isAnyComplexType())
1246 return getIndirectReturnResult(RetTy, State);
1248 // Ignore empty structs/unions.
1249 if (isEmptyRecord(getContext(), RetTy, true))
1250 return ABIArgInfo::getIgnore();
1252 // Small structures which are register sized are generally returned
1254 if (shouldReturnTypeInRegister(RetTy, getContext())) {
1255 uint64_t Size = getContext().getTypeSize(RetTy);
1257 // As a special-case, if the struct is a "single-element" struct, and
1258 // the field is of type "float" or "double", return it in a
1259 // floating-point register. (MSVC does not apply this special case.)
1260 // We apply a similar transformation for pointer types to improve the
1261 // quality of the generated IR.
1262 if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
1263 if ((!IsWin32StructABI && SeltTy->isRealFloatingType())
1264 || SeltTy->hasPointerRepresentation())
1265 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
1267 // FIXME: We should be able to narrow this integer in cases with dead
1269 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size));
1272 return getIndirectReturnResult(RetTy, State);
1275 // Treat an enum type as its underlying type.
1276 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
1277 RetTy = EnumTy->getDecl()->getIntegerType();
1279 return (RetTy->isPromotableIntegerType() ?
1280 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
1283 static bool isSSEVectorType(ASTContext &Context, QualType Ty) {
1284 return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128;
1287 static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) {
1288 const RecordType *RT = Ty->getAs<RecordType>();
1291 const RecordDecl *RD = RT->getDecl();
1293 // If this is a C++ record, check the bases first.
1294 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
1295 for (const auto &I : CXXRD->bases())
1296 if (!isRecordWithSSEVectorType(Context, I.getType()))
1299 for (const auto *i : RD->fields()) {
1300 QualType FT = i->getType();
1302 if (isSSEVectorType(Context, FT))
1305 if (isRecordWithSSEVectorType(Context, FT))
1312 unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty,
1313 unsigned Align) const {
1314 // Otherwise, if the alignment is less than or equal to the minimum ABI
1315 // alignment, just use the default; the backend will handle this.
1316 if (Align <= MinABIStackAlignInBytes)
1317 return 0; // Use default alignment.
1319 // On non-Darwin, the stack type alignment is always 4.
1320 if (!IsDarwinVectorABI) {
1321 // Set explicit alignment, since we may need to realign the top.
1322 return MinABIStackAlignInBytes;
1325 // Otherwise, if the type contains an SSE vector type, the alignment is 16.
1326 if (Align >= 16 && (isSSEVectorType(getContext(), Ty) ||
1327 isRecordWithSSEVectorType(getContext(), Ty)))
1330 return MinABIStackAlignInBytes;
1333 ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal,
1334 CCState &State) const {
1336 if (State.FreeRegs) {
1337 --State.FreeRegs; // Non-byval indirects just use one pointer.
1339 return getNaturalAlignIndirectInReg(Ty);
1341 return getNaturalAlignIndirect(Ty, false);
1344 // Compute the byval alignment.
1345 unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
1346 unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign);
1347 if (StackAlign == 0)
1348 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true);
1350 // If the stack alignment is less than the type alignment, realign the
1352 bool Realign = TypeAlign > StackAlign;
1353 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(StackAlign),
1354 /*ByVal=*/true, Realign);
1357 X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const {
1358 const Type *T = isSingleElementStruct(Ty, getContext());
1360 T = Ty.getTypePtr();
1362 if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
1363 BuiltinType::Kind K = BT->getKind();
1364 if (K == BuiltinType::Float || K == BuiltinType::Double)
1370 bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const {
1371 if (!IsSoftFloatABI) {
1372 Class C = classify(Ty);
1377 unsigned Size = getContext().getTypeSize(Ty);
1378 unsigned SizeInRegs = (Size + 31) / 32;
1380 if (SizeInRegs == 0)
1384 if (SizeInRegs > State.FreeRegs) {
1389 // The MCU psABI allows passing parameters in-reg even if there are
1390 // earlier parameters that are passed on the stack. Also,
1391 // it does not allow passing >8-byte structs in-register,
1392 // even if there are 3 free registers available.
1393 if (SizeInRegs > State.FreeRegs || SizeInRegs > 2)
1397 State.FreeRegs -= SizeInRegs;
1401 bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State,
1403 bool &NeedsPadding) const {
1404 // On Windows, aggregates other than HFAs are never passed in registers, and
1405 // they do not consume register slots. Homogenous floating-point aggregates
1406 // (HFAs) have already been dealt with at this point.
1407 if (IsWin32StructABI && isAggregateTypeForABI(Ty))
1410 NeedsPadding = false;
1413 if (!updateFreeRegs(Ty, State))
1419 if (State.CC == llvm::CallingConv::X86_FastCall ||
1420 State.CC == llvm::CallingConv::X86_VectorCall) {
1421 if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs)
1422 NeedsPadding = true;
1430 bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const {
1431 if (!updateFreeRegs(Ty, State))
1437 if (State.CC == llvm::CallingConv::X86_FastCall ||
1438 State.CC == llvm::CallingConv::X86_VectorCall) {
1439 if (getContext().getTypeSize(Ty) > 32)
1442 return (Ty->isIntegralOrEnumerationType() || Ty->isPointerType() ||
1443 Ty->isReferenceType());
1449 ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
1450 CCState &State) const {
1451 // FIXME: Set alignment on indirect arguments.
1453 Ty = useFirstFieldIfTransparentUnion(Ty);
1455 // Check with the C++ ABI first.
1456 const RecordType *RT = Ty->getAs<RecordType>();
1458 CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
1459 if (RAA == CGCXXABI::RAA_Indirect) {
1460 return getIndirectResult(Ty, false, State);
1461 } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
1462 // The field index doesn't matter, we'll fix it up later.
1463 return ABIArgInfo::getInAlloca(/*FieldIndex=*/0);
1467 // vectorcall adds the concept of a homogenous vector aggregate, similar
1468 // to other targets.
1469 const Type *Base = nullptr;
1470 uint64_t NumElts = 0;
1471 if (State.CC == llvm::CallingConv::X86_VectorCall &&
1472 isHomogeneousAggregate(Ty, Base, NumElts)) {
1473 if (State.FreeSSERegs >= NumElts) {
1474 State.FreeSSERegs -= NumElts;
1475 if (Ty->isBuiltinType() || Ty->isVectorType())
1476 return ABIArgInfo::getDirect();
1477 return ABIArgInfo::getExpand();
1479 return getIndirectResult(Ty, /*ByVal=*/false, State);
1482 if (isAggregateTypeForABI(Ty)) {
1483 // Structures with flexible arrays are always indirect.
1484 // FIXME: This should not be byval!
1485 if (RT && RT->getDecl()->hasFlexibleArrayMember())
1486 return getIndirectResult(Ty, true, State);
1488 // Ignore empty structs/unions on non-Windows.
1489 if (!IsWin32StructABI && isEmptyRecord(getContext(), Ty, true))
1490 return ABIArgInfo::getIgnore();
1492 llvm::LLVMContext &LLVMContext = getVMContext();
1493 llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
1494 bool NeedsPadding = false;
1496 if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
1497 unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
1498 SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
1499 llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
1501 return ABIArgInfo::getDirectInReg(Result);
1503 return ABIArgInfo::getDirect(Result);
1505 llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr;
1507 // Expand small (<= 128-bit) record types when we know that the stack layout
1508 // of those arguments will match the struct. This is important because the
1509 // LLVM backend isn't smart enough to remove byval, which inhibits many
1511 // Don't do this for the MCU if there are still free integer registers
1512 // (see X86_64 ABI for full explanation).
1513 if (getContext().getTypeSize(Ty) <= 4 * 32 &&
1514 (!IsMCUABI || State.FreeRegs == 0) && canExpandIndirectArgument(Ty))
1515 return ABIArgInfo::getExpandWithPadding(
1516 State.CC == llvm::CallingConv::X86_FastCall ||
1517 State.CC == llvm::CallingConv::X86_VectorCall,
1520 return getIndirectResult(Ty, true, State);
1523 if (const VectorType *VT = Ty->getAs<VectorType>()) {
1524 // On Darwin, some vectors are passed in memory, we handle this by passing
1525 // it as an i8/i16/i32/i64.
1526 if (IsDarwinVectorABI) {
1527 uint64_t Size = getContext().getTypeSize(Ty);
1528 if ((Size == 8 || Size == 16 || Size == 32) ||
1529 (Size == 64 && VT->getNumElements() == 1))
1530 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1534 if (IsX86_MMXType(CGT.ConvertType(Ty)))
1535 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
1537 return ABIArgInfo::getDirect();
1541 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
1542 Ty = EnumTy->getDecl()->getIntegerType();
1544 bool InReg = shouldPrimitiveUseInReg(Ty, State);
1546 if (Ty->isPromotableIntegerType()) {
1548 return ABIArgInfo::getExtendInReg();
1549 return ABIArgInfo::getExtend();
1553 return ABIArgInfo::getDirectInReg();
1554 return ABIArgInfo::getDirect();
1557 void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
1558 CCState State(FI.getCallingConvention());
1561 else if (State.CC == llvm::CallingConv::X86_FastCall)
1563 else if (State.CC == llvm::CallingConv::X86_VectorCall) {
1565 State.FreeSSERegs = 6;
1566 } else if (FI.getHasRegParm())
1567 State.FreeRegs = FI.getRegParm();
1569 State.FreeRegs = DefaultNumRegisterParameters;
1571 if (!getCXXABI().classifyReturnType(FI)) {
1572 FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), State);
1573 } else if (FI.getReturnInfo().isIndirect()) {
1574 // The C++ ABI is not aware of register usage, so we have to check if the
1575 // return value was sret and put it in a register ourselves if appropriate.
1576 if (State.FreeRegs) {
1577 --State.FreeRegs; // The sret parameter consumes a register.
1579 FI.getReturnInfo().setInReg(true);
1583 // The chain argument effectively gives us another free register.
1584 if (FI.isChainCall())
1587 bool UsedInAlloca = false;
1588 for (auto &I : FI.arguments()) {
1589 I.info = classifyArgumentType(I.type, State);
1590 UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1593 // If we needed to use inalloca for any argument, do a second pass and rewrite
1594 // all the memory arguments to use inalloca.
1596 rewriteWithInAlloca(FI);
1600 X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1601 CharUnits &StackOffset, ABIArgInfo &Info,
1602 QualType Type) const {
1603 // Arguments are always 4-byte-aligned.
1604 CharUnits FieldAlign = CharUnits::fromQuantity(4);
1606 assert(StackOffset.isMultipleOf(FieldAlign) && "unaligned inalloca struct");
1607 Info = ABIArgInfo::getInAlloca(FrameFields.size());
1608 FrameFields.push_back(CGT.ConvertTypeForMem(Type));
1609 StackOffset += getContext().getTypeSizeInChars(Type);
1611 // Insert padding bytes to respect alignment.
1612 CharUnits FieldEnd = StackOffset;
1613 StackOffset = FieldEnd.alignTo(FieldAlign);
1614 if (StackOffset != FieldEnd) {
1615 CharUnits NumBytes = StackOffset - FieldEnd;
1616 llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
1617 Ty = llvm::ArrayType::get(Ty, NumBytes.getQuantity());
1618 FrameFields.push_back(Ty);
1622 static bool isArgInAlloca(const ABIArgInfo &Info) {
1623 // Leave ignored and inreg arguments alone.
1624 switch (Info.getKind()) {
1625 case ABIArgInfo::InAlloca:
1627 case ABIArgInfo::Indirect:
1628 assert(Info.getIndirectByVal());
1630 case ABIArgInfo::Ignore:
1632 case ABIArgInfo::Direct:
1633 case ABIArgInfo::Extend:
1634 if (Info.getInReg())
1637 case ABIArgInfo::Expand:
1638 case ABIArgInfo::CoerceAndExpand:
1639 // These are aggregate types which are never passed in registers when
1640 // inalloca is involved.
1643 llvm_unreachable("invalid enum");
1646 void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
1647 assert(IsWin32StructABI && "inalloca only supported on win32");
1649 // Build a packed struct type for all of the arguments in memory.
1650 SmallVector<llvm::Type *, 6> FrameFields;
1652 // The stack alignment is always 4.
1653 CharUnits StackAlign = CharUnits::fromQuantity(4);
1655 CharUnits StackOffset;
1656 CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end();
1658 // Put 'this' into the struct before 'sret', if necessary.
1660 FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
1661 ABIArgInfo &Ret = FI.getReturnInfo();
1662 if (Ret.isIndirect() && Ret.isSRetAfterThis() && !IsThisCall &&
1663 isArgInAlloca(I->info)) {
1664 addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1668 // Put the sret parameter into the inalloca struct if it's in memory.
1669 if (Ret.isIndirect() && !Ret.getInReg()) {
1670 CanQualType PtrTy = getContext().getPointerType(FI.getReturnType());
1671 addFieldToArgStruct(FrameFields, StackOffset, Ret, PtrTy);
1672 // On Windows, the hidden sret parameter is always returned in eax.
1673 Ret.setInAllocaSRet(IsWin32StructABI);
1676 // Skip the 'this' parameter in ecx.
1680 // Put arguments passed in memory into the struct.
1681 for (; I != E; ++I) {
1682 if (isArgInAlloca(I->info))
1683 addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1686 FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
1691 Address X86_32ABIInfo::EmitVAArg(CodeGenFunction &CGF,
1692 Address VAListAddr, QualType Ty) const {
1694 auto TypeInfo = getContext().getTypeInfoInChars(Ty);
1696 // x86-32 changes the alignment of certain arguments on the stack.
1698 // Just messing with TypeInfo like this works because we never pass
1699 // anything indirectly.
1700 TypeInfo.second = CharUnits::fromQuantity(
1701 getTypeStackAlignInBytes(Ty, TypeInfo.second.getQuantity()));
1703 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
1704 TypeInfo, CharUnits::fromQuantity(4),
1705 /*AllowHigherAlign*/ true);
1708 bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
1709 const llvm::Triple &Triple, const CodeGenOptions &Opts) {
1710 assert(Triple.getArch() == llvm::Triple::x86);
1712 switch (Opts.getStructReturnConvention()) {
1713 case CodeGenOptions::SRCK_Default:
1715 case CodeGenOptions::SRCK_OnStack: // -fpcc-struct-return
1717 case CodeGenOptions::SRCK_InRegs: // -freg-struct-return
1721 if (Triple.isOSDarwin() || Triple.isOSIAMCU())
1724 switch (Triple.getOS()) {
1725 case llvm::Triple::DragonFly:
1726 case llvm::Triple::FreeBSD:
1727 case llvm::Triple::OpenBSD:
1728 case llvm::Triple::Bitrig:
1729 case llvm::Triple::Win32:
1736 void X86_32TargetCodeGenInfo::setTargetAttributes(const Decl *D,
1737 llvm::GlobalValue *GV,
1738 CodeGen::CodeGenModule &CGM) const {
1739 if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
1740 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1741 // Get the LLVM function.
1742 llvm::Function *Fn = cast<llvm::Function>(GV);
1744 // Now add the 'alignstack' attribute with a value of 16.
1745 llvm::AttrBuilder B;
1746 B.addStackAlignmentAttr(16);
1747 Fn->addAttributes(llvm::AttributeSet::FunctionIndex,
1748 llvm::AttributeSet::get(CGM.getLLVMContext(),
1749 llvm::AttributeSet::FunctionIndex,
1752 if (FD->hasAttr<AnyX86InterruptAttr>()) {
1753 llvm::Function *Fn = cast<llvm::Function>(GV);
1754 Fn->setCallingConv(llvm::CallingConv::X86_INTR);
1759 bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
1760 CodeGen::CodeGenFunction &CGF,
1761 llvm::Value *Address) const {
1762 CodeGen::CGBuilderTy &Builder = CGF.Builder;
1764 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
1766 // 0-7 are the eight integer registers; the order is different
1767 // on Darwin (for EH), but the range is the same.
1769 AssignToArrayRange(Builder, Address, Four8, 0, 8);
1771 if (CGF.CGM.getTarget().getTriple().isOSDarwin()) {
1772 // 12-16 are st(0..4). Not sure why we stop at 4.
1773 // These have size 16, which is sizeof(long double) on
1774 // platforms with 8-byte alignment for that type.
1775 llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
1776 AssignToArrayRange(Builder, Address, Sixteen8, 12, 16);
1779 // 9 is %eflags, which doesn't get a size on Darwin for some
1781 Builder.CreateAlignedStore(
1782 Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9),
1785 // 11-16 are st(0..5). Not sure why we stop at 5.
1786 // These have size 12, which is sizeof(long double) on
1787 // platforms with 4-byte alignment for that type.
1788 llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12);
1789 AssignToArrayRange(Builder, Address, Twelve8, 11, 16);
1795 //===----------------------------------------------------------------------===//
1796 // X86-64 ABI Implementation
1797 //===----------------------------------------------------------------------===//
1801 /// The AVX ABI level for X86 targets.
1802 enum class X86AVXABILevel {
1808 /// \p returns the size in bits of the largest (native) vector for \p AVXLevel.
1809 static unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) {
1811 case X86AVXABILevel::AVX512:
1813 case X86AVXABILevel::AVX:
1815 case X86AVXABILevel::None:
1818 llvm_unreachable("Unknown AVXLevel");
1821 /// X86_64ABIInfo - The X86_64 ABI information.
1822 class X86_64ABIInfo : public SwiftABIInfo {
1834 /// merge - Implement the X86_64 ABI merging algorithm.
1836 /// Merge an accumulating classification \arg Accum with a field
1837 /// classification \arg Field.
1839 /// \param Accum - The accumulating classification. This should
1840 /// always be either NoClass or the result of a previous merge
1841 /// call. In addition, this should never be Memory (the caller
1842 /// should just return Memory for the aggregate).
1843 static Class merge(Class Accum, Class Field);
1845 /// postMerge - Implement the X86_64 ABI post merging algorithm.
1847 /// Post merger cleanup, reduces a malformed Hi and Lo pair to
1848 /// final MEMORY or SSE classes when necessary.
1850 /// \param AggregateSize - The size of the current aggregate in
1851 /// the classification process.
1853 /// \param Lo - The classification for the parts of the type
1854 /// residing in the low word of the containing object.
1856 /// \param Hi - The classification for the parts of the type
1857 /// residing in the higher words of the containing object.
1859 void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
1861 /// classify - Determine the x86_64 register classes in which the
1862 /// given type T should be passed.
1864 /// \param Lo - The classification for the parts of the type
1865 /// residing in the low word of the containing object.
1867 /// \param Hi - The classification for the parts of the type
1868 /// residing in the high word of the containing object.
1870 /// \param OffsetBase - The bit offset of this type in the
1871 /// containing object. Some parameters are classified different
1872 /// depending on whether they straddle an eightbyte boundary.
1874 /// \param isNamedArg - Whether the argument in question is a "named"
1875 /// argument, as used in AMD64-ABI 3.5.7.
1877 /// If a word is unused its result will be NoClass; if a type should
1878 /// be passed in Memory then at least the classification of \arg Lo
1881 /// The \arg Lo class will be NoClass iff the argument is ignored.
1883 /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
1884 /// also be ComplexX87.
1885 void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
1886 bool isNamedArg) const;
1888 llvm::Type *GetByteVectorType(QualType Ty) const;
1889 llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType,
1890 unsigned IROffset, QualType SourceTy,
1891 unsigned SourceOffset) const;
1892 llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType,
1893 unsigned IROffset, QualType SourceTy,
1894 unsigned SourceOffset) const;
1896 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1897 /// such that the argument will be returned in memory.
1898 ABIArgInfo getIndirectReturnResult(QualType Ty) const;
1900 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1901 /// such that the argument will be passed in memory.
1903 /// \param freeIntRegs - The number of free integer registers remaining
1905 ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const;
1907 ABIArgInfo classifyReturnType(QualType RetTy) const;
1909 ABIArgInfo classifyArgumentType(QualType Ty,
1910 unsigned freeIntRegs,
1911 unsigned &neededInt,
1912 unsigned &neededSSE,
1913 bool isNamedArg) const;
1915 bool IsIllegalVectorType(QualType Ty) const;
1917 /// The 0.98 ABI revision clarified a lot of ambiguities,
1918 /// unfortunately in ways that were not always consistent with
1919 /// certain previous compilers. In particular, platforms which
1920 /// required strict binary compatibility with older versions of GCC
1921 /// may need to exempt themselves.
1922 bool honorsRevision0_98() const {
1923 return !getTarget().getTriple().isOSDarwin();
1926 /// GCC classifies <1 x long long> as SSE but compatibility with older clang
1927 // compilers require us to classify it as INTEGER.
1928 bool classifyIntegerMMXAsSSE() const {
1929 const llvm::Triple &Triple = getTarget().getTriple();
1930 if (Triple.isOSDarwin() || Triple.getOS() == llvm::Triple::PS4)
1932 if (Triple.isOSFreeBSD() && Triple.getOSMajorVersion() >= 10)
1937 X86AVXABILevel AVXLevel;
1938 // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on
1940 bool Has64BitPointers;
1943 X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) :
1944 SwiftABIInfo(CGT), AVXLevel(AVXLevel),
1945 Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) {
1948 bool isPassedUsingAVXType(QualType type) const {
1949 unsigned neededInt, neededSSE;
1950 // The freeIntRegs argument doesn't matter here.
1951 ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE,
1952 /*isNamedArg*/true);
1953 if (info.isDirect()) {
1954 llvm::Type *ty = info.getCoerceToType();
1955 if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty))
1956 return (vectorTy->getBitWidth() > 128);
1961 void computeInfo(CGFunctionInfo &FI) const override;
1963 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1964 QualType Ty) const override;
1965 Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
1966 QualType Ty) const override;
1968 bool has64BitPointers() const {
1969 return Has64BitPointers;
1972 bool shouldPassIndirectlyForSwift(CharUnits totalSize,
1973 ArrayRef<llvm::Type*> scalars,
1974 bool asReturnValue) const override {
1975 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
1979 /// WinX86_64ABIInfo - The Windows X86_64 ABI information.
1980 class WinX86_64ABIInfo : public ABIInfo {
1982 WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT)
1984 IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {}
1986 void computeInfo(CGFunctionInfo &FI) const override;
1988 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1989 QualType Ty) const override;
1991 bool isHomogeneousAggregateBaseType(QualType Ty) const override {
1992 // FIXME: Assumes vectorcall is in use.
1993 return isX86VectorTypeForVectorCall(getContext(), Ty);
1996 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
1997 uint64_t NumMembers) const override {
1998 // FIXME: Assumes vectorcall is in use.
1999 return isX86VectorCallAggregateSmallEnough(NumMembers);
2003 ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs,
2004 bool IsReturnType) const;
2009 class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2011 X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2012 : TargetCodeGenInfo(new X86_64ABIInfo(CGT, AVXLevel)) {}
2014 const X86_64ABIInfo &getABIInfo() const {
2015 return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo());
2018 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2022 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2023 llvm::Value *Address) const override {
2024 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2026 // 0-15 are the 16 integer registers.
2028 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2032 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
2033 StringRef Constraint,
2034 llvm::Type* Ty) const override {
2035 return X86AdjustInlineAsmType(CGF, Constraint, Ty);
2038 bool isNoProtoCallVariadic(const CallArgList &args,
2039 const FunctionNoProtoType *fnType) const override {
2040 // The default CC on x86-64 sets %al to the number of SSA
2041 // registers used, and GCC sets this when calling an unprototyped
2042 // function, so we override the default behavior. However, don't do
2043 // that when AVX types are involved: the ABI explicitly states it is
2044 // undefined, and it doesn't work in practice because of how the ABI
2045 // defines varargs anyway.
2046 if (fnType->getCallConv() == CC_C) {
2047 bool HasAVXType = false;
2048 for (CallArgList::const_iterator
2049 it = args.begin(), ie = args.end(); it != ie; ++it) {
2050 if (getABIInfo().isPassedUsingAVXType(it->Ty)) {
2060 return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType);
2064 getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
2066 if (getABIInfo().has64BitPointers())
2067 Sig = (0xeb << 0) | // jmp rel8
2068 (0x0a << 8) | // .+0x0c
2072 Sig = (0xeb << 0) | // jmp rel8
2073 (0x06 << 8) | // .+0x08
2076 return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
2079 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2080 CodeGen::CodeGenModule &CGM) const override {
2081 if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2082 if (FD->hasAttr<AnyX86InterruptAttr>()) {
2083 llvm::Function *Fn = cast<llvm::Function>(GV);
2084 Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2090 class PS4TargetCodeGenInfo : public X86_64TargetCodeGenInfo {
2092 PS4TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2093 : X86_64TargetCodeGenInfo(CGT, AVXLevel) {}
2095 void getDependentLibraryOption(llvm::StringRef Lib,
2096 llvm::SmallString<24> &Opt) const override {
2098 // If the argument contains a space, enclose it in quotes.
2099 if (Lib.find(" ") != StringRef::npos)
2100 Opt += "\"" + Lib.str() + "\"";
2106 static std::string qualifyWindowsLibrary(llvm::StringRef Lib) {
2107 // If the argument does not end in .lib, automatically add the suffix.
2108 // If the argument contains a space, enclose it in quotes.
2109 // This matches the behavior of MSVC.
2110 bool Quote = (Lib.find(" ") != StringRef::npos);
2111 std::string ArgStr = Quote ? "\"" : "";
2113 if (!Lib.endswith_lower(".lib"))
2115 ArgStr += Quote ? "\"" : "";
2119 class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
2121 WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2122 bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
2123 unsigned NumRegisterParameters)
2124 : X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
2125 Win32StructABI, NumRegisterParameters, false) {}
2127 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2128 CodeGen::CodeGenModule &CGM) const override;
2130 void getDependentLibraryOption(llvm::StringRef Lib,
2131 llvm::SmallString<24> &Opt) const override {
2132 Opt = "/DEFAULTLIB:";
2133 Opt += qualifyWindowsLibrary(Lib);
2136 void getDetectMismatchOption(llvm::StringRef Name,
2137 llvm::StringRef Value,
2138 llvm::SmallString<32> &Opt) const override {
2139 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2143 static void addStackProbeSizeTargetAttribute(const Decl *D,
2144 llvm::GlobalValue *GV,
2145 CodeGen::CodeGenModule &CGM) {
2146 if (D && isa<FunctionDecl>(D)) {
2147 if (CGM.getCodeGenOpts().StackProbeSize != 4096) {
2148 llvm::Function *Fn = cast<llvm::Function>(GV);
2150 Fn->addFnAttr("stack-probe-size",
2151 llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
2156 void WinX86_32TargetCodeGenInfo::setTargetAttributes(const Decl *D,
2157 llvm::GlobalValue *GV,
2158 CodeGen::CodeGenModule &CGM) const {
2159 X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2161 addStackProbeSizeTargetAttribute(D, GV, CGM);
2164 class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2166 WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2167 X86AVXABILevel AVXLevel)
2168 : TargetCodeGenInfo(new WinX86_64ABIInfo(CGT)) {}
2170 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2171 CodeGen::CodeGenModule &CGM) const override;
2173 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2177 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2178 llvm::Value *Address) const override {
2179 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2181 // 0-15 are the 16 integer registers.
2183 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2187 void getDependentLibraryOption(llvm::StringRef Lib,
2188 llvm::SmallString<24> &Opt) const override {
2189 Opt = "/DEFAULTLIB:";
2190 Opt += qualifyWindowsLibrary(Lib);
2193 void getDetectMismatchOption(llvm::StringRef Name,
2194 llvm::StringRef Value,
2195 llvm::SmallString<32> &Opt) const override {
2196 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2200 void WinX86_64TargetCodeGenInfo::setTargetAttributes(const Decl *D,
2201 llvm::GlobalValue *GV,
2202 CodeGen::CodeGenModule &CGM) const {
2203 TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2205 if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2206 if (FD->hasAttr<AnyX86InterruptAttr>()) {
2207 llvm::Function *Fn = cast<llvm::Function>(GV);
2208 Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2212 addStackProbeSizeTargetAttribute(D, GV, CGM);
2216 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
2218 // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
2220 // (a) If one of the classes is Memory, the whole argument is passed in
2223 // (b) If X87UP is not preceded by X87, the whole argument is passed in
2226 // (c) If the size of the aggregate exceeds two eightbytes and the first
2227 // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
2228 // argument is passed in memory. NOTE: This is necessary to keep the
2229 // ABI working for processors that don't support the __m256 type.
2231 // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
2233 // Some of these are enforced by the merging logic. Others can arise
2234 // only with unions; for example:
2235 // union { _Complex double; unsigned; }
2237 // Note that clauses (b) and (c) were added in 0.98.
2241 if (Hi == X87Up && Lo != X87 && honorsRevision0_98())
2243 if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp))
2245 if (Hi == SSEUp && Lo != SSE)
2249 X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) {
2250 // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
2251 // classified recursively so that always two fields are
2252 // considered. The resulting class is calculated according to
2253 // the classes of the fields in the eightbyte:
2255 // (a) If both classes are equal, this is the resulting class.
2257 // (b) If one of the classes is NO_CLASS, the resulting class is
2260 // (c) If one of the classes is MEMORY, the result is the MEMORY
2263 // (d) If one of the classes is INTEGER, the result is the
2266 // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class,
2267 // MEMORY is used as class.
2269 // (f) Otherwise class SSE is used.
2271 // Accum should never be memory (we should have returned) or
2272 // ComplexX87 (because this cannot be passed in a structure).
2273 assert((Accum != Memory && Accum != ComplexX87) &&
2274 "Invalid accumulated classification during merge.");
2275 if (Accum == Field || Field == NoClass)
2277 if (Field == Memory)
2279 if (Accum == NoClass)
2281 if (Accum == Integer || Field == Integer)
2283 if (Field == X87 || Field == X87Up || Field == ComplexX87 ||
2284 Accum == X87 || Accum == X87Up)
2289 void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase,
2290 Class &Lo, Class &Hi, bool isNamedArg) const {
2291 // FIXME: This code can be simplified by introducing a simple value class for
2292 // Class pairs with appropriate constructor methods for the various
2295 // FIXME: Some of the split computations are wrong; unaligned vectors
2296 // shouldn't be passed in registers for example, so there is no chance they
2297 // can straddle an eightbyte. Verify & simplify.
2301 Class &Current = OffsetBase < 64 ? Lo : Hi;
2304 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
2305 BuiltinType::Kind k = BT->getKind();
2307 if (k == BuiltinType::Void) {
2309 } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) {
2312 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
2314 } else if (k == BuiltinType::Float || k == BuiltinType::Double) {
2316 } else if (k == BuiltinType::LongDouble) {
2317 const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2318 if (LDF == &llvm::APFloat::IEEEquad) {
2321 } else if (LDF == &llvm::APFloat::x87DoubleExtended) {
2324 } else if (LDF == &llvm::APFloat::IEEEdouble) {
2327 llvm_unreachable("unexpected long double representation!");
2329 // FIXME: _Decimal32 and _Decimal64 are SSE.
2330 // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
2334 if (const EnumType *ET = Ty->getAs<EnumType>()) {
2335 // Classify the underlying integer type.
2336 classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
2340 if (Ty->hasPointerRepresentation()) {
2345 if (Ty->isMemberPointerType()) {
2346 if (Ty->isMemberFunctionPointerType()) {
2347 if (Has64BitPointers) {
2348 // If Has64BitPointers, this is an {i64, i64}, so classify both
2352 // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
2353 // straddles an eightbyte boundary, Hi should be classified as well.
2354 uint64_t EB_FuncPtr = (OffsetBase) / 64;
2355 uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
2356 if (EB_FuncPtr != EB_ThisAdj) {
2368 if (const VectorType *VT = Ty->getAs<VectorType>()) {
2369 uint64_t Size = getContext().getTypeSize(VT);
2370 if (Size == 1 || Size == 8 || Size == 16 || Size == 32) {
2371 // gcc passes the following as integer:
2372 // 4 bytes - <4 x char>, <2 x short>, <1 x int>, <1 x float>
2373 // 2 bytes - <2 x char>, <1 x short>
2374 // 1 byte - <1 x char>
2377 // If this type crosses an eightbyte boundary, it should be
2379 uint64_t EB_Lo = (OffsetBase) / 64;
2380 uint64_t EB_Hi = (OffsetBase + Size - 1) / 64;
2383 } else if (Size == 64) {
2384 QualType ElementType = VT->getElementType();
2386 // gcc passes <1 x double> in memory. :(
2387 if (ElementType->isSpecificBuiltinType(BuiltinType::Double))
2390 // gcc passes <1 x long long> as SSE but clang used to unconditionally
2391 // pass them as integer. For platforms where clang is the de facto
2392 // platform compiler, we must continue to use integer.
2393 if (!classifyIntegerMMXAsSSE() &&
2394 (ElementType->isSpecificBuiltinType(BuiltinType::LongLong) ||
2395 ElementType->isSpecificBuiltinType(BuiltinType::ULongLong) ||
2396 ElementType->isSpecificBuiltinType(BuiltinType::Long) ||
2397 ElementType->isSpecificBuiltinType(BuiltinType::ULong)))
2402 // If this type crosses an eightbyte boundary, it should be
2404 if (OffsetBase && OffsetBase != 64)
2406 } else if (Size == 128 ||
2407 (isNamedArg && Size <= getNativeVectorSizeForAVXABI(AVXLevel))) {
2408 // Arguments of 256-bits are split into four eightbyte chunks. The
2409 // least significant one belongs to class SSE and all the others to class
2410 // SSEUP. The original Lo and Hi design considers that types can't be
2411 // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
2412 // This design isn't correct for 256-bits, but since there're no cases
2413 // where the upper parts would need to be inspected, avoid adding
2414 // complexity and just consider Hi to match the 64-256 part.
2416 // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
2417 // registers if they are "named", i.e. not part of the "..." of a
2418 // variadic function.
2420 // Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are
2421 // split into eight eightbyte chunks, one SSE and seven SSEUP.
2428 if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
2429 QualType ET = getContext().getCanonicalType(CT->getElementType());
2431 uint64_t Size = getContext().getTypeSize(Ty);
2432 if (ET->isIntegralOrEnumerationType()) {
2435 else if (Size <= 128)
2437 } else if (ET == getContext().FloatTy) {
2439 } else if (ET == getContext().DoubleTy) {
2441 } else if (ET == getContext().LongDoubleTy) {
2442 const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2443 if (LDF == &llvm::APFloat::IEEEquad)
2445 else if (LDF == &llvm::APFloat::x87DoubleExtended)
2446 Current = ComplexX87;
2447 else if (LDF == &llvm::APFloat::IEEEdouble)
2450 llvm_unreachable("unexpected long double representation!");
2453 // If this complex type crosses an eightbyte boundary then it
2455 uint64_t EB_Real = (OffsetBase) / 64;
2456 uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64;
2457 if (Hi == NoClass && EB_Real != EB_Imag)
2463 if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
2464 // Arrays are treated like structures.
2466 uint64_t Size = getContext().getTypeSize(Ty);
2468 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2469 // than four eightbytes, ..., it has class MEMORY.
2473 // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
2474 // fields, it has class MEMORY.
2476 // Only need to check alignment of array base.
2477 if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
2480 // Otherwise implement simplified merge. We could be smarter about
2481 // this, but it isn't worth it and would be harder to verify.
2483 uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
2484 uint64_t ArraySize = AT->getSize().getZExtValue();
2486 // The only case a 256-bit wide vector could be used is when the array
2487 // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2488 // to work for sizes wider than 128, early check and fallback to memory.
2489 if (Size > 128 && EltSize != 256)
2492 for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) {
2493 Class FieldLo, FieldHi;
2494 classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
2495 Lo = merge(Lo, FieldLo);
2496 Hi = merge(Hi, FieldHi);
2497 if (Lo == Memory || Hi == Memory)
2501 postMerge(Size, Lo, Hi);
2502 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
2506 if (const RecordType *RT = Ty->getAs<RecordType>()) {
2507 uint64_t Size = getContext().getTypeSize(Ty);
2509 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2510 // than four eightbytes, ..., it has class MEMORY.
2514 // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
2515 // copy constructor or a non-trivial destructor, it is passed by invisible
2517 if (getRecordArgABI(RT, getCXXABI()))
2520 const RecordDecl *RD = RT->getDecl();
2522 // Assume variable sized types are passed in memory.
2523 if (RD->hasFlexibleArrayMember())
2526 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
2528 // Reset Lo class, this will be recomputed.
2531 // If this is a C++ record, classify the bases first.
2532 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2533 for (const auto &I : CXXRD->bases()) {
2534 assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2535 "Unexpected base class!");
2536 const CXXRecordDecl *Base =
2537 cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
2539 // Classify this field.
2541 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
2542 // single eightbyte, each is classified separately. Each eightbyte gets
2543 // initialized to class NO_CLASS.
2544 Class FieldLo, FieldHi;
2546 OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base));
2547 classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
2548 Lo = merge(Lo, FieldLo);
2549 Hi = merge(Hi, FieldHi);
2550 if (Lo == Memory || Hi == Memory) {
2551 postMerge(Size, Lo, Hi);
2557 // Classify the fields one at a time, merging the results.
2559 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2560 i != e; ++i, ++idx) {
2561 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2562 bool BitField = i->isBitField();
2564 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
2565 // four eightbytes, or it contains unaligned fields, it has class MEMORY.
2567 // The only case a 256-bit wide vector could be used is when the struct
2568 // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2569 // to work for sizes wider than 128, early check and fallback to memory.
2571 if (Size > 128 && getContext().getTypeSize(i->getType()) != 256) {
2573 postMerge(Size, Lo, Hi);
2576 // Note, skip this test for bit-fields, see below.
2577 if (!BitField && Offset % getContext().getTypeAlign(i->getType())) {
2579 postMerge(Size, Lo, Hi);
2583 // Classify this field.
2585 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
2586 // exceeds a single eightbyte, each is classified
2587 // separately. Each eightbyte gets initialized to class
2589 Class FieldLo, FieldHi;
2591 // Bit-fields require special handling, they do not force the
2592 // structure to be passed in memory even if unaligned, and
2593 // therefore they can straddle an eightbyte.
2595 // Ignore padding bit-fields.
2596 if (i->isUnnamedBitfield())
2599 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2600 uint64_t Size = i->getBitWidthValue(getContext());
2602 uint64_t EB_Lo = Offset / 64;
2603 uint64_t EB_Hi = (Offset + Size - 1) / 64;
2606 assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes.");
2611 FieldHi = EB_Hi ? Integer : NoClass;
2614 classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
2615 Lo = merge(Lo, FieldLo);
2616 Hi = merge(Hi, FieldHi);
2617 if (Lo == Memory || Hi == Memory)
2621 postMerge(Size, Lo, Hi);
2625 ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const {
2626 // If this is a scalar LLVM value then assume LLVM will pass it in the right
2628 if (!isAggregateTypeForABI(Ty)) {
2629 // Treat an enum type as its underlying type.
2630 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2631 Ty = EnumTy->getDecl()->getIntegerType();
2633 return (Ty->isPromotableIntegerType() ?
2634 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
2637 return getNaturalAlignIndirect(Ty);
2640 bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const {
2641 if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
2642 uint64_t Size = getContext().getTypeSize(VecTy);
2643 unsigned LargestVector = getNativeVectorSizeForAVXABI(AVXLevel);
2644 if (Size <= 64 || Size > LargestVector)
2651 ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty,
2652 unsigned freeIntRegs) const {
2653 // If this is a scalar LLVM value then assume LLVM will pass it in the right
2656 // This assumption is optimistic, as there could be free registers available
2657 // when we need to pass this argument in memory, and LLVM could try to pass
2658 // the argument in the free register. This does not seem to happen currently,
2659 // but this code would be much safer if we could mark the argument with
2660 // 'onstack'. See PR12193.
2661 if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty)) {
2662 // Treat an enum type as its underlying type.
2663 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2664 Ty = EnumTy->getDecl()->getIntegerType();
2666 return (Ty->isPromotableIntegerType() ?
2667 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
2670 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
2671 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
2673 // Compute the byval alignment. We specify the alignment of the byval in all
2674 // cases so that the mid-level optimizer knows the alignment of the byval.
2675 unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U);
2677 // Attempt to avoid passing indirect results using byval when possible. This
2678 // is important for good codegen.
2680 // We do this by coercing the value into a scalar type which the backend can
2681 // handle naturally (i.e., without using byval).
2683 // For simplicity, we currently only do this when we have exhausted all of the
2684 // free integer registers. Doing this when there are free integer registers
2685 // would require more care, as we would have to ensure that the coerced value
2686 // did not claim the unused register. That would require either reording the
2687 // arguments to the function (so that any subsequent inreg values came first),
2688 // or only doing this optimization when there were no following arguments that
2691 // We currently expect it to be rare (particularly in well written code) for
2692 // arguments to be passed on the stack when there are still free integer
2693 // registers available (this would typically imply large structs being passed
2694 // by value), so this seems like a fair tradeoff for now.
2696 // We can revisit this if the backend grows support for 'onstack' parameter
2697 // attributes. See PR12193.
2698 if (freeIntRegs == 0) {
2699 uint64_t Size = getContext().getTypeSize(Ty);
2701 // If this type fits in an eightbyte, coerce it into the matching integral
2702 // type, which will end up on the stack (with alignment 8).
2703 if (Align == 8 && Size <= 64)
2704 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
2708 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align));
2711 /// The ABI specifies that a value should be passed in a full vector XMM/YMM
2712 /// register. Pick an LLVM IR type that will be passed as a vector register.
2713 llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const {
2714 // Wrapper structs/arrays that only contain vectors are passed just like
2715 // vectors; strip them off if present.
2716 if (const Type *InnerTy = isSingleElementStruct(Ty, getContext()))
2717 Ty = QualType(InnerTy, 0);
2719 llvm::Type *IRType = CGT.ConvertType(Ty);
2720 if (isa<llvm::VectorType>(IRType) ||
2721 IRType->getTypeID() == llvm::Type::FP128TyID)
2724 // We couldn't find the preferred IR vector type for 'Ty'.
2725 uint64_t Size = getContext().getTypeSize(Ty);
2726 assert((Size == 128 || Size == 256) && "Invalid type found!");
2728 // Return a LLVM IR vector type based on the size of 'Ty'.
2729 return llvm::VectorType::get(llvm::Type::getDoubleTy(getVMContext()),
2733 /// BitsContainNoUserData - Return true if the specified [start,end) bit range
2734 /// is known to either be off the end of the specified type or being in
2735 /// alignment padding. The user type specified is known to be at most 128 bits
2736 /// in size, and have passed through X86_64ABIInfo::classify with a successful
2737 /// classification that put one of the two halves in the INTEGER class.
2739 /// It is conservatively correct to return false.
2740 static bool BitsContainNoUserData(QualType Ty, unsigned StartBit,
2741 unsigned EndBit, ASTContext &Context) {
2742 // If the bytes being queried are off the end of the type, there is no user
2743 // data hiding here. This handles analysis of builtins, vectors and other
2744 // types that don't contain interesting padding.
2745 unsigned TySize = (unsigned)Context.getTypeSize(Ty);
2746 if (TySize <= StartBit)
2749 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) {
2750 unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
2751 unsigned NumElts = (unsigned)AT->getSize().getZExtValue();
2753 // Check each element to see if the element overlaps with the queried range.
2754 for (unsigned i = 0; i != NumElts; ++i) {
2755 // If the element is after the span we care about, then we're done..
2756 unsigned EltOffset = i*EltSize;
2757 if (EltOffset >= EndBit) break;
2759 unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0;
2760 if (!BitsContainNoUserData(AT->getElementType(), EltStart,
2761 EndBit-EltOffset, Context))
2764 // If it overlaps no elements, then it is safe to process as padding.
2768 if (const RecordType *RT = Ty->getAs<RecordType>()) {
2769 const RecordDecl *RD = RT->getDecl();
2770 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
2772 // If this is a C++ record, check the bases first.
2773 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2774 for (const auto &I : CXXRD->bases()) {
2775 assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2776 "Unexpected base class!");
2777 const CXXRecordDecl *Base =
2778 cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
2780 // If the base is after the span we care about, ignore it.
2781 unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base));
2782 if (BaseOffset >= EndBit) continue;
2784 unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0;
2785 if (!BitsContainNoUserData(I.getType(), BaseStart,
2786 EndBit-BaseOffset, Context))
2791 // Verify that no field has data that overlaps the region of interest. Yes
2792 // this could be sped up a lot by being smarter about queried fields,
2793 // however we're only looking at structs up to 16 bytes, so we don't care
2796 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2797 i != e; ++i, ++idx) {
2798 unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx);
2800 // If we found a field after the region we care about, then we're done.
2801 if (FieldOffset >= EndBit) break;
2803 unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0;
2804 if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
2809 // If nothing in this record overlapped the area of interest, then we're
2817 /// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a
2818 /// float member at the specified offset. For example, {int,{float}} has a
2819 /// float at offset 4. It is conservatively correct for this routine to return
2821 static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset,
2822 const llvm::DataLayout &TD) {
2823 // Base case if we find a float.
2824 if (IROffset == 0 && IRType->isFloatTy())
2827 // If this is a struct, recurse into the field at the specified offset.
2828 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
2829 const llvm::StructLayout *SL = TD.getStructLayout(STy);
2830 unsigned Elt = SL->getElementContainingOffset(IROffset);
2831 IROffset -= SL->getElementOffset(Elt);
2832 return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD);
2835 // If this is an array, recurse into the field at the specified offset.
2836 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
2837 llvm::Type *EltTy = ATy->getElementType();
2838 unsigned EltSize = TD.getTypeAllocSize(EltTy);
2839 IROffset -= IROffset/EltSize*EltSize;
2840 return ContainsFloatAtOffset(EltTy, IROffset, TD);
2847 /// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
2848 /// low 8 bytes of an XMM register, corresponding to the SSE class.
2849 llvm::Type *X86_64ABIInfo::
2850 GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset,
2851 QualType SourceTy, unsigned SourceOffset) const {
2852 // The only three choices we have are either double, <2 x float>, or float. We
2853 // pass as float if the last 4 bytes is just padding. This happens for
2854 // structs that contain 3 floats.
2855 if (BitsContainNoUserData(SourceTy, SourceOffset*8+32,
2856 SourceOffset*8+64, getContext()))
2857 return llvm::Type::getFloatTy(getVMContext());
2859 // We want to pass as <2 x float> if the LLVM IR type contains a float at
2860 // offset+0 and offset+4. Walk the LLVM IR type to find out if this is the
2862 if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) &&
2863 ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout()))
2864 return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2);
2866 return llvm::Type::getDoubleTy(getVMContext());
2870 /// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
2871 /// an 8-byte GPR. This means that we either have a scalar or we are talking
2872 /// about the high or low part of an up-to-16-byte struct. This routine picks
2873 /// the best LLVM IR type to represent this, which may be i64 or may be anything
2874 /// else that the backend will pass in a GPR that works better (e.g. i8, %foo*,
2877 /// PrefType is an LLVM IR type that corresponds to (part of) the IR type for
2878 /// the source type. IROffset is an offset in bytes into the LLVM IR type that
2879 /// the 8-byte value references. PrefType may be null.
2881 /// SourceTy is the source-level type for the entire argument. SourceOffset is
2882 /// an offset into this that we're processing (which is always either 0 or 8).
2884 llvm::Type *X86_64ABIInfo::
2885 GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
2886 QualType SourceTy, unsigned SourceOffset) const {
2887 // If we're dealing with an un-offset LLVM IR type, then it means that we're
2888 // returning an 8-byte unit starting with it. See if we can safely use it.
2889 if (IROffset == 0) {
2890 // Pointers and int64's always fill the 8-byte unit.
2891 if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) ||
2892 IRType->isIntegerTy(64))
2895 // If we have a 1/2/4-byte integer, we can use it only if the rest of the
2896 // goodness in the source type is just tail padding. This is allowed to
2897 // kick in for struct {double,int} on the int, but not on
2898 // struct{double,int,int} because we wouldn't return the second int. We
2899 // have to do this analysis on the source type because we can't depend on
2900 // unions being lowered a specific way etc.
2901 if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) ||
2902 IRType->isIntegerTy(32) ||
2903 (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) {
2904 unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 :
2905 cast<llvm::IntegerType>(IRType)->getBitWidth();
2907 if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth,
2908 SourceOffset*8+64, getContext()))
2913 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
2914 // If this is a struct, recurse into the field at the specified offset.
2915 const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy);
2916 if (IROffset < SL->getSizeInBytes()) {
2917 unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
2918 IROffset -= SL->getElementOffset(FieldIdx);
2920 return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
2921 SourceTy, SourceOffset);
2925 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
2926 llvm::Type *EltTy = ATy->getElementType();
2927 unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
2928 unsigned EltOffset = IROffset/EltSize*EltSize;
2929 return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
2933 // Okay, we don't have any better idea of what to pass, so we pass this in an
2934 // integer register that isn't too big to fit the rest of the struct.
2935 unsigned TySizeInBytes =
2936 (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity();
2938 assert(TySizeInBytes != SourceOffset && "Empty field?");
2940 // It is always safe to classify this as an integer type up to i64 that
2941 // isn't larger than the structure.
2942 return llvm::IntegerType::get(getVMContext(),
2943 std::min(TySizeInBytes-SourceOffset, 8U)*8);
2947 /// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
2948 /// be used as elements of a two register pair to pass or return, return a
2949 /// first class aggregate to represent them. For example, if the low part of
2950 /// a by-value argument should be passed as i32* and the high part as float,
2951 /// return {i32*, float}.
2953 GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi,
2954 const llvm::DataLayout &TD) {
2955 // In order to correctly satisfy the ABI, we need to the high part to start
2956 // at offset 8. If the high and low parts we inferred are both 4-byte types
2957 // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have
2958 // the second element at offset 8. Check for this:
2959 unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo);
2960 unsigned HiAlign = TD.getABITypeAlignment(Hi);
2961 unsigned HiStart = llvm::alignTo(LoSize, HiAlign);
2962 assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!");
2964 // To handle this, we have to increase the size of the low part so that the
2965 // second element will start at an 8 byte offset. We can't increase the size
2966 // of the second element because it might make us access off the end of the
2969 // There are usually two sorts of types the ABI generation code can produce
2970 // for the low part of a pair that aren't 8 bytes in size: float or
2971 // i8/i16/i32. This can also include pointers when they are 32-bit (X32 and
2973 // Promote these to a larger type.
2974 if (Lo->isFloatTy())
2975 Lo = llvm::Type::getDoubleTy(Lo->getContext());
2977 assert((Lo->isIntegerTy() || Lo->isPointerTy())
2978 && "Invalid/unknown lo type");
2979 Lo = llvm::Type::getInt64Ty(Lo->getContext());
2983 llvm::StructType *Result = llvm::StructType::get(Lo, Hi, nullptr);
2986 // Verify that the second element is at an 8-byte offset.
2987 assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
2988 "Invalid x86-64 argument pair!");
2992 ABIArgInfo X86_64ABIInfo::
2993 classifyReturnType(QualType RetTy) const {
2994 // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
2995 // classification algorithm.
2996 X86_64ABIInfo::Class Lo, Hi;
2997 classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);
2999 // Check some invariants.
3000 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3001 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3003 llvm::Type *ResType = nullptr;
3007 return ABIArgInfo::getIgnore();
3008 // If the low part is just padding, it takes no register, leave ResType
3010 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3011 "Unknown missing lo part");
3016 llvm_unreachable("Invalid classification for lo word.");
3018 // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
3021 return getIndirectReturnResult(RetTy);
3023 // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
3024 // available register of the sequence %rax, %rdx is used.
3026 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3028 // If we have a sign or zero extended integer, make sure to return Extend
3029 // so that the parameter gets the right LLVM IR attributes.
3030 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3031 // Treat an enum type as its underlying type.
3032 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
3033 RetTy = EnumTy->getDecl()->getIntegerType();
3035 if (RetTy->isIntegralOrEnumerationType() &&
3036 RetTy->isPromotableIntegerType())
3037 return ABIArgInfo::getExtend();
3041 // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
3042 // available SSE register of the sequence %xmm0, %xmm1 is used.
3044 ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3047 // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
3048 // returned on the X87 stack in %st0 as 80-bit x87 number.
3050 ResType = llvm::Type::getX86_FP80Ty(getVMContext());
3053 // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
3054 // part of the value is returned in %st0 and the imaginary part in
3057 assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.");
3058 ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()),
3059 llvm::Type::getX86_FP80Ty(getVMContext()),
3064 llvm::Type *HighPart = nullptr;
3066 // Memory was handled previously and X87 should
3067 // never occur as a hi class.
3070 llvm_unreachable("Invalid classification for hi word.");
3072 case ComplexX87: // Previously handled.
3077 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3078 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3079 return ABIArgInfo::getDirect(HighPart, 8);
3082 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3083 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3084 return ABIArgInfo::getDirect(HighPart, 8);
3087 // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
3088 // is passed in the next available eightbyte chunk if the last used
3091 // SSEUP should always be preceded by SSE, just widen.
3093 assert(Lo == SSE && "Unexpected SSEUp classification.");
3094 ResType = GetByteVectorType(RetTy);
3097 // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
3098 // returned together with the previous X87 value in %st0.
3100 // If X87Up is preceded by X87, we don't need to do
3101 // anything. However, in some cases with unions it may not be
3102 // preceded by X87. In such situations we follow gcc and pass the
3103 // extra bits in an SSE reg.
3105 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3106 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3107 return ABIArgInfo::getDirect(HighPart, 8);
3112 // If a high part was specified, merge it together with the low part. It is
3113 // known to pass in the high eightbyte of the result. We do this by forming a
3114 // first class struct aggregate with the high and low part: {low, high}
3116 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3118 return ABIArgInfo::getDirect(ResType);
3121 ABIArgInfo X86_64ABIInfo::classifyArgumentType(
3122 QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE,
3126 Ty = useFirstFieldIfTransparentUnion(Ty);
3128 X86_64ABIInfo::Class Lo, Hi;
3129 classify(Ty, 0, Lo, Hi, isNamedArg);
3131 // Check some invariants.
3132 // FIXME: Enforce these by construction.
3133 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3134 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3138 llvm::Type *ResType = nullptr;
3142 return ABIArgInfo::getIgnore();
3143 // If the low part is just padding, it takes no register, leave ResType
3145 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3146 "Unknown missing lo part");
3149 // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
3153 // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
3154 // COMPLEX_X87, it is passed in memory.
3157 if (getRecordArgABI(Ty, getCXXABI()) == CGCXXABI::RAA_Indirect)
3159 return getIndirectResult(Ty, freeIntRegs);
3163 llvm_unreachable("Invalid classification for lo word.");
3165 // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
3166 // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
3171 // Pick an 8-byte type based on the preferred type.
3172 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);
3174 // If we have a sign or zero extended integer, make sure to return Extend
3175 // so that the parameter gets the right LLVM IR attributes.
3176 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3177 // Treat an enum type as its underlying type.
3178 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3179 Ty = EnumTy->getDecl()->getIntegerType();
3181 if (Ty->isIntegralOrEnumerationType() &&
3182 Ty->isPromotableIntegerType())
3183 return ABIArgInfo::getExtend();
3188 // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
3189 // available SSE register is used, the registers are taken in the
3190 // order from %xmm0 to %xmm7.
3192 llvm::Type *IRType = CGT.ConvertType(Ty);
3193 ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);
3199 llvm::Type *HighPart = nullptr;
3201 // Memory was handled previously, ComplexX87 and X87 should
3202 // never occur as hi classes, and X87Up must be preceded by X87,
3203 // which is passed in memory.
3207 llvm_unreachable("Invalid classification for hi word.");
3209 case NoClass: break;
3213 // Pick an 8-byte type based on the preferred type.
3214 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3216 if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3217 return ABIArgInfo::getDirect(HighPart, 8);
3220 // X87Up generally doesn't occur here (long double is passed in
3221 // memory), except in situations involving unions.
3224 HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3226 if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3227 return ABIArgInfo::getDirect(HighPart, 8);
3232 // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
3233 // eightbyte is passed in the upper half of the last used SSE
3234 // register. This only happens when 128-bit vectors are passed.
3236 assert(Lo == SSE && "Unexpected SSEUp classification");
3237 ResType = GetByteVectorType(Ty);
3241 // If a high part was specified, merge it together with the low part. It is
3242 // known to pass in the high eightbyte of the result. We do this by forming a
3243 // first class struct aggregate with the high and low part: {low, high}
3245 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3247 return ABIArgInfo::getDirect(ResType);
3250 void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3252 if (!getCXXABI().classifyReturnType(FI))
3253 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
3255 // Keep track of the number of assigned registers.
3256 unsigned freeIntRegs = 6, freeSSERegs = 8;
3258 // If the return value is indirect, then the hidden argument is consuming one
3259 // integer register.
3260 if (FI.getReturnInfo().isIndirect())
3263 // The chain argument effectively gives us another free register.
3264 if (FI.isChainCall())
3267 unsigned NumRequiredArgs = FI.getNumRequiredArgs();
3268 // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
3269 // get assigned (in left-to-right order) for passing as follows...
3271 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
3272 it != ie; ++it, ++ArgNo) {
3273 bool IsNamedArg = ArgNo < NumRequiredArgs;
3275 unsigned neededInt, neededSSE;
3276 it->info = classifyArgumentType(it->type, freeIntRegs, neededInt,
3277 neededSSE, IsNamedArg);
3279 // AMD64-ABI 3.2.3p3: If there are no registers available for any
3280 // eightbyte of an argument, the whole argument is passed on the
3281 // stack. If registers have already been assigned for some
3282 // eightbytes of such an argument, the assignments get reverted.
3283 if (freeIntRegs >= neededInt && freeSSERegs >= neededSSE) {
3284 freeIntRegs -= neededInt;
3285 freeSSERegs -= neededSSE;
3287 it->info = getIndirectResult(it->type, freeIntRegs);
3292 static Address EmitX86_64VAArgFromMemory(CodeGenFunction &CGF,
3293 Address VAListAddr, QualType Ty) {
3294 Address overflow_arg_area_p = CGF.Builder.CreateStructGEP(
3295 VAListAddr, 2, CharUnits::fromQuantity(8), "overflow_arg_area_p");
3296 llvm::Value *overflow_arg_area =
3297 CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area");
3299 // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
3300 // byte boundary if alignment needed by type exceeds 8 byte boundary.
3301 // It isn't stated explicitly in the standard, but in practice we use
3302 // alignment greater than 16 where necessary.
3303 CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
3304 if (Align > CharUnits::fromQuantity(8)) {
3305 overflow_arg_area = emitRoundPointerUpToAlignment(CGF, overflow_arg_area,
3309 // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
3310 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3312 CGF.Builder.CreateBitCast(overflow_arg_area,
3313 llvm::PointerType::getUnqual(LTy));
3315 // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
3316 // l->overflow_arg_area + sizeof(type).
3317 // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
3318 // an 8 byte boundary.
3320 uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8;
3321 llvm::Value *Offset =
3322 llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7);
3323 overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset,
3324 "overflow_arg_area.next");
3325 CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);
3327 // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
3328 return Address(Res, Align);
3331 Address X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3332 QualType Ty) const {
3333 // Assume that va_list type is correct; should be pointer to LLVM type:
3337 // i8* overflow_arg_area;
3338 // i8* reg_save_area;
3340 unsigned neededInt, neededSSE;
3342 Ty = getContext().getCanonicalType(Ty);
3343 ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
3344 /*isNamedArg*/false);
3346 // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
3347 // in the registers. If not go to step 7.
3348 if (!neededInt && !neededSSE)
3349 return EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3351 // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
3352 // general purpose registers needed to pass type and num_fp to hold
3353 // the number of floating point registers needed.
3355 // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
3356 // registers. In the case: l->gp_offset > 48 - num_gp * 8 or
3357 // l->fp_offset > 304 - num_fp * 16 go to step 7.
3359 // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of
3360 // register save space).
3362 llvm::Value *InRegs = nullptr;
3363 Address gp_offset_p = Address::invalid(), fp_offset_p = Address::invalid();
3364 llvm::Value *gp_offset = nullptr, *fp_offset = nullptr;
3367 CGF.Builder.CreateStructGEP(VAListAddr, 0, CharUnits::Zero(),
3369 gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset");
3370 InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
3371 InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp");
3376 CGF.Builder.CreateStructGEP(VAListAddr, 1, CharUnits::fromQuantity(4),
3378 fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset");
3379 llvm::Value *FitsInFP =
3380 llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
3381 FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp");
3382 InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP;
3385 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
3386 llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
3387 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
3388 CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
3390 // Emit code to load the value if it was passed in registers.
3392 CGF.EmitBlock(InRegBlock);
3394 // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
3395 // an offset of l->gp_offset and/or l->fp_offset. This may require
3396 // copying to a temporary location in case the parameter is passed
3397 // in different register classes or requires an alignment greater
3398 // than 8 for general purpose registers and 16 for XMM registers.
3400 // FIXME: This really results in shameful code when we end up needing to
3401 // collect arguments from different places; often what should result in a
3402 // simple assembling of a structure from scattered addresses has many more
3403 // loads than necessary. Can we clean this up?
3404 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3405 llvm::Value *RegSaveArea = CGF.Builder.CreateLoad(
3406 CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(16)),
3409 Address RegAddr = Address::invalid();
3410 if (neededInt && neededSSE) {
3412 assert(AI.isDirect() && "Unexpected ABI info for mixed regs");
3413 llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType());
3414 Address Tmp = CGF.CreateMemTemp(Ty);
3415 Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3416 assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs");
3417 llvm::Type *TyLo = ST->getElementType(0);
3418 llvm::Type *TyHi = ST->getElementType(1);
3419 assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&
3420 "Unexpected ABI info for mixed regs");
3421 llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo);
3422 llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi);
3423 llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegSaveArea, gp_offset);
3424 llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegSaveArea, fp_offset);
3425 llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? FPAddr : GPAddr;
3426 llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? GPAddr : FPAddr;
3428 // Copy the first element.
3430 CGF.Builder.CreateDefaultAlignedLoad(
3431 CGF.Builder.CreateBitCast(RegLoAddr, PTyLo));
3432 CGF.Builder.CreateStore(V,
3433 CGF.Builder.CreateStructGEP(Tmp, 0, CharUnits::Zero()));
3435 // Copy the second element.
3436 V = CGF.Builder.CreateDefaultAlignedLoad(
3437 CGF.Builder.CreateBitCast(RegHiAddr, PTyHi));
3438 CharUnits Offset = CharUnits::fromQuantity(
3439 getDataLayout().getStructLayout(ST)->getElementOffset(1));
3440 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1, Offset));
3442 RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3443 } else if (neededInt) {
3444 RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, gp_offset),
3445 CharUnits::fromQuantity(8));
3446 RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3448 // Copy to a temporary if necessary to ensure the appropriate alignment.
3449 std::pair<CharUnits, CharUnits> SizeAlign =
3450 getContext().getTypeInfoInChars(Ty);
3451 uint64_t TySize = SizeAlign.first.getQuantity();
3452 CharUnits TyAlign = SizeAlign.second;
3454 // Copy into a temporary if the type is more aligned than the
3455 // register save area.
3456 if (TyAlign.getQuantity() > 8) {
3457 Address Tmp = CGF.CreateMemTemp(Ty);
3458 CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false);
3462 } else if (neededSSE == 1) {
3463 RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3464 CharUnits::fromQuantity(16));
3465 RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3467 assert(neededSSE == 2 && "Invalid number of needed registers!");
3468 // SSE registers are spaced 16 bytes apart in the register save
3469 // area, we need to collect the two eightbytes together.
3470 // The ABI isn't explicit about this, but it seems reasonable
3471 // to assume that the slots are 16-byte aligned, since the stack is
3472 // naturally 16-byte aligned and the prologue is expected to store
3473 // all the SSE registers to the RSA.
3474 Address RegAddrLo = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3475 CharUnits::fromQuantity(16));
3477 CGF.Builder.CreateConstInBoundsByteGEP(RegAddrLo,
3478 CharUnits::fromQuantity(16));
3479 llvm::Type *DoubleTy = CGF.DoubleTy;
3480 llvm::StructType *ST = llvm::StructType::get(DoubleTy, DoubleTy, nullptr);
3482 Address Tmp = CGF.CreateMemTemp(Ty);
3483 Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3484 V = CGF.Builder.CreateLoad(
3485 CGF.Builder.CreateElementBitCast(RegAddrLo, DoubleTy));
3486 CGF.Builder.CreateStore(V,
3487 CGF.Builder.CreateStructGEP(Tmp, 0, CharUnits::Zero()));
3488 V = CGF.Builder.CreateLoad(
3489 CGF.Builder.CreateElementBitCast(RegAddrHi, DoubleTy));
3490 CGF.Builder.CreateStore(V,
3491 CGF.Builder.CreateStructGEP(Tmp, 1, CharUnits::fromQuantity(8)));
3493 RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3496 // AMD64-ABI 3.5.7p5: Step 5. Set:
3497 // l->gp_offset = l->gp_offset + num_gp * 8
3498 // l->fp_offset = l->fp_offset + num_fp * 16.
3500 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8);
3501 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset),
3505 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16);
3506 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset),
3509 CGF.EmitBranch(ContBlock);
3511 // Emit code to load the value if it was passed in memory.
3513 CGF.EmitBlock(InMemBlock);
3514 Address MemAddr = EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3516 // Return the appropriate result.
3518 CGF.EmitBlock(ContBlock);
3519 Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, MemAddr, InMemBlock,
3524 Address X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
3525 QualType Ty) const {
3526 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
3527 CGF.getContext().getTypeInfoInChars(Ty),
3528 CharUnits::fromQuantity(8),
3529 /*allowHigherAlign*/ false);
3532 ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
3533 bool IsReturnType) const {
3535 if (Ty->isVoidType())
3536 return ABIArgInfo::getIgnore();
3538 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3539 Ty = EnumTy->getDecl()->getIntegerType();
3541 TypeInfo Info = getContext().getTypeInfo(Ty);
3542 uint64_t Width = Info.Width;
3543 CharUnits Align = getContext().toCharUnitsFromBits(Info.Align);
3545 const RecordType *RT = Ty->getAs<RecordType>();
3547 if (!IsReturnType) {
3548 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI()))
3549 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
3552 if (RT->getDecl()->hasFlexibleArrayMember())
3553 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3557 // vectorcall adds the concept of a homogenous vector aggregate, similar to
3559 const Type *Base = nullptr;
3560 uint64_t NumElts = 0;
3561 if (FreeSSERegs && isHomogeneousAggregate(Ty, Base, NumElts)) {
3562 if (FreeSSERegs >= NumElts) {
3563 FreeSSERegs -= NumElts;
3564 if (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())
3565 return ABIArgInfo::getDirect();
3566 return ABIArgInfo::getExpand();
3568 return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3572 if (Ty->isMemberPointerType()) {
3573 // If the member pointer is represented by an LLVM int or ptr, pass it
3575 llvm::Type *LLTy = CGT.ConvertType(Ty);
3576 if (LLTy->isPointerTy() || LLTy->isIntegerTy())
3577 return ABIArgInfo::getDirect();
3580 if (RT || Ty->isAnyComplexType() || Ty->isMemberPointerType()) {
3581 // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
3582 // not 1, 2, 4, or 8 bytes, must be passed by reference."
3583 if (Width > 64 || !llvm::isPowerOf2_64(Width))
3584 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3586 // Otherwise, coerce it to a small integer.
3587 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width));
3590 // Bool type is always extended to the ABI, other builtin types are not
3592 const BuiltinType *BT = Ty->getAs<BuiltinType>();
3593 if (BT && BT->getKind() == BuiltinType::Bool)
3594 return ABIArgInfo::getExtend();
3596 // Mingw64 GCC uses the old 80 bit extended precision floating point unit. It
3597 // passes them indirectly through memory.
3598 if (IsMingw64 && BT && BT->getKind() == BuiltinType::LongDouble) {
3599 const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
3600 if (LDF == &llvm::APFloat::x87DoubleExtended)
3601 return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3604 return ABIArgInfo::getDirect();
3607 void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3609 FI.getCallingConvention() == llvm::CallingConv::X86_VectorCall;
3611 // We can use up to 4 SSE return registers with vectorcall.
3612 unsigned FreeSSERegs = IsVectorCall ? 4 : 0;
3613 if (!getCXXABI().classifyReturnType(FI))
3614 FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true);
3616 // We can use up to 6 SSE register parameters with vectorcall.
3617 FreeSSERegs = IsVectorCall ? 6 : 0;
3618 for (auto &I : FI.arguments())
3619 I.info = classify(I.type, FreeSSERegs, false);
3622 Address WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3623 QualType Ty) const {
3624 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
3625 CGF.getContext().getTypeInfoInChars(Ty),
3626 CharUnits::fromQuantity(8),
3627 /*allowHigherAlign*/ false);
3632 /// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
3633 class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
3634 bool IsSoftFloatABI;
3636 PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI)
3637 : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI) {}
3639 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3640 QualType Ty) const override;
3643 class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
3645 PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI)
3646 : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI)) {}
3648 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
3649 // This is recovered from gcc output.
3650 return 1; // r1 is the dedicated stack pointer
3653 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3654 llvm::Value *Address) const override;
3659 // TODO: this implementation is now likely redundant with
3660 // DefaultABIInfo::EmitVAArg.
3661 Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
3662 QualType Ty) const {
3663 const unsigned OverflowLimit = 8;
3664 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
3665 // TODO: Implement this. For now ignore.
3667 return Address::invalid(); // FIXME?
3670 // struct __va_list_tag {
3671 // unsigned char gpr;
3672 // unsigned char fpr;
3673 // unsigned short reserved;
3674 // void *overflow_arg_area;
3675 // void *reg_save_area;
3678 bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;
3680 Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType();
3681 bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(Ty) == 64;
3683 // All aggregates are passed indirectly? That doesn't seem consistent
3684 // with the argument-lowering code.
3685 bool isIndirect = Ty->isAggregateType();
3687 CGBuilderTy &Builder = CGF.Builder;
3689 // The calling convention either uses 1-2 GPRs or 1 FPR.
3690 Address NumRegsAddr = Address::invalid();
3691 if (isInt || IsSoftFloatABI) {
3692 NumRegsAddr = Builder.CreateStructGEP(VAList, 0, CharUnits::Zero(), "gpr");
3694 NumRegsAddr = Builder.CreateStructGEP(VAList, 1, CharUnits::One(), "fpr");
3697 llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs");
3699 // "Align" the register count when TY is i64.
3700 if (isI64 || (isF64 && IsSoftFloatABI)) {
3701 NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1));
3702 NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U));
3706 Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond");
3708 llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
3709 llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
3710 llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
3712 Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
3714 llvm::Type *DirectTy = CGF.ConvertType(Ty);
3715 if (isIndirect) DirectTy = DirectTy->getPointerTo(0);
3717 // Case 1: consume registers.
3718 Address RegAddr = Address::invalid();
3720 CGF.EmitBlock(UsingRegs);
3722 Address RegSaveAreaPtr =
3723 Builder.CreateStructGEP(VAList, 4, CharUnits::fromQuantity(8));
3724 RegAddr = Address(Builder.CreateLoad(RegSaveAreaPtr),
3725 CharUnits::fromQuantity(8));
3726 assert(RegAddr.getElementType() == CGF.Int8Ty);
3728 // Floating-point registers start after the general-purpose registers.
3729 if (!(isInt || IsSoftFloatABI)) {
3730 RegAddr = Builder.CreateConstInBoundsByteGEP(RegAddr,
3731 CharUnits::fromQuantity(32));
3734 // Get the address of the saved value by scaling the number of
3735 // registers we've used by the number of
3736 CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8);
3737 llvm::Value *RegOffset =
3738 Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity()));
3739 RegAddr = Address(Builder.CreateInBoundsGEP(CGF.Int8Ty,
3740 RegAddr.getPointer(), RegOffset),
3741 RegAddr.getAlignment().alignmentOfArrayElement(RegSize));
3742 RegAddr = Builder.CreateElementBitCast(RegAddr, DirectTy);
3744 // Increase the used-register count.
3746 Builder.CreateAdd(NumRegs,
3747 Builder.getInt8((isI64 || (isF64 && IsSoftFloatABI)) ? 2 : 1));
3748 Builder.CreateStore(NumRegs, NumRegsAddr);
3750 CGF.EmitBranch(Cont);
3753 // Case 2: consume space in the overflow area.
3754 Address MemAddr = Address::invalid();
3756 CGF.EmitBlock(UsingOverflow);
3758 Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr);
3760 // Everything in the overflow area is rounded up to a size of at least 4.
3761 CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4);
3765 auto TypeInfo = CGF.getContext().getTypeInfoInChars(Ty);
3766 Size = TypeInfo.first.alignTo(OverflowAreaAlign);
3768 Size = CGF.getPointerSize();
3771 Address OverflowAreaAddr =
3772 Builder.CreateStructGEP(VAList, 3, CharUnits::fromQuantity(4));
3773 Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr, "argp.cur"),
3775 // Round up address of argument to alignment
3776 CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
3777 if (Align > OverflowAreaAlign) {
3778 llvm::Value *Ptr = OverflowArea.getPointer();
3779 OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),
3783 MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy);
3785 // Increase the overflow area.
3786 OverflowArea = Builder.CreateConstInBoundsByteGEP(OverflowArea, Size);
3787 Builder.CreateStore(OverflowArea.getPointer(), OverflowAreaAddr);
3788 CGF.EmitBranch(Cont);
3791 CGF.EmitBlock(Cont);
3793 // Merge the cases with a phi.
3794 Address Result = emitMergePHI(CGF, RegAddr, UsingRegs, MemAddr, UsingOverflow,
3797 // Load the pointer if the argument was passed indirectly.
3799 Result = Address(Builder.CreateLoad(Result, "aggr"),
3800 getContext().getTypeAlignInChars(Ty));
3807 PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3808 llvm::Value *Address) const {
3809 // This is calculated from the LLVM and GCC tables and verified
3810 // against gcc output. AFAIK all ABIs use the same encoding.
3812 CodeGen::CGBuilderTy &Builder = CGF.Builder;
3814 llvm::IntegerType *i8 = CGF.Int8Ty;
3815 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
3816 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
3817 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
3819 // 0-31: r0-31, the 4-byte general-purpose registers
3820 AssignToArrayRange(Builder, Address, Four8, 0, 31);
3822 // 32-63: fp0-31, the 8-byte floating-point registers
3823 AssignToArrayRange(Builder, Address, Eight8, 32, 63);
3825 // 64-76 are various 4-byte special-purpose registers:
3832 AssignToArrayRange(Builder, Address, Four8, 64, 76);
3834 // 77-108: v0-31, the 16-byte vector registers
3835 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
3842 AssignToArrayRange(Builder, Address, Four8, 109, 113);
3850 /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
3851 class PPC64_SVR4_ABIInfo : public ABIInfo {
3859 static const unsigned GPRBits = 64;
3862 bool IsSoftFloatABI;
3864 // A vector of float or double will be promoted to <4 x f32> or <4 x f64> and
3865 // will be passed in a QPX register.
3866 bool IsQPXVectorTy(const Type *Ty) const {
3870 if (const VectorType *VT = Ty->getAs<VectorType>()) {
3871 unsigned NumElements = VT->getNumElements();
3872 if (NumElements == 1)
3875 if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) {
3876 if (getContext().getTypeSize(Ty) <= 256)
3878 } else if (VT->getElementType()->
3879 isSpecificBuiltinType(BuiltinType::Float)) {
3880 if (getContext().getTypeSize(Ty) <= 128)
3888 bool IsQPXVectorTy(QualType Ty) const {
3889 return IsQPXVectorTy(Ty.getTypePtr());
3893 PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
3895 : ABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
3896 IsSoftFloatABI(SoftFloatABI) {}
3898 bool isPromotableTypeForABI(QualType Ty) const;
3899 CharUnits getParamTypeAlignment(QualType Ty) const;
3901 ABIArgInfo classifyReturnType(QualType RetTy) const;
3902 ABIArgInfo classifyArgumentType(QualType Ty) const;
3904 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
3905 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
3906 uint64_t Members) const override;
3908 // TODO: We can add more logic to computeInfo to improve performance.
3909 // Example: For aggregate arguments that fit in a register, we could
3910 // use getDirectInReg (as is done below for structs containing a single
3911 // floating-point value) to avoid pushing them to memory on function
3912 // entry. This would require changing the logic in PPCISelLowering
3913 // when lowering the parameters in the caller and args in the callee.
3914 void computeInfo(CGFunctionInfo &FI) const override {
3915 if (!getCXXABI().classifyReturnType(FI))
3916 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
3917 for (auto &I : FI.arguments()) {
3918 // We rely on the default argument classification for the most part.
3919 // One exception: An aggregate containing a single floating-point
3920 // or vector item must be passed in a register if one is available.
3921 const Type *T = isSingleElementStruct(I.type, getContext());
3923 const BuiltinType *BT = T->getAs<BuiltinType>();
3924 if (IsQPXVectorTy(T) ||
3925 (T->isVectorType() && getContext().getTypeSize(T) == 128) ||
3926 (BT && BT->isFloatingPoint())) {
3928 I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
3932 I.info = classifyArgumentType(I.type);
3936 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3937 QualType Ty) const override;
3940 class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
3943 PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT,
3944 PPC64_SVR4_ABIInfo::ABIKind Kind, bool HasQPX,
3946 : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT, Kind, HasQPX,
3949 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
3950 // This is recovered from gcc output.
3951 return 1; // r1 is the dedicated stack pointer
3954 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3955 llvm::Value *Address) const override;
3958 class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
3960 PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
3962 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
3963 // This is recovered from gcc output.
3964 return 1; // r1 is the dedicated stack pointer
3967 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3968 llvm::Value *Address) const override;
3973 // Return true if the ABI requires Ty to be passed sign- or zero-
3974 // extended to 64 bits.
3976 PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
3977 // Treat an enum type as its underlying type.
3978 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3979 Ty = EnumTy->getDecl()->getIntegerType();
3981 // Promotable integer types are required to be promoted by the ABI.
3982 if (Ty->isPromotableIntegerType())
3985 // In addition to the usual promotable integer types, we also need to
3986 // extend all 32-bit types, since the ABI requires promotion to 64 bits.
3987 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
3988 switch (BT->getKind()) {
3989 case BuiltinType::Int:
3990 case BuiltinType::UInt:
3999 /// isAlignedParamType - Determine whether a type requires 16-byte or
4000 /// higher alignment in the parameter area. Always returns at least 8.
4001 CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4002 // Complex types are passed just like their elements.
4003 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4004 Ty = CTy->getElementType();
4006 // Only vector types of size 16 bytes need alignment (larger types are
4007 // passed via reference, smaller types are not aligned).
4008 if (IsQPXVectorTy(Ty)) {
4009 if (getContext().getTypeSize(Ty) > 128)
4010 return CharUnits::fromQuantity(32);
4012 return CharUnits::fromQuantity(16);
4013 } else if (Ty->isVectorType()) {
4014 return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);
4017 // For single-element float/vector structs, we consider the whole type
4018 // to have the same alignment requirements as its single element.
4019 const Type *AlignAsType = nullptr;
4020 const Type *EltType = isSingleElementStruct(Ty, getContext());
4022 const BuiltinType *BT = EltType->getAs<BuiltinType>();
4023 if (IsQPXVectorTy(EltType) || (EltType->isVectorType() &&
4024 getContext().getTypeSize(EltType) == 128) ||
4025 (BT && BT->isFloatingPoint()))
4026 AlignAsType = EltType;
4029 // Likewise for ELFv2 homogeneous aggregates.
4030 const Type *Base = nullptr;
4031 uint64_t Members = 0;
4032 if (!AlignAsType && Kind == ELFv2 &&
4033 isAggregateTypeForABI(Ty) && isHomogeneousAggregate(Ty, Base, Members))
4036 // With special case aggregates, only vector base types need alignment.
4037 if (AlignAsType && IsQPXVectorTy(AlignAsType)) {
4038 if (getContext().getTypeSize(AlignAsType) > 128)
4039 return CharUnits::fromQuantity(32);
4041 return CharUnits::fromQuantity(16);
4042 } else if (AlignAsType) {
4043 return CharUnits::fromQuantity(AlignAsType->isVectorType() ? 16 : 8);
4046 // Otherwise, we only need alignment for any aggregate type that
4047 // has an alignment requirement of >= 16 bytes.
4048 if (isAggregateTypeForABI(Ty) && getContext().getTypeAlign(Ty) >= 128) {
4049 if (HasQPX && getContext().getTypeAlign(Ty) >= 256)
4050 return CharUnits::fromQuantity(32);
4051 return CharUnits::fromQuantity(16);
4054 return CharUnits::fromQuantity(8);
4057 /// isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous
4058 /// aggregate. Base is set to the base element type, and Members is set
4059 /// to the number of base elements.
4060 bool ABIInfo::isHomogeneousAggregate(QualType Ty, const Type *&Base,
4061 uint64_t &Members) const {
4062 if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
4063 uint64_t NElements = AT->getSize().getZExtValue();
4066 if (!isHomogeneousAggregate(AT->getElementType(), Base, Members))
4068 Members *= NElements;
4069 } else if (const RecordType *RT = Ty->getAs<RecordType>()) {
4070 const RecordDecl *RD = RT->getDecl();
4071 if (RD->hasFlexibleArrayMember())
4076 // If this is a C++ record, check the bases first.
4077 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
4078 for (const auto &I : CXXRD->bases()) {
4079 // Ignore empty records.
4080 if (isEmptyRecord(getContext(), I.getType(), true))
4083 uint64_t FldMembers;
4084 if (!isHomogeneousAggregate(I.getType(), Base, FldMembers))
4087 Members += FldMembers;
4091 for (const auto *FD : RD->fields()) {
4092 // Ignore (non-zero arrays of) empty records.
4093 QualType FT = FD->getType();
4094 while (const ConstantArrayType *AT =
4095 getContext().getAsConstantArrayType(FT)) {
4096 if (AT->getSize().getZExtValue() == 0)
4098 FT = AT->getElementType();
4100 if (isEmptyRecord(getContext(), FT, true))
4103 // For compatibility with GCC, ignore empty bitfields in C++ mode.
4104 if (getContext().getLangOpts().CPlusPlus &&
4105 FD->isBitField() && FD->getBitWidthValue(getContext()) == 0)
4108 uint64_t FldMembers;
4109 if (!isHomogeneousAggregate(FD->getType(), Base, FldMembers))
4112 Members = (RD->isUnion() ?
4113 std::max(Members, FldMembers) : Members + FldMembers);
4119 // Ensure there is no padding.
4120 if (getContext().getTypeSize(Base) * Members !=
4121 getContext().getTypeSize(Ty))
4125 if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
4127 Ty = CT->getElementType();
4130 // Most ABIs only support float, double, and some vector type widths.
4131 if (!isHomogeneousAggregateBaseType(Ty))
4134 // The base type must be the same for all members. Types that
4135 // agree in both total size and mode (float vs. vector) are
4136 // treated as being equivalent here.
4137 const Type *TyPtr = Ty.getTypePtr();
4140 // If it's a non-power-of-2 vector, its size is already a power-of-2,
4141 // so make sure to widen it explicitly.
4142 if (const VectorType *VT = Base->getAs<VectorType>()) {
4143 QualType EltTy = VT->getElementType();
4144 unsigned NumElements =
4145 getContext().getTypeSize(VT) / getContext().getTypeSize(EltTy);
4147 .getVectorType(EltTy, NumElements, VT->getVectorKind())
4152 if (Base->isVectorType() != TyPtr->isVectorType() ||
4153 getContext().getTypeSize(Base) != getContext().getTypeSize(TyPtr))
4156 return Members > 0 && isHomogeneousAggregateSmallEnough(Base, Members);
4159 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
4160 // Homogeneous aggregates for ELFv2 must have base types of float,
4161 // double, long double, or 128-bit vectors.
4162 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4163 if (BT->getKind() == BuiltinType::Float ||
4164 BT->getKind() == BuiltinType::Double ||
4165 BT->getKind() == BuiltinType::LongDouble) {
4171 if (const VectorType *VT = Ty->getAs<VectorType>()) {
4172 if (getContext().getTypeSize(VT) == 128 || IsQPXVectorTy(Ty))
4178 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
4179 const Type *Base, uint64_t Members) const {
4180 // Vector types require one register, floating point types require one
4181 // or two registers depending on their size.
4183 Base->isVectorType() ? 1 : (getContext().getTypeSize(Base) + 63) / 64;
4185 // Homogeneous Aggregates may occupy at most 8 registers.
4186 return Members * NumRegs <= 8;
4190 PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
4191 Ty = useFirstFieldIfTransparentUnion(Ty);
4193 if (Ty->isAnyComplexType())
4194 return ABIArgInfo::getDirect();
4196 // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
4197 // or via reference (larger than 16 bytes).
4198 if (Ty->isVectorType() && !IsQPXVectorTy(Ty)) {
4199 uint64_t Size = getContext().getTypeSize(Ty);
4201 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4202 else if (Size < 128) {
4203 llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4204 return ABIArgInfo::getDirect(CoerceTy);
4208 if (isAggregateTypeForABI(Ty)) {
4209 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
4210 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
4212 uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity();
4213 uint64_t TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();
4215 // ELFv2 homogeneous aggregates are passed as array types.
4216 const Type *Base = nullptr;
4217 uint64_t Members = 0;
4218 if (Kind == ELFv2 &&
4219 isHomogeneousAggregate(Ty, Base, Members)) {
4220 llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4221 llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4222 return ABIArgInfo::getDirect(CoerceTy);
4225 // If an aggregate may end up fully in registers, we do not
4226 // use the ByVal method, but pass the aggregate as array.
4227 // This is usually beneficial since we avoid forcing the
4228 // back-end to store the argument to memory.
4229 uint64_t Bits = getContext().getTypeSize(Ty);
4230 if (Bits > 0 && Bits <= 8 * GPRBits) {
4231 llvm::Type *CoerceTy;
4233 // Types up to 8 bytes are passed as integer type (which will be
4234 // properly aligned in the argument save area doubleword).
4235 if (Bits <= GPRBits)
4237 llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4238 // Larger types are passed as arrays, with the base type selected
4239 // according to the required alignment in the save area.
4241 uint64_t RegBits = ABIAlign * 8;
4242 uint64_t NumRegs = llvm::alignTo(Bits, RegBits) / RegBits;
4243 llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits);
4244 CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);
4247 return ABIArgInfo::getDirect(CoerceTy);
4250 // All other aggregates are passed ByVal.
4251 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(ABIAlign),
4253 /*Realign=*/TyAlign > ABIAlign);
4256 return (isPromotableTypeForABI(Ty) ?
4257 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
4261 PPC64_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {
4262 if (RetTy->isVoidType())
4263 return ABIArgInfo::getIgnore();
4265 if (RetTy->isAnyComplexType())
4266 return ABIArgInfo::getDirect();
4268 // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
4269 // or via reference (larger than 16 bytes).
4270 if (RetTy->isVectorType() && !IsQPXVectorTy(RetTy)) {
4271 uint64_t Size = getContext().getTypeSize(RetTy);
4273 return getNaturalAlignIndirect(RetTy);
4274 else if (Size < 128) {
4275 llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4276 return ABIArgInfo::getDirect(CoerceTy);
4280 if (isAggregateTypeForABI(RetTy)) {
4281 // ELFv2 homogeneous aggregates are returned as array types.
4282 const Type *Base = nullptr;
4283 uint64_t Members = 0;
4284 if (Kind == ELFv2 &&
4285 isHomogeneousAggregate(RetTy, Base, Members)) {
4286 llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4287 llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4288 return ABIArgInfo::getDirect(CoerceTy);
4291 // ELFv2 small aggregates are returned in up to two registers.
4292 uint64_t Bits = getContext().getTypeSize(RetTy);
4293 if (Kind == ELFv2 && Bits <= 2 * GPRBits) {
4295 return ABIArgInfo::getIgnore();
4297 llvm::Type *CoerceTy;
4298 if (Bits > GPRBits) {
4299 CoerceTy = llvm::IntegerType::get(getVMContext(), GPRBits);
4300 CoerceTy = llvm::StructType::get(CoerceTy, CoerceTy, nullptr);
4303 llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4304 return ABIArgInfo::getDirect(CoerceTy);
4307 // All other aggregates are returned indirectly.
4308 return getNaturalAlignIndirect(RetTy);
4311 return (isPromotableTypeForABI(RetTy) ?
4312 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
4315 // Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
4316 Address PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4317 QualType Ty) const {
4318 auto TypeInfo = getContext().getTypeInfoInChars(Ty);
4319 TypeInfo.second = getParamTypeAlignment(Ty);
4321 CharUnits SlotSize = CharUnits::fromQuantity(8);
4323 // If we have a complex type and the base type is smaller than 8 bytes,
4324 // the ABI calls for the real and imaginary parts to be right-adjusted
4325 // in separate doublewords. However, Clang expects us to produce a
4326 // pointer to a structure with the two parts packed tightly. So generate
4327 // loads of the real and imaginary parts relative to the va_list pointer,
4328 // and store them to a temporary structure.
4329 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4330 CharUnits EltSize = TypeInfo.first / 2;
4331 if (EltSize < SlotSize) {
4332 Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty,
4333 SlotSize * 2, SlotSize,
4334 SlotSize, /*AllowHigher*/ true);
4336 Address RealAddr = Addr;
4337 Address ImagAddr = RealAddr;
4338 if (CGF.CGM.getDataLayout().isBigEndian()) {
4339 RealAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr,
4340 SlotSize - EltSize);
4341 ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(ImagAddr,
4342 2 * SlotSize - EltSize);
4344 ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize);
4347 llvm::Type *EltTy = CGF.ConvertTypeForMem(CTy->getElementType());
4348 RealAddr = CGF.Builder.CreateElementBitCast(RealAddr, EltTy);
4349 ImagAddr = CGF.Builder.CreateElementBitCast(ImagAddr, EltTy);
4350 llvm::Value *Real = CGF.Builder.CreateLoad(RealAddr, ".vareal");
4351 llvm::Value *Imag = CGF.Builder.CreateLoad(ImagAddr, ".vaimag");
4353 Address Temp = CGF.CreateMemTemp(Ty, "vacplx");
4354 CGF.EmitStoreOfComplex({Real, Imag}, CGF.MakeAddrLValue(Temp, Ty),
4360 // Otherwise, just use the general rule.
4361 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
4362 TypeInfo, SlotSize, /*AllowHigher*/ true);
4366 PPC64_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4367 llvm::Value *Address) {
4368 // This is calculated from the LLVM and GCC tables and verified
4369 // against gcc output. AFAIK all ABIs use the same encoding.
4371 CodeGen::CGBuilderTy &Builder = CGF.Builder;
4373 llvm::IntegerType *i8 = CGF.Int8Ty;
4374 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4375 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4376 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4378 // 0-31: r0-31, the 8-byte general-purpose registers
4379 AssignToArrayRange(Builder, Address, Eight8, 0, 31);
4381 // 32-63: fp0-31, the 8-byte floating-point registers
4382 AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4384 // 64-76 are various 4-byte special-purpose registers:
4391 AssignToArrayRange(Builder, Address, Four8, 64, 76);
4393 // 77-108: v0-31, the 16-byte vector registers
4394 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4401 AssignToArrayRange(Builder, Address, Four8, 109, 113);
4407 PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
4408 CodeGen::CodeGenFunction &CGF,
4409 llvm::Value *Address) const {
4411 return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4415 PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4416 llvm::Value *Address) const {
4418 return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4421 //===----------------------------------------------------------------------===//
4422 // AArch64 ABI Implementation
4423 //===----------------------------------------------------------------------===//
4427 class AArch64ABIInfo : public SwiftABIInfo {
4438 AArch64ABIInfo(CodeGenTypes &CGT, ABIKind Kind)
4439 : SwiftABIInfo(CGT), Kind(Kind) {}
4442 ABIKind getABIKind() const { return Kind; }
4443 bool isDarwinPCS() const { return Kind == DarwinPCS; }
4445 ABIArgInfo classifyReturnType(QualType RetTy) const;
4446 ABIArgInfo classifyArgumentType(QualType RetTy) const;
4447 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4448 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4449 uint64_t Members) const override;
4451 bool isIllegalVectorType(QualType Ty) const;
4453 void computeInfo(CGFunctionInfo &FI) const override {
4454 if (!getCXXABI().classifyReturnType(FI))
4455 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
4457 for (auto &it : FI.arguments())
4458 it.info = classifyArgumentType(it.type);
4461 Address EmitDarwinVAArg(Address VAListAddr, QualType Ty,
4462 CodeGenFunction &CGF) const;
4464 Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
4465 CodeGenFunction &CGF) const;
4467 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4468 QualType Ty) const override {
4469 return isDarwinPCS() ? EmitDarwinVAArg(VAListAddr, Ty, CGF)
4470 : EmitAAPCSVAArg(VAListAddr, Ty, CGF);
4473 bool shouldPassIndirectlyForSwift(CharUnits totalSize,
4474 ArrayRef<llvm::Type*> scalars,
4475 bool asReturnValue) const override {
4476 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
4480 class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
4482 AArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind Kind)
4483 : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
4485 StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
4486 return "mov\tfp, fp\t\t; marker for objc_retainAutoreleaseReturnValue";
4489 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4493 bool doesReturnSlotInterfereWithArgs() const override { return false; }
4497 ABIArgInfo AArch64ABIInfo::classifyArgumentType(QualType Ty) const {
4498 Ty = useFirstFieldIfTransparentUnion(Ty);
4500 // Handle illegal vector types here.
4501 if (isIllegalVectorType(Ty)) {
4502 uint64_t Size = getContext().getTypeSize(Ty);
4503 // Android promotes <2 x i8> to i16, not i32
4504 if (isAndroid() && (Size <= 16)) {
4505 llvm::Type *ResType = llvm::Type::getInt16Ty(getVMContext());
4506 return ABIArgInfo::getDirect(ResType);
4509 llvm::Type *ResType = llvm::Type::getInt32Ty(getVMContext());
4510 return ABIArgInfo::getDirect(ResType);
4513 llvm::Type *ResType =
4514 llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 2);
4515 return ABIArgInfo::getDirect(ResType);
4518 llvm::Type *ResType =
4519 llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 4);
4520 return ABIArgInfo::getDirect(ResType);
4522 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4525 if (!isAggregateTypeForABI(Ty)) {
4526 // Treat an enum type as its underlying type.
4527 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4528 Ty = EnumTy->getDecl()->getIntegerType();
4530 return (Ty->isPromotableIntegerType() && isDarwinPCS()
4531 ? ABIArgInfo::getExtend()
4532 : ABIArgInfo::getDirect());
4535 // Structures with either a non-trivial destructor or a non-trivial
4536 // copy constructor are always indirect.
4537 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
4538 return getNaturalAlignIndirect(Ty, /*ByVal=*/RAA ==
4539 CGCXXABI::RAA_DirectInMemory);
4542 // Empty records are always ignored on Darwin, but actually passed in C++ mode
4543 // elsewhere for GNU compatibility.
4544 if (isEmptyRecord(getContext(), Ty, true)) {
4545 if (!getContext().getLangOpts().CPlusPlus || isDarwinPCS())
4546 return ABIArgInfo::getIgnore();
4548 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
4551 // Homogeneous Floating-point Aggregates (HFAs) need to be expanded.
4552 const Type *Base = nullptr;
4553 uint64_t Members = 0;
4554 if (isHomogeneousAggregate(Ty, Base, Members)) {
4555 return ABIArgInfo::getDirect(
4556 llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members));
4559 // Aggregates <= 16 bytes are passed directly in registers or on the stack.
4560 uint64_t Size = getContext().getTypeSize(Ty);
4562 unsigned Alignment = getContext().getTypeAlign(Ty);
4563 Size = 64 * ((Size + 63) / 64); // round up to multiple of 8 bytes
4565 // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
4566 // For aggregates with 16-byte alignment, we use i128.
4567 if (Alignment < 128 && Size == 128) {
4568 llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
4569 return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
4571 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
4574 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4577 ABIArgInfo AArch64ABIInfo::classifyReturnType(QualType RetTy) const {
4578 if (RetTy->isVoidType())
4579 return ABIArgInfo::getIgnore();
4581 // Large vector types should be returned via memory.
4582 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128)
4583 return getNaturalAlignIndirect(RetTy);
4585 if (!isAggregateTypeForABI(RetTy)) {
4586 // Treat an enum type as its underlying type.
4587 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
4588 RetTy = EnumTy->getDecl()->getIntegerType();
4590 return (RetTy->isPromotableIntegerType() && isDarwinPCS()
4591 ? ABIArgInfo::getExtend()
4592 : ABIArgInfo::getDirect());
4595 if (isEmptyRecord(getContext(), RetTy, true))
4596 return ABIArgInfo::getIgnore();
4598 const Type *Base = nullptr;
4599 uint64_t Members = 0;
4600 if (isHomogeneousAggregate(RetTy, Base, Members))
4601 // Homogeneous Floating-point Aggregates (HFAs) are returned directly.
4602 return ABIArgInfo::getDirect();
4604 // Aggregates <= 16 bytes are returned directly in registers or on the stack.
4605 uint64_t Size = getContext().getTypeSize(RetTy);
4607 unsigned Alignment = getContext().getTypeAlign(RetTy);
4608 Size = 64 * ((Size + 63) / 64); // round up to multiple of 8 bytes
4610 // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
4611 // For aggregates with 16-byte alignment, we use i128.
4612 if (Alignment < 128 && Size == 128) {
4613 llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
4614 return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
4616 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
4619 return getNaturalAlignIndirect(RetTy);
4622 /// isIllegalVectorType - check whether the vector type is legal for AArch64.
4623 bool AArch64ABIInfo::isIllegalVectorType(QualType Ty) const {
4624 if (const VectorType *VT = Ty->getAs<VectorType>()) {
4625 // Check whether VT is legal.
4626 unsigned NumElements = VT->getNumElements();
4627 uint64_t Size = getContext().getTypeSize(VT);
4628 // NumElements should be power of 2.
4629 if (!llvm::isPowerOf2_32(NumElements))
4631 return Size != 64 && (Size != 128 || NumElements == 1);
4636 bool AArch64ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
4637 // Homogeneous aggregates for AAPCS64 must have base types of a floating
4638 // point type or a short-vector type. This is the same as the 32-bit ABI,
4639 // but with the difference that any floating-point type is allowed,
4640 // including __fp16.
4641 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4642 if (BT->isFloatingPoint())
4644 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
4645 unsigned VecSize = getContext().getTypeSize(VT);
4646 if (VecSize == 64 || VecSize == 128)
4652 bool AArch64ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
4653 uint64_t Members) const {
4654 return Members <= 4;
4657 Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr,
4659 CodeGenFunction &CGF) const {
4660 ABIArgInfo AI = classifyArgumentType(Ty);
4661 bool IsIndirect = AI.isIndirect();
4663 llvm::Type *BaseTy = CGF.ConvertType(Ty);
4665 BaseTy = llvm::PointerType::getUnqual(BaseTy);
4666 else if (AI.getCoerceToType())
4667 BaseTy = AI.getCoerceToType();
4669 unsigned NumRegs = 1;
4670 if (llvm::ArrayType *ArrTy = dyn_cast<llvm::ArrayType>(BaseTy)) {
4671 BaseTy = ArrTy->getElementType();
4672 NumRegs = ArrTy->getNumElements();
4674 bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy();
4676 // The AArch64 va_list type and handling is specified in the Procedure Call
4677 // Standard, section B.4:
4687 llvm::BasicBlock *MaybeRegBlock = CGF.createBasicBlock("vaarg.maybe_reg");
4688 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
4689 llvm::BasicBlock *OnStackBlock = CGF.createBasicBlock("vaarg.on_stack");
4690 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
4692 auto TyInfo = getContext().getTypeInfoInChars(Ty);
4693 CharUnits TyAlign = TyInfo.second;
4695 Address reg_offs_p = Address::invalid();
4696 llvm::Value *reg_offs = nullptr;
4698 CharUnits reg_top_offset;
4699 int RegSize = IsIndirect ? 8 : TyInfo.first.getQuantity();
4701 // 3 is the field number of __gr_offs
4703 CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(24),
4705 reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "gr_offs");
4706 reg_top_index = 1; // field number for __gr_top
4707 reg_top_offset = CharUnits::fromQuantity(8);
4708 RegSize = llvm::alignTo(RegSize, 8);
4710 // 4 is the field number of __vr_offs.
4712 CGF.Builder.CreateStructGEP(VAListAddr, 4, CharUnits::fromQuantity(28),
4714 reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "vr_offs");
4715 reg_top_index = 2; // field number for __vr_top
4716 reg_top_offset = CharUnits::fromQuantity(16);
4717 RegSize = 16 * NumRegs;
4720 //=======================================
4721 // Find out where argument was passed
4722 //=======================================
4724 // If reg_offs >= 0 we're already using the stack for this type of
4725 // argument. We don't want to keep updating reg_offs (in case it overflows,
4726 // though anyone passing 2GB of arguments, each at most 16 bytes, deserves
4727 // whatever they get).
4728 llvm::Value *UsingStack = nullptr;
4729 UsingStack = CGF.Builder.CreateICmpSGE(
4730 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, 0));
4732 CGF.Builder.CreateCondBr(UsingStack, OnStackBlock, MaybeRegBlock);
4734 // Otherwise, at least some kind of argument could go in these registers, the
4735 // question is whether this particular type is too big.
4736 CGF.EmitBlock(MaybeRegBlock);
4738 // Integer arguments may need to correct register alignment (for example a
4739 // "struct { __int128 a; };" gets passed in x_2N, x_{2N+1}). In this case we
4740 // align __gr_offs to calculate the potential address.
4741 if (!IsFPR && !IsIndirect && TyAlign.getQuantity() > 8) {
4742 int Align = TyAlign.getQuantity();
4744 reg_offs = CGF.Builder.CreateAdd(
4745 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, Align - 1),
4747 reg_offs = CGF.Builder.CreateAnd(
4748 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, -Align),
4752 // Update the gr_offs/vr_offs pointer for next call to va_arg on this va_list.
4753 // The fact that this is done unconditionally reflects the fact that
4754 // allocating an argument to the stack also uses up all the remaining
4755 // registers of the appropriate kind.
4756 llvm::Value *NewOffset = nullptr;
4757 NewOffset = CGF.Builder.CreateAdd(
4758 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs");
4759 CGF.Builder.CreateStore(NewOffset, reg_offs_p);
4761 // Now we're in a position to decide whether this argument really was in
4762 // registers or not.
4763 llvm::Value *InRegs = nullptr;
4764 InRegs = CGF.Builder.CreateICmpSLE(
4765 NewOffset, llvm::ConstantInt::get(CGF.Int32Ty, 0), "inreg");
4767 CGF.Builder.CreateCondBr(InRegs, InRegBlock, OnStackBlock);
4769 //=======================================
4770 // Argument was in registers
4771 //=======================================
4773 // Now we emit the code for if the argument was originally passed in
4774 // registers. First start the appropriate block:
4775 CGF.EmitBlock(InRegBlock);
4777 llvm::Value *reg_top = nullptr;
4778 Address reg_top_p = CGF.Builder.CreateStructGEP(VAListAddr, reg_top_index,
4779 reg_top_offset, "reg_top_p");
4780 reg_top = CGF.Builder.CreateLoad(reg_top_p, "reg_top");
4781 Address BaseAddr(CGF.Builder.CreateInBoundsGEP(reg_top, reg_offs),
4782 CharUnits::fromQuantity(IsFPR ? 16 : 8));
4783 Address RegAddr = Address::invalid();
4784 llvm::Type *MemTy = CGF.ConvertTypeForMem(Ty);
4787 // If it's been passed indirectly (actually a struct), whatever we find from
4788 // stored registers or on the stack will actually be a struct **.
4789 MemTy = llvm::PointerType::getUnqual(MemTy);
4792 const Type *Base = nullptr;
4793 uint64_t NumMembers = 0;
4794 bool IsHFA = isHomogeneousAggregate(Ty, Base, NumMembers);
4795 if (IsHFA && NumMembers > 1) {
4796 // Homogeneous aggregates passed in registers will have their elements split
4797 // and stored 16-bytes apart regardless of size (they're notionally in qN,
4798 // qN+1, ...). We reload and store into a temporary local variable
4800 assert(!IsIndirect && "Homogeneous aggregates should be passed directly");
4801 auto BaseTyInfo = getContext().getTypeInfoInChars(QualType(Base, 0));
4802 llvm::Type *BaseTy = CGF.ConvertType(QualType(Base, 0));
4803 llvm::Type *HFATy = llvm::ArrayType::get(BaseTy, NumMembers);
4804 Address Tmp = CGF.CreateTempAlloca(HFATy,
4805 std::max(TyAlign, BaseTyInfo.second));
4807 // On big-endian platforms, the value will be right-aligned in its slot.
4809 if (CGF.CGM.getDataLayout().isBigEndian() &&
4810 BaseTyInfo.first.getQuantity() < 16)
4811 Offset = 16 - BaseTyInfo.first.getQuantity();
4813 for (unsigned i = 0; i < NumMembers; ++i) {
4814 CharUnits BaseOffset = CharUnits::fromQuantity(16 * i + Offset);
4816 CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, BaseOffset);
4817 LoadAddr = CGF.Builder.CreateElementBitCast(LoadAddr, BaseTy);
4820 CGF.Builder.CreateConstArrayGEP(Tmp, i, BaseTyInfo.first);
4822 llvm::Value *Elem = CGF.Builder.CreateLoad(LoadAddr);
4823 CGF.Builder.CreateStore(Elem, StoreAddr);
4826 RegAddr = CGF.Builder.CreateElementBitCast(Tmp, MemTy);
4828 // Otherwise the object is contiguous in memory.
4830 // It might be right-aligned in its slot.
4831 CharUnits SlotSize = BaseAddr.getAlignment();
4832 if (CGF.CGM.getDataLayout().isBigEndian() && !IsIndirect &&
4833 (IsHFA || !isAggregateTypeForABI(Ty)) &&
4834 TyInfo.first < SlotSize) {
4835 CharUnits Offset = SlotSize - TyInfo.first;
4836 BaseAddr = CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, Offset);
4839 RegAddr = CGF.Builder.CreateElementBitCast(BaseAddr, MemTy);
4842 CGF.EmitBranch(ContBlock);
4844 //=======================================
4845 // Argument was on the stack
4846 //=======================================
4847 CGF.EmitBlock(OnStackBlock);
4849 Address stack_p = CGF.Builder.CreateStructGEP(VAListAddr, 0,
4850 CharUnits::Zero(), "stack_p");
4851 llvm::Value *OnStackPtr = CGF.Builder.CreateLoad(stack_p, "stack");
4853 // Again, stack arguments may need realignment. In this case both integer and
4854 // floating-point ones might be affected.
4855 if (!IsIndirect && TyAlign.getQuantity() > 8) {
4856 int Align = TyAlign.getQuantity();
4858 OnStackPtr = CGF.Builder.CreatePtrToInt(OnStackPtr, CGF.Int64Ty);
4860 OnStackPtr = CGF.Builder.CreateAdd(
4861 OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, Align - 1),
4863 OnStackPtr = CGF.Builder.CreateAnd(
4864 OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, -Align),
4867 OnStackPtr = CGF.Builder.CreateIntToPtr(OnStackPtr, CGF.Int8PtrTy);
4869 Address OnStackAddr(OnStackPtr,
4870 std::max(CharUnits::fromQuantity(8), TyAlign));
4872 // All stack slots are multiples of 8 bytes.
4873 CharUnits StackSlotSize = CharUnits::fromQuantity(8);
4874 CharUnits StackSize;
4876 StackSize = StackSlotSize;
4878 StackSize = TyInfo.first.alignTo(StackSlotSize);
4880 llvm::Value *StackSizeC = CGF.Builder.getSize(StackSize);
4881 llvm::Value *NewStack =
4882 CGF.Builder.CreateInBoundsGEP(OnStackPtr, StackSizeC, "new_stack");
4884 // Write the new value of __stack for the next call to va_arg
4885 CGF.Builder.CreateStore(NewStack, stack_p);
4887 if (CGF.CGM.getDataLayout().isBigEndian() && !isAggregateTypeForABI(Ty) &&
4888 TyInfo.first < StackSlotSize) {
4889 CharUnits Offset = StackSlotSize - TyInfo.first;
4890 OnStackAddr = CGF.Builder.CreateConstInBoundsByteGEP(OnStackAddr, Offset);
4893 OnStackAddr = CGF.Builder.CreateElementBitCast(OnStackAddr, MemTy);
4895 CGF.EmitBranch(ContBlock);
4897 //=======================================
4899 //=======================================
4900 CGF.EmitBlock(ContBlock);
4902 Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
4903 OnStackAddr, OnStackBlock, "vaargs.addr");
4906 return Address(CGF.Builder.CreateLoad(ResAddr, "vaarg.addr"),
4912 Address AArch64ABIInfo::EmitDarwinVAArg(Address VAListAddr, QualType Ty,
4913 CodeGenFunction &CGF) const {
4914 // The backend's lowering doesn't support va_arg for aggregates or
4915 // illegal vector types. Lower VAArg here for these cases and use
4916 // the LLVM va_arg instruction for everything else.
4917 if (!isAggregateTypeForABI(Ty) && !isIllegalVectorType(Ty))
4918 return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
4920 CharUnits SlotSize = CharUnits::fromQuantity(8);
4922 // Empty records are ignored for parameter passing purposes.
4923 if (isEmptyRecord(getContext(), Ty, true)) {
4924 Address Addr(CGF.Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize);
4925 Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
4929 // The size of the actual thing passed, which might end up just
4930 // being a pointer for indirect types.
4931 auto TyInfo = getContext().getTypeInfoInChars(Ty);
4933 // Arguments bigger than 16 bytes which aren't homogeneous
4934 // aggregates should be passed indirectly.
4935 bool IsIndirect = false;
4936 if (TyInfo.first.getQuantity() > 16) {
4937 const Type *Base = nullptr;
4938 uint64_t Members = 0;
4939 IsIndirect = !isHomogeneousAggregate(Ty, Base, Members);
4942 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
4943 TyInfo, SlotSize, /*AllowHigherAlign*/ true);
4946 //===----------------------------------------------------------------------===//
4947 // ARM ABI Implementation
4948 //===----------------------------------------------------------------------===//
4952 class ARMABIInfo : public SwiftABIInfo {
4965 ARMABIInfo(CodeGenTypes &CGT, ABIKind _Kind)
4966 : SwiftABIInfo(CGT), Kind(_Kind) {
4970 bool isEABI() const {
4971 switch (getTarget().getTriple().getEnvironment()) {
4972 case llvm::Triple::Android:
4973 case llvm::Triple::EABI:
4974 case llvm::Triple::EABIHF:
4975 case llvm::Triple::GNUEABI:
4976 case llvm::Triple::GNUEABIHF:
4977 case llvm::Triple::MuslEABI:
4978 case llvm::Triple::MuslEABIHF:
4985 bool isEABIHF() const {
4986 switch (getTarget().getTriple().getEnvironment()) {
4987 case llvm::Triple::EABIHF:
4988 case llvm::Triple::GNUEABIHF:
4989 case llvm::Triple::MuslEABIHF:
4996 ABIKind getABIKind() const { return Kind; }
4999 ABIArgInfo classifyReturnType(QualType RetTy, bool isVariadic) const;
5000 ABIArgInfo classifyArgumentType(QualType RetTy, bool isVariadic) const;
5001 bool isIllegalVectorType(QualType Ty) const;
5003 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
5004 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
5005 uint64_t Members) const override;
5007 void computeInfo(CGFunctionInfo &FI) const override;
5009 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5010 QualType Ty) const override;
5012 llvm::CallingConv::ID getLLVMDefaultCC() const;
5013 llvm::CallingConv::ID getABIDefaultCC() const;
5016 bool shouldPassIndirectlyForSwift(CharUnits totalSize,
5017 ArrayRef<llvm::Type*> scalars,
5018 bool asReturnValue) const override {
5019 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
5023 class ARMTargetCodeGenInfo : public TargetCodeGenInfo {
5025 ARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5026 :TargetCodeGenInfo(new ARMABIInfo(CGT, K)) {}
5028 const ARMABIInfo &getABIInfo() const {
5029 return static_cast<const ARMABIInfo&>(TargetCodeGenInfo::getABIInfo());
5032 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5036 StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
5037 return "mov\tr7, r7\t\t@ marker for objc_retainAutoreleaseReturnValue";
5040 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5041 llvm::Value *Address) const override {
5042 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
5044 // 0-15 are the 16 integer registers.
5045 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 15);
5049 unsigned getSizeOfUnwindException() const override {
5050 if (getABIInfo().isEABI()) return 88;
5051 return TargetCodeGenInfo::getSizeOfUnwindException();
5054 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5055 CodeGen::CodeGenModule &CGM) const override {
5056 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
5060 const ARMInterruptAttr *Attr = FD->getAttr<ARMInterruptAttr>();
5065 switch (Attr->getInterrupt()) {
5066 case ARMInterruptAttr::Generic: Kind = ""; break;
5067 case ARMInterruptAttr::IRQ: Kind = "IRQ"; break;
5068 case ARMInterruptAttr::FIQ: Kind = "FIQ"; break;
5069 case ARMInterruptAttr::SWI: Kind = "SWI"; break;
5070 case ARMInterruptAttr::ABORT: Kind = "ABORT"; break;
5071 case ARMInterruptAttr::UNDEF: Kind = "UNDEF"; break;
5074 llvm::Function *Fn = cast<llvm::Function>(GV);
5076 Fn->addFnAttr("interrupt", Kind);
5078 ARMABIInfo::ABIKind ABI = cast<ARMABIInfo>(getABIInfo()).getABIKind();
5079 if (ABI == ARMABIInfo::APCS)
5082 // AAPCS guarantees that sp will be 8-byte aligned on any public interface,
5083 // however this is not necessarily true on taking any interrupt. Instruct
5084 // the backend to perform a realignment as part of the function prologue.
5085 llvm::AttrBuilder B;
5086 B.addStackAlignmentAttr(8);
5087 Fn->addAttributes(llvm::AttributeSet::FunctionIndex,
5088 llvm::AttributeSet::get(CGM.getLLVMContext(),
5089 llvm::AttributeSet::FunctionIndex,
5094 class WindowsARMTargetCodeGenInfo : public ARMTargetCodeGenInfo {
5096 WindowsARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5097 : ARMTargetCodeGenInfo(CGT, K) {}
5099 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5100 CodeGen::CodeGenModule &CGM) const override;
5102 void getDependentLibraryOption(llvm::StringRef Lib,
5103 llvm::SmallString<24> &Opt) const override {
5104 Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
5107 void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
5108 llvm::SmallString<32> &Opt) const override {
5109 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
5113 void WindowsARMTargetCodeGenInfo::setTargetAttributes(
5114 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
5115 ARMTargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
5116 addStackProbeSizeTargetAttribute(D, GV, CGM);
5120 void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const {
5121 if (!getCXXABI().classifyReturnType(FI))
5122 FI.getReturnInfo() =
5123 classifyReturnType(FI.getReturnType(), FI.isVariadic());
5125 for (auto &I : FI.arguments())
5126 I.info = classifyArgumentType(I.type, FI.isVariadic());
5128 // Always honor user-specified calling convention.
5129 if (FI.getCallingConvention() != llvm::CallingConv::C)
5132 llvm::CallingConv::ID cc = getRuntimeCC();
5133 if (cc != llvm::CallingConv::C)
5134 FI.setEffectiveCallingConvention(cc);
5137 /// Return the default calling convention that LLVM will use.
5138 llvm::CallingConv::ID ARMABIInfo::getLLVMDefaultCC() const {
5139 // The default calling convention that LLVM will infer.
5140 if (isEABIHF() || getTarget().getTriple().isWatchABI())
5141 return llvm::CallingConv::ARM_AAPCS_VFP;
5143 return llvm::CallingConv::ARM_AAPCS;
5145 return llvm::CallingConv::ARM_APCS;
5148 /// Return the calling convention that our ABI would like us to use
5149 /// as the C calling convention.
5150 llvm::CallingConv::ID ARMABIInfo::getABIDefaultCC() const {
5151 switch (getABIKind()) {
5152 case APCS: return llvm::CallingConv::ARM_APCS;
5153 case AAPCS: return llvm::CallingConv::ARM_AAPCS;
5154 case AAPCS_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
5155 case AAPCS16_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
5157 llvm_unreachable("bad ABI kind");
5160 void ARMABIInfo::setCCs() {
5161 assert(getRuntimeCC() == llvm::CallingConv::C);
5163 // Don't muddy up the IR with a ton of explicit annotations if
5164 // they'd just match what LLVM will infer from the triple.
5165 llvm::CallingConv::ID abiCC = getABIDefaultCC();
5166 if (abiCC != getLLVMDefaultCC())
5169 // AAPCS apparently requires runtime support functions to be soft-float, but
5170 // that's almost certainly for historic reasons (Thumb1 not supporting VFP
5171 // most likely). It's more convenient for AAPCS16_VFP to be hard-float.
5172 switch (getABIKind()) {
5175 if (abiCC != getLLVMDefaultCC())
5180 BuiltinCC = llvm::CallingConv::ARM_AAPCS;
5185 ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty,
5186 bool isVariadic) const {
5187 // 6.1.2.1 The following argument types are VFP CPRCs:
5188 // A single-precision floating-point type (including promoted
5189 // half-precision types); A double-precision floating-point type;
5190 // A 64-bit or 128-bit containerized vector type; Homogeneous Aggregate
5191 // with a Base Type of a single- or double-precision floating-point type,
5192 // 64-bit containerized vectors or 128-bit containerized vectors with one
5193 // to four Elements.
5194 bool IsEffectivelyAAPCS_VFP = getABIKind() == AAPCS_VFP && !isVariadic;
5196 Ty = useFirstFieldIfTransparentUnion(Ty);
5198 // Handle illegal vector types here.
5199 if (isIllegalVectorType(Ty)) {
5200 uint64_t Size = getContext().getTypeSize(Ty);
5202 llvm::Type *ResType =
5203 llvm::Type::getInt32Ty(getVMContext());
5204 return ABIArgInfo::getDirect(ResType);
5207 llvm::Type *ResType = llvm::VectorType::get(
5208 llvm::Type::getInt32Ty(getVMContext()), 2);
5209 return ABIArgInfo::getDirect(ResType);
5212 llvm::Type *ResType = llvm::VectorType::get(
5213 llvm::Type::getInt32Ty(getVMContext()), 4);
5214 return ABIArgInfo::getDirect(ResType);
5216 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5219 // __fp16 gets passed as if it were an int or float, but with the top 16 bits
5220 // unspecified. This is not done for OpenCL as it handles the half type
5221 // natively, and does not need to interwork with AAPCS code.
5222 if (Ty->isHalfType() && !getContext().getLangOpts().NativeHalfArgsAndReturns) {
5223 llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
5224 llvm::Type::getFloatTy(getVMContext()) :
5225 llvm::Type::getInt32Ty(getVMContext());
5226 return ABIArgInfo::getDirect(ResType);
5229 if (!isAggregateTypeForABI(Ty)) {
5230 // Treat an enum type as its underlying type.
5231 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
5232 Ty = EnumTy->getDecl()->getIntegerType();
5235 return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend()
5236 : ABIArgInfo::getDirect());
5239 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
5240 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
5243 // Ignore empty records.
5244 if (isEmptyRecord(getContext(), Ty, true))
5245 return ABIArgInfo::getIgnore();
5247 if (IsEffectivelyAAPCS_VFP) {
5248 // Homogeneous Aggregates need to be expanded when we can fit the aggregate
5249 // into VFP registers.
5250 const Type *Base = nullptr;
5251 uint64_t Members = 0;
5252 if (isHomogeneousAggregate(Ty, Base, Members)) {
5253 assert(Base && "Base class should be set for homogeneous aggregate");
5254 // Base can be a floating-point or a vector.
5255 return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
5257 } else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) {
5258 // WatchOS does have homogeneous aggregates. Note that we intentionally use
5259 // this convention even for a variadic function: the backend will use GPRs
5261 const Type *Base = nullptr;
5262 uint64_t Members = 0;
5263 if (isHomogeneousAggregate(Ty, Base, Members)) {
5264 assert(Base && Members <= 4 && "unexpected homogeneous aggregate");
5266 llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members);
5267 return ABIArgInfo::getDirect(Ty, 0, nullptr, false);
5271 if (getABIKind() == ARMABIInfo::AAPCS16_VFP &&
5272 getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(16)) {
5273 // WatchOS is adopting the 64-bit AAPCS rule on composite types: if they're
5274 // bigger than 128-bits, they get placed in space allocated by the caller,
5275 // and a pointer is passed.
5276 return ABIArgInfo::getIndirect(
5277 CharUnits::fromQuantity(getContext().getTypeAlign(Ty) / 8), false);
5280 // Support byval for ARM.
5281 // The ABI alignment for APCS is 4-byte and for AAPCS at least 4-byte and at
5282 // most 8-byte. We realign the indirect argument if type alignment is bigger
5283 // than ABI alignment.
5284 uint64_t ABIAlign = 4;
5285 uint64_t TyAlign = getContext().getTypeAlign(Ty) / 8;
5286 if (getABIKind() == ARMABIInfo::AAPCS_VFP ||
5287 getABIKind() == ARMABIInfo::AAPCS)
5288 ABIAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8);
5290 if (getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(64)) {
5291 assert(getABIKind() != ARMABIInfo::AAPCS16_VFP && "unexpected byval");
5292 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(ABIAlign),
5294 /*Realign=*/TyAlign > ABIAlign);
5297 // Otherwise, pass by coercing to a structure of the appropriate size.
5300 // FIXME: Try to match the types of the arguments more accurately where
5302 if (getContext().getTypeAlign(Ty) <= 32) {
5303 ElemTy = llvm::Type::getInt32Ty(getVMContext());
5304 SizeRegs = (getContext().getTypeSize(Ty) + 31) / 32;
5306 ElemTy = llvm::Type::getInt64Ty(getVMContext());
5307 SizeRegs = (getContext().getTypeSize(Ty) + 63) / 64;
5310 return ABIArgInfo::getDirect(llvm::ArrayType::get(ElemTy, SizeRegs));
5313 static bool isIntegerLikeType(QualType Ty, ASTContext &Context,
5314 llvm::LLVMContext &VMContext) {
5315 // APCS, C Language Calling Conventions, Non-Simple Return Values: A structure
5316 // is called integer-like if its size is less than or equal to one word, and
5317 // the offset of each of its addressable sub-fields is zero.
5319 uint64_t Size = Context.getTypeSize(Ty);
5321 // Check that the type fits in a word.
5325 // FIXME: Handle vector types!
5326 if (Ty->isVectorType())
5329 // Float types are never treated as "integer like".
5330 if (Ty->isRealFloatingType())
5333 // If this is a builtin or pointer type then it is ok.
5334 if (Ty->getAs<BuiltinType>() || Ty->isPointerType())
5337 // Small complex integer types are "integer like".
5338 if (const ComplexType *CT = Ty->getAs<ComplexType>())
5339 return isIntegerLikeType(CT->getElementType(), Context, VMContext);
5341 // Single element and zero sized arrays should be allowed, by the definition
5342 // above, but they are not.
5344 // Otherwise, it must be a record type.
5345 const RecordType *RT = Ty->getAs<RecordType>();
5346 if (!RT) return false;
5348 // Ignore records with flexible arrays.
5349 const RecordDecl *RD = RT->getDecl();
5350 if (RD->hasFlexibleArrayMember())
5353 // Check that all sub-fields are at offset 0, and are themselves "integer
5355 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
5357 bool HadField = false;
5359 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
5360 i != e; ++i, ++idx) {
5361 const FieldDecl *FD = *i;
5363 // Bit-fields are not addressable, we only need to verify they are "integer
5364 // like". We still have to disallow a subsequent non-bitfield, for example:
5365 // struct { int : 0; int x }
5366 // is non-integer like according to gcc.
5367 if (FD->isBitField()) {
5371 if (!isIntegerLikeType(FD->getType(), Context, VMContext))
5377 // Check if this field is at offset 0.
5378 if (Layout.getFieldOffset(idx) != 0)
5381 if (!isIntegerLikeType(FD->getType(), Context, VMContext))
5384 // Only allow at most one field in a structure. This doesn't match the
5385 // wording above, but follows gcc in situations with a field following an
5387 if (!RD->isUnion()) {
5398 ABIArgInfo ARMABIInfo::classifyReturnType(QualType RetTy,
5399 bool isVariadic) const {
5400 bool IsEffectivelyAAPCS_VFP =
5401 (getABIKind() == AAPCS_VFP || getABIKind() == AAPCS16_VFP) && !isVariadic;
5403 if (RetTy->isVoidType())
5404 return ABIArgInfo::getIgnore();
5406 // Large vector types should be returned via memory.
5407 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128) {
5408 return getNaturalAlignIndirect(RetTy);
5411 // __fp16 gets returned as if it were an int or float, but with the top 16
5412 // bits unspecified. This is not done for OpenCL as it handles the half type
5413 // natively, and does not need to interwork with AAPCS code.
5414 if (RetTy->isHalfType() && !getContext().getLangOpts().NativeHalfArgsAndReturns) {
5415 llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
5416 llvm::Type::getFloatTy(getVMContext()) :
5417 llvm::Type::getInt32Ty(getVMContext());
5418 return ABIArgInfo::getDirect(ResType);
5421 if (!isAggregateTypeForABI(RetTy)) {
5422 // Treat an enum type as its underlying type.
5423 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5424 RetTy = EnumTy->getDecl()->getIntegerType();
5426 return RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend()
5427 : ABIArgInfo::getDirect();
5430 // Are we following APCS?
5431 if (getABIKind() == APCS) {
5432 if (isEmptyRecord(getContext(), RetTy, false))
5433 return ABIArgInfo::getIgnore();
5435 // Complex types are all returned as packed integers.
5437 // FIXME: Consider using 2 x vector types if the back end handles them
5439 if (RetTy->isAnyComplexType())
5440 return ABIArgInfo::getDirect(llvm::IntegerType::get(
5441 getVMContext(), getContext().getTypeSize(RetTy)));
5443 // Integer like structures are returned in r0.
5444 if (isIntegerLikeType(RetTy, getContext(), getVMContext())) {
5445 // Return in the smallest viable integer type.
5446 uint64_t Size = getContext().getTypeSize(RetTy);
5448 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
5450 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
5451 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
5454 // Otherwise return in memory.
5455 return getNaturalAlignIndirect(RetTy);
5458 // Otherwise this is an AAPCS variant.
5460 if (isEmptyRecord(getContext(), RetTy, true))
5461 return ABIArgInfo::getIgnore();
5463 // Check for homogeneous aggregates with AAPCS-VFP.
5464 if (IsEffectivelyAAPCS_VFP) {
5465 const Type *Base = nullptr;
5466 uint64_t Members = 0;
5467 if (isHomogeneousAggregate(RetTy, Base, Members)) {
5468 assert(Base && "Base class should be set for homogeneous aggregate");
5469 // Homogeneous Aggregates are returned directly.
5470 return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
5474 // Aggregates <= 4 bytes are returned in r0; other aggregates
5475 // are returned indirectly.
5476 uint64_t Size = getContext().getTypeSize(RetTy);
5478 if (getDataLayout().isBigEndian())
5479 // Return in 32 bit integer integer type (as if loaded by LDR, AAPCS 5.4)
5480 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
5482 // Return in the smallest viable integer type.
5484 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
5486 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
5487 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
5488 } else if (Size <= 128 && getABIKind() == AAPCS16_VFP) {
5489 llvm::Type *Int32Ty = llvm::Type::getInt32Ty(getVMContext());
5490 llvm::Type *CoerceTy =
5491 llvm::ArrayType::get(Int32Ty, llvm::alignTo(Size, 32) / 32);
5492 return ABIArgInfo::getDirect(CoerceTy);
5495 return getNaturalAlignIndirect(RetTy);
5498 /// isIllegalVector - check whether Ty is an illegal vector type.
5499 bool ARMABIInfo::isIllegalVectorType(QualType Ty) const {
5500 if (const VectorType *VT = Ty->getAs<VectorType> ()) {
5502 // Android shipped using Clang 3.1, which supported a slightly different
5503 // vector ABI. The primary differences were that 3-element vector types
5504 // were legal, and so were sub 32-bit vectors (i.e. <2 x i8>). This path
5505 // accepts that legacy behavior for Android only.
5506 // Check whether VT is legal.
5507 unsigned NumElements = VT->getNumElements();
5508 // NumElements should be power of 2 or equal to 3.
5509 if (!llvm::isPowerOf2_32(NumElements) && NumElements != 3)
5512 // Check whether VT is legal.
5513 unsigned NumElements = VT->getNumElements();
5514 uint64_t Size = getContext().getTypeSize(VT);
5515 // NumElements should be power of 2.
5516 if (!llvm::isPowerOf2_32(NumElements))
5518 // Size should be greater than 32 bits.
5525 bool ARMABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
5526 // Homogeneous aggregates for AAPCS-VFP must have base types of float,
5527 // double, or 64-bit or 128-bit vectors.
5528 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
5529 if (BT->getKind() == BuiltinType::Float ||
5530 BT->getKind() == BuiltinType::Double ||
5531 BT->getKind() == BuiltinType::LongDouble)
5533 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
5534 unsigned VecSize = getContext().getTypeSize(VT);
5535 if (VecSize == 64 || VecSize == 128)
5541 bool ARMABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
5542 uint64_t Members) const {
5543 return Members <= 4;
5546 Address ARMABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5547 QualType Ty) const {
5548 CharUnits SlotSize = CharUnits::fromQuantity(4);
5550 // Empty records are ignored for parameter passing purposes.
5551 if (isEmptyRecord(getContext(), Ty, true)) {
5552 Address Addr(CGF.Builder.CreateLoad(VAListAddr), SlotSize);
5553 Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
5557 auto TyInfo = getContext().getTypeInfoInChars(Ty);
5558 CharUnits TyAlignForABI = TyInfo.second;
5560 // Use indirect if size of the illegal vector is bigger than 16 bytes.
5561 bool IsIndirect = false;
5562 const Type *Base = nullptr;
5563 uint64_t Members = 0;
5564 if (TyInfo.first > CharUnits::fromQuantity(16) && isIllegalVectorType(Ty)) {
5567 // ARMv7k passes structs bigger than 16 bytes indirectly, in space
5568 // allocated by the caller.
5569 } else if (TyInfo.first > CharUnits::fromQuantity(16) &&
5570 getABIKind() == ARMABIInfo::AAPCS16_VFP &&
5571 !isHomogeneousAggregate(Ty, Base, Members)) {
5574 // Otherwise, bound the type's ABI alignment.
5575 // The ABI alignment for 64-bit or 128-bit vectors is 8 for AAPCS and 4 for
5576 // APCS. For AAPCS, the ABI alignment is at least 4-byte and at most 8-byte.
5577 // Our callers should be prepared to handle an under-aligned address.
5578 } else if (getABIKind() == ARMABIInfo::AAPCS_VFP ||
5579 getABIKind() == ARMABIInfo::AAPCS) {
5580 TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
5581 TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(8));
5582 } else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) {
5583 // ARMv7k allows type alignment up to 16 bytes.
5584 TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
5585 TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(16));
5587 TyAlignForABI = CharUnits::fromQuantity(4);
5589 TyInfo.second = TyAlignForABI;
5591 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, TyInfo,
5592 SlotSize, /*AllowHigherAlign*/ true);
5595 //===----------------------------------------------------------------------===//
5596 // NVPTX ABI Implementation
5597 //===----------------------------------------------------------------------===//
5601 class NVPTXABIInfo : public ABIInfo {
5603 NVPTXABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
5605 ABIArgInfo classifyReturnType(QualType RetTy) const;
5606 ABIArgInfo classifyArgumentType(QualType Ty) const;
5608 void computeInfo(CGFunctionInfo &FI) const override;
5609 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5610 QualType Ty) const override;
5613 class NVPTXTargetCodeGenInfo : public TargetCodeGenInfo {
5615 NVPTXTargetCodeGenInfo(CodeGenTypes &CGT)
5616 : TargetCodeGenInfo(new NVPTXABIInfo(CGT)) {}
5618 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5619 CodeGen::CodeGenModule &M) const override;
5621 // Adds a NamedMDNode with F, Name, and Operand as operands, and adds the
5622 // resulting MDNode to the nvvm.annotations MDNode.
5623 static void addNVVMMetadata(llvm::Function *F, StringRef Name, int Operand);
5626 ABIArgInfo NVPTXABIInfo::classifyReturnType(QualType RetTy) const {
5627 if (RetTy->isVoidType())
5628 return ABIArgInfo::getIgnore();
5630 // note: this is different from default ABI
5631 if (!RetTy->isScalarType())
5632 return ABIArgInfo::getDirect();
5634 // Treat an enum type as its underlying type.
5635 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5636 RetTy = EnumTy->getDecl()->getIntegerType();
5638 return (RetTy->isPromotableIntegerType() ?
5639 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
5642 ABIArgInfo NVPTXABIInfo::classifyArgumentType(QualType Ty) const {
5643 // Treat an enum type as its underlying type.
5644 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
5645 Ty = EnumTy->getDecl()->getIntegerType();
5647 // Return aggregates type as indirect by value
5648 if (isAggregateTypeForABI(Ty))
5649 return getNaturalAlignIndirect(Ty, /* byval */ true);
5651 return (Ty->isPromotableIntegerType() ?
5652 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
5655 void NVPTXABIInfo::computeInfo(CGFunctionInfo &FI) const {
5656 if (!getCXXABI().classifyReturnType(FI))
5657 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
5658 for (auto &I : FI.arguments())
5659 I.info = classifyArgumentType(I.type);
5661 // Always honor user-specified calling convention.
5662 if (FI.getCallingConvention() != llvm::CallingConv::C)
5665 FI.setEffectiveCallingConvention(getRuntimeCC());
5668 Address NVPTXABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5669 QualType Ty) const {
5670 llvm_unreachable("NVPTX does not support varargs");
5673 void NVPTXTargetCodeGenInfo::
5674 setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5675 CodeGen::CodeGenModule &M) const{
5676 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
5679 llvm::Function *F = cast<llvm::Function>(GV);
5681 // Perform special handling in OpenCL mode
5682 if (M.getLangOpts().OpenCL) {
5683 // Use OpenCL function attributes to check for kernel functions
5684 // By default, all functions are device functions
5685 if (FD->hasAttr<OpenCLKernelAttr>()) {
5686 // OpenCL __kernel functions get kernel metadata
5687 // Create !{<func-ref>, metadata !"kernel", i32 1} node
5688 addNVVMMetadata(F, "kernel", 1);
5689 // And kernel functions are not subject to inlining
5690 F->addFnAttr(llvm::Attribute::NoInline);
5694 // Perform special handling in CUDA mode.
5695 if (M.getLangOpts().CUDA) {
5696 // CUDA __global__ functions get a kernel metadata entry. Since
5697 // __global__ functions cannot be called from the device, we do not
5698 // need to set the noinline attribute.
5699 if (FD->hasAttr<CUDAGlobalAttr>()) {
5700 // Create !{<func-ref>, metadata !"kernel", i32 1} node
5701 addNVVMMetadata(F, "kernel", 1);
5703 if (CUDALaunchBoundsAttr *Attr = FD->getAttr<CUDALaunchBoundsAttr>()) {
5704 // Create !{<func-ref>, metadata !"maxntidx", i32 <val>} node
5705 llvm::APSInt MaxThreads(32);
5706 MaxThreads = Attr->getMaxThreads()->EvaluateKnownConstInt(M.getContext());
5708 addNVVMMetadata(F, "maxntidx", MaxThreads.getExtValue());
5710 // min blocks is an optional argument for CUDALaunchBoundsAttr. If it was
5711 // not specified in __launch_bounds__ or if the user specified a 0 value,
5712 // we don't have to add a PTX directive.
5713 if (Attr->getMinBlocks()) {
5714 llvm::APSInt MinBlocks(32);
5715 MinBlocks = Attr->getMinBlocks()->EvaluateKnownConstInt(M.getContext());
5717 // Create !{<func-ref>, metadata !"minctasm", i32 <val>} node
5718 addNVVMMetadata(F, "minctasm", MinBlocks.getExtValue());
5724 void NVPTXTargetCodeGenInfo::addNVVMMetadata(llvm::Function *F, StringRef Name,
5726 llvm::Module *M = F->getParent();
5727 llvm::LLVMContext &Ctx = M->getContext();
5729 // Get "nvvm.annotations" metadata node
5730 llvm::NamedMDNode *MD = M->getOrInsertNamedMetadata("nvvm.annotations");
5732 llvm::Metadata *MDVals[] = {
5733 llvm::ConstantAsMetadata::get(F), llvm::MDString::get(Ctx, Name),
5734 llvm::ConstantAsMetadata::get(
5735 llvm::ConstantInt::get(llvm::Type::getInt32Ty(Ctx), Operand))};
5736 // Append metadata to nvvm.annotations
5737 MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
5741 //===----------------------------------------------------------------------===//
5742 // SystemZ ABI Implementation
5743 //===----------------------------------------------------------------------===//
5747 class SystemZABIInfo : public SwiftABIInfo {
5751 SystemZABIInfo(CodeGenTypes &CGT, bool HV)
5752 : SwiftABIInfo(CGT), HasVector(HV) {}
5754 bool isPromotableIntegerType(QualType Ty) const;
5755 bool isCompoundType(QualType Ty) const;
5756 bool isVectorArgumentType(QualType Ty) const;
5757 bool isFPArgumentType(QualType Ty) const;
5758 QualType GetSingleElementType(QualType Ty) const;
5760 ABIArgInfo classifyReturnType(QualType RetTy) const;
5761 ABIArgInfo classifyArgumentType(QualType ArgTy) const;
5763 void computeInfo(CGFunctionInfo &FI) const override {
5764 if (!getCXXABI().classifyReturnType(FI))
5765 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
5766 for (auto &I : FI.arguments())
5767 I.info = classifyArgumentType(I.type);
5770 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5771 QualType Ty) const override;
5773 bool shouldPassIndirectlyForSwift(CharUnits totalSize,
5774 ArrayRef<llvm::Type*> scalars,
5775 bool asReturnValue) const override {
5776 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
5780 class SystemZTargetCodeGenInfo : public TargetCodeGenInfo {
5782 SystemZTargetCodeGenInfo(CodeGenTypes &CGT, bool HasVector)
5783 : TargetCodeGenInfo(new SystemZABIInfo(CGT, HasVector)) {}
5788 bool SystemZABIInfo::isPromotableIntegerType(QualType Ty) const {
5789 // Treat an enum type as its underlying type.
5790 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
5791 Ty = EnumTy->getDecl()->getIntegerType();
5793 // Promotable integer types are required to be promoted by the ABI.
5794 if (Ty->isPromotableIntegerType())
5797 // 32-bit values must also be promoted.
5798 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
5799 switch (BT->getKind()) {
5800 case BuiltinType::Int:
5801 case BuiltinType::UInt:
5809 bool SystemZABIInfo::isCompoundType(QualType Ty) const {
5810 return (Ty->isAnyComplexType() ||
5811 Ty->isVectorType() ||
5812 isAggregateTypeForABI(Ty));
5815 bool SystemZABIInfo::isVectorArgumentType(QualType Ty) const {
5816 return (HasVector &&
5817 Ty->isVectorType() &&
5818 getContext().getTypeSize(Ty) <= 128);
5821 bool SystemZABIInfo::isFPArgumentType(QualType Ty) const {
5822 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
5823 switch (BT->getKind()) {
5824 case BuiltinType::Float:
5825 case BuiltinType::Double:
5834 QualType SystemZABIInfo::GetSingleElementType(QualType Ty) const {
5835 if (const RecordType *RT = Ty->getAsStructureType()) {
5836 const RecordDecl *RD = RT->getDecl();
5839 // If this is a C++ record, check the bases first.
5840 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
5841 for (const auto &I : CXXRD->bases()) {
5842 QualType Base = I.getType();
5844 // Empty bases don't affect things either way.
5845 if (isEmptyRecord(getContext(), Base, true))
5848 if (!Found.isNull())
5850 Found = GetSingleElementType(Base);
5853 // Check the fields.
5854 for (const auto *FD : RD->fields()) {
5855 // For compatibility with GCC, ignore empty bitfields in C++ mode.
5856 // Unlike isSingleElementStruct(), empty structure and array fields
5857 // do count. So do anonymous bitfields that aren't zero-sized.
5858 if (getContext().getLangOpts().CPlusPlus &&
5859 FD->isBitField() && FD->getBitWidthValue(getContext()) == 0)
5862 // Unlike isSingleElementStruct(), arrays do not count.
5863 // Nested structures still do though.
5864 if (!Found.isNull())
5866 Found = GetSingleElementType(FD->getType());
5869 // Unlike isSingleElementStruct(), trailing padding is allowed.
5870 // An 8-byte aligned struct s { float f; } is passed as a double.
5871 if (!Found.isNull())
5878 Address SystemZABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5879 QualType Ty) const {
5880 // Assume that va_list type is correct; should be pointer to LLVM type:
5884 // i8 *__overflow_arg_area;
5885 // i8 *__reg_save_area;
5888 // Every non-vector argument occupies 8 bytes and is passed by preference
5889 // in either GPRs or FPRs. Vector arguments occupy 8 or 16 bytes and are
5890 // always passed on the stack.
5891 Ty = getContext().getCanonicalType(Ty);
5892 auto TyInfo = getContext().getTypeInfoInChars(Ty);
5893 llvm::Type *ArgTy = CGF.ConvertTypeForMem(Ty);
5894 llvm::Type *DirectTy = ArgTy;
5895 ABIArgInfo AI = classifyArgumentType(Ty);
5896 bool IsIndirect = AI.isIndirect();
5897 bool InFPRs = false;
5898 bool IsVector = false;
5899 CharUnits UnpaddedSize;
5900 CharUnits DirectAlign;
5902 DirectTy = llvm::PointerType::getUnqual(DirectTy);
5903 UnpaddedSize = DirectAlign = CharUnits::fromQuantity(8);
5905 if (AI.getCoerceToType())
5906 ArgTy = AI.getCoerceToType();
5907 InFPRs = ArgTy->isFloatTy() || ArgTy->isDoubleTy();
5908 IsVector = ArgTy->isVectorTy();
5909 UnpaddedSize = TyInfo.first;
5910 DirectAlign = TyInfo.second;
5912 CharUnits PaddedSize = CharUnits::fromQuantity(8);
5913 if (IsVector && UnpaddedSize > PaddedSize)
5914 PaddedSize = CharUnits::fromQuantity(16);
5915 assert((UnpaddedSize <= PaddedSize) && "Invalid argument size.");
5917 CharUnits Padding = (PaddedSize - UnpaddedSize);
5919 llvm::Type *IndexTy = CGF.Int64Ty;
5920 llvm::Value *PaddedSizeV =
5921 llvm::ConstantInt::get(IndexTy, PaddedSize.getQuantity());
5924 // Work out the address of a vector argument on the stack.
5925 // Vector arguments are always passed in the high bits of a
5926 // single (8 byte) or double (16 byte) stack slot.
5927 Address OverflowArgAreaPtr =
5928 CGF.Builder.CreateStructGEP(VAListAddr, 2, CharUnits::fromQuantity(16),
5929 "overflow_arg_area_ptr");
5930 Address OverflowArgArea =
5931 Address(CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"),
5934 CGF.Builder.CreateElementBitCast(OverflowArgArea, DirectTy, "mem_addr");
5936 // Update overflow_arg_area_ptr pointer
5937 llvm::Value *NewOverflowArgArea =
5938 CGF.Builder.CreateGEP(OverflowArgArea.getPointer(), PaddedSizeV,
5939 "overflow_arg_area");
5940 CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
5945 assert(PaddedSize.getQuantity() == 8);
5947 unsigned MaxRegs, RegCountField, RegSaveIndex;
5948 CharUnits RegPadding;
5950 MaxRegs = 4; // Maximum of 4 FPR arguments
5951 RegCountField = 1; // __fpr
5952 RegSaveIndex = 16; // save offset for f0
5953 RegPadding = CharUnits(); // floats are passed in the high bits of an FPR
5955 MaxRegs = 5; // Maximum of 5 GPR arguments
5956 RegCountField = 0; // __gpr
5957 RegSaveIndex = 2; // save offset for r2
5958 RegPadding = Padding; // values are passed in the low bits of a GPR
5961 Address RegCountPtr = CGF.Builder.CreateStructGEP(
5962 VAListAddr, RegCountField, RegCountField * CharUnits::fromQuantity(8),
5964 llvm::Value *RegCount = CGF.Builder.CreateLoad(RegCountPtr, "reg_count");
5965 llvm::Value *MaxRegsV = llvm::ConstantInt::get(IndexTy, MaxRegs);
5966 llvm::Value *InRegs = CGF.Builder.CreateICmpULT(RegCount, MaxRegsV,
5969 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
5970 llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
5971 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
5972 CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
5974 // Emit code to load the value if it was passed in registers.
5975 CGF.EmitBlock(InRegBlock);
5977 // Work out the address of an argument register.
5978 llvm::Value *ScaledRegCount =
5979 CGF.Builder.CreateMul(RegCount, PaddedSizeV, "scaled_reg_count");
5980 llvm::Value *RegBase =
5981 llvm::ConstantInt::get(IndexTy, RegSaveIndex * PaddedSize.getQuantity()
5982 + RegPadding.getQuantity());
5983 llvm::Value *RegOffset =
5984 CGF.Builder.CreateAdd(ScaledRegCount, RegBase, "reg_offset");
5985 Address RegSaveAreaPtr =
5986 CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(24),
5987 "reg_save_area_ptr");
5988 llvm::Value *RegSaveArea =
5989 CGF.Builder.CreateLoad(RegSaveAreaPtr, "reg_save_area");
5990 Address RawRegAddr(CGF.Builder.CreateGEP(RegSaveArea, RegOffset,
5994 CGF.Builder.CreateElementBitCast(RawRegAddr, DirectTy, "reg_addr");
5996 // Update the register count
5997 llvm::Value *One = llvm::ConstantInt::get(IndexTy, 1);
5998 llvm::Value *NewRegCount =
5999 CGF.Builder.CreateAdd(RegCount, One, "reg_count");
6000 CGF.Builder.CreateStore(NewRegCount, RegCountPtr);
6001 CGF.EmitBranch(ContBlock);
6003 // Emit code to load the value if it was passed in memory.
6004 CGF.EmitBlock(InMemBlock);
6006 // Work out the address of a stack argument.
6007 Address OverflowArgAreaPtr = CGF.Builder.CreateStructGEP(
6008 VAListAddr, 2, CharUnits::fromQuantity(16), "overflow_arg_area_ptr");
6009 Address OverflowArgArea =
6010 Address(CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"),
6012 Address RawMemAddr =
6013 CGF.Builder.CreateConstByteGEP(OverflowArgArea, Padding, "raw_mem_addr");
6015 CGF.Builder.CreateElementBitCast(RawMemAddr, DirectTy, "mem_addr");
6017 // Update overflow_arg_area_ptr pointer
6018 llvm::Value *NewOverflowArgArea =
6019 CGF.Builder.CreateGEP(OverflowArgArea.getPointer(), PaddedSizeV,
6020 "overflow_arg_area");
6021 CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
6022 CGF.EmitBranch(ContBlock);
6024 // Return the appropriate result.
6025 CGF.EmitBlock(ContBlock);
6026 Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
6027 MemAddr, InMemBlock, "va_arg.addr");
6030 ResAddr = Address(CGF.Builder.CreateLoad(ResAddr, "indirect_arg"),
6036 ABIArgInfo SystemZABIInfo::classifyReturnType(QualType RetTy) const {
6037 if (RetTy->isVoidType())
6038 return ABIArgInfo::getIgnore();
6039 if (isVectorArgumentType(RetTy))
6040 return ABIArgInfo::getDirect();
6041 if (isCompoundType(RetTy) || getContext().getTypeSize(RetTy) > 64)
6042 return getNaturalAlignIndirect(RetTy);
6043 return (isPromotableIntegerType(RetTy) ?
6044 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6047 ABIArgInfo SystemZABIInfo::classifyArgumentType(QualType Ty) const {
6048 // Handle the generic C++ ABI.
6049 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
6050 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
6052 // Integers and enums are extended to full register width.
6053 if (isPromotableIntegerType(Ty))
6054 return ABIArgInfo::getExtend();
6056 // Handle vector types and vector-like structure types. Note that
6057 // as opposed to float-like structure types, we do not allow any
6058 // padding for vector-like structures, so verify the sizes match.
6059 uint64_t Size = getContext().getTypeSize(Ty);
6060 QualType SingleElementTy = GetSingleElementType(Ty);
6061 if (isVectorArgumentType(SingleElementTy) &&
6062 getContext().getTypeSize(SingleElementTy) == Size)
6063 return ABIArgInfo::getDirect(CGT.ConvertType(SingleElementTy));
6065 // Values that are not 1, 2, 4 or 8 bytes in size are passed indirectly.
6066 if (Size != 8 && Size != 16 && Size != 32 && Size != 64)
6067 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6069 // Handle small structures.
6070 if (const RecordType *RT = Ty->getAs<RecordType>()) {
6071 // Structures with flexible arrays have variable length, so really
6072 // fail the size test above.
6073 const RecordDecl *RD = RT->getDecl();
6074 if (RD->hasFlexibleArrayMember())
6075 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6077 // The structure is passed as an unextended integer, a float, or a double.
6079 if (isFPArgumentType(SingleElementTy)) {
6080 assert(Size == 32 || Size == 64);
6082 PassTy = llvm::Type::getFloatTy(getVMContext());
6084 PassTy = llvm::Type::getDoubleTy(getVMContext());
6086 PassTy = llvm::IntegerType::get(getVMContext(), Size);
6087 return ABIArgInfo::getDirect(PassTy);
6090 // Non-structure compounds are passed indirectly.
6091 if (isCompoundType(Ty))
6092 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6094 return ABIArgInfo::getDirect(nullptr);
6097 //===----------------------------------------------------------------------===//
6098 // MSP430 ABI Implementation
6099 //===----------------------------------------------------------------------===//
6103 class MSP430TargetCodeGenInfo : public TargetCodeGenInfo {
6105 MSP430TargetCodeGenInfo(CodeGenTypes &CGT)
6106 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
6107 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6108 CodeGen::CodeGenModule &M) const override;
6113 void MSP430TargetCodeGenInfo::setTargetAttributes(const Decl *D,
6114 llvm::GlobalValue *GV,
6115 CodeGen::CodeGenModule &M) const {
6116 if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
6117 if (const MSP430InterruptAttr *attr = FD->getAttr<MSP430InterruptAttr>()) {
6118 // Handle 'interrupt' attribute:
6119 llvm::Function *F = cast<llvm::Function>(GV);
6121 // Step 1: Set ISR calling convention.
6122 F->setCallingConv(llvm::CallingConv::MSP430_INTR);
6124 // Step 2: Add attributes goodness.
6125 F->addFnAttr(llvm::Attribute::NoInline);
6127 // Step 3: Emit ISR vector alias.
6128 unsigned Num = attr->getNumber() / 2;
6129 llvm::GlobalAlias::create(llvm::Function::ExternalLinkage,
6130 "__isr_" + Twine(Num), F);
6135 //===----------------------------------------------------------------------===//
6136 // MIPS ABI Implementation. This works for both little-endian and
6137 // big-endian variants.
6138 //===----------------------------------------------------------------------===//
6141 class MipsABIInfo : public ABIInfo {
6143 unsigned MinABIStackAlignInBytes, StackAlignInBytes;
6144 void CoerceToIntArgs(uint64_t TySize,
6145 SmallVectorImpl<llvm::Type *> &ArgList) const;
6146 llvm::Type* HandleAggregates(QualType Ty, uint64_t TySize) const;
6147 llvm::Type* returnAggregateInRegs(QualType RetTy, uint64_t Size) const;
6148 llvm::Type* getPaddingType(uint64_t Align, uint64_t Offset) const;
6150 MipsABIInfo(CodeGenTypes &CGT, bool _IsO32) :
6151 ABIInfo(CGT), IsO32(_IsO32), MinABIStackAlignInBytes(IsO32 ? 4 : 8),
6152 StackAlignInBytes(IsO32 ? 8 : 16) {}
6154 ABIArgInfo classifyReturnType(QualType RetTy) const;
6155 ABIArgInfo classifyArgumentType(QualType RetTy, uint64_t &Offset) const;
6156 void computeInfo(CGFunctionInfo &FI) const override;
6157 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6158 QualType Ty) const override;
6159 bool shouldSignExtUnsignedType(QualType Ty) const override;
6162 class MIPSTargetCodeGenInfo : public TargetCodeGenInfo {
6163 unsigned SizeOfUnwindException;
6165 MIPSTargetCodeGenInfo(CodeGenTypes &CGT, bool IsO32)
6166 : TargetCodeGenInfo(new MipsABIInfo(CGT, IsO32)),
6167 SizeOfUnwindException(IsO32 ? 24 : 32) {}
6169 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
6173 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6174 CodeGen::CodeGenModule &CGM) const override {
6175 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
6177 llvm::Function *Fn = cast<llvm::Function>(GV);
6178 if (FD->hasAttr<Mips16Attr>()) {
6179 Fn->addFnAttr("mips16");
6181 else if (FD->hasAttr<NoMips16Attr>()) {
6182 Fn->addFnAttr("nomips16");
6185 const MipsInterruptAttr *Attr = FD->getAttr<MipsInterruptAttr>();
6190 switch (Attr->getInterrupt()) {
6191 case MipsInterruptAttr::eic: Kind = "eic"; break;
6192 case MipsInterruptAttr::sw0: Kind = "sw0"; break;
6193 case MipsInterruptAttr::sw1: Kind = "sw1"; break;
6194 case MipsInterruptAttr::hw0: Kind = "hw0"; break;
6195 case MipsInterruptAttr::hw1: Kind = "hw1"; break;
6196 case MipsInterruptAttr::hw2: Kind = "hw2"; break;
6197 case MipsInterruptAttr::hw3: Kind = "hw3"; break;
6198 case MipsInterruptAttr::hw4: Kind = "hw4"; break;
6199 case MipsInterruptAttr::hw5: Kind = "hw5"; break;
6202 Fn->addFnAttr("interrupt", Kind);
6206 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
6207 llvm::Value *Address) const override;
6209 unsigned getSizeOfUnwindException() const override {
6210 return SizeOfUnwindException;
6215 void MipsABIInfo::CoerceToIntArgs(
6216 uint64_t TySize, SmallVectorImpl<llvm::Type *> &ArgList) const {
6217 llvm::IntegerType *IntTy =
6218 llvm::IntegerType::get(getVMContext(), MinABIStackAlignInBytes * 8);
6220 // Add (TySize / MinABIStackAlignInBytes) args of IntTy.
6221 for (unsigned N = TySize / (MinABIStackAlignInBytes * 8); N; --N)
6222 ArgList.push_back(IntTy);
6224 // If necessary, add one more integer type to ArgList.
6225 unsigned R = TySize % (MinABIStackAlignInBytes * 8);
6228 ArgList.push_back(llvm::IntegerType::get(getVMContext(), R));
6231 // In N32/64, an aligned double precision floating point field is passed in
6233 llvm::Type* MipsABIInfo::HandleAggregates(QualType Ty, uint64_t TySize) const {
6234 SmallVector<llvm::Type*, 8> ArgList, IntArgList;
6237 CoerceToIntArgs(TySize, ArgList);
6238 return llvm::StructType::get(getVMContext(), ArgList);
6241 if (Ty->isComplexType())
6242 return CGT.ConvertType(Ty);
6244 const RecordType *RT = Ty->getAs<RecordType>();
6246 // Unions/vectors are passed in integer registers.
6247 if (!RT || !RT->isStructureOrClassType()) {
6248 CoerceToIntArgs(TySize, ArgList);
6249 return llvm::StructType::get(getVMContext(), ArgList);
6252 const RecordDecl *RD = RT->getDecl();
6253 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
6254 assert(!(TySize % 8) && "Size of structure must be multiple of 8.");
6256 uint64_t LastOffset = 0;
6258 llvm::IntegerType *I64 = llvm::IntegerType::get(getVMContext(), 64);
6260 // Iterate over fields in the struct/class and check if there are any aligned
6262 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
6263 i != e; ++i, ++idx) {
6264 const QualType Ty = i->getType();
6265 const BuiltinType *BT = Ty->getAs<BuiltinType>();
6267 if (!BT || BT->getKind() != BuiltinType::Double)
6270 uint64_t Offset = Layout.getFieldOffset(idx);
6271 if (Offset % 64) // Ignore doubles that are not aligned.
6274 // Add ((Offset - LastOffset) / 64) args of type i64.
6275 for (unsigned j = (Offset - LastOffset) / 64; j > 0; --j)
6276 ArgList.push_back(I64);
6279 ArgList.push_back(llvm::Type::getDoubleTy(getVMContext()));
6280 LastOffset = Offset + 64;
6283 CoerceToIntArgs(TySize - LastOffset, IntArgList);
6284 ArgList.append(IntArgList.begin(), IntArgList.end());
6286 return llvm::StructType::get(getVMContext(), ArgList);
6289 llvm::Type *MipsABIInfo::getPaddingType(uint64_t OrigOffset,
6290 uint64_t Offset) const {
6291 if (OrigOffset + MinABIStackAlignInBytes > Offset)
6294 return llvm::IntegerType::get(getVMContext(), (Offset - OrigOffset) * 8);
6298 MipsABIInfo::classifyArgumentType(QualType Ty, uint64_t &Offset) const {
6299 Ty = useFirstFieldIfTransparentUnion(Ty);
6301 uint64_t OrigOffset = Offset;
6302 uint64_t TySize = getContext().getTypeSize(Ty);
6303 uint64_t Align = getContext().getTypeAlign(Ty) / 8;
6305 Align = std::min(std::max(Align, (uint64_t)MinABIStackAlignInBytes),
6306 (uint64_t)StackAlignInBytes);
6307 unsigned CurrOffset = llvm::alignTo(Offset, Align);
6308 Offset = CurrOffset + llvm::alignTo(TySize, Align * 8) / 8;
6310 if (isAggregateTypeForABI(Ty) || Ty->isVectorType()) {
6311 // Ignore empty aggregates.
6313 return ABIArgInfo::getIgnore();
6315 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
6316 Offset = OrigOffset + MinABIStackAlignInBytes;
6317 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
6320 // If we have reached here, aggregates are passed directly by coercing to
6321 // another structure type. Padding is inserted if the offset of the
6322 // aggregate is unaligned.
6323 ABIArgInfo ArgInfo =
6324 ABIArgInfo::getDirect(HandleAggregates(Ty, TySize), 0,
6325 getPaddingType(OrigOffset, CurrOffset));
6326 ArgInfo.setInReg(true);
6330 // Treat an enum type as its underlying type.
6331 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6332 Ty = EnumTy->getDecl()->getIntegerType();
6334 // All integral types are promoted to the GPR width.
6335 if (Ty->isIntegralOrEnumerationType())
6336 return ABIArgInfo::getExtend();
6338 return ABIArgInfo::getDirect(
6339 nullptr, 0, IsO32 ? nullptr : getPaddingType(OrigOffset, CurrOffset));
6343 MipsABIInfo::returnAggregateInRegs(QualType RetTy, uint64_t Size) const {
6344 const RecordType *RT = RetTy->getAs<RecordType>();
6345 SmallVector<llvm::Type*, 8> RTList;
6347 if (RT && RT->isStructureOrClassType()) {
6348 const RecordDecl *RD = RT->getDecl();
6349 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
6350 unsigned FieldCnt = Layout.getFieldCount();
6352 // N32/64 returns struct/classes in floating point registers if the
6353 // following conditions are met:
6354 // 1. The size of the struct/class is no larger than 128-bit.
6355 // 2. The struct/class has one or two fields all of which are floating
6357 // 3. The offset of the first field is zero (this follows what gcc does).
6359 // Any other composite results are returned in integer registers.
6361 if (FieldCnt && (FieldCnt <= 2) && !Layout.getFieldOffset(0)) {
6362 RecordDecl::field_iterator b = RD->field_begin(), e = RD->field_end();
6363 for (; b != e; ++b) {
6364 const BuiltinType *BT = b->getType()->getAs<BuiltinType>();
6366 if (!BT || !BT->isFloatingPoint())
6369 RTList.push_back(CGT.ConvertType(b->getType()));
6373 return llvm::StructType::get(getVMContext(), RTList,
6374 RD->hasAttr<PackedAttr>());
6380 CoerceToIntArgs(Size, RTList);
6381 return llvm::StructType::get(getVMContext(), RTList);
6384 ABIArgInfo MipsABIInfo::classifyReturnType(QualType RetTy) const {
6385 uint64_t Size = getContext().getTypeSize(RetTy);
6387 if (RetTy->isVoidType())
6388 return ABIArgInfo::getIgnore();
6390 // O32 doesn't treat zero-sized structs differently from other structs.
6391 // However, N32/N64 ignores zero sized return values.
6392 if (!IsO32 && Size == 0)
6393 return ABIArgInfo::getIgnore();
6395 if (isAggregateTypeForABI(RetTy) || RetTy->isVectorType()) {
6397 if (RetTy->isAnyComplexType())
6398 return ABIArgInfo::getDirect();
6400 // O32 returns integer vectors in registers and N32/N64 returns all small
6401 // aggregates in registers.
6403 (RetTy->isVectorType() && !RetTy->hasFloatingRepresentation())) {
6404 ABIArgInfo ArgInfo =
6405 ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size));
6406 ArgInfo.setInReg(true);
6411 return getNaturalAlignIndirect(RetTy);
6414 // Treat an enum type as its underlying type.
6415 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
6416 RetTy = EnumTy->getDecl()->getIntegerType();
6418 return (RetTy->isPromotableIntegerType() ?
6419 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6422 void MipsABIInfo::computeInfo(CGFunctionInfo &FI) const {
6423 ABIArgInfo &RetInfo = FI.getReturnInfo();
6424 if (!getCXXABI().classifyReturnType(FI))
6425 RetInfo = classifyReturnType(FI.getReturnType());
6427 // Check if a pointer to an aggregate is passed as a hidden argument.
6428 uint64_t Offset = RetInfo.isIndirect() ? MinABIStackAlignInBytes : 0;
6430 for (auto &I : FI.arguments())
6431 I.info = classifyArgumentType(I.type, Offset);
6434 Address MipsABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6435 QualType OrigTy) const {
6436 QualType Ty = OrigTy;
6438 // Integer arguments are promoted to 32-bit on O32 and 64-bit on N32/N64.
6439 // Pointers are also promoted in the same way but this only matters for N32.
6440 unsigned SlotSizeInBits = IsO32 ? 32 : 64;
6441 unsigned PtrWidth = getTarget().getPointerWidth(0);
6442 bool DidPromote = false;
6443 if ((Ty->isIntegerType() &&
6444 getContext().getIntWidth(Ty) < SlotSizeInBits) ||
6445 (Ty->isPointerType() && PtrWidth < SlotSizeInBits)) {
6447 Ty = getContext().getIntTypeForBitwidth(SlotSizeInBits,
6448 Ty->isSignedIntegerType());
6451 auto TyInfo = getContext().getTypeInfoInChars(Ty);
6453 // The alignment of things in the argument area is never larger than
6454 // StackAlignInBytes.
6456 std::min(TyInfo.second, CharUnits::fromQuantity(StackAlignInBytes));
6458 // MinABIStackAlignInBytes is the size of argument slots on the stack.
6459 CharUnits ArgSlotSize = CharUnits::fromQuantity(MinABIStackAlignInBytes);
6461 Address Addr = emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
6462 TyInfo, ArgSlotSize, /*AllowHigherAlign*/ true);
6465 // If there was a promotion, "unpromote" into a temporary.
6466 // TODO: can we just use a pointer into a subset of the original slot?
6468 Address Temp = CGF.CreateMemTemp(OrigTy, "vaarg.promotion-temp");
6469 llvm::Value *Promoted = CGF.Builder.CreateLoad(Addr);
6471 // Truncate down to the right width.
6472 llvm::Type *IntTy = (OrigTy->isIntegerType() ? Temp.getElementType()
6474 llvm::Value *V = CGF.Builder.CreateTrunc(Promoted, IntTy);
6475 if (OrigTy->isPointerType())
6476 V = CGF.Builder.CreateIntToPtr(V, Temp.getElementType());
6478 CGF.Builder.CreateStore(V, Temp);
6485 bool MipsABIInfo::shouldSignExtUnsignedType(QualType Ty) const {
6486 int TySize = getContext().getTypeSize(Ty);
6488 // MIPS64 ABI requires unsigned 32 bit integers to be sign extended.
6489 if (Ty->isUnsignedIntegerOrEnumerationType() && TySize == 32)
6496 MIPSTargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
6497 llvm::Value *Address) const {
6498 // This information comes from gcc's implementation, which seems to
6499 // as canonical as it gets.
6501 // Everything on MIPS is 4 bytes. Double-precision FP registers
6502 // are aliased to pairs of single-precision FP registers.
6503 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
6505 // 0-31 are the general purpose registers, $0 - $31.
6506 // 32-63 are the floating-point registers, $f0 - $f31.
6507 // 64 and 65 are the multiply/divide registers, $hi and $lo.
6508 // 66 is the (notional, I think) register for signal-handler return.
6509 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 65);
6511 // 67-74 are the floating-point status registers, $fcc0 - $fcc7.
6512 // They are one bit wide and ignored here.
6514 // 80-111 are the coprocessor 0 registers, $c0r0 - $c0r31.
6515 // (coprocessor 1 is the FP unit)
6516 // 112-143 are the coprocessor 2 registers, $c2r0 - $c2r31.
6517 // 144-175 are the coprocessor 3 registers, $c3r0 - $c3r31.
6518 // 176-181 are the DSP accumulator registers.
6519 AssignToArrayRange(CGF.Builder, Address, Four8, 80, 181);
6523 //===----------------------------------------------------------------------===//
6524 // TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults.
6525 // Currently subclassed only to implement custom OpenCL C function attribute
6527 //===----------------------------------------------------------------------===//
6531 class TCETargetCodeGenInfo : public DefaultTargetCodeGenInfo {
6533 TCETargetCodeGenInfo(CodeGenTypes &CGT)
6534 : DefaultTargetCodeGenInfo(CGT) {}
6536 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6537 CodeGen::CodeGenModule &M) const override;
6540 void TCETargetCodeGenInfo::setTargetAttributes(
6541 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
6542 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
6545 llvm::Function *F = cast<llvm::Function>(GV);
6547 if (M.getLangOpts().OpenCL) {
6548 if (FD->hasAttr<OpenCLKernelAttr>()) {
6549 // OpenCL C Kernel functions are not subject to inlining
6550 F->addFnAttr(llvm::Attribute::NoInline);
6551 const ReqdWorkGroupSizeAttr *Attr = FD->getAttr<ReqdWorkGroupSizeAttr>();
6553 // Convert the reqd_work_group_size() attributes to metadata.
6554 llvm::LLVMContext &Context = F->getContext();
6555 llvm::NamedMDNode *OpenCLMetadata =
6556 M.getModule().getOrInsertNamedMetadata(
6557 "opencl.kernel_wg_size_info");
6559 SmallVector<llvm::Metadata *, 5> Operands;
6560 Operands.push_back(llvm::ConstantAsMetadata::get(F));
6563 llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
6564 M.Int32Ty, llvm::APInt(32, Attr->getXDim()))));
6566 llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
6567 M.Int32Ty, llvm::APInt(32, Attr->getYDim()))));
6569 llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
6570 M.Int32Ty, llvm::APInt(32, Attr->getZDim()))));
6572 // Add a boolean constant operand for "required" (true) or "hint"
6573 // (false) for implementing the work_group_size_hint attr later.
6574 // Currently always true as the hint is not yet implemented.
6576 llvm::ConstantAsMetadata::get(llvm::ConstantInt::getTrue(Context)));
6577 OpenCLMetadata->addOperand(llvm::MDNode::get(Context, Operands));
6585 //===----------------------------------------------------------------------===//
6586 // Hexagon ABI Implementation
6587 //===----------------------------------------------------------------------===//
6591 class HexagonABIInfo : public ABIInfo {
6595 HexagonABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
6599 ABIArgInfo classifyReturnType(QualType RetTy) const;
6600 ABIArgInfo classifyArgumentType(QualType RetTy) const;
6602 void computeInfo(CGFunctionInfo &FI) const override;
6604 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6605 QualType Ty) const override;
6608 class HexagonTargetCodeGenInfo : public TargetCodeGenInfo {
6610 HexagonTargetCodeGenInfo(CodeGenTypes &CGT)
6611 :TargetCodeGenInfo(new HexagonABIInfo(CGT)) {}
6613 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
6620 void HexagonABIInfo::computeInfo(CGFunctionInfo &FI) const {
6621 if (!getCXXABI().classifyReturnType(FI))
6622 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
6623 for (auto &I : FI.arguments())
6624 I.info = classifyArgumentType(I.type);
6627 ABIArgInfo HexagonABIInfo::classifyArgumentType(QualType Ty) const {
6628 if (!isAggregateTypeForABI(Ty)) {
6629 // Treat an enum type as its underlying type.
6630 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6631 Ty = EnumTy->getDecl()->getIntegerType();
6633 return (Ty->isPromotableIntegerType() ?
6634 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6637 // Ignore empty records.
6638 if (isEmptyRecord(getContext(), Ty, true))
6639 return ABIArgInfo::getIgnore();
6641 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
6642 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
6644 uint64_t Size = getContext().getTypeSize(Ty);
6646 return getNaturalAlignIndirect(Ty, /*ByVal=*/true);
6647 // Pass in the smallest viable integer type.
6649 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
6651 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6653 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
6655 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
6658 ABIArgInfo HexagonABIInfo::classifyReturnType(QualType RetTy) const {
6659 if (RetTy->isVoidType())
6660 return ABIArgInfo::getIgnore();
6662 // Large vector types should be returned via memory.
6663 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 64)
6664 return getNaturalAlignIndirect(RetTy);
6666 if (!isAggregateTypeForABI(RetTy)) {
6667 // Treat an enum type as its underlying type.
6668 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
6669 RetTy = EnumTy->getDecl()->getIntegerType();
6671 return (RetTy->isPromotableIntegerType() ?
6672 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6675 if (isEmptyRecord(getContext(), RetTy, true))
6676 return ABIArgInfo::getIgnore();
6678 // Aggregates <= 8 bytes are returned in r0; other aggregates
6679 // are returned indirectly.
6680 uint64_t Size = getContext().getTypeSize(RetTy);
6682 // Return in the smallest viable integer type.
6684 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
6686 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
6688 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6689 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
6692 return getNaturalAlignIndirect(RetTy, /*ByVal=*/true);
6695 Address HexagonABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6696 QualType Ty) const {
6697 // FIXME: Someone needs to audit that this handle alignment correctly.
6698 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
6699 getContext().getTypeInfoInChars(Ty),
6700 CharUnits::fromQuantity(4),
6701 /*AllowHigherAlign*/ true);
6704 //===----------------------------------------------------------------------===//
6705 // Lanai ABI Implementation
6706 //===----------------------------------------------------------------------===//
6709 class LanaiABIInfo : public DefaultABIInfo {
6711 LanaiABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
6713 bool shouldUseInReg(QualType Ty, CCState &State) const;
6715 void computeInfo(CGFunctionInfo &FI) const override {
6716 CCState State(FI.getCallingConvention());
6717 // Lanai uses 4 registers to pass arguments unless the function has the
6718 // regparm attribute set.
6719 if (FI.getHasRegParm()) {
6720 State.FreeRegs = FI.getRegParm();
6725 if (!getCXXABI().classifyReturnType(FI))
6726 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
6727 for (auto &I : FI.arguments())
6728 I.info = classifyArgumentType(I.type, State);
6731 ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
6732 ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
6734 } // end anonymous namespace
6736 bool LanaiABIInfo::shouldUseInReg(QualType Ty, CCState &State) const {
6737 unsigned Size = getContext().getTypeSize(Ty);
6738 unsigned SizeInRegs = llvm::alignTo(Size, 32U) / 32U;
6740 if (SizeInRegs == 0)
6743 if (SizeInRegs > State.FreeRegs) {
6748 State.FreeRegs -= SizeInRegs;
6753 ABIArgInfo LanaiABIInfo::getIndirectResult(QualType Ty, bool ByVal,
6754 CCState &State) const {
6756 if (State.FreeRegs) {
6757 --State.FreeRegs; // Non-byval indirects just use one pointer.
6758 return getNaturalAlignIndirectInReg(Ty);
6760 return getNaturalAlignIndirect(Ty, false);
6763 // Compute the byval alignment.
6764 const unsigned MinABIStackAlignInBytes = 4;
6765 unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
6766 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true,
6767 /*Realign=*/TypeAlign >
6768 MinABIStackAlignInBytes);
6771 ABIArgInfo LanaiABIInfo::classifyArgumentType(QualType Ty,
6772 CCState &State) const {
6773 // Check with the C++ ABI first.
6774 const RecordType *RT = Ty->getAs<RecordType>();
6776 CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
6777 if (RAA == CGCXXABI::RAA_Indirect) {
6778 return getIndirectResult(Ty, /*ByVal=*/false, State);
6779 } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
6780 return getNaturalAlignIndirect(Ty, /*ByRef=*/true);
6784 if (isAggregateTypeForABI(Ty)) {
6785 // Structures with flexible arrays are always indirect.
6786 if (RT && RT->getDecl()->hasFlexibleArrayMember())
6787 return getIndirectResult(Ty, /*ByVal=*/true, State);
6789 // Ignore empty structs/unions.
6790 if (isEmptyRecord(getContext(), Ty, true))
6791 return ABIArgInfo::getIgnore();
6793 llvm::LLVMContext &LLVMContext = getVMContext();
6794 unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
6795 if (SizeInRegs <= State.FreeRegs) {
6796 llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
6797 SmallVector<llvm::Type *, 3> Elements(SizeInRegs, Int32);
6798 llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
6799 State.FreeRegs -= SizeInRegs;
6800 return ABIArgInfo::getDirectInReg(Result);
6804 return getIndirectResult(Ty, true, State);
6807 // Treat an enum type as its underlying type.
6808 if (const auto *EnumTy = Ty->getAs<EnumType>())
6809 Ty = EnumTy->getDecl()->getIntegerType();
6811 bool InReg = shouldUseInReg(Ty, State);
6812 if (Ty->isPromotableIntegerType()) {
6814 return ABIArgInfo::getDirectInReg();
6815 return ABIArgInfo::getExtend();
6818 return ABIArgInfo::getDirectInReg();
6819 return ABIArgInfo::getDirect();
6823 class LanaiTargetCodeGenInfo : public TargetCodeGenInfo {
6825 LanaiTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
6826 : TargetCodeGenInfo(new LanaiABIInfo(CGT)) {}
6830 //===----------------------------------------------------------------------===//
6831 // AMDGPU ABI Implementation
6832 //===----------------------------------------------------------------------===//
6836 class AMDGPUTargetCodeGenInfo : public TargetCodeGenInfo {
6838 AMDGPUTargetCodeGenInfo(CodeGenTypes &CGT)
6839 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
6840 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6841 CodeGen::CodeGenModule &M) const override;
6842 unsigned getOpenCLKernelCallingConv() const override;
6847 void AMDGPUTargetCodeGenInfo::setTargetAttributes(
6849 llvm::GlobalValue *GV,
6850 CodeGen::CodeGenModule &M) const {
6851 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
6855 if (const auto Attr = FD->getAttr<AMDGPUNumVGPRAttr>()) {
6856 llvm::Function *F = cast<llvm::Function>(GV);
6857 uint32_t NumVGPR = Attr->getNumVGPR();
6859 F->addFnAttr("amdgpu_num_vgpr", llvm::utostr(NumVGPR));
6862 if (const auto Attr = FD->getAttr<AMDGPUNumSGPRAttr>()) {
6863 llvm::Function *F = cast<llvm::Function>(GV);
6864 unsigned NumSGPR = Attr->getNumSGPR();
6866 F->addFnAttr("amdgpu_num_sgpr", llvm::utostr(NumSGPR));
6871 unsigned AMDGPUTargetCodeGenInfo::getOpenCLKernelCallingConv() const {
6872 return llvm::CallingConv::AMDGPU_KERNEL;
6875 //===----------------------------------------------------------------------===//
6876 // SPARC v8 ABI Implementation.
6877 // Based on the SPARC Compliance Definition version 2.4.1.
6879 // Ensures that complex values are passed in registers.
6882 class SparcV8ABIInfo : public DefaultABIInfo {
6884 SparcV8ABIInfo(CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
6887 ABIArgInfo classifyReturnType(QualType RetTy) const;
6888 void computeInfo(CGFunctionInfo &FI) const override;
6890 } // end anonymous namespace
6894 SparcV8ABIInfo::classifyReturnType(QualType Ty) const {
6895 if (Ty->isAnyComplexType()) {
6896 return ABIArgInfo::getDirect();
6899 return DefaultABIInfo::classifyReturnType(Ty);
6903 void SparcV8ABIInfo::computeInfo(CGFunctionInfo &FI) const {
6905 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
6906 for (auto &Arg : FI.arguments())
6907 Arg.info = classifyArgumentType(Arg.type);
6911 class SparcV8TargetCodeGenInfo : public TargetCodeGenInfo {
6913 SparcV8TargetCodeGenInfo(CodeGenTypes &CGT)
6914 : TargetCodeGenInfo(new SparcV8ABIInfo(CGT)) {}
6916 } // end anonymous namespace
6918 //===----------------------------------------------------------------------===//
6919 // SPARC v9 ABI Implementation.
6920 // Based on the SPARC Compliance Definition version 2.4.1.
6922 // Function arguments a mapped to a nominal "parameter array" and promoted to
6923 // registers depending on their type. Each argument occupies 8 or 16 bytes in
6924 // the array, structs larger than 16 bytes are passed indirectly.
6926 // One case requires special care:
6933 // When a struct mixed is passed by value, it only occupies 8 bytes in the
6934 // parameter array, but the int is passed in an integer register, and the float
6935 // is passed in a floating point register. This is represented as two arguments
6936 // with the LLVM IR inreg attribute:
6938 // declare void f(i32 inreg %i, float inreg %f)
6940 // The code generator will only allocate 4 bytes from the parameter array for
6941 // the inreg arguments. All other arguments are allocated a multiple of 8
6945 class SparcV9ABIInfo : public ABIInfo {
6947 SparcV9ABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
6950 ABIArgInfo classifyType(QualType RetTy, unsigned SizeLimit) const;
6951 void computeInfo(CGFunctionInfo &FI) const override;
6952 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6953 QualType Ty) const override;
6955 // Coercion type builder for structs passed in registers. The coercion type
6956 // serves two purposes:
6958 // 1. Pad structs to a multiple of 64 bits, so they are passed 'left-aligned'
6960 // 2. Expose aligned floating point elements as first-level elements, so the
6961 // code generator knows to pass them in floating point registers.
6963 // We also compute the InReg flag which indicates that the struct contains
6964 // aligned 32-bit floats.
6966 struct CoerceBuilder {
6967 llvm::LLVMContext &Context;
6968 const llvm::DataLayout &DL;
6969 SmallVector<llvm::Type*, 8> Elems;
6973 CoerceBuilder(llvm::LLVMContext &c, const llvm::DataLayout &dl)
6974 : Context(c), DL(dl), Size(0), InReg(false) {}
6976 // Pad Elems with integers until Size is ToSize.
6977 void pad(uint64_t ToSize) {
6978 assert(ToSize >= Size && "Cannot remove elements");
6982 // Finish the current 64-bit word.
6983 uint64_t Aligned = llvm::alignTo(Size, 64);
6984 if (Aligned > Size && Aligned <= ToSize) {
6985 Elems.push_back(llvm::IntegerType::get(Context, Aligned - Size));
6989 // Add whole 64-bit words.
6990 while (Size + 64 <= ToSize) {
6991 Elems.push_back(llvm::Type::getInt64Ty(Context));
6995 // Final in-word padding.
6996 if (Size < ToSize) {
6997 Elems.push_back(llvm::IntegerType::get(Context, ToSize - Size));
7002 // Add a floating point element at Offset.
7003 void addFloat(uint64_t Offset, llvm::Type *Ty, unsigned Bits) {
7004 // Unaligned floats are treated as integers.
7007 // The InReg flag is only required if there are any floats < 64 bits.
7011 Elems.push_back(Ty);
7012 Size = Offset + Bits;
7015 // Add a struct type to the coercion type, starting at Offset (in bits).
7016 void addStruct(uint64_t Offset, llvm::StructType *StrTy) {
7017 const llvm::StructLayout *Layout = DL.getStructLayout(StrTy);
7018 for (unsigned i = 0, e = StrTy->getNumElements(); i != e; ++i) {
7019 llvm::Type *ElemTy = StrTy->getElementType(i);
7020 uint64_t ElemOffset = Offset + Layout->getElementOffsetInBits(i);
7021 switch (ElemTy->getTypeID()) {
7022 case llvm::Type::StructTyID:
7023 addStruct(ElemOffset, cast<llvm::StructType>(ElemTy));
7025 case llvm::Type::FloatTyID:
7026 addFloat(ElemOffset, ElemTy, 32);
7028 case llvm::Type::DoubleTyID:
7029 addFloat(ElemOffset, ElemTy, 64);
7031 case llvm::Type::FP128TyID:
7032 addFloat(ElemOffset, ElemTy, 128);
7034 case llvm::Type::PointerTyID:
7035 if (ElemOffset % 64 == 0) {
7037 Elems.push_back(ElemTy);
7047 // Check if Ty is a usable substitute for the coercion type.
7048 bool isUsableType(llvm::StructType *Ty) const {
7049 return llvm::makeArrayRef(Elems) == Ty->elements();
7052 // Get the coercion type as a literal struct type.
7053 llvm::Type *getType() const {
7054 if (Elems.size() == 1)
7055 return Elems.front();
7057 return llvm::StructType::get(Context, Elems);
7061 } // end anonymous namespace
7064 SparcV9ABIInfo::classifyType(QualType Ty, unsigned SizeLimit) const {
7065 if (Ty->isVoidType())
7066 return ABIArgInfo::getIgnore();
7068 uint64_t Size = getContext().getTypeSize(Ty);
7070 // Anything too big to fit in registers is passed with an explicit indirect
7071 // pointer / sret pointer.
7072 if (Size > SizeLimit)
7073 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
7075 // Treat an enum type as its underlying type.
7076 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
7077 Ty = EnumTy->getDecl()->getIntegerType();
7079 // Integer types smaller than a register are extended.
7080 if (Size < 64 && Ty->isIntegerType())
7081 return ABIArgInfo::getExtend();
7083 // Other non-aggregates go in registers.
7084 if (!isAggregateTypeForABI(Ty))
7085 return ABIArgInfo::getDirect();
7087 // If a C++ object has either a non-trivial copy constructor or a non-trivial
7088 // destructor, it is passed with an explicit indirect pointer / sret pointer.
7089 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
7090 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
7092 // This is a small aggregate type that should be passed in registers.
7093 // Build a coercion type from the LLVM struct type.
7094 llvm::StructType *StrTy = dyn_cast<llvm::StructType>(CGT.ConvertType(Ty));
7096 return ABIArgInfo::getDirect();
7098 CoerceBuilder CB(getVMContext(), getDataLayout());
7099 CB.addStruct(0, StrTy);
7100 CB.pad(llvm::alignTo(CB.DL.getTypeSizeInBits(StrTy), 64));
7102 // Try to use the original type for coercion.
7103 llvm::Type *CoerceTy = CB.isUsableType(StrTy) ? StrTy : CB.getType();
7106 return ABIArgInfo::getDirectInReg(CoerceTy);
7108 return ABIArgInfo::getDirect(CoerceTy);
7111 Address SparcV9ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7112 QualType Ty) const {
7113 ABIArgInfo AI = classifyType(Ty, 16 * 8);
7114 llvm::Type *ArgTy = CGT.ConvertType(Ty);
7115 if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
7116 AI.setCoerceToType(ArgTy);
7118 CharUnits SlotSize = CharUnits::fromQuantity(8);
7120 CGBuilderTy &Builder = CGF.Builder;
7121 Address Addr(Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize);
7122 llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
7124 auto TypeInfo = getContext().getTypeInfoInChars(Ty);
7126 Address ArgAddr = Address::invalid();
7128 switch (AI.getKind()) {
7129 case ABIArgInfo::Expand:
7130 case ABIArgInfo::CoerceAndExpand:
7131 case ABIArgInfo::InAlloca:
7132 llvm_unreachable("Unsupported ABI kind for va_arg");
7134 case ABIArgInfo::Extend: {
7136 CharUnits Offset = SlotSize - TypeInfo.first;
7137 ArgAddr = Builder.CreateConstInBoundsByteGEP(Addr, Offset, "extend");
7141 case ABIArgInfo::Direct: {
7142 auto AllocSize = getDataLayout().getTypeAllocSize(AI.getCoerceToType());
7143 Stride = CharUnits::fromQuantity(AllocSize).alignTo(SlotSize);
7148 case ABIArgInfo::Indirect:
7150 ArgAddr = Builder.CreateElementBitCast(Addr, ArgPtrTy, "indirect");
7151 ArgAddr = Address(Builder.CreateLoad(ArgAddr, "indirect.arg"),
7155 case ABIArgInfo::Ignore:
7156 return Address(llvm::UndefValue::get(ArgPtrTy), TypeInfo.second);
7160 llvm::Value *NextPtr =
7161 Builder.CreateConstInBoundsByteGEP(Addr.getPointer(), Stride, "ap.next");
7162 Builder.CreateStore(NextPtr, VAListAddr);
7164 return Builder.CreateBitCast(ArgAddr, ArgPtrTy, "arg.addr");
7167 void SparcV9ABIInfo::computeInfo(CGFunctionInfo &FI) const {
7168 FI.getReturnInfo() = classifyType(FI.getReturnType(), 32 * 8);
7169 for (auto &I : FI.arguments())
7170 I.info = classifyType(I.type, 16 * 8);
7174 class SparcV9TargetCodeGenInfo : public TargetCodeGenInfo {
7176 SparcV9TargetCodeGenInfo(CodeGenTypes &CGT)
7177 : TargetCodeGenInfo(new SparcV9ABIInfo(CGT)) {}
7179 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
7183 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
7184 llvm::Value *Address) const override;
7186 } // end anonymous namespace
7189 SparcV9TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
7190 llvm::Value *Address) const {
7191 // This is calculated from the LLVM and GCC tables and verified
7192 // against gcc output. AFAIK all ABIs use the same encoding.
7194 CodeGen::CGBuilderTy &Builder = CGF.Builder;
7196 llvm::IntegerType *i8 = CGF.Int8Ty;
7197 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
7198 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
7200 // 0-31: the 8-byte general-purpose registers
7201 AssignToArrayRange(Builder, Address, Eight8, 0, 31);
7203 // 32-63: f0-31, the 4-byte floating-point registers
7204 AssignToArrayRange(Builder, Address, Four8, 32, 63);
7214 AssignToArrayRange(Builder, Address, Eight8, 64, 71);
7216 // 72-87: d0-15, the 8-byte floating-point registers
7217 AssignToArrayRange(Builder, Address, Eight8, 72, 87);
7223 //===----------------------------------------------------------------------===//
7224 // XCore ABI Implementation
7225 //===----------------------------------------------------------------------===//
7229 /// A SmallStringEnc instance is used to build up the TypeString by passing
7230 /// it by reference between functions that append to it.
7231 typedef llvm::SmallString<128> SmallStringEnc;
7233 /// TypeStringCache caches the meta encodings of Types.
7235 /// The reason for caching TypeStrings is two fold:
7236 /// 1. To cache a type's encoding for later uses;
7237 /// 2. As a means to break recursive member type inclusion.
7239 /// A cache Entry can have a Status of:
7240 /// NonRecursive: The type encoding is not recursive;
7241 /// Recursive: The type encoding is recursive;
7242 /// Incomplete: An incomplete TypeString;
7243 /// IncompleteUsed: An incomplete TypeString that has been used in a
7244 /// Recursive type encoding.
7246 /// A NonRecursive entry will have all of its sub-members expanded as fully
7247 /// as possible. Whilst it may contain types which are recursive, the type
7248 /// itself is not recursive and thus its encoding may be safely used whenever
7249 /// the type is encountered.
7251 /// A Recursive entry will have all of its sub-members expanded as fully as
7252 /// possible. The type itself is recursive and it may contain other types which
7253 /// are recursive. The Recursive encoding must not be used during the expansion
7254 /// of a recursive type's recursive branch. For simplicity the code uses
7255 /// IncompleteCount to reject all usage of Recursive encodings for member types.
7257 /// An Incomplete entry is always a RecordType and only encodes its
7258 /// identifier e.g. "s(S){}". Incomplete 'StubEnc' entries are ephemeral and
7259 /// are placed into the cache during type expansion as a means to identify and
7260 /// handle recursive inclusion of types as sub-members. If there is recursion
7261 /// the entry becomes IncompleteUsed.
7263 /// During the expansion of a RecordType's members:
7265 /// If the cache contains a NonRecursive encoding for the member type, the
7266 /// cached encoding is used;
7268 /// If the cache contains a Recursive encoding for the member type, the
7269 /// cached encoding is 'Swapped' out, as it may be incorrect, and...
7271 /// If the member is a RecordType, an Incomplete encoding is placed into the
7272 /// cache to break potential recursive inclusion of itself as a sub-member;
7274 /// Once a member RecordType has been expanded, its temporary incomplete
7275 /// entry is removed from the cache. If a Recursive encoding was swapped out
7276 /// it is swapped back in;
7278 /// If an incomplete entry is used to expand a sub-member, the incomplete
7279 /// entry is marked as IncompleteUsed. The cache keeps count of how many
7280 /// IncompleteUsed entries it currently contains in IncompleteUsedCount;
7282 /// If a member's encoding is found to be a NonRecursive or Recursive viz:
7283 /// IncompleteUsedCount==0, the member's encoding is added to the cache.
7284 /// Else the member is part of a recursive type and thus the recursion has
7285 /// been exited too soon for the encoding to be correct for the member.
7287 class TypeStringCache {
7288 enum Status {NonRecursive, Recursive, Incomplete, IncompleteUsed};
7290 std::string Str; // The encoded TypeString for the type.
7291 enum Status State; // Information about the encoding in 'Str'.
7292 std::string Swapped; // A temporary place holder for a Recursive encoding
7293 // during the expansion of RecordType's members.
7295 std::map<const IdentifierInfo *, struct Entry> Map;
7296 unsigned IncompleteCount; // Number of Incomplete entries in the Map.
7297 unsigned IncompleteUsedCount; // Number of IncompleteUsed entries in the Map.
7299 TypeStringCache() : IncompleteCount(0), IncompleteUsedCount(0) {}
7300 void addIncomplete(const IdentifierInfo *ID, std::string StubEnc);
7301 bool removeIncomplete(const IdentifierInfo *ID);
7302 void addIfComplete(const IdentifierInfo *ID, StringRef Str,
7304 StringRef lookupStr(const IdentifierInfo *ID);
7307 /// TypeString encodings for enum & union fields must be order.
7308 /// FieldEncoding is a helper for this ordering process.
7309 class FieldEncoding {
7313 FieldEncoding(bool b, SmallStringEnc &e) : HasName(b), Enc(e.c_str()) {}
7314 StringRef str() {return Enc.c_str();}
7315 bool operator<(const FieldEncoding &rhs) const {
7316 if (HasName != rhs.HasName) return HasName;
7317 return Enc < rhs.Enc;
7321 class XCoreABIInfo : public DefaultABIInfo {
7323 XCoreABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
7324 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7325 QualType Ty) const override;
7328 class XCoreTargetCodeGenInfo : public TargetCodeGenInfo {
7329 mutable TypeStringCache TSC;
7331 XCoreTargetCodeGenInfo(CodeGenTypes &CGT)
7332 :TargetCodeGenInfo(new XCoreABIInfo(CGT)) {}
7333 void emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
7334 CodeGen::CodeGenModule &M) const override;
7337 } // End anonymous namespace.
7339 // TODO: this implementation is likely now redundant with the default
7341 Address XCoreABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7342 QualType Ty) const {
7343 CGBuilderTy &Builder = CGF.Builder;
7346 CharUnits SlotSize = CharUnits::fromQuantity(4);
7347 Address AP(Builder.CreateLoad(VAListAddr), SlotSize);
7349 // Handle the argument.
7350 ABIArgInfo AI = classifyArgumentType(Ty);
7351 CharUnits TypeAlign = getContext().getTypeAlignInChars(Ty);
7352 llvm::Type *ArgTy = CGT.ConvertType(Ty);
7353 if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
7354 AI.setCoerceToType(ArgTy);
7355 llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
7357 Address Val = Address::invalid();
7358 CharUnits ArgSize = CharUnits::Zero();
7359 switch (AI.getKind()) {
7360 case ABIArgInfo::Expand:
7361 case ABIArgInfo::CoerceAndExpand:
7362 case ABIArgInfo::InAlloca:
7363 llvm_unreachable("Unsupported ABI kind for va_arg");
7364 case ABIArgInfo::Ignore:
7365 Val = Address(llvm::UndefValue::get(ArgPtrTy), TypeAlign);
7366 ArgSize = CharUnits::Zero();
7368 case ABIArgInfo::Extend:
7369 case ABIArgInfo::Direct:
7370 Val = Builder.CreateBitCast(AP, ArgPtrTy);
7371 ArgSize = CharUnits::fromQuantity(
7372 getDataLayout().getTypeAllocSize(AI.getCoerceToType()));
7373 ArgSize = ArgSize.alignTo(SlotSize);
7375 case ABIArgInfo::Indirect:
7376 Val = Builder.CreateElementBitCast(AP, ArgPtrTy);
7377 Val = Address(Builder.CreateLoad(Val), TypeAlign);
7382 // Increment the VAList.
7383 if (!ArgSize.isZero()) {
7385 Builder.CreateConstInBoundsByteGEP(AP.getPointer(), ArgSize);
7386 Builder.CreateStore(APN, VAListAddr);
7392 /// During the expansion of a RecordType, an incomplete TypeString is placed
7393 /// into the cache as a means to identify and break recursion.
7394 /// If there is a Recursive encoding in the cache, it is swapped out and will
7395 /// be reinserted by removeIncomplete().
7396 /// All other types of encoding should have been used rather than arriving here.
7397 void TypeStringCache::addIncomplete(const IdentifierInfo *ID,
7398 std::string StubEnc) {
7402 assert( (E.Str.empty() || E.State == Recursive) &&
7403 "Incorrectly use of addIncomplete");
7404 assert(!StubEnc.empty() && "Passing an empty string to addIncomplete()");
7405 E.Swapped.swap(E.Str); // swap out the Recursive
7406 E.Str.swap(StubEnc);
7407 E.State = Incomplete;
7411 /// Once the RecordType has been expanded, the temporary incomplete TypeString
7412 /// must be removed from the cache.
7413 /// If a Recursive was swapped out by addIncomplete(), it will be replaced.
7414 /// Returns true if the RecordType was defined recursively.
7415 bool TypeStringCache::removeIncomplete(const IdentifierInfo *ID) {
7418 auto I = Map.find(ID);
7419 assert(I != Map.end() && "Entry not present");
7420 Entry &E = I->second;
7421 assert( (E.State == Incomplete ||
7422 E.State == IncompleteUsed) &&
7423 "Entry must be an incomplete type");
7424 bool IsRecursive = false;
7425 if (E.State == IncompleteUsed) {
7426 // We made use of our Incomplete encoding, thus we are recursive.
7428 --IncompleteUsedCount;
7430 if (E.Swapped.empty())
7433 // Swap the Recursive back.
7434 E.Swapped.swap(E.Str);
7436 E.State = Recursive;
7442 /// Add the encoded TypeString to the cache only if it is NonRecursive or
7443 /// Recursive (viz: all sub-members were expanded as fully as possible).
7444 void TypeStringCache::addIfComplete(const IdentifierInfo *ID, StringRef Str,
7446 if (!ID || IncompleteUsedCount)
7447 return; // No key or it is is an incomplete sub-type so don't add.
7449 if (IsRecursive && !E.Str.empty()) {
7450 assert(E.State==Recursive && E.Str.size() == Str.size() &&
7451 "This is not the same Recursive entry");
7452 // The parent container was not recursive after all, so we could have used
7453 // this Recursive sub-member entry after all, but we assumed the worse when
7454 // we started viz: IncompleteCount!=0.
7457 assert(E.Str.empty() && "Entry already present");
7459 E.State = IsRecursive? Recursive : NonRecursive;
7462 /// Return a cached TypeString encoding for the ID. If there isn't one, or we
7463 /// are recursively expanding a type (IncompleteCount != 0) and the cached
7464 /// encoding is Recursive, return an empty StringRef.
7465 StringRef TypeStringCache::lookupStr(const IdentifierInfo *ID) {
7467 return StringRef(); // We have no key.
7468 auto I = Map.find(ID);
7470 return StringRef(); // We have no encoding.
7471 Entry &E = I->second;
7472 if (E.State == Recursive && IncompleteCount)
7473 return StringRef(); // We don't use Recursive encodings for member types.
7475 if (E.State == Incomplete) {
7476 // The incomplete type is being used to break out of recursion.
7477 E.State = IncompleteUsed;
7478 ++IncompleteUsedCount;
7480 return E.Str.c_str();
7483 /// The XCore ABI includes a type information section that communicates symbol
7484 /// type information to the linker. The linker uses this information to verify
7485 /// safety/correctness of things such as array bound and pointers et al.
7486 /// The ABI only requires C (and XC) language modules to emit TypeStrings.
7487 /// This type information (TypeString) is emitted into meta data for all global
7488 /// symbols: definitions, declarations, functions & variables.
7490 /// The TypeString carries type, qualifier, name, size & value details.
7491 /// Please see 'Tools Development Guide' section 2.16.2 for format details:
7492 /// https://www.xmos.com/download/public/Tools-Development-Guide%28X9114A%29.pdf
7493 /// The output is tested by test/CodeGen/xcore-stringtype.c.
7495 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
7496 CodeGen::CodeGenModule &CGM, TypeStringCache &TSC);
7498 /// XCore uses emitTargetMD to emit TypeString metadata for global symbols.
7499 void XCoreTargetCodeGenInfo::emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
7500 CodeGen::CodeGenModule &CGM) const {
7502 if (getTypeString(Enc, D, CGM, TSC)) {
7503 llvm::LLVMContext &Ctx = CGM.getModule().getContext();
7504 llvm::Metadata *MDVals[] = {llvm::ConstantAsMetadata::get(GV),
7505 llvm::MDString::get(Ctx, Enc.str())};
7506 llvm::NamedMDNode *MD =
7507 CGM.getModule().getOrInsertNamedMetadata("xcore.typestrings");
7508 MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
7512 //===----------------------------------------------------------------------===//
7513 // SPIR ABI Implementation
7514 //===----------------------------------------------------------------------===//
7517 class SPIRTargetCodeGenInfo : public TargetCodeGenInfo {
7519 SPIRTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
7520 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
7521 void emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
7522 CodeGen::CodeGenModule &M) const override;
7523 unsigned getOpenCLKernelCallingConv() const override;
7525 } // End anonymous namespace.
7527 /// Emit SPIR specific metadata: OpenCL and SPIR version.
7528 void SPIRTargetCodeGenInfo::emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
7529 CodeGen::CodeGenModule &CGM) const {
7530 llvm::LLVMContext &Ctx = CGM.getModule().getContext();
7531 llvm::Type *Int32Ty = llvm::Type::getInt32Ty(Ctx);
7532 llvm::Module &M = CGM.getModule();
7533 // SPIR v2.0 s2.12 - The SPIR version used by the module is stored in the
7534 // opencl.spir.version named metadata.
7535 llvm::Metadata *SPIRVerElts[] = {
7536 llvm::ConstantAsMetadata::get(llvm::ConstantInt::get(Int32Ty, 2)),
7537 llvm::ConstantAsMetadata::get(llvm::ConstantInt::get(Int32Ty, 0))};
7538 llvm::NamedMDNode *SPIRVerMD =
7539 M.getOrInsertNamedMetadata("opencl.spir.version");
7540 SPIRVerMD->addOperand(llvm::MDNode::get(Ctx, SPIRVerElts));
7541 // SPIR v2.0 s2.13 - The OpenCL version used by the module is stored in the
7542 // opencl.ocl.version named metadata node.
7543 llvm::Metadata *OCLVerElts[] = {
7544 llvm::ConstantAsMetadata::get(llvm::ConstantInt::get(
7545 Int32Ty, CGM.getLangOpts().OpenCLVersion / 100)),
7546 llvm::ConstantAsMetadata::get(llvm::ConstantInt::get(
7547 Int32Ty, (CGM.getLangOpts().OpenCLVersion % 100) / 10))};
7548 llvm::NamedMDNode *OCLVerMD =
7549 M.getOrInsertNamedMetadata("opencl.ocl.version");
7550 OCLVerMD->addOperand(llvm::MDNode::get(Ctx, OCLVerElts));
7553 unsigned SPIRTargetCodeGenInfo::getOpenCLKernelCallingConv() const {
7554 return llvm::CallingConv::SPIR_KERNEL;
7557 static bool appendType(SmallStringEnc &Enc, QualType QType,
7558 const CodeGen::CodeGenModule &CGM,
7559 TypeStringCache &TSC);
7561 /// Helper function for appendRecordType().
7562 /// Builds a SmallVector containing the encoded field types in declaration
7564 static bool extractFieldType(SmallVectorImpl<FieldEncoding> &FE,
7565 const RecordDecl *RD,
7566 const CodeGen::CodeGenModule &CGM,
7567 TypeStringCache &TSC) {
7568 for (const auto *Field : RD->fields()) {
7571 Enc += Field->getName();
7573 if (Field->isBitField()) {
7575 llvm::raw_svector_ostream OS(Enc);
7576 OS << Field->getBitWidthValue(CGM.getContext());
7579 if (!appendType(Enc, Field->getType(), CGM, TSC))
7581 if (Field->isBitField())
7584 FE.emplace_back(!Field->getName().empty(), Enc);
7589 /// Appends structure and union types to Enc and adds encoding to cache.
7590 /// Recursively calls appendType (via extractFieldType) for each field.
7591 /// Union types have their fields ordered according to the ABI.
7592 static bool appendRecordType(SmallStringEnc &Enc, const RecordType *RT,
7593 const CodeGen::CodeGenModule &CGM,
7594 TypeStringCache &TSC, const IdentifierInfo *ID) {
7595 // Append the cached TypeString if we have one.
7596 StringRef TypeString = TSC.lookupStr(ID);
7597 if (!TypeString.empty()) {
7602 // Start to emit an incomplete TypeString.
7603 size_t Start = Enc.size();
7604 Enc += (RT->isUnionType()? 'u' : 's');
7607 Enc += ID->getName();
7610 // We collect all encoded fields and order as necessary.
7611 bool IsRecursive = false;
7612 const RecordDecl *RD = RT->getDecl()->getDefinition();
7613 if (RD && !RD->field_empty()) {
7614 // An incomplete TypeString stub is placed in the cache for this RecordType
7615 // so that recursive calls to this RecordType will use it whilst building a
7616 // complete TypeString for this RecordType.
7617 SmallVector<FieldEncoding, 16> FE;
7618 std::string StubEnc(Enc.substr(Start).str());
7619 StubEnc += '}'; // StubEnc now holds a valid incomplete TypeString.
7620 TSC.addIncomplete(ID, std::move(StubEnc));
7621 if (!extractFieldType(FE, RD, CGM, TSC)) {
7622 (void) TSC.removeIncomplete(ID);
7625 IsRecursive = TSC.removeIncomplete(ID);
7626 // The ABI requires unions to be sorted but not structures.
7627 // See FieldEncoding::operator< for sort algorithm.
7628 if (RT->isUnionType())
7629 std::sort(FE.begin(), FE.end());
7630 // We can now complete the TypeString.
7631 unsigned E = FE.size();
7632 for (unsigned I = 0; I != E; ++I) {
7639 TSC.addIfComplete(ID, Enc.substr(Start), IsRecursive);
7643 /// Appends enum types to Enc and adds the encoding to the cache.
7644 static bool appendEnumType(SmallStringEnc &Enc, const EnumType *ET,
7645 TypeStringCache &TSC,
7646 const IdentifierInfo *ID) {
7647 // Append the cached TypeString if we have one.
7648 StringRef TypeString = TSC.lookupStr(ID);
7649 if (!TypeString.empty()) {
7654 size_t Start = Enc.size();
7657 Enc += ID->getName();
7660 // We collect all encoded enumerations and order them alphanumerically.
7661 if (const EnumDecl *ED = ET->getDecl()->getDefinition()) {
7662 SmallVector<FieldEncoding, 16> FE;
7663 for (auto I = ED->enumerator_begin(), E = ED->enumerator_end(); I != E;
7665 SmallStringEnc EnumEnc;
7667 EnumEnc += I->getName();
7669 I->getInitVal().toString(EnumEnc);
7671 FE.push_back(FieldEncoding(!I->getName().empty(), EnumEnc));
7673 std::sort(FE.begin(), FE.end());
7674 unsigned E = FE.size();
7675 for (unsigned I = 0; I != E; ++I) {
7682 TSC.addIfComplete(ID, Enc.substr(Start), false);
7686 /// Appends type's qualifier to Enc.
7687 /// This is done prior to appending the type's encoding.
7688 static void appendQualifier(SmallStringEnc &Enc, QualType QT) {
7689 // Qualifiers are emitted in alphabetical order.
7690 static const char *const Table[]={"","c:","r:","cr:","v:","cv:","rv:","crv:"};
7692 if (QT.isConstQualified())
7694 if (QT.isRestrictQualified())
7696 if (QT.isVolatileQualified())
7698 Enc += Table[Lookup];
7701 /// Appends built-in types to Enc.
7702 static bool appendBuiltinType(SmallStringEnc &Enc, const BuiltinType *BT) {
7703 const char *EncType;
7704 switch (BT->getKind()) {
7705 case BuiltinType::Void:
7708 case BuiltinType::Bool:
7711 case BuiltinType::Char_U:
7714 case BuiltinType::UChar:
7717 case BuiltinType::SChar:
7720 case BuiltinType::UShort:
7723 case BuiltinType::Short:
7726 case BuiltinType::UInt:
7729 case BuiltinType::Int:
7732 case BuiltinType::ULong:
7735 case BuiltinType::Long:
7738 case BuiltinType::ULongLong:
7741 case BuiltinType::LongLong:
7744 case BuiltinType::Float:
7747 case BuiltinType::Double:
7750 case BuiltinType::LongDouble:
7760 /// Appends a pointer encoding to Enc before calling appendType for the pointee.
7761 static bool appendPointerType(SmallStringEnc &Enc, const PointerType *PT,
7762 const CodeGen::CodeGenModule &CGM,
7763 TypeStringCache &TSC) {
7765 if (!appendType(Enc, PT->getPointeeType(), CGM, TSC))
7771 /// Appends array encoding to Enc before calling appendType for the element.
7772 static bool appendArrayType(SmallStringEnc &Enc, QualType QT,
7773 const ArrayType *AT,
7774 const CodeGen::CodeGenModule &CGM,
7775 TypeStringCache &TSC, StringRef NoSizeEnc) {
7776 if (AT->getSizeModifier() != ArrayType::Normal)
7779 if (const ConstantArrayType *CAT = dyn_cast<ConstantArrayType>(AT))
7780 CAT->getSize().toStringUnsigned(Enc);
7782 Enc += NoSizeEnc; // Global arrays use "*", otherwise it is "".
7784 // The Qualifiers should be attached to the type rather than the array.
7785 appendQualifier(Enc, QT);
7786 if (!appendType(Enc, AT->getElementType(), CGM, TSC))
7792 /// Appends a function encoding to Enc, calling appendType for the return type
7793 /// and the arguments.
7794 static bool appendFunctionType(SmallStringEnc &Enc, const FunctionType *FT,
7795 const CodeGen::CodeGenModule &CGM,
7796 TypeStringCache &TSC) {
7798 if (!appendType(Enc, FT->getReturnType(), CGM, TSC))
7801 if (const FunctionProtoType *FPT = FT->getAs<FunctionProtoType>()) {
7802 // N.B. we are only interested in the adjusted param types.
7803 auto I = FPT->param_type_begin();
7804 auto E = FPT->param_type_end();
7807 if (!appendType(Enc, *I, CGM, TSC))
7813 if (FPT->isVariadic())
7816 if (FPT->isVariadic())
7826 /// Handles the type's qualifier before dispatching a call to handle specific
7828 static bool appendType(SmallStringEnc &Enc, QualType QType,
7829 const CodeGen::CodeGenModule &CGM,
7830 TypeStringCache &TSC) {
7832 QualType QT = QType.getCanonicalType();
7834 if (const ArrayType *AT = QT->getAsArrayTypeUnsafe())
7835 // The Qualifiers should be attached to the type rather than the array.
7836 // Thus we don't call appendQualifier() here.
7837 return appendArrayType(Enc, QT, AT, CGM, TSC, "");
7839 appendQualifier(Enc, QT);
7841 if (const BuiltinType *BT = QT->getAs<BuiltinType>())
7842 return appendBuiltinType(Enc, BT);
7844 if (const PointerType *PT = QT->getAs<PointerType>())
7845 return appendPointerType(Enc, PT, CGM, TSC);
7847 if (const EnumType *ET = QT->getAs<EnumType>())
7848 return appendEnumType(Enc, ET, TSC, QT.getBaseTypeIdentifier());
7850 if (const RecordType *RT = QT->getAsStructureType())
7851 return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
7853 if (const RecordType *RT = QT->getAsUnionType())
7854 return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
7856 if (const FunctionType *FT = QT->getAs<FunctionType>())
7857 return appendFunctionType(Enc, FT, CGM, TSC);
7862 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
7863 CodeGen::CodeGenModule &CGM, TypeStringCache &TSC) {
7867 if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) {
7868 if (FD->getLanguageLinkage() != CLanguageLinkage)
7870 return appendType(Enc, FD->getType(), CGM, TSC);
7873 if (const VarDecl *VD = dyn_cast<VarDecl>(D)) {
7874 if (VD->getLanguageLinkage() != CLanguageLinkage)
7876 QualType QT = VD->getType().getCanonicalType();
7877 if (const ArrayType *AT = QT->getAsArrayTypeUnsafe()) {
7878 // Global ArrayTypes are given a size of '*' if the size is unknown.
7879 // The Qualifiers should be attached to the type rather than the array.
7880 // Thus we don't call appendQualifier() here.
7881 return appendArrayType(Enc, QT, AT, CGM, TSC, "*");
7883 return appendType(Enc, QT, CGM, TSC);
7889 //===----------------------------------------------------------------------===//
7891 //===----------------------------------------------------------------------===//
7893 const llvm::Triple &CodeGenModule::getTriple() const {
7894 return getTarget().getTriple();
7897 bool CodeGenModule::supportsCOMDAT() const {
7898 return getTriple().supportsCOMDAT();
7901 const TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() {
7902 if (TheTargetCodeGenInfo)
7903 return *TheTargetCodeGenInfo;
7905 // Helper to set the unique_ptr while still keeping the return value.
7906 auto SetCGInfo = [&](TargetCodeGenInfo *P) -> const TargetCodeGenInfo & {
7907 this->TheTargetCodeGenInfo.reset(P);
7911 const llvm::Triple &Triple = getTarget().getTriple();
7912 switch (Triple.getArch()) {
7914 return SetCGInfo(new DefaultTargetCodeGenInfo(Types));
7916 case llvm::Triple::le32:
7917 return SetCGInfo(new PNaClTargetCodeGenInfo(Types));
7918 case llvm::Triple::mips:
7919 case llvm::Triple::mipsel:
7920 if (Triple.getOS() == llvm::Triple::NaCl)
7921 return SetCGInfo(new PNaClTargetCodeGenInfo(Types));
7922 return SetCGInfo(new MIPSTargetCodeGenInfo(Types, true));
7924 case llvm::Triple::mips64:
7925 case llvm::Triple::mips64el:
7926 return SetCGInfo(new MIPSTargetCodeGenInfo(Types, false));
7928 case llvm::Triple::aarch64:
7929 case llvm::Triple::aarch64_be: {
7930 AArch64ABIInfo::ABIKind Kind = AArch64ABIInfo::AAPCS;
7931 if (getTarget().getABI() == "darwinpcs")
7932 Kind = AArch64ABIInfo::DarwinPCS;
7934 return SetCGInfo(new AArch64TargetCodeGenInfo(Types, Kind));
7937 case llvm::Triple::wasm32:
7938 case llvm::Triple::wasm64:
7939 return SetCGInfo(new WebAssemblyTargetCodeGenInfo(Types));
7941 case llvm::Triple::arm:
7942 case llvm::Triple::armeb:
7943 case llvm::Triple::thumb:
7944 case llvm::Triple::thumbeb: {
7945 if (Triple.getOS() == llvm::Triple::Win32) {
7947 new WindowsARMTargetCodeGenInfo(Types, ARMABIInfo::AAPCS_VFP));
7950 ARMABIInfo::ABIKind Kind = ARMABIInfo::AAPCS;
7951 StringRef ABIStr = getTarget().getABI();
7952 if (ABIStr == "apcs-gnu")
7953 Kind = ARMABIInfo::APCS;
7954 else if (ABIStr == "aapcs16")
7955 Kind = ARMABIInfo::AAPCS16_VFP;
7956 else if (CodeGenOpts.FloatABI == "hard" ||
7957 (CodeGenOpts.FloatABI != "soft" &&
7958 (Triple.getEnvironment() == llvm::Triple::GNUEABIHF ||
7959 Triple.getEnvironment() == llvm::Triple::MuslEABIHF ||
7960 Triple.getEnvironment() == llvm::Triple::EABIHF)))
7961 Kind = ARMABIInfo::AAPCS_VFP;
7963 return SetCGInfo(new ARMTargetCodeGenInfo(Types, Kind));
7966 case llvm::Triple::ppc:
7968 new PPC32TargetCodeGenInfo(Types, CodeGenOpts.FloatABI == "soft"));
7969 case llvm::Triple::ppc64:
7970 if (Triple.isOSBinFormatELF()) {
7971 PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv1;
7972 if (getTarget().getABI() == "elfv2")
7973 Kind = PPC64_SVR4_ABIInfo::ELFv2;
7974 bool HasQPX = getTarget().getABI() == "elfv1-qpx";
7975 bool IsSoftFloat = CodeGenOpts.FloatABI == "soft";
7977 return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX,
7980 return SetCGInfo(new PPC64TargetCodeGenInfo(Types));
7981 case llvm::Triple::ppc64le: {
7982 assert(Triple.isOSBinFormatELF() && "PPC64 LE non-ELF not supported!");
7983 PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv2;
7984 if (getTarget().getABI() == "elfv1" || getTarget().getABI() == "elfv1-qpx")
7985 Kind = PPC64_SVR4_ABIInfo::ELFv1;
7986 bool HasQPX = getTarget().getABI() == "elfv1-qpx";
7987 bool IsSoftFloat = CodeGenOpts.FloatABI == "soft";
7989 return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX,
7993 case llvm::Triple::nvptx:
7994 case llvm::Triple::nvptx64:
7995 return SetCGInfo(new NVPTXTargetCodeGenInfo(Types));
7997 case llvm::Triple::msp430:
7998 return SetCGInfo(new MSP430TargetCodeGenInfo(Types));
8000 case llvm::Triple::systemz: {
8001 bool HasVector = getTarget().getABI() == "vector";
8002 return SetCGInfo(new SystemZTargetCodeGenInfo(Types, HasVector));
8005 case llvm::Triple::tce:
8006 return SetCGInfo(new TCETargetCodeGenInfo(Types));
8008 case llvm::Triple::x86: {
8009 bool IsDarwinVectorABI = Triple.isOSDarwin();
8010 bool RetSmallStructInRegABI =
8011 X86_32TargetCodeGenInfo::isStructReturnInRegABI(Triple, CodeGenOpts);
8012 bool IsWin32FloatStructABI = Triple.isOSWindows() && !Triple.isOSCygMing();
8014 if (Triple.getOS() == llvm::Triple::Win32) {
8015 return SetCGInfo(new WinX86_32TargetCodeGenInfo(
8016 Types, IsDarwinVectorABI, RetSmallStructInRegABI,
8017 IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters));
8019 return SetCGInfo(new X86_32TargetCodeGenInfo(
8020 Types, IsDarwinVectorABI, RetSmallStructInRegABI,
8021 IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters,
8022 CodeGenOpts.FloatABI == "soft"));
8026 case llvm::Triple::x86_64: {
8027 StringRef ABI = getTarget().getABI();
8028 X86AVXABILevel AVXLevel =
8030 ? X86AVXABILevel::AVX512
8031 : ABI == "avx" ? X86AVXABILevel::AVX : X86AVXABILevel::None);
8033 switch (Triple.getOS()) {
8034 case llvm::Triple::Win32:
8035 return SetCGInfo(new WinX86_64TargetCodeGenInfo(Types, AVXLevel));
8036 case llvm::Triple::PS4:
8037 return SetCGInfo(new PS4TargetCodeGenInfo(Types, AVXLevel));
8039 return SetCGInfo(new X86_64TargetCodeGenInfo(Types, AVXLevel));
8042 case llvm::Triple::hexagon:
8043 return SetCGInfo(new HexagonTargetCodeGenInfo(Types));
8044 case llvm::Triple::lanai:
8045 return SetCGInfo(new LanaiTargetCodeGenInfo(Types));
8046 case llvm::Triple::r600:
8047 return SetCGInfo(new AMDGPUTargetCodeGenInfo(Types));
8048 case llvm::Triple::amdgcn:
8049 return SetCGInfo(new AMDGPUTargetCodeGenInfo(Types));
8050 case llvm::Triple::sparc:
8051 return SetCGInfo(new SparcV8TargetCodeGenInfo(Types));
8052 case llvm::Triple::sparcv9:
8053 return SetCGInfo(new SparcV9TargetCodeGenInfo(Types));
8054 case llvm::Triple::xcore:
8055 return SetCGInfo(new XCoreTargetCodeGenInfo(Types));
8056 case llvm::Triple::spir:
8057 case llvm::Triple::spir64:
8058 return SetCGInfo(new SPIRTargetCodeGenInfo(Types));