1 //===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // These classes wrap the information about a call or function
11 // definition used to handle ABI compliancy.
13 //===----------------------------------------------------------------------===//
15 #include "TargetInfo.h"
20 #include "CodeGenFunction.h"
21 #include "clang/AST/RecordLayout.h"
22 #include "clang/CodeGen/CGFunctionInfo.h"
23 #include "clang/CodeGen/SwiftCallingConv.h"
24 #include "clang/Frontend/CodeGenOptions.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/ADT/Twine.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include <algorithm> // std::sort
34 using namespace clang;
35 using namespace CodeGen;
37 // Helper for coercing an aggregate argument or return value into an integer
38 // array of the same size (including padding) and alignment. This alternate
39 // coercion happens only for the RenderScript ABI and can be removed after
40 // runtimes that rely on it are no longer supported.
42 // RenderScript assumes that the size of the argument / return value in the IR
43 // is the same as the size of the corresponding qualified type. This helper
44 // coerces the aggregate type into an array of the same size (including
45 // padding). This coercion is used in lieu of expansion of struct members or
46 // other canonical coercions that return a coerced-type of larger size.
48 // Ty - The argument / return value type
49 // Context - The associated ASTContext
50 // LLVMContext - The associated LLVMContext
51 static ABIArgInfo coerceToIntArray(QualType Ty,
53 llvm::LLVMContext &LLVMContext) {
54 // Alignment and Size are measured in bits.
55 const uint64_t Size = Context.getTypeSize(Ty);
56 const uint64_t Alignment = Context.getTypeAlign(Ty);
57 llvm::Type *IntType = llvm::Type::getIntNTy(LLVMContext, Alignment);
58 const uint64_t NumElements = (Size + Alignment - 1) / Alignment;
59 return ABIArgInfo::getDirect(llvm::ArrayType::get(IntType, NumElements));
62 static void AssignToArrayRange(CodeGen::CGBuilderTy &Builder,
67 // Alternatively, we could emit this as a loop in the source.
68 for (unsigned I = FirstIndex; I <= LastIndex; ++I) {
70 Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I);
71 Builder.CreateAlignedStore(Value, Cell, CharUnits::One());
75 static bool isAggregateTypeForABI(QualType T) {
76 return !CodeGenFunction::hasScalarEvaluationKind(T) ||
77 T->isMemberFunctionPointerType();
81 ABIInfo::getNaturalAlignIndirect(QualType Ty, bool ByRef, bool Realign,
82 llvm::Type *Padding) const {
83 return ABIArgInfo::getIndirect(getContext().getTypeAlignInChars(Ty),
84 ByRef, Realign, Padding);
88 ABIInfo::getNaturalAlignIndirectInReg(QualType Ty, bool Realign) const {
89 return ABIArgInfo::getIndirectInReg(getContext().getTypeAlignInChars(Ty),
90 /*ByRef*/ false, Realign);
93 Address ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
95 return Address::invalid();
98 ABIInfo::~ABIInfo() {}
100 /// Does the given lowering require more than the given number of
101 /// registers when expanded?
103 /// This is intended to be the basis of a reasonable basic implementation
104 /// of should{Pass,Return}IndirectlyForSwift.
106 /// For most targets, a limit of four total registers is reasonable; this
107 /// limits the amount of code required in order to move around the value
108 /// in case it wasn't produced immediately prior to the call by the caller
109 /// (or wasn't produced in exactly the right registers) or isn't used
110 /// immediately within the callee. But some targets may need to further
111 /// limit the register count due to an inability to support that many
112 /// return registers.
113 static bool occupiesMoreThan(CodeGenTypes &cgt,
114 ArrayRef<llvm::Type*> scalarTypes,
115 unsigned maxAllRegisters) {
116 unsigned intCount = 0, fpCount = 0;
117 for (llvm::Type *type : scalarTypes) {
118 if (type->isPointerTy()) {
120 } else if (auto intTy = dyn_cast<llvm::IntegerType>(type)) {
121 auto ptrWidth = cgt.getTarget().getPointerWidth(0);
122 intCount += (intTy->getBitWidth() + ptrWidth - 1) / ptrWidth;
124 assert(type->isVectorTy() || type->isFloatingPointTy());
129 return (intCount + fpCount > maxAllRegisters);
132 bool SwiftABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize,
134 unsigned numElts) const {
135 // The default implementation of this assumes that the target guarantees
136 // 128-bit SIMD support but nothing more.
137 return (vectorSize.getQuantity() > 8 && vectorSize.getQuantity() <= 16);
140 static CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT,
142 const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl());
144 return CGCXXABI::RAA_Default;
145 return CXXABI.getRecordArgABI(RD);
148 static CGCXXABI::RecordArgABI getRecordArgABI(QualType T,
150 const RecordType *RT = T->getAs<RecordType>();
152 return CGCXXABI::RAA_Default;
153 return getRecordArgABI(RT, CXXABI);
156 /// Pass transparent unions as if they were the type of the first element. Sema
157 /// should ensure that all elements of the union have the same "machine type".
158 static QualType useFirstFieldIfTransparentUnion(QualType Ty) {
159 if (const RecordType *UT = Ty->getAsUnionType()) {
160 const RecordDecl *UD = UT->getDecl();
161 if (UD->hasAttr<TransparentUnionAttr>()) {
162 assert(!UD->field_empty() && "sema created an empty transparent union");
163 return UD->field_begin()->getType();
169 CGCXXABI &ABIInfo::getCXXABI() const {
170 return CGT.getCXXABI();
173 ASTContext &ABIInfo::getContext() const {
174 return CGT.getContext();
177 llvm::LLVMContext &ABIInfo::getVMContext() const {
178 return CGT.getLLVMContext();
181 const llvm::DataLayout &ABIInfo::getDataLayout() const {
182 return CGT.getDataLayout();
185 const TargetInfo &ABIInfo::getTarget() const {
186 return CGT.getTarget();
189 const CodeGenOptions &ABIInfo::getCodeGenOpts() const {
190 return CGT.getCodeGenOpts();
193 bool ABIInfo::isAndroid() const { return getTarget().getTriple().isAndroid(); }
195 bool ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
199 bool ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
200 uint64_t Members) const {
204 bool ABIInfo::shouldSignExtUnsignedType(QualType Ty) const {
208 LLVM_DUMP_METHOD void ABIArgInfo::dump() const {
209 raw_ostream &OS = llvm::errs();
210 OS << "(ABIArgInfo Kind=";
213 OS << "Direct Type=";
214 if (llvm::Type *Ty = getCoerceToType())
226 OS << "InAlloca Offset=" << getInAllocaFieldIndex();
229 OS << "Indirect Align=" << getIndirectAlign().getQuantity()
230 << " ByVal=" << getIndirectByVal()
231 << " Realign=" << getIndirectRealign();
236 case CoerceAndExpand:
237 OS << "CoerceAndExpand Type=";
238 getCoerceAndExpandType()->print(OS);
244 // Dynamically round a pointer up to a multiple of the given alignment.
245 static llvm::Value *emitRoundPointerUpToAlignment(CodeGenFunction &CGF,
248 llvm::Value *PtrAsInt = Ptr;
249 // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align;
250 PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
251 PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
252 llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1));
253 PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
254 llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity()));
255 PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt,
257 Ptr->getName() + ".aligned");
261 /// Emit va_arg for a platform using the common void* representation,
262 /// where arguments are simply emitted in an array of slots on the stack.
264 /// This version implements the core direct-value passing rules.
266 /// \param SlotSize - The size and alignment of a stack slot.
267 /// Each argument will be allocated to a multiple of this number of
268 /// slots, and all the slots will be aligned to this value.
269 /// \param AllowHigherAlign - The slot alignment is not a cap;
270 /// an argument type with an alignment greater than the slot size
271 /// will be emitted on a higher-alignment address, potentially
272 /// leaving one or more empty slots behind as padding. If this
273 /// is false, the returned address might be less-aligned than
275 static Address emitVoidPtrDirectVAArg(CodeGenFunction &CGF,
277 llvm::Type *DirectTy,
278 CharUnits DirectSize,
279 CharUnits DirectAlign,
281 bool AllowHigherAlign) {
282 // Cast the element type to i8* if necessary. Some platforms define
283 // va_list as a struct containing an i8* instead of just an i8*.
284 if (VAListAddr.getElementType() != CGF.Int8PtrTy)
285 VAListAddr = CGF.Builder.CreateElementBitCast(VAListAddr, CGF.Int8PtrTy);
287 llvm::Value *Ptr = CGF.Builder.CreateLoad(VAListAddr, "argp.cur");
289 // If the CC aligns values higher than the slot size, do so if needed.
290 Address Addr = Address::invalid();
291 if (AllowHigherAlign && DirectAlign > SlotSize) {
292 Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign),
295 Addr = Address(Ptr, SlotSize);
298 // Advance the pointer past the argument, then store that back.
299 CharUnits FullDirectSize = DirectSize.alignTo(SlotSize);
300 llvm::Value *NextPtr =
301 CGF.Builder.CreateConstInBoundsByteGEP(Addr.getPointer(), FullDirectSize,
303 CGF.Builder.CreateStore(NextPtr, VAListAddr);
305 // If the argument is smaller than a slot, and this is a big-endian
306 // target, the argument will be right-adjusted in its slot.
307 if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() &&
308 !DirectTy->isStructTy()) {
309 Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize);
312 Addr = CGF.Builder.CreateElementBitCast(Addr, DirectTy);
316 /// Emit va_arg for a platform using the common void* representation,
317 /// where arguments are simply emitted in an array of slots on the stack.
319 /// \param IsIndirect - Values of this type are passed indirectly.
320 /// \param ValueInfo - The size and alignment of this type, generally
321 /// computed with getContext().getTypeInfoInChars(ValueTy).
322 /// \param SlotSizeAndAlign - The size and alignment of a stack slot.
323 /// Each argument will be allocated to a multiple of this number of
324 /// slots, and all the slots will be aligned to this value.
325 /// \param AllowHigherAlign - The slot alignment is not a cap;
326 /// an argument type with an alignment greater than the slot size
327 /// will be emitted on a higher-alignment address, potentially
328 /// leaving one or more empty slots behind as padding.
329 static Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr,
330 QualType ValueTy, bool IsIndirect,
331 std::pair<CharUnits, CharUnits> ValueInfo,
332 CharUnits SlotSizeAndAlign,
333 bool AllowHigherAlign) {
334 // The size and alignment of the value that was passed directly.
335 CharUnits DirectSize, DirectAlign;
337 DirectSize = CGF.getPointerSize();
338 DirectAlign = CGF.getPointerAlign();
340 DirectSize = ValueInfo.first;
341 DirectAlign = ValueInfo.second;
344 // Cast the address we've calculated to the right type.
345 llvm::Type *DirectTy = CGF.ConvertTypeForMem(ValueTy);
347 DirectTy = DirectTy->getPointerTo(0);
349 Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy,
350 DirectSize, DirectAlign,
355 Addr = Address(CGF.Builder.CreateLoad(Addr), ValueInfo.second);
362 static Address emitMergePHI(CodeGenFunction &CGF,
363 Address Addr1, llvm::BasicBlock *Block1,
364 Address Addr2, llvm::BasicBlock *Block2,
365 const llvm::Twine &Name = "") {
366 assert(Addr1.getType() == Addr2.getType());
367 llvm::PHINode *PHI = CGF.Builder.CreatePHI(Addr1.getType(), 2, Name);
368 PHI->addIncoming(Addr1.getPointer(), Block1);
369 PHI->addIncoming(Addr2.getPointer(), Block2);
370 CharUnits Align = std::min(Addr1.getAlignment(), Addr2.getAlignment());
371 return Address(PHI, Align);
374 TargetCodeGenInfo::~TargetCodeGenInfo() { delete Info; }
376 // If someone can figure out a general rule for this, that would be great.
377 // It's probably just doomed to be platform-dependent, though.
378 unsigned TargetCodeGenInfo::getSizeOfUnwindException() const {
380 // x86-64 FreeBSD, Linux, Darwin
381 // x86-32 FreeBSD, Linux, Darwin
382 // PowerPC Linux, Darwin
383 // ARM Darwin (*not* EABI)
388 bool TargetCodeGenInfo::isNoProtoCallVariadic(const CallArgList &args,
389 const FunctionNoProtoType *fnType) const {
390 // The following conventions are known to require this to be false:
393 // For everything else, we just prefer false unless we opt out.
398 TargetCodeGenInfo::getDependentLibraryOption(llvm::StringRef Lib,
399 llvm::SmallString<24> &Opt) const {
400 // This assumes the user is passing a library name like "rt" instead of a
401 // filename like "librt.a/so", and that they don't care whether it's static or
407 unsigned TargetCodeGenInfo::getOpenCLKernelCallingConv() const {
408 // OpenCL kernels are called via an explicit runtime API with arguments
409 // set with clSetKernelArg(), not as normal sub-functions.
410 // Return SPIR_KERNEL by default as the kernel calling convention to
411 // ensure the fingerprint is fixed such way that each OpenCL argument
412 // gets one matching argument in the produced kernel function argument
413 // list to enable feasible implementation of clSetKernelArg() with
414 // aggregates etc. In case we would use the default C calling conv here,
415 // clSetKernelArg() might break depending on the target-specific
416 // conventions; different targets might split structs passed as values
417 // to multiple function arguments etc.
418 return llvm::CallingConv::SPIR_KERNEL;
421 llvm::Constant *TargetCodeGenInfo::getNullPointer(const CodeGen::CodeGenModule &CGM,
422 llvm::PointerType *T, QualType QT) const {
423 return llvm::ConstantPointerNull::get(T);
426 LangAS TargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
427 const VarDecl *D) const {
428 assert(!CGM.getLangOpts().OpenCL &&
429 !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
430 "Address space agnostic languages only");
431 return D ? D->getType().getAddressSpace() : LangAS::Default;
434 llvm::Value *TargetCodeGenInfo::performAddrSpaceCast(
435 CodeGen::CodeGenFunction &CGF, llvm::Value *Src, LangAS SrcAddr,
436 LangAS DestAddr, llvm::Type *DestTy, bool isNonNull) const {
437 // Since target may map different address spaces in AST to the same address
438 // space, an address space conversion may end up as a bitcast.
439 if (auto *C = dyn_cast<llvm::Constant>(Src))
440 return performAddrSpaceCast(CGF.CGM, C, SrcAddr, DestAddr, DestTy);
441 return CGF.Builder.CreatePointerBitCastOrAddrSpaceCast(Src, DestTy);
445 TargetCodeGenInfo::performAddrSpaceCast(CodeGenModule &CGM, llvm::Constant *Src,
446 LangAS SrcAddr, LangAS DestAddr,
447 llvm::Type *DestTy) const {
448 // Since target may map different address spaces in AST to the same address
449 // space, an address space conversion may end up as a bitcast.
450 return llvm::ConstantExpr::getPointerCast(Src, DestTy);
454 TargetCodeGenInfo::getLLVMSyncScopeID(SyncScope S, llvm::LLVMContext &C) const {
455 return C.getOrInsertSyncScopeID(""); /* default sync scope */
458 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays);
460 /// isEmptyField - Return true iff a the field is "empty", that is it
461 /// is an unnamed bit-field or an (array of) empty record(s).
462 static bool isEmptyField(ASTContext &Context, const FieldDecl *FD,
464 if (FD->isUnnamedBitfield())
467 QualType FT = FD->getType();
469 // Constant arrays of empty records count as empty, strip them off.
470 // Constant arrays of zero length always count as empty.
472 while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
473 if (AT->getSize() == 0)
475 FT = AT->getElementType();
478 const RecordType *RT = FT->getAs<RecordType>();
482 // C++ record fields are never empty, at least in the Itanium ABI.
484 // FIXME: We should use a predicate for whether this behavior is true in the
486 if (isa<CXXRecordDecl>(RT->getDecl()))
489 return isEmptyRecord(Context, FT, AllowArrays);
492 /// isEmptyRecord - Return true iff a structure contains only empty
493 /// fields. Note that a structure with a flexible array member is not
494 /// considered empty.
495 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) {
496 const RecordType *RT = T->getAs<RecordType>();
499 const RecordDecl *RD = RT->getDecl();
500 if (RD->hasFlexibleArrayMember())
503 // If this is a C++ record, check the bases first.
504 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
505 for (const auto &I : CXXRD->bases())
506 if (!isEmptyRecord(Context, I.getType(), true))
509 for (const auto *I : RD->fields())
510 if (!isEmptyField(Context, I, AllowArrays))
515 /// isSingleElementStruct - Determine if a structure is a "single
516 /// element struct", i.e. it has exactly one non-empty field or
517 /// exactly one field which is itself a single element
518 /// struct. Structures with flexible array members are never
519 /// considered single element structs.
521 /// \return The field declaration for the single non-empty field, if
523 static const Type *isSingleElementStruct(QualType T, ASTContext &Context) {
524 const RecordType *RT = T->getAs<RecordType>();
528 const RecordDecl *RD = RT->getDecl();
529 if (RD->hasFlexibleArrayMember())
532 const Type *Found = nullptr;
534 // If this is a C++ record, check the bases first.
535 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
536 for (const auto &I : CXXRD->bases()) {
537 // Ignore empty records.
538 if (isEmptyRecord(Context, I.getType(), true))
541 // If we already found an element then this isn't a single-element struct.
545 // If this is non-empty and not a single element struct, the composite
546 // cannot be a single element struct.
547 Found = isSingleElementStruct(I.getType(), Context);
553 // Check for single element.
554 for (const auto *FD : RD->fields()) {
555 QualType FT = FD->getType();
557 // Ignore empty fields.
558 if (isEmptyField(Context, FD, true))
561 // If we already found an element then this isn't a single-element
566 // Treat single element arrays as the element.
567 while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
568 if (AT->getSize().getZExtValue() != 1)
570 FT = AT->getElementType();
573 if (!isAggregateTypeForABI(FT)) {
574 Found = FT.getTypePtr();
576 Found = isSingleElementStruct(FT, Context);
582 // We don't consider a struct a single-element struct if it has
583 // padding beyond the element type.
584 if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T))
591 Address EmitVAArgInstr(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
592 const ABIArgInfo &AI) {
593 // This default implementation defers to the llvm backend's va_arg
594 // instruction. It can handle only passing arguments directly
595 // (typically only handled in the backend for primitive types), or
596 // aggregates passed indirectly by pointer (NOTE: if the "byval"
597 // flag has ABI impact in the callee, this implementation cannot
600 // Only a few cases are covered here at the moment -- those needed
601 // by the default abi.
604 if (AI.isIndirect()) {
605 assert(!AI.getPaddingType() &&
606 "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
608 !AI.getIndirectRealign() &&
609 "Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!");
611 auto TyInfo = CGF.getContext().getTypeInfoInChars(Ty);
612 CharUnits TyAlignForABI = TyInfo.second;
615 llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty));
617 CGF.Builder.CreateVAArg(VAListAddr.getPointer(), BaseTy);
618 return Address(Addr, TyAlignForABI);
620 assert((AI.isDirect() || AI.isExtend()) &&
621 "Unexpected ArgInfo Kind in generic VAArg emitter!");
623 assert(!AI.getInReg() &&
624 "Unexpected InReg seen in arginfo in generic VAArg emitter!");
625 assert(!AI.getPaddingType() &&
626 "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
627 assert(!AI.getDirectOffset() &&
628 "Unexpected DirectOffset seen in arginfo in generic VAArg emitter!");
629 assert(!AI.getCoerceToType() &&
630 "Unexpected CoerceToType seen in arginfo in generic VAArg emitter!");
632 Address Temp = CGF.CreateMemTemp(Ty, "varet");
633 Val = CGF.Builder.CreateVAArg(VAListAddr.getPointer(), CGF.ConvertType(Ty));
634 CGF.Builder.CreateStore(Val, Temp);
639 /// DefaultABIInfo - The default implementation for ABI specific
640 /// details. This implementation provides information which results in
641 /// self-consistent and sensible LLVM IR generation, but does not
642 /// conform to any particular ABI.
643 class DefaultABIInfo : public ABIInfo {
645 DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
647 ABIArgInfo classifyReturnType(QualType RetTy) const;
648 ABIArgInfo classifyArgumentType(QualType RetTy) const;
650 void computeInfo(CGFunctionInfo &FI) const override {
651 if (!getCXXABI().classifyReturnType(FI))
652 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
653 for (auto &I : FI.arguments())
654 I.info = classifyArgumentType(I.type);
657 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
658 QualType Ty) const override {
659 return EmitVAArgInstr(CGF, VAListAddr, Ty, classifyArgumentType(Ty));
663 class DefaultTargetCodeGenInfo : public TargetCodeGenInfo {
665 DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
666 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
669 ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty) const {
670 Ty = useFirstFieldIfTransparentUnion(Ty);
672 if (isAggregateTypeForABI(Ty)) {
673 // Records with non-trivial destructors/copy-constructors should not be
675 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
676 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
678 return getNaturalAlignIndirect(Ty);
681 // Treat an enum type as its underlying type.
682 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
683 Ty = EnumTy->getDecl()->getIntegerType();
685 return (Ty->isPromotableIntegerType() ?
686 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
689 ABIArgInfo DefaultABIInfo::classifyReturnType(QualType RetTy) const {
690 if (RetTy->isVoidType())
691 return ABIArgInfo::getIgnore();
693 if (isAggregateTypeForABI(RetTy))
694 return getNaturalAlignIndirect(RetTy);
696 // Treat an enum type as its underlying type.
697 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
698 RetTy = EnumTy->getDecl()->getIntegerType();
700 return (RetTy->isPromotableIntegerType() ?
701 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
704 //===----------------------------------------------------------------------===//
705 // WebAssembly ABI Implementation
707 // This is a very simple ABI that relies a lot on DefaultABIInfo.
708 //===----------------------------------------------------------------------===//
710 class WebAssemblyABIInfo final : public DefaultABIInfo {
712 explicit WebAssemblyABIInfo(CodeGen::CodeGenTypes &CGT)
713 : DefaultABIInfo(CGT) {}
716 ABIArgInfo classifyReturnType(QualType RetTy) const;
717 ABIArgInfo classifyArgumentType(QualType Ty) const;
719 // DefaultABIInfo's classifyReturnType and classifyArgumentType are
720 // non-virtual, but computeInfo and EmitVAArg are virtual, so we
722 void computeInfo(CGFunctionInfo &FI) const override {
723 if (!getCXXABI().classifyReturnType(FI))
724 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
725 for (auto &Arg : FI.arguments())
726 Arg.info = classifyArgumentType(Arg.type);
729 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
730 QualType Ty) const override;
733 class WebAssemblyTargetCodeGenInfo final : public TargetCodeGenInfo {
735 explicit WebAssemblyTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
736 : TargetCodeGenInfo(new WebAssemblyABIInfo(CGT)) {}
739 /// \brief Classify argument of given type \p Ty.
740 ABIArgInfo WebAssemblyABIInfo::classifyArgumentType(QualType Ty) const {
741 Ty = useFirstFieldIfTransparentUnion(Ty);
743 if (isAggregateTypeForABI(Ty)) {
744 // Records with non-trivial destructors/copy-constructors should not be
746 if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
747 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
748 // Ignore empty structs/unions.
749 if (isEmptyRecord(getContext(), Ty, true))
750 return ABIArgInfo::getIgnore();
751 // Lower single-element structs to just pass a regular value. TODO: We
752 // could do reasonable-size multiple-element structs too, using getExpand(),
753 // though watch out for things like bitfields.
754 if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
755 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
758 // Otherwise just do the default thing.
759 return DefaultABIInfo::classifyArgumentType(Ty);
762 ABIArgInfo WebAssemblyABIInfo::classifyReturnType(QualType RetTy) const {
763 if (isAggregateTypeForABI(RetTy)) {
764 // Records with non-trivial destructors/copy-constructors should not be
765 // returned by value.
766 if (!getRecordArgABI(RetTy, getCXXABI())) {
767 // Ignore empty structs/unions.
768 if (isEmptyRecord(getContext(), RetTy, true))
769 return ABIArgInfo::getIgnore();
770 // Lower single-element structs to just return a regular value. TODO: We
771 // could do reasonable-size multiple-element structs too, using
772 // ABIArgInfo::getDirect().
773 if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
774 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
778 // Otherwise just do the default thing.
779 return DefaultABIInfo::classifyReturnType(RetTy);
782 Address WebAssemblyABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
784 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect=*/ false,
785 getContext().getTypeInfoInChars(Ty),
786 CharUnits::fromQuantity(4),
787 /*AllowHigherAlign=*/ true);
790 //===----------------------------------------------------------------------===//
791 // le32/PNaCl bitcode ABI Implementation
793 // This is a simplified version of the x86_32 ABI. Arguments and return values
794 // are always passed on the stack.
795 //===----------------------------------------------------------------------===//
797 class PNaClABIInfo : public ABIInfo {
799 PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
801 ABIArgInfo classifyReturnType(QualType RetTy) const;
802 ABIArgInfo classifyArgumentType(QualType RetTy) const;
804 void computeInfo(CGFunctionInfo &FI) const override;
805 Address EmitVAArg(CodeGenFunction &CGF,
806 Address VAListAddr, QualType Ty) const override;
809 class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
811 PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
812 : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {}
815 void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
816 if (!getCXXABI().classifyReturnType(FI))
817 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
819 for (auto &I : FI.arguments())
820 I.info = classifyArgumentType(I.type);
823 Address PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
825 // The PNaCL ABI is a bit odd, in that varargs don't use normal
826 // function classification. Structs get passed directly for varargs
827 // functions, through a rewriting transform in
828 // pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows
829 // this target to actually support a va_arg instructions with an
830 // aggregate type, unlike other targets.
831 return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
834 /// \brief Classify argument of given type \p Ty.
835 ABIArgInfo PNaClABIInfo::classifyArgumentType(QualType Ty) const {
836 if (isAggregateTypeForABI(Ty)) {
837 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
838 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
839 return getNaturalAlignIndirect(Ty);
840 } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
841 // Treat an enum type as its underlying type.
842 Ty = EnumTy->getDecl()->getIntegerType();
843 } else if (Ty->isFloatingType()) {
844 // Floating-point types don't go inreg.
845 return ABIArgInfo::getDirect();
848 return (Ty->isPromotableIntegerType() ?
849 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
852 ABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const {
853 if (RetTy->isVoidType())
854 return ABIArgInfo::getIgnore();
856 // In the PNaCl ABI we always return records/structures on the stack.
857 if (isAggregateTypeForABI(RetTy))
858 return getNaturalAlignIndirect(RetTy);
860 // Treat an enum type as its underlying type.
861 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
862 RetTy = EnumTy->getDecl()->getIntegerType();
864 return (RetTy->isPromotableIntegerType() ?
865 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
868 /// IsX86_MMXType - Return true if this is an MMX type.
869 bool IsX86_MMXType(llvm::Type *IRType) {
870 // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
871 return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
872 cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
873 IRType->getScalarSizeInBits() != 64;
876 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
877 StringRef Constraint,
879 bool IsMMXCons = llvm::StringSwitch<bool>(Constraint)
880 .Cases("y", "&y", "^Ym", true)
882 if (IsMMXCons && Ty->isVectorTy()) {
883 if (cast<llvm::VectorType>(Ty)->getBitWidth() != 64) {
884 // Invalid MMX constraint
888 return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
891 // No operation needed
895 /// Returns true if this type can be passed in SSE registers with the
896 /// X86_VectorCall calling convention. Shared between x86_32 and x86_64.
897 static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) {
898 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
899 if (BT->isFloatingPoint() && BT->getKind() != BuiltinType::Half) {
900 if (BT->getKind() == BuiltinType::LongDouble) {
901 if (&Context.getTargetInfo().getLongDoubleFormat() ==
902 &llvm::APFloat::x87DoubleExtended())
907 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
908 // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX
909 // registers specially.
910 unsigned VecSize = Context.getTypeSize(VT);
911 if (VecSize == 128 || VecSize == 256 || VecSize == 512)
917 /// Returns true if this aggregate is small enough to be passed in SSE registers
918 /// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64.
919 static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) {
920 return NumMembers <= 4;
923 /// Returns a Homogeneous Vector Aggregate ABIArgInfo, used in X86.
924 static ABIArgInfo getDirectX86Hva(llvm::Type* T = nullptr) {
925 auto AI = ABIArgInfo::getDirect(T);
927 AI.setCanBeFlattened(false);
931 //===----------------------------------------------------------------------===//
932 // X86-32 ABI Implementation
933 //===----------------------------------------------------------------------===//
935 /// \brief Similar to llvm::CCState, but for Clang.
937 CCState(unsigned CC) : CC(CC), FreeRegs(0), FreeSSERegs(0) {}
941 unsigned FreeSSERegs;
945 // Vectorcall only allows the first 6 parameters to be passed in registers.
946 VectorcallMaxParamNumAsReg = 6
949 /// X86_32ABIInfo - The X86-32 ABI information.
950 class X86_32ABIInfo : public SwiftABIInfo {
956 static const unsigned MinABIStackAlignInBytes = 4;
958 bool IsDarwinVectorABI;
959 bool IsRetSmallStructInRegABI;
960 bool IsWin32StructABI;
963 unsigned DefaultNumRegisterParameters;
965 static bool isRegisterSize(unsigned Size) {
966 return (Size == 8 || Size == 16 || Size == 32 || Size == 64);
969 bool isHomogeneousAggregateBaseType(QualType Ty) const override {
970 // FIXME: Assumes vectorcall is in use.
971 return isX86VectorTypeForVectorCall(getContext(), Ty);
974 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
975 uint64_t NumMembers) const override {
976 // FIXME: Assumes vectorcall is in use.
977 return isX86VectorCallAggregateSmallEnough(NumMembers);
980 bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const;
982 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
983 /// such that the argument will be passed in memory.
984 ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
986 ABIArgInfo getIndirectReturnResult(QualType Ty, CCState &State) const;
988 /// \brief Return the alignment to use for the given type on the stack.
989 unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const;
991 Class classify(QualType Ty) const;
992 ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
993 ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
995 /// \brief Updates the number of available free registers, returns
996 /// true if any registers were allocated.
997 bool updateFreeRegs(QualType Ty, CCState &State) const;
999 bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
1000 bool &NeedsPadding) const;
1001 bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const;
1003 bool canExpandIndirectArgument(QualType Ty) const;
1005 /// \brief Rewrite the function info so that all memory arguments use
1007 void rewriteWithInAlloca(CGFunctionInfo &FI) const;
1009 void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1010 CharUnits &StackOffset, ABIArgInfo &Info,
1011 QualType Type) const;
1012 void computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
1013 bool &UsedInAlloca) const;
1017 void computeInfo(CGFunctionInfo &FI) const override;
1018 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1019 QualType Ty) const override;
1021 X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1022 bool RetSmallStructInRegABI, bool Win32StructABI,
1023 unsigned NumRegisterParameters, bool SoftFloatABI)
1024 : SwiftABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
1025 IsRetSmallStructInRegABI(RetSmallStructInRegABI),
1026 IsWin32StructABI(Win32StructABI),
1027 IsSoftFloatABI(SoftFloatABI),
1028 IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()),
1029 DefaultNumRegisterParameters(NumRegisterParameters) {}
1031 bool shouldPassIndirectlyForSwift(CharUnits totalSize,
1032 ArrayRef<llvm::Type*> scalars,
1033 bool asReturnValue) const override {
1034 // LLVM's x86-32 lowering currently only assigns up to three
1035 // integer registers and three fp registers. Oddly, it'll use up to
1036 // four vector registers for vectors, but those can overlap with the
1037 // scalar registers.
1038 return occupiesMoreThan(CGT, scalars, /*total*/ 3);
1041 bool isSwiftErrorInRegister() const override {
1042 // x86-32 lowering does not support passing swifterror in a register.
1047 class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
1049 X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1050 bool RetSmallStructInRegABI, bool Win32StructABI,
1051 unsigned NumRegisterParameters, bool SoftFloatABI)
1052 : TargetCodeGenInfo(new X86_32ABIInfo(
1053 CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
1054 NumRegisterParameters, SoftFloatABI)) {}
1056 static bool isStructReturnInRegABI(
1057 const llvm::Triple &Triple, const CodeGenOptions &Opts);
1059 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
1060 CodeGen::CodeGenModule &CGM,
1061 ForDefinition_t IsForDefinition) const override;
1063 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
1064 // Darwin uses different dwarf register numbers for EH.
1065 if (CGM.getTarget().getTriple().isOSDarwin()) return 5;
1069 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1070 llvm::Value *Address) const override;
1072 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
1073 StringRef Constraint,
1074 llvm::Type* Ty) const override {
1075 return X86AdjustInlineAsmType(CGF, Constraint, Ty);
1078 void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue,
1079 std::string &Constraints,
1080 std::vector<llvm::Type *> &ResultRegTypes,
1081 std::vector<llvm::Type *> &ResultTruncRegTypes,
1082 std::vector<LValue> &ResultRegDests,
1083 std::string &AsmString,
1084 unsigned NumOutputs) const override;
1087 getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
1088 unsigned Sig = (0xeb << 0) | // jmp rel8
1089 (0x06 << 8) | // .+0x08
1092 return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
1095 StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
1096 return "movl\t%ebp, %ebp"
1097 "\t\t// marker for objc_retainAutoreleaseReturnValue";
1103 /// Rewrite input constraint references after adding some output constraints.
1104 /// In the case where there is one output and one input and we add one output,
1105 /// we need to replace all operand references greater than or equal to 1:
1108 /// The result will be:
1111 static void rewriteInputConstraintReferences(unsigned FirstIn,
1112 unsigned NumNewOuts,
1113 std::string &AsmString) {
1115 llvm::raw_string_ostream OS(Buf);
1117 while (Pos < AsmString.size()) {
1118 size_t DollarStart = AsmString.find('$', Pos);
1119 if (DollarStart == std::string::npos)
1120 DollarStart = AsmString.size();
1121 size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart);
1122 if (DollarEnd == std::string::npos)
1123 DollarEnd = AsmString.size();
1124 OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
1126 size_t NumDollars = DollarEnd - DollarStart;
1127 if (NumDollars % 2 != 0 && Pos < AsmString.size()) {
1128 // We have an operand reference.
1129 size_t DigitStart = Pos;
1130 size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart);
1131 if (DigitEnd == std::string::npos)
1132 DigitEnd = AsmString.size();
1133 StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
1134 unsigned OperandIndex;
1135 if (!OperandStr.getAsInteger(10, OperandIndex)) {
1136 if (OperandIndex >= FirstIn)
1137 OperandIndex += NumNewOuts;
1145 AsmString = std::move(OS.str());
1148 /// Add output constraints for EAX:EDX because they are return registers.
1149 void X86_32TargetCodeGenInfo::addReturnRegisterOutputs(
1150 CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints,
1151 std::vector<llvm::Type *> &ResultRegTypes,
1152 std::vector<llvm::Type *> &ResultTruncRegTypes,
1153 std::vector<LValue> &ResultRegDests, std::string &AsmString,
1154 unsigned NumOutputs) const {
1155 uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType());
1157 // Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is
1159 if (!Constraints.empty())
1161 if (RetWidth <= 32) {
1162 Constraints += "={eax}";
1163 ResultRegTypes.push_back(CGF.Int32Ty);
1165 // Use the 'A' constraint for EAX:EDX.
1166 Constraints += "=A";
1167 ResultRegTypes.push_back(CGF.Int64Ty);
1170 // Truncate EAX or EAX:EDX to an integer of the appropriate size.
1171 llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth);
1172 ResultTruncRegTypes.push_back(CoerceTy);
1174 // Coerce the integer by bitcasting the return slot pointer.
1175 ReturnSlot.setAddress(CGF.Builder.CreateBitCast(ReturnSlot.getAddress(),
1176 CoerceTy->getPointerTo()));
1177 ResultRegDests.push_back(ReturnSlot);
1179 rewriteInputConstraintReferences(NumOutputs, 1, AsmString);
1182 /// shouldReturnTypeInRegister - Determine if the given type should be
1183 /// returned in a register (for the Darwin and MCU ABI).
1184 bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
1185 ASTContext &Context) const {
1186 uint64_t Size = Context.getTypeSize(Ty);
1188 // For i386, type must be register sized.
1189 // For the MCU ABI, it only needs to be <= 8-byte
1190 if ((IsMCUABI && Size > 64) || (!IsMCUABI && !isRegisterSize(Size)))
1193 if (Ty->isVectorType()) {
1194 // 64- and 128- bit vectors inside structures are not returned in
1196 if (Size == 64 || Size == 128)
1202 // If this is a builtin, pointer, enum, complex type, member pointer, or
1203 // member function pointer it is ok.
1204 if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() ||
1205 Ty->isAnyComplexType() || Ty->isEnumeralType() ||
1206 Ty->isBlockPointerType() || Ty->isMemberPointerType())
1209 // Arrays are treated like records.
1210 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty))
1211 return shouldReturnTypeInRegister(AT->getElementType(), Context);
1213 // Otherwise, it must be a record type.
1214 const RecordType *RT = Ty->getAs<RecordType>();
1215 if (!RT) return false;
1217 // FIXME: Traverse bases here too.
1219 // Structure types are passed in register if all fields would be
1220 // passed in a register.
1221 for (const auto *FD : RT->getDecl()->fields()) {
1222 // Empty fields are ignored.
1223 if (isEmptyField(Context, FD, true))
1226 // Check fields recursively.
1227 if (!shouldReturnTypeInRegister(FD->getType(), Context))
1233 static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) {
1234 // Treat complex types as the element type.
1235 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
1236 Ty = CTy->getElementType();
1238 // Check for a type which we know has a simple scalar argument-passing
1239 // convention without any padding. (We're specifically looking for 32
1240 // and 64-bit integer and integer-equivalents, float, and double.)
1241 if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() &&
1242 !Ty->isEnumeralType() && !Ty->isBlockPointerType())
1245 uint64_t Size = Context.getTypeSize(Ty);
1246 return Size == 32 || Size == 64;
1249 static bool addFieldSizes(ASTContext &Context, const RecordDecl *RD,
1251 for (const auto *FD : RD->fields()) {
1252 // Scalar arguments on the stack get 4 byte alignment on x86. If the
1253 // argument is smaller than 32-bits, expanding the struct will create
1254 // alignment padding.
1255 if (!is32Or64BitBasicType(FD->getType(), Context))
1258 // FIXME: Reject bit-fields wholesale; there are two problems, we don't know
1259 // how to expand them yet, and the predicate for telling if a bitfield still
1260 // counts as "basic" is more complicated than what we were doing previously.
1261 if (FD->isBitField())
1264 Size += Context.getTypeSize(FD->getType());
1269 static bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD,
1271 // Don't do this if there are any non-empty bases.
1272 for (const CXXBaseSpecifier &Base : RD->bases()) {
1273 if (!addBaseAndFieldSizes(Context, Base.getType()->getAsCXXRecordDecl(),
1277 if (!addFieldSizes(Context, RD, Size))
1282 /// Test whether an argument type which is to be passed indirectly (on the
1283 /// stack) would have the equivalent layout if it was expanded into separate
1284 /// arguments. If so, we prefer to do the latter to avoid inhibiting
1286 bool X86_32ABIInfo::canExpandIndirectArgument(QualType Ty) const {
1287 // We can only expand structure types.
1288 const RecordType *RT = Ty->getAs<RecordType>();
1291 const RecordDecl *RD = RT->getDecl();
1293 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
1294 if (!IsWin32StructABI) {
1295 // On non-Windows, we have to conservatively match our old bitcode
1296 // prototypes in order to be ABI-compatible at the bitcode level.
1297 if (!CXXRD->isCLike())
1300 // Don't do this for dynamic classes.
1301 if (CXXRD->isDynamicClass())
1304 if (!addBaseAndFieldSizes(getContext(), CXXRD, Size))
1307 if (!addFieldSizes(getContext(), RD, Size))
1311 // We can do this if there was no alignment padding.
1312 return Size == getContext().getTypeSize(Ty);
1315 ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(QualType RetTy, CCState &State) const {
1316 // If the return value is indirect, then the hidden argument is consuming one
1317 // integer register.
1318 if (State.FreeRegs) {
1321 return getNaturalAlignIndirectInReg(RetTy);
1323 return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
1326 ABIArgInfo X86_32ABIInfo::classifyReturnType(QualType RetTy,
1327 CCState &State) const {
1328 if (RetTy->isVoidType())
1329 return ABIArgInfo::getIgnore();
1331 const Type *Base = nullptr;
1332 uint64_t NumElts = 0;
1333 if ((State.CC == llvm::CallingConv::X86_VectorCall ||
1334 State.CC == llvm::CallingConv::X86_RegCall) &&
1335 isHomogeneousAggregate(RetTy, Base, NumElts)) {
1336 // The LLVM struct type for such an aggregate should lower properly.
1337 return ABIArgInfo::getDirect();
1340 if (const VectorType *VT = RetTy->getAs<VectorType>()) {
1341 // On Darwin, some vectors are returned in registers.
1342 if (IsDarwinVectorABI) {
1343 uint64_t Size = getContext().getTypeSize(RetTy);
1345 // 128-bit vectors are a special case; they are returned in
1346 // registers and we need to make sure to pick a type the LLVM
1347 // backend will like.
1349 return ABIArgInfo::getDirect(llvm::VectorType::get(
1350 llvm::Type::getInt64Ty(getVMContext()), 2));
1352 // Always return in register if it fits in a general purpose
1353 // register, or if it is 64 bits and has a single element.
1354 if ((Size == 8 || Size == 16 || Size == 32) ||
1355 (Size == 64 && VT->getNumElements() == 1))
1356 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1359 return getIndirectReturnResult(RetTy, State);
1362 return ABIArgInfo::getDirect();
1365 if (isAggregateTypeForABI(RetTy)) {
1366 if (const RecordType *RT = RetTy->getAs<RecordType>()) {
1367 // Structures with flexible arrays are always indirect.
1368 if (RT->getDecl()->hasFlexibleArrayMember())
1369 return getIndirectReturnResult(RetTy, State);
1372 // If specified, structs and unions are always indirect.
1373 if (!IsRetSmallStructInRegABI && !RetTy->isAnyComplexType())
1374 return getIndirectReturnResult(RetTy, State);
1376 // Ignore empty structs/unions.
1377 if (isEmptyRecord(getContext(), RetTy, true))
1378 return ABIArgInfo::getIgnore();
1380 // Small structures which are register sized are generally returned
1382 if (shouldReturnTypeInRegister(RetTy, getContext())) {
1383 uint64_t Size = getContext().getTypeSize(RetTy);
1385 // As a special-case, if the struct is a "single-element" struct, and
1386 // the field is of type "float" or "double", return it in a
1387 // floating-point register. (MSVC does not apply this special case.)
1388 // We apply a similar transformation for pointer types to improve the
1389 // quality of the generated IR.
1390 if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
1391 if ((!IsWin32StructABI && SeltTy->isRealFloatingType())
1392 || SeltTy->hasPointerRepresentation())
1393 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
1395 // FIXME: We should be able to narrow this integer in cases with dead
1397 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size));
1400 return getIndirectReturnResult(RetTy, State);
1403 // Treat an enum type as its underlying type.
1404 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
1405 RetTy = EnumTy->getDecl()->getIntegerType();
1407 return (RetTy->isPromotableIntegerType() ?
1408 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
1411 static bool isSSEVectorType(ASTContext &Context, QualType Ty) {
1412 return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128;
1415 static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) {
1416 const RecordType *RT = Ty->getAs<RecordType>();
1419 const RecordDecl *RD = RT->getDecl();
1421 // If this is a C++ record, check the bases first.
1422 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
1423 for (const auto &I : CXXRD->bases())
1424 if (!isRecordWithSSEVectorType(Context, I.getType()))
1427 for (const auto *i : RD->fields()) {
1428 QualType FT = i->getType();
1430 if (isSSEVectorType(Context, FT))
1433 if (isRecordWithSSEVectorType(Context, FT))
1440 unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty,
1441 unsigned Align) const {
1442 // Otherwise, if the alignment is less than or equal to the minimum ABI
1443 // alignment, just use the default; the backend will handle this.
1444 if (Align <= MinABIStackAlignInBytes)
1445 return 0; // Use default alignment.
1447 // On non-Darwin, the stack type alignment is always 4.
1448 if (!IsDarwinVectorABI) {
1449 // Set explicit alignment, since we may need to realign the top.
1450 return MinABIStackAlignInBytes;
1453 // Otherwise, if the type contains an SSE vector type, the alignment is 16.
1454 if (Align >= 16 && (isSSEVectorType(getContext(), Ty) ||
1455 isRecordWithSSEVectorType(getContext(), Ty)))
1458 return MinABIStackAlignInBytes;
1461 ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal,
1462 CCState &State) const {
1464 if (State.FreeRegs) {
1465 --State.FreeRegs; // Non-byval indirects just use one pointer.
1467 return getNaturalAlignIndirectInReg(Ty);
1469 return getNaturalAlignIndirect(Ty, false);
1472 // Compute the byval alignment.
1473 unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
1474 unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign);
1475 if (StackAlign == 0)
1476 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true);
1478 // If the stack alignment is less than the type alignment, realign the
1480 bool Realign = TypeAlign > StackAlign;
1481 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(StackAlign),
1482 /*ByVal=*/true, Realign);
1485 X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const {
1486 const Type *T = isSingleElementStruct(Ty, getContext());
1488 T = Ty.getTypePtr();
1490 if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
1491 BuiltinType::Kind K = BT->getKind();
1492 if (K == BuiltinType::Float || K == BuiltinType::Double)
1498 bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const {
1499 if (!IsSoftFloatABI) {
1500 Class C = classify(Ty);
1505 unsigned Size = getContext().getTypeSize(Ty);
1506 unsigned SizeInRegs = (Size + 31) / 32;
1508 if (SizeInRegs == 0)
1512 if (SizeInRegs > State.FreeRegs) {
1517 // The MCU psABI allows passing parameters in-reg even if there are
1518 // earlier parameters that are passed on the stack. Also,
1519 // it does not allow passing >8-byte structs in-register,
1520 // even if there are 3 free registers available.
1521 if (SizeInRegs > State.FreeRegs || SizeInRegs > 2)
1525 State.FreeRegs -= SizeInRegs;
1529 bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State,
1531 bool &NeedsPadding) const {
1532 // On Windows, aggregates other than HFAs are never passed in registers, and
1533 // they do not consume register slots. Homogenous floating-point aggregates
1534 // (HFAs) have already been dealt with at this point.
1535 if (IsWin32StructABI && isAggregateTypeForABI(Ty))
1538 NeedsPadding = false;
1541 if (!updateFreeRegs(Ty, State))
1547 if (State.CC == llvm::CallingConv::X86_FastCall ||
1548 State.CC == llvm::CallingConv::X86_VectorCall ||
1549 State.CC == llvm::CallingConv::X86_RegCall) {
1550 if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs)
1551 NeedsPadding = true;
1559 bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const {
1560 if (!updateFreeRegs(Ty, State))
1566 if (State.CC == llvm::CallingConv::X86_FastCall ||
1567 State.CC == llvm::CallingConv::X86_VectorCall ||
1568 State.CC == llvm::CallingConv::X86_RegCall) {
1569 if (getContext().getTypeSize(Ty) > 32)
1572 return (Ty->isIntegralOrEnumerationType() || Ty->isPointerType() ||
1573 Ty->isReferenceType());
1579 ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
1580 CCState &State) const {
1581 // FIXME: Set alignment on indirect arguments.
1583 Ty = useFirstFieldIfTransparentUnion(Ty);
1585 // Check with the C++ ABI first.
1586 const RecordType *RT = Ty->getAs<RecordType>();
1588 CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
1589 if (RAA == CGCXXABI::RAA_Indirect) {
1590 return getIndirectResult(Ty, false, State);
1591 } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
1592 // The field index doesn't matter, we'll fix it up later.
1593 return ABIArgInfo::getInAlloca(/*FieldIndex=*/0);
1597 // Regcall uses the concept of a homogenous vector aggregate, similar
1598 // to other targets.
1599 const Type *Base = nullptr;
1600 uint64_t NumElts = 0;
1601 if (State.CC == llvm::CallingConv::X86_RegCall &&
1602 isHomogeneousAggregate(Ty, Base, NumElts)) {
1604 if (State.FreeSSERegs >= NumElts) {
1605 State.FreeSSERegs -= NumElts;
1606 if (Ty->isBuiltinType() || Ty->isVectorType())
1607 return ABIArgInfo::getDirect();
1608 return ABIArgInfo::getExpand();
1610 return getIndirectResult(Ty, /*ByVal=*/false, State);
1613 if (isAggregateTypeForABI(Ty)) {
1614 // Structures with flexible arrays are always indirect.
1615 // FIXME: This should not be byval!
1616 if (RT && RT->getDecl()->hasFlexibleArrayMember())
1617 return getIndirectResult(Ty, true, State);
1619 // Ignore empty structs/unions on non-Windows.
1620 if (!IsWin32StructABI && isEmptyRecord(getContext(), Ty, true))
1621 return ABIArgInfo::getIgnore();
1623 llvm::LLVMContext &LLVMContext = getVMContext();
1624 llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
1625 bool NeedsPadding = false;
1627 if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
1628 unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
1629 SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
1630 llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
1632 return ABIArgInfo::getDirectInReg(Result);
1634 return ABIArgInfo::getDirect(Result);
1636 llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr;
1638 // Expand small (<= 128-bit) record types when we know that the stack layout
1639 // of those arguments will match the struct. This is important because the
1640 // LLVM backend isn't smart enough to remove byval, which inhibits many
1642 // Don't do this for the MCU if there are still free integer registers
1643 // (see X86_64 ABI for full explanation).
1644 if (getContext().getTypeSize(Ty) <= 4 * 32 &&
1645 (!IsMCUABI || State.FreeRegs == 0) && canExpandIndirectArgument(Ty))
1646 return ABIArgInfo::getExpandWithPadding(
1647 State.CC == llvm::CallingConv::X86_FastCall ||
1648 State.CC == llvm::CallingConv::X86_VectorCall ||
1649 State.CC == llvm::CallingConv::X86_RegCall,
1652 return getIndirectResult(Ty, true, State);
1655 if (const VectorType *VT = Ty->getAs<VectorType>()) {
1656 // On Darwin, some vectors are passed in memory, we handle this by passing
1657 // it as an i8/i16/i32/i64.
1658 if (IsDarwinVectorABI) {
1659 uint64_t Size = getContext().getTypeSize(Ty);
1660 if ((Size == 8 || Size == 16 || Size == 32) ||
1661 (Size == 64 && VT->getNumElements() == 1))
1662 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1666 if (IsX86_MMXType(CGT.ConvertType(Ty)))
1667 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
1669 return ABIArgInfo::getDirect();
1673 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
1674 Ty = EnumTy->getDecl()->getIntegerType();
1676 bool InReg = shouldPrimitiveUseInReg(Ty, State);
1678 if (Ty->isPromotableIntegerType()) {
1680 return ABIArgInfo::getExtendInReg();
1681 return ABIArgInfo::getExtend();
1685 return ABIArgInfo::getDirectInReg();
1686 return ABIArgInfo::getDirect();
1689 void X86_32ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
1690 bool &UsedInAlloca) const {
1691 // Vectorcall x86 works subtly different than in x64, so the format is
1692 // a bit different than the x64 version. First, all vector types (not HVAs)
1693 // are assigned, with the first 6 ending up in the YMM0-5 or XMM0-5 registers.
1694 // This differs from the x64 implementation, where the first 6 by INDEX get
1696 // After that, integers AND HVAs are assigned Left to Right in the same pass.
1697 // Integers are passed as ECX/EDX if one is available (in order). HVAs will
1698 // first take up the remaining YMM/XMM registers. If insufficient registers
1699 // remain but an integer register (ECX/EDX) is available, it will be passed
1700 // in that, else, on the stack.
1701 for (auto &I : FI.arguments()) {
1702 // First pass do all the vector types.
1703 const Type *Base = nullptr;
1704 uint64_t NumElts = 0;
1705 const QualType& Ty = I.type;
1706 if ((Ty->isVectorType() || Ty->isBuiltinType()) &&
1707 isHomogeneousAggregate(Ty, Base, NumElts)) {
1708 if (State.FreeSSERegs >= NumElts) {
1709 State.FreeSSERegs -= NumElts;
1710 I.info = ABIArgInfo::getDirect();
1712 I.info = classifyArgumentType(Ty, State);
1714 UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1718 for (auto &I : FI.arguments()) {
1719 // Second pass, do the rest!
1720 const Type *Base = nullptr;
1721 uint64_t NumElts = 0;
1722 const QualType& Ty = I.type;
1723 bool IsHva = isHomogeneousAggregate(Ty, Base, NumElts);
1725 if (IsHva && !Ty->isVectorType() && !Ty->isBuiltinType()) {
1726 // Assign true HVAs (non vector/native FP types).
1727 if (State.FreeSSERegs >= NumElts) {
1728 State.FreeSSERegs -= NumElts;
1729 I.info = getDirectX86Hva();
1731 I.info = getIndirectResult(Ty, /*ByVal=*/false, State);
1733 } else if (!IsHva) {
1734 // Assign all Non-HVAs, so this will exclude Vector/FP args.
1735 I.info = classifyArgumentType(Ty, State);
1736 UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1741 void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
1742 CCState State(FI.getCallingConvention());
1745 else if (State.CC == llvm::CallingConv::X86_FastCall)
1747 else if (State.CC == llvm::CallingConv::X86_VectorCall) {
1749 State.FreeSSERegs = 6;
1750 } else if (FI.getHasRegParm())
1751 State.FreeRegs = FI.getRegParm();
1752 else if (State.CC == llvm::CallingConv::X86_RegCall) {
1754 State.FreeSSERegs = 8;
1756 State.FreeRegs = DefaultNumRegisterParameters;
1758 if (!getCXXABI().classifyReturnType(FI)) {
1759 FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), State);
1760 } else if (FI.getReturnInfo().isIndirect()) {
1761 // The C++ ABI is not aware of register usage, so we have to check if the
1762 // return value was sret and put it in a register ourselves if appropriate.
1763 if (State.FreeRegs) {
1764 --State.FreeRegs; // The sret parameter consumes a register.
1766 FI.getReturnInfo().setInReg(true);
1770 // The chain argument effectively gives us another free register.
1771 if (FI.isChainCall())
1774 bool UsedInAlloca = false;
1775 if (State.CC == llvm::CallingConv::X86_VectorCall) {
1776 computeVectorCallArgs(FI, State, UsedInAlloca);
1778 // If not vectorcall, revert to normal behavior.
1779 for (auto &I : FI.arguments()) {
1780 I.info = classifyArgumentType(I.type, State);
1781 UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1785 // If we needed to use inalloca for any argument, do a second pass and rewrite
1786 // all the memory arguments to use inalloca.
1788 rewriteWithInAlloca(FI);
1792 X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1793 CharUnits &StackOffset, ABIArgInfo &Info,
1794 QualType Type) const {
1795 // Arguments are always 4-byte-aligned.
1796 CharUnits FieldAlign = CharUnits::fromQuantity(4);
1798 assert(StackOffset.isMultipleOf(FieldAlign) && "unaligned inalloca struct");
1799 Info = ABIArgInfo::getInAlloca(FrameFields.size());
1800 FrameFields.push_back(CGT.ConvertTypeForMem(Type));
1801 StackOffset += getContext().getTypeSizeInChars(Type);
1803 // Insert padding bytes to respect alignment.
1804 CharUnits FieldEnd = StackOffset;
1805 StackOffset = FieldEnd.alignTo(FieldAlign);
1806 if (StackOffset != FieldEnd) {
1807 CharUnits NumBytes = StackOffset - FieldEnd;
1808 llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
1809 Ty = llvm::ArrayType::get(Ty, NumBytes.getQuantity());
1810 FrameFields.push_back(Ty);
1814 static bool isArgInAlloca(const ABIArgInfo &Info) {
1815 // Leave ignored and inreg arguments alone.
1816 switch (Info.getKind()) {
1817 case ABIArgInfo::InAlloca:
1819 case ABIArgInfo::Indirect:
1820 assert(Info.getIndirectByVal());
1822 case ABIArgInfo::Ignore:
1824 case ABIArgInfo::Direct:
1825 case ABIArgInfo::Extend:
1826 if (Info.getInReg())
1829 case ABIArgInfo::Expand:
1830 case ABIArgInfo::CoerceAndExpand:
1831 // These are aggregate types which are never passed in registers when
1832 // inalloca is involved.
1835 llvm_unreachable("invalid enum");
1838 void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
1839 assert(IsWin32StructABI && "inalloca only supported on win32");
1841 // Build a packed struct type for all of the arguments in memory.
1842 SmallVector<llvm::Type *, 6> FrameFields;
1844 // The stack alignment is always 4.
1845 CharUnits StackAlign = CharUnits::fromQuantity(4);
1847 CharUnits StackOffset;
1848 CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end();
1850 // Put 'this' into the struct before 'sret', if necessary.
1852 FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
1853 ABIArgInfo &Ret = FI.getReturnInfo();
1854 if (Ret.isIndirect() && Ret.isSRetAfterThis() && !IsThisCall &&
1855 isArgInAlloca(I->info)) {
1856 addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1860 // Put the sret parameter into the inalloca struct if it's in memory.
1861 if (Ret.isIndirect() && !Ret.getInReg()) {
1862 CanQualType PtrTy = getContext().getPointerType(FI.getReturnType());
1863 addFieldToArgStruct(FrameFields, StackOffset, Ret, PtrTy);
1864 // On Windows, the hidden sret parameter is always returned in eax.
1865 Ret.setInAllocaSRet(IsWin32StructABI);
1868 // Skip the 'this' parameter in ecx.
1872 // Put arguments passed in memory into the struct.
1873 for (; I != E; ++I) {
1874 if (isArgInAlloca(I->info))
1875 addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1878 FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
1883 Address X86_32ABIInfo::EmitVAArg(CodeGenFunction &CGF,
1884 Address VAListAddr, QualType Ty) const {
1886 auto TypeInfo = getContext().getTypeInfoInChars(Ty);
1888 // x86-32 changes the alignment of certain arguments on the stack.
1890 // Just messing with TypeInfo like this works because we never pass
1891 // anything indirectly.
1892 TypeInfo.second = CharUnits::fromQuantity(
1893 getTypeStackAlignInBytes(Ty, TypeInfo.second.getQuantity()));
1895 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
1896 TypeInfo, CharUnits::fromQuantity(4),
1897 /*AllowHigherAlign*/ true);
1900 bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
1901 const llvm::Triple &Triple, const CodeGenOptions &Opts) {
1902 assert(Triple.getArch() == llvm::Triple::x86);
1904 switch (Opts.getStructReturnConvention()) {
1905 case CodeGenOptions::SRCK_Default:
1907 case CodeGenOptions::SRCK_OnStack: // -fpcc-struct-return
1909 case CodeGenOptions::SRCK_InRegs: // -freg-struct-return
1913 if (Triple.isOSDarwin() || Triple.isOSIAMCU())
1916 switch (Triple.getOS()) {
1917 case llvm::Triple::DragonFly:
1918 case llvm::Triple::FreeBSD:
1919 case llvm::Triple::OpenBSD:
1920 case llvm::Triple::Win32:
1927 void X86_32TargetCodeGenInfo::setTargetAttributes(
1928 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM,
1929 ForDefinition_t IsForDefinition) const {
1930 if (!IsForDefinition)
1932 if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
1933 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1934 llvm::Function *Fn = cast<llvm::Function>(GV);
1935 Fn->addFnAttr("stackrealign");
1937 if (FD->hasAttr<AnyX86InterruptAttr>()) {
1938 llvm::Function *Fn = cast<llvm::Function>(GV);
1939 Fn->setCallingConv(llvm::CallingConv::X86_INTR);
1944 bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
1945 CodeGen::CodeGenFunction &CGF,
1946 llvm::Value *Address) const {
1947 CodeGen::CGBuilderTy &Builder = CGF.Builder;
1949 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
1951 // 0-7 are the eight integer registers; the order is different
1952 // on Darwin (for EH), but the range is the same.
1954 AssignToArrayRange(Builder, Address, Four8, 0, 8);
1956 if (CGF.CGM.getTarget().getTriple().isOSDarwin()) {
1957 // 12-16 are st(0..4). Not sure why we stop at 4.
1958 // These have size 16, which is sizeof(long double) on
1959 // platforms with 8-byte alignment for that type.
1960 llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
1961 AssignToArrayRange(Builder, Address, Sixteen8, 12, 16);
1964 // 9 is %eflags, which doesn't get a size on Darwin for some
1966 Builder.CreateAlignedStore(
1967 Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9),
1970 // 11-16 are st(0..5). Not sure why we stop at 5.
1971 // These have size 12, which is sizeof(long double) on
1972 // platforms with 4-byte alignment for that type.
1973 llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12);
1974 AssignToArrayRange(Builder, Address, Twelve8, 11, 16);
1980 //===----------------------------------------------------------------------===//
1981 // X86-64 ABI Implementation
1982 //===----------------------------------------------------------------------===//
1986 /// The AVX ABI level for X86 targets.
1987 enum class X86AVXABILevel {
1993 /// \p returns the size in bits of the largest (native) vector for \p AVXLevel.
1994 static unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) {
1996 case X86AVXABILevel::AVX512:
1998 case X86AVXABILevel::AVX:
2000 case X86AVXABILevel::None:
2003 llvm_unreachable("Unknown AVXLevel");
2006 /// X86_64ABIInfo - The X86_64 ABI information.
2007 class X86_64ABIInfo : public SwiftABIInfo {
2019 /// merge - Implement the X86_64 ABI merging algorithm.
2021 /// Merge an accumulating classification \arg Accum with a field
2022 /// classification \arg Field.
2024 /// \param Accum - The accumulating classification. This should
2025 /// always be either NoClass or the result of a previous merge
2026 /// call. In addition, this should never be Memory (the caller
2027 /// should just return Memory for the aggregate).
2028 static Class merge(Class Accum, Class Field);
2030 /// postMerge - Implement the X86_64 ABI post merging algorithm.
2032 /// Post merger cleanup, reduces a malformed Hi and Lo pair to
2033 /// final MEMORY or SSE classes when necessary.
2035 /// \param AggregateSize - The size of the current aggregate in
2036 /// the classification process.
2038 /// \param Lo - The classification for the parts of the type
2039 /// residing in the low word of the containing object.
2041 /// \param Hi - The classification for the parts of the type
2042 /// residing in the higher words of the containing object.
2044 void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
2046 /// classify - Determine the x86_64 register classes in which the
2047 /// given type T should be passed.
2049 /// \param Lo - The classification for the parts of the type
2050 /// residing in the low word of the containing object.
2052 /// \param Hi - The classification for the parts of the type
2053 /// residing in the high word of the containing object.
2055 /// \param OffsetBase - The bit offset of this type in the
2056 /// containing object. Some parameters are classified different
2057 /// depending on whether they straddle an eightbyte boundary.
2059 /// \param isNamedArg - Whether the argument in question is a "named"
2060 /// argument, as used in AMD64-ABI 3.5.7.
2062 /// If a word is unused its result will be NoClass; if a type should
2063 /// be passed in Memory then at least the classification of \arg Lo
2066 /// The \arg Lo class will be NoClass iff the argument is ignored.
2068 /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
2069 /// also be ComplexX87.
2070 void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
2071 bool isNamedArg) const;
2073 llvm::Type *GetByteVectorType(QualType Ty) const;
2074 llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType,
2075 unsigned IROffset, QualType SourceTy,
2076 unsigned SourceOffset) const;
2077 llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType,
2078 unsigned IROffset, QualType SourceTy,
2079 unsigned SourceOffset) const;
2081 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2082 /// such that the argument will be returned in memory.
2083 ABIArgInfo getIndirectReturnResult(QualType Ty) const;
2085 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2086 /// such that the argument will be passed in memory.
2088 /// \param freeIntRegs - The number of free integer registers remaining
2090 ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const;
2092 ABIArgInfo classifyReturnType(QualType RetTy) const;
2094 ABIArgInfo classifyArgumentType(QualType Ty, unsigned freeIntRegs,
2095 unsigned &neededInt, unsigned &neededSSE,
2096 bool isNamedArg) const;
2098 ABIArgInfo classifyRegCallStructType(QualType Ty, unsigned &NeededInt,
2099 unsigned &NeededSSE) const;
2101 ABIArgInfo classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
2102 unsigned &NeededSSE) const;
2104 bool IsIllegalVectorType(QualType Ty) const;
2106 /// The 0.98 ABI revision clarified a lot of ambiguities,
2107 /// unfortunately in ways that were not always consistent with
2108 /// certain previous compilers. In particular, platforms which
2109 /// required strict binary compatibility with older versions of GCC
2110 /// may need to exempt themselves.
2111 bool honorsRevision0_98() const {
2112 return !getTarget().getTriple().isOSDarwin();
2115 /// GCC classifies <1 x long long> as SSE but some platform ABIs choose to
2116 /// classify it as INTEGER (for compatibility with older clang compilers).
2117 bool classifyIntegerMMXAsSSE() const {
2118 // Clang <= 3.8 did not do this.
2119 if (getCodeGenOpts().getClangABICompat() <=
2120 CodeGenOptions::ClangABI::Ver3_8)
2123 const llvm::Triple &Triple = getTarget().getTriple();
2124 if (Triple.isOSDarwin() || Triple.getOS() == llvm::Triple::PS4)
2126 if (Triple.isOSFreeBSD() && Triple.getOSMajorVersion() >= 10)
2131 X86AVXABILevel AVXLevel;
2132 // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on
2134 bool Has64BitPointers;
2137 X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) :
2138 SwiftABIInfo(CGT), AVXLevel(AVXLevel),
2139 Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) {
2142 bool isPassedUsingAVXType(QualType type) const {
2143 unsigned neededInt, neededSSE;
2144 // The freeIntRegs argument doesn't matter here.
2145 ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE,
2146 /*isNamedArg*/true);
2147 if (info.isDirect()) {
2148 llvm::Type *ty = info.getCoerceToType();
2149 if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty))
2150 return (vectorTy->getBitWidth() > 128);
2155 void computeInfo(CGFunctionInfo &FI) const override;
2157 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2158 QualType Ty) const override;
2159 Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
2160 QualType Ty) const override;
2162 bool has64BitPointers() const {
2163 return Has64BitPointers;
2166 bool shouldPassIndirectlyForSwift(CharUnits totalSize,
2167 ArrayRef<llvm::Type*> scalars,
2168 bool asReturnValue) const override {
2169 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2171 bool isSwiftErrorInRegister() const override {
2176 /// WinX86_64ABIInfo - The Windows X86_64 ABI information.
2177 class WinX86_64ABIInfo : public SwiftABIInfo {
2179 WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT)
2180 : SwiftABIInfo(CGT),
2181 IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {}
2183 void computeInfo(CGFunctionInfo &FI) const override;
2185 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2186 QualType Ty) const override;
2188 bool isHomogeneousAggregateBaseType(QualType Ty) const override {
2189 // FIXME: Assumes vectorcall is in use.
2190 return isX86VectorTypeForVectorCall(getContext(), Ty);
2193 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
2194 uint64_t NumMembers) const override {
2195 // FIXME: Assumes vectorcall is in use.
2196 return isX86VectorCallAggregateSmallEnough(NumMembers);
2199 bool shouldPassIndirectlyForSwift(CharUnits totalSize,
2200 ArrayRef<llvm::Type *> scalars,
2201 bool asReturnValue) const override {
2202 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2205 bool isSwiftErrorInRegister() const override {
2210 ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs, bool IsReturnType,
2211 bool IsVectorCall, bool IsRegCall) const;
2212 ABIArgInfo reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
2213 const ABIArgInfo ¤t) const;
2214 void computeVectorCallArgs(CGFunctionInfo &FI, unsigned FreeSSERegs,
2215 bool IsVectorCall, bool IsRegCall) const;
2220 class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2222 X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2223 : TargetCodeGenInfo(new X86_64ABIInfo(CGT, AVXLevel)) {}
2225 const X86_64ABIInfo &getABIInfo() const {
2226 return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo());
2229 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2233 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2234 llvm::Value *Address) const override {
2235 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2237 // 0-15 are the 16 integer registers.
2239 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2243 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
2244 StringRef Constraint,
2245 llvm::Type* Ty) const override {
2246 return X86AdjustInlineAsmType(CGF, Constraint, Ty);
2249 bool isNoProtoCallVariadic(const CallArgList &args,
2250 const FunctionNoProtoType *fnType) const override {
2251 // The default CC on x86-64 sets %al to the number of SSA
2252 // registers used, and GCC sets this when calling an unprototyped
2253 // function, so we override the default behavior. However, don't do
2254 // that when AVX types are involved: the ABI explicitly states it is
2255 // undefined, and it doesn't work in practice because of how the ABI
2256 // defines varargs anyway.
2257 if (fnType->getCallConv() == CC_C) {
2258 bool HasAVXType = false;
2259 for (CallArgList::const_iterator
2260 it = args.begin(), ie = args.end(); it != ie; ++it) {
2261 if (getABIInfo().isPassedUsingAVXType(it->Ty)) {
2271 return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType);
2275 getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
2276 unsigned Sig = (0xeb << 0) | // jmp rel8
2277 (0x06 << 8) | // .+0x08
2280 return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
2283 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2284 CodeGen::CodeGenModule &CGM,
2285 ForDefinition_t IsForDefinition) const override {
2286 if (!IsForDefinition)
2288 if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2289 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2290 llvm::Function *Fn = cast<llvm::Function>(GV);
2291 Fn->addFnAttr("stackrealign");
2293 if (FD->hasAttr<AnyX86InterruptAttr>()) {
2294 llvm::Function *Fn = cast<llvm::Function>(GV);
2295 Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2301 class PS4TargetCodeGenInfo : public X86_64TargetCodeGenInfo {
2303 PS4TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2304 : X86_64TargetCodeGenInfo(CGT, AVXLevel) {}
2306 void getDependentLibraryOption(llvm::StringRef Lib,
2307 llvm::SmallString<24> &Opt) const override {
2309 // If the argument contains a space, enclose it in quotes.
2310 if (Lib.find(" ") != StringRef::npos)
2311 Opt += "\"" + Lib.str() + "\"";
2317 static std::string qualifyWindowsLibrary(llvm::StringRef Lib) {
2318 // If the argument does not end in .lib, automatically add the suffix.
2319 // If the argument contains a space, enclose it in quotes.
2320 // This matches the behavior of MSVC.
2321 bool Quote = (Lib.find(" ") != StringRef::npos);
2322 std::string ArgStr = Quote ? "\"" : "";
2324 if (!Lib.endswith_lower(".lib"))
2326 ArgStr += Quote ? "\"" : "";
2330 class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
2332 WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2333 bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
2334 unsigned NumRegisterParameters)
2335 : X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
2336 Win32StructABI, NumRegisterParameters, false) {}
2338 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2339 CodeGen::CodeGenModule &CGM,
2340 ForDefinition_t IsForDefinition) const override;
2342 void getDependentLibraryOption(llvm::StringRef Lib,
2343 llvm::SmallString<24> &Opt) const override {
2344 Opt = "/DEFAULTLIB:";
2345 Opt += qualifyWindowsLibrary(Lib);
2348 void getDetectMismatchOption(llvm::StringRef Name,
2349 llvm::StringRef Value,
2350 llvm::SmallString<32> &Opt) const override {
2351 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2355 static void addStackProbeSizeTargetAttribute(const Decl *D,
2356 llvm::GlobalValue *GV,
2357 CodeGen::CodeGenModule &CGM) {
2358 if (D && isa<FunctionDecl>(D)) {
2359 if (CGM.getCodeGenOpts().StackProbeSize != 4096) {
2360 llvm::Function *Fn = cast<llvm::Function>(GV);
2362 Fn->addFnAttr("stack-probe-size",
2363 llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
2368 void WinX86_32TargetCodeGenInfo::setTargetAttributes(
2369 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM,
2370 ForDefinition_t IsForDefinition) const {
2371 X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM, IsForDefinition);
2372 if (!IsForDefinition)
2374 addStackProbeSizeTargetAttribute(D, GV, CGM);
2377 class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2379 WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2380 X86AVXABILevel AVXLevel)
2381 : TargetCodeGenInfo(new WinX86_64ABIInfo(CGT)) {}
2383 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2384 CodeGen::CodeGenModule &CGM,
2385 ForDefinition_t IsForDefinition) const override;
2387 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2391 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2392 llvm::Value *Address) const override {
2393 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2395 // 0-15 are the 16 integer registers.
2397 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2401 void getDependentLibraryOption(llvm::StringRef Lib,
2402 llvm::SmallString<24> &Opt) const override {
2403 Opt = "/DEFAULTLIB:";
2404 Opt += qualifyWindowsLibrary(Lib);
2407 void getDetectMismatchOption(llvm::StringRef Name,
2408 llvm::StringRef Value,
2409 llvm::SmallString<32> &Opt) const override {
2410 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2414 void WinX86_64TargetCodeGenInfo::setTargetAttributes(
2415 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM,
2416 ForDefinition_t IsForDefinition) const {
2417 TargetCodeGenInfo::setTargetAttributes(D, GV, CGM, IsForDefinition);
2418 if (!IsForDefinition)
2420 if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2421 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2422 llvm::Function *Fn = cast<llvm::Function>(GV);
2423 Fn->addFnAttr("stackrealign");
2425 if (FD->hasAttr<AnyX86InterruptAttr>()) {
2426 llvm::Function *Fn = cast<llvm::Function>(GV);
2427 Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2431 addStackProbeSizeTargetAttribute(D, GV, CGM);
2435 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
2437 // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
2439 // (a) If one of the classes is Memory, the whole argument is passed in
2442 // (b) If X87UP is not preceded by X87, the whole argument is passed in
2445 // (c) If the size of the aggregate exceeds two eightbytes and the first
2446 // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
2447 // argument is passed in memory. NOTE: This is necessary to keep the
2448 // ABI working for processors that don't support the __m256 type.
2450 // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
2452 // Some of these are enforced by the merging logic. Others can arise
2453 // only with unions; for example:
2454 // union { _Complex double; unsigned; }
2456 // Note that clauses (b) and (c) were added in 0.98.
2460 if (Hi == X87Up && Lo != X87 && honorsRevision0_98())
2462 if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp))
2464 if (Hi == SSEUp && Lo != SSE)
2468 X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) {
2469 // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
2470 // classified recursively so that always two fields are
2471 // considered. The resulting class is calculated according to
2472 // the classes of the fields in the eightbyte:
2474 // (a) If both classes are equal, this is the resulting class.
2476 // (b) If one of the classes is NO_CLASS, the resulting class is
2479 // (c) If one of the classes is MEMORY, the result is the MEMORY
2482 // (d) If one of the classes is INTEGER, the result is the
2485 // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class,
2486 // MEMORY is used as class.
2488 // (f) Otherwise class SSE is used.
2490 // Accum should never be memory (we should have returned) or
2491 // ComplexX87 (because this cannot be passed in a structure).
2492 assert((Accum != Memory && Accum != ComplexX87) &&
2493 "Invalid accumulated classification during merge.");
2494 if (Accum == Field || Field == NoClass)
2496 if (Field == Memory)
2498 if (Accum == NoClass)
2500 if (Accum == Integer || Field == Integer)
2502 if (Field == X87 || Field == X87Up || Field == ComplexX87 ||
2503 Accum == X87 || Accum == X87Up)
2508 void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase,
2509 Class &Lo, Class &Hi, bool isNamedArg) const {
2510 // FIXME: This code can be simplified by introducing a simple value class for
2511 // Class pairs with appropriate constructor methods for the various
2514 // FIXME: Some of the split computations are wrong; unaligned vectors
2515 // shouldn't be passed in registers for example, so there is no chance they
2516 // can straddle an eightbyte. Verify & simplify.
2520 Class &Current = OffsetBase < 64 ? Lo : Hi;
2523 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
2524 BuiltinType::Kind k = BT->getKind();
2526 if (k == BuiltinType::Void) {
2528 } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) {
2531 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
2533 } else if (k == BuiltinType::Float || k == BuiltinType::Double) {
2535 } else if (k == BuiltinType::LongDouble) {
2536 const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2537 if (LDF == &llvm::APFloat::IEEEquad()) {
2540 } else if (LDF == &llvm::APFloat::x87DoubleExtended()) {
2543 } else if (LDF == &llvm::APFloat::IEEEdouble()) {
2546 llvm_unreachable("unexpected long double representation!");
2548 // FIXME: _Decimal32 and _Decimal64 are SSE.
2549 // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
2553 if (const EnumType *ET = Ty->getAs<EnumType>()) {
2554 // Classify the underlying integer type.
2555 classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
2559 if (Ty->hasPointerRepresentation()) {
2564 if (Ty->isMemberPointerType()) {
2565 if (Ty->isMemberFunctionPointerType()) {
2566 if (Has64BitPointers) {
2567 // If Has64BitPointers, this is an {i64, i64}, so classify both
2571 // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
2572 // straddles an eightbyte boundary, Hi should be classified as well.
2573 uint64_t EB_FuncPtr = (OffsetBase) / 64;
2574 uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
2575 if (EB_FuncPtr != EB_ThisAdj) {
2587 if (const VectorType *VT = Ty->getAs<VectorType>()) {
2588 uint64_t Size = getContext().getTypeSize(VT);
2589 if (Size == 1 || Size == 8 || Size == 16 || Size == 32) {
2590 // gcc passes the following as integer:
2591 // 4 bytes - <4 x char>, <2 x short>, <1 x int>, <1 x float>
2592 // 2 bytes - <2 x char>, <1 x short>
2593 // 1 byte - <1 x char>
2596 // If this type crosses an eightbyte boundary, it should be
2598 uint64_t EB_Lo = (OffsetBase) / 64;
2599 uint64_t EB_Hi = (OffsetBase + Size - 1) / 64;
2602 } else if (Size == 64) {
2603 QualType ElementType = VT->getElementType();
2605 // gcc passes <1 x double> in memory. :(
2606 if (ElementType->isSpecificBuiltinType(BuiltinType::Double))
2609 // gcc passes <1 x long long> as SSE but clang used to unconditionally
2610 // pass them as integer. For platforms where clang is the de facto
2611 // platform compiler, we must continue to use integer.
2612 if (!classifyIntegerMMXAsSSE() &&
2613 (ElementType->isSpecificBuiltinType(BuiltinType::LongLong) ||
2614 ElementType->isSpecificBuiltinType(BuiltinType::ULongLong) ||
2615 ElementType->isSpecificBuiltinType(BuiltinType::Long) ||
2616 ElementType->isSpecificBuiltinType(BuiltinType::ULong)))
2621 // If this type crosses an eightbyte boundary, it should be
2623 if (OffsetBase && OffsetBase != 64)
2625 } else if (Size == 128 ||
2626 (isNamedArg && Size <= getNativeVectorSizeForAVXABI(AVXLevel))) {
2627 // Arguments of 256-bits are split into four eightbyte chunks. The
2628 // least significant one belongs to class SSE and all the others to class
2629 // SSEUP. The original Lo and Hi design considers that types can't be
2630 // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
2631 // This design isn't correct for 256-bits, but since there're no cases
2632 // where the upper parts would need to be inspected, avoid adding
2633 // complexity and just consider Hi to match the 64-256 part.
2635 // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
2636 // registers if they are "named", i.e. not part of the "..." of a
2637 // variadic function.
2639 // Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are
2640 // split into eight eightbyte chunks, one SSE and seven SSEUP.
2647 if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
2648 QualType ET = getContext().getCanonicalType(CT->getElementType());
2650 uint64_t Size = getContext().getTypeSize(Ty);
2651 if (ET->isIntegralOrEnumerationType()) {
2654 else if (Size <= 128)
2656 } else if (ET == getContext().FloatTy) {
2658 } else if (ET == getContext().DoubleTy) {
2660 } else if (ET == getContext().LongDoubleTy) {
2661 const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2662 if (LDF == &llvm::APFloat::IEEEquad())
2664 else if (LDF == &llvm::APFloat::x87DoubleExtended())
2665 Current = ComplexX87;
2666 else if (LDF == &llvm::APFloat::IEEEdouble())
2669 llvm_unreachable("unexpected long double representation!");
2672 // If this complex type crosses an eightbyte boundary then it
2674 uint64_t EB_Real = (OffsetBase) / 64;
2675 uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64;
2676 if (Hi == NoClass && EB_Real != EB_Imag)
2682 if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
2683 // Arrays are treated like structures.
2685 uint64_t Size = getContext().getTypeSize(Ty);
2687 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2688 // than eight eightbytes, ..., it has class MEMORY.
2692 // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
2693 // fields, it has class MEMORY.
2695 // Only need to check alignment of array base.
2696 if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
2699 // Otherwise implement simplified merge. We could be smarter about
2700 // this, but it isn't worth it and would be harder to verify.
2702 uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
2703 uint64_t ArraySize = AT->getSize().getZExtValue();
2705 // The only case a 256-bit wide vector could be used is when the array
2706 // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2707 // to work for sizes wider than 128, early check and fallback to memory.
2710 (Size != EltSize || Size > getNativeVectorSizeForAVXABI(AVXLevel)))
2713 for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) {
2714 Class FieldLo, FieldHi;
2715 classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
2716 Lo = merge(Lo, FieldLo);
2717 Hi = merge(Hi, FieldHi);
2718 if (Lo == Memory || Hi == Memory)
2722 postMerge(Size, Lo, Hi);
2723 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
2727 if (const RecordType *RT = Ty->getAs<RecordType>()) {
2728 uint64_t Size = getContext().getTypeSize(Ty);
2730 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2731 // than eight eightbytes, ..., it has class MEMORY.
2735 // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
2736 // copy constructor or a non-trivial destructor, it is passed by invisible
2738 if (getRecordArgABI(RT, getCXXABI()))
2741 const RecordDecl *RD = RT->getDecl();
2743 // Assume variable sized types are passed in memory.
2744 if (RD->hasFlexibleArrayMember())
2747 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
2749 // Reset Lo class, this will be recomputed.
2752 // If this is a C++ record, classify the bases first.
2753 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2754 for (const auto &I : CXXRD->bases()) {
2755 assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2756 "Unexpected base class!");
2757 const CXXRecordDecl *Base =
2758 cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
2760 // Classify this field.
2762 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
2763 // single eightbyte, each is classified separately. Each eightbyte gets
2764 // initialized to class NO_CLASS.
2765 Class FieldLo, FieldHi;
2767 OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base));
2768 classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
2769 Lo = merge(Lo, FieldLo);
2770 Hi = merge(Hi, FieldHi);
2771 if (Lo == Memory || Hi == Memory) {
2772 postMerge(Size, Lo, Hi);
2778 // Classify the fields one at a time, merging the results.
2780 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2781 i != e; ++i, ++idx) {
2782 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2783 bool BitField = i->isBitField();
2785 // Ignore padding bit-fields.
2786 if (BitField && i->isUnnamedBitfield())
2789 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
2790 // four eightbytes, or it contains unaligned fields, it has class MEMORY.
2792 // The only case a 256-bit wide vector could be used is when the struct
2793 // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2794 // to work for sizes wider than 128, early check and fallback to memory.
2796 if (Size > 128 && (Size != getContext().getTypeSize(i->getType()) ||
2797 Size > getNativeVectorSizeForAVXABI(AVXLevel))) {
2799 postMerge(Size, Lo, Hi);
2802 // Note, skip this test for bit-fields, see below.
2803 if (!BitField && Offset % getContext().getTypeAlign(i->getType())) {
2805 postMerge(Size, Lo, Hi);
2809 // Classify this field.
2811 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
2812 // exceeds a single eightbyte, each is classified
2813 // separately. Each eightbyte gets initialized to class
2815 Class FieldLo, FieldHi;
2817 // Bit-fields require special handling, they do not force the
2818 // structure to be passed in memory even if unaligned, and
2819 // therefore they can straddle an eightbyte.
2821 assert(!i->isUnnamedBitfield());
2822 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2823 uint64_t Size = i->getBitWidthValue(getContext());
2825 uint64_t EB_Lo = Offset / 64;
2826 uint64_t EB_Hi = (Offset + Size - 1) / 64;
2829 assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes.");
2834 FieldHi = EB_Hi ? Integer : NoClass;
2837 classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
2838 Lo = merge(Lo, FieldLo);
2839 Hi = merge(Hi, FieldHi);
2840 if (Lo == Memory || Hi == Memory)
2844 postMerge(Size, Lo, Hi);
2848 ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const {
2849 // If this is a scalar LLVM value then assume LLVM will pass it in the right
2851 if (!isAggregateTypeForABI(Ty)) {
2852 // Treat an enum type as its underlying type.
2853 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2854 Ty = EnumTy->getDecl()->getIntegerType();
2856 return (Ty->isPromotableIntegerType() ?
2857 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
2860 return getNaturalAlignIndirect(Ty);
2863 bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const {
2864 if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
2865 uint64_t Size = getContext().getTypeSize(VecTy);
2866 unsigned LargestVector = getNativeVectorSizeForAVXABI(AVXLevel);
2867 if (Size <= 64 || Size > LargestVector)
2874 ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty,
2875 unsigned freeIntRegs) const {
2876 // If this is a scalar LLVM value then assume LLVM will pass it in the right
2879 // This assumption is optimistic, as there could be free registers available
2880 // when we need to pass this argument in memory, and LLVM could try to pass
2881 // the argument in the free register. This does not seem to happen currently,
2882 // but this code would be much safer if we could mark the argument with
2883 // 'onstack'. See PR12193.
2884 if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty)) {
2885 // Treat an enum type as its underlying type.
2886 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2887 Ty = EnumTy->getDecl()->getIntegerType();
2889 return (Ty->isPromotableIntegerType() ?
2890 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
2893 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
2894 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
2896 // Compute the byval alignment. We specify the alignment of the byval in all
2897 // cases so that the mid-level optimizer knows the alignment of the byval.
2898 unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U);
2900 // Attempt to avoid passing indirect results using byval when possible. This
2901 // is important for good codegen.
2903 // We do this by coercing the value into a scalar type which the backend can
2904 // handle naturally (i.e., without using byval).
2906 // For simplicity, we currently only do this when we have exhausted all of the
2907 // free integer registers. Doing this when there are free integer registers
2908 // would require more care, as we would have to ensure that the coerced value
2909 // did not claim the unused register. That would require either reording the
2910 // arguments to the function (so that any subsequent inreg values came first),
2911 // or only doing this optimization when there were no following arguments that
2914 // We currently expect it to be rare (particularly in well written code) for
2915 // arguments to be passed on the stack when there are still free integer
2916 // registers available (this would typically imply large structs being passed
2917 // by value), so this seems like a fair tradeoff for now.
2919 // We can revisit this if the backend grows support for 'onstack' parameter
2920 // attributes. See PR12193.
2921 if (freeIntRegs == 0) {
2922 uint64_t Size = getContext().getTypeSize(Ty);
2924 // If this type fits in an eightbyte, coerce it into the matching integral
2925 // type, which will end up on the stack (with alignment 8).
2926 if (Align == 8 && Size <= 64)
2927 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
2931 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align));
2934 /// The ABI specifies that a value should be passed in a full vector XMM/YMM
2935 /// register. Pick an LLVM IR type that will be passed as a vector register.
2936 llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const {
2937 // Wrapper structs/arrays that only contain vectors are passed just like
2938 // vectors; strip them off if present.
2939 if (const Type *InnerTy = isSingleElementStruct(Ty, getContext()))
2940 Ty = QualType(InnerTy, 0);
2942 llvm::Type *IRType = CGT.ConvertType(Ty);
2943 if (isa<llvm::VectorType>(IRType) ||
2944 IRType->getTypeID() == llvm::Type::FP128TyID)
2947 // We couldn't find the preferred IR vector type for 'Ty'.
2948 uint64_t Size = getContext().getTypeSize(Ty);
2949 assert((Size == 128 || Size == 256 || Size == 512) && "Invalid type found!");
2951 // Return a LLVM IR vector type based on the size of 'Ty'.
2952 return llvm::VectorType::get(llvm::Type::getDoubleTy(getVMContext()),
2956 /// BitsContainNoUserData - Return true if the specified [start,end) bit range
2957 /// is known to either be off the end of the specified type or being in
2958 /// alignment padding. The user type specified is known to be at most 128 bits
2959 /// in size, and have passed through X86_64ABIInfo::classify with a successful
2960 /// classification that put one of the two halves in the INTEGER class.
2962 /// It is conservatively correct to return false.
2963 static bool BitsContainNoUserData(QualType Ty, unsigned StartBit,
2964 unsigned EndBit, ASTContext &Context) {
2965 // If the bytes being queried are off the end of the type, there is no user
2966 // data hiding here. This handles analysis of builtins, vectors and other
2967 // types that don't contain interesting padding.
2968 unsigned TySize = (unsigned)Context.getTypeSize(Ty);
2969 if (TySize <= StartBit)
2972 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) {
2973 unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
2974 unsigned NumElts = (unsigned)AT->getSize().getZExtValue();
2976 // Check each element to see if the element overlaps with the queried range.
2977 for (unsigned i = 0; i != NumElts; ++i) {
2978 // If the element is after the span we care about, then we're done..
2979 unsigned EltOffset = i*EltSize;
2980 if (EltOffset >= EndBit) break;
2982 unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0;
2983 if (!BitsContainNoUserData(AT->getElementType(), EltStart,
2984 EndBit-EltOffset, Context))
2987 // If it overlaps no elements, then it is safe to process as padding.
2991 if (const RecordType *RT = Ty->getAs<RecordType>()) {
2992 const RecordDecl *RD = RT->getDecl();
2993 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
2995 // If this is a C++ record, check the bases first.
2996 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2997 for (const auto &I : CXXRD->bases()) {
2998 assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2999 "Unexpected base class!");
3000 const CXXRecordDecl *Base =
3001 cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
3003 // If the base is after the span we care about, ignore it.
3004 unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base));
3005 if (BaseOffset >= EndBit) continue;
3007 unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0;
3008 if (!BitsContainNoUserData(I.getType(), BaseStart,
3009 EndBit-BaseOffset, Context))
3014 // Verify that no field has data that overlaps the region of interest. Yes
3015 // this could be sped up a lot by being smarter about queried fields,
3016 // however we're only looking at structs up to 16 bytes, so we don't care
3019 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
3020 i != e; ++i, ++idx) {
3021 unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx);
3023 // If we found a field after the region we care about, then we're done.
3024 if (FieldOffset >= EndBit) break;
3026 unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0;
3027 if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
3032 // If nothing in this record overlapped the area of interest, then we're
3040 /// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a
3041 /// float member at the specified offset. For example, {int,{float}} has a
3042 /// float at offset 4. It is conservatively correct for this routine to return
3044 static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset,
3045 const llvm::DataLayout &TD) {
3046 // Base case if we find a float.
3047 if (IROffset == 0 && IRType->isFloatTy())
3050 // If this is a struct, recurse into the field at the specified offset.
3051 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3052 const llvm::StructLayout *SL = TD.getStructLayout(STy);
3053 unsigned Elt = SL->getElementContainingOffset(IROffset);
3054 IROffset -= SL->getElementOffset(Elt);
3055 return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD);
3058 // If this is an array, recurse into the field at the specified offset.
3059 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3060 llvm::Type *EltTy = ATy->getElementType();
3061 unsigned EltSize = TD.getTypeAllocSize(EltTy);
3062 IROffset -= IROffset/EltSize*EltSize;
3063 return ContainsFloatAtOffset(EltTy, IROffset, TD);
3070 /// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
3071 /// low 8 bytes of an XMM register, corresponding to the SSE class.
3072 llvm::Type *X86_64ABIInfo::
3073 GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3074 QualType SourceTy, unsigned SourceOffset) const {
3075 // The only three choices we have are either double, <2 x float>, or float. We
3076 // pass as float if the last 4 bytes is just padding. This happens for
3077 // structs that contain 3 floats.
3078 if (BitsContainNoUserData(SourceTy, SourceOffset*8+32,
3079 SourceOffset*8+64, getContext()))
3080 return llvm::Type::getFloatTy(getVMContext());
3082 // We want to pass as <2 x float> if the LLVM IR type contains a float at
3083 // offset+0 and offset+4. Walk the LLVM IR type to find out if this is the
3085 if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) &&
3086 ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout()))
3087 return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2);
3089 return llvm::Type::getDoubleTy(getVMContext());
3093 /// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
3094 /// an 8-byte GPR. This means that we either have a scalar or we are talking
3095 /// about the high or low part of an up-to-16-byte struct. This routine picks
3096 /// the best LLVM IR type to represent this, which may be i64 or may be anything
3097 /// else that the backend will pass in a GPR that works better (e.g. i8, %foo*,
3100 /// PrefType is an LLVM IR type that corresponds to (part of) the IR type for
3101 /// the source type. IROffset is an offset in bytes into the LLVM IR type that
3102 /// the 8-byte value references. PrefType may be null.
3104 /// SourceTy is the source-level type for the entire argument. SourceOffset is
3105 /// an offset into this that we're processing (which is always either 0 or 8).
3107 llvm::Type *X86_64ABIInfo::
3108 GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3109 QualType SourceTy, unsigned SourceOffset) const {
3110 // If we're dealing with an un-offset LLVM IR type, then it means that we're
3111 // returning an 8-byte unit starting with it. See if we can safely use it.
3112 if (IROffset == 0) {
3113 // Pointers and int64's always fill the 8-byte unit.
3114 if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) ||
3115 IRType->isIntegerTy(64))
3118 // If we have a 1/2/4-byte integer, we can use it only if the rest of the
3119 // goodness in the source type is just tail padding. This is allowed to
3120 // kick in for struct {double,int} on the int, but not on
3121 // struct{double,int,int} because we wouldn't return the second int. We
3122 // have to do this analysis on the source type because we can't depend on
3123 // unions being lowered a specific way etc.
3124 if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) ||
3125 IRType->isIntegerTy(32) ||
3126 (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) {
3127 unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 :
3128 cast<llvm::IntegerType>(IRType)->getBitWidth();
3130 if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth,
3131 SourceOffset*8+64, getContext()))
3136 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3137 // If this is a struct, recurse into the field at the specified offset.
3138 const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy);
3139 if (IROffset < SL->getSizeInBytes()) {
3140 unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
3141 IROffset -= SL->getElementOffset(FieldIdx);
3143 return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
3144 SourceTy, SourceOffset);
3148 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3149 llvm::Type *EltTy = ATy->getElementType();
3150 unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
3151 unsigned EltOffset = IROffset/EltSize*EltSize;
3152 return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
3156 // Okay, we don't have any better idea of what to pass, so we pass this in an
3157 // integer register that isn't too big to fit the rest of the struct.
3158 unsigned TySizeInBytes =
3159 (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity();
3161 assert(TySizeInBytes != SourceOffset && "Empty field?");
3163 // It is always safe to classify this as an integer type up to i64 that
3164 // isn't larger than the structure.
3165 return llvm::IntegerType::get(getVMContext(),
3166 std::min(TySizeInBytes-SourceOffset, 8U)*8);
3170 /// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
3171 /// be used as elements of a two register pair to pass or return, return a
3172 /// first class aggregate to represent them. For example, if the low part of
3173 /// a by-value argument should be passed as i32* and the high part as float,
3174 /// return {i32*, float}.
3176 GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi,
3177 const llvm::DataLayout &TD) {
3178 // In order to correctly satisfy the ABI, we need to the high part to start
3179 // at offset 8. If the high and low parts we inferred are both 4-byte types
3180 // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have
3181 // the second element at offset 8. Check for this:
3182 unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo);
3183 unsigned HiAlign = TD.getABITypeAlignment(Hi);
3184 unsigned HiStart = llvm::alignTo(LoSize, HiAlign);
3185 assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!");
3187 // To handle this, we have to increase the size of the low part so that the
3188 // second element will start at an 8 byte offset. We can't increase the size
3189 // of the second element because it might make us access off the end of the
3192 // There are usually two sorts of types the ABI generation code can produce
3193 // for the low part of a pair that aren't 8 bytes in size: float or
3194 // i8/i16/i32. This can also include pointers when they are 32-bit (X32 and
3196 // Promote these to a larger type.
3197 if (Lo->isFloatTy())
3198 Lo = llvm::Type::getDoubleTy(Lo->getContext());
3200 assert((Lo->isIntegerTy() || Lo->isPointerTy())
3201 && "Invalid/unknown lo type");
3202 Lo = llvm::Type::getInt64Ty(Lo->getContext());
3206 llvm::StructType *Result = llvm::StructType::get(Lo, Hi);
3208 // Verify that the second element is at an 8-byte offset.
3209 assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
3210 "Invalid x86-64 argument pair!");
3214 ABIArgInfo X86_64ABIInfo::
3215 classifyReturnType(QualType RetTy) const {
3216 // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
3217 // classification algorithm.
3218 X86_64ABIInfo::Class Lo, Hi;
3219 classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);
3221 // Check some invariants.
3222 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3223 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3225 llvm::Type *ResType = nullptr;
3229 return ABIArgInfo::getIgnore();
3230 // If the low part is just padding, it takes no register, leave ResType
3232 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3233 "Unknown missing lo part");
3238 llvm_unreachable("Invalid classification for lo word.");
3240 // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
3243 return getIndirectReturnResult(RetTy);
3245 // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
3246 // available register of the sequence %rax, %rdx is used.
3248 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3250 // If we have a sign or zero extended integer, make sure to return Extend
3251 // so that the parameter gets the right LLVM IR attributes.
3252 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3253 // Treat an enum type as its underlying type.
3254 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
3255 RetTy = EnumTy->getDecl()->getIntegerType();
3257 if (RetTy->isIntegralOrEnumerationType() &&
3258 RetTy->isPromotableIntegerType())
3259 return ABIArgInfo::getExtend();
3263 // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
3264 // available SSE register of the sequence %xmm0, %xmm1 is used.
3266 ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3269 // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
3270 // returned on the X87 stack in %st0 as 80-bit x87 number.
3272 ResType = llvm::Type::getX86_FP80Ty(getVMContext());
3275 // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
3276 // part of the value is returned in %st0 and the imaginary part in
3279 assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.");
3280 ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()),
3281 llvm::Type::getX86_FP80Ty(getVMContext()));
3285 llvm::Type *HighPart = nullptr;
3287 // Memory was handled previously and X87 should
3288 // never occur as a hi class.
3291 llvm_unreachable("Invalid classification for hi word.");
3293 case ComplexX87: // Previously handled.
3298 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3299 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3300 return ABIArgInfo::getDirect(HighPart, 8);
3303 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3304 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3305 return ABIArgInfo::getDirect(HighPart, 8);
3308 // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
3309 // is passed in the next available eightbyte chunk if the last used
3312 // SSEUP should always be preceded by SSE, just widen.
3314 assert(Lo == SSE && "Unexpected SSEUp classification.");
3315 ResType = GetByteVectorType(RetTy);
3318 // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
3319 // returned together with the previous X87 value in %st0.
3321 // If X87Up is preceded by X87, we don't need to do
3322 // anything. However, in some cases with unions it may not be
3323 // preceded by X87. In such situations we follow gcc and pass the
3324 // extra bits in an SSE reg.
3326 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3327 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3328 return ABIArgInfo::getDirect(HighPart, 8);
3333 // If a high part was specified, merge it together with the low part. It is
3334 // known to pass in the high eightbyte of the result. We do this by forming a
3335 // first class struct aggregate with the high and low part: {low, high}
3337 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3339 return ABIArgInfo::getDirect(ResType);
3342 ABIArgInfo X86_64ABIInfo::classifyArgumentType(
3343 QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE,
3347 Ty = useFirstFieldIfTransparentUnion(Ty);
3349 X86_64ABIInfo::Class Lo, Hi;
3350 classify(Ty, 0, Lo, Hi, isNamedArg);
3352 // Check some invariants.
3353 // FIXME: Enforce these by construction.
3354 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3355 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3359 llvm::Type *ResType = nullptr;
3363 return ABIArgInfo::getIgnore();
3364 // If the low part is just padding, it takes no register, leave ResType
3366 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3367 "Unknown missing lo part");
3370 // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
3374 // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
3375 // COMPLEX_X87, it is passed in memory.
3378 if (getRecordArgABI(Ty, getCXXABI()) == CGCXXABI::RAA_Indirect)
3380 return getIndirectResult(Ty, freeIntRegs);
3384 llvm_unreachable("Invalid classification for lo word.");
3386 // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
3387 // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
3392 // Pick an 8-byte type based on the preferred type.
3393 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);
3395 // If we have a sign or zero extended integer, make sure to return Extend
3396 // so that the parameter gets the right LLVM IR attributes.
3397 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3398 // Treat an enum type as its underlying type.
3399 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3400 Ty = EnumTy->getDecl()->getIntegerType();
3402 if (Ty->isIntegralOrEnumerationType() &&
3403 Ty->isPromotableIntegerType())
3404 return ABIArgInfo::getExtend();
3409 // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
3410 // available SSE register is used, the registers are taken in the
3411 // order from %xmm0 to %xmm7.
3413 llvm::Type *IRType = CGT.ConvertType(Ty);
3414 ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);
3420 llvm::Type *HighPart = nullptr;
3422 // Memory was handled previously, ComplexX87 and X87 should
3423 // never occur as hi classes, and X87Up must be preceded by X87,
3424 // which is passed in memory.
3428 llvm_unreachable("Invalid classification for hi word.");
3430 case NoClass: break;
3434 // Pick an 8-byte type based on the preferred type.
3435 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3437 if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3438 return ABIArgInfo::getDirect(HighPart, 8);
3441 // X87Up generally doesn't occur here (long double is passed in
3442 // memory), except in situations involving unions.
3445 HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3447 if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3448 return ABIArgInfo::getDirect(HighPart, 8);
3453 // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
3454 // eightbyte is passed in the upper half of the last used SSE
3455 // register. This only happens when 128-bit vectors are passed.
3457 assert(Lo == SSE && "Unexpected SSEUp classification");
3458 ResType = GetByteVectorType(Ty);
3462 // If a high part was specified, merge it together with the low part. It is
3463 // known to pass in the high eightbyte of the result. We do this by forming a
3464 // first class struct aggregate with the high and low part: {low, high}
3466 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3468 return ABIArgInfo::getDirect(ResType);
3472 X86_64ABIInfo::classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
3473 unsigned &NeededSSE) const {
3474 auto RT = Ty->getAs<RecordType>();
3475 assert(RT && "classifyRegCallStructType only valid with struct types");
3477 if (RT->getDecl()->hasFlexibleArrayMember())
3478 return getIndirectReturnResult(Ty);
3481 if (auto CXXRD = dyn_cast<CXXRecordDecl>(RT->getDecl())) {
3482 if (CXXRD->isDynamicClass()) {
3483 NeededInt = NeededSSE = 0;
3484 return getIndirectReturnResult(Ty);
3487 for (const auto &I : CXXRD->bases())
3488 if (classifyRegCallStructTypeImpl(I.getType(), NeededInt, NeededSSE)
3490 NeededInt = NeededSSE = 0;
3491 return getIndirectReturnResult(Ty);
3496 for (const auto *FD : RT->getDecl()->fields()) {
3497 if (FD->getType()->isRecordType() && !FD->getType()->isUnionType()) {
3498 if (classifyRegCallStructTypeImpl(FD->getType(), NeededInt, NeededSSE)
3500 NeededInt = NeededSSE = 0;
3501 return getIndirectReturnResult(Ty);
3504 unsigned LocalNeededInt, LocalNeededSSE;
3505 if (classifyArgumentType(FD->getType(), UINT_MAX, LocalNeededInt,
3506 LocalNeededSSE, true)
3508 NeededInt = NeededSSE = 0;
3509 return getIndirectReturnResult(Ty);
3511 NeededInt += LocalNeededInt;
3512 NeededSSE += LocalNeededSSE;
3516 return ABIArgInfo::getDirect();
3519 ABIArgInfo X86_64ABIInfo::classifyRegCallStructType(QualType Ty,
3520 unsigned &NeededInt,
3521 unsigned &NeededSSE) const {
3526 return classifyRegCallStructTypeImpl(Ty, NeededInt, NeededSSE);
3529 void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3531 const unsigned CallingConv = FI.getCallingConvention();
3532 // It is possible to force Win64 calling convention on any x86_64 target by
3533 // using __attribute__((ms_abi)). In such case to correctly emit Win64
3534 // compatible code delegate this call to WinX86_64ABIInfo::computeInfo.
3535 if (CallingConv == llvm::CallingConv::Win64) {
3536 WinX86_64ABIInfo Win64ABIInfo(CGT);
3537 Win64ABIInfo.computeInfo(FI);
3541 bool IsRegCall = CallingConv == llvm::CallingConv::X86_RegCall;
3543 // Keep track of the number of assigned registers.
3544 unsigned FreeIntRegs = IsRegCall ? 11 : 6;
3545 unsigned FreeSSERegs = IsRegCall ? 16 : 8;
3546 unsigned NeededInt, NeededSSE;
3548 if (!getCXXABI().classifyReturnType(FI)) {
3549 if (IsRegCall && FI.getReturnType()->getTypePtr()->isRecordType() &&
3550 !FI.getReturnType()->getTypePtr()->isUnionType()) {
3551 FI.getReturnInfo() =
3552 classifyRegCallStructType(FI.getReturnType(), NeededInt, NeededSSE);
3553 if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3554 FreeIntRegs -= NeededInt;
3555 FreeSSERegs -= NeededSSE;
3557 FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3559 } else if (IsRegCall && FI.getReturnType()->getAs<ComplexType>()) {
3560 // Complex Long Double Type is passed in Memory when Regcall
3561 // calling convention is used.
3562 const ComplexType *CT = FI.getReturnType()->getAs<ComplexType>();
3563 if (getContext().getCanonicalType(CT->getElementType()) ==
3564 getContext().LongDoubleTy)
3565 FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3567 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
3570 // If the return value is indirect, then the hidden argument is consuming one
3571 // integer register.
3572 if (FI.getReturnInfo().isIndirect())
3575 // The chain argument effectively gives us another free register.
3576 if (FI.isChainCall())
3579 unsigned NumRequiredArgs = FI.getNumRequiredArgs();
3580 // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
3581 // get assigned (in left-to-right order) for passing as follows...
3583 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
3584 it != ie; ++it, ++ArgNo) {
3585 bool IsNamedArg = ArgNo < NumRequiredArgs;
3587 if (IsRegCall && it->type->isStructureOrClassType())
3588 it->info = classifyRegCallStructType(it->type, NeededInt, NeededSSE);
3590 it->info = classifyArgumentType(it->type, FreeIntRegs, NeededInt,
3591 NeededSSE, IsNamedArg);
3593 // AMD64-ABI 3.2.3p3: If there are no registers available for any
3594 // eightbyte of an argument, the whole argument is passed on the
3595 // stack. If registers have already been assigned for some
3596 // eightbytes of such an argument, the assignments get reverted.
3597 if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3598 FreeIntRegs -= NeededInt;
3599 FreeSSERegs -= NeededSSE;
3601 it->info = getIndirectResult(it->type, FreeIntRegs);
3606 static Address EmitX86_64VAArgFromMemory(CodeGenFunction &CGF,
3607 Address VAListAddr, QualType Ty) {
3608 Address overflow_arg_area_p = CGF.Builder.CreateStructGEP(
3609 VAListAddr, 2, CharUnits::fromQuantity(8), "overflow_arg_area_p");
3610 llvm::Value *overflow_arg_area =
3611 CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area");
3613 // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
3614 // byte boundary if alignment needed by type exceeds 8 byte boundary.
3615 // It isn't stated explicitly in the standard, but in practice we use
3616 // alignment greater than 16 where necessary.
3617 CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
3618 if (Align > CharUnits::fromQuantity(8)) {
3619 overflow_arg_area = emitRoundPointerUpToAlignment(CGF, overflow_arg_area,
3623 // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
3624 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3626 CGF.Builder.CreateBitCast(overflow_arg_area,
3627 llvm::PointerType::getUnqual(LTy));
3629 // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
3630 // l->overflow_arg_area + sizeof(type).
3631 // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
3632 // an 8 byte boundary.
3634 uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8;
3635 llvm::Value *Offset =
3636 llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7);
3637 overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset,
3638 "overflow_arg_area.next");
3639 CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);
3641 // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
3642 return Address(Res, Align);
3645 Address X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3646 QualType Ty) const {
3647 // Assume that va_list type is correct; should be pointer to LLVM type:
3651 // i8* overflow_arg_area;
3652 // i8* reg_save_area;
3654 unsigned neededInt, neededSSE;
3656 Ty = getContext().getCanonicalType(Ty);
3657 ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
3658 /*isNamedArg*/false);
3660 // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
3661 // in the registers. If not go to step 7.
3662 if (!neededInt && !neededSSE)
3663 return EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3665 // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
3666 // general purpose registers needed to pass type and num_fp to hold
3667 // the number of floating point registers needed.
3669 // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
3670 // registers. In the case: l->gp_offset > 48 - num_gp * 8 or
3671 // l->fp_offset > 304 - num_fp * 16 go to step 7.
3673 // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of
3674 // register save space).
3676 llvm::Value *InRegs = nullptr;
3677 Address gp_offset_p = Address::invalid(), fp_offset_p = Address::invalid();
3678 llvm::Value *gp_offset = nullptr, *fp_offset = nullptr;
3681 CGF.Builder.CreateStructGEP(VAListAddr, 0, CharUnits::Zero(),
3683 gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset");
3684 InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
3685 InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp");
3690 CGF.Builder.CreateStructGEP(VAListAddr, 1, CharUnits::fromQuantity(4),
3692 fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset");
3693 llvm::Value *FitsInFP =
3694 llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
3695 FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp");
3696 InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP;
3699 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
3700 llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
3701 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
3702 CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
3704 // Emit code to load the value if it was passed in registers.
3706 CGF.EmitBlock(InRegBlock);
3708 // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
3709 // an offset of l->gp_offset and/or l->fp_offset. This may require
3710 // copying to a temporary location in case the parameter is passed
3711 // in different register classes or requires an alignment greater
3712 // than 8 for general purpose registers and 16 for XMM registers.
3714 // FIXME: This really results in shameful code when we end up needing to
3715 // collect arguments from different places; often what should result in a
3716 // simple assembling of a structure from scattered addresses has many more
3717 // loads than necessary. Can we clean this up?
3718 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3719 llvm::Value *RegSaveArea = CGF.Builder.CreateLoad(
3720 CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(16)),
3723 Address RegAddr = Address::invalid();
3724 if (neededInt && neededSSE) {
3726 assert(AI.isDirect() && "Unexpected ABI info for mixed regs");
3727 llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType());
3728 Address Tmp = CGF.CreateMemTemp(Ty);
3729 Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3730 assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs");
3731 llvm::Type *TyLo = ST->getElementType(0);
3732 llvm::Type *TyHi = ST->getElementType(1);
3733 assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&
3734 "Unexpected ABI info for mixed regs");
3735 llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo);
3736 llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi);
3737 llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegSaveArea, gp_offset);
3738 llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegSaveArea, fp_offset);
3739 llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? FPAddr : GPAddr;
3740 llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? GPAddr : FPAddr;
3742 // Copy the first element.
3743 // FIXME: Our choice of alignment here and below is probably pessimistic.
3744 llvm::Value *V = CGF.Builder.CreateAlignedLoad(
3745 TyLo, CGF.Builder.CreateBitCast(RegLoAddr, PTyLo),
3746 CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyLo)));
3747 CGF.Builder.CreateStore(V,
3748 CGF.Builder.CreateStructGEP(Tmp, 0, CharUnits::Zero()));
3750 // Copy the second element.
3751 V = CGF.Builder.CreateAlignedLoad(
3752 TyHi, CGF.Builder.CreateBitCast(RegHiAddr, PTyHi),
3753 CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyHi)));
3754 CharUnits Offset = CharUnits::fromQuantity(
3755 getDataLayout().getStructLayout(ST)->getElementOffset(1));
3756 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1, Offset));
3758 RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3759 } else if (neededInt) {
3760 RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, gp_offset),
3761 CharUnits::fromQuantity(8));
3762 RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3764 // Copy to a temporary if necessary to ensure the appropriate alignment.
3765 std::pair<CharUnits, CharUnits> SizeAlign =
3766 getContext().getTypeInfoInChars(Ty);
3767 uint64_t TySize = SizeAlign.first.getQuantity();
3768 CharUnits TyAlign = SizeAlign.second;
3770 // Copy into a temporary if the type is more aligned than the
3771 // register save area.
3772 if (TyAlign.getQuantity() > 8) {
3773 Address Tmp = CGF.CreateMemTemp(Ty);
3774 CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false);
3778 } else if (neededSSE == 1) {
3779 RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3780 CharUnits::fromQuantity(16));
3781 RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3783 assert(neededSSE == 2 && "Invalid number of needed registers!");
3784 // SSE registers are spaced 16 bytes apart in the register save
3785 // area, we need to collect the two eightbytes together.
3786 // The ABI isn't explicit about this, but it seems reasonable
3787 // to assume that the slots are 16-byte aligned, since the stack is
3788 // naturally 16-byte aligned and the prologue is expected to store
3789 // all the SSE registers to the RSA.
3790 Address RegAddrLo = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3791 CharUnits::fromQuantity(16));
3793 CGF.Builder.CreateConstInBoundsByteGEP(RegAddrLo,
3794 CharUnits::fromQuantity(16));
3795 llvm::Type *DoubleTy = CGF.DoubleTy;
3796 llvm::StructType *ST = llvm::StructType::get(DoubleTy, DoubleTy);
3798 Address Tmp = CGF.CreateMemTemp(Ty);
3799 Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3800 V = CGF.Builder.CreateLoad(
3801 CGF.Builder.CreateElementBitCast(RegAddrLo, DoubleTy));
3802 CGF.Builder.CreateStore(V,
3803 CGF.Builder.CreateStructGEP(Tmp, 0, CharUnits::Zero()));
3804 V = CGF.Builder.CreateLoad(
3805 CGF.Builder.CreateElementBitCast(RegAddrHi, DoubleTy));
3806 CGF.Builder.CreateStore(V,
3807 CGF.Builder.CreateStructGEP(Tmp, 1, CharUnits::fromQuantity(8)));
3809 RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3812 // AMD64-ABI 3.5.7p5: Step 5. Set:
3813 // l->gp_offset = l->gp_offset + num_gp * 8
3814 // l->fp_offset = l->fp_offset + num_fp * 16.
3816 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8);
3817 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset),
3821 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16);
3822 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset),
3825 CGF.EmitBranch(ContBlock);
3827 // Emit code to load the value if it was passed in memory.
3829 CGF.EmitBlock(InMemBlock);
3830 Address MemAddr = EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3832 // Return the appropriate result.
3834 CGF.EmitBlock(ContBlock);
3835 Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, MemAddr, InMemBlock,
3840 Address X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
3841 QualType Ty) const {
3842 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
3843 CGF.getContext().getTypeInfoInChars(Ty),
3844 CharUnits::fromQuantity(8),
3845 /*allowHigherAlign*/ false);
3849 WinX86_64ABIInfo::reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
3850 const ABIArgInfo ¤t) const {
3851 // Assumes vectorCall calling convention.
3852 const Type *Base = nullptr;
3853 uint64_t NumElts = 0;
3855 if (!Ty->isBuiltinType() && !Ty->isVectorType() &&
3856 isHomogeneousAggregate(Ty, Base, NumElts) && FreeSSERegs >= NumElts) {
3857 FreeSSERegs -= NumElts;
3858 return getDirectX86Hva();
3863 ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
3864 bool IsReturnType, bool IsVectorCall,
3865 bool IsRegCall) const {
3867 if (Ty->isVoidType())
3868 return ABIArgInfo::getIgnore();
3870 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3871 Ty = EnumTy->getDecl()->getIntegerType();
3873 TypeInfo Info = getContext().getTypeInfo(Ty);
3874 uint64_t Width = Info.Width;
3875 CharUnits Align = getContext().toCharUnitsFromBits(Info.Align);
3877 const RecordType *RT = Ty->getAs<RecordType>();
3879 if (!IsReturnType) {
3880 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI()))
3881 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
3884 if (RT->getDecl()->hasFlexibleArrayMember())
3885 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3889 const Type *Base = nullptr;
3890 uint64_t NumElts = 0;
3891 // vectorcall adds the concept of a homogenous vector aggregate, similar to
3893 if ((IsVectorCall || IsRegCall) &&
3894 isHomogeneousAggregate(Ty, Base, NumElts)) {
3896 if (FreeSSERegs >= NumElts) {
3897 FreeSSERegs -= NumElts;
3898 if (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())
3899 return ABIArgInfo::getDirect();
3900 return ABIArgInfo::getExpand();
3902 return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3903 } else if (IsVectorCall) {
3904 if (FreeSSERegs >= NumElts &&
3905 (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())) {
3906 FreeSSERegs -= NumElts;
3907 return ABIArgInfo::getDirect();
3908 } else if (IsReturnType) {
3909 return ABIArgInfo::getExpand();
3910 } else if (!Ty->isBuiltinType() && !Ty->isVectorType()) {
3911 // HVAs are delayed and reclassified in the 2nd step.
3912 return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3917 if (Ty->isMemberPointerType()) {
3918 // If the member pointer is represented by an LLVM int or ptr, pass it
3920 llvm::Type *LLTy = CGT.ConvertType(Ty);
3921 if (LLTy->isPointerTy() || LLTy->isIntegerTy())
3922 return ABIArgInfo::getDirect();
3925 if (RT || Ty->isAnyComplexType() || Ty->isMemberPointerType()) {
3926 // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
3927 // not 1, 2, 4, or 8 bytes, must be passed by reference."
3928 if (Width > 64 || !llvm::isPowerOf2_64(Width))
3929 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3931 // Otherwise, coerce it to a small integer.
3932 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width));
3935 // Bool type is always extended to the ABI, other builtin types are not
3937 const BuiltinType *BT = Ty->getAs<BuiltinType>();
3938 if (BT && BT->getKind() == BuiltinType::Bool)
3939 return ABIArgInfo::getExtend();
3941 // Mingw64 GCC uses the old 80 bit extended precision floating point unit. It
3942 // passes them indirectly through memory.
3943 if (IsMingw64 && BT && BT->getKind() == BuiltinType::LongDouble) {
3944 const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
3945 if (LDF == &llvm::APFloat::x87DoubleExtended())
3946 return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3949 return ABIArgInfo::getDirect();
3952 void WinX86_64ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI,
3953 unsigned FreeSSERegs,
3955 bool IsRegCall) const {
3957 for (auto &I : FI.arguments()) {
3958 // Vectorcall in x64 only permits the first 6 arguments to be passed
3959 // as XMM/YMM registers.
3960 if (Count < VectorcallMaxParamNumAsReg)
3961 I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
3963 // Since these cannot be passed in registers, pretend no registers
3965 unsigned ZeroSSERegsAvail = 0;
3966 I.info = classify(I.type, /*FreeSSERegs=*/ZeroSSERegsAvail, false,
3967 IsVectorCall, IsRegCall);
3972 for (auto &I : FI.arguments()) {
3973 I.info = reclassifyHvaArgType(I.type, FreeSSERegs, I.info);
3977 void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3979 FI.getCallingConvention() == llvm::CallingConv::X86_VectorCall;
3980 bool IsRegCall = FI.getCallingConvention() == llvm::CallingConv::X86_RegCall;
3982 unsigned FreeSSERegs = 0;
3984 // We can use up to 4 SSE return registers with vectorcall.
3986 } else if (IsRegCall) {
3987 // RegCall gives us 16 SSE registers.
3991 if (!getCXXABI().classifyReturnType(FI))
3992 FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true,
3993 IsVectorCall, IsRegCall);
3996 // We can use up to 6 SSE register parameters with vectorcall.
3998 } else if (IsRegCall) {
3999 // RegCall gives us 16 SSE registers, we can reuse the return registers.
4004 computeVectorCallArgs(FI, FreeSSERegs, IsVectorCall, IsRegCall);
4006 for (auto &I : FI.arguments())
4007 I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
4012 Address WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4013 QualType Ty) const {
4015 bool IsIndirect = false;
4017 // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
4018 // not 1, 2, 4, or 8 bytes, must be passed by reference."
4019 if (isAggregateTypeForABI(Ty) || Ty->isMemberPointerType()) {
4020 uint64_t Width = getContext().getTypeSize(Ty);
4021 IsIndirect = Width > 64 || !llvm::isPowerOf2_64(Width);
4024 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
4025 CGF.getContext().getTypeInfoInChars(Ty),
4026 CharUnits::fromQuantity(8),
4027 /*allowHigherAlign*/ false);
4032 /// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
4033 class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
4034 bool IsSoftFloatABI;
4036 CharUnits getParamTypeAlignment(QualType Ty) const;
4039 PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI)
4040 : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI) {}
4042 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4043 QualType Ty) const override;
4046 class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
4048 PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI)
4049 : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI)) {}
4051 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4052 // This is recovered from gcc output.
4053 return 1; // r1 is the dedicated stack pointer
4056 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4057 llvm::Value *Address) const override;
4061 CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4062 // Complex types are passed just like their elements
4063 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4064 Ty = CTy->getElementType();
4066 if (Ty->isVectorType())
4067 return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16
4070 // For single-element float/vector structs, we consider the whole type
4071 // to have the same alignment requirements as its single element.
4072 const Type *AlignTy = nullptr;
4073 if (const Type *EltType = isSingleElementStruct(Ty, getContext())) {
4074 const BuiltinType *BT = EltType->getAs<BuiltinType>();
4075 if ((EltType->isVectorType() && getContext().getTypeSize(EltType) == 128) ||
4076 (BT && BT->isFloatingPoint()))
4081 return CharUnits::fromQuantity(AlignTy->isVectorType() ? 16 : 4);
4082 return CharUnits::fromQuantity(4);
4085 // TODO: this implementation is now likely redundant with
4086 // DefaultABIInfo::EmitVAArg.
4087 Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
4088 QualType Ty) const {
4089 if (getTarget().getTriple().isOSDarwin()) {
4090 auto TI = getContext().getTypeInfoInChars(Ty);
4091 TI.second = getParamTypeAlignment(Ty);
4093 CharUnits SlotSize = CharUnits::fromQuantity(4);
4094 return emitVoidPtrVAArg(CGF, VAList, Ty,
4095 classifyArgumentType(Ty).isIndirect(), TI, SlotSize,
4096 /*AllowHigherAlign=*/true);
4099 const unsigned OverflowLimit = 8;
4100 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4101 // TODO: Implement this. For now ignore.
4103 return Address::invalid(); // FIXME?
4106 // struct __va_list_tag {
4107 // unsigned char gpr;
4108 // unsigned char fpr;
4109 // unsigned short reserved;
4110 // void *overflow_arg_area;
4111 // void *reg_save_area;
4114 bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;
4116 Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType();
4117 bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(Ty) == 64;
4119 // All aggregates are passed indirectly? That doesn't seem consistent
4120 // with the argument-lowering code.
4121 bool isIndirect = Ty->isAggregateType();
4123 CGBuilderTy &Builder = CGF.Builder;
4125 // The calling convention either uses 1-2 GPRs or 1 FPR.
4126 Address NumRegsAddr = Address::invalid();
4127 if (isInt || IsSoftFloatABI) {
4128 NumRegsAddr = Builder.CreateStructGEP(VAList, 0, CharUnits::Zero(), "gpr");
4130 NumRegsAddr = Builder.CreateStructGEP(VAList, 1, CharUnits::One(), "fpr");
4133 llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs");
4135 // "Align" the register count when TY is i64.
4136 if (isI64 || (isF64 && IsSoftFloatABI)) {
4137 NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1));
4138 NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U));
4142 Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond");
4144 llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
4145 llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
4146 llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
4148 Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
4150 llvm::Type *DirectTy = CGF.ConvertType(Ty);
4151 if (isIndirect) DirectTy = DirectTy->getPointerTo(0);
4153 // Case 1: consume registers.
4154 Address RegAddr = Address::invalid();
4156 CGF.EmitBlock(UsingRegs);
4158 Address RegSaveAreaPtr =
4159 Builder.CreateStructGEP(VAList, 4, CharUnits::fromQuantity(8));
4160 RegAddr = Address(Builder.CreateLoad(RegSaveAreaPtr),
4161 CharUnits::fromQuantity(8));
4162 assert(RegAddr.getElementType() == CGF.Int8Ty);
4164 // Floating-point registers start after the general-purpose registers.
4165 if (!(isInt || IsSoftFloatABI)) {
4166 RegAddr = Builder.CreateConstInBoundsByteGEP(RegAddr,
4167 CharUnits::fromQuantity(32));
4170 // Get the address of the saved value by scaling the number of
4171 // registers we've used by the number of
4172 CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8);
4173 llvm::Value *RegOffset =
4174 Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity()));
4175 RegAddr = Address(Builder.CreateInBoundsGEP(CGF.Int8Ty,
4176 RegAddr.getPointer(), RegOffset),
4177 RegAddr.getAlignment().alignmentOfArrayElement(RegSize));
4178 RegAddr = Builder.CreateElementBitCast(RegAddr, DirectTy);
4180 // Increase the used-register count.
4182 Builder.CreateAdd(NumRegs,
4183 Builder.getInt8((isI64 || (isF64 && IsSoftFloatABI)) ? 2 : 1));
4184 Builder.CreateStore(NumRegs, NumRegsAddr);
4186 CGF.EmitBranch(Cont);
4189 // Case 2: consume space in the overflow area.
4190 Address MemAddr = Address::invalid();
4192 CGF.EmitBlock(UsingOverflow);
4194 Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr);
4196 // Everything in the overflow area is rounded up to a size of at least 4.
4197 CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4);
4201 auto TypeInfo = CGF.getContext().getTypeInfoInChars(Ty);
4202 Size = TypeInfo.first.alignTo(OverflowAreaAlign);
4204 Size = CGF.getPointerSize();
4207 Address OverflowAreaAddr =
4208 Builder.CreateStructGEP(VAList, 3, CharUnits::fromQuantity(4));
4209 Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr, "argp.cur"),
4211 // Round up address of argument to alignment
4212 CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
4213 if (Align > OverflowAreaAlign) {
4214 llvm::Value *Ptr = OverflowArea.getPointer();
4215 OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),
4219 MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy);
4221 // Increase the overflow area.
4222 OverflowArea = Builder.CreateConstInBoundsByteGEP(OverflowArea, Size);
4223 Builder.CreateStore(OverflowArea.getPointer(), OverflowAreaAddr);
4224 CGF.EmitBranch(Cont);
4227 CGF.EmitBlock(Cont);
4229 // Merge the cases with a phi.
4230 Address Result = emitMergePHI(CGF, RegAddr, UsingRegs, MemAddr, UsingOverflow,
4233 // Load the pointer if the argument was passed indirectly.
4235 Result = Address(Builder.CreateLoad(Result, "aggr"),
4236 getContext().getTypeAlignInChars(Ty));
4243 PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4244 llvm::Value *Address) const {
4245 // This is calculated from the LLVM and GCC tables and verified
4246 // against gcc output. AFAIK all ABIs use the same encoding.
4248 CodeGen::CGBuilderTy &Builder = CGF.Builder;
4250 llvm::IntegerType *i8 = CGF.Int8Ty;
4251 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4252 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4253 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4255 // 0-31: r0-31, the 4-byte general-purpose registers
4256 AssignToArrayRange(Builder, Address, Four8, 0, 31);
4258 // 32-63: fp0-31, the 8-byte floating-point registers
4259 AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4261 // 64-76 are various 4-byte special-purpose registers:
4268 AssignToArrayRange(Builder, Address, Four8, 64, 76);
4270 // 77-108: v0-31, the 16-byte vector registers
4271 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4278 AssignToArrayRange(Builder, Address, Four8, 109, 113);
4286 /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
4287 class PPC64_SVR4_ABIInfo : public ABIInfo {
4295 static const unsigned GPRBits = 64;
4298 bool IsSoftFloatABI;
4300 // A vector of float or double will be promoted to <4 x f32> or <4 x f64> and
4301 // will be passed in a QPX register.
4302 bool IsQPXVectorTy(const Type *Ty) const {
4306 if (const VectorType *VT = Ty->getAs<VectorType>()) {
4307 unsigned NumElements = VT->getNumElements();
4308 if (NumElements == 1)
4311 if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) {
4312 if (getContext().getTypeSize(Ty) <= 256)
4314 } else if (VT->getElementType()->
4315 isSpecificBuiltinType(BuiltinType::Float)) {
4316 if (getContext().getTypeSize(Ty) <= 128)
4324 bool IsQPXVectorTy(QualType Ty) const {
4325 return IsQPXVectorTy(Ty.getTypePtr());
4329 PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
4331 : ABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
4332 IsSoftFloatABI(SoftFloatABI) {}
4334 bool isPromotableTypeForABI(QualType Ty) const;
4335 CharUnits getParamTypeAlignment(QualType Ty) const;
4337 ABIArgInfo classifyReturnType(QualType RetTy) const;
4338 ABIArgInfo classifyArgumentType(QualType Ty) const;
4340 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4341 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4342 uint64_t Members) const override;
4344 // TODO: We can add more logic to computeInfo to improve performance.
4345 // Example: For aggregate arguments that fit in a register, we could
4346 // use getDirectInReg (as is done below for structs containing a single
4347 // floating-point value) to avoid pushing them to memory on function
4348 // entry. This would require changing the logic in PPCISelLowering
4349 // when lowering the parameters in the caller and args in the callee.
4350 void computeInfo(CGFunctionInfo &FI) const override {
4351 if (!getCXXABI().classifyReturnType(FI))
4352 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
4353 for (auto &I : FI.arguments()) {
4354 // We rely on the default argument classification for the most part.
4355 // One exception: An aggregate containing a single floating-point
4356 // or vector item must be passed in a register if one is available.
4357 const Type *T = isSingleElementStruct(I.type, getContext());
4359 const BuiltinType *BT = T->getAs<BuiltinType>();
4360 if (IsQPXVectorTy(T) ||
4361 (T->isVectorType() && getContext().getTypeSize(T) == 128) ||
4362 (BT && BT->isFloatingPoint())) {
4364 I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
4368 I.info = classifyArgumentType(I.type);
4372 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4373 QualType Ty) const override;
4376 class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
4379 PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT,
4380 PPC64_SVR4_ABIInfo::ABIKind Kind, bool HasQPX,
4382 : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT, Kind, HasQPX,
4385 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4386 // This is recovered from gcc output.
4387 return 1; // r1 is the dedicated stack pointer
4390 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4391 llvm::Value *Address) const override;
4394 class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
4396 PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
4398 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4399 // This is recovered from gcc output.
4400 return 1; // r1 is the dedicated stack pointer
4403 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4404 llvm::Value *Address) const override;
4409 // Return true if the ABI requires Ty to be passed sign- or zero-
4410 // extended to 64 bits.
4412 PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
4413 // Treat an enum type as its underlying type.
4414 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4415 Ty = EnumTy->getDecl()->getIntegerType();
4417 // Promotable integer types are required to be promoted by the ABI.
4418 if (Ty->isPromotableIntegerType())
4421 // In addition to the usual promotable integer types, we also need to
4422 // extend all 32-bit types, since the ABI requires promotion to 64 bits.
4423 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
4424 switch (BT->getKind()) {
4425 case BuiltinType::Int:
4426 case BuiltinType::UInt:
4435 /// isAlignedParamType - Determine whether a type requires 16-byte or
4436 /// higher alignment in the parameter area. Always returns at least 8.
4437 CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4438 // Complex types are passed just like their elements.
4439 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4440 Ty = CTy->getElementType();
4442 // Only vector types of size 16 bytes need alignment (larger types are
4443 // passed via reference, smaller types are not aligned).
4444 if (IsQPXVectorTy(Ty)) {
4445 if (getContext().getTypeSize(Ty) > 128)
4446 return CharUnits::fromQuantity(32);
4448 return CharUnits::fromQuantity(16);
4449 } else if (Ty->isVectorType()) {
4450 return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);
4453 // For single-element float/vector structs, we consider the whole type
4454 // to have the same alignment requirements as its single element.
4455 const Type *AlignAsType = nullptr;
4456 const Type *EltType = isSingleElementStruct(Ty, getContext());
4458 const BuiltinType *BT = EltType->getAs<BuiltinType>();
4459 if (IsQPXVectorTy(EltType) || (EltType->isVectorType() &&
4460 getContext().getTypeSize(EltType) == 128) ||
4461 (BT && BT->isFloatingPoint()))
4462 AlignAsType = EltType;
4465 // Likewise for ELFv2 homogeneous aggregates.
4466 const Type *Base = nullptr;
4467 uint64_t Members = 0;
4468 if (!AlignAsType && Kind == ELFv2 &&
4469 isAggregateTypeForABI(Ty) && isHomogeneousAggregate(Ty, Base, Members))
4472 // With special case aggregates, only vector base types need alignment.
4473 if (AlignAsType && IsQPXVectorTy(AlignAsType)) {
4474 if (getContext().getTypeSize(AlignAsType) > 128)
4475 return CharUnits::fromQuantity(32);
4477 return CharUnits::fromQuantity(16);
4478 } else if (AlignAsType) {
4479 return CharUnits::fromQuantity(AlignAsType->isVectorType() ? 16 : 8);
4482 // Otherwise, we only need alignment for any aggregate type that
4483 // has an alignment requirement of >= 16 bytes.
4484 if (isAggregateTypeForABI(Ty) && getContext().getTypeAlign(Ty) >= 128) {
4485 if (HasQPX && getContext().getTypeAlign(Ty) >= 256)
4486 return CharUnits::fromQuantity(32);
4487 return CharUnits::fromQuantity(16);
4490 return CharUnits::fromQuantity(8);
4493 /// isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous
4494 /// aggregate. Base is set to the base element type, and Members is set
4495 /// to the number of base elements.
4496 bool ABIInfo::isHomogeneousAggregate(QualType Ty, const Type *&Base,
4497 uint64_t &Members) const {
4498 if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
4499 uint64_t NElements = AT->getSize().getZExtValue();
4502 if (!isHomogeneousAggregate(AT->getElementType(), Base, Members))
4504 Members *= NElements;
4505 } else if (const RecordType *RT = Ty->getAs<RecordType>()) {
4506 const RecordDecl *RD = RT->getDecl();
4507 if (RD->hasFlexibleArrayMember())
4512 // If this is a C++ record, check the bases first.
4513 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
4514 for (const auto &I : CXXRD->bases()) {
4515 // Ignore empty records.
4516 if (isEmptyRecord(getContext(), I.getType(), true))
4519 uint64_t FldMembers;
4520 if (!isHomogeneousAggregate(I.getType(), Base, FldMembers))
4523 Members += FldMembers;
4527 for (const auto *FD : RD->fields()) {
4528 // Ignore (non-zero arrays of) empty records.
4529 QualType FT = FD->getType();
4530 while (const ConstantArrayType *AT =
4531 getContext().getAsConstantArrayType(FT)) {
4532 if (AT->getSize().getZExtValue() == 0)
4534 FT = AT->getElementType();
4536 if (isEmptyRecord(getContext(), FT, true))
4539 // For compatibility with GCC, ignore empty bitfields in C++ mode.
4540 if (getContext().getLangOpts().CPlusPlus &&
4541 FD->isBitField() && FD->getBitWidthValue(getContext()) == 0)
4544 uint64_t FldMembers;
4545 if (!isHomogeneousAggregate(FD->getType(), Base, FldMembers))
4548 Members = (RD->isUnion() ?
4549 std::max(Members, FldMembers) : Members + FldMembers);
4555 // Ensure there is no padding.
4556 if (getContext().getTypeSize(Base) * Members !=
4557 getContext().getTypeSize(Ty))
4561 if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
4563 Ty = CT->getElementType();
4566 // Most ABIs only support float, double, and some vector type widths.
4567 if (!isHomogeneousAggregateBaseType(Ty))
4570 // The base type must be the same for all members. Types that
4571 // agree in both total size and mode (float vs. vector) are
4572 // treated as being equivalent here.
4573 const Type *TyPtr = Ty.getTypePtr();
4576 // If it's a non-power-of-2 vector, its size is already a power-of-2,
4577 // so make sure to widen it explicitly.
4578 if (const VectorType *VT = Base->getAs<VectorType>()) {
4579 QualType EltTy = VT->getElementType();
4580 unsigned NumElements =
4581 getContext().getTypeSize(VT) / getContext().getTypeSize(EltTy);
4583 .getVectorType(EltTy, NumElements, VT->getVectorKind())
4588 if (Base->isVectorType() != TyPtr->isVectorType() ||
4589 getContext().getTypeSize(Base) != getContext().getTypeSize(TyPtr))
4592 return Members > 0 && isHomogeneousAggregateSmallEnough(Base, Members);
4595 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
4596 // Homogeneous aggregates for ELFv2 must have base types of float,
4597 // double, long double, or 128-bit vectors.
4598 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4599 if (BT->getKind() == BuiltinType::Float ||
4600 BT->getKind() == BuiltinType::Double ||
4601 BT->getKind() == BuiltinType::LongDouble) {
4607 if (const VectorType *VT = Ty->getAs<VectorType>()) {
4608 if (getContext().getTypeSize(VT) == 128 || IsQPXVectorTy(Ty))
4614 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
4615 const Type *Base, uint64_t Members) const {
4616 // Vector types require one register, floating point types require one
4617 // or two registers depending on their size.
4619 Base->isVectorType() ? 1 : (getContext().getTypeSize(Base) + 63) / 64;
4621 // Homogeneous Aggregates may occupy at most 8 registers.
4622 return Members * NumRegs <= 8;
4626 PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
4627 Ty = useFirstFieldIfTransparentUnion(Ty);
4629 if (Ty->isAnyComplexType())
4630 return ABIArgInfo::getDirect();
4632 // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
4633 // or via reference (larger than 16 bytes).
4634 if (Ty->isVectorType() && !IsQPXVectorTy(Ty)) {
4635 uint64_t Size = getContext().getTypeSize(Ty);
4637 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4638 else if (Size < 128) {
4639 llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4640 return ABIArgInfo::getDirect(CoerceTy);
4644 if (isAggregateTypeForABI(Ty)) {
4645 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
4646 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
4648 uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity();
4649 uint64_t TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();
4651 // ELFv2 homogeneous aggregates are passed as array types.
4652 const Type *Base = nullptr;
4653 uint64_t Members = 0;
4654 if (Kind == ELFv2 &&
4655 isHomogeneousAggregate(Ty, Base, Members)) {
4656 llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4657 llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4658 return ABIArgInfo::getDirect(CoerceTy);
4661 // If an aggregate may end up fully in registers, we do not
4662 // use the ByVal method, but pass the aggregate as array.
4663 // This is usually beneficial since we avoid forcing the
4664 // back-end to store the argument to memory.
4665 uint64_t Bits = getContext().getTypeSize(Ty);
4666 if (Bits > 0 && Bits <= 8 * GPRBits) {
4667 llvm::Type *CoerceTy;
4669 // Types up to 8 bytes are passed as integer type (which will be
4670 // properly aligned in the argument save area doubleword).
4671 if (Bits <= GPRBits)
4673 llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4674 // Larger types are passed as arrays, with the base type selected
4675 // according to the required alignment in the save area.
4677 uint64_t RegBits = ABIAlign * 8;
4678 uint64_t NumRegs = llvm::alignTo(Bits, RegBits) / RegBits;
4679 llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits);
4680 CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);
4683 return ABIArgInfo::getDirect(CoerceTy);
4686 // All other aggregates are passed ByVal.
4687 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(ABIAlign),
4689 /*Realign=*/TyAlign > ABIAlign);
4692 return (isPromotableTypeForABI(Ty) ?
4693 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
4697 PPC64_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {
4698 if (RetTy->isVoidType())
4699 return ABIArgInfo::getIgnore();
4701 if (RetTy->isAnyComplexType())
4702 return ABIArgInfo::getDirect();
4704 // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
4705 // or via reference (larger than 16 bytes).
4706 if (RetTy->isVectorType() && !IsQPXVectorTy(RetTy)) {
4707 uint64_t Size = getContext().getTypeSize(RetTy);
4709 return getNaturalAlignIndirect(RetTy);
4710 else if (Size < 128) {
4711 llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4712 return ABIArgInfo::getDirect(CoerceTy);
4716 if (isAggregateTypeForABI(RetTy)) {
4717 // ELFv2 homogeneous aggregates are returned as array types.
4718 const Type *Base = nullptr;
4719 uint64_t Members = 0;
4720 if (Kind == ELFv2 &&
4721 isHomogeneousAggregate(RetTy, Base, Members)) {
4722 llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4723 llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4724 return ABIArgInfo::getDirect(CoerceTy);
4727 // ELFv2 small aggregates are returned in up to two registers.
4728 uint64_t Bits = getContext().getTypeSize(RetTy);
4729 if (Kind == ELFv2 && Bits <= 2 * GPRBits) {
4731 return ABIArgInfo::getIgnore();
4733 llvm::Type *CoerceTy;
4734 if (Bits > GPRBits) {
4735 CoerceTy = llvm::IntegerType::get(getVMContext(), GPRBits);
4736 CoerceTy = llvm::StructType::get(CoerceTy, CoerceTy);
4739 llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4740 return ABIArgInfo::getDirect(CoerceTy);
4743 // All other aggregates are returned indirectly.
4744 return getNaturalAlignIndirect(RetTy);
4747 return (isPromotableTypeForABI(RetTy) ?
4748 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
4751 // Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
4752 Address PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4753 QualType Ty) const {
4754 auto TypeInfo = getContext().getTypeInfoInChars(Ty);
4755 TypeInfo.second = getParamTypeAlignment(Ty);
4757 CharUnits SlotSize = CharUnits::fromQuantity(8);
4759 // If we have a complex type and the base type is smaller than 8 bytes,
4760 // the ABI calls for the real and imaginary parts to be right-adjusted
4761 // in separate doublewords. However, Clang expects us to produce a
4762 // pointer to a structure with the two parts packed tightly. So generate
4763 // loads of the real and imaginary parts relative to the va_list pointer,
4764 // and store them to a temporary structure.
4765 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4766 CharUnits EltSize = TypeInfo.first / 2;
4767 if (EltSize < SlotSize) {
4768 Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty,
4769 SlotSize * 2, SlotSize,
4770 SlotSize, /*AllowHigher*/ true);
4772 Address RealAddr = Addr;
4773 Address ImagAddr = RealAddr;
4774 if (CGF.CGM.getDataLayout().isBigEndian()) {
4775 RealAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr,
4776 SlotSize - EltSize);
4777 ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(ImagAddr,
4778 2 * SlotSize - EltSize);
4780 ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize);
4783 llvm::Type *EltTy = CGF.ConvertTypeForMem(CTy->getElementType());
4784 RealAddr = CGF.Builder.CreateElementBitCast(RealAddr, EltTy);
4785 ImagAddr = CGF.Builder.CreateElementBitCast(ImagAddr, EltTy);
4786 llvm::Value *Real = CGF.Builder.CreateLoad(RealAddr, ".vareal");
4787 llvm::Value *Imag = CGF.Builder.CreateLoad(ImagAddr, ".vaimag");
4789 Address Temp = CGF.CreateMemTemp(Ty, "vacplx");
4790 CGF.EmitStoreOfComplex({Real, Imag}, CGF.MakeAddrLValue(Temp, Ty),
4796 // Otherwise, just use the general rule.
4797 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
4798 TypeInfo, SlotSize, /*AllowHigher*/ true);
4802 PPC64_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4803 llvm::Value *Address) {
4804 // This is calculated from the LLVM and GCC tables and verified
4805 // against gcc output. AFAIK all ABIs use the same encoding.
4807 CodeGen::CGBuilderTy &Builder = CGF.Builder;
4809 llvm::IntegerType *i8 = CGF.Int8Ty;
4810 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4811 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4812 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4814 // 0-31: r0-31, the 8-byte general-purpose registers
4815 AssignToArrayRange(Builder, Address, Eight8, 0, 31);
4817 // 32-63: fp0-31, the 8-byte floating-point registers
4818 AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4820 // 64-67 are various 8-byte special-purpose registers:
4825 AssignToArrayRange(Builder, Address, Eight8, 64, 67);
4827 // 68-76 are various 4-byte special-purpose registers:
4830 AssignToArrayRange(Builder, Address, Four8, 68, 76);
4832 // 77-108: v0-31, the 16-byte vector registers
4833 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4843 AssignToArrayRange(Builder, Address, Eight8, 109, 116);
4849 PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
4850 CodeGen::CodeGenFunction &CGF,
4851 llvm::Value *Address) const {
4853 return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4857 PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4858 llvm::Value *Address) const {
4860 return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4863 //===----------------------------------------------------------------------===//
4864 // AArch64 ABI Implementation
4865 //===----------------------------------------------------------------------===//
4869 class AArch64ABIInfo : public SwiftABIInfo {
4881 AArch64ABIInfo(CodeGenTypes &CGT, ABIKind Kind)
4882 : SwiftABIInfo(CGT), Kind(Kind) {}
4885 ABIKind getABIKind() const { return Kind; }
4886 bool isDarwinPCS() const { return Kind == DarwinPCS; }
4888 ABIArgInfo classifyReturnType(QualType RetTy) const;
4889 ABIArgInfo classifyArgumentType(QualType RetTy) const;
4890 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4891 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4892 uint64_t Members) const override;
4894 bool isIllegalVectorType(QualType Ty) const;
4896 void computeInfo(CGFunctionInfo &FI) const override {
4897 if (!getCXXABI().classifyReturnType(FI))
4898 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
4900 for (auto &it : FI.arguments())
4901 it.info = classifyArgumentType(it.type);
4904 Address EmitDarwinVAArg(Address VAListAddr, QualType Ty,
4905 CodeGenFunction &CGF) const;
4907 Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
4908 CodeGenFunction &CGF) const;
4910 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4911 QualType Ty) const override {
4912 return Kind == Win64 ? EmitMSVAArg(CGF, VAListAddr, Ty)
4913 : isDarwinPCS() ? EmitDarwinVAArg(VAListAddr, Ty, CGF)
4914 : EmitAAPCSVAArg(VAListAddr, Ty, CGF);
4917 Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
4918 QualType Ty) const override;
4920 bool shouldPassIndirectlyForSwift(CharUnits totalSize,
4921 ArrayRef<llvm::Type*> scalars,
4922 bool asReturnValue) const override {
4923 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
4925 bool isSwiftErrorInRegister() const override {
4929 bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
4930 unsigned elts) const override;
4933 class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
4935 AArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind Kind)
4936 : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
4938 StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
4939 return "mov\tfp, fp\t\t// marker for objc_retainAutoreleaseReturnValue";
4942 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4946 bool doesReturnSlotInterfereWithArgs() const override { return false; }
4949 class WindowsAArch64TargetCodeGenInfo : public AArch64TargetCodeGenInfo {
4951 WindowsAArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind K)
4952 : AArch64TargetCodeGenInfo(CGT, K) {}
4954 void getDependentLibraryOption(llvm::StringRef Lib,
4955 llvm::SmallString<24> &Opt) const override {
4956 Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
4959 void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
4960 llvm::SmallString<32> &Opt) const override {
4961 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
4966 ABIArgInfo AArch64ABIInfo::classifyArgumentType(QualType Ty) const {
4967 Ty = useFirstFieldIfTransparentUnion(Ty);
4969 // Handle illegal vector types here.
4970 if (isIllegalVectorType(Ty)) {
4971 uint64_t Size = getContext().getTypeSize(Ty);
4972 // Android promotes <2 x i8> to i16, not i32
4973 if (isAndroid() && (Size <= 16)) {
4974 llvm::Type *ResType = llvm::Type::getInt16Ty(getVMContext());
4975 return ABIArgInfo::getDirect(ResType);
4978 llvm::Type *ResType = llvm::Type::getInt32Ty(getVMContext());
4979 return ABIArgInfo::getDirect(ResType);
4982 llvm::Type *ResType =
4983 llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 2);
4984 return ABIArgInfo::getDirect(ResType);
4987 llvm::Type *ResType =
4988 llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 4);
4989 return ABIArgInfo::getDirect(ResType);
4991 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4994 if (!isAggregateTypeForABI(Ty)) {
4995 // Treat an enum type as its underlying type.
4996 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4997 Ty = EnumTy->getDecl()->getIntegerType();
4999 return (Ty->isPromotableIntegerType() && isDarwinPCS()
5000 ? ABIArgInfo::getExtend()
5001 : ABIArgInfo::getDirect());
5004 // Structures with either a non-trivial destructor or a non-trivial
5005 // copy constructor are always indirect.
5006 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
5007 return getNaturalAlignIndirect(Ty, /*ByVal=*/RAA ==
5008 CGCXXABI::RAA_DirectInMemory);
5011 // Empty records are always ignored on Darwin, but actually passed in C++ mode
5012 // elsewhere for GNU compatibility.
5013 uint64_t Size = getContext().getTypeSize(Ty);
5014 bool IsEmpty = isEmptyRecord(getContext(), Ty, true);
5015 if (IsEmpty || Size == 0) {
5016 if (!getContext().getLangOpts().CPlusPlus || isDarwinPCS())
5017 return ABIArgInfo::getIgnore();
5019 // GNU C mode. The only argument that gets ignored is an empty one with size
5021 if (IsEmpty && Size == 0)
5022 return ABIArgInfo::getIgnore();
5023 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
5026 // Homogeneous Floating-point Aggregates (HFAs) need to be expanded.
5027 const Type *Base = nullptr;
5028 uint64_t Members = 0;
5029 if (isHomogeneousAggregate(Ty, Base, Members)) {
5030 return ABIArgInfo::getDirect(
5031 llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members));
5034 // Aggregates <= 16 bytes are passed directly in registers or on the stack.
5036 // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
5037 // same size and alignment.
5038 if (getTarget().isRenderScriptTarget()) {
5039 return coerceToIntArray(Ty, getContext(), getVMContext());
5041 unsigned Alignment = getContext().getTypeAlign(Ty);
5042 Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes
5044 // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
5045 // For aggregates with 16-byte alignment, we use i128.
5046 if (Alignment < 128 && Size == 128) {
5047 llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
5048 return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
5050 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
5053 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5056 ABIArgInfo AArch64ABIInfo::classifyReturnType(QualType RetTy) const {
5057 if (RetTy->isVoidType())
5058 return ABIArgInfo::getIgnore();
5060 // Large vector types should be returned via memory.
5061 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128)
5062 return getNaturalAlignIndirect(RetTy);
5064 if (!isAggregateTypeForABI(RetTy)) {
5065 // Treat an enum type as its underlying type.
5066 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5067 RetTy = EnumTy->getDecl()->getIntegerType();
5069 return (RetTy->isPromotableIntegerType() && isDarwinPCS()
5070 ? ABIArgInfo::getExtend()
5071 : ABIArgInfo::getDirect());
5074 uint64_t Size = getContext().getTypeSize(RetTy);
5075 if (isEmptyRecord(getContext(), RetTy, true) || Size == 0)
5076 return ABIArgInfo::getIgnore();
5078 const Type *Base = nullptr;
5079 uint64_t Members = 0;
5080 if (isHomogeneousAggregate(RetTy, Base, Members))
5081 // Homogeneous Floating-point Aggregates (HFAs) are returned directly.
5082 return ABIArgInfo::getDirect();
5084 // Aggregates <= 16 bytes are returned directly in registers or on the stack.
5086 // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
5087 // same size and alignment.
5088 if (getTarget().isRenderScriptTarget()) {
5089 return coerceToIntArray(RetTy, getContext(), getVMContext());
5091 unsigned Alignment = getContext().getTypeAlign(RetTy);
5092 Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes
5094 // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
5095 // For aggregates with 16-byte alignment, we use i128.
5096 if (Alignment < 128 && Size == 128) {
5097 llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
5098 return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
5100 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
5103 return getNaturalAlignIndirect(RetTy);
5106 /// isIllegalVectorType - check whether the vector type is legal for AArch64.
5107 bool AArch64ABIInfo::isIllegalVectorType(QualType Ty) const {
5108 if (const VectorType *VT = Ty->getAs<VectorType>()) {
5109 // Check whether VT is legal.
5110 unsigned NumElements = VT->getNumElements();
5111 uint64_t Size = getContext().getTypeSize(VT);
5112 // NumElements should be power of 2.
5113 if (!llvm::isPowerOf2_32(NumElements))
5115 return Size != 64 && (Size != 128 || NumElements == 1);
5120 bool AArch64ABIInfo::isLegalVectorTypeForSwift(CharUnits totalSize,
5122 unsigned elts) const {
5123 if (!llvm::isPowerOf2_32(elts))
5125 if (totalSize.getQuantity() != 8 &&
5126 (totalSize.getQuantity() != 16 || elts == 1))
5131 bool AArch64ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
5132 // Homogeneous aggregates for AAPCS64 must have base types of a floating
5133 // point type or a short-vector type. This is the same as the 32-bit ABI,
5134 // but with the difference that any floating-point type is allowed,
5135 // including __fp16.
5136 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
5137 if (BT->isFloatingPoint())
5139 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
5140 unsigned VecSize = getContext().getTypeSize(VT);
5141 if (VecSize == 64 || VecSize == 128)
5147 bool AArch64ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
5148 uint64_t Members) const {
5149 return Members <= 4;
5152 Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr,
5154 CodeGenFunction &CGF) const {
5155 ABIArgInfo AI = classifyArgumentType(Ty);
5156 bool IsIndirect = AI.isIndirect();
5158 llvm::Type *BaseTy = CGF.ConvertType(Ty);
5160 BaseTy = llvm::PointerType::getUnqual(BaseTy);
5161 else if (AI.getCoerceToType())
5162 BaseTy = AI.getCoerceToType();
5164 unsigned NumRegs = 1;
5165 if (llvm::ArrayType *ArrTy = dyn_cast<llvm::ArrayType>(BaseTy)) {
5166 BaseTy = ArrTy->getElementType();
5167 NumRegs = ArrTy->getNumElements();
5169 bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy();
5171 // The AArch64 va_list type and handling is specified in the Procedure Call
5172 // Standard, section B.4:
5182 llvm::BasicBlock *MaybeRegBlock = CGF.createBasicBlock("vaarg.maybe_reg");
5183 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
5184 llvm::BasicBlock *OnStackBlock = CGF.createBasicBlock("vaarg.on_stack");
5185 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
5187 auto TyInfo = getContext().getTypeInfoInChars(Ty);
5188 CharUnits TyAlign = TyInfo.second;
5190 Address reg_offs_p = Address::invalid();
5191 llvm::Value *reg_offs = nullptr;
5193 CharUnits reg_top_offset;
5194 int RegSize = IsIndirect ? 8 : TyInfo.first.getQuantity();
5196 // 3 is the field number of __gr_offs
5198 CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(24),
5200 reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "gr_offs");
5201 reg_top_index = 1; // field number for __gr_top
5202 reg_top_offset = CharUnits::fromQuantity(8);
5203 RegSize = llvm::alignTo(RegSize, 8);
5205 // 4 is the field number of __vr_offs.
5207 CGF.Builder.CreateStructGEP(VAListAddr, 4, CharUnits::fromQuantity(28),
5209 reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "vr_offs");
5210 reg_top_index = 2; // field number for __vr_top
5211 reg_top_offset = CharUnits::fromQuantity(16);
5212 RegSize = 16 * NumRegs;
5215 //=======================================
5216 // Find out where argument was passed
5217 //=======================================
5219 // If reg_offs >= 0 we're already using the stack for this type of
5220 // argument. We don't want to keep updating reg_offs (in case it overflows,
5221 // though anyone passing 2GB of arguments, each at most 16 bytes, deserves
5222 // whatever they get).
5223 llvm::Value *UsingStack = nullptr;
5224 UsingStack = CGF.Builder.CreateICmpSGE(
5225 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, 0));
5227 CGF.Builder.CreateCondBr(UsingStack, OnStackBlock, MaybeRegBlock);
5229 // Otherwise, at least some kind of argument could go in these registers, the
5230 // question is whether this particular type is too big.
5231 CGF.EmitBlock(MaybeRegBlock);
5233 // Integer arguments may need to correct register alignment (for example a
5234 // "struct { __int128 a; };" gets passed in x_2N, x_{2N+1}). In this case we
5235 // align __gr_offs to calculate the potential address.
5236 if (!IsFPR && !IsIndirect && TyAlign.getQuantity() > 8) {
5237 int Align = TyAlign.getQuantity();
5239 reg_offs = CGF.Builder.CreateAdd(
5240 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, Align - 1),
5242 reg_offs = CGF.Builder.CreateAnd(
5243 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, -Align),
5247 // Update the gr_offs/vr_offs pointer for next call to va_arg on this va_list.
5248 // The fact that this is done unconditionally reflects the fact that
5249 // allocating an argument to the stack also uses up all the remaining
5250 // registers of the appropriate kind.
5251 llvm::Value *NewOffset = nullptr;
5252 NewOffset = CGF.Builder.CreateAdd(
5253 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs");
5254 CGF.Builder.CreateStore(NewOffset, reg_offs_p);
5256 // Now we're in a position to decide whether this argument really was in
5257 // registers or not.
5258 llvm::Value *InRegs = nullptr;
5259 InRegs = CGF.Builder.CreateICmpSLE(
5260 NewOffset, llvm::ConstantInt::get(CGF.Int32Ty, 0), "inreg");
5262 CGF.Builder.CreateCondBr(InRegs, InRegBlock, OnStackBlock);
5264 //=======================================
5265 // Argument was in registers
5266 //=======================================
5268 // Now we emit the code for if the argument was originally passed in
5269 // registers. First start the appropriate block:
5270 CGF.EmitBlock(InRegBlock);
5272 llvm::Value *reg_top = nullptr;
5273 Address reg_top_p = CGF.Builder.CreateStructGEP(VAListAddr, reg_top_index,
5274 reg_top_offset, "reg_top_p");
5275 reg_top = CGF.Builder.CreateLoad(reg_top_p, "reg_top");
5276 Address BaseAddr(CGF.Builder.CreateInBoundsGEP(reg_top, reg_offs),
5277 CharUnits::fromQuantity(IsFPR ? 16 : 8));
5278 Address RegAddr = Address::invalid();
5279 llvm::Type *MemTy = CGF.ConvertTypeForMem(Ty);
5282 // If it's been passed indirectly (actually a struct), whatever we find from
5283 // stored registers or on the stack will actually be a struct **.
5284 MemTy = llvm::PointerType::getUnqual(MemTy);
5287 const Type *Base = nullptr;
5288 uint64_t NumMembers = 0;
5289 bool IsHFA = isHomogeneousAggregate(Ty, Base, NumMembers);
5290 if (IsHFA && NumMembers > 1) {
5291 // Homogeneous aggregates passed in registers will have their elements split
5292 // and stored 16-bytes apart regardless of size (they're notionally in qN,
5293 // qN+1, ...). We reload and store into a temporary local variable
5295 assert(!IsIndirect && "Homogeneous aggregates should be passed directly");
5296 auto BaseTyInfo = getContext().getTypeInfoInChars(QualType(Base, 0));
5297 llvm::Type *BaseTy = CGF.ConvertType(QualType(Base, 0));
5298 llvm::Type *HFATy = llvm::ArrayType::get(BaseTy, NumMembers);
5299 Address Tmp = CGF.CreateTempAlloca(HFATy,
5300 std::max(TyAlign, BaseTyInfo.second));
5302 // On big-endian platforms, the value will be right-aligned in its slot.
5304 if (CGF.CGM.getDataLayout().isBigEndian() &&
5305 BaseTyInfo.first.getQuantity() < 16)
5306 Offset = 16 - BaseTyInfo.first.getQuantity();
5308 for (unsigned i = 0; i < NumMembers; ++i) {
5309 CharUnits BaseOffset = CharUnits::fromQuantity(16 * i + Offset);
5311 CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, BaseOffset);
5312 LoadAddr = CGF.Builder.CreateElementBitCast(LoadAddr, BaseTy);
5315 CGF.Builder.CreateConstArrayGEP(Tmp, i, BaseTyInfo.first);
5317 llvm::Value *Elem = CGF.Builder.CreateLoad(LoadAddr);
5318 CGF.Builder.CreateStore(Elem, StoreAddr);
5321 RegAddr = CGF.Builder.CreateElementBitCast(Tmp, MemTy);
5323 // Otherwise the object is contiguous in memory.
5325 // It might be right-aligned in its slot.
5326 CharUnits SlotSize = BaseAddr.getAlignment();
5327 if (CGF.CGM.getDataLayout().isBigEndian() && !IsIndirect &&
5328 (IsHFA || !isAggregateTypeForABI(Ty)) &&
5329 TyInfo.first < SlotSize) {
5330 CharUnits Offset = SlotSize - TyInfo.first;
5331 BaseAddr = CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, Offset);
5334 RegAddr = CGF.Builder.CreateElementBitCast(BaseAddr, MemTy);
5337 CGF.EmitBranch(ContBlock);
5339 //=======================================
5340 // Argument was on the stack
5341 //=======================================
5342 CGF.EmitBlock(OnStackBlock);
5344 Address stack_p = CGF.Builder.CreateStructGEP(VAListAddr, 0,
5345 CharUnits::Zero(), "stack_p");
5346 llvm::Value *OnStackPtr = CGF.Builder.CreateLoad(stack_p, "stack");
5348 // Again, stack arguments may need realignment. In this case both integer and
5349 // floating-point ones might be affected.
5350 if (!IsIndirect && TyAlign.getQuantity() > 8) {
5351 int Align = TyAlign.getQuantity();
5353 OnStackPtr = CGF.Builder.CreatePtrToInt(OnStackPtr, CGF.Int64Ty);
5355 OnStackPtr = CGF.Builder.CreateAdd(
5356 OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, Align - 1),
5358 OnStackPtr = CGF.Builder.CreateAnd(
5359 OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, -Align),
5362 OnStackPtr = CGF.Builder.CreateIntToPtr(OnStackPtr, CGF.Int8PtrTy);
5364 Address OnStackAddr(OnStackPtr,
5365 std::max(CharUnits::fromQuantity(8), TyAlign));
5367 // All stack slots are multiples of 8 bytes.
5368 CharUnits StackSlotSize = CharUnits::fromQuantity(8);
5369 CharUnits StackSize;
5371 StackSize = StackSlotSize;
5373 StackSize = TyInfo.first.alignTo(StackSlotSize);
5375 llvm::Value *StackSizeC = CGF.Builder.getSize(StackSize);
5376 llvm::Value *NewStack =
5377 CGF.Builder.CreateInBoundsGEP(OnStackPtr, StackSizeC, "new_stack");
5379 // Write the new value of __stack for the next call to va_arg
5380 CGF.Builder.CreateStore(NewStack, stack_p);
5382 if (CGF.CGM.getDataLayout().isBigEndian() && !isAggregateTypeForABI(Ty) &&
5383 TyInfo.first < StackSlotSize) {
5384 CharUnits Offset = StackSlotSize - TyInfo.first;
5385 OnStackAddr = CGF.Builder.CreateConstInBoundsByteGEP(OnStackAddr, Offset);
5388 OnStackAddr = CGF.Builder.CreateElementBitCast(OnStackAddr, MemTy);
5390 CGF.EmitBranch(ContBlock);
5392 //=======================================
5394 //=======================================
5395 CGF.EmitBlock(ContBlock);
5397 Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
5398 OnStackAddr, OnStackBlock, "vaargs.addr");
5401 return Address(CGF.Builder.CreateLoad(ResAddr, "vaarg.addr"),
5407 Address AArch64ABIInfo::EmitDarwinVAArg(Address VAListAddr, QualType Ty,
5408 CodeGenFunction &CGF) const {
5409 // The backend's lowering doesn't support va_arg for aggregates or
5410 // illegal vector types. Lower VAArg here for these cases and use
5411 // the LLVM va_arg instruction for everything else.
5412 if (!isAggregateTypeForABI(Ty) && !isIllegalVectorType(Ty))
5413 return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
5415 CharUnits SlotSize = CharUnits::fromQuantity(8);
5417 // Empty records are ignored for parameter passing purposes.
5418 if (isEmptyRecord(getContext(), Ty, true)) {
5419 Address Addr(CGF.Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize);
5420 Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
5424 // The size of the actual thing passed, which might end up just
5425 // being a pointer for indirect types.
5426 auto TyInfo = getContext().getTypeInfoInChars(Ty);
5428 // Arguments bigger than 16 bytes which aren't homogeneous
5429 // aggregates should be passed indirectly.
5430 bool IsIndirect = false;
5431 if (TyInfo.first.getQuantity() > 16) {
5432 const Type *Base = nullptr;
5433 uint64_t Members = 0;
5434 IsIndirect = !isHomogeneousAggregate(Ty, Base, Members);
5437 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
5438 TyInfo, SlotSize, /*AllowHigherAlign*/ true);
5441 Address AArch64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
5442 QualType Ty) const {
5443 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
5444 CGF.getContext().getTypeInfoInChars(Ty),
5445 CharUnits::fromQuantity(8),
5446 /*allowHigherAlign*/ false);
5449 //===----------------------------------------------------------------------===//
5450 // ARM ABI Implementation
5451 //===----------------------------------------------------------------------===//
5455 class ARMABIInfo : public SwiftABIInfo {
5468 ARMABIInfo(CodeGenTypes &CGT, ABIKind _Kind)
5469 : SwiftABIInfo(CGT), Kind(_Kind) {
5473 bool isEABI() const {
5474 switch (getTarget().getTriple().getEnvironment()) {
5475 case llvm::Triple::Android:
5476 case llvm::Triple::EABI:
5477 case llvm::Triple::EABIHF:
5478 case llvm::Triple::GNUEABI:
5479 case llvm::Triple::GNUEABIHF:
5480 case llvm::Triple::MuslEABI:
5481 case llvm::Triple::MuslEABIHF:
5488 bool isEABIHF() const {
5489 switch (getTarget().getTriple().getEnvironment()) {
5490 case llvm::Triple::EABIHF:
5491 case llvm::Triple::GNUEABIHF:
5492 case llvm::Triple::MuslEABIHF:
5499 ABIKind getABIKind() const { return Kind; }
5502 ABIArgInfo classifyReturnType(QualType RetTy, bool isVariadic) const;
5503 ABIArgInfo classifyArgumentType(QualType RetTy, bool isVariadic) const;
5504 bool isIllegalVectorType(QualType Ty) const;
5506 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
5507 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
5508 uint64_t Members) const override;
5510 void computeInfo(CGFunctionInfo &FI) const override;
5512 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5513 QualType Ty) const override;
5515 llvm::CallingConv::ID getLLVMDefaultCC() const;
5516 llvm::CallingConv::ID getABIDefaultCC() const;
5519 bool shouldPassIndirectlyForSwift(CharUnits totalSize,
5520 ArrayRef<llvm::Type*> scalars,
5521 bool asReturnValue) const override {
5522 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
5524 bool isSwiftErrorInRegister() const override {
5527 bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
5528 unsigned elts) const override;
5531 class ARMTargetCodeGenInfo : public TargetCodeGenInfo {
5533 ARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5534 :TargetCodeGenInfo(new ARMABIInfo(CGT, K)) {}
5536 const ARMABIInfo &getABIInfo() const {
5537 return static_cast<const ARMABIInfo&>(TargetCodeGenInfo::getABIInfo());
5540 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5544 StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
5545 return "mov\tr7, r7\t\t// marker for objc_retainAutoreleaseReturnValue";
5548 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5549 llvm::Value *Address) const override {
5550 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
5552 // 0-15 are the 16 integer registers.
5553 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 15);
5557 unsigned getSizeOfUnwindException() const override {
5558 if (getABIInfo().isEABI()) return 88;
5559 return TargetCodeGenInfo::getSizeOfUnwindException();
5562 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5563 CodeGen::CodeGenModule &CGM,
5564 ForDefinition_t IsForDefinition) const override {
5565 if (!IsForDefinition)
5567 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
5571 const ARMInterruptAttr *Attr = FD->getAttr<ARMInterruptAttr>();
5576 switch (Attr->getInterrupt()) {
5577 case ARMInterruptAttr::Generic: Kind = ""; break;
5578 case ARMInterruptAttr::IRQ: Kind = "IRQ"; break;
5579 case ARMInterruptAttr::FIQ: Kind = "FIQ"; break;
5580 case ARMInterruptAttr::SWI: Kind = "SWI"; break;
5581 case ARMInterruptAttr::ABORT: Kind = "ABORT"; break;
5582 case ARMInterruptAttr::UNDEF: Kind = "UNDEF"; break;
5585 llvm::Function *Fn = cast<llvm::Function>(GV);
5587 Fn->addFnAttr("interrupt", Kind);
5589 ARMABIInfo::ABIKind ABI = cast<ARMABIInfo>(getABIInfo()).getABIKind();
5590 if (ABI == ARMABIInfo::APCS)
5593 // AAPCS guarantees that sp will be 8-byte aligned on any public interface,
5594 // however this is not necessarily true on taking any interrupt. Instruct
5595 // the backend to perform a realignment as part of the function prologue.
5596 llvm::AttrBuilder B;
5597 B.addStackAlignmentAttr(8);
5598 Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
5602 class WindowsARMTargetCodeGenInfo : public ARMTargetCodeGenInfo {
5604 WindowsARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5605 : ARMTargetCodeGenInfo(CGT, K) {}
5607 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5608 CodeGen::CodeGenModule &CGM,
5609 ForDefinition_t IsForDefinition) const override;
5611 void getDependentLibraryOption(llvm::StringRef Lib,
5612 llvm::SmallString<24> &Opt) const override {
5613 Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
5616 void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
5617 llvm::SmallString<32> &Opt) const override {
5618 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
5622 void WindowsARMTargetCodeGenInfo::setTargetAttributes(
5623 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM,
5624 ForDefinition_t IsForDefinition) const {
5625 ARMTargetCodeGenInfo::setTargetAttributes(D, GV, CGM, IsForDefinition);
5626 if (!IsForDefinition)
5628 addStackProbeSizeTargetAttribute(D, GV, CGM);
5632 void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const {
5633 if (!getCXXABI().classifyReturnType(FI))
5634 FI.getReturnInfo() =
5635 classifyReturnType(FI.getReturnType(), FI.isVariadic());
5637 for (auto &I : FI.arguments())
5638 I.info = classifyArgumentType(I.type, FI.isVariadic());
5640 // Always honor user-specified calling convention.
5641 if (FI.getCallingConvention() != llvm::CallingConv::C)
5644 llvm::CallingConv::ID cc = getRuntimeCC();
5645 if (cc != llvm::CallingConv::C)
5646 FI.setEffectiveCallingConvention(cc);
5649 /// Return the default calling convention that LLVM will use.
5650 llvm::CallingConv::ID ARMABIInfo::getLLVMDefaultCC() const {
5651 // The default calling convention that LLVM will infer.
5652 if (isEABIHF() || getTarget().getTriple().isWatchABI())
5653 return llvm::CallingConv::ARM_AAPCS_VFP;
5655 return llvm::CallingConv::ARM_AAPCS;
5657 return llvm::CallingConv::ARM_APCS;
5660 /// Return the calling convention that our ABI would like us to use
5661 /// as the C calling convention.
5662 llvm::CallingConv::ID ARMABIInfo::getABIDefaultCC() const {
5663 switch (getABIKind()) {
5664 case APCS: return llvm::CallingConv::ARM_APCS;
5665 case AAPCS: return llvm::CallingConv::ARM_AAPCS;
5666 case AAPCS_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
5667 case AAPCS16_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
5669 llvm_unreachable("bad ABI kind");
5672 void ARMABIInfo::setCCs() {
5673 assert(getRuntimeCC() == llvm::CallingConv::C);
5675 // Don't muddy up the IR with a ton of explicit annotations if
5676 // they'd just match what LLVM will infer from the triple.
5677 llvm::CallingConv::ID abiCC = getABIDefaultCC();
5678 if (abiCC != getLLVMDefaultCC())
5681 // AAPCS apparently requires runtime support functions to be soft-float, but
5682 // that's almost certainly for historic reasons (Thumb1 not supporting VFP
5683 // most likely). It's more convenient for AAPCS16_VFP to be hard-float.
5685 // The Run-time ABI for the ARM Architecture section 4.1.2 requires
5686 // AEABI-complying FP helper functions to use the base AAPCS.
5687 // These AEABI functions are expanded in the ARM llvm backend, all the builtin
5688 // support functions emitted by clang such as the _Complex helpers follow the
5690 if (abiCC != getLLVMDefaultCC())
5694 ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty,
5695 bool isVariadic) const {
5696 // 6.1.2.1 The following argument types are VFP CPRCs:
5697 // A single-precision floating-point type (including promoted
5698 // half-precision types); A double-precision floating-point type;
5699 // A 64-bit or 128-bit containerized vector type; Homogeneous Aggregate
5700 // with a Base Type of a single- or double-precision floating-point type,
5701 // 64-bit containerized vectors or 128-bit containerized vectors with one
5702 // to four Elements.
5703 bool IsEffectivelyAAPCS_VFP = getABIKind() == AAPCS_VFP && !isVariadic;
5705 Ty = useFirstFieldIfTransparentUnion(Ty);
5707 // Handle illegal vector types here.
5708 if (isIllegalVectorType(Ty)) {
5709 uint64_t Size = getContext().getTypeSize(Ty);
5711 llvm::Type *ResType =
5712 llvm::Type::getInt32Ty(getVMContext());
5713 return ABIArgInfo::getDirect(ResType);
5716 llvm::Type *ResType = llvm::VectorType::get(
5717 llvm::Type::getInt32Ty(getVMContext()), 2);
5718 return ABIArgInfo::getDirect(ResType);
5721 llvm::Type *ResType = llvm::VectorType::get(
5722 llvm::Type::getInt32Ty(getVMContext()), 4);
5723 return ABIArgInfo::getDirect(ResType);
5725 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5728 // __fp16 gets passed as if it were an int or float, but with the top 16 bits
5729 // unspecified. This is not done for OpenCL as it handles the half type
5730 // natively, and does not need to interwork with AAPCS code.
5731 if (Ty->isHalfType() && !getContext().getLangOpts().NativeHalfArgsAndReturns) {
5732 llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
5733 llvm::Type::getFloatTy(getVMContext()) :
5734 llvm::Type::getInt32Ty(getVMContext());
5735 return ABIArgInfo::getDirect(ResType);
5738 if (!isAggregateTypeForABI(Ty)) {
5739 // Treat an enum type as its underlying type.
5740 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
5741 Ty = EnumTy->getDecl()->getIntegerType();
5744 return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend()
5745 : ABIArgInfo::getDirect());
5748 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
5749 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
5752 // Ignore empty records.
5753 if (isEmptyRecord(getContext(), Ty, true))
5754 return ABIArgInfo::getIgnore();
5756 if (IsEffectivelyAAPCS_VFP) {
5757 // Homogeneous Aggregates need to be expanded when we can fit the aggregate
5758 // into VFP registers.
5759 const Type *Base = nullptr;
5760 uint64_t Members = 0;
5761 if (isHomogeneousAggregate(Ty, Base, Members)) {
5762 assert(Base && "Base class should be set for homogeneous aggregate");
5763 // Base can be a floating-point or a vector.
5764 return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
5766 } else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) {
5767 // WatchOS does have homogeneous aggregates. Note that we intentionally use
5768 // this convention even for a variadic function: the backend will use GPRs
5770 const Type *Base = nullptr;
5771 uint64_t Members = 0;
5772 if (isHomogeneousAggregate(Ty, Base, Members)) {
5773 assert(Base && Members <= 4 && "unexpected homogeneous aggregate");
5775 llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members);
5776 return ABIArgInfo::getDirect(Ty, 0, nullptr, false);
5780 if (getABIKind() == ARMABIInfo::AAPCS16_VFP &&
5781 getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(16)) {
5782 // WatchOS is adopting the 64-bit AAPCS rule on composite types: if they're
5783 // bigger than 128-bits, they get placed in space allocated by the caller,
5784 // and a pointer is passed.
5785 return ABIArgInfo::getIndirect(
5786 CharUnits::fromQuantity(getContext().getTypeAlign(Ty) / 8), false);
5789 // Support byval for ARM.
5790 // The ABI alignment for APCS is 4-byte and for AAPCS at least 4-byte and at
5791 // most 8-byte. We realign the indirect argument if type alignment is bigger
5792 // than ABI alignment.
5793 uint64_t ABIAlign = 4;
5794 uint64_t TyAlign = getContext().getTypeAlign(Ty) / 8;
5795 if (getABIKind() == ARMABIInfo::AAPCS_VFP ||
5796 getABIKind() == ARMABIInfo::AAPCS)
5797 ABIAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8);
5799 if (getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(64)) {
5800 assert(getABIKind() != ARMABIInfo::AAPCS16_VFP && "unexpected byval");
5801 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(ABIAlign),
5803 /*Realign=*/TyAlign > ABIAlign);
5806 // On RenderScript, coerce Aggregates <= 64 bytes to an integer array of
5807 // same size and alignment.
5808 if (getTarget().isRenderScriptTarget()) {
5809 return coerceToIntArray(Ty, getContext(), getVMContext());
5812 // Otherwise, pass by coercing to a structure of the appropriate size.
5815 // FIXME: Try to match the types of the arguments more accurately where
5817 if (getContext().getTypeAlign(Ty) <= 32) {
5818 ElemTy = llvm::Type::getInt32Ty(getVMContext());
5819 SizeRegs = (getContext().getTypeSize(Ty) + 31) / 32;
5821 ElemTy = llvm::Type::getInt64Ty(getVMContext());
5822 SizeRegs = (getContext().getTypeSize(Ty) + 63) / 64;
5825 return ABIArgInfo::getDirect(llvm::ArrayType::get(ElemTy, SizeRegs));
5828 static bool isIntegerLikeType(QualType Ty, ASTContext &Context,
5829 llvm::LLVMContext &VMContext) {
5830 // APCS, C Language Calling Conventions, Non-Simple Return Values: A structure
5831 // is called integer-like if its size is less than or equal to one word, and
5832 // the offset of each of its addressable sub-fields is zero.
5834 uint64_t Size = Context.getTypeSize(Ty);
5836 // Check that the type fits in a word.
5840 // FIXME: Handle vector types!
5841 if (Ty->isVectorType())
5844 // Float types are never treated as "integer like".
5845 if (Ty->isRealFloatingType())
5848 // If this is a builtin or pointer type then it is ok.
5849 if (Ty->getAs<BuiltinType>() || Ty->isPointerType())
5852 // Small complex integer types are "integer like".
5853 if (const ComplexType *CT = Ty->getAs<ComplexType>())
5854 return isIntegerLikeType(CT->getElementType(), Context, VMContext);
5856 // Single element and zero sized arrays should be allowed, by the definition
5857 // above, but they are not.
5859 // Otherwise, it must be a record type.
5860 const RecordType *RT = Ty->getAs<RecordType>();
5861 if (!RT) return false;
5863 // Ignore records with flexible arrays.
5864 const RecordDecl *RD = RT->getDecl();
5865 if (RD->hasFlexibleArrayMember())
5868 // Check that all sub-fields are at offset 0, and are themselves "integer
5870 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
5872 bool HadField = false;
5874 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
5875 i != e; ++i, ++idx) {
5876 const FieldDecl *FD = *i;
5878 // Bit-fields are not addressable, we only need to verify they are "integer
5879 // like". We still have to disallow a subsequent non-bitfield, for example:
5880 // struct { int : 0; int x }
5881 // is non-integer like according to gcc.
5882 if (FD->isBitField()) {
5886 if (!isIntegerLikeType(FD->getType(), Context, VMContext))
5892 // Check if this field is at offset 0.
5893 if (Layout.getFieldOffset(idx) != 0)
5896 if (!isIntegerLikeType(FD->getType(), Context, VMContext))
5899 // Only allow at most one field in a structure. This doesn't match the
5900 // wording above, but follows gcc in situations with a field following an
5902 if (!RD->isUnion()) {
5913 ABIArgInfo ARMABIInfo::classifyReturnType(QualType RetTy,
5914 bool isVariadic) const {
5915 bool IsEffectivelyAAPCS_VFP =
5916 (getABIKind() == AAPCS_VFP || getABIKind() == AAPCS16_VFP) && !isVariadic;
5918 if (RetTy->isVoidType())
5919 return ABIArgInfo::getIgnore();
5921 // Large vector types should be returned via memory.
5922 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128) {
5923 return getNaturalAlignIndirect(RetTy);
5926 // __fp16 gets returned as if it were an int or float, but with the top 16
5927 // bits unspecified. This is not done for OpenCL as it handles the half type
5928 // natively, and does not need to interwork with AAPCS code.
5929 if (RetTy->isHalfType() && !getContext().getLangOpts().NativeHalfArgsAndReturns) {
5930 llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
5931 llvm::Type::getFloatTy(getVMContext()) :
5932 llvm::Type::getInt32Ty(getVMContext());
5933 return ABIArgInfo::getDirect(ResType);
5936 if (!isAggregateTypeForABI(RetTy)) {
5937 // Treat an enum type as its underlying type.
5938 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5939 RetTy = EnumTy->getDecl()->getIntegerType();
5941 return RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend()
5942 : ABIArgInfo::getDirect();
5945 // Are we following APCS?
5946 if (getABIKind() == APCS) {
5947 if (isEmptyRecord(getContext(), RetTy, false))
5948 return ABIArgInfo::getIgnore();
5950 // Complex types are all returned as packed integers.
5952 // FIXME: Consider using 2 x vector types if the back end handles them
5954 if (RetTy->isAnyComplexType())
5955 return ABIArgInfo::getDirect(llvm::IntegerType::get(
5956 getVMContext(), getContext().getTypeSize(RetTy)));
5958 // Integer like structures are returned in r0.
5959 if (isIntegerLikeType(RetTy, getContext(), getVMContext())) {
5960 // Return in the smallest viable integer type.
5961 uint64_t Size = getContext().getTypeSize(RetTy);
5963 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
5965 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
5966 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
5969 // Otherwise return in memory.
5970 return getNaturalAlignIndirect(RetTy);
5973 // Otherwise this is an AAPCS variant.
5975 if (isEmptyRecord(getContext(), RetTy, true))
5976 return ABIArgInfo::getIgnore();
5978 // Check for homogeneous aggregates with AAPCS-VFP.
5979 if (IsEffectivelyAAPCS_VFP) {
5980 const Type *Base = nullptr;
5981 uint64_t Members = 0;
5982 if (isHomogeneousAggregate(RetTy, Base, Members)) {
5983 assert(Base && "Base class should be set for homogeneous aggregate");
5984 // Homogeneous Aggregates are returned directly.
5985 return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
5989 // Aggregates <= 4 bytes are returned in r0; other aggregates
5990 // are returned indirectly.
5991 uint64_t Size = getContext().getTypeSize(RetTy);
5993 // On RenderScript, coerce Aggregates <= 4 bytes to an integer array of
5994 // same size and alignment.
5995 if (getTarget().isRenderScriptTarget()) {
5996 return coerceToIntArray(RetTy, getContext(), getVMContext());
5998 if (getDataLayout().isBigEndian())
5999 // Return in 32 bit integer integer type (as if loaded by LDR, AAPCS 5.4)
6000 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6002 // Return in the smallest viable integer type.
6004 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
6006 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
6007 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6008 } else if (Size <= 128 && getABIKind() == AAPCS16_VFP) {
6009 llvm::Type *Int32Ty = llvm::Type::getInt32Ty(getVMContext());
6010 llvm::Type *CoerceTy =
6011 llvm::ArrayType::get(Int32Ty, llvm::alignTo(Size, 32) / 32);
6012 return ABIArgInfo::getDirect(CoerceTy);
6015 return getNaturalAlignIndirect(RetTy);
6018 /// isIllegalVector - check whether Ty is an illegal vector type.
6019 bool ARMABIInfo::isIllegalVectorType(QualType Ty) const {
6020 if (const VectorType *VT = Ty->getAs<VectorType> ()) {
6022 // Android shipped using Clang 3.1, which supported a slightly different
6023 // vector ABI. The primary differences were that 3-element vector types
6024 // were legal, and so were sub 32-bit vectors (i.e. <2 x i8>). This path
6025 // accepts that legacy behavior for Android only.
6026 // Check whether VT is legal.
6027 unsigned NumElements = VT->getNumElements();
6028 // NumElements should be power of 2 or equal to 3.
6029 if (!llvm::isPowerOf2_32(NumElements) && NumElements != 3)
6032 // Check whether VT is legal.
6033 unsigned NumElements = VT->getNumElements();
6034 uint64_t Size = getContext().getTypeSize(VT);
6035 // NumElements should be power of 2.
6036 if (!llvm::isPowerOf2_32(NumElements))
6038 // Size should be greater than 32 bits.
6045 bool ARMABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize,
6047 unsigned numElts) const {
6048 if (!llvm::isPowerOf2_32(numElts))
6050 unsigned size = getDataLayout().getTypeStoreSizeInBits(eltTy);
6053 if (vectorSize.getQuantity() != 8 &&
6054 (vectorSize.getQuantity() != 16 || numElts == 1))
6059 bool ARMABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
6060 // Homogeneous aggregates for AAPCS-VFP must have base types of float,
6061 // double, or 64-bit or 128-bit vectors.
6062 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
6063 if (BT->getKind() == BuiltinType::Float ||
6064 BT->getKind() == BuiltinType::Double ||
6065 BT->getKind() == BuiltinType::LongDouble)
6067 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
6068 unsigned VecSize = getContext().getTypeSize(VT);
6069 if (VecSize == 64 || VecSize == 128)
6075 bool ARMABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
6076 uint64_t Members) const {
6077 return Members <= 4;
6080 Address ARMABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6081 QualType Ty) const {
6082 CharUnits SlotSize = CharUnits::fromQuantity(4);
6084 // Empty records are ignored for parameter passing purposes.
6085 if (isEmptyRecord(getContext(), Ty, true)) {
6086 Address Addr(CGF.Builder.CreateLoad(VAListAddr), SlotSize);
6087 Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
6091 auto TyInfo = getContext().getTypeInfoInChars(Ty);
6092 CharUnits TyAlignForABI = TyInfo.second;
6094 // Use indirect if size of the illegal vector is bigger than 16 bytes.
6095 bool IsIndirect = false;
6096 const Type *Base = nullptr;
6097 uint64_t Members = 0;
6098 if (TyInfo.first > CharUnits::fromQuantity(16) && isIllegalVectorType(Ty)) {
6101 // ARMv7k passes structs bigger than 16 bytes indirectly, in space
6102 // allocated by the caller.
6103 } else if (TyInfo.first > CharUnits::fromQuantity(16) &&
6104 getABIKind() == ARMABIInfo::AAPCS16_VFP &&
6105 !isHomogeneousAggregate(Ty, Base, Members)) {
6108 // Otherwise, bound the type's ABI alignment.
6109 // The ABI alignment for 64-bit or 128-bit vectors is 8 for AAPCS and 4 for
6110 // APCS. For AAPCS, the ABI alignment is at least 4-byte and at most 8-byte.
6111 // Our callers should be prepared to handle an under-aligned address.
6112 } else if (getABIKind() == ARMABIInfo::AAPCS_VFP ||
6113 getABIKind() == ARMABIInfo::AAPCS) {
6114 TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
6115 TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(8));
6116 } else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) {
6117 // ARMv7k allows type alignment up to 16 bytes.
6118 TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
6119 TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(16));
6121 TyAlignForABI = CharUnits::fromQuantity(4);
6123 TyInfo.second = TyAlignForABI;
6125 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, TyInfo,
6126 SlotSize, /*AllowHigherAlign*/ true);
6129 //===----------------------------------------------------------------------===//
6130 // NVPTX ABI Implementation
6131 //===----------------------------------------------------------------------===//
6135 class NVPTXABIInfo : public ABIInfo {
6137 NVPTXABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
6139 ABIArgInfo classifyReturnType(QualType RetTy) const;
6140 ABIArgInfo classifyArgumentType(QualType Ty) const;
6142 void computeInfo(CGFunctionInfo &FI) const override;
6143 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6144 QualType Ty) const override;
6147 class NVPTXTargetCodeGenInfo : public TargetCodeGenInfo {
6149 NVPTXTargetCodeGenInfo(CodeGenTypes &CGT)
6150 : TargetCodeGenInfo(new NVPTXABIInfo(CGT)) {}
6152 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6153 CodeGen::CodeGenModule &M,
6154 ForDefinition_t IsForDefinition) const override;
6157 // Adds a NamedMDNode with F, Name, and Operand as operands, and adds the
6158 // resulting MDNode to the nvvm.annotations MDNode.
6159 static void addNVVMMetadata(llvm::Function *F, StringRef Name, int Operand);
6162 ABIArgInfo NVPTXABIInfo::classifyReturnType(QualType RetTy) const {
6163 if (RetTy->isVoidType())
6164 return ABIArgInfo::getIgnore();
6166 // note: this is different from default ABI
6167 if (!RetTy->isScalarType())
6168 return ABIArgInfo::getDirect();
6170 // Treat an enum type as its underlying type.
6171 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
6172 RetTy = EnumTy->getDecl()->getIntegerType();
6174 return (RetTy->isPromotableIntegerType() ?
6175 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6178 ABIArgInfo NVPTXABIInfo::classifyArgumentType(QualType Ty) const {
6179 // Treat an enum type as its underlying type.
6180 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6181 Ty = EnumTy->getDecl()->getIntegerType();
6183 // Return aggregates type as indirect by value
6184 if (isAggregateTypeForABI(Ty))
6185 return getNaturalAlignIndirect(Ty, /* byval */ true);
6187 return (Ty->isPromotableIntegerType() ?
6188 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6191 void NVPTXABIInfo::computeInfo(CGFunctionInfo &FI) const {
6192 if (!getCXXABI().classifyReturnType(FI))
6193 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
6194 for (auto &I : FI.arguments())
6195 I.info = classifyArgumentType(I.type);
6197 // Always honor user-specified calling convention.
6198 if (FI.getCallingConvention() != llvm::CallingConv::C)
6201 FI.setEffectiveCallingConvention(getRuntimeCC());
6204 Address NVPTXABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6205 QualType Ty) const {
6206 llvm_unreachable("NVPTX does not support varargs");
6209 void NVPTXTargetCodeGenInfo::setTargetAttributes(
6210 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M,
6211 ForDefinition_t IsForDefinition) const {
6212 if (!IsForDefinition)
6214 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
6217 llvm::Function *F = cast<llvm::Function>(GV);
6219 // Perform special handling in OpenCL mode
6220 if (M.getLangOpts().OpenCL) {
6221 // Use OpenCL function attributes to check for kernel functions
6222 // By default, all functions are device functions
6223 if (FD->hasAttr<OpenCLKernelAttr>()) {
6224 // OpenCL __kernel functions get kernel metadata
6225 // Create !{<func-ref>, metadata !"kernel", i32 1} node
6226 addNVVMMetadata(F, "kernel", 1);
6227 // And kernel functions are not subject to inlining
6228 F->addFnAttr(llvm::Attribute::NoInline);
6232 // Perform special handling in CUDA mode.
6233 if (M.getLangOpts().CUDA) {
6234 // CUDA __global__ functions get a kernel metadata entry. Since
6235 // __global__ functions cannot be called from the device, we do not
6236 // need to set the noinline attribute.
6237 if (FD->hasAttr<CUDAGlobalAttr>()) {
6238 // Create !{<func-ref>, metadata !"kernel", i32 1} node
6239 addNVVMMetadata(F, "kernel", 1);
6241 if (CUDALaunchBoundsAttr *Attr = FD->getAttr<CUDALaunchBoundsAttr>()) {
6242 // Create !{<func-ref>, metadata !"maxntidx", i32 <val>} node
6243 llvm::APSInt MaxThreads(32);
6244 MaxThreads = Attr->getMaxThreads()->EvaluateKnownConstInt(M.getContext());
6246 addNVVMMetadata(F, "maxntidx", MaxThreads.getExtValue());
6248 // min blocks is an optional argument for CUDALaunchBoundsAttr. If it was
6249 // not specified in __launch_bounds__ or if the user specified a 0 value,
6250 // we don't have to add a PTX directive.
6251 if (Attr->getMinBlocks()) {
6252 llvm::APSInt MinBlocks(32);
6253 MinBlocks = Attr->getMinBlocks()->EvaluateKnownConstInt(M.getContext());
6255 // Create !{<func-ref>, metadata !"minctasm", i32 <val>} node
6256 addNVVMMetadata(F, "minctasm", MinBlocks.getExtValue());
6262 void NVPTXTargetCodeGenInfo::addNVVMMetadata(llvm::Function *F, StringRef Name,
6264 llvm::Module *M = F->getParent();
6265 llvm::LLVMContext &Ctx = M->getContext();
6267 // Get "nvvm.annotations" metadata node
6268 llvm::NamedMDNode *MD = M->getOrInsertNamedMetadata("nvvm.annotations");
6270 llvm::Metadata *MDVals[] = {
6271 llvm::ConstantAsMetadata::get(F), llvm::MDString::get(Ctx, Name),
6272 llvm::ConstantAsMetadata::get(
6273 llvm::ConstantInt::get(llvm::Type::getInt32Ty(Ctx), Operand))};
6274 // Append metadata to nvvm.annotations
6275 MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
6279 //===----------------------------------------------------------------------===//
6280 // SystemZ ABI Implementation
6281 //===----------------------------------------------------------------------===//
6285 class SystemZABIInfo : public SwiftABIInfo {
6289 SystemZABIInfo(CodeGenTypes &CGT, bool HV)
6290 : SwiftABIInfo(CGT), HasVector(HV) {}
6292 bool isPromotableIntegerType(QualType Ty) const;
6293 bool isCompoundType(QualType Ty) const;
6294 bool isVectorArgumentType(QualType Ty) const;
6295 bool isFPArgumentType(QualType Ty) const;
6296 QualType GetSingleElementType(QualType Ty) const;
6298 ABIArgInfo classifyReturnType(QualType RetTy) const;
6299 ABIArgInfo classifyArgumentType(QualType ArgTy) const;
6301 void computeInfo(CGFunctionInfo &FI) const override {
6302 if (!getCXXABI().classifyReturnType(FI))
6303 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
6304 for (auto &I : FI.arguments())
6305 I.info = classifyArgumentType(I.type);
6308 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6309 QualType Ty) const override;
6311 bool shouldPassIndirectlyForSwift(CharUnits totalSize,
6312 ArrayRef<llvm::Type*> scalars,
6313 bool asReturnValue) const override {
6314 return occupiesMoreThan(CGT, scalars, /*total*/ 4);
6316 bool isSwiftErrorInRegister() const override {
6321 class SystemZTargetCodeGenInfo : public TargetCodeGenInfo {
6323 SystemZTargetCodeGenInfo(CodeGenTypes &CGT, bool HasVector)
6324 : TargetCodeGenInfo(new SystemZABIInfo(CGT, HasVector)) {}
6329 bool SystemZABIInfo::isPromotableIntegerType(QualType Ty) const {
6330 // Treat an enum type as its underlying type.
6331 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6332 Ty = EnumTy->getDecl()->getIntegerType();
6334 // Promotable integer types are required to be promoted by the ABI.
6335 if (Ty->isPromotableIntegerType())
6338 // 32-bit values must also be promoted.
6339 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
6340 switch (BT->getKind()) {
6341 case BuiltinType::Int:
6342 case BuiltinType::UInt:
6350 bool SystemZABIInfo::isCompoundType(QualType Ty) const {
6351 return (Ty->isAnyComplexType() ||
6352 Ty->isVectorType() ||
6353 isAggregateTypeForABI(Ty));
6356 bool SystemZABIInfo::isVectorArgumentType(QualType Ty) const {
6357 return (HasVector &&
6358 Ty->isVectorType() &&
6359 getContext().getTypeSize(Ty) <= 128);
6362 bool SystemZABIInfo::isFPArgumentType(QualType Ty) const {
6363 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
6364 switch (BT->getKind()) {
6365 case BuiltinType::Float:
6366 case BuiltinType::Double:
6375 QualType SystemZABIInfo::GetSingleElementType(QualType Ty) const {
6376 if (const RecordType *RT = Ty->getAsStructureType()) {
6377 const RecordDecl *RD = RT->getDecl();
6380 // If this is a C++ record, check the bases first.
6381 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
6382 for (const auto &I : CXXRD->bases()) {
6383 QualType Base = I.getType();
6385 // Empty bases don't affect things either way.
6386 if (isEmptyRecord(getContext(), Base, true))
6389 if (!Found.isNull())
6391 Found = GetSingleElementType(Base);
6394 // Check the fields.
6395 for (const auto *FD : RD->fields()) {
6396 // For compatibility with GCC, ignore empty bitfields in C++ mode.
6397 // Unlike isSingleElementStruct(), empty structure and array fields
6398 // do count. So do anonymous bitfields that aren't zero-sized.
6399 if (getContext().getLangOpts().CPlusPlus &&
6400 FD->isBitField() && FD->getBitWidthValue(getContext()) == 0)
6403 // Unlike isSingleElementStruct(), arrays do not count.
6404 // Nested structures still do though.
6405 if (!Found.isNull())
6407 Found = GetSingleElementType(FD->getType());
6410 // Unlike isSingleElementStruct(), trailing padding is allowed.
6411 // An 8-byte aligned struct s { float f; } is passed as a double.
6412 if (!Found.isNull())
6419 Address SystemZABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6420 QualType Ty) const {
6421 // Assume that va_list type is correct; should be pointer to LLVM type:
6425 // i8 *__overflow_arg_area;
6426 // i8 *__reg_save_area;
6429 // Every non-vector argument occupies 8 bytes and is passed by preference
6430 // in either GPRs or FPRs. Vector arguments occupy 8 or 16 bytes and are
6431 // always passed on the stack.
6432 Ty = getContext().getCanonicalType(Ty);
6433 auto TyInfo = getContext().getTypeInfoInChars(Ty);
6434 llvm::Type *ArgTy = CGF.ConvertTypeForMem(Ty);
6435 llvm::Type *DirectTy = ArgTy;
6436 ABIArgInfo AI = classifyArgumentType(Ty);
6437 bool IsIndirect = AI.isIndirect();
6438 bool InFPRs = false;
6439 bool IsVector = false;
6440 CharUnits UnpaddedSize;
6441 CharUnits DirectAlign;
6443 DirectTy = llvm::PointerType::getUnqual(DirectTy);
6444 UnpaddedSize = DirectAlign = CharUnits::fromQuantity(8);
6446 if (AI.getCoerceToType())
6447 ArgTy = AI.getCoerceToType();
6448 InFPRs = ArgTy->isFloatTy() || ArgTy->isDoubleTy();
6449 IsVector = ArgTy->isVectorTy();
6450 UnpaddedSize = TyInfo.first;
6451 DirectAlign = TyInfo.second;
6453 CharUnits PaddedSize = CharUnits::fromQuantity(8);
6454 if (IsVector && UnpaddedSize > PaddedSize)
6455 PaddedSize = CharUnits::fromQuantity(16);
6456 assert((UnpaddedSize <= PaddedSize) && "Invalid argument size.");
6458 CharUnits Padding = (PaddedSize - UnpaddedSize);
6460 llvm::Type *IndexTy = CGF.Int64Ty;
6461 llvm::Value *PaddedSizeV =
6462 llvm::ConstantInt::get(IndexTy, PaddedSize.getQuantity());
6465 // Work out the address of a vector argument on the stack.
6466 // Vector arguments are always passed in the high bits of a
6467 // single (8 byte) or double (16 byte) stack slot.
6468 Address OverflowArgAreaPtr =
6469 CGF.Builder.CreateStructGEP(VAListAddr, 2, CharUnits::fromQuantity(16),
6470 "overflow_arg_area_ptr");
6471 Address OverflowArgArea =
6472 Address(CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"),
6475 CGF.Builder.CreateElementBitCast(OverflowArgArea, DirectTy, "mem_addr");
6477 // Update overflow_arg_area_ptr pointer
6478 llvm::Value *NewOverflowArgArea =
6479 CGF.Builder.CreateGEP(OverflowArgArea.getPointer(), PaddedSizeV,
6480 "overflow_arg_area");
6481 CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
6486 assert(PaddedSize.getQuantity() == 8);
6488 unsigned MaxRegs, RegCountField, RegSaveIndex;
6489 CharUnits RegPadding;
6491 MaxRegs = 4; // Maximum of 4 FPR arguments
6492 RegCountField = 1; // __fpr
6493 RegSaveIndex = 16; // save offset for f0
6494 RegPadding = CharUnits(); // floats are passed in the high bits of an FPR
6496 MaxRegs = 5; // Maximum of 5 GPR arguments
6497 RegCountField = 0; // __gpr
6498 RegSaveIndex = 2; // save offset for r2
6499 RegPadding = Padding; // values are passed in the low bits of a GPR
6502 Address RegCountPtr = CGF.Builder.CreateStructGEP(
6503 VAListAddr, RegCountField, RegCountField * CharUnits::fromQuantity(8),
6505 llvm::Value *RegCount = CGF.Builder.CreateLoad(RegCountPtr, "reg_count");
6506 llvm::Value *MaxRegsV = llvm::ConstantInt::get(IndexTy, MaxRegs);
6507 llvm::Value *InRegs = CGF.Builder.CreateICmpULT(RegCount, MaxRegsV,
6510 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
6511 llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
6512 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
6513 CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
6515 // Emit code to load the value if it was passed in registers.
6516 CGF.EmitBlock(InRegBlock);
6518 // Work out the address of an argument register.
6519 llvm::Value *ScaledRegCount =
6520 CGF.Builder.CreateMul(RegCount, PaddedSizeV, "scaled_reg_count");
6521 llvm::Value *RegBase =
6522 llvm::ConstantInt::get(IndexTy, RegSaveIndex * PaddedSize.getQuantity()
6523 + RegPadding.getQuantity());
6524 llvm::Value *RegOffset =
6525 CGF.Builder.CreateAdd(ScaledRegCount, RegBase, "reg_offset");
6526 Address RegSaveAreaPtr =
6527 CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(24),
6528 "reg_save_area_ptr");
6529 llvm::Value *RegSaveArea =
6530 CGF.Builder.CreateLoad(RegSaveAreaPtr, "reg_save_area");
6531 Address RawRegAddr(CGF.Builder.CreateGEP(RegSaveArea, RegOffset,
6535 CGF.Builder.CreateElementBitCast(RawRegAddr, DirectTy, "reg_addr");
6537 // Update the register count
6538 llvm::Value *One = llvm::ConstantInt::get(IndexTy, 1);
6539 llvm::Value *NewRegCount =
6540 CGF.Builder.CreateAdd(RegCount, One, "reg_count");
6541 CGF.Builder.CreateStore(NewRegCount, RegCountPtr);
6542 CGF.EmitBranch(ContBlock);
6544 // Emit code to load the value if it was passed in memory.
6545 CGF.EmitBlock(InMemBlock);
6547 // Work out the address of a stack argument.
6548 Address OverflowArgAreaPtr = CGF.Builder.CreateStructGEP(
6549 VAListAddr, 2, CharUnits::fromQuantity(16), "overflow_arg_area_ptr");
6550 Address OverflowArgArea =
6551 Address(CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"),
6553 Address RawMemAddr =
6554 CGF.Builder.CreateConstByteGEP(OverflowArgArea, Padding, "raw_mem_addr");
6556 CGF.Builder.CreateElementBitCast(RawMemAddr, DirectTy, "mem_addr");
6558 // Update overflow_arg_area_ptr pointer
6559 llvm::Value *NewOverflowArgArea =
6560 CGF.Builder.CreateGEP(OverflowArgArea.getPointer(), PaddedSizeV,
6561 "overflow_arg_area");
6562 CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
6563 CGF.EmitBranch(ContBlock);
6565 // Return the appropriate result.
6566 CGF.EmitBlock(ContBlock);
6567 Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
6568 MemAddr, InMemBlock, "va_arg.addr");
6571 ResAddr = Address(CGF.Builder.CreateLoad(ResAddr, "indirect_arg"),
6577 ABIArgInfo SystemZABIInfo::classifyReturnType(QualType RetTy) const {
6578 if (RetTy->isVoidType())
6579 return ABIArgInfo::getIgnore();
6580 if (isVectorArgumentType(RetTy))
6581 return ABIArgInfo::getDirect();
6582 if (isCompoundType(RetTy) || getContext().getTypeSize(RetTy) > 64)
6583 return getNaturalAlignIndirect(RetTy);
6584 return (isPromotableIntegerType(RetTy) ?
6585 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6588 ABIArgInfo SystemZABIInfo::classifyArgumentType(QualType Ty) const {
6589 // Handle the generic C++ ABI.
6590 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
6591 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
6593 // Integers and enums are extended to full register width.
6594 if (isPromotableIntegerType(Ty))
6595 return ABIArgInfo::getExtend();
6597 // Handle vector types and vector-like structure types. Note that
6598 // as opposed to float-like structure types, we do not allow any
6599 // padding for vector-like structures, so verify the sizes match.
6600 uint64_t Size = getContext().getTypeSize(Ty);
6601 QualType SingleElementTy = GetSingleElementType(Ty);
6602 if (isVectorArgumentType(SingleElementTy) &&
6603 getContext().getTypeSize(SingleElementTy) == Size)
6604 return ABIArgInfo::getDirect(CGT.ConvertType(SingleElementTy));
6606 // Values that are not 1, 2, 4 or 8 bytes in size are passed indirectly.
6607 if (Size != 8 && Size != 16 && Size != 32 && Size != 64)
6608 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6610 // Handle small structures.
6611 if (const RecordType *RT = Ty->getAs<RecordType>()) {
6612 // Structures with flexible arrays have variable length, so really
6613 // fail the size test above.
6614 const RecordDecl *RD = RT->getDecl();
6615 if (RD->hasFlexibleArrayMember())
6616 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6618 // The structure is passed as an unextended integer, a float, or a double.
6620 if (isFPArgumentType(SingleElementTy)) {
6621 assert(Size == 32 || Size == 64);
6623 PassTy = llvm::Type::getFloatTy(getVMContext());
6625 PassTy = llvm::Type::getDoubleTy(getVMContext());
6627 PassTy = llvm::IntegerType::get(getVMContext(), Size);
6628 return ABIArgInfo::getDirect(PassTy);
6631 // Non-structure compounds are passed indirectly.
6632 if (isCompoundType(Ty))
6633 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6635 return ABIArgInfo::getDirect(nullptr);
6638 //===----------------------------------------------------------------------===//
6639 // MSP430 ABI Implementation
6640 //===----------------------------------------------------------------------===//
6644 class MSP430TargetCodeGenInfo : public TargetCodeGenInfo {
6646 MSP430TargetCodeGenInfo(CodeGenTypes &CGT)
6647 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
6648 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6649 CodeGen::CodeGenModule &M,
6650 ForDefinition_t IsForDefinition) const override;
6655 void MSP430TargetCodeGenInfo::setTargetAttributes(
6656 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M,
6657 ForDefinition_t IsForDefinition) const {
6658 if (!IsForDefinition)
6660 if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
6661 if (const MSP430InterruptAttr *attr = FD->getAttr<MSP430InterruptAttr>()) {
6662 // Handle 'interrupt' attribute:
6663 llvm::Function *F = cast<llvm::Function>(GV);
6665 // Step 1: Set ISR calling convention.
6666 F->setCallingConv(llvm::CallingConv::MSP430_INTR);
6668 // Step 2: Add attributes goodness.
6669 F->addFnAttr(llvm::Attribute::NoInline);
6671 // Step 3: Emit ISR vector alias.
6672 unsigned Num = attr->getNumber() / 2;
6673 llvm::GlobalAlias::create(llvm::Function::ExternalLinkage,
6674 "__isr_" + Twine(Num), F);
6679 //===----------------------------------------------------------------------===//
6680 // MIPS ABI Implementation. This works for both little-endian and
6681 // big-endian variants.
6682 //===----------------------------------------------------------------------===//
6685 class MipsABIInfo : public ABIInfo {
6687 unsigned MinABIStackAlignInBytes, StackAlignInBytes;
6688 void CoerceToIntArgs(uint64_t TySize,
6689 SmallVectorImpl<llvm::Type *> &ArgList) const;
6690 llvm::Type* HandleAggregates(QualType Ty, uint64_t TySize) const;
6691 llvm::Type* returnAggregateInRegs(QualType RetTy, uint64_t Size) const;
6692 llvm::Type* getPaddingType(uint64_t Align, uint64_t Offset) const;
6694 MipsABIInfo(CodeGenTypes &CGT, bool _IsO32) :
6695 ABIInfo(CGT), IsO32(_IsO32), MinABIStackAlignInBytes(IsO32 ? 4 : 8),
6696 StackAlignInBytes(IsO32 ? 8 : 16) {}
6698 ABIArgInfo classifyReturnType(QualType RetTy) const;
6699 ABIArgInfo classifyArgumentType(QualType RetTy, uint64_t &Offset) const;
6700 void computeInfo(CGFunctionInfo &FI) const override;
6701 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6702 QualType Ty) const override;
6703 bool shouldSignExtUnsignedType(QualType Ty) const override;
6706 class MIPSTargetCodeGenInfo : public TargetCodeGenInfo {
6707 unsigned SizeOfUnwindException;
6709 MIPSTargetCodeGenInfo(CodeGenTypes &CGT, bool IsO32)
6710 : TargetCodeGenInfo(new MipsABIInfo(CGT, IsO32)),
6711 SizeOfUnwindException(IsO32 ? 24 : 32) {}
6713 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
6717 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6718 CodeGen::CodeGenModule &CGM,
6719 ForDefinition_t IsForDefinition) const override {
6720 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
6722 llvm::Function *Fn = cast<llvm::Function>(GV);
6724 if (FD->hasAttr<MipsLongCallAttr>())
6725 Fn->addFnAttr("long-call");
6726 else if (FD->hasAttr<MipsShortCallAttr>())
6727 Fn->addFnAttr("short-call");
6729 // Other attributes do not have a meaning for declarations.
6730 if (!IsForDefinition)
6733 if (FD->hasAttr<Mips16Attr>()) {
6734 Fn->addFnAttr("mips16");
6736 else if (FD->hasAttr<NoMips16Attr>()) {
6737 Fn->addFnAttr("nomips16");
6740 if (FD->hasAttr<MicroMipsAttr>())
6741 Fn->addFnAttr("micromips");
6742 else if (FD->hasAttr<NoMicroMipsAttr>())
6743 Fn->addFnAttr("nomicromips");
6745 const MipsInterruptAttr *Attr = FD->getAttr<MipsInterruptAttr>();
6750 switch (Attr->getInterrupt()) {
6751 case MipsInterruptAttr::eic: Kind = "eic"; break;
6752 case MipsInterruptAttr::sw0: Kind = "sw0"; break;
6753 case MipsInterruptAttr::sw1: Kind = "sw1"; break;
6754 case MipsInterruptAttr::hw0: Kind = "hw0"; break;
6755 case MipsInterruptAttr::hw1: Kind = "hw1"; break;
6756 case MipsInterruptAttr::hw2: Kind = "hw2"; break;
6757 case MipsInterruptAttr::hw3: Kind = "hw3"; break;
6758 case MipsInterruptAttr::hw4: Kind = "hw4"; break;
6759 case MipsInterruptAttr::hw5: Kind = "hw5"; break;
6762 Fn->addFnAttr("interrupt", Kind);
6766 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
6767 llvm::Value *Address) const override;
6769 unsigned getSizeOfUnwindException() const override {
6770 return SizeOfUnwindException;
6775 void MipsABIInfo::CoerceToIntArgs(
6776 uint64_t TySize, SmallVectorImpl<llvm::Type *> &ArgList) const {
6777 llvm::IntegerType *IntTy =
6778 llvm::IntegerType::get(getVMContext(), MinABIStackAlignInBytes * 8);
6780 // Add (TySize / MinABIStackAlignInBytes) args of IntTy.
6781 for (unsigned N = TySize / (MinABIStackAlignInBytes * 8); N; --N)
6782 ArgList.push_back(IntTy);
6784 // If necessary, add one more integer type to ArgList.
6785 unsigned R = TySize % (MinABIStackAlignInBytes * 8);
6788 ArgList.push_back(llvm::IntegerType::get(getVMContext(), R));
6791 // In N32/64, an aligned double precision floating point field is passed in
6793 llvm::Type* MipsABIInfo::HandleAggregates(QualType Ty, uint64_t TySize) const {
6794 SmallVector<llvm::Type*, 8> ArgList, IntArgList;
6797 CoerceToIntArgs(TySize, ArgList);
6798 return llvm::StructType::get(getVMContext(), ArgList);
6801 if (Ty->isComplexType())
6802 return CGT.ConvertType(Ty);
6804 const RecordType *RT = Ty->getAs<RecordType>();
6806 // Unions/vectors are passed in integer registers.
6807 if (!RT || !RT->isStructureOrClassType()) {
6808 CoerceToIntArgs(TySize, ArgList);
6809 return llvm::StructType::get(getVMContext(), ArgList);
6812 const RecordDecl *RD = RT->getDecl();
6813 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
6814 assert(!(TySize % 8) && "Size of structure must be multiple of 8.");
6816 uint64_t LastOffset = 0;
6818 llvm::IntegerType *I64 = llvm::IntegerType::get(getVMContext(), 64);
6820 // Iterate over fields in the struct/class and check if there are any aligned
6822 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
6823 i != e; ++i, ++idx) {
6824 const QualType Ty = i->getType();
6825 const BuiltinType *BT = Ty->getAs<BuiltinType>();
6827 if (!BT || BT->getKind() != BuiltinType::Double)
6830 uint64_t Offset = Layout.getFieldOffset(idx);
6831 if (Offset % 64) // Ignore doubles that are not aligned.
6834 // Add ((Offset - LastOffset) / 64) args of type i64.
6835 for (unsigned j = (Offset - LastOffset) / 64; j > 0; --j)
6836 ArgList.push_back(I64);
6839 ArgList.push_back(llvm::Type::getDoubleTy(getVMContext()));
6840 LastOffset = Offset + 64;
6843 CoerceToIntArgs(TySize - LastOffset, IntArgList);
6844 ArgList.append(IntArgList.begin(), IntArgList.end());
6846 return llvm::StructType::get(getVMContext(), ArgList);
6849 llvm::Type *MipsABIInfo::getPaddingType(uint64_t OrigOffset,
6850 uint64_t Offset) const {
6851 if (OrigOffset + MinABIStackAlignInBytes > Offset)
6854 return llvm::IntegerType::get(getVMContext(), (Offset - OrigOffset) * 8);
6858 MipsABIInfo::classifyArgumentType(QualType Ty, uint64_t &Offset) const {
6859 Ty = useFirstFieldIfTransparentUnion(Ty);
6861 uint64_t OrigOffset = Offset;
6862 uint64_t TySize = getContext().getTypeSize(Ty);
6863 uint64_t Align = getContext().getTypeAlign(Ty) / 8;
6865 Align = std::min(std::max(Align, (uint64_t)MinABIStackAlignInBytes),
6866 (uint64_t)StackAlignInBytes);
6867 unsigned CurrOffset = llvm::alignTo(Offset, Align);
6868 Offset = CurrOffset + llvm::alignTo(TySize, Align * 8) / 8;
6870 if (isAggregateTypeForABI(Ty) || Ty->isVectorType()) {
6871 // Ignore empty aggregates.
6873 return ABIArgInfo::getIgnore();
6875 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
6876 Offset = OrigOffset + MinABIStackAlignInBytes;
6877 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
6880 // If we have reached here, aggregates are passed directly by coercing to
6881 // another structure type. Padding is inserted if the offset of the
6882 // aggregate is unaligned.
6883 ABIArgInfo ArgInfo =
6884 ABIArgInfo::getDirect(HandleAggregates(Ty, TySize), 0,
6885 getPaddingType(OrigOffset, CurrOffset));
6886 ArgInfo.setInReg(true);
6890 // Treat an enum type as its underlying type.
6891 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6892 Ty = EnumTy->getDecl()->getIntegerType();
6894 // All integral types are promoted to the GPR width.
6895 if (Ty->isIntegralOrEnumerationType())
6896 return ABIArgInfo::getExtend();
6898 return ABIArgInfo::getDirect(
6899 nullptr, 0, IsO32 ? nullptr : getPaddingType(OrigOffset, CurrOffset));
6903 MipsABIInfo::returnAggregateInRegs(QualType RetTy, uint64_t Size) const {
6904 const RecordType *RT = RetTy->getAs<RecordType>();
6905 SmallVector<llvm::Type*, 8> RTList;
6907 if (RT && RT->isStructureOrClassType()) {
6908 const RecordDecl *RD = RT->getDecl();
6909 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
6910 unsigned FieldCnt = Layout.getFieldCount();
6912 // N32/64 returns struct/classes in floating point registers if the
6913 // following conditions are met:
6914 // 1. The size of the struct/class is no larger than 128-bit.
6915 // 2. The struct/class has one or two fields all of which are floating
6917 // 3. The offset of the first field is zero (this follows what gcc does).
6919 // Any other composite results are returned in integer registers.
6921 if (FieldCnt && (FieldCnt <= 2) && !Layout.getFieldOffset(0)) {
6922 RecordDecl::field_iterator b = RD->field_begin(), e = RD->field_end();
6923 for (; b != e; ++b) {
6924 const BuiltinType *BT = b->getType()->getAs<BuiltinType>();
6926 if (!BT || !BT->isFloatingPoint())
6929 RTList.push_back(CGT.ConvertType(b->getType()));
6933 return llvm::StructType::get(getVMContext(), RTList,
6934 RD->hasAttr<PackedAttr>());
6940 CoerceToIntArgs(Size, RTList);
6941 return llvm::StructType::get(getVMContext(), RTList);
6944 ABIArgInfo MipsABIInfo::classifyReturnType(QualType RetTy) const {
6945 uint64_t Size = getContext().getTypeSize(RetTy);
6947 if (RetTy->isVoidType())
6948 return ABIArgInfo::getIgnore();
6950 // O32 doesn't treat zero-sized structs differently from other structs.
6951 // However, N32/N64 ignores zero sized return values.
6952 if (!IsO32 && Size == 0)
6953 return ABIArgInfo::getIgnore();
6955 if (isAggregateTypeForABI(RetTy) || RetTy->isVectorType()) {
6957 if (RetTy->isAnyComplexType())
6958 return ABIArgInfo::getDirect();
6960 // O32 returns integer vectors in registers and N32/N64 returns all small
6961 // aggregates in registers.
6963 (RetTy->isVectorType() && !RetTy->hasFloatingRepresentation())) {
6964 ABIArgInfo ArgInfo =
6965 ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size));
6966 ArgInfo.setInReg(true);
6971 return getNaturalAlignIndirect(RetTy);
6974 // Treat an enum type as its underlying type.
6975 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
6976 RetTy = EnumTy->getDecl()->getIntegerType();
6978 return (RetTy->isPromotableIntegerType() ?
6979 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6982 void MipsABIInfo::computeInfo(CGFunctionInfo &FI) const {
6983 ABIArgInfo &RetInfo = FI.getReturnInfo();
6984 if (!getCXXABI().classifyReturnType(FI))
6985 RetInfo = classifyReturnType(FI.getReturnType());
6987 // Check if a pointer to an aggregate is passed as a hidden argument.
6988 uint64_t Offset = RetInfo.isIndirect() ? MinABIStackAlignInBytes : 0;
6990 for (auto &I : FI.arguments())
6991 I.info = classifyArgumentType(I.type, Offset);
6994 Address MipsABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6995 QualType OrigTy) const {
6996 QualType Ty = OrigTy;
6998 // Integer arguments are promoted to 32-bit on O32 and 64-bit on N32/N64.
6999 // Pointers are also promoted in the same way but this only matters for N32.
7000 unsigned SlotSizeInBits = IsO32 ? 32 : 64;
7001 unsigned PtrWidth = getTarget().getPointerWidth(0);
7002 bool DidPromote = false;
7003 if ((Ty->isIntegerType() &&
7004 getContext().getIntWidth(Ty) < SlotSizeInBits) ||
7005 (Ty->isPointerType() && PtrWidth < SlotSizeInBits)) {
7007 Ty = getContext().getIntTypeForBitwidth(SlotSizeInBits,
7008 Ty->isSignedIntegerType());
7011 auto TyInfo = getContext().getTypeInfoInChars(Ty);
7013 // The alignment of things in the argument area is never larger than
7014 // StackAlignInBytes.
7016 std::min(TyInfo.second, CharUnits::fromQuantity(StackAlignInBytes));
7018 // MinABIStackAlignInBytes is the size of argument slots on the stack.
7019 CharUnits ArgSlotSize = CharUnits::fromQuantity(MinABIStackAlignInBytes);
7021 Address Addr = emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
7022 TyInfo, ArgSlotSize, /*AllowHigherAlign*/ true);
7025 // If there was a promotion, "unpromote" into a temporary.
7026 // TODO: can we just use a pointer into a subset of the original slot?
7028 Address Temp = CGF.CreateMemTemp(OrigTy, "vaarg.promotion-temp");
7029 llvm::Value *Promoted = CGF.Builder.CreateLoad(Addr);
7031 // Truncate down to the right width.
7032 llvm::Type *IntTy = (OrigTy->isIntegerType() ? Temp.getElementType()
7034 llvm::Value *V = CGF.Builder.CreateTrunc(Promoted, IntTy);
7035 if (OrigTy->isPointerType())
7036 V = CGF.Builder.CreateIntToPtr(V, Temp.getElementType());
7038 CGF.Builder.CreateStore(V, Temp);
7045 bool MipsABIInfo::shouldSignExtUnsignedType(QualType Ty) const {
7046 int TySize = getContext().getTypeSize(Ty);
7048 // MIPS64 ABI requires unsigned 32 bit integers to be sign extended.
7049 if (Ty->isUnsignedIntegerOrEnumerationType() && TySize == 32)
7056 MIPSTargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
7057 llvm::Value *Address) const {
7058 // This information comes from gcc's implementation, which seems to
7059 // as canonical as it gets.
7061 // Everything on MIPS is 4 bytes. Double-precision FP registers
7062 // are aliased to pairs of single-precision FP registers.
7063 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
7065 // 0-31 are the general purpose registers, $0 - $31.
7066 // 32-63 are the floating-point registers, $f0 - $f31.
7067 // 64 and 65 are the multiply/divide registers, $hi and $lo.
7068 // 66 is the (notional, I think) register for signal-handler return.
7069 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 65);
7071 // 67-74 are the floating-point status registers, $fcc0 - $fcc7.
7072 // They are one bit wide and ignored here.
7074 // 80-111 are the coprocessor 0 registers, $c0r0 - $c0r31.
7075 // (coprocessor 1 is the FP unit)
7076 // 112-143 are the coprocessor 2 registers, $c2r0 - $c2r31.
7077 // 144-175 are the coprocessor 3 registers, $c3r0 - $c3r31.
7078 // 176-181 are the DSP accumulator registers.
7079 AssignToArrayRange(CGF.Builder, Address, Four8, 80, 181);
7083 //===----------------------------------------------------------------------===//
7084 // AVR ABI Implementation.
7085 //===----------------------------------------------------------------------===//
7088 class AVRTargetCodeGenInfo : public TargetCodeGenInfo {
7090 AVRTargetCodeGenInfo(CodeGenTypes &CGT)
7091 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) { }
7093 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
7094 CodeGen::CodeGenModule &CGM,
7095 ForDefinition_t IsForDefinition) const override {
7096 if (!IsForDefinition)
7098 const auto *FD = dyn_cast_or_null<FunctionDecl>(D);
7100 auto *Fn = cast<llvm::Function>(GV);
7102 if (FD->getAttr<AVRInterruptAttr>())
7103 Fn->addFnAttr("interrupt");
7105 if (FD->getAttr<AVRSignalAttr>())
7106 Fn->addFnAttr("signal");
7111 //===----------------------------------------------------------------------===//
7112 // TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults.
7113 // Currently subclassed only to implement custom OpenCL C function attribute
7115 //===----------------------------------------------------------------------===//
7119 class TCETargetCodeGenInfo : public DefaultTargetCodeGenInfo {
7121 TCETargetCodeGenInfo(CodeGenTypes &CGT)
7122 : DefaultTargetCodeGenInfo(CGT) {}
7124 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
7125 CodeGen::CodeGenModule &M,
7126 ForDefinition_t IsForDefinition) const override;
7129 void TCETargetCodeGenInfo::setTargetAttributes(
7130 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M,
7131 ForDefinition_t IsForDefinition) const {
7132 if (!IsForDefinition)
7134 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
7137 llvm::Function *F = cast<llvm::Function>(GV);
7139 if (M.getLangOpts().OpenCL) {
7140 if (FD->hasAttr<OpenCLKernelAttr>()) {
7141 // OpenCL C Kernel functions are not subject to inlining
7142 F->addFnAttr(llvm::Attribute::NoInline);
7143 const ReqdWorkGroupSizeAttr *Attr = FD->getAttr<ReqdWorkGroupSizeAttr>();
7145 // Convert the reqd_work_group_size() attributes to metadata.
7146 llvm::LLVMContext &Context = F->getContext();
7147 llvm::NamedMDNode *OpenCLMetadata =
7148 M.getModule().getOrInsertNamedMetadata(
7149 "opencl.kernel_wg_size_info");
7151 SmallVector<llvm::Metadata *, 5> Operands;
7152 Operands.push_back(llvm::ConstantAsMetadata::get(F));
7155 llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
7156 M.Int32Ty, llvm::APInt(32, Attr->getXDim()))));
7158 llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
7159 M.Int32Ty, llvm::APInt(32, Attr->getYDim()))));
7161 llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
7162 M.Int32Ty, llvm::APInt(32, Attr->getZDim()))));
7164 // Add a boolean constant operand for "required" (true) or "hint"
7165 // (false) for implementing the work_group_size_hint attr later.
7166 // Currently always true as the hint is not yet implemented.
7168 llvm::ConstantAsMetadata::get(llvm::ConstantInt::getTrue(Context)));
7169 OpenCLMetadata->addOperand(llvm::MDNode::get(Context, Operands));
7177 //===----------------------------------------------------------------------===//
7178 // Hexagon ABI Implementation
7179 //===----------------------------------------------------------------------===//
7183 class HexagonABIInfo : public ABIInfo {
7187 HexagonABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
7191 ABIArgInfo classifyReturnType(QualType RetTy) const;
7192 ABIArgInfo classifyArgumentType(QualType RetTy) const;
7194 void computeInfo(CGFunctionInfo &FI) const override;
7196 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7197 QualType Ty) const override;
7200 class HexagonTargetCodeGenInfo : public TargetCodeGenInfo {
7202 HexagonTargetCodeGenInfo(CodeGenTypes &CGT)
7203 :TargetCodeGenInfo(new HexagonABIInfo(CGT)) {}
7205 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
7212 void HexagonABIInfo::computeInfo(CGFunctionInfo &FI) const {
7213 if (!getCXXABI().classifyReturnType(FI))
7214 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
7215 for (auto &I : FI.arguments())
7216 I.info = classifyArgumentType(I.type);
7219 ABIArgInfo HexagonABIInfo::classifyArgumentType(QualType Ty) const {
7220 if (!isAggregateTypeForABI(Ty)) {
7221 // Treat an enum type as its underlying type.
7222 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
7223 Ty = EnumTy->getDecl()->getIntegerType();
7225 return (Ty->isPromotableIntegerType() ?
7226 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
7229 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
7230 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
7232 // Ignore empty records.
7233 if (isEmptyRecord(getContext(), Ty, true))
7234 return ABIArgInfo::getIgnore();
7236 uint64_t Size = getContext().getTypeSize(Ty);
7238 return getNaturalAlignIndirect(Ty, /*ByVal=*/true);
7239 // Pass in the smallest viable integer type.
7241 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
7243 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7245 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7247 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
7250 ABIArgInfo HexagonABIInfo::classifyReturnType(QualType RetTy) const {
7251 if (RetTy->isVoidType())
7252 return ABIArgInfo::getIgnore();
7254 // Large vector types should be returned via memory.
7255 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 64)
7256 return getNaturalAlignIndirect(RetTy);
7258 if (!isAggregateTypeForABI(RetTy)) {
7259 // Treat an enum type as its underlying type.
7260 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
7261 RetTy = EnumTy->getDecl()->getIntegerType();
7263 return (RetTy->isPromotableIntegerType() ?
7264 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
7267 if (isEmptyRecord(getContext(), RetTy, true))
7268 return ABIArgInfo::getIgnore();
7270 // Aggregates <= 8 bytes are returned in r0; other aggregates
7271 // are returned indirectly.
7272 uint64_t Size = getContext().getTypeSize(RetTy);
7274 // Return in the smallest viable integer type.
7276 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
7278 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7280 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7281 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
7284 return getNaturalAlignIndirect(RetTy, /*ByVal=*/true);
7287 Address HexagonABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7288 QualType Ty) const {
7289 // FIXME: Someone needs to audit that this handle alignment correctly.
7290 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
7291 getContext().getTypeInfoInChars(Ty),
7292 CharUnits::fromQuantity(4),
7293 /*AllowHigherAlign*/ true);
7296 //===----------------------------------------------------------------------===//
7297 // Lanai ABI Implementation
7298 //===----------------------------------------------------------------------===//
7301 class LanaiABIInfo : public DefaultABIInfo {
7303 LanaiABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
7305 bool shouldUseInReg(QualType Ty, CCState &State) const;
7307 void computeInfo(CGFunctionInfo &FI) const override {
7308 CCState State(FI.getCallingConvention());
7309 // Lanai uses 4 registers to pass arguments unless the function has the
7310 // regparm attribute set.
7311 if (FI.getHasRegParm()) {
7312 State.FreeRegs = FI.getRegParm();
7317 if (!getCXXABI().classifyReturnType(FI))
7318 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
7319 for (auto &I : FI.arguments())
7320 I.info = classifyArgumentType(I.type, State);
7323 ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
7324 ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
7326 } // end anonymous namespace
7328 bool LanaiABIInfo::shouldUseInReg(QualType Ty, CCState &State) const {
7329 unsigned Size = getContext().getTypeSize(Ty);
7330 unsigned SizeInRegs = llvm::alignTo(Size, 32U) / 32U;
7332 if (SizeInRegs == 0)
7335 if (SizeInRegs > State.FreeRegs) {
7340 State.FreeRegs -= SizeInRegs;
7345 ABIArgInfo LanaiABIInfo::getIndirectResult(QualType Ty, bool ByVal,
7346 CCState &State) const {
7348 if (State.FreeRegs) {
7349 --State.FreeRegs; // Non-byval indirects just use one pointer.
7350 return getNaturalAlignIndirectInReg(Ty);
7352 return getNaturalAlignIndirect(Ty, false);
7355 // Compute the byval alignment.
7356 const unsigned MinABIStackAlignInBytes = 4;
7357 unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
7358 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true,
7359 /*Realign=*/TypeAlign >
7360 MinABIStackAlignInBytes);
7363 ABIArgInfo LanaiABIInfo::classifyArgumentType(QualType Ty,
7364 CCState &State) const {
7365 // Check with the C++ ABI first.
7366 const RecordType *RT = Ty->getAs<RecordType>();
7368 CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
7369 if (RAA == CGCXXABI::RAA_Indirect) {
7370 return getIndirectResult(Ty, /*ByVal=*/false, State);
7371 } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
7372 return getNaturalAlignIndirect(Ty, /*ByRef=*/true);
7376 if (isAggregateTypeForABI(Ty)) {
7377 // Structures with flexible arrays are always indirect.
7378 if (RT && RT->getDecl()->hasFlexibleArrayMember())
7379 return getIndirectResult(Ty, /*ByVal=*/true, State);
7381 // Ignore empty structs/unions.
7382 if (isEmptyRecord(getContext(), Ty, true))
7383 return ABIArgInfo::getIgnore();
7385 llvm::LLVMContext &LLVMContext = getVMContext();
7386 unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
7387 if (SizeInRegs <= State.FreeRegs) {
7388 llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
7389 SmallVector<llvm::Type *, 3> Elements(SizeInRegs, Int32);
7390 llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
7391 State.FreeRegs -= SizeInRegs;
7392 return ABIArgInfo::getDirectInReg(Result);
7396 return getIndirectResult(Ty, true, State);
7399 // Treat an enum type as its underlying type.
7400 if (const auto *EnumTy = Ty->getAs<EnumType>())
7401 Ty = EnumTy->getDecl()->getIntegerType();
7403 bool InReg = shouldUseInReg(Ty, State);
7404 if (Ty->isPromotableIntegerType()) {
7406 return ABIArgInfo::getDirectInReg();
7407 return ABIArgInfo::getExtend();
7410 return ABIArgInfo::getDirectInReg();
7411 return ABIArgInfo::getDirect();
7415 class LanaiTargetCodeGenInfo : public TargetCodeGenInfo {
7417 LanaiTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
7418 : TargetCodeGenInfo(new LanaiABIInfo(CGT)) {}
7422 //===----------------------------------------------------------------------===//
7423 // AMDGPU ABI Implementation
7424 //===----------------------------------------------------------------------===//
7428 class AMDGPUABIInfo final : public DefaultABIInfo {
7430 static const unsigned MaxNumRegsForArgsRet = 16;
7432 unsigned numRegsForType(QualType Ty) const;
7434 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
7435 bool isHomogeneousAggregateSmallEnough(const Type *Base,
7436 uint64_t Members) const override;
7439 explicit AMDGPUABIInfo(CodeGen::CodeGenTypes &CGT) :
7440 DefaultABIInfo(CGT) {}
7442 ABIArgInfo classifyReturnType(QualType RetTy) const;
7443 ABIArgInfo classifyKernelArgumentType(QualType Ty) const;
7444 ABIArgInfo classifyArgumentType(QualType Ty, unsigned &NumRegsLeft) const;
7446 void computeInfo(CGFunctionInfo &FI) const override;
7449 bool AMDGPUABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
7453 bool AMDGPUABIInfo::isHomogeneousAggregateSmallEnough(
7454 const Type *Base, uint64_t Members) const {
7455 uint32_t NumRegs = (getContext().getTypeSize(Base) + 31) / 32;
7457 // Homogeneous Aggregates may occupy at most 16 registers.
7458 return Members * NumRegs <= MaxNumRegsForArgsRet;
7461 /// Estimate number of registers the type will use when passed in registers.
7462 unsigned AMDGPUABIInfo::numRegsForType(QualType Ty) const {
7463 unsigned NumRegs = 0;
7465 if (const VectorType *VT = Ty->getAs<VectorType>()) {
7466 // Compute from the number of elements. The reported size is based on the
7467 // in-memory size, which includes the padding 4th element for 3-vectors.
7468 QualType EltTy = VT->getElementType();
7469 unsigned EltSize = getContext().getTypeSize(EltTy);
7471 // 16-bit element vectors should be passed as packed.
7473 return (VT->getNumElements() + 1) / 2;
7475 unsigned EltNumRegs = (EltSize + 31) / 32;
7476 return EltNumRegs * VT->getNumElements();
7479 if (const RecordType *RT = Ty->getAs<RecordType>()) {
7480 const RecordDecl *RD = RT->getDecl();
7481 assert(!RD->hasFlexibleArrayMember());
7483 for (const FieldDecl *Field : RD->fields()) {
7484 QualType FieldTy = Field->getType();
7485 NumRegs += numRegsForType(FieldTy);
7491 return (getContext().getTypeSize(Ty) + 31) / 32;
7494 void AMDGPUABIInfo::computeInfo(CGFunctionInfo &FI) const {
7495 llvm::CallingConv::ID CC = FI.getCallingConvention();
7497 if (!getCXXABI().classifyReturnType(FI))
7498 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
7500 unsigned NumRegsLeft = MaxNumRegsForArgsRet;
7501 for (auto &Arg : FI.arguments()) {
7502 if (CC == llvm::CallingConv::AMDGPU_KERNEL) {
7503 Arg.info = classifyKernelArgumentType(Arg.type);
7505 Arg.info = classifyArgumentType(Arg.type, NumRegsLeft);
7510 ABIArgInfo AMDGPUABIInfo::classifyReturnType(QualType RetTy) const {
7511 if (isAggregateTypeForABI(RetTy)) {
7512 // Records with non-trivial destructors/copy-constructors should not be
7513 // returned by value.
7514 if (!getRecordArgABI(RetTy, getCXXABI())) {
7515 // Ignore empty structs/unions.
7516 if (isEmptyRecord(getContext(), RetTy, true))
7517 return ABIArgInfo::getIgnore();
7519 // Lower single-element structs to just return a regular value.
7520 if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
7521 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
7523 if (const RecordType *RT = RetTy->getAs<RecordType>()) {
7524 const RecordDecl *RD = RT->getDecl();
7525 if (RD->hasFlexibleArrayMember())
7526 return DefaultABIInfo::classifyReturnType(RetTy);
7529 // Pack aggregates <= 4 bytes into single VGPR or pair.
7530 uint64_t Size = getContext().getTypeSize(RetTy);
7532 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7535 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7538 llvm::Type *I32Ty = llvm::Type::getInt32Ty(getVMContext());
7539 return ABIArgInfo::getDirect(llvm::ArrayType::get(I32Ty, 2));
7542 if (numRegsForType(RetTy) <= MaxNumRegsForArgsRet)
7543 return ABIArgInfo::getDirect();
7547 // Otherwise just do the default thing.
7548 return DefaultABIInfo::classifyReturnType(RetTy);
7551 /// For kernels all parameters are really passed in a special buffer. It doesn't
7552 /// make sense to pass anything byval, so everything must be direct.
7553 ABIArgInfo AMDGPUABIInfo::classifyKernelArgumentType(QualType Ty) const {
7554 Ty = useFirstFieldIfTransparentUnion(Ty);
7556 // TODO: Can we omit empty structs?
7558 // Coerce single element structs to its element.
7559 if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
7560 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
7562 // If we set CanBeFlattened to true, CodeGen will expand the struct to its
7563 // individual elements, which confuses the Clover OpenCL backend; therefore we
7564 // have to set it to false here. Other args of getDirect() are just defaults.
7565 return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
7568 ABIArgInfo AMDGPUABIInfo::classifyArgumentType(QualType Ty,
7569 unsigned &NumRegsLeft) const {
7570 assert(NumRegsLeft <= MaxNumRegsForArgsRet && "register estimate underflow");
7572 Ty = useFirstFieldIfTransparentUnion(Ty);
7574 if (isAggregateTypeForABI(Ty)) {
7575 // Records with non-trivial destructors/copy-constructors should not be
7577 if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
7578 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
7580 // Ignore empty structs/unions.
7581 if (isEmptyRecord(getContext(), Ty, true))
7582 return ABIArgInfo::getIgnore();
7584 // Lower single-element structs to just pass a regular value. TODO: We
7585 // could do reasonable-size multiple-element structs too, using getExpand(),
7586 // though watch out for things like bitfields.
7587 if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
7588 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
7590 if (const RecordType *RT = Ty->getAs<RecordType>()) {
7591 const RecordDecl *RD = RT->getDecl();
7592 if (RD->hasFlexibleArrayMember())
7593 return DefaultABIInfo::classifyArgumentType(Ty);
7596 // Pack aggregates <= 8 bytes into single VGPR or pair.
7597 uint64_t Size = getContext().getTypeSize(Ty);
7599 unsigned NumRegs = (Size + 31) / 32;
7600 NumRegsLeft -= std::min(NumRegsLeft, NumRegs);
7603 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7606 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7608 // XXX: Should this be i64 instead, and should the limit increase?
7609 llvm::Type *I32Ty = llvm::Type::getInt32Ty(getVMContext());
7610 return ABIArgInfo::getDirect(llvm::ArrayType::get(I32Ty, 2));
7613 if (NumRegsLeft > 0) {
7614 unsigned NumRegs = numRegsForType(Ty);
7615 if (NumRegsLeft >= NumRegs) {
7616 NumRegsLeft -= NumRegs;
7617 return ABIArgInfo::getDirect();
7622 // Otherwise just do the default thing.
7623 ABIArgInfo ArgInfo = DefaultABIInfo::classifyArgumentType(Ty);
7624 if (!ArgInfo.isIndirect()) {
7625 unsigned NumRegs = numRegsForType(Ty);
7626 NumRegsLeft -= std::min(NumRegs, NumRegsLeft);
7632 class AMDGPUTargetCodeGenInfo : public TargetCodeGenInfo {
7634 AMDGPUTargetCodeGenInfo(CodeGenTypes &CGT)
7635 : TargetCodeGenInfo(new AMDGPUABIInfo(CGT)) {}
7636 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
7637 CodeGen::CodeGenModule &M,
7638 ForDefinition_t IsForDefinition) const override;
7639 unsigned getOpenCLKernelCallingConv() const override;
7641 llvm::Constant *getNullPointer(const CodeGen::CodeGenModule &CGM,
7642 llvm::PointerType *T, QualType QT) const override;
7644 LangAS getASTAllocaAddressSpace() const override {
7645 return getLangASFromTargetAS(
7646 getABIInfo().getDataLayout().getAllocaAddrSpace());
7648 LangAS getGlobalVarAddressSpace(CodeGenModule &CGM,
7649 const VarDecl *D) const override;
7650 llvm::SyncScope::ID getLLVMSyncScopeID(SyncScope S,
7651 llvm::LLVMContext &C) const override;
7653 createEnqueuedBlockKernel(CodeGenFunction &CGF,
7654 llvm::Function *BlockInvokeFunc,
7655 llvm::Value *BlockLiteral) const override;
7659 void AMDGPUTargetCodeGenInfo::setTargetAttributes(
7660 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M,
7661 ForDefinition_t IsForDefinition) const {
7662 if (!IsForDefinition)
7664 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
7668 llvm::Function *F = cast<llvm::Function>(GV);
7670 const auto *ReqdWGS = M.getLangOpts().OpenCL ?
7671 FD->getAttr<ReqdWorkGroupSizeAttr>() : nullptr;
7672 const auto *FlatWGS = FD->getAttr<AMDGPUFlatWorkGroupSizeAttr>();
7673 if (ReqdWGS || FlatWGS) {
7674 unsigned Min = FlatWGS ? FlatWGS->getMin() : 0;
7675 unsigned Max = FlatWGS ? FlatWGS->getMax() : 0;
7676 if (ReqdWGS && Min == 0 && Max == 0)
7677 Min = Max = ReqdWGS->getXDim() * ReqdWGS->getYDim() * ReqdWGS->getZDim();
7680 assert(Min <= Max && "Min must be less than or equal Max");
7682 std::string AttrVal = llvm::utostr(Min) + "," + llvm::utostr(Max);
7683 F->addFnAttr("amdgpu-flat-work-group-size", AttrVal);
7685 assert(Max == 0 && "Max must be zero");
7688 if (const auto *Attr = FD->getAttr<AMDGPUWavesPerEUAttr>()) {
7689 unsigned Min = Attr->getMin();
7690 unsigned Max = Attr->getMax();
7693 assert((Max == 0 || Min <= Max) && "Min must be less than or equal Max");
7695 std::string AttrVal = llvm::utostr(Min);
7697 AttrVal = AttrVal + "," + llvm::utostr(Max);
7698 F->addFnAttr("amdgpu-waves-per-eu", AttrVal);
7700 assert(Max == 0 && "Max must be zero");
7703 if (const auto *Attr = FD->getAttr<AMDGPUNumSGPRAttr>()) {
7704 unsigned NumSGPR = Attr->getNumSGPR();
7707 F->addFnAttr("amdgpu-num-sgpr", llvm::utostr(NumSGPR));
7710 if (const auto *Attr = FD->getAttr<AMDGPUNumVGPRAttr>()) {
7711 uint32_t NumVGPR = Attr->getNumVGPR();
7714 F->addFnAttr("amdgpu-num-vgpr", llvm::utostr(NumVGPR));
7718 unsigned AMDGPUTargetCodeGenInfo::getOpenCLKernelCallingConv() const {
7719 return llvm::CallingConv::AMDGPU_KERNEL;
7722 // Currently LLVM assumes null pointers always have value 0,
7723 // which results in incorrectly transformed IR. Therefore, instead of
7724 // emitting null pointers in private and local address spaces, a null
7725 // pointer in generic address space is emitted which is casted to a
7726 // pointer in local or private address space.
7727 llvm::Constant *AMDGPUTargetCodeGenInfo::getNullPointer(
7728 const CodeGen::CodeGenModule &CGM, llvm::PointerType *PT,
7729 QualType QT) const {
7730 if (CGM.getContext().getTargetNullPointerValue(QT) == 0)
7731 return llvm::ConstantPointerNull::get(PT);
7733 auto &Ctx = CGM.getContext();
7734 auto NPT = llvm::PointerType::get(PT->getElementType(),
7735 Ctx.getTargetAddressSpace(LangAS::opencl_generic));
7736 return llvm::ConstantExpr::getAddrSpaceCast(
7737 llvm::ConstantPointerNull::get(NPT), PT);
7741 AMDGPUTargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
7742 const VarDecl *D) const {
7743 assert(!CGM.getLangOpts().OpenCL &&
7744 !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
7745 "Address space agnostic languages only");
7746 LangAS DefaultGlobalAS = getLangASFromTargetAS(
7747 CGM.getContext().getTargetAddressSpace(LangAS::opencl_global));
7749 return DefaultGlobalAS;
7751 LangAS AddrSpace = D->getType().getAddressSpace();
7752 assert(AddrSpace == LangAS::Default || isTargetAddressSpace(AddrSpace));
7753 if (AddrSpace != LangAS::Default)
7756 if (CGM.isTypeConstant(D->getType(), false)) {
7757 if (auto ConstAS = CGM.getTarget().getConstantAddressSpace())
7758 return ConstAS.getValue();
7760 return DefaultGlobalAS;
7764 AMDGPUTargetCodeGenInfo::getLLVMSyncScopeID(SyncScope S,
7765 llvm::LLVMContext &C) const {
7768 case SyncScope::OpenCLWorkGroup:
7771 case SyncScope::OpenCLDevice:
7774 case SyncScope::OpenCLAllSVMDevices:
7777 case SyncScope::OpenCLSubGroup:
7780 return C.getOrInsertSyncScopeID(Name);
7783 //===----------------------------------------------------------------------===//
7784 // SPARC v8 ABI Implementation.
7785 // Based on the SPARC Compliance Definition version 2.4.1.
7787 // Ensures that complex values are passed in registers.
7790 class SparcV8ABIInfo : public DefaultABIInfo {
7792 SparcV8ABIInfo(CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
7795 ABIArgInfo classifyReturnType(QualType RetTy) const;
7796 void computeInfo(CGFunctionInfo &FI) const override;
7798 } // end anonymous namespace
7802 SparcV8ABIInfo::classifyReturnType(QualType Ty) const {
7803 if (Ty->isAnyComplexType()) {
7804 return ABIArgInfo::getDirect();
7807 return DefaultABIInfo::classifyReturnType(Ty);
7811 void SparcV8ABIInfo::computeInfo(CGFunctionInfo &FI) const {
7813 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
7814 for (auto &Arg : FI.arguments())
7815 Arg.info = classifyArgumentType(Arg.type);
7819 class SparcV8TargetCodeGenInfo : public TargetCodeGenInfo {
7821 SparcV8TargetCodeGenInfo(CodeGenTypes &CGT)
7822 : TargetCodeGenInfo(new SparcV8ABIInfo(CGT)) {}
7824 } // end anonymous namespace
7826 //===----------------------------------------------------------------------===//
7827 // SPARC v9 ABI Implementation.
7828 // Based on the SPARC Compliance Definition version 2.4.1.
7830 // Function arguments a mapped to a nominal "parameter array" and promoted to
7831 // registers depending on their type. Each argument occupies 8 or 16 bytes in
7832 // the array, structs larger than 16 bytes are passed indirectly.
7834 // One case requires special care:
7841 // When a struct mixed is passed by value, it only occupies 8 bytes in the
7842 // parameter array, but the int is passed in an integer register, and the float
7843 // is passed in a floating point register. This is represented as two arguments
7844 // with the LLVM IR inreg attribute:
7846 // declare void f(i32 inreg %i, float inreg %f)
7848 // The code generator will only allocate 4 bytes from the parameter array for
7849 // the inreg arguments. All other arguments are allocated a multiple of 8
7853 class SparcV9ABIInfo : public ABIInfo {
7855 SparcV9ABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
7858 ABIArgInfo classifyType(QualType RetTy, unsigned SizeLimit) const;
7859 void computeInfo(CGFunctionInfo &FI) const override;
7860 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7861 QualType Ty) const override;
7863 // Coercion type builder for structs passed in registers. The coercion type
7864 // serves two purposes:
7866 // 1. Pad structs to a multiple of 64 bits, so they are passed 'left-aligned'
7868 // 2. Expose aligned floating point elements as first-level elements, so the
7869 // code generator knows to pass them in floating point registers.
7871 // We also compute the InReg flag which indicates that the struct contains
7872 // aligned 32-bit floats.
7874 struct CoerceBuilder {
7875 llvm::LLVMContext &Context;
7876 const llvm::DataLayout &DL;
7877 SmallVector<llvm::Type*, 8> Elems;
7881 CoerceBuilder(llvm::LLVMContext &c, const llvm::DataLayout &dl)
7882 : Context(c), DL(dl), Size(0), InReg(false) {}
7884 // Pad Elems with integers until Size is ToSize.
7885 void pad(uint64_t ToSize) {
7886 assert(ToSize >= Size && "Cannot remove elements");
7890 // Finish the current 64-bit word.
7891 uint64_t Aligned = llvm::alignTo(Size, 64);
7892 if (Aligned > Size && Aligned <= ToSize) {
7893 Elems.push_back(llvm::IntegerType::get(Context, Aligned - Size));
7897 // Add whole 64-bit words.
7898 while (Size + 64 <= ToSize) {
7899 Elems.push_back(llvm::Type::getInt64Ty(Context));
7903 // Final in-word padding.
7904 if (Size < ToSize) {
7905 Elems.push_back(llvm::IntegerType::get(Context, ToSize - Size));
7910 // Add a floating point element at Offset.
7911 void addFloat(uint64_t Offset, llvm::Type *Ty, unsigned Bits) {
7912 // Unaligned floats are treated as integers.
7915 // The InReg flag is only required if there are any floats < 64 bits.
7919 Elems.push_back(Ty);
7920 Size = Offset + Bits;
7923 // Add a struct type to the coercion type, starting at Offset (in bits).
7924 void addStruct(uint64_t Offset, llvm::StructType *StrTy) {
7925 const llvm::StructLayout *Layout = DL.getStructLayout(StrTy);
7926 for (unsigned i = 0, e = StrTy->getNumElements(); i != e; ++i) {
7927 llvm::Type *ElemTy = StrTy->getElementType(i);
7928 uint64_t ElemOffset = Offset + Layout->getElementOffsetInBits(i);
7929 switch (ElemTy->getTypeID()) {
7930 case llvm::Type::StructTyID:
7931 addStruct(ElemOffset, cast<llvm::StructType>(ElemTy));
7933 case llvm::Type::FloatTyID:
7934 addFloat(ElemOffset, ElemTy, 32);
7936 case llvm::Type::DoubleTyID:
7937 addFloat(ElemOffset, ElemTy, 64);
7939 case llvm::Type::FP128TyID:
7940 addFloat(ElemOffset, ElemTy, 128);
7942 case llvm::Type::PointerTyID:
7943 if (ElemOffset % 64 == 0) {
7945 Elems.push_back(ElemTy);
7955 // Check if Ty is a usable substitute for the coercion type.
7956 bool isUsableType(llvm::StructType *Ty) const {
7957 return llvm::makeArrayRef(Elems) == Ty->elements();
7960 // Get the coercion type as a literal struct type.
7961 llvm::Type *getType() const {
7962 if (Elems.size() == 1)
7963 return Elems.front();
7965 return llvm::StructType::get(Context, Elems);
7969 } // end anonymous namespace
7972 SparcV9ABIInfo::classifyType(QualType Ty, unsigned SizeLimit) const {
7973 if (Ty->isVoidType())
7974 return ABIArgInfo::getIgnore();
7976 uint64_t Size = getContext().getTypeSize(Ty);
7978 // Anything too big to fit in registers is passed with an explicit indirect
7979 // pointer / sret pointer.
7980 if (Size > SizeLimit)
7981 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
7983 // Treat an enum type as its underlying type.
7984 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
7985 Ty = EnumTy->getDecl()->getIntegerType();
7987 // Integer types smaller than a register are extended.
7988 if (Size < 64 && Ty->isIntegerType())
7989 return ABIArgInfo::getExtend();
7991 // Other non-aggregates go in registers.
7992 if (!isAggregateTypeForABI(Ty))
7993 return ABIArgInfo::getDirect();
7995 // If a C++ object has either a non-trivial copy constructor or a non-trivial
7996 // destructor, it is passed with an explicit indirect pointer / sret pointer.
7997 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
7998 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
8000 // This is a small aggregate type that should be passed in registers.
8001 // Build a coercion type from the LLVM struct type.
8002 llvm::StructType *StrTy = dyn_cast<llvm::StructType>(CGT.ConvertType(Ty));
8004 return ABIArgInfo::getDirect();
8006 CoerceBuilder CB(getVMContext(), getDataLayout());
8007 CB.addStruct(0, StrTy);
8008 CB.pad(llvm::alignTo(CB.DL.getTypeSizeInBits(StrTy), 64));
8010 // Try to use the original type for coercion.
8011 llvm::Type *CoerceTy = CB.isUsableType(StrTy) ? StrTy : CB.getType();
8014 return ABIArgInfo::getDirectInReg(CoerceTy);
8016 return ABIArgInfo::getDirect(CoerceTy);
8019 Address SparcV9ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8020 QualType Ty) const {
8021 ABIArgInfo AI = classifyType(Ty, 16 * 8);
8022 llvm::Type *ArgTy = CGT.ConvertType(Ty);
8023 if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
8024 AI.setCoerceToType(ArgTy);
8026 CharUnits SlotSize = CharUnits::fromQuantity(8);
8028 CGBuilderTy &Builder = CGF.Builder;
8029 Address Addr(Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize);
8030 llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
8032 auto TypeInfo = getContext().getTypeInfoInChars(Ty);
8034 Address ArgAddr = Address::invalid();
8036 switch (AI.getKind()) {
8037 case ABIArgInfo::Expand:
8038 case ABIArgInfo::CoerceAndExpand:
8039 case ABIArgInfo::InAlloca:
8040 llvm_unreachable("Unsupported ABI kind for va_arg");
8042 case ABIArgInfo::Extend: {
8044 CharUnits Offset = SlotSize - TypeInfo.first;
8045 ArgAddr = Builder.CreateConstInBoundsByteGEP(Addr, Offset, "extend");
8049 case ABIArgInfo::Direct: {
8050 auto AllocSize = getDataLayout().getTypeAllocSize(AI.getCoerceToType());
8051 Stride = CharUnits::fromQuantity(AllocSize).alignTo(SlotSize);
8056 case ABIArgInfo::Indirect:
8058 ArgAddr = Builder.CreateElementBitCast(Addr, ArgPtrTy, "indirect");
8059 ArgAddr = Address(Builder.CreateLoad(ArgAddr, "indirect.arg"),
8063 case ABIArgInfo::Ignore:
8064 return Address(llvm::UndefValue::get(ArgPtrTy), TypeInfo.second);
8068 llvm::Value *NextPtr =
8069 Builder.CreateConstInBoundsByteGEP(Addr.getPointer(), Stride, "ap.next");
8070 Builder.CreateStore(NextPtr, VAListAddr);
8072 return Builder.CreateBitCast(ArgAddr, ArgPtrTy, "arg.addr");
8075 void SparcV9ABIInfo::computeInfo(CGFunctionInfo &FI) const {
8076 FI.getReturnInfo() = classifyType(FI.getReturnType(), 32 * 8);
8077 for (auto &I : FI.arguments())
8078 I.info = classifyType(I.type, 16 * 8);
8082 class SparcV9TargetCodeGenInfo : public TargetCodeGenInfo {
8084 SparcV9TargetCodeGenInfo(CodeGenTypes &CGT)
8085 : TargetCodeGenInfo(new SparcV9ABIInfo(CGT)) {}
8087 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
8091 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
8092 llvm::Value *Address) const override;
8094 } // end anonymous namespace
8097 SparcV9TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
8098 llvm::Value *Address) const {
8099 // This is calculated from the LLVM and GCC tables and verified
8100 // against gcc output. AFAIK all ABIs use the same encoding.
8102 CodeGen::CGBuilderTy &Builder = CGF.Builder;
8104 llvm::IntegerType *i8 = CGF.Int8Ty;
8105 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
8106 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
8108 // 0-31: the 8-byte general-purpose registers
8109 AssignToArrayRange(Builder, Address, Eight8, 0, 31);
8111 // 32-63: f0-31, the 4-byte floating-point registers
8112 AssignToArrayRange(Builder, Address, Four8, 32, 63);
8122 AssignToArrayRange(Builder, Address, Eight8, 64, 71);
8124 // 72-87: d0-15, the 8-byte floating-point registers
8125 AssignToArrayRange(Builder, Address, Eight8, 72, 87);
8131 //===----------------------------------------------------------------------===//
8132 // XCore ABI Implementation
8133 //===----------------------------------------------------------------------===//
8137 /// A SmallStringEnc instance is used to build up the TypeString by passing
8138 /// it by reference between functions that append to it.
8139 typedef llvm::SmallString<128> SmallStringEnc;
8141 /// TypeStringCache caches the meta encodings of Types.
8143 /// The reason for caching TypeStrings is two fold:
8144 /// 1. To cache a type's encoding for later uses;
8145 /// 2. As a means to break recursive member type inclusion.
8147 /// A cache Entry can have a Status of:
8148 /// NonRecursive: The type encoding is not recursive;
8149 /// Recursive: The type encoding is recursive;
8150 /// Incomplete: An incomplete TypeString;
8151 /// IncompleteUsed: An incomplete TypeString that has been used in a
8152 /// Recursive type encoding.
8154 /// A NonRecursive entry will have all of its sub-members expanded as fully
8155 /// as possible. Whilst it may contain types which are recursive, the type
8156 /// itself is not recursive and thus its encoding may be safely used whenever
8157 /// the type is encountered.
8159 /// A Recursive entry will have all of its sub-members expanded as fully as
8160 /// possible. The type itself is recursive and it may contain other types which
8161 /// are recursive. The Recursive encoding must not be used during the expansion
8162 /// of a recursive type's recursive branch. For simplicity the code uses
8163 /// IncompleteCount to reject all usage of Recursive encodings for member types.
8165 /// An Incomplete entry is always a RecordType and only encodes its
8166 /// identifier e.g. "s(S){}". Incomplete 'StubEnc' entries are ephemeral and
8167 /// are placed into the cache during type expansion as a means to identify and
8168 /// handle recursive inclusion of types as sub-members. If there is recursion
8169 /// the entry becomes IncompleteUsed.
8171 /// During the expansion of a RecordType's members:
8173 /// If the cache contains a NonRecursive encoding for the member type, the
8174 /// cached encoding is used;
8176 /// If the cache contains a Recursive encoding for the member type, the
8177 /// cached encoding is 'Swapped' out, as it may be incorrect, and...
8179 /// If the member is a RecordType, an Incomplete encoding is placed into the
8180 /// cache to break potential recursive inclusion of itself as a sub-member;
8182 /// Once a member RecordType has been expanded, its temporary incomplete
8183 /// entry is removed from the cache. If a Recursive encoding was swapped out
8184 /// it is swapped back in;
8186 /// If an incomplete entry is used to expand a sub-member, the incomplete
8187 /// entry is marked as IncompleteUsed. The cache keeps count of how many
8188 /// IncompleteUsed entries it currently contains in IncompleteUsedCount;
8190 /// If a member's encoding is found to be a NonRecursive or Recursive viz:
8191 /// IncompleteUsedCount==0, the member's encoding is added to the cache.
8192 /// Else the member is part of a recursive type and thus the recursion has
8193 /// been exited too soon for the encoding to be correct for the member.
8195 class TypeStringCache {
8196 enum Status {NonRecursive, Recursive, Incomplete, IncompleteUsed};
8198 std::string Str; // The encoded TypeString for the type.
8199 enum Status State; // Information about the encoding in 'Str'.
8200 std::string Swapped; // A temporary place holder for a Recursive encoding
8201 // during the expansion of RecordType's members.
8203 std::map<const IdentifierInfo *, struct Entry> Map;
8204 unsigned IncompleteCount; // Number of Incomplete entries in the Map.
8205 unsigned IncompleteUsedCount; // Number of IncompleteUsed entries in the Map.
8207 TypeStringCache() : IncompleteCount(0), IncompleteUsedCount(0) {}
8208 void addIncomplete(const IdentifierInfo *ID, std::string StubEnc);
8209 bool removeIncomplete(const IdentifierInfo *ID);
8210 void addIfComplete(const IdentifierInfo *ID, StringRef Str,
8212 StringRef lookupStr(const IdentifierInfo *ID);
8215 /// TypeString encodings for enum & union fields must be order.
8216 /// FieldEncoding is a helper for this ordering process.
8217 class FieldEncoding {
8221 FieldEncoding(bool b, SmallStringEnc &e) : HasName(b), Enc(e.c_str()) {}
8222 StringRef str() { return Enc; }
8223 bool operator<(const FieldEncoding &rhs) const {
8224 if (HasName != rhs.HasName) return HasName;
8225 return Enc < rhs.Enc;
8229 class XCoreABIInfo : public DefaultABIInfo {
8231 XCoreABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
8232 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8233 QualType Ty) const override;
8236 class XCoreTargetCodeGenInfo : public TargetCodeGenInfo {
8237 mutable TypeStringCache TSC;
8239 XCoreTargetCodeGenInfo(CodeGenTypes &CGT)
8240 :TargetCodeGenInfo(new XCoreABIInfo(CGT)) {}
8241 void emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
8242 CodeGen::CodeGenModule &M) const override;
8245 } // End anonymous namespace.
8247 // TODO: this implementation is likely now redundant with the default
8249 Address XCoreABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8250 QualType Ty) const {
8251 CGBuilderTy &Builder = CGF.Builder;
8254 CharUnits SlotSize = CharUnits::fromQuantity(4);
8255 Address AP(Builder.CreateLoad(VAListAddr), SlotSize);
8257 // Handle the argument.
8258 ABIArgInfo AI = classifyArgumentType(Ty);
8259 CharUnits TypeAlign = getContext().getTypeAlignInChars(Ty);
8260 llvm::Type *ArgTy = CGT.ConvertType(Ty);
8261 if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
8262 AI.setCoerceToType(ArgTy);
8263 llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
8265 Address Val = Address::invalid();
8266 CharUnits ArgSize = CharUnits::Zero();
8267 switch (AI.getKind()) {
8268 case ABIArgInfo::Expand:
8269 case ABIArgInfo::CoerceAndExpand:
8270 case ABIArgInfo::InAlloca:
8271 llvm_unreachable("Unsupported ABI kind for va_arg");
8272 case ABIArgInfo::Ignore:
8273 Val = Address(llvm::UndefValue::get(ArgPtrTy), TypeAlign);
8274 ArgSize = CharUnits::Zero();
8276 case ABIArgInfo::Extend:
8277 case ABIArgInfo::Direct:
8278 Val = Builder.CreateBitCast(AP, ArgPtrTy);
8279 ArgSize = CharUnits::fromQuantity(
8280 getDataLayout().getTypeAllocSize(AI.getCoerceToType()));
8281 ArgSize = ArgSize.alignTo(SlotSize);
8283 case ABIArgInfo::Indirect:
8284 Val = Builder.CreateElementBitCast(AP, ArgPtrTy);
8285 Val = Address(Builder.CreateLoad(Val), TypeAlign);
8290 // Increment the VAList.
8291 if (!ArgSize.isZero()) {
8293 Builder.CreateConstInBoundsByteGEP(AP.getPointer(), ArgSize);
8294 Builder.CreateStore(APN, VAListAddr);
8300 /// During the expansion of a RecordType, an incomplete TypeString is placed
8301 /// into the cache as a means to identify and break recursion.
8302 /// If there is a Recursive encoding in the cache, it is swapped out and will
8303 /// be reinserted by removeIncomplete().
8304 /// All other types of encoding should have been used rather than arriving here.
8305 void TypeStringCache::addIncomplete(const IdentifierInfo *ID,
8306 std::string StubEnc) {
8310 assert( (E.Str.empty() || E.State == Recursive) &&
8311 "Incorrectly use of addIncomplete");
8312 assert(!StubEnc.empty() && "Passing an empty string to addIncomplete()");
8313 E.Swapped.swap(E.Str); // swap out the Recursive
8314 E.Str.swap(StubEnc);
8315 E.State = Incomplete;
8319 /// Once the RecordType has been expanded, the temporary incomplete TypeString
8320 /// must be removed from the cache.
8321 /// If a Recursive was swapped out by addIncomplete(), it will be replaced.
8322 /// Returns true if the RecordType was defined recursively.
8323 bool TypeStringCache::removeIncomplete(const IdentifierInfo *ID) {
8326 auto I = Map.find(ID);
8327 assert(I != Map.end() && "Entry not present");
8328 Entry &E = I->second;
8329 assert( (E.State == Incomplete ||
8330 E.State == IncompleteUsed) &&
8331 "Entry must be an incomplete type");
8332 bool IsRecursive = false;
8333 if (E.State == IncompleteUsed) {
8334 // We made use of our Incomplete encoding, thus we are recursive.
8336 --IncompleteUsedCount;
8338 if (E.Swapped.empty())
8341 // Swap the Recursive back.
8342 E.Swapped.swap(E.Str);
8344 E.State = Recursive;
8350 /// Add the encoded TypeString to the cache only if it is NonRecursive or
8351 /// Recursive (viz: all sub-members were expanded as fully as possible).
8352 void TypeStringCache::addIfComplete(const IdentifierInfo *ID, StringRef Str,
8354 if (!ID || IncompleteUsedCount)
8355 return; // No key or it is is an incomplete sub-type so don't add.
8357 if (IsRecursive && !E.Str.empty()) {
8358 assert(E.State==Recursive && E.Str.size() == Str.size() &&
8359 "This is not the same Recursive entry");
8360 // The parent container was not recursive after all, so we could have used
8361 // this Recursive sub-member entry after all, but we assumed the worse when
8362 // we started viz: IncompleteCount!=0.
8365 assert(E.Str.empty() && "Entry already present");
8367 E.State = IsRecursive? Recursive : NonRecursive;
8370 /// Return a cached TypeString encoding for the ID. If there isn't one, or we
8371 /// are recursively expanding a type (IncompleteCount != 0) and the cached
8372 /// encoding is Recursive, return an empty StringRef.
8373 StringRef TypeStringCache::lookupStr(const IdentifierInfo *ID) {
8375 return StringRef(); // We have no key.
8376 auto I = Map.find(ID);
8378 return StringRef(); // We have no encoding.
8379 Entry &E = I->second;
8380 if (E.State == Recursive && IncompleteCount)
8381 return StringRef(); // We don't use Recursive encodings for member types.
8383 if (E.State == Incomplete) {
8384 // The incomplete type is being used to break out of recursion.
8385 E.State = IncompleteUsed;
8386 ++IncompleteUsedCount;
8391 /// The XCore ABI includes a type information section that communicates symbol
8392 /// type information to the linker. The linker uses this information to verify
8393 /// safety/correctness of things such as array bound and pointers et al.
8394 /// The ABI only requires C (and XC) language modules to emit TypeStrings.
8395 /// This type information (TypeString) is emitted into meta data for all global
8396 /// symbols: definitions, declarations, functions & variables.
8398 /// The TypeString carries type, qualifier, name, size & value details.
8399 /// Please see 'Tools Development Guide' section 2.16.2 for format details:
8400 /// https://www.xmos.com/download/public/Tools-Development-Guide%28X9114A%29.pdf
8401 /// The output is tested by test/CodeGen/xcore-stringtype.c.
8403 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
8404 CodeGen::CodeGenModule &CGM, TypeStringCache &TSC);
8406 /// XCore uses emitTargetMD to emit TypeString metadata for global symbols.
8407 void XCoreTargetCodeGenInfo::emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
8408 CodeGen::CodeGenModule &CGM) const {
8410 if (getTypeString(Enc, D, CGM, TSC)) {
8411 llvm::LLVMContext &Ctx = CGM.getModule().getContext();
8412 llvm::Metadata *MDVals[] = {llvm::ConstantAsMetadata::get(GV),
8413 llvm::MDString::get(Ctx, Enc.str())};
8414 llvm::NamedMDNode *MD =
8415 CGM.getModule().getOrInsertNamedMetadata("xcore.typestrings");
8416 MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
8420 //===----------------------------------------------------------------------===//
8421 // SPIR ABI Implementation
8422 //===----------------------------------------------------------------------===//
8425 class SPIRTargetCodeGenInfo : public TargetCodeGenInfo {
8427 SPIRTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
8428 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
8429 unsigned getOpenCLKernelCallingConv() const override;
8432 } // End anonymous namespace.
8436 void computeSPIRKernelABIInfo(CodeGenModule &CGM, CGFunctionInfo &FI) {
8437 DefaultABIInfo SPIRABI(CGM.getTypes());
8438 SPIRABI.computeInfo(FI);
8443 unsigned SPIRTargetCodeGenInfo::getOpenCLKernelCallingConv() const {
8444 return llvm::CallingConv::SPIR_KERNEL;
8447 static bool appendType(SmallStringEnc &Enc, QualType QType,
8448 const CodeGen::CodeGenModule &CGM,
8449 TypeStringCache &TSC);
8451 /// Helper function for appendRecordType().
8452 /// Builds a SmallVector containing the encoded field types in declaration
8454 static bool extractFieldType(SmallVectorImpl<FieldEncoding> &FE,
8455 const RecordDecl *RD,
8456 const CodeGen::CodeGenModule &CGM,
8457 TypeStringCache &TSC) {
8458 for (const auto *Field : RD->fields()) {
8461 Enc += Field->getName();
8463 if (Field->isBitField()) {
8465 llvm::raw_svector_ostream OS(Enc);
8466 OS << Field->getBitWidthValue(CGM.getContext());
8469 if (!appendType(Enc, Field->getType(), CGM, TSC))
8471 if (Field->isBitField())
8474 FE.emplace_back(!Field->getName().empty(), Enc);
8479 /// Appends structure and union types to Enc and adds encoding to cache.
8480 /// Recursively calls appendType (via extractFieldType) for each field.
8481 /// Union types have their fields ordered according to the ABI.
8482 static bool appendRecordType(SmallStringEnc &Enc, const RecordType *RT,
8483 const CodeGen::CodeGenModule &CGM,
8484 TypeStringCache &TSC, const IdentifierInfo *ID) {
8485 // Append the cached TypeString if we have one.
8486 StringRef TypeString = TSC.lookupStr(ID);
8487 if (!TypeString.empty()) {
8492 // Start to emit an incomplete TypeString.
8493 size_t Start = Enc.size();
8494 Enc += (RT->isUnionType()? 'u' : 's');
8497 Enc += ID->getName();
8500 // We collect all encoded fields and order as necessary.
8501 bool IsRecursive = false;
8502 const RecordDecl *RD = RT->getDecl()->getDefinition();
8503 if (RD && !RD->field_empty()) {
8504 // An incomplete TypeString stub is placed in the cache for this RecordType
8505 // so that recursive calls to this RecordType will use it whilst building a
8506 // complete TypeString for this RecordType.
8507 SmallVector<FieldEncoding, 16> FE;
8508 std::string StubEnc(Enc.substr(Start).str());
8509 StubEnc += '}'; // StubEnc now holds a valid incomplete TypeString.
8510 TSC.addIncomplete(ID, std::move(StubEnc));
8511 if (!extractFieldType(FE, RD, CGM, TSC)) {
8512 (void) TSC.removeIncomplete(ID);
8515 IsRecursive = TSC.removeIncomplete(ID);
8516 // The ABI requires unions to be sorted but not structures.
8517 // See FieldEncoding::operator< for sort algorithm.
8518 if (RT->isUnionType())
8519 std::sort(FE.begin(), FE.end());
8520 // We can now complete the TypeString.
8521 unsigned E = FE.size();
8522 for (unsigned I = 0; I != E; ++I) {
8529 TSC.addIfComplete(ID, Enc.substr(Start), IsRecursive);
8533 /// Appends enum types to Enc and adds the encoding to the cache.
8534 static bool appendEnumType(SmallStringEnc &Enc, const EnumType *ET,
8535 TypeStringCache &TSC,
8536 const IdentifierInfo *ID) {
8537 // Append the cached TypeString if we have one.
8538 StringRef TypeString = TSC.lookupStr(ID);
8539 if (!TypeString.empty()) {
8544 size_t Start = Enc.size();
8547 Enc += ID->getName();
8550 // We collect all encoded enumerations and order them alphanumerically.
8551 if (const EnumDecl *ED = ET->getDecl()->getDefinition()) {
8552 SmallVector<FieldEncoding, 16> FE;
8553 for (auto I = ED->enumerator_begin(), E = ED->enumerator_end(); I != E;
8555 SmallStringEnc EnumEnc;
8557 EnumEnc += I->getName();
8559 I->getInitVal().toString(EnumEnc);
8561 FE.push_back(FieldEncoding(!I->getName().empty(), EnumEnc));
8563 std::sort(FE.begin(), FE.end());
8564 unsigned E = FE.size();
8565 for (unsigned I = 0; I != E; ++I) {
8572 TSC.addIfComplete(ID, Enc.substr(Start), false);
8576 /// Appends type's qualifier to Enc.
8577 /// This is done prior to appending the type's encoding.
8578 static void appendQualifier(SmallStringEnc &Enc, QualType QT) {
8579 // Qualifiers are emitted in alphabetical order.
8580 static const char *const Table[]={"","c:","r:","cr:","v:","cv:","rv:","crv:"};
8582 if (QT.isConstQualified())
8584 if (QT.isRestrictQualified())
8586 if (QT.isVolatileQualified())
8588 Enc += Table[Lookup];
8591 /// Appends built-in types to Enc.
8592 static bool appendBuiltinType(SmallStringEnc &Enc, const BuiltinType *BT) {
8593 const char *EncType;
8594 switch (BT->getKind()) {
8595 case BuiltinType::Void:
8598 case BuiltinType::Bool:
8601 case BuiltinType::Char_U:
8604 case BuiltinType::UChar:
8607 case BuiltinType::SChar:
8610 case BuiltinType::UShort:
8613 case BuiltinType::Short:
8616 case BuiltinType::UInt:
8619 case BuiltinType::Int:
8622 case BuiltinType::ULong:
8625 case BuiltinType::Long:
8628 case BuiltinType::ULongLong:
8631 case BuiltinType::LongLong:
8634 case BuiltinType::Float:
8637 case BuiltinType::Double:
8640 case BuiltinType::LongDouble:
8650 /// Appends a pointer encoding to Enc before calling appendType for the pointee.
8651 static bool appendPointerType(SmallStringEnc &Enc, const PointerType *PT,
8652 const CodeGen::CodeGenModule &CGM,
8653 TypeStringCache &TSC) {
8655 if (!appendType(Enc, PT->getPointeeType(), CGM, TSC))
8661 /// Appends array encoding to Enc before calling appendType for the element.
8662 static bool appendArrayType(SmallStringEnc &Enc, QualType QT,
8663 const ArrayType *AT,
8664 const CodeGen::CodeGenModule &CGM,
8665 TypeStringCache &TSC, StringRef NoSizeEnc) {
8666 if (AT->getSizeModifier() != ArrayType::Normal)
8669 if (const ConstantArrayType *CAT = dyn_cast<ConstantArrayType>(AT))
8670 CAT->getSize().toStringUnsigned(Enc);
8672 Enc += NoSizeEnc; // Global arrays use "*", otherwise it is "".
8674 // The Qualifiers should be attached to the type rather than the array.
8675 appendQualifier(Enc, QT);
8676 if (!appendType(Enc, AT->getElementType(), CGM, TSC))
8682 /// Appends a function encoding to Enc, calling appendType for the return type
8683 /// and the arguments.
8684 static bool appendFunctionType(SmallStringEnc &Enc, const FunctionType *FT,
8685 const CodeGen::CodeGenModule &CGM,
8686 TypeStringCache &TSC) {
8688 if (!appendType(Enc, FT->getReturnType(), CGM, TSC))
8691 if (const FunctionProtoType *FPT = FT->getAs<FunctionProtoType>()) {
8692 // N.B. we are only interested in the adjusted param types.
8693 auto I = FPT->param_type_begin();
8694 auto E = FPT->param_type_end();
8697 if (!appendType(Enc, *I, CGM, TSC))
8703 if (FPT->isVariadic())
8706 if (FPT->isVariadic())
8716 /// Handles the type's qualifier before dispatching a call to handle specific
8718 static bool appendType(SmallStringEnc &Enc, QualType QType,
8719 const CodeGen::CodeGenModule &CGM,
8720 TypeStringCache &TSC) {
8722 QualType QT = QType.getCanonicalType();
8724 if (const ArrayType *AT = QT->getAsArrayTypeUnsafe())
8725 // The Qualifiers should be attached to the type rather than the array.
8726 // Thus we don't call appendQualifier() here.
8727 return appendArrayType(Enc, QT, AT, CGM, TSC, "");
8729 appendQualifier(Enc, QT);
8731 if (const BuiltinType *BT = QT->getAs<BuiltinType>())
8732 return appendBuiltinType(Enc, BT);
8734 if (const PointerType *PT = QT->getAs<PointerType>())
8735 return appendPointerType(Enc, PT, CGM, TSC);
8737 if (const EnumType *ET = QT->getAs<EnumType>())
8738 return appendEnumType(Enc, ET, TSC, QT.getBaseTypeIdentifier());
8740 if (const RecordType *RT = QT->getAsStructureType())
8741 return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
8743 if (const RecordType *RT = QT->getAsUnionType())
8744 return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
8746 if (const FunctionType *FT = QT->getAs<FunctionType>())
8747 return appendFunctionType(Enc, FT, CGM, TSC);
8752 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
8753 CodeGen::CodeGenModule &CGM, TypeStringCache &TSC) {
8757 if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) {
8758 if (FD->getLanguageLinkage() != CLanguageLinkage)
8760 return appendType(Enc, FD->getType(), CGM, TSC);
8763 if (const VarDecl *VD = dyn_cast<VarDecl>(D)) {
8764 if (VD->getLanguageLinkage() != CLanguageLinkage)
8766 QualType QT = VD->getType().getCanonicalType();
8767 if (const ArrayType *AT = QT->getAsArrayTypeUnsafe()) {
8768 // Global ArrayTypes are given a size of '*' if the size is unknown.
8769 // The Qualifiers should be attached to the type rather than the array.
8770 // Thus we don't call appendQualifier() here.
8771 return appendArrayType(Enc, QT, AT, CGM, TSC, "*");
8773 return appendType(Enc, QT, CGM, TSC);
8779 //===----------------------------------------------------------------------===//
8781 //===----------------------------------------------------------------------===//
8783 bool CodeGenModule::supportsCOMDAT() const {
8784 return getTriple().supportsCOMDAT();
8787 const TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() {
8788 if (TheTargetCodeGenInfo)
8789 return *TheTargetCodeGenInfo;
8791 // Helper to set the unique_ptr while still keeping the return value.
8792 auto SetCGInfo = [&](TargetCodeGenInfo *P) -> const TargetCodeGenInfo & {
8793 this->TheTargetCodeGenInfo.reset(P);
8797 const llvm::Triple &Triple = getTarget().getTriple();
8798 switch (Triple.getArch()) {
8800 return SetCGInfo(new DefaultTargetCodeGenInfo(Types));
8802 case llvm::Triple::le32:
8803 return SetCGInfo(new PNaClTargetCodeGenInfo(Types));
8804 case llvm::Triple::mips:
8805 case llvm::Triple::mipsel:
8806 if (Triple.getOS() == llvm::Triple::NaCl)
8807 return SetCGInfo(new PNaClTargetCodeGenInfo(Types));
8808 return SetCGInfo(new MIPSTargetCodeGenInfo(Types, true));
8810 case llvm::Triple::mips64:
8811 case llvm::Triple::mips64el:
8812 return SetCGInfo(new MIPSTargetCodeGenInfo(Types, false));
8814 case llvm::Triple::avr:
8815 return SetCGInfo(new AVRTargetCodeGenInfo(Types));
8817 case llvm::Triple::aarch64:
8818 case llvm::Triple::aarch64_be: {
8819 AArch64ABIInfo::ABIKind Kind = AArch64ABIInfo::AAPCS;
8820 if (getTarget().getABI() == "darwinpcs")
8821 Kind = AArch64ABIInfo::DarwinPCS;
8822 else if (Triple.isOSWindows())
8824 new WindowsAArch64TargetCodeGenInfo(Types, AArch64ABIInfo::Win64));
8826 return SetCGInfo(new AArch64TargetCodeGenInfo(Types, Kind));
8829 case llvm::Triple::wasm32:
8830 case llvm::Triple::wasm64:
8831 return SetCGInfo(new WebAssemblyTargetCodeGenInfo(Types));
8833 case llvm::Triple::arm:
8834 case llvm::Triple::armeb:
8835 case llvm::Triple::thumb:
8836 case llvm::Triple::thumbeb: {
8837 if (Triple.getOS() == llvm::Triple::Win32) {
8839 new WindowsARMTargetCodeGenInfo(Types, ARMABIInfo::AAPCS_VFP));
8842 ARMABIInfo::ABIKind Kind = ARMABIInfo::AAPCS;
8843 StringRef ABIStr = getTarget().getABI();
8844 if (ABIStr == "apcs-gnu")
8845 Kind = ARMABIInfo::APCS;
8846 else if (ABIStr == "aapcs16")
8847 Kind = ARMABIInfo::AAPCS16_VFP;
8848 else if (CodeGenOpts.FloatABI == "hard" ||
8849 (CodeGenOpts.FloatABI != "soft" &&
8850 (Triple.getEnvironment() == llvm::Triple::GNUEABIHF ||
8851 Triple.getEnvironment() == llvm::Triple::MuslEABIHF ||
8852 Triple.getEnvironment() == llvm::Triple::EABIHF)))
8853 Kind = ARMABIInfo::AAPCS_VFP;
8855 return SetCGInfo(new ARMTargetCodeGenInfo(Types, Kind));
8858 case llvm::Triple::ppc:
8860 new PPC32TargetCodeGenInfo(Types, CodeGenOpts.FloatABI == "soft"));
8861 case llvm::Triple::ppc64:
8862 if (Triple.isOSBinFormatELF()) {
8863 PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv1;
8864 if (getTarget().getABI() == "elfv2")
8865 Kind = PPC64_SVR4_ABIInfo::ELFv2;
8866 bool HasQPX = getTarget().getABI() == "elfv1-qpx";
8867 bool IsSoftFloat = CodeGenOpts.FloatABI == "soft";
8869 return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX,
8872 return SetCGInfo(new PPC64TargetCodeGenInfo(Types));
8873 case llvm::Triple::ppc64le: {
8874 assert(Triple.isOSBinFormatELF() && "PPC64 LE non-ELF not supported!");
8875 PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv2;
8876 if (getTarget().getABI() == "elfv1" || getTarget().getABI() == "elfv1-qpx")
8877 Kind = PPC64_SVR4_ABIInfo::ELFv1;
8878 bool HasQPX = getTarget().getABI() == "elfv1-qpx";
8879 bool IsSoftFloat = CodeGenOpts.FloatABI == "soft";
8881 return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX,
8885 case llvm::Triple::nvptx:
8886 case llvm::Triple::nvptx64:
8887 return SetCGInfo(new NVPTXTargetCodeGenInfo(Types));
8889 case llvm::Triple::msp430:
8890 return SetCGInfo(new MSP430TargetCodeGenInfo(Types));
8892 case llvm::Triple::systemz: {
8893 bool HasVector = getTarget().getABI() == "vector";
8894 return SetCGInfo(new SystemZTargetCodeGenInfo(Types, HasVector));
8897 case llvm::Triple::tce:
8898 case llvm::Triple::tcele:
8899 return SetCGInfo(new TCETargetCodeGenInfo(Types));
8901 case llvm::Triple::x86: {
8902 bool IsDarwinVectorABI = Triple.isOSDarwin();
8903 bool RetSmallStructInRegABI =
8904 X86_32TargetCodeGenInfo::isStructReturnInRegABI(Triple, CodeGenOpts);
8905 bool IsWin32FloatStructABI = Triple.isOSWindows() && !Triple.isOSCygMing();
8907 if (Triple.getOS() == llvm::Triple::Win32) {
8908 return SetCGInfo(new WinX86_32TargetCodeGenInfo(
8909 Types, IsDarwinVectorABI, RetSmallStructInRegABI,
8910 IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters));
8912 return SetCGInfo(new X86_32TargetCodeGenInfo(
8913 Types, IsDarwinVectorABI, RetSmallStructInRegABI,
8914 IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters,
8915 CodeGenOpts.FloatABI == "soft"));
8919 case llvm::Triple::x86_64: {
8920 StringRef ABI = getTarget().getABI();
8921 X86AVXABILevel AVXLevel =
8923 ? X86AVXABILevel::AVX512
8924 : ABI == "avx" ? X86AVXABILevel::AVX : X86AVXABILevel::None);
8926 switch (Triple.getOS()) {
8927 case llvm::Triple::Win32:
8928 return SetCGInfo(new WinX86_64TargetCodeGenInfo(Types, AVXLevel));
8929 case llvm::Triple::PS4:
8930 return SetCGInfo(new PS4TargetCodeGenInfo(Types, AVXLevel));
8932 return SetCGInfo(new X86_64TargetCodeGenInfo(Types, AVXLevel));
8935 case llvm::Triple::hexagon:
8936 return SetCGInfo(new HexagonTargetCodeGenInfo(Types));
8937 case llvm::Triple::lanai:
8938 return SetCGInfo(new LanaiTargetCodeGenInfo(Types));
8939 case llvm::Triple::r600:
8940 return SetCGInfo(new AMDGPUTargetCodeGenInfo(Types));
8941 case llvm::Triple::amdgcn:
8942 return SetCGInfo(new AMDGPUTargetCodeGenInfo(Types));
8943 case llvm::Triple::sparc:
8944 return SetCGInfo(new SparcV8TargetCodeGenInfo(Types));
8945 case llvm::Triple::sparcv9:
8946 return SetCGInfo(new SparcV9TargetCodeGenInfo(Types));
8947 case llvm::Triple::xcore:
8948 return SetCGInfo(new XCoreTargetCodeGenInfo(Types));
8949 case llvm::Triple::spir:
8950 case llvm::Triple::spir64:
8951 return SetCGInfo(new SPIRTargetCodeGenInfo(Types));
8955 /// Create an OpenCL kernel for an enqueued block.
8957 /// The kernel has the same function type as the block invoke function. Its
8958 /// name is the name of the block invoke function postfixed with "_kernel".
8959 /// It simply calls the block invoke function then returns.
8961 TargetCodeGenInfo::createEnqueuedBlockKernel(CodeGenFunction &CGF,
8962 llvm::Function *Invoke,
8963 llvm::Value *BlockLiteral) const {
8964 auto *InvokeFT = Invoke->getFunctionType();
8965 llvm::SmallVector<llvm::Type *, 2> ArgTys;
8966 for (auto &P : InvokeFT->params())
8967 ArgTys.push_back(P);
8968 auto &C = CGF.getLLVMContext();
8969 std::string Name = Invoke->getName().str() + "_kernel";
8970 auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false);
8971 auto *F = llvm::Function::Create(FT, llvm::GlobalValue::InternalLinkage, Name,
8972 &CGF.CGM.getModule());
8973 auto IP = CGF.Builder.saveIP();
8974 auto *BB = llvm::BasicBlock::Create(C, "entry", F);
8975 auto &Builder = CGF.Builder;
8976 Builder.SetInsertPoint(BB);
8977 llvm::SmallVector<llvm::Value *, 2> Args;
8978 for (auto &A : F->args())
8980 Builder.CreateCall(Invoke, Args);
8981 Builder.CreateRetVoid();
8982 Builder.restoreIP(IP);
8986 /// Create an OpenCL kernel for an enqueued block.
8988 /// The type of the first argument (the block literal) is the struct type
8989 /// of the block literal instead of a pointer type. The first argument
8990 /// (block literal) is passed directly by value to the kernel. The kernel
8991 /// allocates the same type of struct on stack and stores the block literal
8992 /// to it and passes its pointer to the block invoke function. The kernel
8993 /// has "enqueued-block" function attribute and kernel argument metadata.
8994 llvm::Function *AMDGPUTargetCodeGenInfo::createEnqueuedBlockKernel(
8995 CodeGenFunction &CGF, llvm::Function *Invoke,
8996 llvm::Value *BlockLiteral) const {
8997 auto &Builder = CGF.Builder;
8998 auto &C = CGF.getLLVMContext();
9000 auto *BlockTy = BlockLiteral->getType()->getPointerElementType();
9001 auto *InvokeFT = Invoke->getFunctionType();
9002 llvm::SmallVector<llvm::Type *, 2> ArgTys;
9003 llvm::SmallVector<llvm::Metadata *, 8> AddressQuals;
9004 llvm::SmallVector<llvm::Metadata *, 8> AccessQuals;
9005 llvm::SmallVector<llvm::Metadata *, 8> ArgTypeNames;
9006 llvm::SmallVector<llvm::Metadata *, 8> ArgBaseTypeNames;
9007 llvm::SmallVector<llvm::Metadata *, 8> ArgTypeQuals;
9008 llvm::SmallVector<llvm::Metadata *, 8> ArgNames;
9010 ArgTys.push_back(BlockTy);
9011 ArgTypeNames.push_back(llvm::MDString::get(C, "__block_literal"));
9012 AddressQuals.push_back(llvm::ConstantAsMetadata::get(Builder.getInt32(0)));
9013 ArgBaseTypeNames.push_back(llvm::MDString::get(C, "__block_literal"));
9014 ArgTypeQuals.push_back(llvm::MDString::get(C, ""));
9015 AccessQuals.push_back(llvm::MDString::get(C, "none"));
9016 ArgNames.push_back(llvm::MDString::get(C, "block_literal"));
9017 for (unsigned I = 1, E = InvokeFT->getNumParams(); I < E; ++I) {
9018 ArgTys.push_back(InvokeFT->getParamType(I));
9019 ArgTypeNames.push_back(llvm::MDString::get(C, "void*"));
9020 AddressQuals.push_back(llvm::ConstantAsMetadata::get(Builder.getInt32(3)));
9021 AccessQuals.push_back(llvm::MDString::get(C, "none"));
9022 ArgBaseTypeNames.push_back(llvm::MDString::get(C, "void*"));
9023 ArgTypeQuals.push_back(llvm::MDString::get(C, ""));
9025 llvm::MDString::get(C, (Twine("local_arg") + Twine(I)).str()));
9027 std::string Name = Invoke->getName().str() + "_kernel";
9028 auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false);
9029 auto *F = llvm::Function::Create(FT, llvm::GlobalValue::InternalLinkage, Name,
9030 &CGF.CGM.getModule());
9031 F->addFnAttr("enqueued-block");
9032 auto IP = CGF.Builder.saveIP();
9033 auto *BB = llvm::BasicBlock::Create(C, "entry", F);
9034 Builder.SetInsertPoint(BB);
9035 unsigned BlockAlign = CGF.CGM.getDataLayout().getPrefTypeAlignment(BlockTy);
9036 auto *BlockPtr = Builder.CreateAlloca(BlockTy, nullptr);
9037 BlockPtr->setAlignment(BlockAlign);
9038 Builder.CreateAlignedStore(F->arg_begin(), BlockPtr, BlockAlign);
9039 auto *Cast = Builder.CreatePointerCast(BlockPtr, InvokeFT->getParamType(0));
9040 llvm::SmallVector<llvm::Value *, 2> Args;
9041 Args.push_back(Cast);
9042 for (auto I = F->arg_begin() + 1, E = F->arg_end(); I != E; ++I)
9044 Builder.CreateCall(Invoke, Args);
9045 Builder.CreateRetVoid();
9046 Builder.restoreIP(IP);
9048 F->setMetadata("kernel_arg_addr_space", llvm::MDNode::get(C, AddressQuals));
9049 F->setMetadata("kernel_arg_access_qual", llvm::MDNode::get(C, AccessQuals));
9050 F->setMetadata("kernel_arg_type", llvm::MDNode::get(C, ArgTypeNames));
9051 F->setMetadata("kernel_arg_base_type",
9052 llvm::MDNode::get(C, ArgBaseTypeNames));
9053 F->setMetadata("kernel_arg_type_qual", llvm::MDNode::get(C, ArgTypeQuals));
9054 if (CGF.CGM.getCodeGenOpts().EmitOpenCLArgMetadata)
9055 F->setMetadata("kernel_arg_name", llvm::MDNode::get(C, ArgNames));