1 //===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // These classes wrap the information about a call or function
11 // definition used to handle ABI compliancy.
13 //===----------------------------------------------------------------------===//
15 #include "TargetInfo.h"
19 #include "CodeGenFunction.h"
20 #include "clang/AST/RecordLayout.h"
21 #include "clang/CodeGen/CGFunctionInfo.h"
22 #include "clang/Frontend/CodeGenOptions.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/ADT/Triple.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/Type.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include <algorithm> // std::sort
30 using namespace clang;
31 using namespace CodeGen;
33 static void AssignToArrayRange(CodeGen::CGBuilderTy &Builder,
38 // Alternatively, we could emit this as a loop in the source.
39 for (unsigned I = FirstIndex; I <= LastIndex; ++I) {
41 Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I);
42 Builder.CreateStore(Value, Cell);
46 static bool isAggregateTypeForABI(QualType T) {
47 return !CodeGenFunction::hasScalarEvaluationKind(T) ||
48 T->isMemberFunctionPointerType();
51 ABIInfo::~ABIInfo() {}
53 static CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT,
55 const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl());
57 return CGCXXABI::RAA_Default;
58 return CXXABI.getRecordArgABI(RD);
61 static CGCXXABI::RecordArgABI getRecordArgABI(QualType T,
63 const RecordType *RT = T->getAs<RecordType>();
65 return CGCXXABI::RAA_Default;
66 return getRecordArgABI(RT, CXXABI);
69 /// Pass transparent unions as if they were the type of the first element. Sema
70 /// should ensure that all elements of the union have the same "machine type".
71 static QualType useFirstFieldIfTransparentUnion(QualType Ty) {
72 if (const RecordType *UT = Ty->getAsUnionType()) {
73 const RecordDecl *UD = UT->getDecl();
74 if (UD->hasAttr<TransparentUnionAttr>()) {
75 assert(!UD->field_empty() && "sema created an empty transparent union");
76 return UD->field_begin()->getType();
82 CGCXXABI &ABIInfo::getCXXABI() const {
83 return CGT.getCXXABI();
86 ASTContext &ABIInfo::getContext() const {
87 return CGT.getContext();
90 llvm::LLVMContext &ABIInfo::getVMContext() const {
91 return CGT.getLLVMContext();
94 const llvm::DataLayout &ABIInfo::getDataLayout() const {
95 return CGT.getDataLayout();
98 const TargetInfo &ABIInfo::getTarget() const {
99 return CGT.getTarget();
102 bool ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
106 bool ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
107 uint64_t Members) const {
111 bool ABIInfo::shouldSignExtUnsignedType(QualType Ty) const {
115 void ABIArgInfo::dump() const {
116 raw_ostream &OS = llvm::errs();
117 OS << "(ABIArgInfo Kind=";
120 OS << "Direct Type=";
121 if (llvm::Type *Ty = getCoerceToType())
133 OS << "InAlloca Offset=" << getInAllocaFieldIndex();
136 OS << "Indirect Align=" << getIndirectAlign()
137 << " ByVal=" << getIndirectByVal()
138 << " Realign=" << getIndirectRealign();
147 TargetCodeGenInfo::~TargetCodeGenInfo() { delete Info; }
149 // If someone can figure out a general rule for this, that would be great.
150 // It's probably just doomed to be platform-dependent, though.
151 unsigned TargetCodeGenInfo::getSizeOfUnwindException() const {
153 // x86-64 FreeBSD, Linux, Darwin
154 // x86-32 FreeBSD, Linux, Darwin
155 // PowerPC Linux, Darwin
156 // ARM Darwin (*not* EABI)
161 bool TargetCodeGenInfo::isNoProtoCallVariadic(const CallArgList &args,
162 const FunctionNoProtoType *fnType) const {
163 // The following conventions are known to require this to be false:
166 // For everything else, we just prefer false unless we opt out.
171 TargetCodeGenInfo::getDependentLibraryOption(llvm::StringRef Lib,
172 llvm::SmallString<24> &Opt) const {
173 // This assumes the user is passing a library name like "rt" instead of a
174 // filename like "librt.a/so", and that they don't care whether it's static or
180 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays);
182 /// isEmptyField - Return true iff a the field is "empty", that is it
183 /// is an unnamed bit-field or an (array of) empty record(s).
184 static bool isEmptyField(ASTContext &Context, const FieldDecl *FD,
186 if (FD->isUnnamedBitfield())
189 QualType FT = FD->getType();
191 // Constant arrays of empty records count as empty, strip them off.
192 // Constant arrays of zero length always count as empty.
194 while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
195 if (AT->getSize() == 0)
197 FT = AT->getElementType();
200 const RecordType *RT = FT->getAs<RecordType>();
204 // C++ record fields are never empty, at least in the Itanium ABI.
206 // FIXME: We should use a predicate for whether this behavior is true in the
208 if (isa<CXXRecordDecl>(RT->getDecl()))
211 return isEmptyRecord(Context, FT, AllowArrays);
214 /// isEmptyRecord - Return true iff a structure contains only empty
215 /// fields. Note that a structure with a flexible array member is not
216 /// considered empty.
217 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) {
218 const RecordType *RT = T->getAs<RecordType>();
221 const RecordDecl *RD = RT->getDecl();
222 if (RD->hasFlexibleArrayMember())
225 // If this is a C++ record, check the bases first.
226 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
227 for (const auto &I : CXXRD->bases())
228 if (!isEmptyRecord(Context, I.getType(), true))
231 for (const auto *I : RD->fields())
232 if (!isEmptyField(Context, I, AllowArrays))
237 /// isSingleElementStruct - Determine if a structure is a "single
238 /// element struct", i.e. it has exactly one non-empty field or
239 /// exactly one field which is itself a single element
240 /// struct. Structures with flexible array members are never
241 /// considered single element structs.
243 /// \return The field declaration for the single non-empty field, if
245 static const Type *isSingleElementStruct(QualType T, ASTContext &Context) {
246 const RecordType *RT = T->getAs<RecordType>();
250 const RecordDecl *RD = RT->getDecl();
251 if (RD->hasFlexibleArrayMember())
254 const Type *Found = nullptr;
256 // If this is a C++ record, check the bases first.
257 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
258 for (const auto &I : CXXRD->bases()) {
259 // Ignore empty records.
260 if (isEmptyRecord(Context, I.getType(), true))
263 // If we already found an element then this isn't a single-element struct.
267 // If this is non-empty and not a single element struct, the composite
268 // cannot be a single element struct.
269 Found = isSingleElementStruct(I.getType(), Context);
275 // Check for single element.
276 for (const auto *FD : RD->fields()) {
277 QualType FT = FD->getType();
279 // Ignore empty fields.
280 if (isEmptyField(Context, FD, true))
283 // If we already found an element then this isn't a single-element
288 // Treat single element arrays as the element.
289 while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
290 if (AT->getSize().getZExtValue() != 1)
292 FT = AT->getElementType();
295 if (!isAggregateTypeForABI(FT)) {
296 Found = FT.getTypePtr();
298 Found = isSingleElementStruct(FT, Context);
304 // We don't consider a struct a single-element struct if it has
305 // padding beyond the element type.
306 if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T))
312 static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) {
313 // Treat complex types as the element type.
314 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
315 Ty = CTy->getElementType();
317 // Check for a type which we know has a simple scalar argument-passing
318 // convention without any padding. (We're specifically looking for 32
319 // and 64-bit integer and integer-equivalents, float, and double.)
320 if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() &&
321 !Ty->isEnumeralType() && !Ty->isBlockPointerType())
324 uint64_t Size = Context.getTypeSize(Ty);
325 return Size == 32 || Size == 64;
328 /// canExpandIndirectArgument - Test whether an argument type which is to be
329 /// passed indirectly (on the stack) would have the equivalent layout if it was
330 /// expanded into separate arguments. If so, we prefer to do the latter to avoid
331 /// inhibiting optimizations.
333 // FIXME: This predicate is missing many cases, currently it just follows
334 // llvm-gcc (checks that all fields are 32-bit or 64-bit primitive types). We
335 // should probably make this smarter, or better yet make the LLVM backend
336 // capable of handling it.
337 static bool canExpandIndirectArgument(QualType Ty, ASTContext &Context) {
338 // We can only expand structure types.
339 const RecordType *RT = Ty->getAs<RecordType>();
343 // We can only expand (C) structures.
345 // FIXME: This needs to be generalized to handle classes as well.
346 const RecordDecl *RD = RT->getDecl();
350 // We try to expand CLike CXXRecordDecl.
351 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
352 if (!CXXRD->isCLike())
358 for (const auto *FD : RD->fields()) {
359 if (!is32Or64BitBasicType(FD->getType(), Context))
362 // FIXME: Reject bit-fields wholesale; there are two problems, we don't know
363 // how to expand them yet, and the predicate for telling if a bitfield still
364 // counts as "basic" is more complicated than what we were doing previously.
365 if (FD->isBitField())
368 Size += Context.getTypeSize(FD->getType());
371 // Make sure there are not any holes in the struct.
372 if (Size != Context.getTypeSize(Ty))
379 /// DefaultABIInfo - The default implementation for ABI specific
380 /// details. This implementation provides information which results in
381 /// self-consistent and sensible LLVM IR generation, but does not
382 /// conform to any particular ABI.
383 class DefaultABIInfo : public ABIInfo {
385 DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
387 ABIArgInfo classifyReturnType(QualType RetTy) const;
388 ABIArgInfo classifyArgumentType(QualType RetTy) const;
390 void computeInfo(CGFunctionInfo &FI) const override {
391 if (!getCXXABI().classifyReturnType(FI))
392 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
393 for (auto &I : FI.arguments())
394 I.info = classifyArgumentType(I.type);
397 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
398 CodeGenFunction &CGF) const override;
401 class DefaultTargetCodeGenInfo : public TargetCodeGenInfo {
403 DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
404 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
407 llvm::Value *DefaultABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
408 CodeGenFunction &CGF) const {
412 ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty) const {
413 Ty = useFirstFieldIfTransparentUnion(Ty);
415 if (isAggregateTypeForABI(Ty)) {
416 // Records with non-trivial destructors/copy-constructors should not be
418 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
419 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
421 return ABIArgInfo::getIndirect(0);
424 // Treat an enum type as its underlying type.
425 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
426 Ty = EnumTy->getDecl()->getIntegerType();
428 return (Ty->isPromotableIntegerType() ?
429 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
432 ABIArgInfo DefaultABIInfo::classifyReturnType(QualType RetTy) const {
433 if (RetTy->isVoidType())
434 return ABIArgInfo::getIgnore();
436 if (isAggregateTypeForABI(RetTy))
437 return ABIArgInfo::getIndirect(0);
439 // Treat an enum type as its underlying type.
440 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
441 RetTy = EnumTy->getDecl()->getIntegerType();
443 return (RetTy->isPromotableIntegerType() ?
444 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
447 //===----------------------------------------------------------------------===//
448 // le32/PNaCl bitcode ABI Implementation
450 // This is a simplified version of the x86_32 ABI. Arguments and return values
451 // are always passed on the stack.
452 //===----------------------------------------------------------------------===//
454 class PNaClABIInfo : public ABIInfo {
456 PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
458 ABIArgInfo classifyReturnType(QualType RetTy) const;
459 ABIArgInfo classifyArgumentType(QualType RetTy) const;
461 void computeInfo(CGFunctionInfo &FI) const override;
462 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
463 CodeGenFunction &CGF) const override;
466 class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
468 PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
469 : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {}
472 void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
473 if (!getCXXABI().classifyReturnType(FI))
474 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
476 for (auto &I : FI.arguments())
477 I.info = classifyArgumentType(I.type);
480 llvm::Value *PNaClABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
481 CodeGenFunction &CGF) const {
485 /// \brief Classify argument of given type \p Ty.
486 ABIArgInfo PNaClABIInfo::classifyArgumentType(QualType Ty) const {
487 if (isAggregateTypeForABI(Ty)) {
488 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
489 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
490 return ABIArgInfo::getIndirect(0);
491 } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
492 // Treat an enum type as its underlying type.
493 Ty = EnumTy->getDecl()->getIntegerType();
494 } else if (Ty->isFloatingType()) {
495 // Floating-point types don't go inreg.
496 return ABIArgInfo::getDirect();
499 return (Ty->isPromotableIntegerType() ?
500 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
503 ABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const {
504 if (RetTy->isVoidType())
505 return ABIArgInfo::getIgnore();
507 // In the PNaCl ABI we always return records/structures on the stack.
508 if (isAggregateTypeForABI(RetTy))
509 return ABIArgInfo::getIndirect(0);
511 // Treat an enum type as its underlying type.
512 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
513 RetTy = EnumTy->getDecl()->getIntegerType();
515 return (RetTy->isPromotableIntegerType() ?
516 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
519 /// IsX86_MMXType - Return true if this is an MMX type.
520 bool IsX86_MMXType(llvm::Type *IRType) {
521 // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
522 return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
523 cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
524 IRType->getScalarSizeInBits() != 64;
527 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
528 StringRef Constraint,
530 if ((Constraint == "y" || Constraint == "&y") && Ty->isVectorTy()) {
531 if (cast<llvm::VectorType>(Ty)->getBitWidth() != 64) {
532 // Invalid MMX constraint
536 return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
539 // No operation needed
543 /// Returns true if this type can be passed in SSE registers with the
544 /// X86_VectorCall calling convention. Shared between x86_32 and x86_64.
545 static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) {
546 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
547 if (BT->isFloatingPoint() && BT->getKind() != BuiltinType::Half)
549 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
550 // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX
551 // registers specially.
552 unsigned VecSize = Context.getTypeSize(VT);
553 if (VecSize == 128 || VecSize == 256 || VecSize == 512)
559 /// Returns true if this aggregate is small enough to be passed in SSE registers
560 /// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64.
561 static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) {
562 return NumMembers <= 4;
565 //===----------------------------------------------------------------------===//
566 // X86-32 ABI Implementation
567 //===----------------------------------------------------------------------===//
569 /// \brief Similar to llvm::CCState, but for Clang.
571 CCState(unsigned CC) : CC(CC), FreeRegs(0), FreeSSERegs(0) {}
575 unsigned FreeSSERegs;
578 /// X86_32ABIInfo - The X86-32 ABI information.
579 class X86_32ABIInfo : public ABIInfo {
585 static const unsigned MinABIStackAlignInBytes = 4;
587 bool IsDarwinVectorABI;
588 bool IsSmallStructInRegABI;
589 bool IsWin32StructABI;
590 unsigned DefaultNumRegisterParameters;
592 static bool isRegisterSize(unsigned Size) {
593 return (Size == 8 || Size == 16 || Size == 32 || Size == 64);
596 bool isHomogeneousAggregateBaseType(QualType Ty) const override {
597 // FIXME: Assumes vectorcall is in use.
598 return isX86VectorTypeForVectorCall(getContext(), Ty);
601 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
602 uint64_t NumMembers) const override {
603 // FIXME: Assumes vectorcall is in use.
604 return isX86VectorCallAggregateSmallEnough(NumMembers);
607 bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const;
609 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
610 /// such that the argument will be passed in memory.
611 ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
613 ABIArgInfo getIndirectReturnResult(CCState &State) const;
615 /// \brief Return the alignment to use for the given type on the stack.
616 unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const;
618 Class classify(QualType Ty) const;
619 ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
620 ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
621 bool shouldUseInReg(QualType Ty, CCState &State, bool &NeedsPadding) const;
623 /// \brief Rewrite the function info so that all memory arguments use
625 void rewriteWithInAlloca(CGFunctionInfo &FI) const;
627 void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
628 unsigned &StackOffset, ABIArgInfo &Info,
629 QualType Type) const;
633 void computeInfo(CGFunctionInfo &FI) const override;
634 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
635 CodeGenFunction &CGF) const override;
637 X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool d, bool p, bool w,
639 : ABIInfo(CGT), IsDarwinVectorABI(d), IsSmallStructInRegABI(p),
640 IsWin32StructABI(w), DefaultNumRegisterParameters(r) {}
643 class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
645 X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
646 bool d, bool p, bool w, unsigned r)
647 :TargetCodeGenInfo(new X86_32ABIInfo(CGT, d, p, w, r)) {}
649 static bool isStructReturnInRegABI(
650 const llvm::Triple &Triple, const CodeGenOptions &Opts);
652 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
653 CodeGen::CodeGenModule &CGM) const override;
655 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
656 // Darwin uses different dwarf register numbers for EH.
657 if (CGM.getTarget().getTriple().isOSDarwin()) return 5;
661 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
662 llvm::Value *Address) const override;
664 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
665 StringRef Constraint,
666 llvm::Type* Ty) const override {
667 return X86AdjustInlineAsmType(CGF, Constraint, Ty);
670 void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue,
671 std::string &Constraints,
672 std::vector<llvm::Type *> &ResultRegTypes,
673 std::vector<llvm::Type *> &ResultTruncRegTypes,
674 std::vector<LValue> &ResultRegDests,
675 std::string &AsmString,
676 unsigned NumOutputs) const override;
679 getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
680 unsigned Sig = (0xeb << 0) | // jmp rel8
681 (0x06 << 8) | // .+0x08
684 return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
690 /// Rewrite input constraint references after adding some output constraints.
691 /// In the case where there is one output and one input and we add one output,
692 /// we need to replace all operand references greater than or equal to 1:
695 /// The result will be:
698 static void rewriteInputConstraintReferences(unsigned FirstIn,
700 std::string &AsmString) {
702 llvm::raw_string_ostream OS(Buf);
704 while (Pos < AsmString.size()) {
705 size_t DollarStart = AsmString.find('$', Pos);
706 if (DollarStart == std::string::npos)
707 DollarStart = AsmString.size();
708 size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart);
709 if (DollarEnd == std::string::npos)
710 DollarEnd = AsmString.size();
711 OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
713 size_t NumDollars = DollarEnd - DollarStart;
714 if (NumDollars % 2 != 0 && Pos < AsmString.size()) {
715 // We have an operand reference.
716 size_t DigitStart = Pos;
717 size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart);
718 if (DigitEnd == std::string::npos)
719 DigitEnd = AsmString.size();
720 StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
721 unsigned OperandIndex;
722 if (!OperandStr.getAsInteger(10, OperandIndex)) {
723 if (OperandIndex >= FirstIn)
724 OperandIndex += NumNewOuts;
732 AsmString = std::move(OS.str());
735 /// Add output constraints for EAX:EDX because they are return registers.
736 void X86_32TargetCodeGenInfo::addReturnRegisterOutputs(
737 CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints,
738 std::vector<llvm::Type *> &ResultRegTypes,
739 std::vector<llvm::Type *> &ResultTruncRegTypes,
740 std::vector<LValue> &ResultRegDests, std::string &AsmString,
741 unsigned NumOutputs) const {
742 uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType());
744 // Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is
746 if (!Constraints.empty())
748 if (RetWidth <= 32) {
749 Constraints += "={eax}";
750 ResultRegTypes.push_back(CGF.Int32Ty);
752 // Use the 'A' constraint for EAX:EDX.
754 ResultRegTypes.push_back(CGF.Int64Ty);
757 // Truncate EAX or EAX:EDX to an integer of the appropriate size.
758 llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth);
759 ResultTruncRegTypes.push_back(CoerceTy);
761 // Coerce the integer by bitcasting the return slot pointer.
762 ReturnSlot.setAddress(CGF.Builder.CreateBitCast(ReturnSlot.getAddress(),
763 CoerceTy->getPointerTo()));
764 ResultRegDests.push_back(ReturnSlot);
766 rewriteInputConstraintReferences(NumOutputs, 1, AsmString);
769 /// shouldReturnTypeInRegister - Determine if the given type should be
770 /// passed in a register (for the Darwin ABI).
771 bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
772 ASTContext &Context) const {
773 uint64_t Size = Context.getTypeSize(Ty);
775 // Type must be register sized.
776 if (!isRegisterSize(Size))
779 if (Ty->isVectorType()) {
780 // 64- and 128- bit vectors inside structures are not returned in
782 if (Size == 64 || Size == 128)
788 // If this is a builtin, pointer, enum, complex type, member pointer, or
789 // member function pointer it is ok.
790 if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() ||
791 Ty->isAnyComplexType() || Ty->isEnumeralType() ||
792 Ty->isBlockPointerType() || Ty->isMemberPointerType())
795 // Arrays are treated like records.
796 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty))
797 return shouldReturnTypeInRegister(AT->getElementType(), Context);
799 // Otherwise, it must be a record type.
800 const RecordType *RT = Ty->getAs<RecordType>();
801 if (!RT) return false;
803 // FIXME: Traverse bases here too.
805 // Structure types are passed in register if all fields would be
806 // passed in a register.
807 for (const auto *FD : RT->getDecl()->fields()) {
808 // Empty fields are ignored.
809 if (isEmptyField(Context, FD, true))
812 // Check fields recursively.
813 if (!shouldReturnTypeInRegister(FD->getType(), Context))
819 ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(CCState &State) const {
820 // If the return value is indirect, then the hidden argument is consuming one
822 if (State.FreeRegs) {
824 return ABIArgInfo::getIndirectInReg(/*Align=*/0, /*ByVal=*/false);
826 return ABIArgInfo::getIndirect(/*Align=*/0, /*ByVal=*/false);
829 ABIArgInfo X86_32ABIInfo::classifyReturnType(QualType RetTy, CCState &State) const {
830 if (RetTy->isVoidType())
831 return ABIArgInfo::getIgnore();
833 const Type *Base = nullptr;
834 uint64_t NumElts = 0;
835 if (State.CC == llvm::CallingConv::X86_VectorCall &&
836 isHomogeneousAggregate(RetTy, Base, NumElts)) {
837 // The LLVM struct type for such an aggregate should lower properly.
838 return ABIArgInfo::getDirect();
841 if (const VectorType *VT = RetTy->getAs<VectorType>()) {
842 // On Darwin, some vectors are returned in registers.
843 if (IsDarwinVectorABI) {
844 uint64_t Size = getContext().getTypeSize(RetTy);
846 // 128-bit vectors are a special case; they are returned in
847 // registers and we need to make sure to pick a type the LLVM
848 // backend will like.
850 return ABIArgInfo::getDirect(llvm::VectorType::get(
851 llvm::Type::getInt64Ty(getVMContext()), 2));
853 // Always return in register if it fits in a general purpose
854 // register, or if it is 64 bits and has a single element.
855 if ((Size == 8 || Size == 16 || Size == 32) ||
856 (Size == 64 && VT->getNumElements() == 1))
857 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
860 return getIndirectReturnResult(State);
863 return ABIArgInfo::getDirect();
866 if (isAggregateTypeForABI(RetTy)) {
867 if (const RecordType *RT = RetTy->getAs<RecordType>()) {
868 // Structures with flexible arrays are always indirect.
869 if (RT->getDecl()->hasFlexibleArrayMember())
870 return getIndirectReturnResult(State);
873 // If specified, structs and unions are always indirect.
874 if (!IsSmallStructInRegABI && !RetTy->isAnyComplexType())
875 return getIndirectReturnResult(State);
877 // Small structures which are register sized are generally returned
879 if (shouldReturnTypeInRegister(RetTy, getContext())) {
880 uint64_t Size = getContext().getTypeSize(RetTy);
882 // As a special-case, if the struct is a "single-element" struct, and
883 // the field is of type "float" or "double", return it in a
884 // floating-point register. (MSVC does not apply this special case.)
885 // We apply a similar transformation for pointer types to improve the
886 // quality of the generated IR.
887 if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
888 if ((!IsWin32StructABI && SeltTy->isRealFloatingType())
889 || SeltTy->hasPointerRepresentation())
890 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
892 // FIXME: We should be able to narrow this integer in cases with dead
894 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size));
897 return getIndirectReturnResult(State);
900 // Treat an enum type as its underlying type.
901 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
902 RetTy = EnumTy->getDecl()->getIntegerType();
904 return (RetTy->isPromotableIntegerType() ?
905 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
908 static bool isSSEVectorType(ASTContext &Context, QualType Ty) {
909 return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128;
912 static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) {
913 const RecordType *RT = Ty->getAs<RecordType>();
916 const RecordDecl *RD = RT->getDecl();
918 // If this is a C++ record, check the bases first.
919 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
920 for (const auto &I : CXXRD->bases())
921 if (!isRecordWithSSEVectorType(Context, I.getType()))
924 for (const auto *i : RD->fields()) {
925 QualType FT = i->getType();
927 if (isSSEVectorType(Context, FT))
930 if (isRecordWithSSEVectorType(Context, FT))
937 unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty,
938 unsigned Align) const {
939 // Otherwise, if the alignment is less than or equal to the minimum ABI
940 // alignment, just use the default; the backend will handle this.
941 if (Align <= MinABIStackAlignInBytes)
942 return 0; // Use default alignment.
944 // On non-Darwin, the stack type alignment is always 4.
945 if (!IsDarwinVectorABI) {
946 // Set explicit alignment, since we may need to realign the top.
947 return MinABIStackAlignInBytes;
950 // Otherwise, if the type contains an SSE vector type, the alignment is 16.
951 if (Align >= 16 && (isSSEVectorType(getContext(), Ty) ||
952 isRecordWithSSEVectorType(getContext(), Ty)))
955 return MinABIStackAlignInBytes;
958 ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal,
959 CCState &State) const {
961 if (State.FreeRegs) {
962 --State.FreeRegs; // Non-byval indirects just use one pointer.
963 return ABIArgInfo::getIndirectInReg(0, false);
965 return ABIArgInfo::getIndirect(0, false);
968 // Compute the byval alignment.
969 unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
970 unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign);
972 return ABIArgInfo::getIndirect(4, /*ByVal=*/true);
974 // If the stack alignment is less than the type alignment, realign the
976 bool Realign = TypeAlign > StackAlign;
977 return ABIArgInfo::getIndirect(StackAlign, /*ByVal=*/true, Realign);
980 X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const {
981 const Type *T = isSingleElementStruct(Ty, getContext());
985 if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
986 BuiltinType::Kind K = BT->getKind();
987 if (K == BuiltinType::Float || K == BuiltinType::Double)
993 bool X86_32ABIInfo::shouldUseInReg(QualType Ty, CCState &State,
994 bool &NeedsPadding) const {
995 NeedsPadding = false;
996 Class C = classify(Ty);
1000 unsigned Size = getContext().getTypeSize(Ty);
1001 unsigned SizeInRegs = (Size + 31) / 32;
1003 if (SizeInRegs == 0)
1006 if (SizeInRegs > State.FreeRegs) {
1011 State.FreeRegs -= SizeInRegs;
1013 if (State.CC == llvm::CallingConv::X86_FastCall ||
1014 State.CC == llvm::CallingConv::X86_VectorCall) {
1018 if (Ty->isIntegralOrEnumerationType())
1021 if (Ty->isPointerType())
1024 if (Ty->isReferenceType())
1028 NeedsPadding = true;
1036 ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
1037 CCState &State) const {
1038 // FIXME: Set alignment on indirect arguments.
1040 Ty = useFirstFieldIfTransparentUnion(Ty);
1042 // Check with the C++ ABI first.
1043 const RecordType *RT = Ty->getAs<RecordType>();
1045 CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
1046 if (RAA == CGCXXABI::RAA_Indirect) {
1047 return getIndirectResult(Ty, false, State);
1048 } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
1049 // The field index doesn't matter, we'll fix it up later.
1050 return ABIArgInfo::getInAlloca(/*FieldIndex=*/0);
1054 // vectorcall adds the concept of a homogenous vector aggregate, similar
1055 // to other targets.
1056 const Type *Base = nullptr;
1057 uint64_t NumElts = 0;
1058 if (State.CC == llvm::CallingConv::X86_VectorCall &&
1059 isHomogeneousAggregate(Ty, Base, NumElts)) {
1060 if (State.FreeSSERegs >= NumElts) {
1061 State.FreeSSERegs -= NumElts;
1062 if (Ty->isBuiltinType() || Ty->isVectorType())
1063 return ABIArgInfo::getDirect();
1064 return ABIArgInfo::getExpand();
1066 return getIndirectResult(Ty, /*ByVal=*/false, State);
1069 if (isAggregateTypeForABI(Ty)) {
1071 // Structs are always byval on win32, regardless of what they contain.
1072 if (IsWin32StructABI)
1073 return getIndirectResult(Ty, true, State);
1075 // Structures with flexible arrays are always indirect.
1076 if (RT->getDecl()->hasFlexibleArrayMember())
1077 return getIndirectResult(Ty, true, State);
1080 // Ignore empty structs/unions.
1081 if (isEmptyRecord(getContext(), Ty, true))
1082 return ABIArgInfo::getIgnore();
1084 llvm::LLVMContext &LLVMContext = getVMContext();
1085 llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
1087 if (shouldUseInReg(Ty, State, NeedsPadding)) {
1088 unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
1089 SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
1090 llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
1091 return ABIArgInfo::getDirectInReg(Result);
1093 llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr;
1095 // Expand small (<= 128-bit) record types when we know that the stack layout
1096 // of those arguments will match the struct. This is important because the
1097 // LLVM backend isn't smart enough to remove byval, which inhibits many
1099 if (getContext().getTypeSize(Ty) <= 4*32 &&
1100 canExpandIndirectArgument(Ty, getContext()))
1101 return ABIArgInfo::getExpandWithPadding(
1102 State.CC == llvm::CallingConv::X86_FastCall ||
1103 State.CC == llvm::CallingConv::X86_VectorCall,
1106 return getIndirectResult(Ty, true, State);
1109 if (const VectorType *VT = Ty->getAs<VectorType>()) {
1110 // On Darwin, some vectors are passed in memory, we handle this by passing
1111 // it as an i8/i16/i32/i64.
1112 if (IsDarwinVectorABI) {
1113 uint64_t Size = getContext().getTypeSize(Ty);
1114 if ((Size == 8 || Size == 16 || Size == 32) ||
1115 (Size == 64 && VT->getNumElements() == 1))
1116 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1120 if (IsX86_MMXType(CGT.ConvertType(Ty)))
1121 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
1123 return ABIArgInfo::getDirect();
1127 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
1128 Ty = EnumTy->getDecl()->getIntegerType();
1131 bool InReg = shouldUseInReg(Ty, State, NeedsPadding);
1133 if (Ty->isPromotableIntegerType()) {
1135 return ABIArgInfo::getExtendInReg();
1136 return ABIArgInfo::getExtend();
1139 return ABIArgInfo::getDirectInReg();
1140 return ABIArgInfo::getDirect();
1143 void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
1144 CCState State(FI.getCallingConvention());
1145 if (State.CC == llvm::CallingConv::X86_FastCall)
1147 else if (State.CC == llvm::CallingConv::X86_VectorCall) {
1149 State.FreeSSERegs = 6;
1150 } else if (FI.getHasRegParm())
1151 State.FreeRegs = FI.getRegParm();
1153 State.FreeRegs = DefaultNumRegisterParameters;
1155 if (!getCXXABI().classifyReturnType(FI)) {
1156 FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), State);
1157 } else if (FI.getReturnInfo().isIndirect()) {
1158 // The C++ ABI is not aware of register usage, so we have to check if the
1159 // return value was sret and put it in a register ourselves if appropriate.
1160 if (State.FreeRegs) {
1161 --State.FreeRegs; // The sret parameter consumes a register.
1162 FI.getReturnInfo().setInReg(true);
1166 // The chain argument effectively gives us another free register.
1167 if (FI.isChainCall())
1170 bool UsedInAlloca = false;
1171 for (auto &I : FI.arguments()) {
1172 I.info = classifyArgumentType(I.type, State);
1173 UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1176 // If we needed to use inalloca for any argument, do a second pass and rewrite
1177 // all the memory arguments to use inalloca.
1179 rewriteWithInAlloca(FI);
1183 X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1184 unsigned &StackOffset,
1185 ABIArgInfo &Info, QualType Type) const {
1186 assert(StackOffset % 4U == 0 && "unaligned inalloca struct");
1187 Info = ABIArgInfo::getInAlloca(FrameFields.size());
1188 FrameFields.push_back(CGT.ConvertTypeForMem(Type));
1189 StackOffset += getContext().getTypeSizeInChars(Type).getQuantity();
1191 // Insert padding bytes to respect alignment. For x86_32, each argument is 4
1193 if (StackOffset % 4U) {
1194 unsigned OldOffset = StackOffset;
1195 StackOffset = llvm::RoundUpToAlignment(StackOffset, 4U);
1196 unsigned NumBytes = StackOffset - OldOffset;
1198 llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
1199 Ty = llvm::ArrayType::get(Ty, NumBytes);
1200 FrameFields.push_back(Ty);
1204 static bool isArgInAlloca(const ABIArgInfo &Info) {
1205 // Leave ignored and inreg arguments alone.
1206 switch (Info.getKind()) {
1207 case ABIArgInfo::InAlloca:
1209 case ABIArgInfo::Indirect:
1210 assert(Info.getIndirectByVal());
1212 case ABIArgInfo::Ignore:
1214 case ABIArgInfo::Direct:
1215 case ABIArgInfo::Extend:
1216 case ABIArgInfo::Expand:
1217 if (Info.getInReg())
1221 llvm_unreachable("invalid enum");
1224 void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
1225 assert(IsWin32StructABI && "inalloca only supported on win32");
1227 // Build a packed struct type for all of the arguments in memory.
1228 SmallVector<llvm::Type *, 6> FrameFields;
1230 unsigned StackOffset = 0;
1231 CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end();
1233 // Put 'this' into the struct before 'sret', if necessary.
1235 FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
1236 ABIArgInfo &Ret = FI.getReturnInfo();
1237 if (Ret.isIndirect() && Ret.isSRetAfterThis() && !IsThisCall &&
1238 isArgInAlloca(I->info)) {
1239 addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1243 // Put the sret parameter into the inalloca struct if it's in memory.
1244 if (Ret.isIndirect() && !Ret.getInReg()) {
1245 CanQualType PtrTy = getContext().getPointerType(FI.getReturnType());
1246 addFieldToArgStruct(FrameFields, StackOffset, Ret, PtrTy);
1247 // On Windows, the hidden sret parameter is always returned in eax.
1248 Ret.setInAllocaSRet(IsWin32StructABI);
1251 // Skip the 'this' parameter in ecx.
1255 // Put arguments passed in memory into the struct.
1256 for (; I != E; ++I) {
1257 if (isArgInAlloca(I->info))
1258 addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1261 FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
1262 /*isPacked=*/true));
1265 llvm::Value *X86_32ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
1266 CodeGenFunction &CGF) const {
1267 llvm::Type *BPP = CGF.Int8PtrPtrTy;
1269 CGBuilderTy &Builder = CGF.Builder;
1270 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP,
1272 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur");
1274 // Compute if the address needs to be aligned
1275 unsigned Align = CGF.getContext().getTypeAlignInChars(Ty).getQuantity();
1276 Align = getTypeStackAlignInBytes(Ty, Align);
1277 Align = std::max(Align, 4U);
1279 // addr = (addr + align - 1) & -align;
1280 llvm::Value *Offset =
1281 llvm::ConstantInt::get(CGF.Int32Ty, Align - 1);
1282 Addr = CGF.Builder.CreateGEP(Addr, Offset);
1283 llvm::Value *AsInt = CGF.Builder.CreatePtrToInt(Addr,
1285 llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int32Ty, -Align);
1286 Addr = CGF.Builder.CreateIntToPtr(CGF.Builder.CreateAnd(AsInt, Mask),
1292 llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
1293 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy);
1296 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, Align);
1297 llvm::Value *NextAddr =
1298 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset),
1300 Builder.CreateStore(NextAddr, VAListAddrAsBPP);
1305 bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
1306 const llvm::Triple &Triple, const CodeGenOptions &Opts) {
1307 assert(Triple.getArch() == llvm::Triple::x86);
1309 switch (Opts.getStructReturnConvention()) {
1310 case CodeGenOptions::SRCK_Default:
1312 case CodeGenOptions::SRCK_OnStack: // -fpcc-struct-return
1314 case CodeGenOptions::SRCK_InRegs: // -freg-struct-return
1318 if (Triple.isOSDarwin())
1321 switch (Triple.getOS()) {
1322 case llvm::Triple::DragonFly:
1323 case llvm::Triple::FreeBSD:
1324 case llvm::Triple::OpenBSD:
1325 case llvm::Triple::Bitrig:
1326 case llvm::Triple::Win32:
1333 void X86_32TargetCodeGenInfo::SetTargetAttributes(const Decl *D,
1334 llvm::GlobalValue *GV,
1335 CodeGen::CodeGenModule &CGM) const {
1336 if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) {
1337 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1338 // Get the LLVM function.
1339 llvm::Function *Fn = cast<llvm::Function>(GV);
1341 // Now add the 'alignstack' attribute with a value of 16.
1342 llvm::AttrBuilder B;
1343 B.addStackAlignmentAttr(16);
1344 Fn->addAttributes(llvm::AttributeSet::FunctionIndex,
1345 llvm::AttributeSet::get(CGM.getLLVMContext(),
1346 llvm::AttributeSet::FunctionIndex,
1352 bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
1353 CodeGen::CodeGenFunction &CGF,
1354 llvm::Value *Address) const {
1355 CodeGen::CGBuilderTy &Builder = CGF.Builder;
1357 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
1359 // 0-7 are the eight integer registers; the order is different
1360 // on Darwin (for EH), but the range is the same.
1362 AssignToArrayRange(Builder, Address, Four8, 0, 8);
1364 if (CGF.CGM.getTarget().getTriple().isOSDarwin()) {
1365 // 12-16 are st(0..4). Not sure why we stop at 4.
1366 // These have size 16, which is sizeof(long double) on
1367 // platforms with 8-byte alignment for that type.
1368 llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
1369 AssignToArrayRange(Builder, Address, Sixteen8, 12, 16);
1372 // 9 is %eflags, which doesn't get a size on Darwin for some
1374 Builder.CreateStore(
1375 Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9));
1377 // 11-16 are st(0..5). Not sure why we stop at 5.
1378 // These have size 12, which is sizeof(long double) on
1379 // platforms with 4-byte alignment for that type.
1380 llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12);
1381 AssignToArrayRange(Builder, Address, Twelve8, 11, 16);
1387 //===----------------------------------------------------------------------===//
1388 // X86-64 ABI Implementation
1389 //===----------------------------------------------------------------------===//
1393 /// X86_64ABIInfo - The X86_64 ABI information.
1394 class X86_64ABIInfo : public ABIInfo {
1406 /// merge - Implement the X86_64 ABI merging algorithm.
1408 /// Merge an accumulating classification \arg Accum with a field
1409 /// classification \arg Field.
1411 /// \param Accum - The accumulating classification. This should
1412 /// always be either NoClass or the result of a previous merge
1413 /// call. In addition, this should never be Memory (the caller
1414 /// should just return Memory for the aggregate).
1415 static Class merge(Class Accum, Class Field);
1417 /// postMerge - Implement the X86_64 ABI post merging algorithm.
1419 /// Post merger cleanup, reduces a malformed Hi and Lo pair to
1420 /// final MEMORY or SSE classes when necessary.
1422 /// \param AggregateSize - The size of the current aggregate in
1423 /// the classification process.
1425 /// \param Lo - The classification for the parts of the type
1426 /// residing in the low word of the containing object.
1428 /// \param Hi - The classification for the parts of the type
1429 /// residing in the higher words of the containing object.
1431 void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
1433 /// classify - Determine the x86_64 register classes in which the
1434 /// given type T should be passed.
1436 /// \param Lo - The classification for the parts of the type
1437 /// residing in the low word of the containing object.
1439 /// \param Hi - The classification for the parts of the type
1440 /// residing in the high word of the containing object.
1442 /// \param OffsetBase - The bit offset of this type in the
1443 /// containing object. Some parameters are classified different
1444 /// depending on whether they straddle an eightbyte boundary.
1446 /// \param isNamedArg - Whether the argument in question is a "named"
1447 /// argument, as used in AMD64-ABI 3.5.7.
1449 /// If a word is unused its result will be NoClass; if a type should
1450 /// be passed in Memory then at least the classification of \arg Lo
1453 /// The \arg Lo class will be NoClass iff the argument is ignored.
1455 /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
1456 /// also be ComplexX87.
1457 void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
1458 bool isNamedArg) const;
1460 llvm::Type *GetByteVectorType(QualType Ty) const;
1461 llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType,
1462 unsigned IROffset, QualType SourceTy,
1463 unsigned SourceOffset) const;
1464 llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType,
1465 unsigned IROffset, QualType SourceTy,
1466 unsigned SourceOffset) const;
1468 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1469 /// such that the argument will be returned in memory.
1470 ABIArgInfo getIndirectReturnResult(QualType Ty) const;
1472 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1473 /// such that the argument will be passed in memory.
1475 /// \param freeIntRegs - The number of free integer registers remaining
1477 ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const;
1479 ABIArgInfo classifyReturnType(QualType RetTy) const;
1481 ABIArgInfo classifyArgumentType(QualType Ty,
1482 unsigned freeIntRegs,
1483 unsigned &neededInt,
1484 unsigned &neededSSE,
1485 bool isNamedArg) const;
1487 bool IsIllegalVectorType(QualType Ty) const;
1489 /// The 0.98 ABI revision clarified a lot of ambiguities,
1490 /// unfortunately in ways that were not always consistent with
1491 /// certain previous compilers. In particular, platforms which
1492 /// required strict binary compatibility with older versions of GCC
1493 /// may need to exempt themselves.
1494 bool honorsRevision0_98() const {
1495 return !getTarget().getTriple().isOSDarwin();
1498 // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on
1500 bool Has64BitPointers;
1503 X86_64ABIInfo(CodeGen::CodeGenTypes &CGT) :
1505 Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) {
1508 bool isPassedUsingAVXType(QualType type) const {
1509 unsigned neededInt, neededSSE;
1510 // The freeIntRegs argument doesn't matter here.
1511 ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE,
1512 /*isNamedArg*/true);
1513 if (info.isDirect()) {
1514 llvm::Type *ty = info.getCoerceToType();
1515 if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty))
1516 return (vectorTy->getBitWidth() > 128);
1521 void computeInfo(CGFunctionInfo &FI) const override;
1523 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
1524 CodeGenFunction &CGF) const override;
1526 bool has64BitPointers() const {
1527 return Has64BitPointers;
1530 bool hasAVX() const {
1531 return getTarget().getABI() == "avx";
1535 /// WinX86_64ABIInfo - The Windows X86_64 ABI information.
1536 class WinX86_64ABIInfo : public ABIInfo {
1538 ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs,
1539 bool IsReturnType) const;
1542 WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
1544 void computeInfo(CGFunctionInfo &FI) const override;
1546 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
1547 CodeGenFunction &CGF) const override;
1549 bool isHomogeneousAggregateBaseType(QualType Ty) const override {
1550 // FIXME: Assumes vectorcall is in use.
1551 return isX86VectorTypeForVectorCall(getContext(), Ty);
1554 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
1555 uint64_t NumMembers) const override {
1556 // FIXME: Assumes vectorcall is in use.
1557 return isX86VectorCallAggregateSmallEnough(NumMembers);
1561 class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
1563 X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
1564 : TargetCodeGenInfo(new X86_64ABIInfo(CGT)) {}
1566 const X86_64ABIInfo &getABIInfo() const {
1567 return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo());
1570 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
1574 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1575 llvm::Value *Address) const override {
1576 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
1578 // 0-15 are the 16 integer registers.
1580 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
1584 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
1585 StringRef Constraint,
1586 llvm::Type* Ty) const override {
1587 return X86AdjustInlineAsmType(CGF, Constraint, Ty);
1590 bool isNoProtoCallVariadic(const CallArgList &args,
1591 const FunctionNoProtoType *fnType) const override {
1592 // The default CC on x86-64 sets %al to the number of SSA
1593 // registers used, and GCC sets this when calling an unprototyped
1594 // function, so we override the default behavior. However, don't do
1595 // that when AVX types are involved: the ABI explicitly states it is
1596 // undefined, and it doesn't work in practice because of how the ABI
1597 // defines varargs anyway.
1598 if (fnType->getCallConv() == CC_C) {
1599 bool HasAVXType = false;
1600 for (CallArgList::const_iterator
1601 it = args.begin(), ie = args.end(); it != ie; ++it) {
1602 if (getABIInfo().isPassedUsingAVXType(it->Ty)) {
1612 return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType);
1616 getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
1618 if (getABIInfo().has64BitPointers())
1619 Sig = (0xeb << 0) | // jmp rel8
1620 (0x0a << 8) | // .+0x0c
1624 Sig = (0xeb << 0) | // jmp rel8
1625 (0x06 << 8) | // .+0x08
1628 return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
1631 unsigned getOpenMPSimdDefaultAlignment(QualType) const override {
1632 return getABIInfo().hasAVX() ? 32 : 16;
1636 class PS4TargetCodeGenInfo : public X86_64TargetCodeGenInfo {
1638 PS4TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
1639 : X86_64TargetCodeGenInfo(CGT) {}
1641 void getDependentLibraryOption(llvm::StringRef Lib,
1642 llvm::SmallString<24> &Opt) const override {
1648 static std::string qualifyWindowsLibrary(llvm::StringRef Lib) {
1649 // If the argument does not end in .lib, automatically add the suffix.
1650 // If the argument contains a space, enclose it in quotes.
1651 // This matches the behavior of MSVC.
1652 bool Quote = (Lib.find(" ") != StringRef::npos);
1653 std::string ArgStr = Quote ? "\"" : "";
1655 if (!Lib.endswith_lower(".lib"))
1657 ArgStr += Quote ? "\"" : "";
1661 class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
1663 WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
1664 bool d, bool p, bool w, unsigned RegParms)
1665 : X86_32TargetCodeGenInfo(CGT, d, p, w, RegParms) {}
1667 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
1668 CodeGen::CodeGenModule &CGM) const override;
1670 void getDependentLibraryOption(llvm::StringRef Lib,
1671 llvm::SmallString<24> &Opt) const override {
1672 Opt = "/DEFAULTLIB:";
1673 Opt += qualifyWindowsLibrary(Lib);
1676 void getDetectMismatchOption(llvm::StringRef Name,
1677 llvm::StringRef Value,
1678 llvm::SmallString<32> &Opt) const override {
1679 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
1683 static void addStackProbeSizeTargetAttribute(const Decl *D,
1684 llvm::GlobalValue *GV,
1685 CodeGen::CodeGenModule &CGM) {
1686 if (isa<FunctionDecl>(D)) {
1687 if (CGM.getCodeGenOpts().StackProbeSize != 4096) {
1688 llvm::Function *Fn = cast<llvm::Function>(GV);
1690 Fn->addFnAttr("stack-probe-size", llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
1695 void WinX86_32TargetCodeGenInfo::SetTargetAttributes(const Decl *D,
1696 llvm::GlobalValue *GV,
1697 CodeGen::CodeGenModule &CGM) const {
1698 X86_32TargetCodeGenInfo::SetTargetAttributes(D, GV, CGM);
1700 addStackProbeSizeTargetAttribute(D, GV, CGM);
1703 class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo {
1704 bool hasAVX() const { return getABIInfo().getTarget().getABI() == "avx"; }
1707 WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
1708 : TargetCodeGenInfo(new WinX86_64ABIInfo(CGT)) {}
1710 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
1711 CodeGen::CodeGenModule &CGM) const override;
1713 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
1717 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1718 llvm::Value *Address) const override {
1719 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
1721 // 0-15 are the 16 integer registers.
1723 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
1727 void getDependentLibraryOption(llvm::StringRef Lib,
1728 llvm::SmallString<24> &Opt) const override {
1729 Opt = "/DEFAULTLIB:";
1730 Opt += qualifyWindowsLibrary(Lib);
1733 void getDetectMismatchOption(llvm::StringRef Name,
1734 llvm::StringRef Value,
1735 llvm::SmallString<32> &Opt) const override {
1736 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
1739 unsigned getOpenMPSimdDefaultAlignment(QualType) const override {
1740 return hasAVX() ? 32 : 16;
1744 void WinX86_64TargetCodeGenInfo::SetTargetAttributes(const Decl *D,
1745 llvm::GlobalValue *GV,
1746 CodeGen::CodeGenModule &CGM) const {
1747 TargetCodeGenInfo::SetTargetAttributes(D, GV, CGM);
1749 addStackProbeSizeTargetAttribute(D, GV, CGM);
1753 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
1755 // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
1757 // (a) If one of the classes is Memory, the whole argument is passed in
1760 // (b) If X87UP is not preceded by X87, the whole argument is passed in
1763 // (c) If the size of the aggregate exceeds two eightbytes and the first
1764 // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
1765 // argument is passed in memory. NOTE: This is necessary to keep the
1766 // ABI working for processors that don't support the __m256 type.
1768 // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
1770 // Some of these are enforced by the merging logic. Others can arise
1771 // only with unions; for example:
1772 // union { _Complex double; unsigned; }
1774 // Note that clauses (b) and (c) were added in 0.98.
1778 if (Hi == X87Up && Lo != X87 && honorsRevision0_98())
1780 if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp))
1782 if (Hi == SSEUp && Lo != SSE)
1786 X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) {
1787 // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
1788 // classified recursively so that always two fields are
1789 // considered. The resulting class is calculated according to
1790 // the classes of the fields in the eightbyte:
1792 // (a) If both classes are equal, this is the resulting class.
1794 // (b) If one of the classes is NO_CLASS, the resulting class is
1797 // (c) If one of the classes is MEMORY, the result is the MEMORY
1800 // (d) If one of the classes is INTEGER, the result is the
1803 // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class,
1804 // MEMORY is used as class.
1806 // (f) Otherwise class SSE is used.
1808 // Accum should never be memory (we should have returned) or
1809 // ComplexX87 (because this cannot be passed in a structure).
1810 assert((Accum != Memory && Accum != ComplexX87) &&
1811 "Invalid accumulated classification during merge.");
1812 if (Accum == Field || Field == NoClass)
1814 if (Field == Memory)
1816 if (Accum == NoClass)
1818 if (Accum == Integer || Field == Integer)
1820 if (Field == X87 || Field == X87Up || Field == ComplexX87 ||
1821 Accum == X87 || Accum == X87Up)
1826 void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase,
1827 Class &Lo, Class &Hi, bool isNamedArg) const {
1828 // FIXME: This code can be simplified by introducing a simple value class for
1829 // Class pairs with appropriate constructor methods for the various
1832 // FIXME: Some of the split computations are wrong; unaligned vectors
1833 // shouldn't be passed in registers for example, so there is no chance they
1834 // can straddle an eightbyte. Verify & simplify.
1838 Class &Current = OffsetBase < 64 ? Lo : Hi;
1841 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
1842 BuiltinType::Kind k = BT->getKind();
1844 if (k == BuiltinType::Void) {
1846 } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) {
1849 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
1851 } else if ((k == BuiltinType::Float || k == BuiltinType::Double) ||
1852 (k == BuiltinType::LongDouble &&
1853 getTarget().getTriple().isOSNaCl())) {
1855 } else if (k == BuiltinType::LongDouble) {
1859 // FIXME: _Decimal32 and _Decimal64 are SSE.
1860 // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
1864 if (const EnumType *ET = Ty->getAs<EnumType>()) {
1865 // Classify the underlying integer type.
1866 classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
1870 if (Ty->hasPointerRepresentation()) {
1875 if (Ty->isMemberPointerType()) {
1876 if (Ty->isMemberFunctionPointerType()) {
1877 if (Has64BitPointers) {
1878 // If Has64BitPointers, this is an {i64, i64}, so classify both
1882 // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
1883 // straddles an eightbyte boundary, Hi should be classified as well.
1884 uint64_t EB_FuncPtr = (OffsetBase) / 64;
1885 uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
1886 if (EB_FuncPtr != EB_ThisAdj) {
1898 if (const VectorType *VT = Ty->getAs<VectorType>()) {
1899 uint64_t Size = getContext().getTypeSize(VT);
1901 // gcc passes all <4 x char>, <2 x short>, <1 x int>, <1 x
1902 // float> as integer.
1905 // If this type crosses an eightbyte boundary, it should be
1907 uint64_t EB_Real = (OffsetBase) / 64;
1908 uint64_t EB_Imag = (OffsetBase + Size - 1) / 64;
1909 if (EB_Real != EB_Imag)
1911 } else if (Size == 64) {
1912 // gcc passes <1 x double> in memory. :(
1913 if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double))
1916 // gcc passes <1 x long long> as INTEGER.
1917 if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::LongLong) ||
1918 VT->getElementType()->isSpecificBuiltinType(BuiltinType::ULongLong) ||
1919 VT->getElementType()->isSpecificBuiltinType(BuiltinType::Long) ||
1920 VT->getElementType()->isSpecificBuiltinType(BuiltinType::ULong))
1925 // If this type crosses an eightbyte boundary, it should be
1927 if (OffsetBase && OffsetBase != 64)
1929 } else if (Size == 128 || (hasAVX() && isNamedArg && Size == 256)) {
1930 // Arguments of 256-bits are split into four eightbyte chunks. The
1931 // least significant one belongs to class SSE and all the others to class
1932 // SSEUP. The original Lo and Hi design considers that types can't be
1933 // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
1934 // This design isn't correct for 256-bits, but since there're no cases
1935 // where the upper parts would need to be inspected, avoid adding
1936 // complexity and just consider Hi to match the 64-256 part.
1938 // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
1939 // registers if they are "named", i.e. not part of the "..." of a
1940 // variadic function.
1947 if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
1948 QualType ET = getContext().getCanonicalType(CT->getElementType());
1950 uint64_t Size = getContext().getTypeSize(Ty);
1951 if (ET->isIntegralOrEnumerationType()) {
1954 else if (Size <= 128)
1956 } else if (ET == getContext().FloatTy)
1958 else if (ET == getContext().DoubleTy ||
1959 (ET == getContext().LongDoubleTy &&
1960 getTarget().getTriple().isOSNaCl()))
1962 else if (ET == getContext().LongDoubleTy)
1963 Current = ComplexX87;
1965 // If this complex type crosses an eightbyte boundary then it
1967 uint64_t EB_Real = (OffsetBase) / 64;
1968 uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64;
1969 if (Hi == NoClass && EB_Real != EB_Imag)
1975 if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
1976 // Arrays are treated like structures.
1978 uint64_t Size = getContext().getTypeSize(Ty);
1980 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
1981 // than four eightbytes, ..., it has class MEMORY.
1985 // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
1986 // fields, it has class MEMORY.
1988 // Only need to check alignment of array base.
1989 if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
1992 // Otherwise implement simplified merge. We could be smarter about
1993 // this, but it isn't worth it and would be harder to verify.
1995 uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
1996 uint64_t ArraySize = AT->getSize().getZExtValue();
1998 // The only case a 256-bit wide vector could be used is when the array
1999 // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2000 // to work for sizes wider than 128, early check and fallback to memory.
2001 if (Size > 128 && EltSize != 256)
2004 for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) {
2005 Class FieldLo, FieldHi;
2006 classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
2007 Lo = merge(Lo, FieldLo);
2008 Hi = merge(Hi, FieldHi);
2009 if (Lo == Memory || Hi == Memory)
2013 postMerge(Size, Lo, Hi);
2014 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
2018 if (const RecordType *RT = Ty->getAs<RecordType>()) {
2019 uint64_t Size = getContext().getTypeSize(Ty);
2021 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2022 // than four eightbytes, ..., it has class MEMORY.
2026 // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
2027 // copy constructor or a non-trivial destructor, it is passed by invisible
2029 if (getRecordArgABI(RT, getCXXABI()))
2032 const RecordDecl *RD = RT->getDecl();
2034 // Assume variable sized types are passed in memory.
2035 if (RD->hasFlexibleArrayMember())
2038 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
2040 // Reset Lo class, this will be recomputed.
2043 // If this is a C++ record, classify the bases first.
2044 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2045 for (const auto &I : CXXRD->bases()) {
2046 assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2047 "Unexpected base class!");
2048 const CXXRecordDecl *Base =
2049 cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
2051 // Classify this field.
2053 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
2054 // single eightbyte, each is classified separately. Each eightbyte gets
2055 // initialized to class NO_CLASS.
2056 Class FieldLo, FieldHi;
2058 OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base));
2059 classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
2060 Lo = merge(Lo, FieldLo);
2061 Hi = merge(Hi, FieldHi);
2062 if (Lo == Memory || Hi == Memory)
2067 // Classify the fields one at a time, merging the results.
2069 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2070 i != e; ++i, ++idx) {
2071 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2072 bool BitField = i->isBitField();
2074 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
2075 // four eightbytes, or it contains unaligned fields, it has class MEMORY.
2077 // The only case a 256-bit wide vector could be used is when the struct
2078 // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2079 // to work for sizes wider than 128, early check and fallback to memory.
2081 if (Size > 128 && getContext().getTypeSize(i->getType()) != 256) {
2085 // Note, skip this test for bit-fields, see below.
2086 if (!BitField && Offset % getContext().getTypeAlign(i->getType())) {
2091 // Classify this field.
2093 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
2094 // exceeds a single eightbyte, each is classified
2095 // separately. Each eightbyte gets initialized to class
2097 Class FieldLo, FieldHi;
2099 // Bit-fields require special handling, they do not force the
2100 // structure to be passed in memory even if unaligned, and
2101 // therefore they can straddle an eightbyte.
2103 // Ignore padding bit-fields.
2104 if (i->isUnnamedBitfield())
2107 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2108 uint64_t Size = i->getBitWidthValue(getContext());
2110 uint64_t EB_Lo = Offset / 64;
2111 uint64_t EB_Hi = (Offset + Size - 1) / 64;
2114 assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes.");
2119 FieldHi = EB_Hi ? Integer : NoClass;
2122 classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
2123 Lo = merge(Lo, FieldLo);
2124 Hi = merge(Hi, FieldHi);
2125 if (Lo == Memory || Hi == Memory)
2129 postMerge(Size, Lo, Hi);
2133 ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const {
2134 // If this is a scalar LLVM value then assume LLVM will pass it in the right
2136 if (!isAggregateTypeForABI(Ty)) {
2137 // Treat an enum type as its underlying type.
2138 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2139 Ty = EnumTy->getDecl()->getIntegerType();
2141 return (Ty->isPromotableIntegerType() ?
2142 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
2145 return ABIArgInfo::getIndirect(0);
2148 bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const {
2149 if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
2150 uint64_t Size = getContext().getTypeSize(VecTy);
2151 unsigned LargestVector = hasAVX() ? 256 : 128;
2152 if (Size <= 64 || Size > LargestVector)
2159 ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty,
2160 unsigned freeIntRegs) const {
2161 // If this is a scalar LLVM value then assume LLVM will pass it in the right
2164 // This assumption is optimistic, as there could be free registers available
2165 // when we need to pass this argument in memory, and LLVM could try to pass
2166 // the argument in the free register. This does not seem to happen currently,
2167 // but this code would be much safer if we could mark the argument with
2168 // 'onstack'. See PR12193.
2169 if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty)) {
2170 // Treat an enum type as its underlying type.
2171 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2172 Ty = EnumTy->getDecl()->getIntegerType();
2174 return (Ty->isPromotableIntegerType() ?
2175 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
2178 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
2179 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
2181 // Compute the byval alignment. We specify the alignment of the byval in all
2182 // cases so that the mid-level optimizer knows the alignment of the byval.
2183 unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U);
2185 // Attempt to avoid passing indirect results using byval when possible. This
2186 // is important for good codegen.
2188 // We do this by coercing the value into a scalar type which the backend can
2189 // handle naturally (i.e., without using byval).
2191 // For simplicity, we currently only do this when we have exhausted all of the
2192 // free integer registers. Doing this when there are free integer registers
2193 // would require more care, as we would have to ensure that the coerced value
2194 // did not claim the unused register. That would require either reording the
2195 // arguments to the function (so that any subsequent inreg values came first),
2196 // or only doing this optimization when there were no following arguments that
2199 // We currently expect it to be rare (particularly in well written code) for
2200 // arguments to be passed on the stack when there are still free integer
2201 // registers available (this would typically imply large structs being passed
2202 // by value), so this seems like a fair tradeoff for now.
2204 // We can revisit this if the backend grows support for 'onstack' parameter
2205 // attributes. See PR12193.
2206 if (freeIntRegs == 0) {
2207 uint64_t Size = getContext().getTypeSize(Ty);
2209 // If this type fits in an eightbyte, coerce it into the matching integral
2210 // type, which will end up on the stack (with alignment 8).
2211 if (Align == 8 && Size <= 64)
2212 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
2216 return ABIArgInfo::getIndirect(Align);
2219 /// The ABI specifies that a value should be passed in a full vector XMM/YMM
2220 /// register. Pick an LLVM IR type that will be passed as a vector register.
2221 llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const {
2222 // Wrapper structs/arrays that only contain vectors are passed just like
2223 // vectors; strip them off if present.
2224 if (const Type *InnerTy = isSingleElementStruct(Ty, getContext()))
2225 Ty = QualType(InnerTy, 0);
2227 llvm::Type *IRType = CGT.ConvertType(Ty);
2228 assert(isa<llvm::VectorType>(IRType) &&
2229 "Trying to return a non-vector type in a vector register!");
2233 /// BitsContainNoUserData - Return true if the specified [start,end) bit range
2234 /// is known to either be off the end of the specified type or being in
2235 /// alignment padding. The user type specified is known to be at most 128 bits
2236 /// in size, and have passed through X86_64ABIInfo::classify with a successful
2237 /// classification that put one of the two halves in the INTEGER class.
2239 /// It is conservatively correct to return false.
2240 static bool BitsContainNoUserData(QualType Ty, unsigned StartBit,
2241 unsigned EndBit, ASTContext &Context) {
2242 // If the bytes being queried are off the end of the type, there is no user
2243 // data hiding here. This handles analysis of builtins, vectors and other
2244 // types that don't contain interesting padding.
2245 unsigned TySize = (unsigned)Context.getTypeSize(Ty);
2246 if (TySize <= StartBit)
2249 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) {
2250 unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
2251 unsigned NumElts = (unsigned)AT->getSize().getZExtValue();
2253 // Check each element to see if the element overlaps with the queried range.
2254 for (unsigned i = 0; i != NumElts; ++i) {
2255 // If the element is after the span we care about, then we're done..
2256 unsigned EltOffset = i*EltSize;
2257 if (EltOffset >= EndBit) break;
2259 unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0;
2260 if (!BitsContainNoUserData(AT->getElementType(), EltStart,
2261 EndBit-EltOffset, Context))
2264 // If it overlaps no elements, then it is safe to process as padding.
2268 if (const RecordType *RT = Ty->getAs<RecordType>()) {
2269 const RecordDecl *RD = RT->getDecl();
2270 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
2272 // If this is a C++ record, check the bases first.
2273 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2274 for (const auto &I : CXXRD->bases()) {
2275 assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2276 "Unexpected base class!");
2277 const CXXRecordDecl *Base =
2278 cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
2280 // If the base is after the span we care about, ignore it.
2281 unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base));
2282 if (BaseOffset >= EndBit) continue;
2284 unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0;
2285 if (!BitsContainNoUserData(I.getType(), BaseStart,
2286 EndBit-BaseOffset, Context))
2291 // Verify that no field has data that overlaps the region of interest. Yes
2292 // this could be sped up a lot by being smarter about queried fields,
2293 // however we're only looking at structs up to 16 bytes, so we don't care
2296 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2297 i != e; ++i, ++idx) {
2298 unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx);
2300 // If we found a field after the region we care about, then we're done.
2301 if (FieldOffset >= EndBit) break;
2303 unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0;
2304 if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
2309 // If nothing in this record overlapped the area of interest, then we're
2317 /// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a
2318 /// float member at the specified offset. For example, {int,{float}} has a
2319 /// float at offset 4. It is conservatively correct for this routine to return
2321 static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset,
2322 const llvm::DataLayout &TD) {
2323 // Base case if we find a float.
2324 if (IROffset == 0 && IRType->isFloatTy())
2327 // If this is a struct, recurse into the field at the specified offset.
2328 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
2329 const llvm::StructLayout *SL = TD.getStructLayout(STy);
2330 unsigned Elt = SL->getElementContainingOffset(IROffset);
2331 IROffset -= SL->getElementOffset(Elt);
2332 return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD);
2335 // If this is an array, recurse into the field at the specified offset.
2336 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
2337 llvm::Type *EltTy = ATy->getElementType();
2338 unsigned EltSize = TD.getTypeAllocSize(EltTy);
2339 IROffset -= IROffset/EltSize*EltSize;
2340 return ContainsFloatAtOffset(EltTy, IROffset, TD);
2347 /// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
2348 /// low 8 bytes of an XMM register, corresponding to the SSE class.
2349 llvm::Type *X86_64ABIInfo::
2350 GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset,
2351 QualType SourceTy, unsigned SourceOffset) const {
2352 // The only three choices we have are either double, <2 x float>, or float. We
2353 // pass as float if the last 4 bytes is just padding. This happens for
2354 // structs that contain 3 floats.
2355 if (BitsContainNoUserData(SourceTy, SourceOffset*8+32,
2356 SourceOffset*8+64, getContext()))
2357 return llvm::Type::getFloatTy(getVMContext());
2359 // We want to pass as <2 x float> if the LLVM IR type contains a float at
2360 // offset+0 and offset+4. Walk the LLVM IR type to find out if this is the
2362 if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) &&
2363 ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout()))
2364 return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2);
2366 return llvm::Type::getDoubleTy(getVMContext());
2370 /// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
2371 /// an 8-byte GPR. This means that we either have a scalar or we are talking
2372 /// about the high or low part of an up-to-16-byte struct. This routine picks
2373 /// the best LLVM IR type to represent this, which may be i64 or may be anything
2374 /// else that the backend will pass in a GPR that works better (e.g. i8, %foo*,
2377 /// PrefType is an LLVM IR type that corresponds to (part of) the IR type for
2378 /// the source type. IROffset is an offset in bytes into the LLVM IR type that
2379 /// the 8-byte value references. PrefType may be null.
2381 /// SourceTy is the source-level type for the entire argument. SourceOffset is
2382 /// an offset into this that we're processing (which is always either 0 or 8).
2384 llvm::Type *X86_64ABIInfo::
2385 GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
2386 QualType SourceTy, unsigned SourceOffset) const {
2387 // If we're dealing with an un-offset LLVM IR type, then it means that we're
2388 // returning an 8-byte unit starting with it. See if we can safely use it.
2389 if (IROffset == 0) {
2390 // Pointers and int64's always fill the 8-byte unit.
2391 if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) ||
2392 IRType->isIntegerTy(64))
2395 // If we have a 1/2/4-byte integer, we can use it only if the rest of the
2396 // goodness in the source type is just tail padding. This is allowed to
2397 // kick in for struct {double,int} on the int, but not on
2398 // struct{double,int,int} because we wouldn't return the second int. We
2399 // have to do this analysis on the source type because we can't depend on
2400 // unions being lowered a specific way etc.
2401 if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) ||
2402 IRType->isIntegerTy(32) ||
2403 (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) {
2404 unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 :
2405 cast<llvm::IntegerType>(IRType)->getBitWidth();
2407 if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth,
2408 SourceOffset*8+64, getContext()))
2413 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
2414 // If this is a struct, recurse into the field at the specified offset.
2415 const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy);
2416 if (IROffset < SL->getSizeInBytes()) {
2417 unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
2418 IROffset -= SL->getElementOffset(FieldIdx);
2420 return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
2421 SourceTy, SourceOffset);
2425 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
2426 llvm::Type *EltTy = ATy->getElementType();
2427 unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
2428 unsigned EltOffset = IROffset/EltSize*EltSize;
2429 return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
2433 // Okay, we don't have any better idea of what to pass, so we pass this in an
2434 // integer register that isn't too big to fit the rest of the struct.
2435 unsigned TySizeInBytes =
2436 (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity();
2438 assert(TySizeInBytes != SourceOffset && "Empty field?");
2440 // It is always safe to classify this as an integer type up to i64 that
2441 // isn't larger than the structure.
2442 return llvm::IntegerType::get(getVMContext(),
2443 std::min(TySizeInBytes-SourceOffset, 8U)*8);
2447 /// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
2448 /// be used as elements of a two register pair to pass or return, return a
2449 /// first class aggregate to represent them. For example, if the low part of
2450 /// a by-value argument should be passed as i32* and the high part as float,
2451 /// return {i32*, float}.
2453 GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi,
2454 const llvm::DataLayout &TD) {
2455 // In order to correctly satisfy the ABI, we need to the high part to start
2456 // at offset 8. If the high and low parts we inferred are both 4-byte types
2457 // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have
2458 // the second element at offset 8. Check for this:
2459 unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo);
2460 unsigned HiAlign = TD.getABITypeAlignment(Hi);
2461 unsigned HiStart = llvm::RoundUpToAlignment(LoSize, HiAlign);
2462 assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!");
2464 // To handle this, we have to increase the size of the low part so that the
2465 // second element will start at an 8 byte offset. We can't increase the size
2466 // of the second element because it might make us access off the end of the
2469 // There are only two sorts of types the ABI generation code can produce for
2470 // the low part of a pair that aren't 8 bytes in size: float or i8/i16/i32.
2471 // Promote these to a larger type.
2472 if (Lo->isFloatTy())
2473 Lo = llvm::Type::getDoubleTy(Lo->getContext());
2475 assert(Lo->isIntegerTy() && "Invalid/unknown lo type");
2476 Lo = llvm::Type::getInt64Ty(Lo->getContext());
2480 llvm::StructType *Result = llvm::StructType::get(Lo, Hi, nullptr);
2483 // Verify that the second element is at an 8-byte offset.
2484 assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
2485 "Invalid x86-64 argument pair!");
2489 ABIArgInfo X86_64ABIInfo::
2490 classifyReturnType(QualType RetTy) const {
2491 // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
2492 // classification algorithm.
2493 X86_64ABIInfo::Class Lo, Hi;
2494 classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);
2496 // Check some invariants.
2497 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
2498 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
2500 llvm::Type *ResType = nullptr;
2504 return ABIArgInfo::getIgnore();
2505 // If the low part is just padding, it takes no register, leave ResType
2507 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
2508 "Unknown missing lo part");
2513 llvm_unreachable("Invalid classification for lo word.");
2515 // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
2518 return getIndirectReturnResult(RetTy);
2520 // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
2521 // available register of the sequence %rax, %rdx is used.
2523 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
2525 // If we have a sign or zero extended integer, make sure to return Extend
2526 // so that the parameter gets the right LLVM IR attributes.
2527 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
2528 // Treat an enum type as its underlying type.
2529 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
2530 RetTy = EnumTy->getDecl()->getIntegerType();
2532 if (RetTy->isIntegralOrEnumerationType() &&
2533 RetTy->isPromotableIntegerType())
2534 return ABIArgInfo::getExtend();
2538 // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
2539 // available SSE register of the sequence %xmm0, %xmm1 is used.
2541 ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
2544 // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
2545 // returned on the X87 stack in %st0 as 80-bit x87 number.
2547 ResType = llvm::Type::getX86_FP80Ty(getVMContext());
2550 // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
2551 // part of the value is returned in %st0 and the imaginary part in
2554 assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.");
2555 ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()),
2556 llvm::Type::getX86_FP80Ty(getVMContext()),
2561 llvm::Type *HighPart = nullptr;
2563 // Memory was handled previously and X87 should
2564 // never occur as a hi class.
2567 llvm_unreachable("Invalid classification for hi word.");
2569 case ComplexX87: // Previously handled.
2574 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
2575 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
2576 return ABIArgInfo::getDirect(HighPart, 8);
2579 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
2580 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
2581 return ABIArgInfo::getDirect(HighPart, 8);
2584 // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
2585 // is passed in the next available eightbyte chunk if the last used
2588 // SSEUP should always be preceded by SSE, just widen.
2590 assert(Lo == SSE && "Unexpected SSEUp classification.");
2591 ResType = GetByteVectorType(RetTy);
2594 // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
2595 // returned together with the previous X87 value in %st0.
2597 // If X87Up is preceded by X87, we don't need to do
2598 // anything. However, in some cases with unions it may not be
2599 // preceded by X87. In such situations we follow gcc and pass the
2600 // extra bits in an SSE reg.
2602 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
2603 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
2604 return ABIArgInfo::getDirect(HighPart, 8);
2609 // If a high part was specified, merge it together with the low part. It is
2610 // known to pass in the high eightbyte of the result. We do this by forming a
2611 // first class struct aggregate with the high and low part: {low, high}
2613 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
2615 return ABIArgInfo::getDirect(ResType);
2618 ABIArgInfo X86_64ABIInfo::classifyArgumentType(
2619 QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE,
2623 Ty = useFirstFieldIfTransparentUnion(Ty);
2625 X86_64ABIInfo::Class Lo, Hi;
2626 classify(Ty, 0, Lo, Hi, isNamedArg);
2628 // Check some invariants.
2629 // FIXME: Enforce these by construction.
2630 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
2631 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
2635 llvm::Type *ResType = nullptr;
2639 return ABIArgInfo::getIgnore();
2640 // If the low part is just padding, it takes no register, leave ResType
2642 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
2643 "Unknown missing lo part");
2646 // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
2650 // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
2651 // COMPLEX_X87, it is passed in memory.
2654 if (getRecordArgABI(Ty, getCXXABI()) == CGCXXABI::RAA_Indirect)
2656 return getIndirectResult(Ty, freeIntRegs);
2660 llvm_unreachable("Invalid classification for lo word.");
2662 // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
2663 // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
2668 // Pick an 8-byte type based on the preferred type.
2669 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);
2671 // If we have a sign or zero extended integer, make sure to return Extend
2672 // so that the parameter gets the right LLVM IR attributes.
2673 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
2674 // Treat an enum type as its underlying type.
2675 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2676 Ty = EnumTy->getDecl()->getIntegerType();
2678 if (Ty->isIntegralOrEnumerationType() &&
2679 Ty->isPromotableIntegerType())
2680 return ABIArgInfo::getExtend();
2685 // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
2686 // available SSE register is used, the registers are taken in the
2687 // order from %xmm0 to %xmm7.
2689 llvm::Type *IRType = CGT.ConvertType(Ty);
2690 ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);
2696 llvm::Type *HighPart = nullptr;
2698 // Memory was handled previously, ComplexX87 and X87 should
2699 // never occur as hi classes, and X87Up must be preceded by X87,
2700 // which is passed in memory.
2704 llvm_unreachable("Invalid classification for hi word.");
2706 case NoClass: break;
2710 // Pick an 8-byte type based on the preferred type.
2711 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
2713 if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
2714 return ABIArgInfo::getDirect(HighPart, 8);
2717 // X87Up generally doesn't occur here (long double is passed in
2718 // memory), except in situations involving unions.
2721 HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
2723 if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
2724 return ABIArgInfo::getDirect(HighPart, 8);
2729 // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
2730 // eightbyte is passed in the upper half of the last used SSE
2731 // register. This only happens when 128-bit vectors are passed.
2733 assert(Lo == SSE && "Unexpected SSEUp classification");
2734 ResType = GetByteVectorType(Ty);
2738 // If a high part was specified, merge it together with the low part. It is
2739 // known to pass in the high eightbyte of the result. We do this by forming a
2740 // first class struct aggregate with the high and low part: {low, high}
2742 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
2744 return ABIArgInfo::getDirect(ResType);
2747 void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
2749 if (!getCXXABI().classifyReturnType(FI))
2750 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
2752 // Keep track of the number of assigned registers.
2753 unsigned freeIntRegs = 6, freeSSERegs = 8;
2755 // If the return value is indirect, then the hidden argument is consuming one
2756 // integer register.
2757 if (FI.getReturnInfo().isIndirect())
2760 // The chain argument effectively gives us another free register.
2761 if (FI.isChainCall())
2764 unsigned NumRequiredArgs = FI.getNumRequiredArgs();
2765 // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
2766 // get assigned (in left-to-right order) for passing as follows...
2768 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
2769 it != ie; ++it, ++ArgNo) {
2770 bool IsNamedArg = ArgNo < NumRequiredArgs;
2772 unsigned neededInt, neededSSE;
2773 it->info = classifyArgumentType(it->type, freeIntRegs, neededInt,
2774 neededSSE, IsNamedArg);
2776 // AMD64-ABI 3.2.3p3: If there are no registers available for any
2777 // eightbyte of an argument, the whole argument is passed on the
2778 // stack. If registers have already been assigned for some
2779 // eightbytes of such an argument, the assignments get reverted.
2780 if (freeIntRegs >= neededInt && freeSSERegs >= neededSSE) {
2781 freeIntRegs -= neededInt;
2782 freeSSERegs -= neededSSE;
2784 it->info = getIndirectResult(it->type, freeIntRegs);
2789 static llvm::Value *EmitVAArgFromMemory(llvm::Value *VAListAddr,
2791 CodeGenFunction &CGF) {
2792 llvm::Value *overflow_arg_area_p = CGF.Builder.CreateStructGEP(
2793 nullptr, VAListAddr, 2, "overflow_arg_area_p");
2794 llvm::Value *overflow_arg_area =
2795 CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area");
2797 // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
2798 // byte boundary if alignment needed by type exceeds 8 byte boundary.
2799 // It isn't stated explicitly in the standard, but in practice we use
2800 // alignment greater than 16 where necessary.
2801 uint64_t Align = CGF.getContext().getTypeAlign(Ty) / 8;
2803 // overflow_arg_area = (overflow_arg_area + align - 1) & -align;
2804 llvm::Value *Offset =
2805 llvm::ConstantInt::get(CGF.Int64Ty, Align - 1);
2806 overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset);
2807 llvm::Value *AsInt = CGF.Builder.CreatePtrToInt(overflow_arg_area,
2809 llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int64Ty, -(uint64_t)Align);
2811 CGF.Builder.CreateIntToPtr(CGF.Builder.CreateAnd(AsInt, Mask),
2812 overflow_arg_area->getType(),
2813 "overflow_arg_area.align");
2816 // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
2817 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
2819 CGF.Builder.CreateBitCast(overflow_arg_area,
2820 llvm::PointerType::getUnqual(LTy));
2822 // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
2823 // l->overflow_arg_area + sizeof(type).
2824 // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
2825 // an 8 byte boundary.
2827 uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8;
2828 llvm::Value *Offset =
2829 llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7);
2830 overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset,
2831 "overflow_arg_area.next");
2832 CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);
2834 // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
2838 llvm::Value *X86_64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
2839 CodeGenFunction &CGF) const {
2840 // Assume that va_list type is correct; should be pointer to LLVM type:
2844 // i8* overflow_arg_area;
2845 // i8* reg_save_area;
2847 unsigned neededInt, neededSSE;
2849 Ty = CGF.getContext().getCanonicalType(Ty);
2850 ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
2851 /*isNamedArg*/false);
2853 // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
2854 // in the registers. If not go to step 7.
2855 if (!neededInt && !neededSSE)
2856 return EmitVAArgFromMemory(VAListAddr, Ty, CGF);
2858 // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
2859 // general purpose registers needed to pass type and num_fp to hold
2860 // the number of floating point registers needed.
2862 // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
2863 // registers. In the case: l->gp_offset > 48 - num_gp * 8 or
2864 // l->fp_offset > 304 - num_fp * 16 go to step 7.
2866 // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of
2867 // register save space).
2869 llvm::Value *InRegs = nullptr;
2870 llvm::Value *gp_offset_p = nullptr, *gp_offset = nullptr;
2871 llvm::Value *fp_offset_p = nullptr, *fp_offset = nullptr;
2874 CGF.Builder.CreateStructGEP(nullptr, VAListAddr, 0, "gp_offset_p");
2875 gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset");
2876 InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
2877 InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp");
2882 CGF.Builder.CreateStructGEP(nullptr, VAListAddr, 1, "fp_offset_p");
2883 fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset");
2884 llvm::Value *FitsInFP =
2885 llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
2886 FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp");
2887 InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP;
2890 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
2891 llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
2892 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
2893 CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
2895 // Emit code to load the value if it was passed in registers.
2897 CGF.EmitBlock(InRegBlock);
2899 // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
2900 // an offset of l->gp_offset and/or l->fp_offset. This may require
2901 // copying to a temporary location in case the parameter is passed
2902 // in different register classes or requires an alignment greater
2903 // than 8 for general purpose registers and 16 for XMM registers.
2905 // FIXME: This really results in shameful code when we end up needing to
2906 // collect arguments from different places; often what should result in a
2907 // simple assembling of a structure from scattered addresses has many more
2908 // loads than necessary. Can we clean this up?
2909 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
2910 llvm::Value *RegAddr = CGF.Builder.CreateLoad(
2911 CGF.Builder.CreateStructGEP(nullptr, VAListAddr, 3), "reg_save_area");
2912 if (neededInt && neededSSE) {
2914 assert(AI.isDirect() && "Unexpected ABI info for mixed regs");
2915 llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType());
2916 llvm::Value *Tmp = CGF.CreateMemTemp(Ty);
2917 Tmp = CGF.Builder.CreateBitCast(Tmp, ST->getPointerTo());
2918 assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs");
2919 llvm::Type *TyLo = ST->getElementType(0);
2920 llvm::Type *TyHi = ST->getElementType(1);
2921 assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&
2922 "Unexpected ABI info for mixed regs");
2923 llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo);
2924 llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi);
2925 llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegAddr, gp_offset);
2926 llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegAddr, fp_offset);
2927 llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? FPAddr : GPAddr;
2928 llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? GPAddr : FPAddr;
2930 CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegLoAddr, PTyLo));
2931 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(ST, Tmp, 0));
2932 V = CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegHiAddr, PTyHi));
2933 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(ST, Tmp, 1));
2935 RegAddr = CGF.Builder.CreateBitCast(Tmp,
2936 llvm::PointerType::getUnqual(LTy));
2937 } else if (neededInt) {
2938 RegAddr = CGF.Builder.CreateGEP(RegAddr, gp_offset);
2939 RegAddr = CGF.Builder.CreateBitCast(RegAddr,
2940 llvm::PointerType::getUnqual(LTy));
2942 // Copy to a temporary if necessary to ensure the appropriate alignment.
2943 std::pair<CharUnits, CharUnits> SizeAlign =
2944 CGF.getContext().getTypeInfoInChars(Ty);
2945 uint64_t TySize = SizeAlign.first.getQuantity();
2946 unsigned TyAlign = SizeAlign.second.getQuantity();
2948 llvm::Value *Tmp = CGF.CreateMemTemp(Ty);
2949 CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, 8, false);
2952 } else if (neededSSE == 1) {
2953 RegAddr = CGF.Builder.CreateGEP(RegAddr, fp_offset);
2954 RegAddr = CGF.Builder.CreateBitCast(RegAddr,
2955 llvm::PointerType::getUnqual(LTy));
2957 assert(neededSSE == 2 && "Invalid number of needed registers!");
2958 // SSE registers are spaced 16 bytes apart in the register save
2959 // area, we need to collect the two eightbytes together.
2960 llvm::Value *RegAddrLo = CGF.Builder.CreateGEP(RegAddr, fp_offset);
2961 llvm::Value *RegAddrHi = CGF.Builder.CreateConstGEP1_32(RegAddrLo, 16);
2962 llvm::Type *DoubleTy = CGF.DoubleTy;
2963 llvm::Type *DblPtrTy =
2964 llvm::PointerType::getUnqual(DoubleTy);
2965 llvm::StructType *ST = llvm::StructType::get(DoubleTy, DoubleTy, nullptr);
2966 llvm::Value *V, *Tmp = CGF.CreateMemTemp(Ty);
2967 Tmp = CGF.Builder.CreateBitCast(Tmp, ST->getPointerTo());
2968 V = CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegAddrLo,
2970 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(ST, Tmp, 0));
2971 V = CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegAddrHi,
2973 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(ST, Tmp, 1));
2974 RegAddr = CGF.Builder.CreateBitCast(Tmp,
2975 llvm::PointerType::getUnqual(LTy));
2978 // AMD64-ABI 3.5.7p5: Step 5. Set:
2979 // l->gp_offset = l->gp_offset + num_gp * 8
2980 // l->fp_offset = l->fp_offset + num_fp * 16.
2982 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8);
2983 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset),
2987 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16);
2988 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset),
2991 CGF.EmitBranch(ContBlock);
2993 // Emit code to load the value if it was passed in memory.
2995 CGF.EmitBlock(InMemBlock);
2996 llvm::Value *MemAddr = EmitVAArgFromMemory(VAListAddr, Ty, CGF);
2998 // Return the appropriate result.
3000 CGF.EmitBlock(ContBlock);
3001 llvm::PHINode *ResAddr = CGF.Builder.CreatePHI(RegAddr->getType(), 2,
3003 ResAddr->addIncoming(RegAddr, InRegBlock);
3004 ResAddr->addIncoming(MemAddr, InMemBlock);
3008 ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
3009 bool IsReturnType) const {
3011 if (Ty->isVoidType())
3012 return ABIArgInfo::getIgnore();
3014 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3015 Ty = EnumTy->getDecl()->getIntegerType();
3017 TypeInfo Info = getContext().getTypeInfo(Ty);
3018 uint64_t Width = Info.Width;
3019 unsigned Align = getContext().toCharUnitsFromBits(Info.Align).getQuantity();
3021 const RecordType *RT = Ty->getAs<RecordType>();
3023 if (!IsReturnType) {
3024 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI()))
3025 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
3028 if (RT->getDecl()->hasFlexibleArrayMember())
3029 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
3031 // FIXME: mingw-w64-gcc emits 128-bit struct as i128
3032 if (Width == 128 && getTarget().getTriple().isWindowsGNUEnvironment())
3033 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
3037 // vectorcall adds the concept of a homogenous vector aggregate, similar to
3039 const Type *Base = nullptr;
3040 uint64_t NumElts = 0;
3041 if (FreeSSERegs && isHomogeneousAggregate(Ty, Base, NumElts)) {
3042 if (FreeSSERegs >= NumElts) {
3043 FreeSSERegs -= NumElts;
3044 if (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())
3045 return ABIArgInfo::getDirect();
3046 return ABIArgInfo::getExpand();
3048 return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3052 if (Ty->isMemberPointerType()) {
3053 // If the member pointer is represented by an LLVM int or ptr, pass it
3055 llvm::Type *LLTy = CGT.ConvertType(Ty);
3056 if (LLTy->isPointerTy() || LLTy->isIntegerTy())
3057 return ABIArgInfo::getDirect();
3060 if (RT || Ty->isAnyComplexType() || Ty->isMemberPointerType()) {
3061 // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
3062 // not 1, 2, 4, or 8 bytes, must be passed by reference."
3063 if (Width > 64 || !llvm::isPowerOf2_64(Width))
3064 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
3066 // Otherwise, coerce it to a small integer.
3067 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width));
3070 // Bool type is always extended to the ABI, other builtin types are not
3072 const BuiltinType *BT = Ty->getAs<BuiltinType>();
3073 if (BT && BT->getKind() == BuiltinType::Bool)
3074 return ABIArgInfo::getExtend();
3076 return ABIArgInfo::getDirect();
3079 void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3081 FI.getCallingConvention() == llvm::CallingConv::X86_VectorCall;
3083 // We can use up to 4 SSE return registers with vectorcall.
3084 unsigned FreeSSERegs = IsVectorCall ? 4 : 0;
3085 if (!getCXXABI().classifyReturnType(FI))
3086 FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true);
3088 // We can use up to 6 SSE register parameters with vectorcall.
3089 FreeSSERegs = IsVectorCall ? 6 : 0;
3090 for (auto &I : FI.arguments())
3091 I.info = classify(I.type, FreeSSERegs, false);
3094 llvm::Value *WinX86_64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
3095 CodeGenFunction &CGF) const {
3096 llvm::Type *BPP = CGF.Int8PtrPtrTy;
3098 CGBuilderTy &Builder = CGF.Builder;
3099 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP,
3101 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur");
3103 llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
3104 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy);
3107 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, 8);
3108 llvm::Value *NextAddr =
3109 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset),
3111 Builder.CreateStore(NextAddr, VAListAddrAsBPP);
3118 /// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
3119 class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
3121 PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
3123 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
3124 CodeGenFunction &CGF) const override;
3127 class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
3129 PPC32TargetCodeGenInfo(CodeGenTypes &CGT) : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT)) {}
3131 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
3132 // This is recovered from gcc output.
3133 return 1; // r1 is the dedicated stack pointer
3136 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3137 llvm::Value *Address) const override;
3139 unsigned getOpenMPSimdDefaultAlignment(QualType) const override {
3140 return 16; // Natural alignment for Altivec vectors.
3146 llvm::Value *PPC32_SVR4_ABIInfo::EmitVAArg(llvm::Value *VAListAddr,
3148 CodeGenFunction &CGF) const {
3149 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
3150 // TODO: Implement this. For now ignore.
3155 bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;
3156 bool isInt = Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType();
3157 llvm::Type *CharPtr = CGF.Int8PtrTy;
3158 llvm::Type *CharPtrPtr = CGF.Int8PtrPtrTy;
3160 CGBuilderTy &Builder = CGF.Builder;
3161 llvm::Value *GPRPtr = Builder.CreateBitCast(VAListAddr, CharPtr, "gprptr");
3162 llvm::Value *GPRPtrAsInt = Builder.CreatePtrToInt(GPRPtr, CGF.Int32Ty);
3163 llvm::Value *FPRPtrAsInt = Builder.CreateAdd(GPRPtrAsInt, Builder.getInt32(1));
3164 llvm::Value *FPRPtr = Builder.CreateIntToPtr(FPRPtrAsInt, CharPtr);
3165 llvm::Value *OverflowAreaPtrAsInt = Builder.CreateAdd(FPRPtrAsInt, Builder.getInt32(3));
3166 llvm::Value *OverflowAreaPtr = Builder.CreateIntToPtr(OverflowAreaPtrAsInt, CharPtrPtr);
3167 llvm::Value *RegsaveAreaPtrAsInt = Builder.CreateAdd(OverflowAreaPtrAsInt, Builder.getInt32(4));
3168 llvm::Value *RegsaveAreaPtr = Builder.CreateIntToPtr(RegsaveAreaPtrAsInt, CharPtrPtr);
3169 llvm::Value *GPR = Builder.CreateLoad(GPRPtr, false, "gpr");
3170 // Align GPR when TY is i64.
3172 llvm::Value *GPRAnd = Builder.CreateAnd(GPR, Builder.getInt8(1));
3173 llvm::Value *CC64 = Builder.CreateICmpEQ(GPRAnd, Builder.getInt8(1));
3174 llvm::Value *GPRPlusOne = Builder.CreateAdd(GPR, Builder.getInt8(1));
3175 GPR = Builder.CreateSelect(CC64, GPRPlusOne, GPR);
3177 llvm::Value *FPR = Builder.CreateLoad(FPRPtr, false, "fpr");
3178 llvm::Value *OverflowArea = Builder.CreateLoad(OverflowAreaPtr, false, "overflow_area");
3179 llvm::Value *OverflowAreaAsInt = Builder.CreatePtrToInt(OverflowArea, CGF.Int32Ty);
3180 llvm::Value *RegsaveArea = Builder.CreateLoad(RegsaveAreaPtr, false, "regsave_area");
3181 llvm::Value *RegsaveAreaAsInt = Builder.CreatePtrToInt(RegsaveArea, CGF.Int32Ty);
3183 llvm::Value *CC = Builder.CreateICmpULT(isInt ? GPR : FPR,
3184 Builder.getInt8(8), "cond");
3186 llvm::Value *RegConstant = Builder.CreateMul(isInt ? GPR : FPR,
3187 Builder.getInt8(isInt ? 4 : 8));
3189 llvm::Value *OurReg = Builder.CreateAdd(RegsaveAreaAsInt, Builder.CreateSExt(RegConstant, CGF.Int32Ty));
3191 if (Ty->isFloatingType())
3192 OurReg = Builder.CreateAdd(OurReg, Builder.getInt32(32));
3194 llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
3195 llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
3196 llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
3198 Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
3200 CGF.EmitBlock(UsingRegs);
3202 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
3203 llvm::Value *Result1 = Builder.CreateIntToPtr(OurReg, PTy);
3204 // Increase the GPR/FPR indexes.
3206 GPR = Builder.CreateAdd(GPR, Builder.getInt8(isI64 ? 2 : 1));
3207 Builder.CreateStore(GPR, GPRPtr);
3209 FPR = Builder.CreateAdd(FPR, Builder.getInt8(1));
3210 Builder.CreateStore(FPR, FPRPtr);
3212 CGF.EmitBranch(Cont);
3214 CGF.EmitBlock(UsingOverflow);
3216 // Increase the overflow area.
3217 llvm::Value *Result2 = Builder.CreateIntToPtr(OverflowAreaAsInt, PTy);
3218 OverflowAreaAsInt = Builder.CreateAdd(OverflowAreaAsInt, Builder.getInt32(isInt ? 4 : 8));
3219 Builder.CreateStore(Builder.CreateIntToPtr(OverflowAreaAsInt, CharPtr), OverflowAreaPtr);
3220 CGF.EmitBranch(Cont);
3222 CGF.EmitBlock(Cont);
3224 llvm::PHINode *Result = CGF.Builder.CreatePHI(PTy, 2, "vaarg.addr");
3225 Result->addIncoming(Result1, UsingRegs);
3226 Result->addIncoming(Result2, UsingOverflow);
3228 if (Ty->isAggregateType()) {
3229 llvm::Value *AGGPtr = Builder.CreateBitCast(Result, CharPtrPtr, "aggrptr") ;
3230 return Builder.CreateLoad(AGGPtr, false, "aggr");
3237 PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3238 llvm::Value *Address) const {
3239 // This is calculated from the LLVM and GCC tables and verified
3240 // against gcc output. AFAIK all ABIs use the same encoding.
3242 CodeGen::CGBuilderTy &Builder = CGF.Builder;
3244 llvm::IntegerType *i8 = CGF.Int8Ty;
3245 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
3246 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
3247 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
3249 // 0-31: r0-31, the 4-byte general-purpose registers
3250 AssignToArrayRange(Builder, Address, Four8, 0, 31);
3252 // 32-63: fp0-31, the 8-byte floating-point registers
3253 AssignToArrayRange(Builder, Address, Eight8, 32, 63);
3255 // 64-76 are various 4-byte special-purpose registers:
3262 AssignToArrayRange(Builder, Address, Four8, 64, 76);
3264 // 77-108: v0-31, the 16-byte vector registers
3265 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
3272 AssignToArrayRange(Builder, Address, Four8, 109, 113);
3280 /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
3281 class PPC64_SVR4_ABIInfo : public DefaultABIInfo {
3289 static const unsigned GPRBits = 64;
3293 // A vector of float or double will be promoted to <4 x f32> or <4 x f64> and
3294 // will be passed in a QPX register.
3295 bool IsQPXVectorTy(const Type *Ty) const {
3299 if (const VectorType *VT = Ty->getAs<VectorType>()) {
3300 unsigned NumElements = VT->getNumElements();
3301 if (NumElements == 1)
3304 if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) {
3305 if (getContext().getTypeSize(Ty) <= 256)
3307 } else if (VT->getElementType()->
3308 isSpecificBuiltinType(BuiltinType::Float)) {
3309 if (getContext().getTypeSize(Ty) <= 128)
3317 bool IsQPXVectorTy(QualType Ty) const {
3318 return IsQPXVectorTy(Ty.getTypePtr());
3322 PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX)
3323 : DefaultABIInfo(CGT), Kind(Kind), HasQPX(HasQPX) {}
3325 bool isPromotableTypeForABI(QualType Ty) const;
3326 bool isAlignedParamType(QualType Ty, bool &Align32) const;
3328 ABIArgInfo classifyReturnType(QualType RetTy) const;
3329 ABIArgInfo classifyArgumentType(QualType Ty) const;
3331 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
3332 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
3333 uint64_t Members) const override;
3335 // TODO: We can add more logic to computeInfo to improve performance.
3336 // Example: For aggregate arguments that fit in a register, we could
3337 // use getDirectInReg (as is done below for structs containing a single
3338 // floating-point value) to avoid pushing them to memory on function
3339 // entry. This would require changing the logic in PPCISelLowering
3340 // when lowering the parameters in the caller and args in the callee.
3341 void computeInfo(CGFunctionInfo &FI) const override {
3342 if (!getCXXABI().classifyReturnType(FI))
3343 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
3344 for (auto &I : FI.arguments()) {
3345 // We rely on the default argument classification for the most part.
3346 // One exception: An aggregate containing a single floating-point
3347 // or vector item must be passed in a register if one is available.
3348 const Type *T = isSingleElementStruct(I.type, getContext());
3350 const BuiltinType *BT = T->getAs<BuiltinType>();
3351 if (IsQPXVectorTy(T) ||
3352 (T->isVectorType() && getContext().getTypeSize(T) == 128) ||
3353 (BT && BT->isFloatingPoint())) {
3355 I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
3359 I.info = classifyArgumentType(I.type);
3363 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
3364 CodeGenFunction &CGF) const override;
3367 class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
3371 PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT,
3372 PPC64_SVR4_ABIInfo::ABIKind Kind, bool HasQPX)
3373 : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT, Kind, HasQPX)),
3376 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
3377 // This is recovered from gcc output.
3378 return 1; // r1 is the dedicated stack pointer
3381 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3382 llvm::Value *Address) const override;
3384 unsigned getOpenMPSimdDefaultAlignment(QualType QT) const override {
3386 if (const PointerType *PT = QT->getAs<PointerType>())
3387 if (PT->getPointeeType()->isSpecificBuiltinType(BuiltinType::Double))
3388 return 32; // Natural alignment for QPX doubles.
3390 return 16; // Natural alignment for Altivec and VSX vectors.
3394 class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
3396 PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
3398 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
3399 // This is recovered from gcc output.
3400 return 1; // r1 is the dedicated stack pointer
3403 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3404 llvm::Value *Address) const override;
3406 unsigned getOpenMPSimdDefaultAlignment(QualType) const override {
3407 return 16; // Natural alignment for Altivec vectors.
3413 // Return true if the ABI requires Ty to be passed sign- or zero-
3414 // extended to 64 bits.
3416 PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
3417 // Treat an enum type as its underlying type.
3418 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3419 Ty = EnumTy->getDecl()->getIntegerType();
3421 // Promotable integer types are required to be promoted by the ABI.
3422 if (Ty->isPromotableIntegerType())
3425 // In addition to the usual promotable integer types, we also need to
3426 // extend all 32-bit types, since the ABI requires promotion to 64 bits.
3427 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
3428 switch (BT->getKind()) {
3429 case BuiltinType::Int:
3430 case BuiltinType::UInt:
3439 /// isAlignedParamType - Determine whether a type requires 16-byte
3440 /// alignment in the parameter area.
3442 PPC64_SVR4_ABIInfo::isAlignedParamType(QualType Ty, bool &Align32) const {
3445 // Complex types are passed just like their elements.
3446 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
3447 Ty = CTy->getElementType();
3449 // Only vector types of size 16 bytes need alignment (larger types are
3450 // passed via reference, smaller types are not aligned).
3451 if (IsQPXVectorTy(Ty)) {
3452 if (getContext().getTypeSize(Ty) > 128)
3456 } else if (Ty->isVectorType()) {
3457 return getContext().getTypeSize(Ty) == 128;
3460 // For single-element float/vector structs, we consider the whole type
3461 // to have the same alignment requirements as its single element.
3462 const Type *AlignAsType = nullptr;
3463 const Type *EltType = isSingleElementStruct(Ty, getContext());
3465 const BuiltinType *BT = EltType->getAs<BuiltinType>();
3466 if (IsQPXVectorTy(EltType) || (EltType->isVectorType() &&
3467 getContext().getTypeSize(EltType) == 128) ||
3468 (BT && BT->isFloatingPoint()))
3469 AlignAsType = EltType;
3472 // Likewise for ELFv2 homogeneous aggregates.
3473 const Type *Base = nullptr;
3474 uint64_t Members = 0;
3475 if (!AlignAsType && Kind == ELFv2 &&
3476 isAggregateTypeForABI(Ty) && isHomogeneousAggregate(Ty, Base, Members))
3479 // With special case aggregates, only vector base types need alignment.
3480 if (AlignAsType && IsQPXVectorTy(AlignAsType)) {
3481 if (getContext().getTypeSize(AlignAsType) > 128)
3485 } else if (AlignAsType) {
3486 return AlignAsType->isVectorType();
3489 // Otherwise, we only need alignment for any aggregate type that
3490 // has an alignment requirement of >= 16 bytes.
3491 if (isAggregateTypeForABI(Ty) && getContext().getTypeAlign(Ty) >= 128) {
3492 if (HasQPX && getContext().getTypeAlign(Ty) >= 256)
3500 /// isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous
3501 /// aggregate. Base is set to the base element type, and Members is set
3502 /// to the number of base elements.
3503 bool ABIInfo::isHomogeneousAggregate(QualType Ty, const Type *&Base,
3504 uint64_t &Members) const {
3505 if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
3506 uint64_t NElements = AT->getSize().getZExtValue();
3509 if (!isHomogeneousAggregate(AT->getElementType(), Base, Members))
3511 Members *= NElements;
3512 } else if (const RecordType *RT = Ty->getAs<RecordType>()) {
3513 const RecordDecl *RD = RT->getDecl();
3514 if (RD->hasFlexibleArrayMember())
3519 // If this is a C++ record, check the bases first.
3520 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
3521 for (const auto &I : CXXRD->bases()) {
3522 // Ignore empty records.
3523 if (isEmptyRecord(getContext(), I.getType(), true))
3526 uint64_t FldMembers;
3527 if (!isHomogeneousAggregate(I.getType(), Base, FldMembers))
3530 Members += FldMembers;
3534 for (const auto *FD : RD->fields()) {
3535 // Ignore (non-zero arrays of) empty records.
3536 QualType FT = FD->getType();
3537 while (const ConstantArrayType *AT =
3538 getContext().getAsConstantArrayType(FT)) {
3539 if (AT->getSize().getZExtValue() == 0)
3541 FT = AT->getElementType();
3543 if (isEmptyRecord(getContext(), FT, true))
3546 // For compatibility with GCC, ignore empty bitfields in C++ mode.
3547 if (getContext().getLangOpts().CPlusPlus &&
3548 FD->isBitField() && FD->getBitWidthValue(getContext()) == 0)
3551 uint64_t FldMembers;
3552 if (!isHomogeneousAggregate(FD->getType(), Base, FldMembers))
3555 Members = (RD->isUnion() ?
3556 std::max(Members, FldMembers) : Members + FldMembers);
3562 // Ensure there is no padding.
3563 if (getContext().getTypeSize(Base) * Members !=
3564 getContext().getTypeSize(Ty))
3568 if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
3570 Ty = CT->getElementType();
3573 // Most ABIs only support float, double, and some vector type widths.
3574 if (!isHomogeneousAggregateBaseType(Ty))
3577 // The base type must be the same for all members. Types that
3578 // agree in both total size and mode (float vs. vector) are
3579 // treated as being equivalent here.
3580 const Type *TyPtr = Ty.getTypePtr();
3584 if (Base->isVectorType() != TyPtr->isVectorType() ||
3585 getContext().getTypeSize(Base) != getContext().getTypeSize(TyPtr))
3588 return Members > 0 && isHomogeneousAggregateSmallEnough(Base, Members);
3591 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
3592 // Homogeneous aggregates for ELFv2 must have base types of float,
3593 // double, long double, or 128-bit vectors.
3594 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
3595 if (BT->getKind() == BuiltinType::Float ||
3596 BT->getKind() == BuiltinType::Double ||
3597 BT->getKind() == BuiltinType::LongDouble)
3600 if (const VectorType *VT = Ty->getAs<VectorType>()) {
3601 if (getContext().getTypeSize(VT) == 128 || IsQPXVectorTy(Ty))
3607 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
3608 const Type *Base, uint64_t Members) const {
3609 // Vector types require one register, floating point types require one
3610 // or two registers depending on their size.
3612 Base->isVectorType() ? 1 : (getContext().getTypeSize(Base) + 63) / 64;
3614 // Homogeneous Aggregates may occupy at most 8 registers.
3615 return Members * NumRegs <= 8;
3619 PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
3620 Ty = useFirstFieldIfTransparentUnion(Ty);
3622 if (Ty->isAnyComplexType())
3623 return ABIArgInfo::getDirect();
3625 // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
3626 // or via reference (larger than 16 bytes).
3627 if (Ty->isVectorType() && !IsQPXVectorTy(Ty)) {
3628 uint64_t Size = getContext().getTypeSize(Ty);
3630 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
3631 else if (Size < 128) {
3632 llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
3633 return ABIArgInfo::getDirect(CoerceTy);
3637 if (isAggregateTypeForABI(Ty)) {
3638 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
3639 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
3642 uint64_t ABIAlign = isAlignedParamType(Ty, Align32) ?
3643 (Align32 ? 32 : 16) : 8;
3644 uint64_t TyAlign = getContext().getTypeAlign(Ty) / 8;
3646 // ELFv2 homogeneous aggregates are passed as array types.
3647 const Type *Base = nullptr;
3648 uint64_t Members = 0;
3649 if (Kind == ELFv2 &&
3650 isHomogeneousAggregate(Ty, Base, Members)) {
3651 llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
3652 llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
3653 return ABIArgInfo::getDirect(CoerceTy);
3656 // If an aggregate may end up fully in registers, we do not
3657 // use the ByVal method, but pass the aggregate as array.
3658 // This is usually beneficial since we avoid forcing the
3659 // back-end to store the argument to memory.
3660 uint64_t Bits = getContext().getTypeSize(Ty);
3661 if (Bits > 0 && Bits <= 8 * GPRBits) {
3662 llvm::Type *CoerceTy;
3664 // Types up to 8 bytes are passed as integer type (which will be
3665 // properly aligned in the argument save area doubleword).
3666 if (Bits <= GPRBits)
3667 CoerceTy = llvm::IntegerType::get(getVMContext(),
3668 llvm::RoundUpToAlignment(Bits, 8));
3669 // Larger types are passed as arrays, with the base type selected
3670 // according to the required alignment in the save area.
3672 uint64_t RegBits = ABIAlign * 8;
3673 uint64_t NumRegs = llvm::RoundUpToAlignment(Bits, RegBits) / RegBits;
3674 llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits);
3675 CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);
3678 return ABIArgInfo::getDirect(CoerceTy);
3681 // All other aggregates are passed ByVal.
3682 return ABIArgInfo::getIndirect(ABIAlign, /*ByVal=*/true,
3683 /*Realign=*/TyAlign > ABIAlign);
3686 return (isPromotableTypeForABI(Ty) ?
3687 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
3691 PPC64_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {
3692 if (RetTy->isVoidType())
3693 return ABIArgInfo::getIgnore();
3695 if (RetTy->isAnyComplexType())
3696 return ABIArgInfo::getDirect();
3698 // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
3699 // or via reference (larger than 16 bytes).
3700 if (RetTy->isVectorType() && !IsQPXVectorTy(RetTy)) {
3701 uint64_t Size = getContext().getTypeSize(RetTy);
3703 return ABIArgInfo::getIndirect(0);
3704 else if (Size < 128) {
3705 llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
3706 return ABIArgInfo::getDirect(CoerceTy);
3710 if (isAggregateTypeForABI(RetTy)) {
3711 // ELFv2 homogeneous aggregates are returned as array types.
3712 const Type *Base = nullptr;
3713 uint64_t Members = 0;
3714 if (Kind == ELFv2 &&
3715 isHomogeneousAggregate(RetTy, Base, Members)) {
3716 llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
3717 llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
3718 return ABIArgInfo::getDirect(CoerceTy);
3721 // ELFv2 small aggregates are returned in up to two registers.
3722 uint64_t Bits = getContext().getTypeSize(RetTy);
3723 if (Kind == ELFv2 && Bits <= 2 * GPRBits) {
3725 return ABIArgInfo::getIgnore();
3727 llvm::Type *CoerceTy;
3728 if (Bits > GPRBits) {
3729 CoerceTy = llvm::IntegerType::get(getVMContext(), GPRBits);
3730 CoerceTy = llvm::StructType::get(CoerceTy, CoerceTy, nullptr);
3732 CoerceTy = llvm::IntegerType::get(getVMContext(),
3733 llvm::RoundUpToAlignment(Bits, 8));
3734 return ABIArgInfo::getDirect(CoerceTy);
3737 // All other aggregates are returned indirectly.
3738 return ABIArgInfo::getIndirect(0);
3741 return (isPromotableTypeForABI(RetTy) ?
3742 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
3745 // Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
3746 llvm::Value *PPC64_SVR4_ABIInfo::EmitVAArg(llvm::Value *VAListAddr,
3748 CodeGenFunction &CGF) const {
3749 llvm::Type *BP = CGF.Int8PtrTy;
3750 llvm::Type *BPP = CGF.Int8PtrPtrTy;
3752 CGBuilderTy &Builder = CGF.Builder;
3753 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap");
3754 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur");
3756 // Handle types that require 16-byte alignment in the parameter save area.
3758 if (isAlignedParamType(Ty, Align32)) {
3759 llvm::Value *AddrAsInt = Builder.CreatePtrToInt(Addr, CGF.Int64Ty);
3760 AddrAsInt = Builder.CreateAdd(AddrAsInt,
3761 Builder.getInt64(Align32 ? 31 : 15));
3762 AddrAsInt = Builder.CreateAnd(AddrAsInt,
3763 Builder.getInt64(Align32 ? -32 : -16));
3764 Addr = Builder.CreateIntToPtr(AddrAsInt, BP, "ap.align");
3767 // Update the va_list pointer. The pointer should be bumped by the
3768 // size of the object. We can trust getTypeSize() except for a complex
3769 // type whose base type is smaller than a doubleword. For these, the
3770 // size of the object is 16 bytes; see below for further explanation.
3771 unsigned SizeInBytes = CGF.getContext().getTypeSize(Ty) / 8;
3773 unsigned CplxBaseSize = 0;
3775 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
3776 BaseTy = CTy->getElementType();
3777 CplxBaseSize = CGF.getContext().getTypeSize(BaseTy) / 8;
3778 if (CplxBaseSize < 8)
3782 unsigned Offset = llvm::RoundUpToAlignment(SizeInBytes, 8);
3783 llvm::Value *NextAddr =
3784 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int64Ty, Offset),
3786 Builder.CreateStore(NextAddr, VAListAddrAsBPP);
3788 // If we have a complex type and the base type is smaller than 8 bytes,
3789 // the ABI calls for the real and imaginary parts to be right-adjusted
3790 // in separate doublewords. However, Clang expects us to produce a
3791 // pointer to a structure with the two parts packed tightly. So generate
3792 // loads of the real and imaginary parts relative to the va_list pointer,
3793 // and store them to a temporary structure.
3794 if (CplxBaseSize && CplxBaseSize < 8) {
3795 llvm::Value *RealAddr = Builder.CreatePtrToInt(Addr, CGF.Int64Ty);
3796 llvm::Value *ImagAddr = RealAddr;
3797 if (CGF.CGM.getDataLayout().isBigEndian()) {
3798 RealAddr = Builder.CreateAdd(RealAddr, Builder.getInt64(8 - CplxBaseSize));
3799 ImagAddr = Builder.CreateAdd(ImagAddr, Builder.getInt64(16 - CplxBaseSize));
3801 ImagAddr = Builder.CreateAdd(ImagAddr, Builder.getInt64(8));
3803 llvm::Type *PBaseTy = llvm::PointerType::getUnqual(CGF.ConvertType(BaseTy));
3804 RealAddr = Builder.CreateIntToPtr(RealAddr, PBaseTy);
3805 ImagAddr = Builder.CreateIntToPtr(ImagAddr, PBaseTy);
3806 llvm::Value *Real = Builder.CreateLoad(RealAddr, false, ".vareal");
3807 llvm::Value *Imag = Builder.CreateLoad(ImagAddr, false, ".vaimag");
3808 llvm::AllocaInst *Ptr =
3809 CGF.CreateTempAlloca(CGT.ConvertTypeForMem(Ty), "vacplx");
3810 llvm::Value *RealPtr =
3811 Builder.CreateStructGEP(Ptr->getAllocatedType(), Ptr, 0, ".real");
3812 llvm::Value *ImagPtr =
3813 Builder.CreateStructGEP(Ptr->getAllocatedType(), Ptr, 1, ".imag");
3814 Builder.CreateStore(Real, RealPtr, false);
3815 Builder.CreateStore(Imag, ImagPtr, false);
3819 // If the argument is smaller than 8 bytes, it is right-adjusted in
3820 // its doubleword slot. Adjust the pointer to pick it up from the
3822 if (SizeInBytes < 8 && CGF.CGM.getDataLayout().isBigEndian()) {
3823 llvm::Value *AddrAsInt = Builder.CreatePtrToInt(Addr, CGF.Int64Ty);
3824 AddrAsInt = Builder.CreateAdd(AddrAsInt, Builder.getInt64(8 - SizeInBytes));
3825 Addr = Builder.CreateIntToPtr(AddrAsInt, BP);
3828 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
3829 return Builder.CreateBitCast(Addr, PTy);
3833 PPC64_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3834 llvm::Value *Address) {
3835 // This is calculated from the LLVM and GCC tables and verified
3836 // against gcc output. AFAIK all ABIs use the same encoding.
3838 CodeGen::CGBuilderTy &Builder = CGF.Builder;
3840 llvm::IntegerType *i8 = CGF.Int8Ty;
3841 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
3842 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
3843 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
3845 // 0-31: r0-31, the 8-byte general-purpose registers
3846 AssignToArrayRange(Builder, Address, Eight8, 0, 31);
3848 // 32-63: fp0-31, the 8-byte floating-point registers
3849 AssignToArrayRange(Builder, Address, Eight8, 32, 63);
3851 // 64-76 are various 4-byte special-purpose registers:
3858 AssignToArrayRange(Builder, Address, Four8, 64, 76);
3860 // 77-108: v0-31, the 16-byte vector registers
3861 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
3868 AssignToArrayRange(Builder, Address, Four8, 109, 113);
3874 PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
3875 CodeGen::CodeGenFunction &CGF,
3876 llvm::Value *Address) const {
3878 return PPC64_initDwarfEHRegSizeTable(CGF, Address);
3882 PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3883 llvm::Value *Address) const {
3885 return PPC64_initDwarfEHRegSizeTable(CGF, Address);
3888 //===----------------------------------------------------------------------===//
3889 // AArch64 ABI Implementation
3890 //===----------------------------------------------------------------------===//
3894 class AArch64ABIInfo : public ABIInfo {
3905 AArch64ABIInfo(CodeGenTypes &CGT, ABIKind Kind) : ABIInfo(CGT), Kind(Kind) {}
3908 ABIKind getABIKind() const { return Kind; }
3909 bool isDarwinPCS() const { return Kind == DarwinPCS; }
3911 ABIArgInfo classifyReturnType(QualType RetTy) const;
3912 ABIArgInfo classifyArgumentType(QualType RetTy) const;
3913 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
3914 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
3915 uint64_t Members) const override;
3917 bool isIllegalVectorType(QualType Ty) const;
3919 void computeInfo(CGFunctionInfo &FI) const override {
3920 if (!getCXXABI().classifyReturnType(FI))
3921 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
3923 for (auto &it : FI.arguments())
3924 it.info = classifyArgumentType(it.type);
3927 llvm::Value *EmitDarwinVAArg(llvm::Value *VAListAddr, QualType Ty,
3928 CodeGenFunction &CGF) const;
3930 llvm::Value *EmitAAPCSVAArg(llvm::Value *VAListAddr, QualType Ty,
3931 CodeGenFunction &CGF) const;
3933 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
3934 CodeGenFunction &CGF) const override {
3935 return isDarwinPCS() ? EmitDarwinVAArg(VAListAddr, Ty, CGF)
3936 : EmitAAPCSVAArg(VAListAddr, Ty, CGF);
3940 class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
3942 AArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind Kind)
3943 : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
3945 StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
3946 return "mov\tfp, fp\t\t; marker for objc_retainAutoreleaseReturnValue";
3949 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
3953 bool doesReturnSlotInterfereWithArgs() const override { return false; }
3957 ABIArgInfo AArch64ABIInfo::classifyArgumentType(QualType Ty) const {
3958 Ty = useFirstFieldIfTransparentUnion(Ty);
3960 // Handle illegal vector types here.
3961 if (isIllegalVectorType(Ty)) {
3962 uint64_t Size = getContext().getTypeSize(Ty);
3964 llvm::Type *ResType = llvm::Type::getInt32Ty(getVMContext());
3965 return ABIArgInfo::getDirect(ResType);
3968 llvm::Type *ResType =
3969 llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 2);
3970 return ABIArgInfo::getDirect(ResType);
3973 llvm::Type *ResType =
3974 llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 4);
3975 return ABIArgInfo::getDirect(ResType);
3977 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
3980 if (!isAggregateTypeForABI(Ty)) {
3981 // Treat an enum type as its underlying type.
3982 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3983 Ty = EnumTy->getDecl()->getIntegerType();
3985 return (Ty->isPromotableIntegerType() && isDarwinPCS()
3986 ? ABIArgInfo::getExtend()
3987 : ABIArgInfo::getDirect());
3990 // Structures with either a non-trivial destructor or a non-trivial
3991 // copy constructor are always indirect.
3992 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
3993 return ABIArgInfo::getIndirect(0, /*ByVal=*/RAA ==
3994 CGCXXABI::RAA_DirectInMemory);
3997 // Empty records are always ignored on Darwin, but actually passed in C++ mode
3998 // elsewhere for GNU compatibility.
3999 if (isEmptyRecord(getContext(), Ty, true)) {
4000 if (!getContext().getLangOpts().CPlusPlus || isDarwinPCS())
4001 return ABIArgInfo::getIgnore();
4003 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
4006 // Homogeneous Floating-point Aggregates (HFAs) need to be expanded.
4007 const Type *Base = nullptr;
4008 uint64_t Members = 0;
4009 if (isHomogeneousAggregate(Ty, Base, Members)) {
4010 return ABIArgInfo::getDirect(
4011 llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members));
4014 // Aggregates <= 16 bytes are passed directly in registers or on the stack.
4015 uint64_t Size = getContext().getTypeSize(Ty);
4017 unsigned Alignment = getContext().getTypeAlign(Ty);
4018 Size = 64 * ((Size + 63) / 64); // round up to multiple of 8 bytes
4020 // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
4021 // For aggregates with 16-byte alignment, we use i128.
4022 if (Alignment < 128 && Size == 128) {
4023 llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
4024 return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
4026 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
4029 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
4032 ABIArgInfo AArch64ABIInfo::classifyReturnType(QualType RetTy) const {
4033 if (RetTy->isVoidType())
4034 return ABIArgInfo::getIgnore();
4036 // Large vector types should be returned via memory.
4037 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128)
4038 return ABIArgInfo::getIndirect(0);
4040 if (!isAggregateTypeForABI(RetTy)) {
4041 // Treat an enum type as its underlying type.
4042 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
4043 RetTy = EnumTy->getDecl()->getIntegerType();
4045 return (RetTy->isPromotableIntegerType() && isDarwinPCS()
4046 ? ABIArgInfo::getExtend()
4047 : ABIArgInfo::getDirect());
4050 if (isEmptyRecord(getContext(), RetTy, true))
4051 return ABIArgInfo::getIgnore();
4053 const Type *Base = nullptr;
4054 uint64_t Members = 0;
4055 if (isHomogeneousAggregate(RetTy, Base, Members))
4056 // Homogeneous Floating-point Aggregates (HFAs) are returned directly.
4057 return ABIArgInfo::getDirect();
4059 // Aggregates <= 16 bytes are returned directly in registers or on the stack.
4060 uint64_t Size = getContext().getTypeSize(RetTy);
4062 unsigned Alignment = getContext().getTypeAlign(RetTy);
4063 Size = 64 * ((Size + 63) / 64); // round up to multiple of 8 bytes
4065 // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
4066 // For aggregates with 16-byte alignment, we use i128.
4067 if (Alignment < 128 && Size == 128) {
4068 llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
4069 return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
4071 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
4074 return ABIArgInfo::getIndirect(0);
4077 /// isIllegalVectorType - check whether the vector type is legal for AArch64.
4078 bool AArch64ABIInfo::isIllegalVectorType(QualType Ty) const {
4079 if (const VectorType *VT = Ty->getAs<VectorType>()) {
4080 // Check whether VT is legal.
4081 unsigned NumElements = VT->getNumElements();
4082 uint64_t Size = getContext().getTypeSize(VT);
4083 // NumElements should be power of 2 between 1 and 16.
4084 if ((NumElements & (NumElements - 1)) != 0 || NumElements > 16)
4086 return Size != 64 && (Size != 128 || NumElements == 1);
4091 bool AArch64ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
4092 // Homogeneous aggregates for AAPCS64 must have base types of a floating
4093 // point type or a short-vector type. This is the same as the 32-bit ABI,
4094 // but with the difference that any floating-point type is allowed,
4095 // including __fp16.
4096 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4097 if (BT->isFloatingPoint())
4099 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
4100 unsigned VecSize = getContext().getTypeSize(VT);
4101 if (VecSize == 64 || VecSize == 128)
4107 bool AArch64ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
4108 uint64_t Members) const {
4109 return Members <= 4;
4112 llvm::Value *AArch64ABIInfo::EmitAAPCSVAArg(llvm::Value *VAListAddr,
4114 CodeGenFunction &CGF) const {
4115 ABIArgInfo AI = classifyArgumentType(Ty);
4116 bool IsIndirect = AI.isIndirect();
4118 llvm::Type *BaseTy = CGF.ConvertType(Ty);
4120 BaseTy = llvm::PointerType::getUnqual(BaseTy);
4121 else if (AI.getCoerceToType())
4122 BaseTy = AI.getCoerceToType();
4124 unsigned NumRegs = 1;
4125 if (llvm::ArrayType *ArrTy = dyn_cast<llvm::ArrayType>(BaseTy)) {
4126 BaseTy = ArrTy->getElementType();
4127 NumRegs = ArrTy->getNumElements();
4129 bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy();
4131 // The AArch64 va_list type and handling is specified in the Procedure Call
4132 // Standard, section B.4:
4142 llvm::BasicBlock *MaybeRegBlock = CGF.createBasicBlock("vaarg.maybe_reg");
4143 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
4144 llvm::BasicBlock *OnStackBlock = CGF.createBasicBlock("vaarg.on_stack");
4145 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
4146 auto &Ctx = CGF.getContext();
4148 llvm::Value *reg_offs_p = nullptr, *reg_offs = nullptr;
4150 int RegSize = IsIndirect ? 8 : getContext().getTypeSize(Ty) / 8;
4152 // 3 is the field number of __gr_offs
4154 CGF.Builder.CreateStructGEP(nullptr, VAListAddr, 3, "gr_offs_p");
4155 reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "gr_offs");
4156 reg_top_index = 1; // field number for __gr_top
4157 RegSize = llvm::RoundUpToAlignment(RegSize, 8);
4159 // 4 is the field number of __vr_offs.
4161 CGF.Builder.CreateStructGEP(nullptr, VAListAddr, 4, "vr_offs_p");
4162 reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "vr_offs");
4163 reg_top_index = 2; // field number for __vr_top
4164 RegSize = 16 * NumRegs;
4167 //=======================================
4168 // Find out where argument was passed
4169 //=======================================
4171 // If reg_offs >= 0 we're already using the stack for this type of
4172 // argument. We don't want to keep updating reg_offs (in case it overflows,
4173 // though anyone passing 2GB of arguments, each at most 16 bytes, deserves
4174 // whatever they get).
4175 llvm::Value *UsingStack = nullptr;
4176 UsingStack = CGF.Builder.CreateICmpSGE(
4177 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, 0));
4179 CGF.Builder.CreateCondBr(UsingStack, OnStackBlock, MaybeRegBlock);
4181 // Otherwise, at least some kind of argument could go in these registers, the
4182 // question is whether this particular type is too big.
4183 CGF.EmitBlock(MaybeRegBlock);
4185 // Integer arguments may need to correct register alignment (for example a
4186 // "struct { __int128 a; };" gets passed in x_2N, x_{2N+1}). In this case we
4187 // align __gr_offs to calculate the potential address.
4188 if (!IsFPR && !IsIndirect && Ctx.getTypeAlign(Ty) > 64) {
4189 int Align = Ctx.getTypeAlign(Ty) / 8;
4191 reg_offs = CGF.Builder.CreateAdd(
4192 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, Align - 1),
4194 reg_offs = CGF.Builder.CreateAnd(
4195 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, -Align),
4199 // Update the gr_offs/vr_offs pointer for next call to va_arg on this va_list.
4200 llvm::Value *NewOffset = nullptr;
4201 NewOffset = CGF.Builder.CreateAdd(
4202 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs");
4203 CGF.Builder.CreateStore(NewOffset, reg_offs_p);
4205 // Now we're in a position to decide whether this argument really was in
4206 // registers or not.
4207 llvm::Value *InRegs = nullptr;
4208 InRegs = CGF.Builder.CreateICmpSLE(
4209 NewOffset, llvm::ConstantInt::get(CGF.Int32Ty, 0), "inreg");
4211 CGF.Builder.CreateCondBr(InRegs, InRegBlock, OnStackBlock);
4213 //=======================================
4214 // Argument was in registers
4215 //=======================================
4217 // Now we emit the code for if the argument was originally passed in
4218 // registers. First start the appropriate block:
4219 CGF.EmitBlock(InRegBlock);
4221 llvm::Value *reg_top_p = nullptr, *reg_top = nullptr;
4222 reg_top_p = CGF.Builder.CreateStructGEP(nullptr, VAListAddr, reg_top_index,
4224 reg_top = CGF.Builder.CreateLoad(reg_top_p, "reg_top");
4225 llvm::Value *BaseAddr = CGF.Builder.CreateGEP(reg_top, reg_offs);
4226 llvm::Value *RegAddr = nullptr;
4227 llvm::Type *MemTy = llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty));
4230 // If it's been passed indirectly (actually a struct), whatever we find from
4231 // stored registers or on the stack will actually be a struct **.
4232 MemTy = llvm::PointerType::getUnqual(MemTy);
4235 const Type *Base = nullptr;
4236 uint64_t NumMembers = 0;
4237 bool IsHFA = isHomogeneousAggregate(Ty, Base, NumMembers);
4238 if (IsHFA && NumMembers > 1) {
4239 // Homogeneous aggregates passed in registers will have their elements split
4240 // and stored 16-bytes apart regardless of size (they're notionally in qN,
4241 // qN+1, ...). We reload and store into a temporary local variable
4243 assert(!IsIndirect && "Homogeneous aggregates should be passed directly");
4244 llvm::Type *BaseTy = CGF.ConvertType(QualType(Base, 0));
4245 llvm::Type *HFATy = llvm::ArrayType::get(BaseTy, NumMembers);
4246 llvm::AllocaInst *Tmp = CGF.CreateTempAlloca(HFATy);
4249 if (CGF.CGM.getDataLayout().isBigEndian() && Ctx.getTypeSize(Base) < 128)
4250 Offset = 16 - Ctx.getTypeSize(Base) / 8;
4251 for (unsigned i = 0; i < NumMembers; ++i) {
4252 llvm::Value *BaseOffset =
4253 llvm::ConstantInt::get(CGF.Int32Ty, 16 * i + Offset);
4254 llvm::Value *LoadAddr = CGF.Builder.CreateGEP(BaseAddr, BaseOffset);
4255 LoadAddr = CGF.Builder.CreateBitCast(
4256 LoadAddr, llvm::PointerType::getUnqual(BaseTy));
4257 llvm::Value *StoreAddr =
4258 CGF.Builder.CreateStructGEP(Tmp->getAllocatedType(), Tmp, i);
4260 llvm::Value *Elem = CGF.Builder.CreateLoad(LoadAddr);
4261 CGF.Builder.CreateStore(Elem, StoreAddr);
4264 RegAddr = CGF.Builder.CreateBitCast(Tmp, MemTy);
4266 // Otherwise the object is contiguous in memory
4267 unsigned BeAlign = reg_top_index == 2 ? 16 : 8;
4268 if (CGF.CGM.getDataLayout().isBigEndian() &&
4269 (IsHFA || !isAggregateTypeForABI(Ty)) &&
4270 Ctx.getTypeSize(Ty) < (BeAlign * 8)) {
4271 int Offset = BeAlign - Ctx.getTypeSize(Ty) / 8;
4272 BaseAddr = CGF.Builder.CreatePtrToInt(BaseAddr, CGF.Int64Ty);
4274 BaseAddr = CGF.Builder.CreateAdd(
4275 BaseAddr, llvm::ConstantInt::get(CGF.Int64Ty, Offset), "align_be");
4277 BaseAddr = CGF.Builder.CreateIntToPtr(BaseAddr, CGF.Int8PtrTy);
4280 RegAddr = CGF.Builder.CreateBitCast(BaseAddr, MemTy);
4283 CGF.EmitBranch(ContBlock);
4285 //=======================================
4286 // Argument was on the stack
4287 //=======================================
4288 CGF.EmitBlock(OnStackBlock);
4290 llvm::Value *stack_p = nullptr, *OnStackAddr = nullptr;
4291 stack_p = CGF.Builder.CreateStructGEP(nullptr, VAListAddr, 0, "stack_p");
4292 OnStackAddr = CGF.Builder.CreateLoad(stack_p, "stack");
4294 // Again, stack arguments may need realigmnent. In this case both integer and
4295 // floating-point ones might be affected.
4296 if (!IsIndirect && Ctx.getTypeAlign(Ty) > 64) {
4297 int Align = Ctx.getTypeAlign(Ty) / 8;
4299 OnStackAddr = CGF.Builder.CreatePtrToInt(OnStackAddr, CGF.Int64Ty);
4301 OnStackAddr = CGF.Builder.CreateAdd(
4302 OnStackAddr, llvm::ConstantInt::get(CGF.Int64Ty, Align - 1),
4304 OnStackAddr = CGF.Builder.CreateAnd(
4305 OnStackAddr, llvm::ConstantInt::get(CGF.Int64Ty, -Align),
4308 OnStackAddr = CGF.Builder.CreateIntToPtr(OnStackAddr, CGF.Int8PtrTy);
4315 StackSize = Ctx.getTypeSize(Ty) / 8;
4317 // All stack slots are 8 bytes
4318 StackSize = llvm::RoundUpToAlignment(StackSize, 8);
4320 llvm::Value *StackSizeC = llvm::ConstantInt::get(CGF.Int32Ty, StackSize);
4321 llvm::Value *NewStack =
4322 CGF.Builder.CreateGEP(OnStackAddr, StackSizeC, "new_stack");
4324 // Write the new value of __stack for the next call to va_arg
4325 CGF.Builder.CreateStore(NewStack, stack_p);
4327 if (CGF.CGM.getDataLayout().isBigEndian() && !isAggregateTypeForABI(Ty) &&
4328 Ctx.getTypeSize(Ty) < 64) {
4329 int Offset = 8 - Ctx.getTypeSize(Ty) / 8;
4330 OnStackAddr = CGF.Builder.CreatePtrToInt(OnStackAddr, CGF.Int64Ty);
4332 OnStackAddr = CGF.Builder.CreateAdd(
4333 OnStackAddr, llvm::ConstantInt::get(CGF.Int64Ty, Offset), "align_be");
4335 OnStackAddr = CGF.Builder.CreateIntToPtr(OnStackAddr, CGF.Int8PtrTy);
4338 OnStackAddr = CGF.Builder.CreateBitCast(OnStackAddr, MemTy);
4340 CGF.EmitBranch(ContBlock);
4342 //=======================================
4344 //=======================================
4345 CGF.EmitBlock(ContBlock);
4347 llvm::PHINode *ResAddr = CGF.Builder.CreatePHI(MemTy, 2, "vaarg.addr");
4348 ResAddr->addIncoming(RegAddr, InRegBlock);
4349 ResAddr->addIncoming(OnStackAddr, OnStackBlock);
4352 return CGF.Builder.CreateLoad(ResAddr, "vaarg.addr");
4357 llvm::Value *AArch64ABIInfo::EmitDarwinVAArg(llvm::Value *VAListAddr, QualType Ty,
4358 CodeGenFunction &CGF) const {
4359 // We do not support va_arg for aggregates or illegal vector types.
4360 // Lower VAArg here for these cases and use the LLVM va_arg instruction for
4362 if (!isAggregateTypeForABI(Ty) && !isIllegalVectorType(Ty))
4365 uint64_t Size = CGF.getContext().getTypeSize(Ty) / 8;
4366 uint64_t Align = CGF.getContext().getTypeAlign(Ty) / 8;
4368 const Type *Base = nullptr;
4369 uint64_t Members = 0;
4370 bool isHA = isHomogeneousAggregate(Ty, Base, Members);
4372 bool isIndirect = false;
4373 // Arguments bigger than 16 bytes which aren't homogeneous aggregates should
4374 // be passed indirectly.
4375 if (Size > 16 && !isHA) {
4381 llvm::Type *BP = llvm::Type::getInt8PtrTy(CGF.getLLVMContext());
4382 llvm::Type *BPP = llvm::PointerType::getUnqual(BP);
4384 CGBuilderTy &Builder = CGF.Builder;
4385 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap");
4386 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur");
4388 if (isEmptyRecord(getContext(), Ty, true)) {
4389 // These are ignored for parameter passing purposes.
4390 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
4391 return Builder.CreateBitCast(Addr, PTy);
4394 const uint64_t MinABIAlign = 8;
4395 if (Align > MinABIAlign) {
4396 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, Align - 1);
4397 Addr = Builder.CreateGEP(Addr, Offset);
4398 llvm::Value *AsInt = Builder.CreatePtrToInt(Addr, CGF.Int64Ty);
4399 llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int64Ty, ~(Align - 1));
4400 llvm::Value *Aligned = Builder.CreateAnd(AsInt, Mask);
4401 Addr = Builder.CreateIntToPtr(Aligned, BP, "ap.align");
4404 uint64_t Offset = llvm::RoundUpToAlignment(Size, MinABIAlign);
4405 llvm::Value *NextAddr = Builder.CreateGEP(
4406 Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset), "ap.next");
4407 Builder.CreateStore(NextAddr, VAListAddrAsBPP);
4410 Addr = Builder.CreateLoad(Builder.CreateBitCast(Addr, BPP));
4411 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
4412 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy);
4417 //===----------------------------------------------------------------------===//
4418 // ARM ABI Implementation
4419 //===----------------------------------------------------------------------===//
4423 class ARMABIInfo : public ABIInfo {
4435 ARMABIInfo(CodeGenTypes &CGT, ABIKind _Kind) : ABIInfo(CGT), Kind(_Kind) {
4439 bool isEABI() const {
4440 switch (getTarget().getTriple().getEnvironment()) {
4441 case llvm::Triple::Android:
4442 case llvm::Triple::EABI:
4443 case llvm::Triple::EABIHF:
4444 case llvm::Triple::GNUEABI:
4445 case llvm::Triple::GNUEABIHF:
4452 bool isEABIHF() const {
4453 switch (getTarget().getTriple().getEnvironment()) {
4454 case llvm::Triple::EABIHF:
4455 case llvm::Triple::GNUEABIHF:
4462 ABIKind getABIKind() const { return Kind; }
4465 ABIArgInfo classifyReturnType(QualType RetTy, bool isVariadic) const;
4466 ABIArgInfo classifyArgumentType(QualType RetTy, bool isVariadic) const;
4467 bool isIllegalVectorType(QualType Ty) const;
4469 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4470 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4471 uint64_t Members) const override;
4473 void computeInfo(CGFunctionInfo &FI) const override;
4475 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
4476 CodeGenFunction &CGF) const override;
4478 llvm::CallingConv::ID getLLVMDefaultCC() const;
4479 llvm::CallingConv::ID getABIDefaultCC() const;
4483 class ARMTargetCodeGenInfo : public TargetCodeGenInfo {
4485 ARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
4486 :TargetCodeGenInfo(new ARMABIInfo(CGT, K)) {}
4488 const ARMABIInfo &getABIInfo() const {
4489 return static_cast<const ARMABIInfo&>(TargetCodeGenInfo::getABIInfo());
4492 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4496 StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
4497 return "mov\tr7, r7\t\t@ marker for objc_retainAutoreleaseReturnValue";
4500 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4501 llvm::Value *Address) const override {
4502 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
4504 // 0-15 are the 16 integer registers.
4505 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 15);
4509 unsigned getSizeOfUnwindException() const override {
4510 if (getABIInfo().isEABI()) return 88;
4511 return TargetCodeGenInfo::getSizeOfUnwindException();
4514 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
4515 CodeGen::CodeGenModule &CGM) const override {
4516 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D);
4520 const ARMInterruptAttr *Attr = FD->getAttr<ARMInterruptAttr>();
4525 switch (Attr->getInterrupt()) {
4526 case ARMInterruptAttr::Generic: Kind = ""; break;
4527 case ARMInterruptAttr::IRQ: Kind = "IRQ"; break;
4528 case ARMInterruptAttr::FIQ: Kind = "FIQ"; break;
4529 case ARMInterruptAttr::SWI: Kind = "SWI"; break;
4530 case ARMInterruptAttr::ABORT: Kind = "ABORT"; break;
4531 case ARMInterruptAttr::UNDEF: Kind = "UNDEF"; break;
4534 llvm::Function *Fn = cast<llvm::Function>(GV);
4536 Fn->addFnAttr("interrupt", Kind);
4538 if (cast<ARMABIInfo>(getABIInfo()).getABIKind() == ARMABIInfo::APCS)
4541 // AAPCS guarantees that sp will be 8-byte aligned on any public interface,
4542 // however this is not necessarily true on taking any interrupt. Instruct
4543 // the backend to perform a realignment as part of the function prologue.
4544 llvm::AttrBuilder B;
4545 B.addStackAlignmentAttr(8);
4546 Fn->addAttributes(llvm::AttributeSet::FunctionIndex,
4547 llvm::AttributeSet::get(CGM.getLLVMContext(),
4548 llvm::AttributeSet::FunctionIndex,
4553 class WindowsARMTargetCodeGenInfo : public ARMTargetCodeGenInfo {
4554 void addStackProbeSizeTargetAttribute(const Decl *D, llvm::GlobalValue *GV,
4555 CodeGen::CodeGenModule &CGM) const;
4558 WindowsARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
4559 : ARMTargetCodeGenInfo(CGT, K) {}
4561 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
4562 CodeGen::CodeGenModule &CGM) const override;
4565 void WindowsARMTargetCodeGenInfo::addStackProbeSizeTargetAttribute(
4566 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
4567 if (!isa<FunctionDecl>(D))
4569 if (CGM.getCodeGenOpts().StackProbeSize == 4096)
4572 llvm::Function *F = cast<llvm::Function>(GV);
4573 F->addFnAttr("stack-probe-size",
4574 llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
4577 void WindowsARMTargetCodeGenInfo::SetTargetAttributes(
4578 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
4579 ARMTargetCodeGenInfo::SetTargetAttributes(D, GV, CGM);
4580 addStackProbeSizeTargetAttribute(D, GV, CGM);
4584 void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const {
4585 if (!getCXXABI().classifyReturnType(FI))
4586 FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), FI.isVariadic());
4588 for (auto &I : FI.arguments())
4589 I.info = classifyArgumentType(I.type, FI.isVariadic());
4591 // Always honor user-specified calling convention.
4592 if (FI.getCallingConvention() != llvm::CallingConv::C)
4595 llvm::CallingConv::ID cc = getRuntimeCC();
4596 if (cc != llvm::CallingConv::C)
4597 FI.setEffectiveCallingConvention(cc);
4600 /// Return the default calling convention that LLVM will use.
4601 llvm::CallingConv::ID ARMABIInfo::getLLVMDefaultCC() const {
4602 // The default calling convention that LLVM will infer.
4604 return llvm::CallingConv::ARM_AAPCS_VFP;
4606 return llvm::CallingConv::ARM_AAPCS;
4608 return llvm::CallingConv::ARM_APCS;
4611 /// Return the calling convention that our ABI would like us to use
4612 /// as the C calling convention.
4613 llvm::CallingConv::ID ARMABIInfo::getABIDefaultCC() const {
4614 switch (getABIKind()) {
4615 case APCS: return llvm::CallingConv::ARM_APCS;
4616 case AAPCS: return llvm::CallingConv::ARM_AAPCS;
4617 case AAPCS_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
4619 llvm_unreachable("bad ABI kind");
4622 void ARMABIInfo::setCCs() {
4623 assert(getRuntimeCC() == llvm::CallingConv::C);
4625 // Don't muddy up the IR with a ton of explicit annotations if
4626 // they'd just match what LLVM will infer from the triple.
4627 llvm::CallingConv::ID abiCC = getABIDefaultCC();
4628 if (abiCC != getLLVMDefaultCC())
4631 BuiltinCC = (getABIKind() == APCS ?
4632 llvm::CallingConv::ARM_APCS : llvm::CallingConv::ARM_AAPCS);
4635 ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty,
4636 bool isVariadic) const {
4637 // 6.1.2.1 The following argument types are VFP CPRCs:
4638 // A single-precision floating-point type (including promoted
4639 // half-precision types); A double-precision floating-point type;
4640 // A 64-bit or 128-bit containerized vector type; Homogeneous Aggregate
4641 // with a Base Type of a single- or double-precision floating-point type,
4642 // 64-bit containerized vectors or 128-bit containerized vectors with one
4643 // to four Elements.
4644 bool IsEffectivelyAAPCS_VFP = getABIKind() == AAPCS_VFP && !isVariadic;
4646 Ty = useFirstFieldIfTransparentUnion(Ty);
4648 // Handle illegal vector types here.
4649 if (isIllegalVectorType(Ty)) {
4650 uint64_t Size = getContext().getTypeSize(Ty);
4652 llvm::Type *ResType =
4653 llvm::Type::getInt32Ty(getVMContext());
4654 return ABIArgInfo::getDirect(ResType);
4657 llvm::Type *ResType = llvm::VectorType::get(
4658 llvm::Type::getInt32Ty(getVMContext()), 2);
4659 return ABIArgInfo::getDirect(ResType);
4662 llvm::Type *ResType = llvm::VectorType::get(
4663 llvm::Type::getInt32Ty(getVMContext()), 4);
4664 return ABIArgInfo::getDirect(ResType);
4666 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
4669 if (!isAggregateTypeForABI(Ty)) {
4670 // Treat an enum type as its underlying type.
4671 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
4672 Ty = EnumTy->getDecl()->getIntegerType();
4675 return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend()
4676 : ABIArgInfo::getDirect());
4679 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
4680 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
4683 // Ignore empty records.
4684 if (isEmptyRecord(getContext(), Ty, true))
4685 return ABIArgInfo::getIgnore();
4687 if (IsEffectivelyAAPCS_VFP) {
4688 // Homogeneous Aggregates need to be expanded when we can fit the aggregate
4689 // into VFP registers.
4690 const Type *Base = nullptr;
4691 uint64_t Members = 0;
4692 if (isHomogeneousAggregate(Ty, Base, Members)) {
4693 assert(Base && "Base class should be set for homogeneous aggregate");
4694 // Base can be a floating-point or a vector.
4695 return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
4699 // Support byval for ARM.
4700 // The ABI alignment for APCS is 4-byte and for AAPCS at least 4-byte and at
4701 // most 8-byte. We realign the indirect argument if type alignment is bigger
4702 // than ABI alignment.
4703 uint64_t ABIAlign = 4;
4704 uint64_t TyAlign = getContext().getTypeAlign(Ty) / 8;
4705 if (getABIKind() == ARMABIInfo::AAPCS_VFP ||
4706 getABIKind() == ARMABIInfo::AAPCS)
4707 ABIAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8);
4709 if (getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(64)) {
4710 return ABIArgInfo::getIndirect(ABIAlign, /*ByVal=*/true,
4711 /*Realign=*/TyAlign > ABIAlign);
4714 // Otherwise, pass by coercing to a structure of the appropriate size.
4717 // FIXME: Try to match the types of the arguments more accurately where
4719 if (getContext().getTypeAlign(Ty) <= 32) {
4720 ElemTy = llvm::Type::getInt32Ty(getVMContext());
4721 SizeRegs = (getContext().getTypeSize(Ty) + 31) / 32;
4723 ElemTy = llvm::Type::getInt64Ty(getVMContext());
4724 SizeRegs = (getContext().getTypeSize(Ty) + 63) / 64;
4727 return ABIArgInfo::getDirect(llvm::ArrayType::get(ElemTy, SizeRegs));
4730 static bool isIntegerLikeType(QualType Ty, ASTContext &Context,
4731 llvm::LLVMContext &VMContext) {
4732 // APCS, C Language Calling Conventions, Non-Simple Return Values: A structure
4733 // is called integer-like if its size is less than or equal to one word, and
4734 // the offset of each of its addressable sub-fields is zero.
4736 uint64_t Size = Context.getTypeSize(Ty);
4738 // Check that the type fits in a word.
4742 // FIXME: Handle vector types!
4743 if (Ty->isVectorType())
4746 // Float types are never treated as "integer like".
4747 if (Ty->isRealFloatingType())
4750 // If this is a builtin or pointer type then it is ok.
4751 if (Ty->getAs<BuiltinType>() || Ty->isPointerType())
4754 // Small complex integer types are "integer like".
4755 if (const ComplexType *CT = Ty->getAs<ComplexType>())
4756 return isIntegerLikeType(CT->getElementType(), Context, VMContext);
4758 // Single element and zero sized arrays should be allowed, by the definition
4759 // above, but they are not.
4761 // Otherwise, it must be a record type.
4762 const RecordType *RT = Ty->getAs<RecordType>();
4763 if (!RT) return false;
4765 // Ignore records with flexible arrays.
4766 const RecordDecl *RD = RT->getDecl();
4767 if (RD->hasFlexibleArrayMember())
4770 // Check that all sub-fields are at offset 0, and are themselves "integer
4772 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
4774 bool HadField = false;
4776 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
4777 i != e; ++i, ++idx) {
4778 const FieldDecl *FD = *i;
4780 // Bit-fields are not addressable, we only need to verify they are "integer
4781 // like". We still have to disallow a subsequent non-bitfield, for example:
4782 // struct { int : 0; int x }
4783 // is non-integer like according to gcc.
4784 if (FD->isBitField()) {
4788 if (!isIntegerLikeType(FD->getType(), Context, VMContext))
4794 // Check if this field is at offset 0.
4795 if (Layout.getFieldOffset(idx) != 0)
4798 if (!isIntegerLikeType(FD->getType(), Context, VMContext))
4801 // Only allow at most one field in a structure. This doesn't match the
4802 // wording above, but follows gcc in situations with a field following an
4804 if (!RD->isUnion()) {
4815 ABIArgInfo ARMABIInfo::classifyReturnType(QualType RetTy,
4816 bool isVariadic) const {
4817 bool IsEffectivelyAAPCS_VFP = getABIKind() == AAPCS_VFP && !isVariadic;
4819 if (RetTy->isVoidType())
4820 return ABIArgInfo::getIgnore();
4822 // Large vector types should be returned via memory.
4823 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128) {
4824 return ABIArgInfo::getIndirect(0);
4827 if (!isAggregateTypeForABI(RetTy)) {
4828 // Treat an enum type as its underlying type.
4829 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
4830 RetTy = EnumTy->getDecl()->getIntegerType();
4832 return RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend()
4833 : ABIArgInfo::getDirect();
4836 // Are we following APCS?
4837 if (getABIKind() == APCS) {
4838 if (isEmptyRecord(getContext(), RetTy, false))
4839 return ABIArgInfo::getIgnore();
4841 // Complex types are all returned as packed integers.
4843 // FIXME: Consider using 2 x vector types if the back end handles them
4845 if (RetTy->isAnyComplexType())
4846 return ABIArgInfo::getDirect(llvm::IntegerType::get(
4847 getVMContext(), getContext().getTypeSize(RetTy)));
4849 // Integer like structures are returned in r0.
4850 if (isIntegerLikeType(RetTy, getContext(), getVMContext())) {
4851 // Return in the smallest viable integer type.
4852 uint64_t Size = getContext().getTypeSize(RetTy);
4854 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
4856 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
4857 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
4860 // Otherwise return in memory.
4861 return ABIArgInfo::getIndirect(0);
4864 // Otherwise this is an AAPCS variant.
4866 if (isEmptyRecord(getContext(), RetTy, true))
4867 return ABIArgInfo::getIgnore();
4869 // Check for homogeneous aggregates with AAPCS-VFP.
4870 if (IsEffectivelyAAPCS_VFP) {
4871 const Type *Base = nullptr;
4873 if (isHomogeneousAggregate(RetTy, Base, Members)) {
4874 assert(Base && "Base class should be set for homogeneous aggregate");
4875 // Homogeneous Aggregates are returned directly.
4876 return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
4880 // Aggregates <= 4 bytes are returned in r0; other aggregates
4881 // are returned indirectly.
4882 uint64_t Size = getContext().getTypeSize(RetTy);
4884 if (getDataLayout().isBigEndian())
4885 // Return in 32 bit integer integer type (as if loaded by LDR, AAPCS 5.4)
4886 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
4888 // Return in the smallest viable integer type.
4890 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
4892 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
4893 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
4896 return ABIArgInfo::getIndirect(0);
4899 /// isIllegalVector - check whether Ty is an illegal vector type.
4900 bool ARMABIInfo::isIllegalVectorType(QualType Ty) const {
4901 if (const VectorType *VT = Ty->getAs<VectorType>()) {
4902 // Check whether VT is legal.
4903 unsigned NumElements = VT->getNumElements();
4904 uint64_t Size = getContext().getTypeSize(VT);
4905 // NumElements should be power of 2.
4906 if ((NumElements & (NumElements - 1)) != 0)
4908 // Size should be greater than 32 bits.
4914 bool ARMABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
4915 // Homogeneous aggregates for AAPCS-VFP must have base types of float,
4916 // double, or 64-bit or 128-bit vectors.
4917 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4918 if (BT->getKind() == BuiltinType::Float ||
4919 BT->getKind() == BuiltinType::Double ||
4920 BT->getKind() == BuiltinType::LongDouble)
4922 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
4923 unsigned VecSize = getContext().getTypeSize(VT);
4924 if (VecSize == 64 || VecSize == 128)
4930 bool ARMABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
4931 uint64_t Members) const {
4932 return Members <= 4;
4935 llvm::Value *ARMABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
4936 CodeGenFunction &CGF) const {
4937 llvm::Type *BP = CGF.Int8PtrTy;
4938 llvm::Type *BPP = CGF.Int8PtrPtrTy;
4940 CGBuilderTy &Builder = CGF.Builder;
4941 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap");
4942 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur");
4944 if (isEmptyRecord(getContext(), Ty, true)) {
4945 // These are ignored for parameter passing purposes.
4946 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
4947 return Builder.CreateBitCast(Addr, PTy);
4950 uint64_t Size = CGF.getContext().getTypeSize(Ty) / 8;
4951 uint64_t TyAlign = CGF.getContext().getTypeAlign(Ty) / 8;
4952 bool IsIndirect = false;
4954 // The ABI alignment for 64-bit or 128-bit vectors is 8 for AAPCS and 4 for
4955 // APCS. For AAPCS, the ABI alignment is at least 4-byte and at most 8-byte.
4956 if (getABIKind() == ARMABIInfo::AAPCS_VFP ||
4957 getABIKind() == ARMABIInfo::AAPCS)
4958 TyAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8);
4961 // Use indirect if size of the illegal vector is bigger than 16 bytes.
4962 if (isIllegalVectorType(Ty) && Size > 16) {
4968 // Handle address alignment for ABI alignment > 4 bytes.
4970 assert((TyAlign & (TyAlign - 1)) == 0 &&
4971 "Alignment is not power of 2!");
4972 llvm::Value *AddrAsInt = Builder.CreatePtrToInt(Addr, CGF.Int32Ty);
4973 AddrAsInt = Builder.CreateAdd(AddrAsInt, Builder.getInt32(TyAlign - 1));
4974 AddrAsInt = Builder.CreateAnd(AddrAsInt, Builder.getInt32(~(TyAlign - 1)));
4975 Addr = Builder.CreateIntToPtr(AddrAsInt, BP, "ap.align");
4979 llvm::RoundUpToAlignment(Size, 4);
4980 llvm::Value *NextAddr =
4981 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset),
4983 Builder.CreateStore(NextAddr, VAListAddrAsBPP);
4986 Addr = Builder.CreateLoad(Builder.CreateBitCast(Addr, BPP));
4987 else if (TyAlign < CGF.getContext().getTypeAlign(Ty) / 8) {
4988 // We can't directly cast ap.cur to pointer to a vector type, since ap.cur
4989 // may not be correctly aligned for the vector type. We create an aligned
4990 // temporary space and copy the content over from ap.cur to the temporary
4991 // space. This is necessary if the natural alignment of the type is greater
4992 // than the ABI alignment.
4993 llvm::Type *I8PtrTy = Builder.getInt8PtrTy();
4994 CharUnits CharSize = getContext().getTypeSizeInChars(Ty);
4995 llvm::Value *AlignedTemp = CGF.CreateTempAlloca(CGF.ConvertType(Ty),
4997 llvm::Value *Dst = Builder.CreateBitCast(AlignedTemp, I8PtrTy);
4998 llvm::Value *Src = Builder.CreateBitCast(Addr, I8PtrTy);
4999 Builder.CreateMemCpy(Dst, Src,
5000 llvm::ConstantInt::get(CGF.IntPtrTy, CharSize.getQuantity()),
5002 Addr = AlignedTemp; //The content is in aligned location.
5005 llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
5006 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy);
5011 //===----------------------------------------------------------------------===//
5012 // NVPTX ABI Implementation
5013 //===----------------------------------------------------------------------===//
5017 class NVPTXABIInfo : public ABIInfo {
5019 NVPTXABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
5021 ABIArgInfo classifyReturnType(QualType RetTy) const;
5022 ABIArgInfo classifyArgumentType(QualType Ty) const;
5024 void computeInfo(CGFunctionInfo &FI) const override;
5025 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
5026 CodeGenFunction &CFG) const override;
5029 class NVPTXTargetCodeGenInfo : public TargetCodeGenInfo {
5031 NVPTXTargetCodeGenInfo(CodeGenTypes &CGT)
5032 : TargetCodeGenInfo(new NVPTXABIInfo(CGT)) {}
5034 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5035 CodeGen::CodeGenModule &M) const override;
5037 // Adds a NamedMDNode with F, Name, and Operand as operands, and adds the
5038 // resulting MDNode to the nvvm.annotations MDNode.
5039 static void addNVVMMetadata(llvm::Function *F, StringRef Name, int Operand);
5042 ABIArgInfo NVPTXABIInfo::classifyReturnType(QualType RetTy) const {
5043 if (RetTy->isVoidType())
5044 return ABIArgInfo::getIgnore();
5046 // note: this is different from default ABI
5047 if (!RetTy->isScalarType())
5048 return ABIArgInfo::getDirect();
5050 // Treat an enum type as its underlying type.
5051 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5052 RetTy = EnumTy->getDecl()->getIntegerType();
5054 return (RetTy->isPromotableIntegerType() ?
5055 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
5058 ABIArgInfo NVPTXABIInfo::classifyArgumentType(QualType Ty) const {
5059 // Treat an enum type as its underlying type.
5060 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
5061 Ty = EnumTy->getDecl()->getIntegerType();
5063 // Return aggregates type as indirect by value
5064 if (isAggregateTypeForABI(Ty))
5065 return ABIArgInfo::getIndirect(0, /* byval */ true);
5067 return (Ty->isPromotableIntegerType() ?
5068 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
5071 void NVPTXABIInfo::computeInfo(CGFunctionInfo &FI) const {
5072 if (!getCXXABI().classifyReturnType(FI))
5073 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
5074 for (auto &I : FI.arguments())
5075 I.info = classifyArgumentType(I.type);
5077 // Always honor user-specified calling convention.
5078 if (FI.getCallingConvention() != llvm::CallingConv::C)
5081 FI.setEffectiveCallingConvention(getRuntimeCC());
5084 llvm::Value *NVPTXABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
5085 CodeGenFunction &CFG) const {
5086 llvm_unreachable("NVPTX does not support varargs");
5089 void NVPTXTargetCodeGenInfo::
5090 SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5091 CodeGen::CodeGenModule &M) const{
5092 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D);
5095 llvm::Function *F = cast<llvm::Function>(GV);
5097 // Perform special handling in OpenCL mode
5098 if (M.getLangOpts().OpenCL) {
5099 // Use OpenCL function attributes to check for kernel functions
5100 // By default, all functions are device functions
5101 if (FD->hasAttr<OpenCLKernelAttr>()) {
5102 // OpenCL __kernel functions get kernel metadata
5103 // Create !{<func-ref>, metadata !"kernel", i32 1} node
5104 addNVVMMetadata(F, "kernel", 1);
5105 // And kernel functions are not subject to inlining
5106 F->addFnAttr(llvm::Attribute::NoInline);
5110 // Perform special handling in CUDA mode.
5111 if (M.getLangOpts().CUDA) {
5112 // CUDA __global__ functions get a kernel metadata entry. Since
5113 // __global__ functions cannot be called from the device, we do not
5114 // need to set the noinline attribute.
5115 if (FD->hasAttr<CUDAGlobalAttr>()) {
5116 // Create !{<func-ref>, metadata !"kernel", i32 1} node
5117 addNVVMMetadata(F, "kernel", 1);
5119 if (CUDALaunchBoundsAttr *Attr = FD->getAttr<CUDALaunchBoundsAttr>()) {
5120 // Create !{<func-ref>, metadata !"maxntidx", i32 <val>} node
5121 llvm::APSInt MaxThreads(32);
5122 MaxThreads = Attr->getMaxThreads()->EvaluateKnownConstInt(M.getContext());
5124 addNVVMMetadata(F, "maxntidx", MaxThreads.getExtValue());
5126 // min blocks is an optional argument for CUDALaunchBoundsAttr. If it was
5127 // not specified in __launch_bounds__ or if the user specified a 0 value,
5128 // we don't have to add a PTX directive.
5129 if (Attr->getMinBlocks()) {
5130 llvm::APSInt MinBlocks(32);
5131 MinBlocks = Attr->getMinBlocks()->EvaluateKnownConstInt(M.getContext());
5133 // Create !{<func-ref>, metadata !"minctasm", i32 <val>} node
5134 addNVVMMetadata(F, "minctasm", MinBlocks.getExtValue());
5140 void NVPTXTargetCodeGenInfo::addNVVMMetadata(llvm::Function *F, StringRef Name,
5142 llvm::Module *M = F->getParent();
5143 llvm::LLVMContext &Ctx = M->getContext();
5145 // Get "nvvm.annotations" metadata node
5146 llvm::NamedMDNode *MD = M->getOrInsertNamedMetadata("nvvm.annotations");
5148 llvm::Metadata *MDVals[] = {
5149 llvm::ConstantAsMetadata::get(F), llvm::MDString::get(Ctx, Name),
5150 llvm::ConstantAsMetadata::get(
5151 llvm::ConstantInt::get(llvm::Type::getInt32Ty(Ctx), Operand))};
5152 // Append metadata to nvvm.annotations
5153 MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
5157 //===----------------------------------------------------------------------===//
5158 // SystemZ ABI Implementation
5159 //===----------------------------------------------------------------------===//
5163 class SystemZABIInfo : public ABIInfo {
5167 SystemZABIInfo(CodeGenTypes &CGT, bool HV)
5168 : ABIInfo(CGT), HasVector(HV) {}
5170 bool isPromotableIntegerType(QualType Ty) const;
5171 bool isCompoundType(QualType Ty) const;
5172 bool isVectorArgumentType(QualType Ty) const;
5173 bool isFPArgumentType(QualType Ty) const;
5174 QualType GetSingleElementType(QualType Ty) const;
5176 ABIArgInfo classifyReturnType(QualType RetTy) const;
5177 ABIArgInfo classifyArgumentType(QualType ArgTy) const;
5179 void computeInfo(CGFunctionInfo &FI) const override {
5180 if (!getCXXABI().classifyReturnType(FI))
5181 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
5182 for (auto &I : FI.arguments())
5183 I.info = classifyArgumentType(I.type);
5186 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
5187 CodeGenFunction &CGF) const override;
5190 class SystemZTargetCodeGenInfo : public TargetCodeGenInfo {
5192 SystemZTargetCodeGenInfo(CodeGenTypes &CGT, bool HasVector)
5193 : TargetCodeGenInfo(new SystemZABIInfo(CGT, HasVector)) {}
5198 bool SystemZABIInfo::isPromotableIntegerType(QualType Ty) const {
5199 // Treat an enum type as its underlying type.
5200 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
5201 Ty = EnumTy->getDecl()->getIntegerType();
5203 // Promotable integer types are required to be promoted by the ABI.
5204 if (Ty->isPromotableIntegerType())
5207 // 32-bit values must also be promoted.
5208 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
5209 switch (BT->getKind()) {
5210 case BuiltinType::Int:
5211 case BuiltinType::UInt:
5219 bool SystemZABIInfo::isCompoundType(QualType Ty) const {
5220 return (Ty->isAnyComplexType() ||
5221 Ty->isVectorType() ||
5222 isAggregateTypeForABI(Ty));
5225 bool SystemZABIInfo::isVectorArgumentType(QualType Ty) const {
5226 return (HasVector &&
5227 Ty->isVectorType() &&
5228 getContext().getTypeSize(Ty) <= 128);
5231 bool SystemZABIInfo::isFPArgumentType(QualType Ty) const {
5232 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
5233 switch (BT->getKind()) {
5234 case BuiltinType::Float:
5235 case BuiltinType::Double:
5244 QualType SystemZABIInfo::GetSingleElementType(QualType Ty) const {
5245 if (const RecordType *RT = Ty->getAsStructureType()) {
5246 const RecordDecl *RD = RT->getDecl();
5249 // If this is a C++ record, check the bases first.
5250 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
5251 for (const auto &I : CXXRD->bases()) {
5252 QualType Base = I.getType();
5254 // Empty bases don't affect things either way.
5255 if (isEmptyRecord(getContext(), Base, true))
5258 if (!Found.isNull())
5260 Found = GetSingleElementType(Base);
5263 // Check the fields.
5264 for (const auto *FD : RD->fields()) {
5265 // For compatibility with GCC, ignore empty bitfields in C++ mode.
5266 // Unlike isSingleElementStruct(), empty structure and array fields
5267 // do count. So do anonymous bitfields that aren't zero-sized.
5268 if (getContext().getLangOpts().CPlusPlus &&
5269 FD->isBitField() && FD->getBitWidthValue(getContext()) == 0)
5272 // Unlike isSingleElementStruct(), arrays do not count.
5273 // Nested structures still do though.
5274 if (!Found.isNull())
5276 Found = GetSingleElementType(FD->getType());
5279 // Unlike isSingleElementStruct(), trailing padding is allowed.
5280 // An 8-byte aligned struct s { float f; } is passed as a double.
5281 if (!Found.isNull())
5288 llvm::Value *SystemZABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
5289 CodeGenFunction &CGF) const {
5290 // Assume that va_list type is correct; should be pointer to LLVM type:
5294 // i8 *__overflow_arg_area;
5295 // i8 *__reg_save_area;
5298 // Every non-vector argument occupies 8 bytes and is passed by preference
5299 // in either GPRs or FPRs. Vector arguments occupy 8 or 16 bytes and are
5300 // always passed on the stack.
5301 Ty = CGF.getContext().getCanonicalType(Ty);
5302 llvm::Type *ArgTy = CGF.ConvertTypeForMem(Ty);
5303 llvm::Type *APTy = llvm::PointerType::getUnqual(ArgTy);
5304 ABIArgInfo AI = classifyArgumentType(Ty);
5305 bool IsIndirect = AI.isIndirect();
5306 bool InFPRs = false;
5307 bool IsVector = false;
5308 unsigned UnpaddedBitSize;
5310 APTy = llvm::PointerType::getUnqual(APTy);
5311 UnpaddedBitSize = 64;
5313 if (AI.getCoerceToType())
5314 ArgTy = AI.getCoerceToType();
5315 InFPRs = ArgTy->isFloatTy() || ArgTy->isDoubleTy();
5316 IsVector = ArgTy->isVectorTy();
5317 UnpaddedBitSize = getContext().getTypeSize(Ty);
5319 unsigned PaddedBitSize = (IsVector && UnpaddedBitSize > 64) ? 128 : 64;
5320 assert((UnpaddedBitSize <= PaddedBitSize) && "Invalid argument size.");
5322 unsigned PaddedSize = PaddedBitSize / 8;
5323 unsigned Padding = (PaddedBitSize - UnpaddedBitSize) / 8;
5325 llvm::Type *IndexTy = CGF.Int64Ty;
5326 llvm::Value *PaddedSizeV = llvm::ConstantInt::get(IndexTy, PaddedSize);
5329 // Work out the address of a vector argument on the stack.
5330 // Vector arguments are always passed in the high bits of a
5331 // single (8 byte) or double (16 byte) stack slot.
5332 llvm::Value *OverflowArgAreaPtr =
5333 CGF.Builder.CreateStructGEP(nullptr, VAListAddr, 2,
5334 "overflow_arg_area_ptr");
5335 llvm::Value *OverflowArgArea =
5336 CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area");
5337 llvm::Value *MemAddr =
5338 CGF.Builder.CreateBitCast(OverflowArgArea, APTy, "mem_addr");
5340 // Update overflow_arg_area_ptr pointer
5341 llvm::Value *NewOverflowArgArea =
5342 CGF.Builder.CreateGEP(OverflowArgArea, PaddedSizeV, "overflow_arg_area");
5343 CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
5348 unsigned MaxRegs, RegCountField, RegSaveIndex, RegPadding;
5350 MaxRegs = 4; // Maximum of 4 FPR arguments
5351 RegCountField = 1; // __fpr
5352 RegSaveIndex = 16; // save offset for f0
5353 RegPadding = 0; // floats are passed in the high bits of an FPR
5355 MaxRegs = 5; // Maximum of 5 GPR arguments
5356 RegCountField = 0; // __gpr
5357 RegSaveIndex = 2; // save offset for r2
5358 RegPadding = Padding; // values are passed in the low bits of a GPR
5361 llvm::Value *RegCountPtr = CGF.Builder.CreateStructGEP(
5362 nullptr, VAListAddr, RegCountField, "reg_count_ptr");
5363 llvm::Value *RegCount = CGF.Builder.CreateLoad(RegCountPtr, "reg_count");
5364 llvm::Value *MaxRegsV = llvm::ConstantInt::get(IndexTy, MaxRegs);
5365 llvm::Value *InRegs = CGF.Builder.CreateICmpULT(RegCount, MaxRegsV,
5368 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
5369 llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
5370 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
5371 CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
5373 // Emit code to load the value if it was passed in registers.
5374 CGF.EmitBlock(InRegBlock);
5376 // Work out the address of an argument register.
5377 llvm::Value *ScaledRegCount =
5378 CGF.Builder.CreateMul(RegCount, PaddedSizeV, "scaled_reg_count");
5379 llvm::Value *RegBase =
5380 llvm::ConstantInt::get(IndexTy, RegSaveIndex * PaddedSize + RegPadding);
5381 llvm::Value *RegOffset =
5382 CGF.Builder.CreateAdd(ScaledRegCount, RegBase, "reg_offset");
5383 llvm::Value *RegSaveAreaPtr =
5384 CGF.Builder.CreateStructGEP(nullptr, VAListAddr, 3, "reg_save_area_ptr");
5385 llvm::Value *RegSaveArea =
5386 CGF.Builder.CreateLoad(RegSaveAreaPtr, "reg_save_area");
5387 llvm::Value *RawRegAddr =
5388 CGF.Builder.CreateGEP(RegSaveArea, RegOffset, "raw_reg_addr");
5389 llvm::Value *RegAddr =
5390 CGF.Builder.CreateBitCast(RawRegAddr, APTy, "reg_addr");
5392 // Update the register count
5393 llvm::Value *One = llvm::ConstantInt::get(IndexTy, 1);
5394 llvm::Value *NewRegCount =
5395 CGF.Builder.CreateAdd(RegCount, One, "reg_count");
5396 CGF.Builder.CreateStore(NewRegCount, RegCountPtr);
5397 CGF.EmitBranch(ContBlock);
5399 // Emit code to load the value if it was passed in memory.
5400 CGF.EmitBlock(InMemBlock);
5402 // Work out the address of a stack argument.
5403 llvm::Value *OverflowArgAreaPtr = CGF.Builder.CreateStructGEP(
5404 nullptr, VAListAddr, 2, "overflow_arg_area_ptr");
5405 llvm::Value *OverflowArgArea =
5406 CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area");
5407 llvm::Value *PaddingV = llvm::ConstantInt::get(IndexTy, Padding);
5408 llvm::Value *RawMemAddr =
5409 CGF.Builder.CreateGEP(OverflowArgArea, PaddingV, "raw_mem_addr");
5410 llvm::Value *MemAddr =
5411 CGF.Builder.CreateBitCast(RawMemAddr, APTy, "mem_addr");
5413 // Update overflow_arg_area_ptr pointer
5414 llvm::Value *NewOverflowArgArea =
5415 CGF.Builder.CreateGEP(OverflowArgArea, PaddedSizeV, "overflow_arg_area");
5416 CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
5417 CGF.EmitBranch(ContBlock);
5419 // Return the appropriate result.
5420 CGF.EmitBlock(ContBlock);
5421 llvm::PHINode *ResAddr = CGF.Builder.CreatePHI(APTy, 2, "va_arg.addr");
5422 ResAddr->addIncoming(RegAddr, InRegBlock);
5423 ResAddr->addIncoming(MemAddr, InMemBlock);
5426 return CGF.Builder.CreateLoad(ResAddr, "indirect_arg");
5431 ABIArgInfo SystemZABIInfo::classifyReturnType(QualType RetTy) const {
5432 if (RetTy->isVoidType())
5433 return ABIArgInfo::getIgnore();
5434 if (isVectorArgumentType(RetTy))
5435 return ABIArgInfo::getDirect();
5436 if (isCompoundType(RetTy) || getContext().getTypeSize(RetTy) > 64)
5437 return ABIArgInfo::getIndirect(0);
5438 return (isPromotableIntegerType(RetTy) ?
5439 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
5442 ABIArgInfo SystemZABIInfo::classifyArgumentType(QualType Ty) const {
5443 // Handle the generic C++ ABI.
5444 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
5445 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
5447 // Integers and enums are extended to full register width.
5448 if (isPromotableIntegerType(Ty))
5449 return ABIArgInfo::getExtend();
5451 // Handle vector types and vector-like structure types. Note that
5452 // as opposed to float-like structure types, we do not allow any
5453 // padding for vector-like structures, so verify the sizes match.
5454 uint64_t Size = getContext().getTypeSize(Ty);
5455 QualType SingleElementTy = GetSingleElementType(Ty);
5456 if (isVectorArgumentType(SingleElementTy) &&
5457 getContext().getTypeSize(SingleElementTy) == Size)
5458 return ABIArgInfo::getDirect(CGT.ConvertType(SingleElementTy));
5460 // Values that are not 1, 2, 4 or 8 bytes in size are passed indirectly.
5461 if (Size != 8 && Size != 16 && Size != 32 && Size != 64)
5462 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
5464 // Handle small structures.
5465 if (const RecordType *RT = Ty->getAs<RecordType>()) {
5466 // Structures with flexible arrays have variable length, so really
5467 // fail the size test above.
5468 const RecordDecl *RD = RT->getDecl();
5469 if (RD->hasFlexibleArrayMember())
5470 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
5472 // The structure is passed as an unextended integer, a float, or a double.
5474 if (isFPArgumentType(SingleElementTy)) {
5475 assert(Size == 32 || Size == 64);
5477 PassTy = llvm::Type::getFloatTy(getVMContext());
5479 PassTy = llvm::Type::getDoubleTy(getVMContext());
5481 PassTy = llvm::IntegerType::get(getVMContext(), Size);
5482 return ABIArgInfo::getDirect(PassTy);
5485 // Non-structure compounds are passed indirectly.
5486 if (isCompoundType(Ty))
5487 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
5489 return ABIArgInfo::getDirect(nullptr);
5492 //===----------------------------------------------------------------------===//
5493 // MSP430 ABI Implementation
5494 //===----------------------------------------------------------------------===//
5498 class MSP430TargetCodeGenInfo : public TargetCodeGenInfo {
5500 MSP430TargetCodeGenInfo(CodeGenTypes &CGT)
5501 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
5502 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5503 CodeGen::CodeGenModule &M) const override;
5508 void MSP430TargetCodeGenInfo::SetTargetAttributes(const Decl *D,
5509 llvm::GlobalValue *GV,
5510 CodeGen::CodeGenModule &M) const {
5511 if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) {
5512 if (const MSP430InterruptAttr *attr = FD->getAttr<MSP430InterruptAttr>()) {
5513 // Handle 'interrupt' attribute:
5514 llvm::Function *F = cast<llvm::Function>(GV);
5516 // Step 1: Set ISR calling convention.
5517 F->setCallingConv(llvm::CallingConv::MSP430_INTR);
5519 // Step 2: Add attributes goodness.
5520 F->addFnAttr(llvm::Attribute::NoInline);
5522 // Step 3: Emit ISR vector alias.
5523 unsigned Num = attr->getNumber() / 2;
5524 llvm::GlobalAlias::create(llvm::Function::ExternalLinkage,
5525 "__isr_" + Twine(Num), F);
5530 //===----------------------------------------------------------------------===//
5531 // MIPS ABI Implementation. This works for both little-endian and
5532 // big-endian variants.
5533 //===----------------------------------------------------------------------===//
5536 class MipsABIInfo : public ABIInfo {
5538 unsigned MinABIStackAlignInBytes, StackAlignInBytes;
5539 void CoerceToIntArgs(uint64_t TySize,
5540 SmallVectorImpl<llvm::Type *> &ArgList) const;
5541 llvm::Type* HandleAggregates(QualType Ty, uint64_t TySize) const;
5542 llvm::Type* returnAggregateInRegs(QualType RetTy, uint64_t Size) const;
5543 llvm::Type* getPaddingType(uint64_t Align, uint64_t Offset) const;
5545 MipsABIInfo(CodeGenTypes &CGT, bool _IsO32) :
5546 ABIInfo(CGT), IsO32(_IsO32), MinABIStackAlignInBytes(IsO32 ? 4 : 8),
5547 StackAlignInBytes(IsO32 ? 8 : 16) {}
5549 ABIArgInfo classifyReturnType(QualType RetTy) const;
5550 ABIArgInfo classifyArgumentType(QualType RetTy, uint64_t &Offset) const;
5551 void computeInfo(CGFunctionInfo &FI) const override;
5552 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
5553 CodeGenFunction &CGF) const override;
5554 bool shouldSignExtUnsignedType(QualType Ty) const override;
5557 class MIPSTargetCodeGenInfo : public TargetCodeGenInfo {
5558 unsigned SizeOfUnwindException;
5560 MIPSTargetCodeGenInfo(CodeGenTypes &CGT, bool IsO32)
5561 : TargetCodeGenInfo(new MipsABIInfo(CGT, IsO32)),
5562 SizeOfUnwindException(IsO32 ? 24 : 32) {}
5564 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
5568 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5569 CodeGen::CodeGenModule &CGM) const override {
5570 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D);
5572 llvm::Function *Fn = cast<llvm::Function>(GV);
5573 if (FD->hasAttr<Mips16Attr>()) {
5574 Fn->addFnAttr("mips16");
5576 else if (FD->hasAttr<NoMips16Attr>()) {
5577 Fn->addFnAttr("nomips16");
5581 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5582 llvm::Value *Address) const override;
5584 unsigned getSizeOfUnwindException() const override {
5585 return SizeOfUnwindException;
5590 void MipsABIInfo::CoerceToIntArgs(uint64_t TySize,
5591 SmallVectorImpl<llvm::Type *> &ArgList) const {
5592 llvm::IntegerType *IntTy =
5593 llvm::IntegerType::get(getVMContext(), MinABIStackAlignInBytes * 8);
5595 // Add (TySize / MinABIStackAlignInBytes) args of IntTy.
5596 for (unsigned N = TySize / (MinABIStackAlignInBytes * 8); N; --N)
5597 ArgList.push_back(IntTy);
5599 // If necessary, add one more integer type to ArgList.
5600 unsigned R = TySize % (MinABIStackAlignInBytes * 8);
5603 ArgList.push_back(llvm::IntegerType::get(getVMContext(), R));
5606 // In N32/64, an aligned double precision floating point field is passed in
5608 llvm::Type* MipsABIInfo::HandleAggregates(QualType Ty, uint64_t TySize) const {
5609 SmallVector<llvm::Type*, 8> ArgList, IntArgList;
5612 CoerceToIntArgs(TySize, ArgList);
5613 return llvm::StructType::get(getVMContext(), ArgList);
5616 if (Ty->isComplexType())
5617 return CGT.ConvertType(Ty);
5619 const RecordType *RT = Ty->getAs<RecordType>();
5621 // Unions/vectors are passed in integer registers.
5622 if (!RT || !RT->isStructureOrClassType()) {
5623 CoerceToIntArgs(TySize, ArgList);
5624 return llvm::StructType::get(getVMContext(), ArgList);
5627 const RecordDecl *RD = RT->getDecl();
5628 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
5629 assert(!(TySize % 8) && "Size of structure must be multiple of 8.");
5631 uint64_t LastOffset = 0;
5633 llvm::IntegerType *I64 = llvm::IntegerType::get(getVMContext(), 64);
5635 // Iterate over fields in the struct/class and check if there are any aligned
5637 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
5638 i != e; ++i, ++idx) {
5639 const QualType Ty = i->getType();
5640 const BuiltinType *BT = Ty->getAs<BuiltinType>();
5642 if (!BT || BT->getKind() != BuiltinType::Double)
5645 uint64_t Offset = Layout.getFieldOffset(idx);
5646 if (Offset % 64) // Ignore doubles that are not aligned.
5649 // Add ((Offset - LastOffset) / 64) args of type i64.
5650 for (unsigned j = (Offset - LastOffset) / 64; j > 0; --j)
5651 ArgList.push_back(I64);
5654 ArgList.push_back(llvm::Type::getDoubleTy(getVMContext()));
5655 LastOffset = Offset + 64;
5658 CoerceToIntArgs(TySize - LastOffset, IntArgList);
5659 ArgList.append(IntArgList.begin(), IntArgList.end());
5661 return llvm::StructType::get(getVMContext(), ArgList);
5664 llvm::Type *MipsABIInfo::getPaddingType(uint64_t OrigOffset,
5665 uint64_t Offset) const {
5666 if (OrigOffset + MinABIStackAlignInBytes > Offset)
5669 return llvm::IntegerType::get(getVMContext(), (Offset - OrigOffset) * 8);
5673 MipsABIInfo::classifyArgumentType(QualType Ty, uint64_t &Offset) const {
5674 Ty = useFirstFieldIfTransparentUnion(Ty);
5676 uint64_t OrigOffset = Offset;
5677 uint64_t TySize = getContext().getTypeSize(Ty);
5678 uint64_t Align = getContext().getTypeAlign(Ty) / 8;
5680 Align = std::min(std::max(Align, (uint64_t)MinABIStackAlignInBytes),
5681 (uint64_t)StackAlignInBytes);
5682 unsigned CurrOffset = llvm::RoundUpToAlignment(Offset, Align);
5683 Offset = CurrOffset + llvm::RoundUpToAlignment(TySize, Align * 8) / 8;
5685 if (isAggregateTypeForABI(Ty) || Ty->isVectorType()) {
5686 // Ignore empty aggregates.
5688 return ABIArgInfo::getIgnore();
5690 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
5691 Offset = OrigOffset + MinABIStackAlignInBytes;
5692 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
5695 // If we have reached here, aggregates are passed directly by coercing to
5696 // another structure type. Padding is inserted if the offset of the
5697 // aggregate is unaligned.
5698 ABIArgInfo ArgInfo =
5699 ABIArgInfo::getDirect(HandleAggregates(Ty, TySize), 0,
5700 getPaddingType(OrigOffset, CurrOffset));
5701 ArgInfo.setInReg(true);
5705 // Treat an enum type as its underlying type.
5706 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
5707 Ty = EnumTy->getDecl()->getIntegerType();
5709 // All integral types are promoted to the GPR width.
5710 if (Ty->isIntegralOrEnumerationType())
5711 return ABIArgInfo::getExtend();
5713 return ABIArgInfo::getDirect(
5714 nullptr, 0, IsO32 ? nullptr : getPaddingType(OrigOffset, CurrOffset));
5718 MipsABIInfo::returnAggregateInRegs(QualType RetTy, uint64_t Size) const {
5719 const RecordType *RT = RetTy->getAs<RecordType>();
5720 SmallVector<llvm::Type*, 8> RTList;
5722 if (RT && RT->isStructureOrClassType()) {
5723 const RecordDecl *RD = RT->getDecl();
5724 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
5725 unsigned FieldCnt = Layout.getFieldCount();
5727 // N32/64 returns struct/classes in floating point registers if the
5728 // following conditions are met:
5729 // 1. The size of the struct/class is no larger than 128-bit.
5730 // 2. The struct/class has one or two fields all of which are floating
5732 // 3. The offset of the first field is zero (this follows what gcc does).
5734 // Any other composite results are returned in integer registers.
5736 if (FieldCnt && (FieldCnt <= 2) && !Layout.getFieldOffset(0)) {
5737 RecordDecl::field_iterator b = RD->field_begin(), e = RD->field_end();
5738 for (; b != e; ++b) {
5739 const BuiltinType *BT = b->getType()->getAs<BuiltinType>();
5741 if (!BT || !BT->isFloatingPoint())
5744 RTList.push_back(CGT.ConvertType(b->getType()));
5748 return llvm::StructType::get(getVMContext(), RTList,
5749 RD->hasAttr<PackedAttr>());
5755 CoerceToIntArgs(Size, RTList);
5756 return llvm::StructType::get(getVMContext(), RTList);
5759 ABIArgInfo MipsABIInfo::classifyReturnType(QualType RetTy) const {
5760 uint64_t Size = getContext().getTypeSize(RetTy);
5762 if (RetTy->isVoidType())
5763 return ABIArgInfo::getIgnore();
5765 // O32 doesn't treat zero-sized structs differently from other structs.
5766 // However, N32/N64 ignores zero sized return values.
5767 if (!IsO32 && Size == 0)
5768 return ABIArgInfo::getIgnore();
5770 if (isAggregateTypeForABI(RetTy) || RetTy->isVectorType()) {
5772 if (RetTy->isAnyComplexType())
5773 return ABIArgInfo::getDirect();
5775 // O32 returns integer vectors in registers and N32/N64 returns all small
5776 // aggregates in registers.
5778 (RetTy->isVectorType() && !RetTy->hasFloatingRepresentation())) {
5779 ABIArgInfo ArgInfo =
5780 ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size));
5781 ArgInfo.setInReg(true);
5786 return ABIArgInfo::getIndirect(0);
5789 // Treat an enum type as its underlying type.
5790 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5791 RetTy = EnumTy->getDecl()->getIntegerType();
5793 return (RetTy->isPromotableIntegerType() ?
5794 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
5797 void MipsABIInfo::computeInfo(CGFunctionInfo &FI) const {
5798 ABIArgInfo &RetInfo = FI.getReturnInfo();
5799 if (!getCXXABI().classifyReturnType(FI))
5800 RetInfo = classifyReturnType(FI.getReturnType());
5802 // Check if a pointer to an aggregate is passed as a hidden argument.
5803 uint64_t Offset = RetInfo.isIndirect() ? MinABIStackAlignInBytes : 0;
5805 for (auto &I : FI.arguments())
5806 I.info = classifyArgumentType(I.type, Offset);
5809 llvm::Value* MipsABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
5810 CodeGenFunction &CGF) const {
5811 llvm::Type *BP = CGF.Int8PtrTy;
5812 llvm::Type *BPP = CGF.Int8PtrPtrTy;
5814 // Integer arguments are promoted to 32-bit on O32 and 64-bit on N32/N64.
5815 // Pointers are also promoted in the same way but this only matters for N32.
5816 unsigned SlotSizeInBits = IsO32 ? 32 : 64;
5817 unsigned PtrWidth = getTarget().getPointerWidth(0);
5818 if ((Ty->isIntegerType() &&
5819 CGF.getContext().getIntWidth(Ty) < SlotSizeInBits) ||
5820 (Ty->isPointerType() && PtrWidth < SlotSizeInBits)) {
5821 Ty = CGF.getContext().getIntTypeForBitwidth(SlotSizeInBits,
5822 Ty->isSignedIntegerType());
5825 CGBuilderTy &Builder = CGF.Builder;
5826 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap");
5827 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur");
5829 std::min(getContext().getTypeAlign(Ty) / 8, StackAlignInBytes);
5830 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
5831 llvm::Value *AddrTyped;
5832 llvm::IntegerType *IntTy = (PtrWidth == 32) ? CGF.Int32Ty : CGF.Int64Ty;
5834 if (TypeAlign > MinABIStackAlignInBytes) {
5835 llvm::Value *AddrAsInt = CGF.Builder.CreatePtrToInt(Addr, IntTy);
5836 llvm::Value *Inc = llvm::ConstantInt::get(IntTy, TypeAlign - 1);
5837 llvm::Value *Mask = llvm::ConstantInt::get(IntTy, -TypeAlign);
5838 llvm::Value *Add = CGF.Builder.CreateAdd(AddrAsInt, Inc);
5839 llvm::Value *And = CGF.Builder.CreateAnd(Add, Mask);
5840 AddrTyped = CGF.Builder.CreateIntToPtr(And, PTy);
5843 AddrTyped = Builder.CreateBitCast(Addr, PTy);
5845 llvm::Value *AlignedAddr = Builder.CreateBitCast(AddrTyped, BP);
5846 TypeAlign = std::max((unsigned)TypeAlign, MinABIStackAlignInBytes);
5847 unsigned ArgSizeInBits = CGF.getContext().getTypeSize(Ty);
5848 uint64_t Offset = llvm::RoundUpToAlignment(ArgSizeInBits / 8, TypeAlign);
5849 llvm::Value *NextAddr =
5850 Builder.CreateGEP(AlignedAddr, llvm::ConstantInt::get(IntTy, Offset),
5852 Builder.CreateStore(NextAddr, VAListAddrAsBPP);
5857 bool MipsABIInfo::shouldSignExtUnsignedType(QualType Ty) const {
5858 int TySize = getContext().getTypeSize(Ty);
5860 // MIPS64 ABI requires unsigned 32 bit integers to be sign extended.
5861 if (Ty->isUnsignedIntegerOrEnumerationType() && TySize == 32)
5868 MIPSTargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5869 llvm::Value *Address) const {
5870 // This information comes from gcc's implementation, which seems to
5871 // as canonical as it gets.
5873 // Everything on MIPS is 4 bytes. Double-precision FP registers
5874 // are aliased to pairs of single-precision FP registers.
5875 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
5877 // 0-31 are the general purpose registers, $0 - $31.
5878 // 32-63 are the floating-point registers, $f0 - $f31.
5879 // 64 and 65 are the multiply/divide registers, $hi and $lo.
5880 // 66 is the (notional, I think) register for signal-handler return.
5881 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 65);
5883 // 67-74 are the floating-point status registers, $fcc0 - $fcc7.
5884 // They are one bit wide and ignored here.
5886 // 80-111 are the coprocessor 0 registers, $c0r0 - $c0r31.
5887 // (coprocessor 1 is the FP unit)
5888 // 112-143 are the coprocessor 2 registers, $c2r0 - $c2r31.
5889 // 144-175 are the coprocessor 3 registers, $c3r0 - $c3r31.
5890 // 176-181 are the DSP accumulator registers.
5891 AssignToArrayRange(CGF.Builder, Address, Four8, 80, 181);
5895 //===----------------------------------------------------------------------===//
5896 // TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults.
5897 // Currently subclassed only to implement custom OpenCL C function attribute
5899 //===----------------------------------------------------------------------===//
5903 class TCETargetCodeGenInfo : public DefaultTargetCodeGenInfo {
5905 TCETargetCodeGenInfo(CodeGenTypes &CGT)
5906 : DefaultTargetCodeGenInfo(CGT) {}
5908 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5909 CodeGen::CodeGenModule &M) const override;
5912 void TCETargetCodeGenInfo::SetTargetAttributes(const Decl *D,
5913 llvm::GlobalValue *GV,
5914 CodeGen::CodeGenModule &M) const {
5915 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D);
5918 llvm::Function *F = cast<llvm::Function>(GV);
5920 if (M.getLangOpts().OpenCL) {
5921 if (FD->hasAttr<OpenCLKernelAttr>()) {
5922 // OpenCL C Kernel functions are not subject to inlining
5923 F->addFnAttr(llvm::Attribute::NoInline);
5924 const ReqdWorkGroupSizeAttr *Attr = FD->getAttr<ReqdWorkGroupSizeAttr>();
5926 // Convert the reqd_work_group_size() attributes to metadata.
5927 llvm::LLVMContext &Context = F->getContext();
5928 llvm::NamedMDNode *OpenCLMetadata =
5929 M.getModule().getOrInsertNamedMetadata("opencl.kernel_wg_size_info");
5931 SmallVector<llvm::Metadata *, 5> Operands;
5932 Operands.push_back(llvm::ConstantAsMetadata::get(F));
5935 llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
5936 M.Int32Ty, llvm::APInt(32, Attr->getXDim()))));
5938 llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
5939 M.Int32Ty, llvm::APInt(32, Attr->getYDim()))));
5941 llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
5942 M.Int32Ty, llvm::APInt(32, Attr->getZDim()))));
5944 // Add a boolean constant operand for "required" (true) or "hint" (false)
5945 // for implementing the work_group_size_hint attr later. Currently
5946 // always true as the hint is not yet implemented.
5948 llvm::ConstantAsMetadata::get(llvm::ConstantInt::getTrue(Context)));
5949 OpenCLMetadata->addOperand(llvm::MDNode::get(Context, Operands));
5957 //===----------------------------------------------------------------------===//
5958 // Hexagon ABI Implementation
5959 //===----------------------------------------------------------------------===//
5963 class HexagonABIInfo : public ABIInfo {
5967 HexagonABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
5971 ABIArgInfo classifyReturnType(QualType RetTy) const;
5972 ABIArgInfo classifyArgumentType(QualType RetTy) const;
5974 void computeInfo(CGFunctionInfo &FI) const override;
5976 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
5977 CodeGenFunction &CGF) const override;
5980 class HexagonTargetCodeGenInfo : public TargetCodeGenInfo {
5982 HexagonTargetCodeGenInfo(CodeGenTypes &CGT)
5983 :TargetCodeGenInfo(new HexagonABIInfo(CGT)) {}
5985 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5992 void HexagonABIInfo::computeInfo(CGFunctionInfo &FI) const {
5993 if (!getCXXABI().classifyReturnType(FI))
5994 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
5995 for (auto &I : FI.arguments())
5996 I.info = classifyArgumentType(I.type);
5999 ABIArgInfo HexagonABIInfo::classifyArgumentType(QualType Ty) const {
6000 if (!isAggregateTypeForABI(Ty)) {
6001 // Treat an enum type as its underlying type.
6002 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6003 Ty = EnumTy->getDecl()->getIntegerType();
6005 return (Ty->isPromotableIntegerType() ?
6006 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6009 // Ignore empty records.
6010 if (isEmptyRecord(getContext(), Ty, true))
6011 return ABIArgInfo::getIgnore();
6013 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
6014 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
6016 uint64_t Size = getContext().getTypeSize(Ty);
6018 return ABIArgInfo::getIndirect(0, /*ByVal=*/true);
6019 // Pass in the smallest viable integer type.
6021 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
6023 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6025 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
6027 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
6030 ABIArgInfo HexagonABIInfo::classifyReturnType(QualType RetTy) const {
6031 if (RetTy->isVoidType())
6032 return ABIArgInfo::getIgnore();
6034 // Large vector types should be returned via memory.
6035 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 64)
6036 return ABIArgInfo::getIndirect(0);
6038 if (!isAggregateTypeForABI(RetTy)) {
6039 // Treat an enum type as its underlying type.
6040 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
6041 RetTy = EnumTy->getDecl()->getIntegerType();
6043 return (RetTy->isPromotableIntegerType() ?
6044 ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6047 if (isEmptyRecord(getContext(), RetTy, true))
6048 return ABIArgInfo::getIgnore();
6050 // Aggregates <= 8 bytes are returned in r0; other aggregates
6051 // are returned indirectly.
6052 uint64_t Size = getContext().getTypeSize(RetTy);
6054 // Return in the smallest viable integer type.
6056 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
6058 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
6060 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6061 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
6064 return ABIArgInfo::getIndirect(0, /*ByVal=*/true);
6067 llvm::Value *HexagonABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
6068 CodeGenFunction &CGF) const {
6069 // FIXME: Need to handle alignment
6070 llvm::Type *BPP = CGF.Int8PtrPtrTy;
6072 CGBuilderTy &Builder = CGF.Builder;
6073 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP,
6075 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur");
6077 llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
6078 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy);
6081 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, 4);
6082 llvm::Value *NextAddr =
6083 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset),
6085 Builder.CreateStore(NextAddr, VAListAddrAsBPP);
6090 //===----------------------------------------------------------------------===//
6091 // AMDGPU ABI Implementation
6092 //===----------------------------------------------------------------------===//
6096 class AMDGPUTargetCodeGenInfo : public TargetCodeGenInfo {
6098 AMDGPUTargetCodeGenInfo(CodeGenTypes &CGT)
6099 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
6100 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6101 CodeGen::CodeGenModule &M) const override;
6106 void AMDGPUTargetCodeGenInfo::SetTargetAttributes(
6108 llvm::GlobalValue *GV,
6109 CodeGen::CodeGenModule &M) const {
6110 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D);
6114 if (const auto Attr = FD->getAttr<AMDGPUNumVGPRAttr>()) {
6115 llvm::Function *F = cast<llvm::Function>(GV);
6116 uint32_t NumVGPR = Attr->getNumVGPR();
6118 F->addFnAttr("amdgpu_num_vgpr", llvm::utostr(NumVGPR));
6121 if (const auto Attr = FD->getAttr<AMDGPUNumSGPRAttr>()) {
6122 llvm::Function *F = cast<llvm::Function>(GV);
6123 unsigned NumSGPR = Attr->getNumSGPR();
6125 F->addFnAttr("amdgpu_num_sgpr", llvm::utostr(NumSGPR));
6130 //===----------------------------------------------------------------------===//
6131 // SPARC v9 ABI Implementation.
6132 // Based on the SPARC Compliance Definition version 2.4.1.
6134 // Function arguments a mapped to a nominal "parameter array" and promoted to
6135 // registers depending on their type. Each argument occupies 8 or 16 bytes in
6136 // the array, structs larger than 16 bytes are passed indirectly.
6138 // One case requires special care:
6145 // When a struct mixed is passed by value, it only occupies 8 bytes in the
6146 // parameter array, but the int is passed in an integer register, and the float
6147 // is passed in a floating point register. This is represented as two arguments
6148 // with the LLVM IR inreg attribute:
6150 // declare void f(i32 inreg %i, float inreg %f)
6152 // The code generator will only allocate 4 bytes from the parameter array for
6153 // the inreg arguments. All other arguments are allocated a multiple of 8
6157 class SparcV9ABIInfo : public ABIInfo {
6159 SparcV9ABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
6162 ABIArgInfo classifyType(QualType RetTy, unsigned SizeLimit) const;
6163 void computeInfo(CGFunctionInfo &FI) const override;
6164 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
6165 CodeGenFunction &CGF) const override;
6167 // Coercion type builder for structs passed in registers. The coercion type
6168 // serves two purposes:
6170 // 1. Pad structs to a multiple of 64 bits, so they are passed 'left-aligned'
6172 // 2. Expose aligned floating point elements as first-level elements, so the
6173 // code generator knows to pass them in floating point registers.
6175 // We also compute the InReg flag which indicates that the struct contains
6176 // aligned 32-bit floats.
6178 struct CoerceBuilder {
6179 llvm::LLVMContext &Context;
6180 const llvm::DataLayout &DL;
6181 SmallVector<llvm::Type*, 8> Elems;
6185 CoerceBuilder(llvm::LLVMContext &c, const llvm::DataLayout &dl)
6186 : Context(c), DL(dl), Size(0), InReg(false) {}
6188 // Pad Elems with integers until Size is ToSize.
6189 void pad(uint64_t ToSize) {
6190 assert(ToSize >= Size && "Cannot remove elements");
6194 // Finish the current 64-bit word.
6195 uint64_t Aligned = llvm::RoundUpToAlignment(Size, 64);
6196 if (Aligned > Size && Aligned <= ToSize) {
6197 Elems.push_back(llvm::IntegerType::get(Context, Aligned - Size));
6201 // Add whole 64-bit words.
6202 while (Size + 64 <= ToSize) {
6203 Elems.push_back(llvm::Type::getInt64Ty(Context));
6207 // Final in-word padding.
6208 if (Size < ToSize) {
6209 Elems.push_back(llvm::IntegerType::get(Context, ToSize - Size));
6214 // Add a floating point element at Offset.
6215 void addFloat(uint64_t Offset, llvm::Type *Ty, unsigned Bits) {
6216 // Unaligned floats are treated as integers.
6219 // The InReg flag is only required if there are any floats < 64 bits.
6223 Elems.push_back(Ty);
6224 Size = Offset + Bits;
6227 // Add a struct type to the coercion type, starting at Offset (in bits).
6228 void addStruct(uint64_t Offset, llvm::StructType *StrTy) {
6229 const llvm::StructLayout *Layout = DL.getStructLayout(StrTy);
6230 for (unsigned i = 0, e = StrTy->getNumElements(); i != e; ++i) {
6231 llvm::Type *ElemTy = StrTy->getElementType(i);
6232 uint64_t ElemOffset = Offset + Layout->getElementOffsetInBits(i);
6233 switch (ElemTy->getTypeID()) {
6234 case llvm::Type::StructTyID:
6235 addStruct(ElemOffset, cast<llvm::StructType>(ElemTy));
6237 case llvm::Type::FloatTyID:
6238 addFloat(ElemOffset, ElemTy, 32);
6240 case llvm::Type::DoubleTyID:
6241 addFloat(ElemOffset, ElemTy, 64);
6243 case llvm::Type::FP128TyID:
6244 addFloat(ElemOffset, ElemTy, 128);
6246 case llvm::Type::PointerTyID:
6247 if (ElemOffset % 64 == 0) {
6249 Elems.push_back(ElemTy);
6259 // Check if Ty is a usable substitute for the coercion type.
6260 bool isUsableType(llvm::StructType *Ty) const {
6261 return llvm::makeArrayRef(Elems) == Ty->elements();
6264 // Get the coercion type as a literal struct type.
6265 llvm::Type *getType() const {
6266 if (Elems.size() == 1)
6267 return Elems.front();
6269 return llvm::StructType::get(Context, Elems);
6273 } // end anonymous namespace
6276 SparcV9ABIInfo::classifyType(QualType Ty, unsigned SizeLimit) const {
6277 if (Ty->isVoidType())
6278 return ABIArgInfo::getIgnore();
6280 uint64_t Size = getContext().getTypeSize(Ty);
6282 // Anything too big to fit in registers is passed with an explicit indirect
6283 // pointer / sret pointer.
6284 if (Size > SizeLimit)
6285 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
6287 // Treat an enum type as its underlying type.
6288 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6289 Ty = EnumTy->getDecl()->getIntegerType();
6291 // Integer types smaller than a register are extended.
6292 if (Size < 64 && Ty->isIntegerType())
6293 return ABIArgInfo::getExtend();
6295 // Other non-aggregates go in registers.
6296 if (!isAggregateTypeForABI(Ty))
6297 return ABIArgInfo::getDirect();
6299 // If a C++ object has either a non-trivial copy constructor or a non-trivial
6300 // destructor, it is passed with an explicit indirect pointer / sret pointer.
6301 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
6302 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
6304 // This is a small aggregate type that should be passed in registers.
6305 // Build a coercion type from the LLVM struct type.
6306 llvm::StructType *StrTy = dyn_cast<llvm::StructType>(CGT.ConvertType(Ty));
6308 return ABIArgInfo::getDirect();
6310 CoerceBuilder CB(getVMContext(), getDataLayout());
6311 CB.addStruct(0, StrTy);
6312 CB.pad(llvm::RoundUpToAlignment(CB.DL.getTypeSizeInBits(StrTy), 64));
6314 // Try to use the original type for coercion.
6315 llvm::Type *CoerceTy = CB.isUsableType(StrTy) ? StrTy : CB.getType();
6318 return ABIArgInfo::getDirectInReg(CoerceTy);
6320 return ABIArgInfo::getDirect(CoerceTy);
6323 llvm::Value *SparcV9ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
6324 CodeGenFunction &CGF) const {
6325 ABIArgInfo AI = classifyType(Ty, 16 * 8);
6326 llvm::Type *ArgTy = CGT.ConvertType(Ty);
6327 if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
6328 AI.setCoerceToType(ArgTy);
6330 llvm::Type *BPP = CGF.Int8PtrPtrTy;
6331 CGBuilderTy &Builder = CGF.Builder;
6332 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap");
6333 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur");
6334 llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
6335 llvm::Value *ArgAddr;
6338 switch (AI.getKind()) {
6339 case ABIArgInfo::Expand:
6340 case ABIArgInfo::InAlloca:
6341 llvm_unreachable("Unsupported ABI kind for va_arg");
6343 case ABIArgInfo::Extend:
6346 .CreateConstGEP1_32(Addr, 8 - getDataLayout().getTypeAllocSize(ArgTy),
6350 case ABIArgInfo::Direct:
6351 Stride = getDataLayout().getTypeAllocSize(AI.getCoerceToType());
6355 case ABIArgInfo::Indirect:
6357 ArgAddr = Builder.CreateBitCast(Addr,
6358 llvm::PointerType::getUnqual(ArgPtrTy),
6360 ArgAddr = Builder.CreateLoad(ArgAddr, "indirect.arg");
6363 case ABIArgInfo::Ignore:
6364 return llvm::UndefValue::get(ArgPtrTy);
6368 Addr = Builder.CreateConstGEP1_32(Addr, Stride, "ap.next");
6369 Builder.CreateStore(Addr, VAListAddrAsBPP);
6371 return Builder.CreatePointerCast(ArgAddr, ArgPtrTy, "arg.addr");
6374 void SparcV9ABIInfo::computeInfo(CGFunctionInfo &FI) const {
6375 FI.getReturnInfo() = classifyType(FI.getReturnType(), 32 * 8);
6376 for (auto &I : FI.arguments())
6377 I.info = classifyType(I.type, 16 * 8);
6381 class SparcV9TargetCodeGenInfo : public TargetCodeGenInfo {
6383 SparcV9TargetCodeGenInfo(CodeGenTypes &CGT)
6384 : TargetCodeGenInfo(new SparcV9ABIInfo(CGT)) {}
6386 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
6390 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
6391 llvm::Value *Address) const override;
6393 } // end anonymous namespace
6396 SparcV9TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
6397 llvm::Value *Address) const {
6398 // This is calculated from the LLVM and GCC tables and verified
6399 // against gcc output. AFAIK all ABIs use the same encoding.
6401 CodeGen::CGBuilderTy &Builder = CGF.Builder;
6403 llvm::IntegerType *i8 = CGF.Int8Ty;
6404 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
6405 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
6407 // 0-31: the 8-byte general-purpose registers
6408 AssignToArrayRange(Builder, Address, Eight8, 0, 31);
6410 // 32-63: f0-31, the 4-byte floating-point registers
6411 AssignToArrayRange(Builder, Address, Four8, 32, 63);
6421 AssignToArrayRange(Builder, Address, Eight8, 64, 71);
6423 // 72-87: d0-15, the 8-byte floating-point registers
6424 AssignToArrayRange(Builder, Address, Eight8, 72, 87);
6430 //===----------------------------------------------------------------------===//
6431 // XCore ABI Implementation
6432 //===----------------------------------------------------------------------===//
6436 /// A SmallStringEnc instance is used to build up the TypeString by passing
6437 /// it by reference between functions that append to it.
6438 typedef llvm::SmallString<128> SmallStringEnc;
6440 /// TypeStringCache caches the meta encodings of Types.
6442 /// The reason for caching TypeStrings is two fold:
6443 /// 1. To cache a type's encoding for later uses;
6444 /// 2. As a means to break recursive member type inclusion.
6446 /// A cache Entry can have a Status of:
6447 /// NonRecursive: The type encoding is not recursive;
6448 /// Recursive: The type encoding is recursive;
6449 /// Incomplete: An incomplete TypeString;
6450 /// IncompleteUsed: An incomplete TypeString that has been used in a
6451 /// Recursive type encoding.
6453 /// A NonRecursive entry will have all of its sub-members expanded as fully
6454 /// as possible. Whilst it may contain types which are recursive, the type
6455 /// itself is not recursive and thus its encoding may be safely used whenever
6456 /// the type is encountered.
6458 /// A Recursive entry will have all of its sub-members expanded as fully as
6459 /// possible. The type itself is recursive and it may contain other types which
6460 /// are recursive. The Recursive encoding must not be used during the expansion
6461 /// of a recursive type's recursive branch. For simplicity the code uses
6462 /// IncompleteCount to reject all usage of Recursive encodings for member types.
6464 /// An Incomplete entry is always a RecordType and only encodes its
6465 /// identifier e.g. "s(S){}". Incomplete 'StubEnc' entries are ephemeral and
6466 /// are placed into the cache during type expansion as a means to identify and
6467 /// handle recursive inclusion of types as sub-members. If there is recursion
6468 /// the entry becomes IncompleteUsed.
6470 /// During the expansion of a RecordType's members:
6472 /// If the cache contains a NonRecursive encoding for the member type, the
6473 /// cached encoding is used;
6475 /// If the cache contains a Recursive encoding for the member type, the
6476 /// cached encoding is 'Swapped' out, as it may be incorrect, and...
6478 /// If the member is a RecordType, an Incomplete encoding is placed into the
6479 /// cache to break potential recursive inclusion of itself as a sub-member;
6481 /// Once a member RecordType has been expanded, its temporary incomplete
6482 /// entry is removed from the cache. If a Recursive encoding was swapped out
6483 /// it is swapped back in;
6485 /// If an incomplete entry is used to expand a sub-member, the incomplete
6486 /// entry is marked as IncompleteUsed. The cache keeps count of how many
6487 /// IncompleteUsed entries it currently contains in IncompleteUsedCount;
6489 /// If a member's encoding is found to be a NonRecursive or Recursive viz:
6490 /// IncompleteUsedCount==0, the member's encoding is added to the cache.
6491 /// Else the member is part of a recursive type and thus the recursion has
6492 /// been exited too soon for the encoding to be correct for the member.
6494 class TypeStringCache {
6495 enum Status {NonRecursive, Recursive, Incomplete, IncompleteUsed};
6497 std::string Str; // The encoded TypeString for the type.
6498 enum Status State; // Information about the encoding in 'Str'.
6499 std::string Swapped; // A temporary place holder for a Recursive encoding
6500 // during the expansion of RecordType's members.
6502 std::map<const IdentifierInfo *, struct Entry> Map;
6503 unsigned IncompleteCount; // Number of Incomplete entries in the Map.
6504 unsigned IncompleteUsedCount; // Number of IncompleteUsed entries in the Map.
6506 TypeStringCache() : IncompleteCount(0), IncompleteUsedCount(0) {};
6507 void addIncomplete(const IdentifierInfo *ID, std::string StubEnc);
6508 bool removeIncomplete(const IdentifierInfo *ID);
6509 void addIfComplete(const IdentifierInfo *ID, StringRef Str,
6511 StringRef lookupStr(const IdentifierInfo *ID);
6514 /// TypeString encodings for enum & union fields must be order.
6515 /// FieldEncoding is a helper for this ordering process.
6516 class FieldEncoding {
6520 FieldEncoding(bool b, SmallStringEnc &e) : HasName(b), Enc(e.c_str()) {};
6521 StringRef str() {return Enc.c_str();};
6522 bool operator<(const FieldEncoding &rhs) const {
6523 if (HasName != rhs.HasName) return HasName;
6524 return Enc < rhs.Enc;
6528 class XCoreABIInfo : public DefaultABIInfo {
6530 XCoreABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
6531 llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
6532 CodeGenFunction &CGF) const override;
6535 class XCoreTargetCodeGenInfo : public TargetCodeGenInfo {
6536 mutable TypeStringCache TSC;
6538 XCoreTargetCodeGenInfo(CodeGenTypes &CGT)
6539 :TargetCodeGenInfo(new XCoreABIInfo(CGT)) {}
6540 void emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
6541 CodeGen::CodeGenModule &M) const override;
6544 } // End anonymous namespace.
6546 llvm::Value *XCoreABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
6547 CodeGenFunction &CGF) const {
6548 CGBuilderTy &Builder = CGF.Builder;
6551 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr,
6553 llvm::Value *AP = Builder.CreateLoad(VAListAddrAsBPP);
6555 // Handle the argument.
6556 ABIArgInfo AI = classifyArgumentType(Ty);
6557 llvm::Type *ArgTy = CGT.ConvertType(Ty);
6558 if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
6559 AI.setCoerceToType(ArgTy);
6560 llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
6562 uint64_t ArgSize = 0;
6563 switch (AI.getKind()) {
6564 case ABIArgInfo::Expand:
6565 case ABIArgInfo::InAlloca:
6566 llvm_unreachable("Unsupported ABI kind for va_arg");
6567 case ABIArgInfo::Ignore:
6568 Val = llvm::UndefValue::get(ArgPtrTy);
6571 case ABIArgInfo::Extend:
6572 case ABIArgInfo::Direct:
6573 Val = Builder.CreatePointerCast(AP, ArgPtrTy);
6574 ArgSize = getDataLayout().getTypeAllocSize(AI.getCoerceToType());
6578 case ABIArgInfo::Indirect:
6579 llvm::Value *ArgAddr;
6580 ArgAddr = Builder.CreateBitCast(AP, llvm::PointerType::getUnqual(ArgPtrTy));
6581 ArgAddr = Builder.CreateLoad(ArgAddr);
6582 Val = Builder.CreatePointerCast(ArgAddr, ArgPtrTy);
6587 // Increment the VAList.
6589 llvm::Value *APN = Builder.CreateConstGEP1_32(AP, ArgSize);
6590 Builder.CreateStore(APN, VAListAddrAsBPP);
6595 /// During the expansion of a RecordType, an incomplete TypeString is placed
6596 /// into the cache as a means to identify and break recursion.
6597 /// If there is a Recursive encoding in the cache, it is swapped out and will
6598 /// be reinserted by removeIncomplete().
6599 /// All other types of encoding should have been used rather than arriving here.
6600 void TypeStringCache::addIncomplete(const IdentifierInfo *ID,
6601 std::string StubEnc) {
6605 assert( (E.Str.empty() || E.State == Recursive) &&
6606 "Incorrectly use of addIncomplete");
6607 assert(!StubEnc.empty() && "Passing an empty string to addIncomplete()");
6608 E.Swapped.swap(E.Str); // swap out the Recursive
6609 E.Str.swap(StubEnc);
6610 E.State = Incomplete;
6614 /// Once the RecordType has been expanded, the temporary incomplete TypeString
6615 /// must be removed from the cache.
6616 /// If a Recursive was swapped out by addIncomplete(), it will be replaced.
6617 /// Returns true if the RecordType was defined recursively.
6618 bool TypeStringCache::removeIncomplete(const IdentifierInfo *ID) {
6621 auto I = Map.find(ID);
6622 assert(I != Map.end() && "Entry not present");
6623 Entry &E = I->second;
6624 assert( (E.State == Incomplete ||
6625 E.State == IncompleteUsed) &&
6626 "Entry must be an incomplete type");
6627 bool IsRecursive = false;
6628 if (E.State == IncompleteUsed) {
6629 // We made use of our Incomplete encoding, thus we are recursive.
6631 --IncompleteUsedCount;
6633 if (E.Swapped.empty())
6636 // Swap the Recursive back.
6637 E.Swapped.swap(E.Str);
6639 E.State = Recursive;
6645 /// Add the encoded TypeString to the cache only if it is NonRecursive or
6646 /// Recursive (viz: all sub-members were expanded as fully as possible).
6647 void TypeStringCache::addIfComplete(const IdentifierInfo *ID, StringRef Str,
6649 if (!ID || IncompleteUsedCount)
6650 return; // No key or it is is an incomplete sub-type so don't add.
6652 if (IsRecursive && !E.Str.empty()) {
6653 assert(E.State==Recursive && E.Str.size() == Str.size() &&
6654 "This is not the same Recursive entry");
6655 // The parent container was not recursive after all, so we could have used
6656 // this Recursive sub-member entry after all, but we assumed the worse when
6657 // we started viz: IncompleteCount!=0.
6660 assert(E.Str.empty() && "Entry already present");
6662 E.State = IsRecursive? Recursive : NonRecursive;
6665 /// Return a cached TypeString encoding for the ID. If there isn't one, or we
6666 /// are recursively expanding a type (IncompleteCount != 0) and the cached
6667 /// encoding is Recursive, return an empty StringRef.
6668 StringRef TypeStringCache::lookupStr(const IdentifierInfo *ID) {
6670 return StringRef(); // We have no key.
6671 auto I = Map.find(ID);
6673 return StringRef(); // We have no encoding.
6674 Entry &E = I->second;
6675 if (E.State == Recursive && IncompleteCount)
6676 return StringRef(); // We don't use Recursive encodings for member types.
6678 if (E.State == Incomplete) {
6679 // The incomplete type is being used to break out of recursion.
6680 E.State = IncompleteUsed;
6681 ++IncompleteUsedCount;
6683 return E.Str.c_str();
6686 /// The XCore ABI includes a type information section that communicates symbol
6687 /// type information to the linker. The linker uses this information to verify
6688 /// safety/correctness of things such as array bound and pointers et al.
6689 /// The ABI only requires C (and XC) language modules to emit TypeStrings.
6690 /// This type information (TypeString) is emitted into meta data for all global
6691 /// symbols: definitions, declarations, functions & variables.
6693 /// The TypeString carries type, qualifier, name, size & value details.
6694 /// Please see 'Tools Development Guide' section 2.16.2 for format details:
6695 /// <https://www.xmos.com/download/public/Tools-Development-Guide%28X9114A%29.pdf>
6696 /// The output is tested by test/CodeGen/xcore-stringtype.c.
6698 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
6699 CodeGen::CodeGenModule &CGM, TypeStringCache &TSC);
6701 /// XCore uses emitTargetMD to emit TypeString metadata for global symbols.
6702 void XCoreTargetCodeGenInfo::emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
6703 CodeGen::CodeGenModule &CGM) const {
6705 if (getTypeString(Enc, D, CGM, TSC)) {
6706 llvm::LLVMContext &Ctx = CGM.getModule().getContext();
6707 llvm::SmallVector<llvm::Metadata *, 2> MDVals;
6708 MDVals.push_back(llvm::ConstantAsMetadata::get(GV));
6709 MDVals.push_back(llvm::MDString::get(Ctx, Enc.str()));
6710 llvm::NamedMDNode *MD =
6711 CGM.getModule().getOrInsertNamedMetadata("xcore.typestrings");
6712 MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
6716 static bool appendType(SmallStringEnc &Enc, QualType QType,
6717 const CodeGen::CodeGenModule &CGM,
6718 TypeStringCache &TSC);
6720 /// Helper function for appendRecordType().
6721 /// Builds a SmallVector containing the encoded field types in declaration order.
6722 static bool extractFieldType(SmallVectorImpl<FieldEncoding> &FE,
6723 const RecordDecl *RD,
6724 const CodeGen::CodeGenModule &CGM,
6725 TypeStringCache &TSC) {
6726 for (const auto *Field : RD->fields()) {
6729 Enc += Field->getName();
6731 if (Field->isBitField()) {
6733 llvm::raw_svector_ostream OS(Enc);
6735 OS << Field->getBitWidthValue(CGM.getContext());
6739 if (!appendType(Enc, Field->getType(), CGM, TSC))
6741 if (Field->isBitField())
6744 FE.push_back(FieldEncoding(!Field->getName().empty(), Enc));
6749 /// Appends structure and union types to Enc and adds encoding to cache.
6750 /// Recursively calls appendType (via extractFieldType) for each field.
6751 /// Union types have their fields ordered according to the ABI.
6752 static bool appendRecordType(SmallStringEnc &Enc, const RecordType *RT,
6753 const CodeGen::CodeGenModule &CGM,
6754 TypeStringCache &TSC, const IdentifierInfo *ID) {
6755 // Append the cached TypeString if we have one.
6756 StringRef TypeString = TSC.lookupStr(ID);
6757 if (!TypeString.empty()) {
6762 // Start to emit an incomplete TypeString.
6763 size_t Start = Enc.size();
6764 Enc += (RT->isUnionType()? 'u' : 's');
6767 Enc += ID->getName();
6770 // We collect all encoded fields and order as necessary.
6771 bool IsRecursive = false;
6772 const RecordDecl *RD = RT->getDecl()->getDefinition();
6773 if (RD && !RD->field_empty()) {
6774 // An incomplete TypeString stub is placed in the cache for this RecordType
6775 // so that recursive calls to this RecordType will use it whilst building a
6776 // complete TypeString for this RecordType.
6777 SmallVector<FieldEncoding, 16> FE;
6778 std::string StubEnc(Enc.substr(Start).str());
6779 StubEnc += '}'; // StubEnc now holds a valid incomplete TypeString.
6780 TSC.addIncomplete(ID, std::move(StubEnc));
6781 if (!extractFieldType(FE, RD, CGM, TSC)) {
6782 (void) TSC.removeIncomplete(ID);
6785 IsRecursive = TSC.removeIncomplete(ID);
6786 // The ABI requires unions to be sorted but not structures.
6787 // See FieldEncoding::operator< for sort algorithm.
6788 if (RT->isUnionType())
6789 std::sort(FE.begin(), FE.end());
6790 // We can now complete the TypeString.
6791 unsigned E = FE.size();
6792 for (unsigned I = 0; I != E; ++I) {
6799 TSC.addIfComplete(ID, Enc.substr(Start), IsRecursive);
6803 /// Appends enum types to Enc and adds the encoding to the cache.
6804 static bool appendEnumType(SmallStringEnc &Enc, const EnumType *ET,
6805 TypeStringCache &TSC,
6806 const IdentifierInfo *ID) {
6807 // Append the cached TypeString if we have one.
6808 StringRef TypeString = TSC.lookupStr(ID);
6809 if (!TypeString.empty()) {
6814 size_t Start = Enc.size();
6817 Enc += ID->getName();
6820 // We collect all encoded enumerations and order them alphanumerically.
6821 if (const EnumDecl *ED = ET->getDecl()->getDefinition()) {
6822 SmallVector<FieldEncoding, 16> FE;
6823 for (auto I = ED->enumerator_begin(), E = ED->enumerator_end(); I != E;
6825 SmallStringEnc EnumEnc;
6827 EnumEnc += I->getName();
6829 I->getInitVal().toString(EnumEnc);
6831 FE.push_back(FieldEncoding(!I->getName().empty(), EnumEnc));
6833 std::sort(FE.begin(), FE.end());
6834 unsigned E = FE.size();
6835 for (unsigned I = 0; I != E; ++I) {
6842 TSC.addIfComplete(ID, Enc.substr(Start), false);
6846 /// Appends type's qualifier to Enc.
6847 /// This is done prior to appending the type's encoding.
6848 static void appendQualifier(SmallStringEnc &Enc, QualType QT) {
6849 // Qualifiers are emitted in alphabetical order.
6850 static const char *Table[] = {"","c:","r:","cr:","v:","cv:","rv:","crv:"};
6852 if (QT.isConstQualified())
6854 if (QT.isRestrictQualified())
6856 if (QT.isVolatileQualified())
6858 Enc += Table[Lookup];
6861 /// Appends built-in types to Enc.
6862 static bool appendBuiltinType(SmallStringEnc &Enc, const BuiltinType *BT) {
6863 const char *EncType;
6864 switch (BT->getKind()) {
6865 case BuiltinType::Void:
6868 case BuiltinType::Bool:
6871 case BuiltinType::Char_U:
6874 case BuiltinType::UChar:
6877 case BuiltinType::SChar:
6880 case BuiltinType::UShort:
6883 case BuiltinType::Short:
6886 case BuiltinType::UInt:
6889 case BuiltinType::Int:
6892 case BuiltinType::ULong:
6895 case BuiltinType::Long:
6898 case BuiltinType::ULongLong:
6901 case BuiltinType::LongLong:
6904 case BuiltinType::Float:
6907 case BuiltinType::Double:
6910 case BuiltinType::LongDouble:
6920 /// Appends a pointer encoding to Enc before calling appendType for the pointee.
6921 static bool appendPointerType(SmallStringEnc &Enc, const PointerType *PT,
6922 const CodeGen::CodeGenModule &CGM,
6923 TypeStringCache &TSC) {
6925 if (!appendType(Enc, PT->getPointeeType(), CGM, TSC))
6931 /// Appends array encoding to Enc before calling appendType for the element.
6932 static bool appendArrayType(SmallStringEnc &Enc, QualType QT,
6933 const ArrayType *AT,
6934 const CodeGen::CodeGenModule &CGM,
6935 TypeStringCache &TSC, StringRef NoSizeEnc) {
6936 if (AT->getSizeModifier() != ArrayType::Normal)
6939 if (const ConstantArrayType *CAT = dyn_cast<ConstantArrayType>(AT))
6940 CAT->getSize().toStringUnsigned(Enc);
6942 Enc += NoSizeEnc; // Global arrays use "*", otherwise it is "".
6944 // The Qualifiers should be attached to the type rather than the array.
6945 appendQualifier(Enc, QT);
6946 if (!appendType(Enc, AT->getElementType(), CGM, TSC))
6952 /// Appends a function encoding to Enc, calling appendType for the return type
6953 /// and the arguments.
6954 static bool appendFunctionType(SmallStringEnc &Enc, const FunctionType *FT,
6955 const CodeGen::CodeGenModule &CGM,
6956 TypeStringCache &TSC) {
6958 if (!appendType(Enc, FT->getReturnType(), CGM, TSC))
6961 if (const FunctionProtoType *FPT = FT->getAs<FunctionProtoType>()) {
6962 // N.B. we are only interested in the adjusted param types.
6963 auto I = FPT->param_type_begin();
6964 auto E = FPT->param_type_end();
6967 if (!appendType(Enc, *I, CGM, TSC))
6973 if (FPT->isVariadic())
6976 if (FPT->isVariadic())
6986 /// Handles the type's qualifier before dispatching a call to handle specific
6988 static bool appendType(SmallStringEnc &Enc, QualType QType,
6989 const CodeGen::CodeGenModule &CGM,
6990 TypeStringCache &TSC) {
6992 QualType QT = QType.getCanonicalType();
6994 if (const ArrayType *AT = QT->getAsArrayTypeUnsafe())
6995 // The Qualifiers should be attached to the type rather than the array.
6996 // Thus we don't call appendQualifier() here.
6997 return appendArrayType(Enc, QT, AT, CGM, TSC, "");
6999 appendQualifier(Enc, QT);
7001 if (const BuiltinType *BT = QT->getAs<BuiltinType>())
7002 return appendBuiltinType(Enc, BT);
7004 if (const PointerType *PT = QT->getAs<PointerType>())
7005 return appendPointerType(Enc, PT, CGM, TSC);
7007 if (const EnumType *ET = QT->getAs<EnumType>())
7008 return appendEnumType(Enc, ET, TSC, QT.getBaseTypeIdentifier());
7010 if (const RecordType *RT = QT->getAsStructureType())
7011 return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
7013 if (const RecordType *RT = QT->getAsUnionType())
7014 return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
7016 if (const FunctionType *FT = QT->getAs<FunctionType>())
7017 return appendFunctionType(Enc, FT, CGM, TSC);
7022 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
7023 CodeGen::CodeGenModule &CGM, TypeStringCache &TSC) {
7027 if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) {
7028 if (FD->getLanguageLinkage() != CLanguageLinkage)
7030 return appendType(Enc, FD->getType(), CGM, TSC);
7033 if (const VarDecl *VD = dyn_cast<VarDecl>(D)) {
7034 if (VD->getLanguageLinkage() != CLanguageLinkage)
7036 QualType QT = VD->getType().getCanonicalType();
7037 if (const ArrayType *AT = QT->getAsArrayTypeUnsafe()) {
7038 // Global ArrayTypes are given a size of '*' if the size is unknown.
7039 // The Qualifiers should be attached to the type rather than the array.
7040 // Thus we don't call appendQualifier() here.
7041 return appendArrayType(Enc, QT, AT, CGM, TSC, "*");
7043 return appendType(Enc, QT, CGM, TSC);
7049 //===----------------------------------------------------------------------===//
7051 //===----------------------------------------------------------------------===//
7053 const llvm::Triple &CodeGenModule::getTriple() const {
7054 return getTarget().getTriple();
7057 bool CodeGenModule::supportsCOMDAT() const {
7058 return !getTriple().isOSBinFormatMachO();
7061 const TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() {
7062 if (TheTargetCodeGenInfo)
7063 return *TheTargetCodeGenInfo;
7065 const llvm::Triple &Triple = getTarget().getTriple();
7066 switch (Triple.getArch()) {
7068 return *(TheTargetCodeGenInfo = new DefaultTargetCodeGenInfo(Types));
7070 case llvm::Triple::le32:
7071 return *(TheTargetCodeGenInfo = new PNaClTargetCodeGenInfo(Types));
7072 case llvm::Triple::mips:
7073 case llvm::Triple::mipsel:
7074 return *(TheTargetCodeGenInfo = new MIPSTargetCodeGenInfo(Types, true));
7076 case llvm::Triple::mips64:
7077 case llvm::Triple::mips64el:
7078 return *(TheTargetCodeGenInfo = new MIPSTargetCodeGenInfo(Types, false));
7080 case llvm::Triple::aarch64:
7081 case llvm::Triple::aarch64_be: {
7082 AArch64ABIInfo::ABIKind Kind = AArch64ABIInfo::AAPCS;
7083 if (getTarget().getABI() == "darwinpcs")
7084 Kind = AArch64ABIInfo::DarwinPCS;
7086 return *(TheTargetCodeGenInfo = new AArch64TargetCodeGenInfo(Types, Kind));
7089 case llvm::Triple::arm:
7090 case llvm::Triple::armeb:
7091 case llvm::Triple::thumb:
7092 case llvm::Triple::thumbeb:
7094 if (Triple.getOS() == llvm::Triple::Win32) {
7095 TheTargetCodeGenInfo =
7096 new WindowsARMTargetCodeGenInfo(Types, ARMABIInfo::AAPCS_VFP);
7097 return *TheTargetCodeGenInfo;
7100 ARMABIInfo::ABIKind Kind = ARMABIInfo::AAPCS;
7101 if (getTarget().getABI() == "apcs-gnu")
7102 Kind = ARMABIInfo::APCS;
7103 else if (CodeGenOpts.FloatABI == "hard" ||
7104 (CodeGenOpts.FloatABI != "soft" &&
7105 Triple.getEnvironment() == llvm::Triple::GNUEABIHF))
7106 Kind = ARMABIInfo::AAPCS_VFP;
7108 return *(TheTargetCodeGenInfo = new ARMTargetCodeGenInfo(Types, Kind));
7111 case llvm::Triple::ppc:
7112 return *(TheTargetCodeGenInfo = new PPC32TargetCodeGenInfo(Types));
7113 case llvm::Triple::ppc64:
7114 if (Triple.isOSBinFormatELF()) {
7115 PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv1;
7116 if (getTarget().getABI() == "elfv2")
7117 Kind = PPC64_SVR4_ABIInfo::ELFv2;
7118 bool HasQPX = getTarget().getABI() == "elfv1-qpx";
7120 return *(TheTargetCodeGenInfo =
7121 new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX));
7123 return *(TheTargetCodeGenInfo = new PPC64TargetCodeGenInfo(Types));
7124 case llvm::Triple::ppc64le: {
7125 assert(Triple.isOSBinFormatELF() && "PPC64 LE non-ELF not supported!");
7126 PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv2;
7127 if (getTarget().getABI() == "elfv1" || getTarget().getABI() == "elfv1-qpx")
7128 Kind = PPC64_SVR4_ABIInfo::ELFv1;
7129 bool HasQPX = getTarget().getABI() == "elfv1-qpx";
7131 return *(TheTargetCodeGenInfo =
7132 new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX));
7135 case llvm::Triple::nvptx:
7136 case llvm::Triple::nvptx64:
7137 return *(TheTargetCodeGenInfo = new NVPTXTargetCodeGenInfo(Types));
7139 case llvm::Triple::msp430:
7140 return *(TheTargetCodeGenInfo = new MSP430TargetCodeGenInfo(Types));
7142 case llvm::Triple::systemz: {
7143 bool HasVector = getTarget().getABI() == "vector";
7144 return *(TheTargetCodeGenInfo = new SystemZTargetCodeGenInfo(Types,
7148 case llvm::Triple::tce:
7149 return *(TheTargetCodeGenInfo = new TCETargetCodeGenInfo(Types));
7151 case llvm::Triple::x86: {
7152 bool IsDarwinVectorABI = Triple.isOSDarwin();
7153 bool IsSmallStructInRegABI =
7154 X86_32TargetCodeGenInfo::isStructReturnInRegABI(Triple, CodeGenOpts);
7155 bool IsWin32FloatStructABI = Triple.isOSWindows() && !Triple.isOSCygMing();
7157 if (Triple.getOS() == llvm::Triple::Win32) {
7158 return *(TheTargetCodeGenInfo =
7159 new WinX86_32TargetCodeGenInfo(Types,
7160 IsDarwinVectorABI, IsSmallStructInRegABI,
7161 IsWin32FloatStructABI,
7162 CodeGenOpts.NumRegisterParameters));
7164 return *(TheTargetCodeGenInfo =
7165 new X86_32TargetCodeGenInfo(Types,
7166 IsDarwinVectorABI, IsSmallStructInRegABI,
7167 IsWin32FloatStructABI,
7168 CodeGenOpts.NumRegisterParameters));
7172 case llvm::Triple::x86_64: {
7173 switch (Triple.getOS()) {
7174 case llvm::Triple::Win32:
7175 return *(TheTargetCodeGenInfo = new WinX86_64TargetCodeGenInfo(Types));
7176 case llvm::Triple::PS4:
7177 return *(TheTargetCodeGenInfo = new PS4TargetCodeGenInfo(Types));
7179 return *(TheTargetCodeGenInfo = new X86_64TargetCodeGenInfo(Types));
7182 case llvm::Triple::hexagon:
7183 return *(TheTargetCodeGenInfo = new HexagonTargetCodeGenInfo(Types));
7184 case llvm::Triple::r600:
7185 return *(TheTargetCodeGenInfo = new AMDGPUTargetCodeGenInfo(Types));
7186 case llvm::Triple::amdgcn:
7187 return *(TheTargetCodeGenInfo = new AMDGPUTargetCodeGenInfo(Types));
7188 case llvm::Triple::sparcv9:
7189 return *(TheTargetCodeGenInfo = new SparcV9TargetCodeGenInfo(Types));
7190 case llvm::Triple::xcore:
7191 return *(TheTargetCodeGenInfo = new XCoreTargetCodeGenInfo(Types));