1 /*===---- avx512vldqintrin.h - AVX512VL and AVX512DQ intrinsics ---------------------------===
3 * Permission is hereby granted, free of charge, to any person obtaining a copy
4 * of this software and associated documentation files (the "Software"), to deal
5 * in the Software without restriction, including without limitation the rights
6 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
7 * copies of the Software, and to permit persons to whom the Software is
8 * furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
16 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
18 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 *===-----------------------------------------------------------------------===
25 #error "Never use <avx512vldqintrin.h> directly; include <immintrin.h> instead."
28 #ifndef __AVX512VLDQINTRIN_H
29 #define __AVX512VLDQINTRIN_H
31 /* Define the default attributes for the functions in this file. */
32 #define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__))
34 static __inline__ __m256i __DEFAULT_FN_ATTRS
35 _mm256_mullo_epi64 (__m256i __A, __m256i __B) {
36 return (__m256i) ((__v4di) __A * (__v4di) __B);
39 static __inline__ __m256i __DEFAULT_FN_ATTRS
40 _mm256_mask_mullo_epi64 (__m256i __W, __mmask8 __U, __m256i __A, __m256i __B) {
41 return (__m256i) __builtin_ia32_pmullq256_mask ((__v4di) __A,
47 static __inline__ __m256i __DEFAULT_FN_ATTRS
48 _mm256_maskz_mullo_epi64 (__mmask8 __U, __m256i __A, __m256i __B) {
49 return (__m256i) __builtin_ia32_pmullq256_mask ((__v4di) __A,
52 _mm256_setzero_si256 (),
56 static __inline__ __m128i __DEFAULT_FN_ATTRS
57 _mm_mullo_epi64 (__m128i __A, __m128i __B) {
58 return (__m128i) ((__v2di) __A * (__v2di) __B);
61 static __inline__ __m128i __DEFAULT_FN_ATTRS
62 _mm_mask_mullo_epi64 (__m128i __W, __mmask8 __U, __m128i __A, __m128i __B) {
63 return (__m128i) __builtin_ia32_pmullq128_mask ((__v2di) __A,
69 static __inline__ __m128i __DEFAULT_FN_ATTRS
70 _mm_maskz_mullo_epi64 (__mmask8 __U, __m128i __A, __m128i __B) {
71 return (__m128i) __builtin_ia32_pmullq128_mask ((__v2di) __A,
78 static __inline__ __m256d __DEFAULT_FN_ATTRS
79 _mm256_mask_andnot_pd (__m256d __W, __mmask8 __U, __m256d __A, __m256d __B) {
80 return (__m256d) __builtin_ia32_andnpd256_mask ((__v4df) __A,
86 static __inline__ __m256d __DEFAULT_FN_ATTRS
87 _mm256_maskz_andnot_pd (__mmask8 __U, __m256d __A, __m256d __B) {
88 return (__m256d) __builtin_ia32_andnpd256_mask ((__v4df) __A,
95 static __inline__ __m128d __DEFAULT_FN_ATTRS
96 _mm_mask_andnot_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
97 return (__m128d) __builtin_ia32_andnpd128_mask ((__v2df) __A,
103 static __inline__ __m128d __DEFAULT_FN_ATTRS
104 _mm_maskz_andnot_pd (__mmask8 __U, __m128d __A, __m128d __B) {
105 return (__m128d) __builtin_ia32_andnpd128_mask ((__v2df) __A,
112 static __inline__ __m256 __DEFAULT_FN_ATTRS
113 _mm256_mask_andnot_ps (__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
114 return (__m256) __builtin_ia32_andnps256_mask ((__v8sf) __A,
120 static __inline__ __m256 __DEFAULT_FN_ATTRS
121 _mm256_maskz_andnot_ps (__mmask8 __U, __m256 __A, __m256 __B) {
122 return (__m256) __builtin_ia32_andnps256_mask ((__v8sf) __A,
125 _mm256_setzero_ps (),
129 static __inline__ __m128 __DEFAULT_FN_ATTRS
130 _mm_mask_andnot_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
131 return (__m128) __builtin_ia32_andnps128_mask ((__v4sf) __A,
137 static __inline__ __m128 __DEFAULT_FN_ATTRS
138 _mm_maskz_andnot_ps (__mmask8 __U, __m128 __A, __m128 __B) {
139 return (__m128) __builtin_ia32_andnps128_mask ((__v4sf) __A,
146 static __inline__ __m256d __DEFAULT_FN_ATTRS
147 _mm256_mask_and_pd (__m256d __W, __mmask8 __U, __m256d __A, __m256d __B) {
148 return (__m256d) __builtin_ia32_andpd256_mask ((__v4df) __A,
154 static __inline__ __m256d __DEFAULT_FN_ATTRS
155 _mm256_maskz_and_pd (__mmask8 __U, __m256d __A, __m256d __B) {
156 return (__m256d) __builtin_ia32_andpd256_mask ((__v4df) __A,
159 _mm256_setzero_pd (),
163 static __inline__ __m128d __DEFAULT_FN_ATTRS
164 _mm_mask_and_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
165 return (__m128d) __builtin_ia32_andpd128_mask ((__v2df) __A,
171 static __inline__ __m128d __DEFAULT_FN_ATTRS
172 _mm_maskz_and_pd (__mmask8 __U, __m128d __A, __m128d __B) {
173 return (__m128d) __builtin_ia32_andpd128_mask ((__v2df) __A,
180 static __inline__ __m256 __DEFAULT_FN_ATTRS
181 _mm256_mask_and_ps (__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
182 return (__m256) __builtin_ia32_andps256_mask ((__v8sf) __A,
188 static __inline__ __m256 __DEFAULT_FN_ATTRS
189 _mm256_maskz_and_ps (__mmask8 __U, __m256 __A, __m256 __B) {
190 return (__m256) __builtin_ia32_andps256_mask ((__v8sf) __A,
193 _mm256_setzero_ps (),
197 static __inline__ __m128 __DEFAULT_FN_ATTRS
198 _mm_mask_and_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
199 return (__m128) __builtin_ia32_andps128_mask ((__v4sf) __A,
205 static __inline__ __m128 __DEFAULT_FN_ATTRS
206 _mm_maskz_and_ps (__mmask8 __U, __m128 __A, __m128 __B) {
207 return (__m128) __builtin_ia32_andps128_mask ((__v4sf) __A,
214 static __inline__ __m256d __DEFAULT_FN_ATTRS
215 _mm256_mask_xor_pd (__m256d __W, __mmask8 __U, __m256d __A,
217 return (__m256d) __builtin_ia32_xorpd256_mask ((__v4df) __A,
223 static __inline__ __m256d __DEFAULT_FN_ATTRS
224 _mm256_maskz_xor_pd (__mmask8 __U, __m256d __A, __m256d __B) {
225 return (__m256d) __builtin_ia32_xorpd256_mask ((__v4df) __A,
228 _mm256_setzero_pd (),
232 static __inline__ __m128d __DEFAULT_FN_ATTRS
233 _mm_mask_xor_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
234 return (__m128d) __builtin_ia32_xorpd128_mask ((__v2df) __A,
240 static __inline__ __m128d __DEFAULT_FN_ATTRS
241 _mm_maskz_xor_pd (__mmask8 __U, __m128d __A, __m128d __B) {
242 return (__m128d) __builtin_ia32_xorpd128_mask ((__v2df) __A,
249 static __inline__ __m256 __DEFAULT_FN_ATTRS
250 _mm256_mask_xor_ps (__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
251 return (__m256) __builtin_ia32_xorps256_mask ((__v8sf) __A,
257 static __inline__ __m256 __DEFAULT_FN_ATTRS
258 _mm256_maskz_xor_ps (__mmask8 __U, __m256 __A, __m256 __B) {
259 return (__m256) __builtin_ia32_xorps256_mask ((__v8sf) __A,
262 _mm256_setzero_ps (),
266 static __inline__ __m128 __DEFAULT_FN_ATTRS
267 _mm_mask_xor_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
268 return (__m128) __builtin_ia32_xorps128_mask ((__v4sf) __A,
274 static __inline__ __m128 __DEFAULT_FN_ATTRS
275 _mm_maskz_xor_ps (__mmask8 __U, __m128 __A, __m128 __B) {
276 return (__m128) __builtin_ia32_xorps128_mask ((__v4sf) __A,
283 static __inline__ __m256d __DEFAULT_FN_ATTRS
284 _mm256_mask_or_pd (__m256d __W, __mmask8 __U, __m256d __A, __m256d __B) {
285 return (__m256d) __builtin_ia32_orpd256_mask ((__v4df) __A,
291 static __inline__ __m256d __DEFAULT_FN_ATTRS
292 _mm256_maskz_or_pd (__mmask8 __U, __m256d __A, __m256d __B) {
293 return (__m256d) __builtin_ia32_orpd256_mask ((__v4df) __A,
296 _mm256_setzero_pd (),
300 static __inline__ __m128d __DEFAULT_FN_ATTRS
301 _mm_mask_or_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
302 return (__m128d) __builtin_ia32_orpd128_mask ((__v2df) __A,
308 static __inline__ __m128d __DEFAULT_FN_ATTRS
309 _mm_maskz_or_pd (__mmask8 __U, __m128d __A, __m128d __B) {
310 return (__m128d) __builtin_ia32_orpd128_mask ((__v2df) __A,
317 static __inline__ __m256 __DEFAULT_FN_ATTRS
318 _mm256_mask_or_ps (__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
319 return (__m256) __builtin_ia32_orps256_mask ((__v8sf) __A,
325 static __inline__ __m256 __DEFAULT_FN_ATTRS
326 _mm256_maskz_or_ps (__mmask8 __U, __m256 __A, __m256 __B) {
327 return (__m256) __builtin_ia32_orps256_mask ((__v8sf) __A,
330 _mm256_setzero_ps (),
334 static __inline__ __m128 __DEFAULT_FN_ATTRS
335 _mm_mask_or_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
336 return (__m128) __builtin_ia32_orps128_mask ((__v4sf) __A,
342 static __inline__ __m128 __DEFAULT_FN_ATTRS
343 _mm_maskz_or_ps (__mmask8 __U, __m128 __A, __m128 __B) {
344 return (__m128) __builtin_ia32_orps128_mask ((__v4sf) __A,
351 #undef __DEFAULT_FN_ATTRS