1 /*===------------- avx512vlvbmi2intrin.h - VBMI2 intrinsics -----------------===
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 *===-----------------------------------------------------------------------===
25 #error "Never use <avx512vlvbmi2intrin.h> directly; include <immintrin.h> instead."
28 #ifndef __AVX512VLVBMI2INTRIN_H
29 #define __AVX512VLVBMI2INTRIN_H
31 /* Define the default attributes for the functions in this file. */
32 #define __DEFAULT_FN_ATTRS128 __attribute__((__always_inline__, __nodebug__, __target__("avx512vl,avx512vbmi2"), __min_vector_width__(128)))
33 #define __DEFAULT_FN_ATTRS256 __attribute__((__always_inline__, __nodebug__, __target__("avx512vl,avx512vbmi2"), __min_vector_width__(256)))
35 static __inline__ __m128i __DEFAULT_FN_ATTRS128
36 _mm_mask_compress_epi16(__m128i __S, __mmask8 __U, __m128i __D)
38 return (__m128i) __builtin_ia32_compresshi128_mask ((__v8hi) __D,
43 static __inline__ __m128i __DEFAULT_FN_ATTRS128
44 _mm_maskz_compress_epi16(__mmask8 __U, __m128i __D)
46 return (__m128i) __builtin_ia32_compresshi128_mask ((__v8hi) __D,
47 (__v8hi) _mm_setzero_si128(),
51 static __inline__ __m128i __DEFAULT_FN_ATTRS128
52 _mm_mask_compress_epi8(__m128i __S, __mmask16 __U, __m128i __D)
54 return (__m128i) __builtin_ia32_compressqi128_mask ((__v16qi) __D,
59 static __inline__ __m128i __DEFAULT_FN_ATTRS128
60 _mm_maskz_compress_epi8(__mmask16 __U, __m128i __D)
62 return (__m128i) __builtin_ia32_compressqi128_mask ((__v16qi) __D,
63 (__v16qi) _mm_setzero_si128(),
67 static __inline__ void __DEFAULT_FN_ATTRS128
68 _mm_mask_compressstoreu_epi16(void *__P, __mmask8 __U, __m128i __D)
70 __builtin_ia32_compressstorehi128_mask ((__v8hi *) __P, (__v8hi) __D,
74 static __inline__ void __DEFAULT_FN_ATTRS128
75 _mm_mask_compressstoreu_epi8(void *__P, __mmask16 __U, __m128i __D)
77 __builtin_ia32_compressstoreqi128_mask ((__v16qi *) __P, (__v16qi) __D,
81 static __inline__ __m128i __DEFAULT_FN_ATTRS128
82 _mm_mask_expand_epi16(__m128i __S, __mmask8 __U, __m128i __D)
84 return (__m128i) __builtin_ia32_expandhi128_mask ((__v8hi) __D,
89 static __inline__ __m128i __DEFAULT_FN_ATTRS128
90 _mm_maskz_expand_epi16(__mmask8 __U, __m128i __D)
92 return (__m128i) __builtin_ia32_expandhi128_mask ((__v8hi) __D,
93 (__v8hi) _mm_setzero_si128(),
97 static __inline__ __m128i __DEFAULT_FN_ATTRS128
98 _mm_mask_expand_epi8(__m128i __S, __mmask16 __U, __m128i __D)
100 return (__m128i) __builtin_ia32_expandqi128_mask ((__v16qi) __D,
105 static __inline__ __m128i __DEFAULT_FN_ATTRS128
106 _mm_maskz_expand_epi8(__mmask16 __U, __m128i __D)
108 return (__m128i) __builtin_ia32_expandqi128_mask ((__v16qi) __D,
109 (__v16qi) _mm_setzero_si128(),
113 static __inline__ __m128i __DEFAULT_FN_ATTRS128
114 _mm_mask_expandloadu_epi16(__m128i __S, __mmask8 __U, void const *__P)
116 return (__m128i) __builtin_ia32_expandloadhi128_mask ((const __v8hi *)__P,
121 static __inline__ __m128i __DEFAULT_FN_ATTRS128
122 _mm_maskz_expandloadu_epi16(__mmask8 __U, void const *__P)
124 return (__m128i) __builtin_ia32_expandloadhi128_mask ((const __v8hi *)__P,
125 (__v8hi) _mm_setzero_si128(),
129 static __inline__ __m128i __DEFAULT_FN_ATTRS128
130 _mm_mask_expandloadu_epi8(__m128i __S, __mmask16 __U, void const *__P)
132 return (__m128i) __builtin_ia32_expandloadqi128_mask ((const __v16qi *)__P,
137 static __inline__ __m128i __DEFAULT_FN_ATTRS128
138 _mm_maskz_expandloadu_epi8(__mmask16 __U, void const *__P)
140 return (__m128i) __builtin_ia32_expandloadqi128_mask ((const __v16qi *)__P,
141 (__v16qi) _mm_setzero_si128(),
145 static __inline__ __m256i __DEFAULT_FN_ATTRS256
146 _mm256_mask_compress_epi16(__m256i __S, __mmask16 __U, __m256i __D)
148 return (__m256i) __builtin_ia32_compresshi256_mask ((__v16hi) __D,
153 static __inline__ __m256i __DEFAULT_FN_ATTRS256
154 _mm256_maskz_compress_epi16(__mmask16 __U, __m256i __D)
156 return (__m256i) __builtin_ia32_compresshi256_mask ((__v16hi) __D,
157 (__v16hi) _mm256_setzero_si256(),
161 static __inline__ __m256i __DEFAULT_FN_ATTRS256
162 _mm256_mask_compress_epi8(__m256i __S, __mmask32 __U, __m256i __D)
164 return (__m256i) __builtin_ia32_compressqi256_mask ((__v32qi) __D,
169 static __inline__ __m256i __DEFAULT_FN_ATTRS256
170 _mm256_maskz_compress_epi8(__mmask32 __U, __m256i __D)
172 return (__m256i) __builtin_ia32_compressqi256_mask ((__v32qi) __D,
173 (__v32qi) _mm256_setzero_si256(),
177 static __inline__ void __DEFAULT_FN_ATTRS256
178 _mm256_mask_compressstoreu_epi16(void *__P, __mmask16 __U, __m256i __D)
180 __builtin_ia32_compressstorehi256_mask ((__v16hi *) __P, (__v16hi) __D,
184 static __inline__ void __DEFAULT_FN_ATTRS256
185 _mm256_mask_compressstoreu_epi8(void *__P, __mmask32 __U, __m256i __D)
187 __builtin_ia32_compressstoreqi256_mask ((__v32qi *) __P, (__v32qi) __D,
191 static __inline__ __m256i __DEFAULT_FN_ATTRS256
192 _mm256_mask_expand_epi16(__m256i __S, __mmask16 __U, __m256i __D)
194 return (__m256i) __builtin_ia32_expandhi256_mask ((__v16hi) __D,
199 static __inline__ __m256i __DEFAULT_FN_ATTRS256
200 _mm256_maskz_expand_epi16(__mmask16 __U, __m256i __D)
202 return (__m256i) __builtin_ia32_expandhi256_mask ((__v16hi) __D,
203 (__v16hi) _mm256_setzero_si256(),
207 static __inline__ __m256i __DEFAULT_FN_ATTRS256
208 _mm256_mask_expand_epi8(__m256i __S, __mmask32 __U, __m256i __D)
210 return (__m256i) __builtin_ia32_expandqi256_mask ((__v32qi) __D,
215 static __inline__ __m256i __DEFAULT_FN_ATTRS256
216 _mm256_maskz_expand_epi8(__mmask32 __U, __m256i __D)
218 return (__m256i) __builtin_ia32_expandqi256_mask ((__v32qi) __D,
219 (__v32qi) _mm256_setzero_si256(),
223 static __inline__ __m256i __DEFAULT_FN_ATTRS256
224 _mm256_mask_expandloadu_epi16(__m256i __S, __mmask16 __U, void const *__P)
226 return (__m256i) __builtin_ia32_expandloadhi256_mask ((const __v16hi *)__P,
231 static __inline__ __m256i __DEFAULT_FN_ATTRS256
232 _mm256_maskz_expandloadu_epi16(__mmask16 __U, void const *__P)
234 return (__m256i) __builtin_ia32_expandloadhi256_mask ((const __v16hi *)__P,
235 (__v16hi) _mm256_setzero_si256(),
239 static __inline__ __m256i __DEFAULT_FN_ATTRS256
240 _mm256_mask_expandloadu_epi8(__m256i __S, __mmask32 __U, void const *__P)
242 return (__m256i) __builtin_ia32_expandloadqi256_mask ((const __v32qi *)__P,
247 static __inline__ __m256i __DEFAULT_FN_ATTRS256
248 _mm256_maskz_expandloadu_epi8(__mmask32 __U, void const *__P)
250 return (__m256i) __builtin_ia32_expandloadqi256_mask ((const __v32qi *)__P,
251 (__v32qi) _mm256_setzero_si256(),
255 #define _mm256_shldi_epi64(A, B, I) \
256 (__m256i)__builtin_ia32_vpshldq256((__v4di)(__m256i)(A), \
257 (__v4di)(__m256i)(B), (int)(I))
259 #define _mm256_mask_shldi_epi64(S, U, A, B, I) \
260 (__m256i)__builtin_ia32_selectq_256((__mmask8)(U), \
261 (__v4di)_mm256_shldi_epi64((A), (B), (I)), \
262 (__v4di)(__m256i)(S))
264 #define _mm256_maskz_shldi_epi64(U, A, B, I) \
265 (__m256i)__builtin_ia32_selectq_256((__mmask8)(U), \
266 (__v4di)_mm256_shldi_epi64((A), (B), (I)), \
267 (__v4di)_mm256_setzero_si256())
269 #define _mm_shldi_epi64(A, B, I) \
270 (__m128i)__builtin_ia32_vpshldq128((__v2di)(__m128i)(A), \
271 (__v2di)(__m128i)(B), (int)(I))
273 #define _mm_mask_shldi_epi64(S, U, A, B, I) \
274 (__m128i)__builtin_ia32_selectq_128((__mmask8)(U), \
275 (__v2di)_mm_shldi_epi64((A), (B), (I)), \
276 (__v2di)(__m128i)(S))
278 #define _mm_maskz_shldi_epi64(U, A, B, I) \
279 (__m128i)__builtin_ia32_selectq_128((__mmask8)(U), \
280 (__v2di)_mm_shldi_epi64((A), (B), (I)), \
281 (__v2di)_mm_setzero_si128())
283 #define _mm256_shldi_epi32(A, B, I) \
284 (__m256i)__builtin_ia32_vpshldd256((__v8si)(__m256i)(A), \
285 (__v8si)(__m256i)(B), (int)(I))
287 #define _mm256_mask_shldi_epi32(S, U, A, B, I) \
288 (__m256i)__builtin_ia32_selectd_256((__mmask8)(U), \
289 (__v8si)_mm256_shldi_epi32((A), (B), (I)), \
290 (__v8si)(__m256i)(S))
292 #define _mm256_maskz_shldi_epi32(U, A, B, I) \
293 (__m256i)__builtin_ia32_selectd_256((__mmask8)(U), \
294 (__v8si)_mm256_shldi_epi32((A), (B), (I)), \
295 (__v8si)_mm256_setzero_si256())
297 #define _mm_shldi_epi32(A, B, I) \
298 (__m128i)__builtin_ia32_vpshldd128((__v4si)(__m128i)(A), \
299 (__v4si)(__m128i)(B), (int)(I))
301 #define _mm_mask_shldi_epi32(S, U, A, B, I) \
302 (__m128i)__builtin_ia32_selectd_128((__mmask8)(U), \
303 (__v4si)_mm_shldi_epi32((A), (B), (I)), \
304 (__v4si)(__m128i)(S))
306 #define _mm_maskz_shldi_epi32(U, A, B, I) \
307 (__m128i)__builtin_ia32_selectd_128((__mmask8)(U), \
308 (__v4si)_mm_shldi_epi32((A), (B), (I)), \
309 (__v4si)_mm_setzero_si128())
311 #define _mm256_shldi_epi16(A, B, I) \
312 (__m256i)__builtin_ia32_vpshldw256((__v16hi)(__m256i)(A), \
313 (__v16hi)(__m256i)(B), (int)(I))
315 #define _mm256_mask_shldi_epi16(S, U, A, B, I) \
316 (__m256i)__builtin_ia32_selectw_256((__mmask16)(U), \
317 (__v16hi)_mm256_shldi_epi16((A), (B), (I)), \
318 (__v16hi)(__m256i)(S))
320 #define _mm256_maskz_shldi_epi16(U, A, B, I) \
321 (__m256i)__builtin_ia32_selectw_256((__mmask16)(U), \
322 (__v16hi)_mm256_shldi_epi16((A), (B), (I)), \
323 (__v16hi)_mm256_setzero_si256())
325 #define _mm_shldi_epi16(A, B, I) \
326 (__m128i)__builtin_ia32_vpshldw128((__v8hi)(__m128i)(A), \
327 (__v8hi)(__m128i)(B), (int)(I))
329 #define _mm_mask_shldi_epi16(S, U, A, B, I) \
330 (__m128i)__builtin_ia32_selectw_128((__mmask8)(U), \
331 (__v8hi)_mm_shldi_epi16((A), (B), (I)), \
332 (__v8hi)(__m128i)(S))
334 #define _mm_maskz_shldi_epi16(U, A, B, I) \
335 (__m128i)__builtin_ia32_selectw_128((__mmask8)(U), \
336 (__v8hi)_mm_shldi_epi16((A), (B), (I)), \
337 (__v8hi)_mm_setzero_si128())
339 #define _mm256_shrdi_epi64(A, B, I) \
340 (__m256i)__builtin_ia32_vpshrdq256((__v4di)(__m256i)(A), \
341 (__v4di)(__m256i)(B), (int)(I))
343 #define _mm256_mask_shrdi_epi64(S, U, A, B, I) \
344 (__m256i)__builtin_ia32_selectq_256((__mmask8)(U), \
345 (__v4di)_mm256_shrdi_epi64((A), (B), (I)), \
346 (__v4di)(__m256i)(S))
348 #define _mm256_maskz_shrdi_epi64(U, A, B, I) \
349 (__m256i)__builtin_ia32_selectq_256((__mmask8)(U), \
350 (__v4di)_mm256_shrdi_epi64((A), (B), (I)), \
351 (__v4di)_mm256_setzero_si256())
353 #define _mm_shrdi_epi64(A, B, I) \
354 (__m128i)__builtin_ia32_vpshrdq128((__v2di)(__m128i)(A), \
355 (__v2di)(__m128i)(B), (int)(I))
357 #define _mm_mask_shrdi_epi64(S, U, A, B, I) \
358 (__m128i)__builtin_ia32_selectq_128((__mmask8)(U), \
359 (__v2di)_mm_shrdi_epi64((A), (B), (I)), \
360 (__v2di)(__m128i)(S))
362 #define _mm_maskz_shrdi_epi64(U, A, B, I) \
363 (__m128i)__builtin_ia32_selectq_128((__mmask8)(U), \
364 (__v2di)_mm_shrdi_epi64((A), (B), (I)), \
365 (__v2di)_mm_setzero_si128())
367 #define _mm256_shrdi_epi32(A, B, I) \
368 (__m256i)__builtin_ia32_vpshrdd256((__v8si)(__m256i)(A), \
369 (__v8si)(__m256i)(B), (int)(I))
371 #define _mm256_mask_shrdi_epi32(S, U, A, B, I) \
372 (__m256i)__builtin_ia32_selectd_256((__mmask8)(U), \
373 (__v8si)_mm256_shrdi_epi32((A), (B), (I)), \
374 (__v8si)(__m256i)(S))
376 #define _mm256_maskz_shrdi_epi32(U, A, B, I) \
377 (__m256i)__builtin_ia32_selectd_256((__mmask8)(U), \
378 (__v8si)_mm256_shrdi_epi32((A), (B), (I)), \
379 (__v8si)_mm256_setzero_si256())
381 #define _mm_shrdi_epi32(A, B, I) \
382 (__m128i)__builtin_ia32_vpshrdd128((__v4si)(__m128i)(A), \
383 (__v4si)(__m128i)(B), (int)(I))
385 #define _mm_mask_shrdi_epi32(S, U, A, B, I) \
386 (__m128i)__builtin_ia32_selectd_128((__mmask8)(U), \
387 (__v4si)_mm_shrdi_epi32((A), (B), (I)), \
388 (__v4si)(__m128i)(S))
390 #define _mm_maskz_shrdi_epi32(U, A, B, I) \
391 (__m128i)__builtin_ia32_selectd_128((__mmask8)(U), \
392 (__v4si)_mm_shrdi_epi32((A), (B), (I)), \
393 (__v4si)_mm_setzero_si128())
395 #define _mm256_shrdi_epi16(A, B, I) \
396 (__m256i)__builtin_ia32_vpshrdw256((__v16hi)(__m256i)(A), \
397 (__v16hi)(__m256i)(B), (int)(I))
399 #define _mm256_mask_shrdi_epi16(S, U, A, B, I) \
400 (__m256i)__builtin_ia32_selectw_256((__mmask16)(U), \
401 (__v16hi)_mm256_shrdi_epi16((A), (B), (I)), \
402 (__v16hi)(__m256i)(S))
404 #define _mm256_maskz_shrdi_epi16(U, A, B, I) \
405 (__m256i)__builtin_ia32_selectw_256((__mmask16)(U), \
406 (__v16hi)_mm256_shrdi_epi16((A), (B), (I)), \
407 (__v16hi)_mm256_setzero_si256())
409 #define _mm_shrdi_epi16(A, B, I) \
410 (__m128i)__builtin_ia32_vpshrdw128((__v8hi)(__m128i)(A), \
411 (__v8hi)(__m128i)(B), (int)(I))
413 #define _mm_mask_shrdi_epi16(S, U, A, B, I) \
414 (__m128i)__builtin_ia32_selectw_128((__mmask8)(U), \
415 (__v8hi)_mm_shrdi_epi16((A), (B), (I)), \
416 (__v8hi)(__m128i)(S))
418 #define _mm_maskz_shrdi_epi16(U, A, B, I) \
419 (__m128i)__builtin_ia32_selectw_128((__mmask8)(U), \
420 (__v8hi)_mm_shrdi_epi16((A), (B), (I)), \
421 (__v8hi)_mm_setzero_si128())
423 static __inline__ __m256i __DEFAULT_FN_ATTRS256
424 _mm256_shldv_epi64(__m256i __A, __m256i __B, __m256i __C)
426 return (__m256i)__builtin_ia32_vpshldvq256((__v4di)__A, (__v4di)__B,
430 static __inline__ __m256i __DEFAULT_FN_ATTRS256
431 _mm256_mask_shldv_epi64(__m256i __A, __mmask8 __U, __m256i __B, __m256i __C)
433 return (__m256i)__builtin_ia32_selectq_256(__U,
434 (__v4di)_mm256_shldv_epi64(__A, __B, __C),
438 static __inline__ __m256i __DEFAULT_FN_ATTRS256
439 _mm256_maskz_shldv_epi64(__mmask8 __U, __m256i __A, __m256i __B, __m256i __C)
441 return (__m256i)__builtin_ia32_selectq_256(__U,
442 (__v4di)_mm256_shldv_epi64(__A, __B, __C),
443 (__v4di)_mm256_setzero_si256());
446 static __inline__ __m128i __DEFAULT_FN_ATTRS128
447 _mm_shldv_epi64(__m128i __A, __m128i __B, __m128i __C)
449 return (__m128i)__builtin_ia32_vpshldvq128((__v2di)__A, (__v2di)__B,
453 static __inline__ __m128i __DEFAULT_FN_ATTRS128
454 _mm_mask_shldv_epi64(__m128i __A, __mmask8 __U, __m128i __B, __m128i __C)
456 return (__m128i)__builtin_ia32_selectq_128(__U,
457 (__v2di)_mm_shldv_epi64(__A, __B, __C),
461 static __inline__ __m128i __DEFAULT_FN_ATTRS128
462 _mm_maskz_shldv_epi64(__mmask8 __U, __m128i __A, __m128i __B, __m128i __C)
464 return (__m128i)__builtin_ia32_selectq_128(__U,
465 (__v2di)_mm_shldv_epi64(__A, __B, __C),
466 (__v2di)_mm_setzero_si128());
469 static __inline__ __m256i __DEFAULT_FN_ATTRS256
470 _mm256_shldv_epi32(__m256i __A, __m256i __B, __m256i __C)
472 return (__m256i)__builtin_ia32_vpshldvd256((__v8si)__A, (__v8si)__B,
476 static __inline__ __m256i __DEFAULT_FN_ATTRS256
477 _mm256_mask_shldv_epi32(__m256i __A, __mmask8 __U, __m256i __B, __m256i __C)
479 return (__m256i)__builtin_ia32_selectd_256(__U,
480 (__v8si)_mm256_shldv_epi32(__A, __B, __C),
484 static __inline__ __m256i __DEFAULT_FN_ATTRS256
485 _mm256_maskz_shldv_epi32(__mmask8 __U, __m256i __A, __m256i __B, __m256i __C)
487 return (__m256i)__builtin_ia32_selectd_256(__U,
488 (__v8si)_mm256_shldv_epi32(__A, __B, __C),
489 (__v8si)_mm256_setzero_si256());
492 static __inline__ __m128i __DEFAULT_FN_ATTRS128
493 _mm_shldv_epi32(__m128i __A, __m128i __B, __m128i __C)
495 return (__m128i)__builtin_ia32_vpshldvd128((__v4si)__A, (__v4si)__B,
499 static __inline__ __m128i __DEFAULT_FN_ATTRS128
500 _mm_mask_shldv_epi32(__m128i __A, __mmask8 __U, __m128i __B, __m128i __C)
502 return (__m128i)__builtin_ia32_selectd_128(__U,
503 (__v4si)_mm_shldv_epi32(__A, __B, __C),
507 static __inline__ __m128i __DEFAULT_FN_ATTRS128
508 _mm_maskz_shldv_epi32(__mmask8 __U, __m128i __A, __m128i __B, __m128i __C)
510 return (__m128i)__builtin_ia32_selectd_128(__U,
511 (__v4si)_mm_shldv_epi32(__A, __B, __C),
512 (__v4si)_mm_setzero_si128());
515 static __inline__ __m256i __DEFAULT_FN_ATTRS256
516 _mm256_shldv_epi16(__m256i __A, __m256i __B, __m256i __C)
518 return (__m256i)__builtin_ia32_vpshldvw256((__v16hi)__A, (__v16hi)__B,
522 static __inline__ __m256i __DEFAULT_FN_ATTRS256
523 _mm256_mask_shldv_epi16(__m256i __A, __mmask16 __U, __m256i __B, __m256i __C)
525 return (__m256i)__builtin_ia32_selectw_256(__U,
526 (__v16hi)_mm256_shldv_epi16(__A, __B, __C),
530 static __inline__ __m256i __DEFAULT_FN_ATTRS256
531 _mm256_maskz_shldv_epi16(__mmask16 __U, __m256i __A, __m256i __B, __m256i __C)
533 return (__m256i)__builtin_ia32_selectw_256(__U,
534 (__v16hi)_mm256_shldv_epi16(__A, __B, __C),
535 (__v16hi)_mm256_setzero_si256());
538 static __inline__ __m128i __DEFAULT_FN_ATTRS128
539 _mm_shldv_epi16(__m128i __A, __m128i __B, __m128i __C)
541 return (__m128i)__builtin_ia32_vpshldvw128((__v8hi)__A, (__v8hi)__B,
545 static __inline__ __m128i __DEFAULT_FN_ATTRS128
546 _mm_mask_shldv_epi16(__m128i __A, __mmask8 __U, __m128i __B, __m128i __C)
548 return (__m128i)__builtin_ia32_selectw_128(__U,
549 (__v8hi)_mm_shldv_epi16(__A, __B, __C),
553 static __inline__ __m128i __DEFAULT_FN_ATTRS128
554 _mm_maskz_shldv_epi16(__mmask8 __U, __m128i __A, __m128i __B, __m128i __C)
556 return (__m128i)__builtin_ia32_selectw_128(__U,
557 (__v8hi)_mm_shldv_epi16(__A, __B, __C),
558 (__v8hi)_mm_setzero_si128());
561 static __inline__ __m256i __DEFAULT_FN_ATTRS256
562 _mm256_shrdv_epi64(__m256i __A, __m256i __B, __m256i __C)
564 return (__m256i)__builtin_ia32_vpshrdvq256((__v4di)__A, (__v4di)__B,
568 static __inline__ __m256i __DEFAULT_FN_ATTRS256
569 _mm256_mask_shrdv_epi64(__m256i __A, __mmask8 __U, __m256i __B, __m256i __C)
571 return (__m256i)__builtin_ia32_selectq_256(__U,
572 (__v4di)_mm256_shrdv_epi64(__A, __B, __C),
576 static __inline__ __m256i __DEFAULT_FN_ATTRS256
577 _mm256_maskz_shrdv_epi64(__mmask8 __U, __m256i __A, __m256i __B, __m256i __C)
579 return (__m256i)__builtin_ia32_selectq_256(__U,
580 (__v4di)_mm256_shrdv_epi64(__A, __B, __C),
581 (__v4di)_mm256_setzero_si256());
584 static __inline__ __m128i __DEFAULT_FN_ATTRS128
585 _mm_shrdv_epi64(__m128i __A, __m128i __B, __m128i __C)
587 return (__m128i)__builtin_ia32_vpshrdvq128((__v2di)__A, (__v2di)__B,
591 static __inline__ __m128i __DEFAULT_FN_ATTRS128
592 _mm_mask_shrdv_epi64(__m128i __A, __mmask8 __U, __m128i __B, __m128i __C)
594 return (__m128i)__builtin_ia32_selectq_128(__U,
595 (__v2di)_mm_shrdv_epi64(__A, __B, __C),
599 static __inline__ __m128i __DEFAULT_FN_ATTRS128
600 _mm_maskz_shrdv_epi64(__mmask8 __U, __m128i __A, __m128i __B, __m128i __C)
602 return (__m128i)__builtin_ia32_selectq_128(__U,
603 (__v2di)_mm_shrdv_epi64(__A, __B, __C),
604 (__v2di)_mm_setzero_si128());
607 static __inline__ __m256i __DEFAULT_FN_ATTRS256
608 _mm256_shrdv_epi32(__m256i __A, __m256i __B, __m256i __C)
610 return (__m256i)__builtin_ia32_vpshrdvd256((__v8si)__A, (__v8si)__B,
614 static __inline__ __m256i __DEFAULT_FN_ATTRS256
615 _mm256_mask_shrdv_epi32(__m256i __A, __mmask8 __U, __m256i __B, __m256i __C)
617 return (__m256i)__builtin_ia32_selectd_256(__U,
618 (__v8si)_mm256_shrdv_epi32(__A, __B, __C),
622 static __inline__ __m256i __DEFAULT_FN_ATTRS256
623 _mm256_maskz_shrdv_epi32(__mmask8 __U, __m256i __A, __m256i __B, __m256i __C)
625 return (__m256i)__builtin_ia32_selectd_256(__U,
626 (__v8si)_mm256_shrdv_epi32(__A, __B, __C),
627 (__v8si)_mm256_setzero_si256());
630 static __inline__ __m128i __DEFAULT_FN_ATTRS128
631 _mm_shrdv_epi32(__m128i __A, __m128i __B, __m128i __C)
633 return (__m128i)__builtin_ia32_vpshrdvd128((__v4si)__A, (__v4si)__B,
637 static __inline__ __m128i __DEFAULT_FN_ATTRS128
638 _mm_mask_shrdv_epi32(__m128i __A, __mmask8 __U, __m128i __B, __m128i __C)
640 return (__m128i)__builtin_ia32_selectd_128(__U,
641 (__v4si)_mm_shrdv_epi32(__A, __B, __C),
645 static __inline__ __m128i __DEFAULT_FN_ATTRS128
646 _mm_maskz_shrdv_epi32(__mmask8 __U, __m128i __A, __m128i __B, __m128i __C)
648 return (__m128i)__builtin_ia32_selectd_128(__U,
649 (__v4si)_mm_shrdv_epi32(__A, __B, __C),
650 (__v4si)_mm_setzero_si128());
653 static __inline__ __m256i __DEFAULT_FN_ATTRS256
654 _mm256_shrdv_epi16(__m256i __A, __m256i __B, __m256i __C)
656 return (__m256i)__builtin_ia32_vpshrdvw256((__v16hi)__A, (__v16hi)__B,
660 static __inline__ __m256i __DEFAULT_FN_ATTRS256
661 _mm256_mask_shrdv_epi16(__m256i __A, __mmask16 __U, __m256i __B, __m256i __C)
663 return (__m256i)__builtin_ia32_selectw_256(__U,
664 (__v16hi)_mm256_shrdv_epi16(__A, __B, __C),
668 static __inline__ __m256i __DEFAULT_FN_ATTRS256
669 _mm256_maskz_shrdv_epi16(__mmask16 __U, __m256i __A, __m256i __B, __m256i __C)
671 return (__m256i)__builtin_ia32_selectw_256(__U,
672 (__v16hi)_mm256_shrdv_epi16(__A, __B, __C),
673 (__v16hi)_mm256_setzero_si256());
676 static __inline__ __m128i __DEFAULT_FN_ATTRS128
677 _mm_shrdv_epi16(__m128i __A, __m128i __B, __m128i __C)
679 return (__m128i)__builtin_ia32_vpshrdvw128((__v8hi)__A, (__v8hi)__B,
683 static __inline__ __m128i __DEFAULT_FN_ATTRS128
684 _mm_mask_shrdv_epi16(__m128i __A, __mmask8 __U, __m128i __B, __m128i __C)
686 return (__m128i)__builtin_ia32_selectw_128(__U,
687 (__v8hi)_mm_shrdv_epi16(__A, __B, __C),
691 static __inline__ __m128i __DEFAULT_FN_ATTRS128
692 _mm_maskz_shrdv_epi16(__mmask8 __U, __m128i __A, __m128i __B, __m128i __C)
694 return (__m128i)__builtin_ia32_selectw_128(__U,
695 (__v8hi)_mm_shrdv_epi16(__A, __B, __C),
696 (__v8hi)_mm_setzero_si128());
700 #undef __DEFAULT_FN_ATTRS128
701 #undef __DEFAULT_FN_ATTRS256