1 /*===------------- avx512vlvbmi2intrin.h - VBMI2 intrinsics -----------------===
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 *===-----------------------------------------------------------------------===
25 #error "Never use <avx512vlvbmi2intrin.h> directly; include <immintrin.h> instead."
28 #ifndef __AVX512VLVBMI2INTRIN_H
29 #define __AVX512VLVBMI2INTRIN_H
31 /* Define the default attributes for the functions in this file. */
32 #define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512vl,avx512vbmi2")))
34 static __inline __m128i __DEFAULT_FN_ATTRS
35 _mm128_setzero_hi(void) {
36 return (__m128i)(__v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 };
39 static __inline__ __m128i __DEFAULT_FN_ATTRS
40 _mm128_mask_compress_epi16(__m128i __S, __mmask8 __U, __m128i __D)
42 return (__m128i) __builtin_ia32_compresshi128_mask ((__v8hi) __D,
47 static __inline__ __m128i __DEFAULT_FN_ATTRS
48 _mm128_maskz_compress_epi16(__mmask8 __U, __m128i __D)
50 return (__m128i) __builtin_ia32_compresshi128_mask ((__v8hi) __D,
51 (__v8hi) _mm128_setzero_hi(),
55 static __inline__ __m128i __DEFAULT_FN_ATTRS
56 _mm128_mask_compress_epi8(__m128i __S, __mmask16 __U, __m128i __D)
58 return (__m128i) __builtin_ia32_compressqi128_mask ((__v16qi) __D,
63 static __inline__ __m128i __DEFAULT_FN_ATTRS
64 _mm128_maskz_compress_epi8(__mmask16 __U, __m128i __D)
66 return (__m128i) __builtin_ia32_compressqi128_mask ((__v16qi) __D,
67 (__v16qi) _mm128_setzero_hi(),
71 static __inline__ void __DEFAULT_FN_ATTRS
72 _mm128_mask_compressstoreu_epi16(void *__P, __mmask8 __U, __m128i __D)
74 __builtin_ia32_compressstorehi128_mask ((__v8hi *) __P, (__v8hi) __D,
78 static __inline__ void __DEFAULT_FN_ATTRS
79 _mm128_mask_compressstoreu_epi8(void *__P, __mmask16 __U, __m128i __D)
81 __builtin_ia32_compressstoreqi128_mask ((__v16qi *) __P, (__v16qi) __D,
85 static __inline__ __m128i __DEFAULT_FN_ATTRS
86 _mm128_mask_expand_epi16(__m128i __S, __mmask8 __U, __m128i __D)
88 return (__m128i) __builtin_ia32_expandhi128_mask ((__v8hi) __D,
93 static __inline__ __m128i __DEFAULT_FN_ATTRS
94 _mm128_maskz_expand_epi16(__mmask8 __U, __m128i __D)
96 return (__m128i) __builtin_ia32_expandhi128_mask ((__v8hi) __D,
97 (__v8hi) _mm128_setzero_hi(),
101 static __inline__ __m128i __DEFAULT_FN_ATTRS
102 _mm128_mask_expand_epi8(__m128i __S, __mmask16 __U, __m128i __D)
104 return (__m128i) __builtin_ia32_expandqi128_mask ((__v16qi) __D,
109 static __inline__ __m128i __DEFAULT_FN_ATTRS
110 _mm128_maskz_expand_epi8(__mmask16 __U, __m128i __D)
112 return (__m128i) __builtin_ia32_expandqi128_mask ((__v16qi) __D,
113 (__v16qi) _mm128_setzero_hi(),
117 static __inline__ __m128i __DEFAULT_FN_ATTRS
118 _mm128_mask_expandloadu_epi16(__m128i __S, __mmask8 __U, void const *__P)
120 return (__m128i) __builtin_ia32_expandloadhi128_mask ((const __v8hi *)__P,
125 static __inline__ __m128i __DEFAULT_FN_ATTRS
126 _mm128_maskz_expandloadu_epi16(__mmask8 __U, void const *__P)
128 return (__m128i) __builtin_ia32_expandloadhi128_mask ((const __v8hi *)__P,
129 (__v8hi) _mm128_setzero_hi(),
133 static __inline__ __m128i __DEFAULT_FN_ATTRS
134 _mm128_mask_expandloadu_epi8(__m128i __S, __mmask16 __U, void const *__P)
136 return (__m128i) __builtin_ia32_expandloadqi128_mask ((const __v16qi *)__P,
141 static __inline__ __m128i __DEFAULT_FN_ATTRS
142 _mm128_maskz_expandloadu_epi8(__mmask16 __U, void const *__P)
144 return (__m128i) __builtin_ia32_expandloadqi128_mask ((const __v16qi *)__P,
145 (__v16qi) _mm128_setzero_hi(),
149 static __inline __m256i __DEFAULT_FN_ATTRS
150 _mm256_setzero_hi(void) {
151 return (__m256i)(__v16hi){ 0, 0, 0, 0, 0, 0, 0, 0,
152 0, 0, 0, 0, 0, 0, 0, 0 };
155 static __inline__ __m256i __DEFAULT_FN_ATTRS
156 _mm256_mask_compress_epi16(__m256i __S, __mmask16 __U, __m256i __D)
158 return (__m256i) __builtin_ia32_compresshi256_mask ((__v16hi) __D,
163 static __inline__ __m256i __DEFAULT_FN_ATTRS
164 _mm256_maskz_compress_epi16(__mmask16 __U, __m256i __D)
166 return (__m256i) __builtin_ia32_compresshi256_mask ((__v16hi) __D,
167 (__v16hi) _mm256_setzero_hi(),
171 static __inline__ __m256i __DEFAULT_FN_ATTRS
172 _mm256_mask_compress_epi8(__m256i __S, __mmask32 __U, __m256i __D)
174 return (__m256i) __builtin_ia32_compressqi256_mask ((__v32qi) __D,
179 static __inline__ __m256i __DEFAULT_FN_ATTRS
180 _mm256_maskz_compress_epi8(__mmask32 __U, __m256i __D)
182 return (__m256i) __builtin_ia32_compressqi256_mask ((__v32qi) __D,
183 (__v32qi) _mm256_setzero_hi(),
187 static __inline__ void __DEFAULT_FN_ATTRS
188 _mm256_mask_compressstoreu_epi16(void *__P, __mmask16 __U, __m256i __D)
190 __builtin_ia32_compressstorehi256_mask ((__v16hi *) __P, (__v16hi) __D,
194 static __inline__ void __DEFAULT_FN_ATTRS
195 _mm256_mask_compressstoreu_epi8(void *__P, __mmask32 __U, __m256i __D)
197 __builtin_ia32_compressstoreqi256_mask ((__v32qi *) __P, (__v32qi) __D,
201 static __inline__ __m256i __DEFAULT_FN_ATTRS
202 _mm256_mask_expand_epi16(__m256i __S, __mmask16 __U, __m256i __D)
204 return (__m256i) __builtin_ia32_expandhi256_mask ((__v16hi) __D,
209 static __inline__ __m256i __DEFAULT_FN_ATTRS
210 _mm256_maskz_expand_epi16(__mmask16 __U, __m256i __D)
212 return (__m256i) __builtin_ia32_expandhi256_mask ((__v16hi) __D,
213 (__v16hi) _mm256_setzero_hi(),
217 static __inline__ __m256i __DEFAULT_FN_ATTRS
218 _mm256_mask_expand_epi8(__m256i __S, __mmask32 __U, __m256i __D)
220 return (__m256i) __builtin_ia32_expandqi256_mask ((__v32qi) __D,
225 static __inline__ __m256i __DEFAULT_FN_ATTRS
226 _mm256_maskz_expand_epi8(__mmask32 __U, __m256i __D)
228 return (__m256i) __builtin_ia32_expandqi256_mask ((__v32qi) __D,
229 (__v32qi) _mm256_setzero_hi(),
233 static __inline__ __m256i __DEFAULT_FN_ATTRS
234 _mm256_mask_expandloadu_epi16(__m256i __S, __mmask16 __U, void const *__P)
236 return (__m256i) __builtin_ia32_expandloadhi256_mask ((const __v16hi *)__P,
241 static __inline__ __m256i __DEFAULT_FN_ATTRS
242 _mm256_maskz_expandloadu_epi16(__mmask16 __U, void const *__P)
244 return (__m256i) __builtin_ia32_expandloadhi256_mask ((const __v16hi *)__P,
245 (__v16hi) _mm256_setzero_hi(),
249 static __inline__ __m256i __DEFAULT_FN_ATTRS
250 _mm256_mask_expandloadu_epi8(__m256i __S, __mmask32 __U, void const *__P)
252 return (__m256i) __builtin_ia32_expandloadqi256_mask ((const __v32qi *)__P,
257 static __inline__ __m256i __DEFAULT_FN_ATTRS
258 _mm256_maskz_expandloadu_epi8(__mmask32 __U, void const *__P)
260 return (__m256i) __builtin_ia32_expandloadqi256_mask ((const __v32qi *)__P,
261 (__v32qi) _mm256_setzero_hi(),
265 #define _mm256_mask_shldi_epi64(S, U, A, B, I) __extension__ ({ \
266 (__m256i)__builtin_ia32_vpshldq256_mask((__v4di)(A), \
272 #define _mm256_maskz_shldi_epi64(U, A, B, I) \
273 _mm256_mask_shldi_epi64(_mm256_setzero_hi(), (U), (A), (B), (I))
275 #define _mm256_shldi_epi64(A, B, I) \
276 _mm256_mask_shldi_epi64(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I))
278 #define _mm128_mask_shldi_epi64(S, U, A, B, I) __extension__ ({ \
279 (__m128i)__builtin_ia32_vpshldq128_mask((__v2di)(A), \
285 #define _mm128_maskz_shldi_epi64(U, A, B, I) \
286 _mm128_mask_shldi_epi64(_mm128_setzero_hi(), (U), (A), (B), (I))
288 #define _mm128_shldi_epi64(A, B, I) \
289 _mm128_mask_shldi_epi64(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I))
291 #define _mm256_mask_shldi_epi32(S, U, A, B, I) __extension__ ({ \
292 (__m256i)__builtin_ia32_vpshldd256_mask((__v8si)(A), \
298 #define _mm256_maskz_shldi_epi32(U, A, B, I) \
299 _mm256_mask_shldi_epi32(_mm256_setzero_hi(), (U), (A), (B), (I))
301 #define _mm256_shldi_epi32(A, B, I) \
302 _mm256_mask_shldi_epi32(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I))
304 #define _mm128_mask_shldi_epi32(S, U, A, B, I) __extension__ ({ \
305 (__m128i)__builtin_ia32_vpshldd128_mask((__v4si)(A), \
311 #define _mm128_maskz_shldi_epi32(U, A, B, I) \
312 _mm128_mask_shldi_epi32(_mm128_setzero_hi(), (U), (A), (B), (I))
314 #define _mm128_shldi_epi32(A, B, I) \
315 _mm128_mask_shldi_epi32(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I))
317 #define _mm256_mask_shldi_epi16(S, U, A, B, I) __extension__ ({ \
318 (__m256i)__builtin_ia32_vpshldw256_mask((__v16hi)(A), \
324 #define _mm256_maskz_shldi_epi16(U, A, B, I) \
325 _mm256_mask_shldi_epi16(_mm256_setzero_hi(), (U), (A), (B), (I))
327 #define _mm256_shldi_epi16(A, B, I) \
328 _mm256_mask_shldi_epi16(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I))
330 #define _mm128_mask_shldi_epi16(S, U, A, B, I) __extension__ ({ \
331 (__m128i)__builtin_ia32_vpshldw128_mask((__v8hi)(A), \
337 #define _mm128_maskz_shldi_epi16(U, A, B, I) \
338 _mm128_mask_shldi_epi16(_mm128_setzero_hi(), (U), (A), (B), (I))
340 #define _mm128_shldi_epi16(A, B, I) \
341 _mm128_mask_shldi_epi16(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I))
343 #define _mm256_mask_shrdi_epi64(S, U, A, B, I) __extension__ ({ \
344 (__m256i)__builtin_ia32_vpshrdq256_mask((__v4di)(A), \
350 #define _mm256_maskz_shrdi_epi64(U, A, B, I) \
351 _mm256_mask_shrdi_epi64(_mm256_setzero_hi(), (U), (A), (B), (I))
353 #define _mm256_shrdi_epi64(A, B, I) \
354 _mm256_mask_shrdi_epi64(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I))
356 #define _mm128_mask_shrdi_epi64(S, U, A, B, I) __extension__ ({ \
357 (__m128i)__builtin_ia32_vpshrdq128_mask((__v2di)(A), \
363 #define _mm128_maskz_shrdi_epi64(U, A, B, I) \
364 _mm128_mask_shrdi_epi64(_mm128_setzero_hi(), (U), (A), (B), (I))
366 #define _mm128_shrdi_epi64(A, B, I) \
367 _mm128_mask_shrdi_epi64(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I))
369 #define _mm256_mask_shrdi_epi32(S, U, A, B, I) __extension__ ({ \
370 (__m256i)__builtin_ia32_vpshrdd256_mask((__v8si)(A), \
376 #define _mm256_maskz_shrdi_epi32(U, A, B, I) \
377 _mm256_mask_shrdi_epi32(_mm256_setzero_hi(), (U), (A), (B), (I))
379 #define _mm256_shrdi_epi32(A, B, I) \
380 _mm256_mask_shrdi_epi32(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I))
382 #define _mm128_mask_shrdi_epi32(S, U, A, B, I) __extension__ ({ \
383 (__m128i)__builtin_ia32_vpshrdd128_mask((__v4si)(A), \
389 #define _mm128_maskz_shrdi_epi32(U, A, B, I) \
390 _mm128_mask_shrdi_epi32(_mm128_setzero_hi(), (U), (A), (B), (I))
392 #define _mm128_shrdi_epi32(A, B, I) \
393 _mm128_mask_shrdi_epi32(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I))
395 #define _mm256_mask_shrdi_epi16(S, U, A, B, I) __extension__ ({ \
396 (__m256i)__builtin_ia32_vpshrdw256_mask((__v16hi)(A), \
402 #define _mm256_maskz_shrdi_epi16(U, A, B, I) \
403 _mm256_mask_shrdi_epi16(_mm256_setzero_hi(), (U), (A), (B), (I))
405 #define _mm256_shrdi_epi16(A, B, I) \
406 _mm256_mask_shrdi_epi16(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I))
408 #define _mm128_mask_shrdi_epi16(S, U, A, B, I) __extension__ ({ \
409 (__m128i)__builtin_ia32_vpshrdw128_mask((__v8hi)(A), \
415 #define _mm128_maskz_shrdi_epi16(U, A, B, I) \
416 _mm128_mask_shrdi_epi16(_mm128_setzero_hi(), (U), (A), (B), (I))
418 #define _mm128_shrdi_epi16(A, B, I) \
419 _mm128_mask_shrdi_epi16(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I))
421 static __inline__ __m256i __DEFAULT_FN_ATTRS
422 _mm256_mask_shldv_epi64(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
424 return (__m256i) __builtin_ia32_vpshldvq256_mask ((__v4di) __S,
430 static __inline__ __m256i __DEFAULT_FN_ATTRS
431 _mm256_maskz_shldv_epi64(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
433 return (__m256i) __builtin_ia32_vpshldvq256_maskz ((__v4di) __S,
439 static __inline__ __m256i __DEFAULT_FN_ATTRS
440 _mm256_shldv_epi64(__m256i __S, __m256i __A, __m256i __B)
442 return (__m256i) __builtin_ia32_vpshldvq256_mask ((__v4di) __S,
448 static __inline__ __m128i __DEFAULT_FN_ATTRS
449 _mm128_mask_shldv_epi64(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
451 return (__m128i) __builtin_ia32_vpshldvq128_mask ((__v2di) __S,
457 static __inline__ __m128i __DEFAULT_FN_ATTRS
458 _mm128_maskz_shldv_epi64(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
460 return (__m128i) __builtin_ia32_vpshldvq128_maskz ((__v2di) __S,
466 static __inline__ __m128i __DEFAULT_FN_ATTRS
467 _mm128_shldv_epi64(__m128i __S, __m128i __A, __m128i __B)
469 return (__m128i) __builtin_ia32_vpshldvq128_mask ((__v2di) __S,
475 static __inline__ __m256i __DEFAULT_FN_ATTRS
476 _mm256_mask_shldv_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
478 return (__m256i) __builtin_ia32_vpshldvd256_mask ((__v8si) __S,
484 static __inline__ __m256i __DEFAULT_FN_ATTRS
485 _mm256_maskz_shldv_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
487 return (__m256i) __builtin_ia32_vpshldvd256_maskz ((__v8si) __S,
493 static __inline__ __m256i __DEFAULT_FN_ATTRS
494 _mm256_shldv_epi32(__m256i __S, __m256i __A, __m256i __B)
496 return (__m256i) __builtin_ia32_vpshldvd256_mask ((__v8si) __S,
502 static __inline__ __m128i __DEFAULT_FN_ATTRS
503 _mm128_mask_shldv_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
505 return (__m128i) __builtin_ia32_vpshldvd128_mask ((__v4si) __S,
511 static __inline__ __m128i __DEFAULT_FN_ATTRS
512 _mm128_maskz_shldv_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
514 return (__m128i) __builtin_ia32_vpshldvd128_maskz ((__v4si) __S,
520 static __inline__ __m128i __DEFAULT_FN_ATTRS
521 _mm128_shldv_epi32(__m128i __S, __m128i __A, __m128i __B)
523 return (__m128i) __builtin_ia32_vpshldvd128_mask ((__v4si) __S,
529 static __inline__ __m256i __DEFAULT_FN_ATTRS
530 _mm256_mask_shldv_epi16(__m256i __S, __mmask16 __U, __m256i __A, __m256i __B)
532 return (__m256i) __builtin_ia32_vpshldvw256_mask ((__v16hi) __S,
538 static __inline__ __m256i __DEFAULT_FN_ATTRS
539 _mm256_maskz_shldv_epi16(__mmask16 __U, __m256i __S, __m256i __A, __m256i __B)
541 return (__m256i) __builtin_ia32_vpshldvw256_maskz ((__v16hi) __S,
547 static __inline__ __m256i __DEFAULT_FN_ATTRS
548 _mm256_shldv_epi16(__m256i __S, __m256i __A, __m256i __B)
550 return (__m256i) __builtin_ia32_vpshldvw256_mask ((__v16hi) __S,
556 static __inline__ __m128i __DEFAULT_FN_ATTRS
557 _mm128_mask_shldv_epi16(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
559 return (__m128i) __builtin_ia32_vpshldvw128_mask ((__v8hi) __S,
565 static __inline__ __m128i __DEFAULT_FN_ATTRS
566 _mm128_maskz_shldv_epi16(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
568 return (__m128i) __builtin_ia32_vpshldvw128_maskz ((__v8hi) __S,
574 static __inline__ __m128i __DEFAULT_FN_ATTRS
575 _mm128_shldv_epi16(__m128i __S, __m128i __A, __m128i __B)
577 return (__m128i) __builtin_ia32_vpshldvw128_mask ((__v8hi) __S,
583 static __inline__ __m256i __DEFAULT_FN_ATTRS
584 _mm256_mask_shrdv_epi64(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
586 return (__m256i) __builtin_ia32_vpshrdvq256_mask ((__v4di) __S,
592 static __inline__ __m256i __DEFAULT_FN_ATTRS
593 _mm256_maskz_shrdv_epi64(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
595 return (__m256i) __builtin_ia32_vpshrdvq256_maskz ((__v4di) __S,
601 static __inline__ __m256i __DEFAULT_FN_ATTRS
602 _mm256_shrdv_epi64(__m256i __S, __m256i __A, __m256i __B)
604 return (__m256i) __builtin_ia32_vpshrdvq256_mask ((__v4di) __S,
610 static __inline__ __m128i __DEFAULT_FN_ATTRS
611 _mm128_mask_shrdv_epi64(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
613 return (__m128i) __builtin_ia32_vpshrdvq128_mask ((__v2di) __S,
619 static __inline__ __m128i __DEFAULT_FN_ATTRS
620 _mm128_maskz_shrdv_epi64(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
622 return (__m128i) __builtin_ia32_vpshrdvq128_maskz ((__v2di) __S,
628 static __inline__ __m128i __DEFAULT_FN_ATTRS
629 _mm128_shrdv_epi64(__m128i __S, __m128i __A, __m128i __B)
631 return (__m128i) __builtin_ia32_vpshrdvq128_mask ((__v2di) __S,
637 static __inline__ __m256i __DEFAULT_FN_ATTRS
638 _mm256_mask_shrdv_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
640 return (__m256i) __builtin_ia32_vpshrdvd256_mask ((__v8si) __S,
646 static __inline__ __m256i __DEFAULT_FN_ATTRS
647 _mm256_maskz_shrdv_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
649 return (__m256i) __builtin_ia32_vpshrdvd256_maskz ((__v8si) __S,
655 static __inline__ __m256i __DEFAULT_FN_ATTRS
656 _mm256_shrdv_epi32(__m256i __S, __m256i __A, __m256i __B)
658 return (__m256i) __builtin_ia32_vpshrdvd256_mask ((__v8si) __S,
664 static __inline__ __m128i __DEFAULT_FN_ATTRS
665 _mm128_mask_shrdv_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
667 return (__m128i) __builtin_ia32_vpshrdvd128_mask ((__v4si) __S,
673 static __inline__ __m128i __DEFAULT_FN_ATTRS
674 _mm128_maskz_shrdv_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
676 return (__m128i) __builtin_ia32_vpshrdvd128_maskz ((__v4si) __S,
682 static __inline__ __m128i __DEFAULT_FN_ATTRS
683 _mm128_shrdv_epi32(__m128i __S, __m128i __A, __m128i __B)
685 return (__m128i) __builtin_ia32_vpshrdvd128_mask ((__v4si) __S,
691 static __inline__ __m256i __DEFAULT_FN_ATTRS
692 _mm256_mask_shrdv_epi16(__m256i __S, __mmask16 __U, __m256i __A, __m256i __B)
694 return (__m256i) __builtin_ia32_vpshrdvw256_mask ((__v16hi) __S,
700 static __inline__ __m256i __DEFAULT_FN_ATTRS
701 _mm256_maskz_shrdv_epi16(__mmask16 __U, __m256i __S, __m256i __A, __m256i __B)
703 return (__m256i) __builtin_ia32_vpshrdvw256_maskz ((__v16hi) __S,
709 static __inline__ __m256i __DEFAULT_FN_ATTRS
710 _mm256_shrdv_epi16(__m256i __S, __m256i __A, __m256i __B)
712 return (__m256i) __builtin_ia32_vpshrdvw256_mask ((__v16hi) __S,
718 static __inline__ __m128i __DEFAULT_FN_ATTRS
719 _mm128_mask_shrdv_epi16(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
721 return (__m128i) __builtin_ia32_vpshrdvw128_mask ((__v8hi) __S,
727 static __inline__ __m128i __DEFAULT_FN_ATTRS
728 _mm128_maskz_shrdv_epi16(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
730 return (__m128i) __builtin_ia32_vpshrdvw128_maskz ((__v8hi) __S,
736 static __inline__ __m128i __DEFAULT_FN_ATTRS
737 _mm128_shrdv_epi16(__m128i __S, __m128i __A, __m128i __B)
739 return (__m128i) __builtin_ia32_vpshrdvw128_mask ((__v8hi) __S,
746 #undef __DEFAULT_FN_ATTRS