1 //===- Chunks.cpp ---------------------------------------------------------===//
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "InputFiles.h"
14 #include "lld/Common/ErrorHandler.h"
15 #include "llvm/ADT/Twine.h"
16 #include "llvm/BinaryFormat/COFF.h"
17 #include "llvm/Object/COFF.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/Endian.h"
20 #include "llvm/Support/raw_ostream.h"
24 using namespace llvm::object;
25 using namespace llvm::support::endian;
26 using namespace llvm::COFF;
27 using llvm::support::ulittle32_t;
32 SectionChunk::SectionChunk(ObjFile *F, const coff_section *H)
33 : Chunk(SectionKind), Repl(this), Header(H), File(F),
34 Relocs(File->getCOFFObj()->getRelocations(Header)) {
35 // Initialize SectionName.
36 File->getCOFFObj()->getSectionName(Header, SectionName);
38 Alignment = Header->getAlignment();
40 // If linker GC is disabled, every chunk starts out alive. If linker GC is
41 // enabled, treat non-comdat sections as roots. Generally optimized object
42 // files will be built with -ffunction-sections or /Gy, so most things worth
43 // stripping will be in a comdat.
44 Live = !Config->DoGC || !isCOMDAT();
47 static void add16(uint8_t *P, int16_t V) { write16le(P, read16le(P) + V); }
48 static void add32(uint8_t *P, int32_t V) { write32le(P, read32le(P) + V); }
49 static void add64(uint8_t *P, int64_t V) { write64le(P, read64le(P) + V); }
50 static void or16(uint8_t *P, uint16_t V) { write16le(P, read16le(P) | V); }
51 static void or32(uint8_t *P, uint32_t V) { write32le(P, read32le(P) | V); }
53 // Verify that given sections are appropriate targets for SECREL
54 // relocations. This check is relaxed because unfortunately debug
55 // sections have section-relative relocations against absolute symbols.
56 static bool checkSecRel(const SectionChunk *Sec, OutputSection *OS) {
59 if (Sec->isCodeView())
61 fatal("SECREL relocation cannot be applied to absolute symbols");
64 static void applySecRel(const SectionChunk *Sec, uint8_t *Off,
65 OutputSection *OS, uint64_t S) {
66 if (!checkSecRel(Sec, OS))
68 uint64_t SecRel = S - OS->getRVA();
69 if (SecRel > UINT32_MAX) {
70 error("overflow in SECREL relocation in section: " + Sec->getSectionName());
76 static void applySecIdx(uint8_t *Off, OutputSection *OS) {
77 // Absolute symbol doesn't have section index, but section index relocation
78 // against absolute symbol should be resolved to one plus the last output
79 // section index. This is required for compatibility with MSVC.
81 add16(Off, OS->SectionIndex);
83 add16(Off, DefinedAbsolute::NumOutputSections + 1);
86 void SectionChunk::applyRelX64(uint8_t *Off, uint16_t Type, OutputSection *OS,
87 uint64_t S, uint64_t P) const {
89 case IMAGE_REL_AMD64_ADDR32: add32(Off, S + Config->ImageBase); break;
90 case IMAGE_REL_AMD64_ADDR64: add64(Off, S + Config->ImageBase); break;
91 case IMAGE_REL_AMD64_ADDR32NB: add32(Off, S); break;
92 case IMAGE_REL_AMD64_REL32: add32(Off, S - P - 4); break;
93 case IMAGE_REL_AMD64_REL32_1: add32(Off, S - P - 5); break;
94 case IMAGE_REL_AMD64_REL32_2: add32(Off, S - P - 6); break;
95 case IMAGE_REL_AMD64_REL32_3: add32(Off, S - P - 7); break;
96 case IMAGE_REL_AMD64_REL32_4: add32(Off, S - P - 8); break;
97 case IMAGE_REL_AMD64_REL32_5: add32(Off, S - P - 9); break;
98 case IMAGE_REL_AMD64_SECTION: applySecIdx(Off, OS); break;
99 case IMAGE_REL_AMD64_SECREL: applySecRel(this, Off, OS, S); break;
101 fatal("unsupported relocation type 0x" + Twine::utohexstr(Type) + " in " +
106 void SectionChunk::applyRelX86(uint8_t *Off, uint16_t Type, OutputSection *OS,
107 uint64_t S, uint64_t P) const {
109 case IMAGE_REL_I386_ABSOLUTE: break;
110 case IMAGE_REL_I386_DIR32: add32(Off, S + Config->ImageBase); break;
111 case IMAGE_REL_I386_DIR32NB: add32(Off, S); break;
112 case IMAGE_REL_I386_REL32: add32(Off, S - P - 4); break;
113 case IMAGE_REL_I386_SECTION: applySecIdx(Off, OS); break;
114 case IMAGE_REL_I386_SECREL: applySecRel(this, Off, OS, S); break;
116 fatal("unsupported relocation type 0x" + Twine::utohexstr(Type) + " in " +
121 static void applyMOV(uint8_t *Off, uint16_t V) {
122 write16le(Off, (read16le(Off) & 0xfbf0) | ((V & 0x800) >> 1) | ((V >> 12) & 0xf));
123 write16le(Off + 2, (read16le(Off + 2) & 0x8f00) | ((V & 0x700) << 4) | (V & 0xff));
126 static uint16_t readMOV(uint8_t *Off) {
127 uint16_t Op1 = read16le(Off);
128 uint16_t Op2 = read16le(Off + 2);
129 return (Op2 & 0x00ff) | ((Op2 >> 4) & 0x0700) | ((Op1 << 1) & 0x0800) |
130 ((Op1 & 0x000f) << 12);
133 void applyMOV32T(uint8_t *Off, uint32_t V) {
134 uint16_t ImmW = readMOV(Off); // read MOVW operand
135 uint16_t ImmT = readMOV(Off + 4); // read MOVT operand
136 uint32_t Imm = ImmW | (ImmT << 16);
137 V += Imm; // add the immediate offset
138 applyMOV(Off, V); // set MOVW operand
139 applyMOV(Off + 4, V >> 16); // set MOVT operand
142 static void applyBranch20T(uint8_t *Off, int32_t V) {
144 fatal("relocation out of range");
145 uint32_t S = V < 0 ? 1 : 0;
146 uint32_t J1 = (V >> 19) & 1;
147 uint32_t J2 = (V >> 18) & 1;
148 or16(Off, (S << 10) | ((V >> 12) & 0x3f));
149 or16(Off + 2, (J1 << 13) | (J2 << 11) | ((V >> 1) & 0x7ff));
152 void applyBranch24T(uint8_t *Off, int32_t V) {
154 fatal("relocation out of range");
155 uint32_t S = V < 0 ? 1 : 0;
156 uint32_t J1 = ((~V >> 23) & 1) ^ S;
157 uint32_t J2 = ((~V >> 22) & 1) ^ S;
158 or16(Off, (S << 10) | ((V >> 12) & 0x3ff));
159 // Clear out the J1 and J2 bits which may be set.
160 write16le(Off + 2, (read16le(Off + 2) & 0xd000) | (J1 << 13) | (J2 << 11) | ((V >> 1) & 0x7ff));
163 void SectionChunk::applyRelARM(uint8_t *Off, uint16_t Type, OutputSection *OS,
164 uint64_t S, uint64_t P) const {
165 // Pointer to thumb code must have the LSB set.
167 if (OS && (OS->Header.Characteristics & IMAGE_SCN_MEM_EXECUTE))
170 case IMAGE_REL_ARM_ADDR32: add32(Off, SX + Config->ImageBase); break;
171 case IMAGE_REL_ARM_ADDR32NB: add32(Off, SX); break;
172 case IMAGE_REL_ARM_MOV32T: applyMOV32T(Off, SX + Config->ImageBase); break;
173 case IMAGE_REL_ARM_BRANCH20T: applyBranch20T(Off, SX - P - 4); break;
174 case IMAGE_REL_ARM_BRANCH24T: applyBranch24T(Off, SX - P - 4); break;
175 case IMAGE_REL_ARM_BLX23T: applyBranch24T(Off, SX - P - 4); break;
176 case IMAGE_REL_ARM_SECTION: applySecIdx(Off, OS); break;
177 case IMAGE_REL_ARM_SECREL: applySecRel(this, Off, OS, S); break;
179 fatal("unsupported relocation type 0x" + Twine::utohexstr(Type) + " in " +
184 // Interpret the existing immediate value as a byte offset to the
185 // target symbol, then update the instruction with the immediate as
186 // the page offset from the current instruction to the target.
187 static void applyArm64Addr(uint8_t *Off, uint64_t S, uint64_t P, int Shift) {
188 uint32_t Orig = read32le(Off);
189 uint64_t Imm = ((Orig >> 29) & 0x3) | ((Orig >> 3) & 0x1FFFFC);
191 Imm = (S >> Shift) - (P >> Shift);
192 uint32_t ImmLo = (Imm & 0x3) << 29;
193 uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
194 uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3);
195 write32le(Off, (Orig & ~Mask) | ImmLo | ImmHi);
198 // Update the immediate field in a AARCH64 ldr, str, and add instruction.
199 // Optionally limit the range of the written immediate by one or more bits
201 static void applyArm64Imm(uint8_t *Off, uint64_t Imm, uint32_t RangeLimit) {
202 uint32_t Orig = read32le(Off);
203 Imm += (Orig >> 10) & 0xFFF;
204 Orig &= ~(0xFFF << 10);
205 write32le(Off, Orig | ((Imm & (0xFFF >> RangeLimit)) << 10));
208 // Add the 12 bit page offset to the existing immediate.
209 // Ldr/str instructions store the opcode immediate scaled
210 // by the load/store size (giving a larger range for larger
211 // loads/stores). The immediate is always (both before and after
212 // fixing up the relocation) stored scaled similarly.
213 // Even if larger loads/stores have a larger range, limit the
214 // effective offset to 12 bit, since it is intended to be a
216 static void applyArm64Ldr(uint8_t *Off, uint64_t Imm) {
217 uint32_t Orig = read32le(Off);
218 uint32_t Size = Orig >> 30;
219 // 0x04000000 indicates SIMD/FP registers
220 // 0x00800000 indicates 128 bit
221 if ((Orig & 0x4800000) == 0x4800000)
223 if ((Imm & ((1 << Size) - 1)) != 0)
224 fatal("misaligned ldr/str offset");
225 applyArm64Imm(Off, Imm >> Size, Size);
228 static void applySecRelLow12A(const SectionChunk *Sec, uint8_t *Off,
229 OutputSection *OS, uint64_t S) {
230 if (checkSecRel(Sec, OS))
231 applyArm64Imm(Off, (S - OS->getRVA()) & 0xfff, 0);
234 static void applySecRelHigh12A(const SectionChunk *Sec, uint8_t *Off,
235 OutputSection *OS, uint64_t S) {
236 if (!checkSecRel(Sec, OS))
238 uint64_t SecRel = (S - OS->getRVA()) >> 12;
239 if (0xfff < SecRel) {
240 error("overflow in SECREL_HIGH12A relocation in section: " +
241 Sec->getSectionName());
244 applyArm64Imm(Off, SecRel & 0xfff, 0);
247 static void applySecRelLdr(const SectionChunk *Sec, uint8_t *Off,
248 OutputSection *OS, uint64_t S) {
249 if (checkSecRel(Sec, OS))
250 applyArm64Ldr(Off, (S - OS->getRVA()) & 0xfff);
253 static void applyArm64Branch26(uint8_t *Off, int64_t V) {
255 fatal("relocation out of range");
256 or32(Off, (V & 0x0FFFFFFC) >> 2);
259 static void applyArm64Branch19(uint8_t *Off, int64_t V) {
261 fatal("relocation out of range");
262 or32(Off, (V & 0x001FFFFC) << 3);
265 static void applyArm64Branch14(uint8_t *Off, int64_t V) {
267 fatal("relocation out of range");
268 or32(Off, (V & 0x0000FFFC) << 3);
271 void SectionChunk::applyRelARM64(uint8_t *Off, uint16_t Type, OutputSection *OS,
272 uint64_t S, uint64_t P) const {
274 case IMAGE_REL_ARM64_PAGEBASE_REL21: applyArm64Addr(Off, S, P, 12); break;
275 case IMAGE_REL_ARM64_REL21: applyArm64Addr(Off, S, P, 0); break;
276 case IMAGE_REL_ARM64_PAGEOFFSET_12A: applyArm64Imm(Off, S & 0xfff, 0); break;
277 case IMAGE_REL_ARM64_PAGEOFFSET_12L: applyArm64Ldr(Off, S & 0xfff); break;
278 case IMAGE_REL_ARM64_BRANCH26: applyArm64Branch26(Off, S - P); break;
279 case IMAGE_REL_ARM64_BRANCH19: applyArm64Branch19(Off, S - P); break;
280 case IMAGE_REL_ARM64_BRANCH14: applyArm64Branch14(Off, S - P); break;
281 case IMAGE_REL_ARM64_ADDR32: add32(Off, S + Config->ImageBase); break;
282 case IMAGE_REL_ARM64_ADDR32NB: add32(Off, S); break;
283 case IMAGE_REL_ARM64_ADDR64: add64(Off, S + Config->ImageBase); break;
284 case IMAGE_REL_ARM64_SECREL: applySecRel(this, Off, OS, S); break;
285 case IMAGE_REL_ARM64_SECREL_LOW12A: applySecRelLow12A(this, Off, OS, S); break;
286 case IMAGE_REL_ARM64_SECREL_HIGH12A: applySecRelHigh12A(this, Off, OS, S); break;
287 case IMAGE_REL_ARM64_SECREL_LOW12L: applySecRelLdr(this, Off, OS, S); break;
288 case IMAGE_REL_ARM64_SECTION: applySecIdx(Off, OS); break;
290 fatal("unsupported relocation type 0x" + Twine::utohexstr(Type) + " in " +
295 void SectionChunk::writeTo(uint8_t *Buf) const {
298 // Copy section contents from source object file to output file.
299 ArrayRef<uint8_t> A = getContents();
301 memcpy(Buf + OutputSectionOff, A.data(), A.size());
303 // Apply relocations.
304 size_t InputSize = getSize();
305 for (const coff_relocation &Rel : Relocs) {
306 // Check for an invalid relocation offset. This check isn't perfect, because
307 // we don't have the relocation size, which is only known after checking the
308 // machine and relocation type. As a result, a relocation may overwrite the
309 // beginning of the following input section.
310 if (Rel.VirtualAddress >= InputSize)
311 fatal("relocation points beyond the end of its parent section");
313 uint8_t *Off = Buf + OutputSectionOff + Rel.VirtualAddress;
315 // Get the output section of the symbol for this relocation. The output
316 // section is needed to compute SECREL and SECTION relocations used in debug
319 dyn_cast_or_null<Defined>(File->getSymbol(Rel.SymbolTableIndex));
321 if (isCodeView() || isDWARF())
323 // Symbols in early discarded sections are represented using null pointers,
324 // so we need to retrieve the name from the object file.
326 check(File->getCOFFObj()->getSymbol(Rel.SymbolTableIndex));
328 File->getCOFFObj()->getSymbolName(Sym, Name);
329 fatal("relocation against symbol in discarded section: " + Name);
331 Chunk *C = Sym->getChunk();
332 OutputSection *OS = C ? C->getOutputSection() : nullptr;
334 // Only absolute and __ImageBase symbols lack an output section. For any
335 // other symbol, this indicates that the chunk was discarded. Normally
336 // relocations against discarded sections are an error. However, debug info
337 // sections are not GC roots and can end up with these kinds of relocations.
338 // Skip these relocations.
339 if (!OS && !isa<DefinedAbsolute>(Sym) && !isa<DefinedSynthetic>(Sym)) {
340 if (isCodeView() || isDWARF())
342 fatal("relocation against symbol in discarded section: " +
345 uint64_t S = Sym->getRVA();
347 // Compute the RVA of the relocation for relative relocations.
348 uint64_t P = RVA + Rel.VirtualAddress;
349 switch (Config->Machine) {
351 applyRelX64(Off, Rel.Type, OS, S, P);
354 applyRelX86(Off, Rel.Type, OS, S, P);
357 applyRelARM(Off, Rel.Type, OS, S, P);
360 applyRelARM64(Off, Rel.Type, OS, S, P);
363 llvm_unreachable("unknown machine type");
368 void SectionChunk::addAssociative(SectionChunk *Child) {
369 AssocChildren.push_back(Child);
372 static uint8_t getBaserelType(const coff_relocation &Rel) {
373 switch (Config->Machine) {
375 if (Rel.Type == IMAGE_REL_AMD64_ADDR64)
376 return IMAGE_REL_BASED_DIR64;
377 return IMAGE_REL_BASED_ABSOLUTE;
379 if (Rel.Type == IMAGE_REL_I386_DIR32)
380 return IMAGE_REL_BASED_HIGHLOW;
381 return IMAGE_REL_BASED_ABSOLUTE;
383 if (Rel.Type == IMAGE_REL_ARM_ADDR32)
384 return IMAGE_REL_BASED_HIGHLOW;
385 if (Rel.Type == IMAGE_REL_ARM_MOV32T)
386 return IMAGE_REL_BASED_ARM_MOV32T;
387 return IMAGE_REL_BASED_ABSOLUTE;
389 if (Rel.Type == IMAGE_REL_ARM64_ADDR64)
390 return IMAGE_REL_BASED_DIR64;
391 return IMAGE_REL_BASED_ABSOLUTE;
393 llvm_unreachable("unknown machine type");
398 // Collect all locations that contain absolute addresses, which need to be
399 // fixed by the loader if load-time relocation is needed.
400 // Only called when base relocation is enabled.
401 void SectionChunk::getBaserels(std::vector<Baserel> *Res) {
402 for (const coff_relocation &Rel : Relocs) {
403 uint8_t Ty = getBaserelType(Rel);
404 if (Ty == IMAGE_REL_BASED_ABSOLUTE)
406 Symbol *Target = File->getSymbol(Rel.SymbolTableIndex);
407 if (!Target || isa<DefinedAbsolute>(Target))
409 Res->emplace_back(RVA + Rel.VirtualAddress, Ty);
413 bool SectionChunk::hasData() const {
414 return !(Header->Characteristics & IMAGE_SCN_CNT_UNINITIALIZED_DATA);
417 uint32_t SectionChunk::getOutputCharacteristics() const {
418 return Header->Characteristics & (PermMask | TypeMask);
421 bool SectionChunk::isCOMDAT() const {
422 return Header->Characteristics & IMAGE_SCN_LNK_COMDAT;
425 void SectionChunk::printDiscardedMessage() const {
426 // Removed by dead-stripping. If it's removed by ICF, ICF already
427 // printed out the name, so don't repeat that here.
428 if (Sym && this == Repl)
429 message("Discarded " + Sym->getName());
432 StringRef SectionChunk::getDebugName() {
434 return Sym->getName();
438 ArrayRef<uint8_t> SectionChunk::getContents() const {
440 File->getCOFFObj()->getSectionContents(Header, A);
444 void SectionChunk::replace(SectionChunk *Other) {
445 Alignment = std::max(Alignment, Other->Alignment);
450 CommonChunk::CommonChunk(const COFFSymbolRef S) : Sym(S) {
451 // Common symbols are aligned on natural boundaries up to 32 bytes.
452 // This is what MSVC link.exe does.
453 Alignment = std::min(uint64_t(32), PowerOf2Ceil(Sym.getValue()));
456 uint32_t CommonChunk::getOutputCharacteristics() const {
457 return IMAGE_SCN_CNT_UNINITIALIZED_DATA | IMAGE_SCN_MEM_READ |
461 void StringChunk::writeTo(uint8_t *Buf) const {
462 memcpy(Buf + OutputSectionOff, Str.data(), Str.size());
465 ImportThunkChunkX64::ImportThunkChunkX64(Defined *S) : ImpSymbol(S) {
466 // Intel Optimization Manual says that all branch targets
467 // should be 16-byte aligned. MSVC linker does this too.
471 void ImportThunkChunkX64::writeTo(uint8_t *Buf) const {
472 memcpy(Buf + OutputSectionOff, ImportThunkX86, sizeof(ImportThunkX86));
473 // The first two bytes is a JMP instruction. Fill its operand.
474 write32le(Buf + OutputSectionOff + 2, ImpSymbol->getRVA() - RVA - getSize());
477 void ImportThunkChunkX86::getBaserels(std::vector<Baserel> *Res) {
478 Res->emplace_back(getRVA() + 2);
481 void ImportThunkChunkX86::writeTo(uint8_t *Buf) const {
482 memcpy(Buf + OutputSectionOff, ImportThunkX86, sizeof(ImportThunkX86));
483 // The first two bytes is a JMP instruction. Fill its operand.
484 write32le(Buf + OutputSectionOff + 2,
485 ImpSymbol->getRVA() + Config->ImageBase);
488 void ImportThunkChunkARM::getBaserels(std::vector<Baserel> *Res) {
489 Res->emplace_back(getRVA(), IMAGE_REL_BASED_ARM_MOV32T);
492 void ImportThunkChunkARM::writeTo(uint8_t *Buf) const {
493 memcpy(Buf + OutputSectionOff, ImportThunkARM, sizeof(ImportThunkARM));
494 // Fix mov.w and mov.t operands.
495 applyMOV32T(Buf + OutputSectionOff, ImpSymbol->getRVA() + Config->ImageBase);
498 void ImportThunkChunkARM64::writeTo(uint8_t *Buf) const {
499 int64_t Off = ImpSymbol->getRVA() & 0xfff;
500 memcpy(Buf + OutputSectionOff, ImportThunkARM64, sizeof(ImportThunkARM64));
501 applyArm64Addr(Buf + OutputSectionOff, ImpSymbol->getRVA(), RVA, 12);
502 applyArm64Ldr(Buf + OutputSectionOff + 4, Off);
505 void LocalImportChunk::getBaserels(std::vector<Baserel> *Res) {
506 Res->emplace_back(getRVA());
509 size_t LocalImportChunk::getSize() const {
510 return Config->is64() ? 8 : 4;
513 void LocalImportChunk::writeTo(uint8_t *Buf) const {
514 if (Config->is64()) {
515 write64le(Buf + OutputSectionOff, Sym->getRVA() + Config->ImageBase);
517 write32le(Buf + OutputSectionOff, Sym->getRVA() + Config->ImageBase);
521 void RVATableChunk::writeTo(uint8_t *Buf) const {
522 ulittle32_t *Begin = reinterpret_cast<ulittle32_t *>(Buf + OutputSectionOff);
524 for (const ChunkAndOffset &CO : Syms)
525 Begin[Cnt++] = CO.InputChunk->getRVA() + CO.Offset;
526 std::sort(Begin, Begin + Cnt);
527 assert(std::unique(Begin, Begin + Cnt) == Begin + Cnt &&
528 "RVA tables should be de-duplicated");
531 // Windows-specific. This class represents a block in .reloc section.
532 // The format is described here.
534 // On Windows, each DLL is linked against a fixed base address and
535 // usually loaded to that address. However, if there's already another
536 // DLL that overlaps, the loader has to relocate it. To do that, DLLs
537 // contain .reloc sections which contain offsets that need to be fixed
538 // up at runtime. If the loader finds that a DLL cannot be loaded to its
539 // desired base address, it loads it to somewhere else, and add <actual
540 // base address> - <desired base address> to each offset that is
541 // specified by the .reloc section. In ELF terms, .reloc sections
542 // contain relative relocations in REL format (as opposed to RELA.)
544 // This already significantly reduces the size of relocations compared
545 // to ELF .rel.dyn, but Windows does more to reduce it (probably because
546 // it was invented for PCs in the late '80s or early '90s.) Offsets in
547 // .reloc are grouped by page where the page size is 12 bits, and
548 // offsets sharing the same page address are stored consecutively to
549 // represent them with less space. This is very similar to the page
550 // table which is grouped by (multiple stages of) pages.
552 // For example, let's say we have 0x00030, 0x00500, 0x00700, 0x00A00,
553 // 0x20004, and 0x20008 in a .reloc section for x64. The uppermost 4
554 // bits have a type IMAGE_REL_BASED_DIR64 or 0xA. In the section, they
555 // are represented like this:
557 // 0x00000 -- page address (4 bytes)
558 // 16 -- size of this block (4 bytes)
559 // 0xA030 -- entries (2 bytes each)
563 // 0x20000 -- page address (4 bytes)
564 // 12 -- size of this block (4 bytes)
565 // 0xA004 -- entries (2 bytes each)
568 // Usually we have a lot of relocations for each page, so the number of
569 // bytes for one .reloc entry is close to 2 bytes on average.
570 BaserelChunk::BaserelChunk(uint32_t Page, Baserel *Begin, Baserel *End) {
571 // Block header consists of 4 byte page RVA and 4 byte block size.
572 // Each entry is 2 byte. Last entry may be padding.
573 Data.resize(alignTo((End - Begin) * 2 + 8, 4));
574 uint8_t *P = Data.data();
576 write32le(P + 4, Data.size());
578 for (Baserel *I = Begin; I != End; ++I) {
579 write16le(P, (I->Type << 12) | (I->RVA - Page));
584 void BaserelChunk::writeTo(uint8_t *Buf) const {
585 memcpy(Buf + OutputSectionOff, Data.data(), Data.size());
588 uint8_t Baserel::getDefaultType() {
589 switch (Config->Machine) {
592 return IMAGE_REL_BASED_DIR64;
595 return IMAGE_REL_BASED_HIGHLOW;
597 llvm_unreachable("unknown machine type");
601 std::map<uint32_t, MergeChunk *> MergeChunk::Instances;
603 MergeChunk::MergeChunk(uint32_t Alignment)
604 : Builder(StringTableBuilder::RAW, Alignment) {
605 this->Alignment = Alignment;
608 void MergeChunk::addSection(SectionChunk *C) {
609 auto *&MC = Instances[C->Alignment];
611 MC = make<MergeChunk>(C->Alignment);
612 MC->Sections.push_back(C);
615 void MergeChunk::finalizeContents() {
616 for (SectionChunk *C : Sections)
618 Builder.add(toStringRef(C->getContents()));
621 for (SectionChunk *C : Sections) {
624 size_t Off = Builder.getOffset(toStringRef(C->getContents()));
625 C->setOutputSection(Out);
626 C->setRVA(RVA + Off);
627 C->OutputSectionOff = OutputSectionOff + Off;
631 uint32_t MergeChunk::getOutputCharacteristics() const {
632 return IMAGE_SCN_MEM_READ | IMAGE_SCN_CNT_INITIALIZED_DATA;
635 size_t MergeChunk::getSize() const {
636 return Builder.getSize();
639 void MergeChunk::writeTo(uint8_t *Buf) const {
640 Builder.write(Buf + OutputSectionOff);