1 //===- AArch64.cpp --------------------------------------------------------===//
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
13 #include "SyntheticSections.h"
16 #include "llvm/Object/ELF.h"
17 #include "llvm/Support/Endian.h"
20 using namespace llvm::support::endian;
21 using namespace llvm::ELF;
23 using namespace lld::elf;
25 // Page(Expr) is the page address of the expression Expr, defined
26 // as (Expr & ~0xFFF). (This applies even if the machine page size
27 // supported by the platform has a different value.)
28 uint64_t elf::getAArch64Page(uint64_t Expr) {
29 return Expr & ~static_cast<uint64_t>(0xFFF);
33 class AArch64 final : public TargetInfo {
36 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
37 const uint8_t *Loc) const override;
38 bool isPicRel(uint32_t Type) const override;
39 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
40 void writePltHeader(uint8_t *Buf) const override;
41 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
42 int32_t Index, unsigned RelOff) const override;
43 bool usesOnlyLowPageBits(uint32_t Type) const override;
44 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
45 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
46 RelExpr Expr) const override;
47 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
48 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
49 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
54 CopyRel = R_AARCH64_COPY;
55 RelativeRel = R_AARCH64_RELATIVE;
56 IRelativeRel = R_AARCH64_IRELATIVE;
57 GotRel = R_AARCH64_GLOB_DAT;
58 PltRel = R_AARCH64_JUMP_SLOT;
59 TlsDescRel = R_AARCH64_TLSDESC;
60 TlsGotRel = R_AARCH64_TLS_TPREL64;
65 DefaultMaxPageSize = 65536;
67 // It doesn't seem to be documented anywhere, but tls on aarch64 uses variant
68 // 1 of the tls structures and the tcb size is 16.
72 RelExpr AArch64::getRelExpr(uint32_t Type, const SymbolBody &S,
73 const uint8_t *Loc) const {
77 case R_AARCH64_TLSDESC_ADR_PAGE21:
78 return R_TLSDESC_PAGE;
79 case R_AARCH64_TLSDESC_LD64_LO12:
80 case R_AARCH64_TLSDESC_ADD_LO12:
82 case R_AARCH64_TLSDESC_CALL:
83 return R_TLSDESC_CALL;
84 case R_AARCH64_TLSLE_ADD_TPREL_HI12:
85 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
87 case R_AARCH64_CALL26:
88 case R_AARCH64_CONDBR19:
89 case R_AARCH64_JUMP26:
90 case R_AARCH64_TSTBR14:
92 case R_AARCH64_PREL16:
93 case R_AARCH64_PREL32:
94 case R_AARCH64_PREL64:
95 case R_AARCH64_ADR_PREL_LO21:
97 case R_AARCH64_ADR_PREL_PG_HI21:
99 case R_AARCH64_LD64_GOT_LO12_NC:
100 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
102 case R_AARCH64_ADR_GOT_PAGE:
103 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
104 return R_GOT_PAGE_PC;
110 RelExpr AArch64::adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
111 RelExpr Expr) const {
112 if (Expr == R_RELAX_TLS_GD_TO_IE) {
113 if (Type == R_AARCH64_TLSDESC_ADR_PAGE21)
114 return R_RELAX_TLS_GD_TO_IE_PAGE_PC;
115 return R_RELAX_TLS_GD_TO_IE_ABS;
120 bool AArch64::usesOnlyLowPageBits(uint32_t Type) const {
124 case R_AARCH64_ADD_ABS_LO12_NC:
125 case R_AARCH64_LD64_GOT_LO12_NC:
126 case R_AARCH64_LDST128_ABS_LO12_NC:
127 case R_AARCH64_LDST16_ABS_LO12_NC:
128 case R_AARCH64_LDST32_ABS_LO12_NC:
129 case R_AARCH64_LDST64_ABS_LO12_NC:
130 case R_AARCH64_LDST8_ABS_LO12_NC:
131 case R_AARCH64_TLSDESC_ADD_LO12:
132 case R_AARCH64_TLSDESC_LD64_LO12:
133 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
138 bool AArch64::isPicRel(uint32_t Type) const {
139 return Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64;
142 void AArch64::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
143 write64le(Buf, InX::Plt->getVA());
146 void AArch64::writePltHeader(uint8_t *Buf) const {
147 const uint8_t PltData[] = {
148 0xf0, 0x7b, 0xbf, 0xa9, // stp x16, x30, [sp,#-16]!
149 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[2]))
150 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[2]))]
151 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[2]))
152 0x20, 0x02, 0x1f, 0xd6, // br x17
153 0x1f, 0x20, 0x03, 0xd5, // nop
154 0x1f, 0x20, 0x03, 0xd5, // nop
155 0x1f, 0x20, 0x03, 0xd5 // nop
157 memcpy(Buf, PltData, sizeof(PltData));
159 uint64_t Got = InX::GotPlt->getVA();
160 uint64_t Plt = InX::Plt->getVA();
161 relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21,
162 getAArch64Page(Got + 16) - getAArch64Page(Plt + 4));
163 relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16);
164 relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16);
167 void AArch64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
168 uint64_t PltEntryAddr, int32_t Index,
169 unsigned RelOff) const {
170 const uint8_t Inst[] = {
171 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n]))
172 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[n]))]
173 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[n]))
174 0x20, 0x02, 0x1f, 0xd6 // br x17
176 memcpy(Buf, Inst, sizeof(Inst));
178 relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21,
179 getAArch64Page(GotPltEntryAddr) - getAArch64Page(PltEntryAddr));
180 relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotPltEntryAddr);
181 relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotPltEntryAddr);
184 static void write32AArch64Addr(uint8_t *L, uint64_t Imm) {
185 uint32_t ImmLo = (Imm & 0x3) << 29;
186 uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
187 uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3);
188 write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi);
191 // Return the bits [Start, End] from Val shifted Start bits.
192 // For instance, getBits(0xF0, 4, 8) returns 0xF.
193 static uint64_t getBits(uint64_t Val, int Start, int End) {
194 uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1;
195 return (Val >> Start) & Mask;
198 static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
200 // Update the immediate field in a AARCH64 ldr, str, and add instruction.
201 static void or32AArch64Imm(uint8_t *L, uint64_t Imm) {
202 or32le(L, (Imm & 0xFFF) << 10);
205 void AArch64::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
207 case R_AARCH64_ABS16:
208 case R_AARCH64_PREL16:
209 checkIntUInt<16>(Loc, Val, Type);
212 case R_AARCH64_ABS32:
213 case R_AARCH64_PREL32:
214 checkIntUInt<32>(Loc, Val, Type);
217 case R_AARCH64_ABS64:
218 case R_AARCH64_GLOB_DAT:
219 case R_AARCH64_PREL64:
222 case R_AARCH64_ADD_ABS_LO12_NC:
223 or32AArch64Imm(Loc, Val);
225 case R_AARCH64_ADR_GOT_PAGE:
226 case R_AARCH64_ADR_PREL_PG_HI21:
227 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
228 case R_AARCH64_TLSDESC_ADR_PAGE21:
229 checkInt<33>(Loc, Val, Type);
230 write32AArch64Addr(Loc, Val >> 12);
232 case R_AARCH64_ADR_PREL_LO21:
233 checkInt<21>(Loc, Val, Type);
234 write32AArch64Addr(Loc, Val);
236 case R_AARCH64_CALL26:
237 case R_AARCH64_JUMP26:
238 checkInt<28>(Loc, Val, Type);
239 or32le(Loc, (Val & 0x0FFFFFFC) >> 2);
241 case R_AARCH64_CONDBR19:
242 checkInt<21>(Loc, Val, Type);
243 or32le(Loc, (Val & 0x1FFFFC) << 3);
245 case R_AARCH64_LD64_GOT_LO12_NC:
246 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
247 case R_AARCH64_TLSDESC_LD64_LO12:
248 checkAlignment<8>(Loc, Val, Type);
249 or32le(Loc, (Val & 0xFF8) << 7);
251 case R_AARCH64_LDST8_ABS_LO12_NC:
252 or32AArch64Imm(Loc, getBits(Val, 0, 11));
254 case R_AARCH64_LDST16_ABS_LO12_NC:
255 or32AArch64Imm(Loc, getBits(Val, 1, 11));
257 case R_AARCH64_LDST32_ABS_LO12_NC:
258 or32AArch64Imm(Loc, getBits(Val, 2, 11));
260 case R_AARCH64_LDST64_ABS_LO12_NC:
261 or32AArch64Imm(Loc, getBits(Val, 3, 11));
263 case R_AARCH64_LDST128_ABS_LO12_NC:
264 or32AArch64Imm(Loc, getBits(Val, 4, 11));
266 case R_AARCH64_MOVW_UABS_G0_NC:
267 or32le(Loc, (Val & 0xFFFF) << 5);
269 case R_AARCH64_MOVW_UABS_G1_NC:
270 or32le(Loc, (Val & 0xFFFF0000) >> 11);
272 case R_AARCH64_MOVW_UABS_G2_NC:
273 or32le(Loc, (Val & 0xFFFF00000000) >> 27);
275 case R_AARCH64_MOVW_UABS_G3:
276 or32le(Loc, (Val & 0xFFFF000000000000) >> 43);
278 case R_AARCH64_TSTBR14:
279 checkInt<16>(Loc, Val, Type);
280 or32le(Loc, (Val & 0xFFFC) << 3);
282 case R_AARCH64_TLSLE_ADD_TPREL_HI12:
283 checkInt<24>(Loc, Val, Type);
284 or32AArch64Imm(Loc, Val >> 12);
286 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
287 case R_AARCH64_TLSDESC_ADD_LO12:
288 or32AArch64Imm(Loc, Val);
291 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
295 void AArch64::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
296 // TLSDESC Global-Dynamic relocation are in the form:
297 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21]
298 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12]
299 // add x0, x0, :tlsdesc_los:v [R_AARCH64_TLSDESC_ADD_LO12]
300 // .tlsdesccall [R_AARCH64_TLSDESC_CALL]
302 // And it can optimized to:
303 // movz x0, #0x0, lsl #16
307 checkUInt<32>(Loc, Val, Type);
310 case R_AARCH64_TLSDESC_ADD_LO12:
311 case R_AARCH64_TLSDESC_CALL:
312 write32le(Loc, 0xd503201f); // nop
314 case R_AARCH64_TLSDESC_ADR_PAGE21:
315 write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz
317 case R_AARCH64_TLSDESC_LD64_LO12:
318 write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk
321 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
325 void AArch64::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
326 // TLSDESC Global-Dynamic relocation are in the form:
327 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21]
328 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12]
329 // add x0, x0, :tlsdesc_los:v [R_AARCH64_TLSDESC_ADD_LO12]
330 // .tlsdesccall [R_AARCH64_TLSDESC_CALL]
332 // And it can optimized to:
333 // adrp x0, :gottprel:v
334 // ldr x0, [x0, :gottprel_lo12:v]
339 case R_AARCH64_TLSDESC_ADD_LO12:
340 case R_AARCH64_TLSDESC_CALL:
341 write32le(Loc, 0xd503201f); // nop
343 case R_AARCH64_TLSDESC_ADR_PAGE21:
344 write32le(Loc, 0x90000000); // adrp
345 relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val);
347 case R_AARCH64_TLSDESC_LD64_LO12:
348 write32le(Loc, 0xf9400000); // ldr
349 relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val);
352 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
356 void AArch64::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
357 checkUInt<32>(Loc, Val, Type);
359 if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) {
361 uint32_t RegNo = read32le(Loc) & 0x1f;
362 write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5));
365 if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) {
367 uint32_t RegNo = read32le(Loc) & 0x1f;
368 write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5));
371 llvm_unreachable("invalid relocation for TLS IE to LE relaxation");
374 TargetInfo *elf::createAArch64TargetInfo() { return make<AArch64>(); }