1 //===- AArch64.cpp --------------------------------------------------------===//
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "SyntheticSections.h"
14 #include "lld/Common/ErrorHandler.h"
15 #include "llvm/Object/ELF.h"
16 #include "llvm/Support/Endian.h"
19 using namespace llvm::support::endian;
20 using namespace llvm::ELF;
22 using namespace lld::elf;
24 // Page(Expr) is the page address of the expression Expr, defined
25 // as (Expr & ~0xFFF). (This applies even if the machine page size
26 // supported by the platform has a different value.)
27 uint64_t elf::getAArch64Page(uint64_t Expr) {
28 return Expr & ~static_cast<uint64_t>(0xFFF);
32 class AArch64 final : public TargetInfo {
35 RelExpr getRelExpr(RelType Type, const Symbol &S,
36 const uint8_t *Loc) const override;
37 bool isPicRel(RelType Type) const override;
38 void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
39 void writePltHeader(uint8_t *Buf) const override;
40 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
41 int32_t Index, unsigned RelOff) const override;
42 bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
43 uint64_t BranchAddr, const Symbol &S) const override;
44 bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override;
45 bool usesOnlyLowPageBits(RelType Type) const override;
46 void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
47 RelExpr adjustRelaxExpr(RelType Type, const uint8_t *Data,
48 RelExpr Expr) const override;
49 void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
50 void relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
51 void relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
56 CopyRel = R_AARCH64_COPY;
57 RelativeRel = R_AARCH64_RELATIVE;
58 IRelativeRel = R_AARCH64_IRELATIVE;
59 GotRel = R_AARCH64_GLOB_DAT;
60 PltRel = R_AARCH64_JUMP_SLOT;
61 TlsDescRel = R_AARCH64_TLSDESC;
62 TlsGotRel = R_AARCH64_TLS_TPREL64;
67 DefaultMaxPageSize = 65536;
69 // It doesn't seem to be documented anywhere, but tls on aarch64 uses variant
70 // 1 of the tls structures and the tcb size is 16.
74 // See comment in Arch/ARM.cpp for a more detailed explanation of
75 // ThunkSectionSpacing. For AArch64 the only branches we are permitted to
76 // Thunk have a range of +/- 128 MiB
77 ThunkSectionSpacing = (128 * 1024 * 1024) - 0x30000;
80 RelExpr AArch64::getRelExpr(RelType Type, const Symbol &S,
81 const uint8_t *Loc) const {
83 case R_AARCH64_TLSDESC_ADR_PAGE21:
84 return R_TLSDESC_PAGE;
85 case R_AARCH64_TLSDESC_LD64_LO12:
86 case R_AARCH64_TLSDESC_ADD_LO12:
88 case R_AARCH64_TLSDESC_CALL:
89 return R_TLSDESC_CALL;
90 case R_AARCH64_TLSLE_ADD_TPREL_HI12:
91 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
93 case R_AARCH64_CALL26:
94 case R_AARCH64_CONDBR19:
95 case R_AARCH64_JUMP26:
96 case R_AARCH64_TSTBR14:
98 case R_AARCH64_PREL16:
99 case R_AARCH64_PREL32:
100 case R_AARCH64_PREL64:
101 case R_AARCH64_ADR_PREL_LO21:
102 case R_AARCH64_LD_PREL_LO19:
104 case R_AARCH64_ADR_PREL_PG_HI21:
106 case R_AARCH64_LD64_GOT_LO12_NC:
107 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
109 case R_AARCH64_ADR_GOT_PAGE:
110 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
111 return R_GOT_PAGE_PC;
119 RelExpr AArch64::adjustRelaxExpr(RelType Type, const uint8_t *Data,
120 RelExpr Expr) const {
121 if (Expr == R_RELAX_TLS_GD_TO_IE) {
122 if (Type == R_AARCH64_TLSDESC_ADR_PAGE21)
123 return R_RELAX_TLS_GD_TO_IE_PAGE_PC;
124 return R_RELAX_TLS_GD_TO_IE_ABS;
129 bool AArch64::usesOnlyLowPageBits(RelType Type) const {
133 case R_AARCH64_ADD_ABS_LO12_NC:
134 case R_AARCH64_LD64_GOT_LO12_NC:
135 case R_AARCH64_LDST128_ABS_LO12_NC:
136 case R_AARCH64_LDST16_ABS_LO12_NC:
137 case R_AARCH64_LDST32_ABS_LO12_NC:
138 case R_AARCH64_LDST64_ABS_LO12_NC:
139 case R_AARCH64_LDST8_ABS_LO12_NC:
140 case R_AARCH64_TLSDESC_ADD_LO12:
141 case R_AARCH64_TLSDESC_LD64_LO12:
142 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
147 bool AArch64::isPicRel(RelType Type) const {
148 return Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64;
151 void AArch64::writeGotPlt(uint8_t *Buf, const Symbol &) const {
152 write64le(Buf, InX::Plt->getVA());
155 void AArch64::writePltHeader(uint8_t *Buf) const {
156 const uint8_t PltData[] = {
157 0xf0, 0x7b, 0xbf, 0xa9, // stp x16, x30, [sp,#-16]!
158 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[2]))
159 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[2]))]
160 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[2]))
161 0x20, 0x02, 0x1f, 0xd6, // br x17
162 0x1f, 0x20, 0x03, 0xd5, // nop
163 0x1f, 0x20, 0x03, 0xd5, // nop
164 0x1f, 0x20, 0x03, 0xd5 // nop
166 memcpy(Buf, PltData, sizeof(PltData));
168 uint64_t Got = InX::GotPlt->getVA();
169 uint64_t Plt = InX::Plt->getVA();
170 relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21,
171 getAArch64Page(Got + 16) - getAArch64Page(Plt + 4));
172 relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16);
173 relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16);
176 void AArch64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
177 uint64_t PltEntryAddr, int32_t Index,
178 unsigned RelOff) const {
179 const uint8_t Inst[] = {
180 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n]))
181 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[n]))]
182 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[n]))
183 0x20, 0x02, 0x1f, 0xd6 // br x17
185 memcpy(Buf, Inst, sizeof(Inst));
187 relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21,
188 getAArch64Page(GotPltEntryAddr) - getAArch64Page(PltEntryAddr));
189 relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotPltEntryAddr);
190 relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotPltEntryAddr);
193 bool AArch64::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
194 uint64_t BranchAddr, const Symbol &S) const {
195 // ELF for the ARM 64-bit architecture, section Call and Jump relocations
196 // only permits range extension thunks for R_AARCH64_CALL26 and
197 // R_AARCH64_JUMP26 relocation types.
198 if (Type != R_AARCH64_CALL26 && Type != R_AARCH64_JUMP26)
200 uint64_t Dst = (Expr == R_PLT_PC) ? S.getPltVA() : S.getVA();
201 return !inBranchRange(Type, BranchAddr, Dst);
204 bool AArch64::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
205 if (Type != R_AARCH64_CALL26 && Type != R_AARCH64_JUMP26)
207 // The AArch64 call and unconditional branch instructions have a range of
209 uint64_t Range = 128 * 1024 * 1024;
211 // Immediate of branch is signed.
213 return Dst - Src <= Range;
215 return Src - Dst <= Range;
218 static void write32AArch64Addr(uint8_t *L, uint64_t Imm) {
219 uint32_t ImmLo = (Imm & 0x3) << 29;
220 uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
221 uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3);
222 write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi);
225 // Return the bits [Start, End] from Val shifted Start bits.
226 // For instance, getBits(0xF0, 4, 8) returns 0xF.
227 static uint64_t getBits(uint64_t Val, int Start, int End) {
228 uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1;
229 return (Val >> Start) & Mask;
232 static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
234 // Update the immediate field in a AARCH64 ldr, str, and add instruction.
235 static void or32AArch64Imm(uint8_t *L, uint64_t Imm) {
236 or32le(L, (Imm & 0xFFF) << 10);
239 void AArch64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
241 case R_AARCH64_ABS16:
242 case R_AARCH64_PREL16:
243 checkIntUInt<16>(Loc, Val, Type);
246 case R_AARCH64_ABS32:
247 case R_AARCH64_PREL32:
248 checkIntUInt<32>(Loc, Val, Type);
251 case R_AARCH64_ABS64:
252 case R_AARCH64_GLOB_DAT:
253 case R_AARCH64_PREL64:
256 case R_AARCH64_ADD_ABS_LO12_NC:
257 or32AArch64Imm(Loc, Val);
259 case R_AARCH64_ADR_GOT_PAGE:
260 case R_AARCH64_ADR_PREL_PG_HI21:
261 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
262 case R_AARCH64_TLSDESC_ADR_PAGE21:
263 checkInt<33>(Loc, Val, Type);
264 write32AArch64Addr(Loc, Val >> 12);
266 case R_AARCH64_ADR_PREL_LO21:
267 checkInt<21>(Loc, Val, Type);
268 write32AArch64Addr(Loc, Val);
270 case R_AARCH64_JUMP26:
271 // Normally we would just write the bits of the immediate field, however
272 // when patching instructions for the cpu errata fix -fix-cortex-a53-843419
273 // we want to replace a non-branch instruction with a branch immediate
274 // instruction. By writing all the bits of the instruction including the
275 // opcode and the immediate (0 001 | 01 imm26) we can do this
276 // transformation by placing a R_AARCH64_JUMP26 relocation at the offset of
277 // the instruction we want to patch.
278 write32le(Loc, 0x14000000);
280 case R_AARCH64_CALL26:
281 checkInt<28>(Loc, Val, Type);
282 or32le(Loc, (Val & 0x0FFFFFFC) >> 2);
284 case R_AARCH64_CONDBR19:
285 case R_AARCH64_LD_PREL_LO19:
286 checkAlignment<4>(Loc, Val, Type);
287 checkInt<21>(Loc, Val, Type);
288 or32le(Loc, (Val & 0x1FFFFC) << 3);
290 case R_AARCH64_LD64_GOT_LO12_NC:
291 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
292 case R_AARCH64_TLSDESC_LD64_LO12:
293 checkAlignment<8>(Loc, Val, Type);
294 or32le(Loc, (Val & 0xFF8) << 7);
296 case R_AARCH64_LDST8_ABS_LO12_NC:
297 or32AArch64Imm(Loc, getBits(Val, 0, 11));
299 case R_AARCH64_LDST16_ABS_LO12_NC:
300 checkAlignment<2>(Loc, Val, Type);
301 or32AArch64Imm(Loc, getBits(Val, 1, 11));
303 case R_AARCH64_LDST32_ABS_LO12_NC:
304 checkAlignment<4>(Loc, Val, Type);
305 or32AArch64Imm(Loc, getBits(Val, 2, 11));
307 case R_AARCH64_LDST64_ABS_LO12_NC:
308 checkAlignment<8>(Loc, Val, Type);
309 or32AArch64Imm(Loc, getBits(Val, 3, 11));
311 case R_AARCH64_LDST128_ABS_LO12_NC:
312 checkAlignment<16>(Loc, Val, Type);
313 or32AArch64Imm(Loc, getBits(Val, 4, 11));
315 case R_AARCH64_MOVW_UABS_G0_NC:
316 or32le(Loc, (Val & 0xFFFF) << 5);
318 case R_AARCH64_MOVW_UABS_G1_NC:
319 or32le(Loc, (Val & 0xFFFF0000) >> 11);
321 case R_AARCH64_MOVW_UABS_G2_NC:
322 or32le(Loc, (Val & 0xFFFF00000000) >> 27);
324 case R_AARCH64_MOVW_UABS_G3:
325 or32le(Loc, (Val & 0xFFFF000000000000) >> 43);
327 case R_AARCH64_TSTBR14:
328 checkInt<16>(Loc, Val, Type);
329 or32le(Loc, (Val & 0xFFFC) << 3);
331 case R_AARCH64_TLSLE_ADD_TPREL_HI12:
332 checkInt<24>(Loc, Val, Type);
333 or32AArch64Imm(Loc, Val >> 12);
335 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
336 case R_AARCH64_TLSDESC_ADD_LO12:
337 or32AArch64Imm(Loc, Val);
340 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
344 void AArch64::relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
345 // TLSDESC Global-Dynamic relocation are in the form:
346 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21]
347 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12]
348 // add x0, x0, :tlsdesc_los:v [R_AARCH64_TLSDESC_ADD_LO12]
349 // .tlsdesccall [R_AARCH64_TLSDESC_CALL]
351 // And it can optimized to:
352 // movz x0, #0x0, lsl #16
356 checkUInt<32>(Loc, Val, Type);
359 case R_AARCH64_TLSDESC_ADD_LO12:
360 case R_AARCH64_TLSDESC_CALL:
361 write32le(Loc, 0xd503201f); // nop
363 case R_AARCH64_TLSDESC_ADR_PAGE21:
364 write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz
366 case R_AARCH64_TLSDESC_LD64_LO12:
367 write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk
370 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
374 void AArch64::relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const {
375 // TLSDESC Global-Dynamic relocation are in the form:
376 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21]
377 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12]
378 // add x0, x0, :tlsdesc_los:v [R_AARCH64_TLSDESC_ADD_LO12]
379 // .tlsdesccall [R_AARCH64_TLSDESC_CALL]
381 // And it can optimized to:
382 // adrp x0, :gottprel:v
383 // ldr x0, [x0, :gottprel_lo12:v]
388 case R_AARCH64_TLSDESC_ADD_LO12:
389 case R_AARCH64_TLSDESC_CALL:
390 write32le(Loc, 0xd503201f); // nop
392 case R_AARCH64_TLSDESC_ADR_PAGE21:
393 write32le(Loc, 0x90000000); // adrp
394 relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val);
396 case R_AARCH64_TLSDESC_LD64_LO12:
397 write32le(Loc, 0xf9400000); // ldr
398 relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val);
401 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
405 void AArch64::relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
406 checkUInt<32>(Loc, Val, Type);
408 if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) {
410 uint32_t RegNo = read32le(Loc) & 0x1f;
411 write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5));
414 if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) {
416 uint32_t RegNo = read32le(Loc) & 0x1f;
417 write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5));
420 llvm_unreachable("invalid relocation for TLS IE to LE relaxation");
423 TargetInfo *elf::getAArch64TargetInfo() {
424 static AArch64 Target;