1 //===- PPC64.cpp ----------------------------------------------------------===//
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "SyntheticSections.h"
13 #include "lld/Common/ErrorHandler.h"
14 #include "llvm/Support/Endian.h"
17 using namespace llvm::object;
18 using namespace llvm::support::endian;
19 using namespace llvm::ELF;
21 using namespace lld::elf;
23 static uint64_t PPC64TocOffset = 0x8000;
24 static uint64_t DynamicThreadPointerOffset = 0x8000;
26 // The instruction encoding of bits 21-30 from the ISA for the Xform and Dform
27 // instructions that can be used as part of the initial exec TLS sequence.
63 uint64_t elf::getPPC64TocBase() {
64 // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The
65 // TOC starts where the first of these sections starts. We always create a
66 // .got when we see a relocation that uses it, so for us the start is always
68 uint64_t TocVA = In.Got->getVA();
70 // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000
71 // thus permitting a full 64 Kbytes segment. Note that the glibc startup
72 // code (crt1.o) assumes that you can get from the TOC base to the
73 // start of the .toc section with only a single (signed) 16-bit relocation.
74 return TocVA + PPC64TocOffset;
77 unsigned elf::getPPC64GlobalEntryToLocalEntryOffset(uint8_t StOther) {
78 // The offset is encoded into the 3 most significant bits of the st_other
79 // field, with some special values described in section 3.4.1 of the ABI:
80 // 0 --> Zero offset between the GEP and LEP, and the function does NOT use
81 // the TOC pointer (r2). r2 will hold the same value on returning from
82 // the function as it did on entering the function.
83 // 1 --> Zero offset between the GEP and LEP, and r2 should be treated as a
84 // caller-saved register for all callers.
85 // 2-6 --> The binary logarithm of the offset eg:
86 // 2 --> 2^2 = 4 bytes --> 1 instruction.
87 // 6 --> 2^6 = 64 bytes --> 16 instructions.
89 uint8_t GepToLep = (StOther >> 5) & 7;
93 // The value encoded in the st_other bits is the
94 // log-base-2(offset).
98 error("reserved value of 7 in the 3 most-significant-bits of st_other");
103 class PPC64 final : public TargetInfo {
106 uint32_t calcEFlags() const override;
107 RelExpr getRelExpr(RelType Type, const Symbol &S,
108 const uint8_t *Loc) const override;
109 void writePltHeader(uint8_t *Buf) const override;
110 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
111 int32_t Index, unsigned RelOff) const override;
112 void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
113 void writeGotHeader(uint8_t *Buf) const override;
114 bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
115 uint64_t BranchAddr, const Symbol &S) const override;
116 uint32_t getThunkSectionSpacing() const override;
117 bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override;
118 RelExpr adjustRelaxExpr(RelType Type, const uint8_t *Data,
119 RelExpr Expr) const override;
120 void relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
121 void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
122 void relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
123 void relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
125 bool adjustPrologueForCrossSplitStack(uint8_t *Loc, uint8_t *End,
126 uint8_t StOther) const override;
130 // Relocation masks following the #lo(value), #hi(value), #ha(value),
131 // #higher(value), #highera(value), #highest(value), and #highesta(value)
132 // macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi
134 static uint16_t lo(uint64_t V) { return V; }
135 static uint16_t hi(uint64_t V) { return V >> 16; }
136 static uint16_t ha(uint64_t V) { return (V + 0x8000) >> 16; }
137 static uint16_t higher(uint64_t V) { return V >> 32; }
138 static uint16_t highera(uint64_t V) { return (V + 0x8000) >> 32; }
139 static uint16_t highest(uint64_t V) { return V >> 48; }
140 static uint16_t highesta(uint64_t V) { return (V + 0x8000) >> 48; }
142 // Extracts the 'PO' field of an instruction encoding.
143 static uint8_t getPrimaryOpCode(uint32_t Encoding) { return (Encoding >> 26); }
145 static bool isDQFormInstruction(uint32_t Encoding) {
146 switch (getPrimaryOpCode(Encoding)) {
150 // The only instruction with a primary opcode of 56 is `lq`.
153 // There are both DS and DQ instruction forms with this primary opcode.
154 // Namely `lxv` and `stxv` are the DQ-forms that use it.
155 // The DS 'XO' bits being set to 01 is restricted to DQ form.
156 return (Encoding & 3) == 0x1;
160 static bool isInstructionUpdateForm(uint32_t Encoding) {
161 switch (getPrimaryOpCode(Encoding)) {
176 // LWA has the same opcode as LD, and the DS bits is what differentiates
177 // between LD/LDU/LWA
180 return (Encoding & 3) == 1;
184 // There are a number of places when we either want to read or write an
185 // instruction when handling a half16 relocation type. On big-endian the buffer
186 // pointer is pointing into the middle of the word we want to extract, and on
187 // little-endian it is pointing to the start of the word. These 2 helpers are to
188 // simplify reading and writing in that context.
189 static void writeInstrFromHalf16(uint8_t *Loc, uint32_t Instr) {
190 write32(Loc - (Config->EKind == ELF64BEKind ? 2 : 0), Instr);
193 static uint32_t readInstrFromHalf16(const uint8_t *Loc) {
194 return read32(Loc - (Config->EKind == ELF64BEKind ? 2 : 0));
198 GotRel = R_PPC64_GLOB_DAT;
199 NoneRel = R_PPC64_NONE;
200 PltRel = R_PPC64_JMP_SLOT;
201 RelativeRel = R_PPC64_RELATIVE;
202 IRelativeRel = R_PPC64_IRELATIVE;
206 GotBaseSymInGotPlt = false;
207 GotBaseSymOff = 0x8000;
208 GotHeaderEntriesNum = 1;
209 GotPltHeaderEntriesNum = 2;
213 TlsModuleIndexRel = R_PPC64_DTPMOD64;
214 TlsOffsetRel = R_PPC64_DTPREL64;
216 TlsGotRel = R_PPC64_TPREL64;
218 NeedsMoreStackNonSplit = false;
220 // We need 64K pages (at least under glibc/Linux, the loader won't
221 // set different permissions on a finer granularity than that).
222 DefaultMaxPageSize = 65536;
224 // The PPC64 ELF ABI v1 spec, says:
226 // It is normally desirable to put segments with different characteristics
227 // in separate 256 Mbyte portions of the address space, to give the
228 // operating system full paging flexibility in the 64-bit address space.
230 // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers
231 // use 0x10000000 as the starting address.
232 DefaultImageBase = 0x10000000;
234 write32(TrapInstr.data(), 0x7fe00008);
237 static uint32_t getEFlags(InputFile *File) {
238 if (Config->EKind == ELF64BEKind)
239 return cast<ObjFile<ELF64BE>>(File)->getObj().getHeader()->e_flags;
240 return cast<ObjFile<ELF64LE>>(File)->getObj().getHeader()->e_flags;
243 // This file implements v2 ABI. This function makes sure that all
244 // object files have v2 or an unspecified version as an ABI version.
245 uint32_t PPC64::calcEFlags() const {
246 for (InputFile *F : ObjectFiles) {
247 uint32_t Flag = getEFlags(F);
249 error(toString(F) + ": ABI version 1 is not supported");
251 error(toString(F) + ": unrecognized e_flags: " + Twine(Flag));
256 void PPC64::relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
257 // Reference: 3.7.4.2 of the 64-bit ELF V2 abi supplement.
258 // The general dynamic code sequence for a global `x` will look like:
259 // Instruction Relocation Symbol
260 // addis r3, r2, x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x
261 // addi r3, r3, x@got@tlsgd@l R_PPC64_GOT_TLSGD16_LO x
262 // bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x
263 // R_PPC64_REL24 __tls_get_addr
266 // Relaxing to local exec entails converting:
267 // addis r3, r2, x@got@tlsgd@ha into nop
268 // addi r3, r3, x@got@tlsgd@l into addis r3, r13, x@tprel@ha
269 // bl __tls_get_addr(x@tlsgd) into nop
270 // nop into addi r3, r3, x@tprel@l
273 case R_PPC64_GOT_TLSGD16_HA:
274 writeInstrFromHalf16(Loc, 0x60000000); // nop
276 case R_PPC64_GOT_TLSGD16:
277 case R_PPC64_GOT_TLSGD16_LO:
278 writeInstrFromHalf16(Loc, 0x3c6d0000); // addis r3, r13
279 relocateOne(Loc, R_PPC64_TPREL16_HA, Val);
282 write32(Loc, 0x60000000); // nop
283 write32(Loc + 4, 0x38630000); // addi r3, r3
284 // Since we are relocating a half16 type relocation and Loc + 4 points to
285 // the start of an instruction we need to advance the buffer by an extra
287 relocateOne(Loc + 4 + (Config->EKind == ELF64BEKind ? 2 : 0),
288 R_PPC64_TPREL16_LO, Val);
291 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
295 void PPC64::relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
296 // Reference: 3.7.4.3 of the 64-bit ELF V2 abi supplement.
297 // The local dynamic code sequence for a global `x` will look like:
298 // Instruction Relocation Symbol
299 // addis r3, r2, x@got@tlsld@ha R_PPC64_GOT_TLSLD16_HA x
300 // addi r3, r3, x@got@tlsld@l R_PPC64_GOT_TLSLD16_LO x
301 // bl __tls_get_addr(x@tlsgd) R_PPC64_TLSLD x
302 // R_PPC64_REL24 __tls_get_addr
305 // Relaxing to local exec entails converting:
306 // addis r3, r2, x@got@tlsld@ha into nop
307 // addi r3, r3, x@got@tlsld@l into addis r3, r13, 0
308 // bl __tls_get_addr(x@tlsgd) into nop
309 // nop into addi r3, r3, 4096
312 case R_PPC64_GOT_TLSLD16_HA:
313 writeInstrFromHalf16(Loc, 0x60000000); // nop
315 case R_PPC64_GOT_TLSLD16_LO:
316 writeInstrFromHalf16(Loc, 0x3c6d0000); // addis r3, r13, 0
319 write32(Loc, 0x60000000); // nop
320 write32(Loc + 4, 0x38631000); // addi r3, r3, 4096
322 case R_PPC64_DTPREL16:
323 case R_PPC64_DTPREL16_HA:
324 case R_PPC64_DTPREL16_HI:
325 case R_PPC64_DTPREL16_DS:
326 case R_PPC64_DTPREL16_LO:
327 case R_PPC64_DTPREL16_LO_DS:
328 case R_PPC64_GOT_DTPREL16_HA:
329 case R_PPC64_GOT_DTPREL16_LO_DS:
330 case R_PPC64_GOT_DTPREL16_DS:
331 case R_PPC64_GOT_DTPREL16_HI:
332 relocateOne(Loc, Type, Val);
335 llvm_unreachable("unsupported relocation for TLS LD to LE relaxation");
339 static unsigned getDFormOp(unsigned SecondaryOp) {
340 switch (SecondaryOp) {
360 error("unrecognized instruction for IE to LE R_PPC64_TLS");
365 void PPC64::relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
366 // The initial exec code sequence for a global `x` will look like:
367 // Instruction Relocation Symbol
368 // addis r9, r2, x@got@tprel@ha R_PPC64_GOT_TPREL16_HA x
369 // ld r9, x@got@tprel@l(r9) R_PPC64_GOT_TPREL16_LO_DS x
370 // add r9, r9, x@tls R_PPC64_TLS x
372 // Relaxing to local exec entails converting:
373 // addis r9, r2, x@got@tprel@ha into nop
374 // ld r9, x@got@tprel@l(r9) into addis r9, r13, x@tprel@ha
375 // add r9, r9, x@tls into addi r9, r9, x@tprel@l
377 // x@tls R_PPC64_TLS is a relocation which does not compute anything,
378 // it is replaced with r13 (thread pointer).
380 // The add instruction in the initial exec sequence has multiple variations
381 // that need to be handled. If we are building an address it will use an add
382 // instruction, if we are accessing memory it will use any of the X-form
383 // indexed load or store instructions.
385 unsigned Offset = (Config->EKind == ELF64BEKind) ? 2 : 0;
387 case R_PPC64_GOT_TPREL16_HA:
388 write32(Loc - Offset, 0x60000000); // nop
390 case R_PPC64_GOT_TPREL16_LO_DS:
391 case R_PPC64_GOT_TPREL16_DS: {
392 uint32_t RegNo = read32(Loc - Offset) & 0x03E00000; // bits 6-10
393 write32(Loc - Offset, 0x3C0D0000 | RegNo); // addis RegNo, r13
394 relocateOne(Loc, R_PPC64_TPREL16_HA, Val);
398 uint32_t PrimaryOp = getPrimaryOpCode(read32(Loc));
400 error("unrecognized instruction for IE to LE R_PPC64_TLS");
401 uint32_t SecondaryOp = (read32(Loc) & 0x000007FE) >> 1; // bits 21-30
402 uint32_t DFormOp = getDFormOp(SecondaryOp);
403 write32(Loc, ((DFormOp << 26) | (read32(Loc) & 0x03FFFFFF)));
404 relocateOne(Loc + Offset, R_PPC64_TPREL16_LO, Val);
408 llvm_unreachable("unknown relocation for IE to LE");
413 RelExpr PPC64::getRelExpr(RelType Type, const Symbol &S,
414 const uint8_t *Loc) const {
417 case R_PPC64_GOT16_DS:
418 case R_PPC64_GOT16_HA:
419 case R_PPC64_GOT16_HI:
420 case R_PPC64_GOT16_LO:
421 case R_PPC64_GOT16_LO_DS:
424 case R_PPC64_TOC16_DS:
425 case R_PPC64_TOC16_HA:
426 case R_PPC64_TOC16_HI:
427 case R_PPC64_TOC16_LO:
428 case R_PPC64_TOC16_LO_DS:
434 return R_PPC_CALL_PLT;
435 case R_PPC64_REL16_LO:
436 case R_PPC64_REL16_HA:
440 case R_PPC64_GOT_TLSGD16:
441 case R_PPC64_GOT_TLSGD16_HA:
442 case R_PPC64_GOT_TLSGD16_HI:
443 case R_PPC64_GOT_TLSGD16_LO:
445 case R_PPC64_GOT_TLSLD16:
446 case R_PPC64_GOT_TLSLD16_HA:
447 case R_PPC64_GOT_TLSLD16_HI:
448 case R_PPC64_GOT_TLSLD16_LO:
450 case R_PPC64_GOT_TPREL16_HA:
451 case R_PPC64_GOT_TPREL16_LO_DS:
452 case R_PPC64_GOT_TPREL16_DS:
453 case R_PPC64_GOT_TPREL16_HI:
455 case R_PPC64_GOT_DTPREL16_HA:
456 case R_PPC64_GOT_DTPREL16_LO_DS:
457 case R_PPC64_GOT_DTPREL16_DS:
458 case R_PPC64_GOT_DTPREL16_HI:
459 return R_TLSLD_GOT_OFF;
460 case R_PPC64_TPREL16:
461 case R_PPC64_TPREL16_HA:
462 case R_PPC64_TPREL16_LO:
463 case R_PPC64_TPREL16_HI:
464 case R_PPC64_TPREL16_DS:
465 case R_PPC64_TPREL16_LO_DS:
466 case R_PPC64_TPREL16_HIGHER:
467 case R_PPC64_TPREL16_HIGHERA:
468 case R_PPC64_TPREL16_HIGHEST:
469 case R_PPC64_TPREL16_HIGHESTA:
471 case R_PPC64_DTPREL16:
472 case R_PPC64_DTPREL16_DS:
473 case R_PPC64_DTPREL16_HA:
474 case R_PPC64_DTPREL16_HI:
475 case R_PPC64_DTPREL16_HIGHER:
476 case R_PPC64_DTPREL16_HIGHERA:
477 case R_PPC64_DTPREL16_HIGHEST:
478 case R_PPC64_DTPREL16_HIGHESTA:
479 case R_PPC64_DTPREL16_LO:
480 case R_PPC64_DTPREL16_LO_DS:
481 case R_PPC64_DTPREL64:
484 return R_TLSDESC_CALL;
494 void PPC64::writeGotHeader(uint8_t *Buf) const {
495 write64(Buf, getPPC64TocBase());
498 void PPC64::writePltHeader(uint8_t *Buf) const {
499 // The generic resolver stub goes first.
500 write32(Buf + 0, 0x7c0802a6); // mflr r0
501 write32(Buf + 4, 0x429f0005); // bcl 20,4*cr7+so,8 <_glink+0x8>
502 write32(Buf + 8, 0x7d6802a6); // mflr r11
503 write32(Buf + 12, 0x7c0803a6); // mtlr r0
504 write32(Buf + 16, 0x7d8b6050); // subf r12, r11, r12
505 write32(Buf + 20, 0x380cffcc); // subi r0,r12,52
506 write32(Buf + 24, 0x7800f082); // srdi r0,r0,62,2
507 write32(Buf + 28, 0xe98b002c); // ld r12,44(r11)
508 write32(Buf + 32, 0x7d6c5a14); // add r11,r12,r11
509 write32(Buf + 36, 0xe98b0000); // ld r12,0(r11)
510 write32(Buf + 40, 0xe96b0008); // ld r11,8(r11)
511 write32(Buf + 44, 0x7d8903a6); // mtctr r12
512 write32(Buf + 48, 0x4e800420); // bctr
514 // The 'bcl' instruction will set the link register to the address of the
515 // following instruction ('mflr r11'). Here we store the offset from that
516 // instruction to the first entry in the GotPlt section.
517 int64_t GotPltOffset = In.GotPlt->getVA() - (In.Plt->getVA() + 8);
518 write64(Buf + 52, GotPltOffset);
521 void PPC64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
522 uint64_t PltEntryAddr, int32_t Index,
523 unsigned RelOff) const {
524 int32_t Offset = PltHeaderSize + Index * PltEntrySize;
525 // bl __glink_PLTresolve
526 write32(Buf, 0x48000000 | ((-Offset) & 0x03FFFFFc));
529 static std::pair<RelType, uint64_t> toAddr16Rel(RelType Type, uint64_t Val) {
530 // Relocations relative to the toc-base need to be adjusted by the Toc offset.
531 uint64_t TocBiasedVal = Val - PPC64TocOffset;
532 // Relocations relative to dtv[dtpmod] need to be adjusted by the DTP offset.
533 uint64_t DTPBiasedVal = Val - DynamicThreadPointerOffset;
536 // TOC biased relocation.
538 case R_PPC64_GOT_TLSGD16:
539 case R_PPC64_GOT_TLSLD16:
541 return {R_PPC64_ADDR16, TocBiasedVal};
542 case R_PPC64_GOT16_DS:
543 case R_PPC64_TOC16_DS:
544 case R_PPC64_GOT_TPREL16_DS:
545 case R_PPC64_GOT_DTPREL16_DS:
546 return {R_PPC64_ADDR16_DS, TocBiasedVal};
547 case R_PPC64_GOT16_HA:
548 case R_PPC64_GOT_TLSGD16_HA:
549 case R_PPC64_GOT_TLSLD16_HA:
550 case R_PPC64_GOT_TPREL16_HA:
551 case R_PPC64_GOT_DTPREL16_HA:
552 case R_PPC64_TOC16_HA:
553 return {R_PPC64_ADDR16_HA, TocBiasedVal};
554 case R_PPC64_GOT16_HI:
555 case R_PPC64_GOT_TLSGD16_HI:
556 case R_PPC64_GOT_TLSLD16_HI:
557 case R_PPC64_GOT_TPREL16_HI:
558 case R_PPC64_GOT_DTPREL16_HI:
559 case R_PPC64_TOC16_HI:
560 return {R_PPC64_ADDR16_HI, TocBiasedVal};
561 case R_PPC64_GOT16_LO:
562 case R_PPC64_GOT_TLSGD16_LO:
563 case R_PPC64_GOT_TLSLD16_LO:
564 case R_PPC64_TOC16_LO:
565 return {R_PPC64_ADDR16_LO, TocBiasedVal};
566 case R_PPC64_GOT16_LO_DS:
567 case R_PPC64_TOC16_LO_DS:
568 case R_PPC64_GOT_TPREL16_LO_DS:
569 case R_PPC64_GOT_DTPREL16_LO_DS:
570 return {R_PPC64_ADDR16_LO_DS, TocBiasedVal};
572 // Dynamic Thread pointer biased relocation types.
573 case R_PPC64_DTPREL16:
574 return {R_PPC64_ADDR16, DTPBiasedVal};
575 case R_PPC64_DTPREL16_DS:
576 return {R_PPC64_ADDR16_DS, DTPBiasedVal};
577 case R_PPC64_DTPREL16_HA:
578 return {R_PPC64_ADDR16_HA, DTPBiasedVal};
579 case R_PPC64_DTPREL16_HI:
580 return {R_PPC64_ADDR16_HI, DTPBiasedVal};
581 case R_PPC64_DTPREL16_HIGHER:
582 return {R_PPC64_ADDR16_HIGHER, DTPBiasedVal};
583 case R_PPC64_DTPREL16_HIGHERA:
584 return {R_PPC64_ADDR16_HIGHERA, DTPBiasedVal};
585 case R_PPC64_DTPREL16_HIGHEST:
586 return {R_PPC64_ADDR16_HIGHEST, DTPBiasedVal};
587 case R_PPC64_DTPREL16_HIGHESTA:
588 return {R_PPC64_ADDR16_HIGHESTA, DTPBiasedVal};
589 case R_PPC64_DTPREL16_LO:
590 return {R_PPC64_ADDR16_LO, DTPBiasedVal};
591 case R_PPC64_DTPREL16_LO_DS:
592 return {R_PPC64_ADDR16_LO_DS, DTPBiasedVal};
593 case R_PPC64_DTPREL64:
594 return {R_PPC64_ADDR64, DTPBiasedVal};
601 static bool isTocOptType(RelType Type) {
603 case R_PPC64_GOT16_HA:
604 case R_PPC64_GOT16_LO_DS:
605 case R_PPC64_TOC16_HA:
606 case R_PPC64_TOC16_LO_DS:
607 case R_PPC64_TOC16_LO:
614 void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
615 // We need to save the original relocation type to use in diagnostics, and
616 // use the original type to determine if we should toc-optimize the
617 // instructions being relocated.
618 RelType OriginalType = Type;
619 bool ShouldTocOptimize = isTocOptType(Type);
620 // For dynamic thread pointer relative, toc-relative, and got-indirect
621 // relocations, proceed in terms of the corresponding ADDR16 relocation type.
622 std::tie(Type, Val) = toAddr16Rel(Type, Val);
625 case R_PPC64_ADDR14: {
626 checkAlignment(Loc, Val, 4, Type);
627 // Preserve the AA/LK bits in the branch instruction
628 uint8_t AALK = Loc[3];
629 write16(Loc + 2, (AALK & 3) | (Val & 0xfffc));
633 case R_PPC64_TPREL16:
634 checkInt(Loc, Val, 16, OriginalType);
637 case R_PPC64_ADDR16_DS:
638 case R_PPC64_TPREL16_DS: {
639 checkInt(Loc, Val, 16, OriginalType);
640 // DQ-form instructions use bits 28-31 as part of the instruction encoding
641 // DS-form instructions only use bits 30-31.
642 uint16_t Mask = isDQFormInstruction(readInstrFromHalf16(Loc)) ? 0xF : 0x3;
643 checkAlignment(Loc, lo(Val), Mask + 1, OriginalType);
644 write16(Loc, (read16(Loc) & Mask) | lo(Val));
646 case R_PPC64_ADDR16_HA:
647 case R_PPC64_REL16_HA:
648 case R_PPC64_TPREL16_HA:
649 if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0)
650 writeInstrFromHalf16(Loc, 0x60000000);
652 write16(Loc, ha(Val));
654 case R_PPC64_ADDR16_HI:
655 case R_PPC64_REL16_HI:
656 case R_PPC64_TPREL16_HI:
657 write16(Loc, hi(Val));
659 case R_PPC64_ADDR16_HIGHER:
660 case R_PPC64_TPREL16_HIGHER:
661 write16(Loc, higher(Val));
663 case R_PPC64_ADDR16_HIGHERA:
664 case R_PPC64_TPREL16_HIGHERA:
665 write16(Loc, highera(Val));
667 case R_PPC64_ADDR16_HIGHEST:
668 case R_PPC64_TPREL16_HIGHEST:
669 write16(Loc, highest(Val));
671 case R_PPC64_ADDR16_HIGHESTA:
672 case R_PPC64_TPREL16_HIGHESTA:
673 write16(Loc, highesta(Val));
675 case R_PPC64_ADDR16_LO:
676 case R_PPC64_REL16_LO:
677 case R_PPC64_TPREL16_LO:
678 // When the high-adjusted part of a toc relocation evalutes to 0, it is
679 // changed into a nop. The lo part then needs to be updated to use the
680 // toc-pointer register r2, as the base register.
681 if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0) {
682 uint32_t Instr = readInstrFromHalf16(Loc);
683 if (isInstructionUpdateForm(Instr))
684 error(getErrorLocation(Loc) +
685 "can't toc-optimize an update instruction: 0x" +
687 Instr = (Instr & 0xFFE00000) | 0x00020000;
688 writeInstrFromHalf16(Loc, Instr);
690 write16(Loc, lo(Val));
692 case R_PPC64_ADDR16_LO_DS:
693 case R_PPC64_TPREL16_LO_DS: {
694 // DQ-form instructions use bits 28-31 as part of the instruction encoding
695 // DS-form instructions only use bits 30-31.
696 uint32_t Inst = readInstrFromHalf16(Loc);
697 uint16_t Mask = isDQFormInstruction(Inst) ? 0xF : 0x3;
698 checkAlignment(Loc, lo(Val), Mask + 1, OriginalType);
699 if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0) {
700 // When the high-adjusted part of a toc relocation evalutes to 0, it is
701 // changed into a nop. The lo part then needs to be updated to use the toc
702 // pointer register r2, as the base register.
703 if (isInstructionUpdateForm(Inst))
704 error(getErrorLocation(Loc) +
705 "Can't toc-optimize an update instruction: 0x" +
706 Twine::utohexstr(Inst));
707 Inst = (Inst & 0xFFE0000F) | 0x00020000;
708 writeInstrFromHalf16(Loc, Inst);
710 write16(Loc, (read16(Loc) & Mask) | lo(Val));
714 checkInt(Loc, Val, 32, Type);
722 case R_PPC64_REL14: {
723 uint32_t Mask = 0x0000FFFC;
724 checkInt(Loc, Val, 16, Type);
725 checkAlignment(Loc, Val, 4, Type);
726 write32(Loc, (read32(Loc) & ~Mask) | (Val & Mask));
729 case R_PPC64_REL24: {
730 uint32_t Mask = 0x03FFFFFC;
731 checkInt(Loc, Val, 26, Type);
732 checkAlignment(Loc, Val, 4, Type);
733 write32(Loc, (read32(Loc) & ~Mask) | (Val & Mask));
736 case R_PPC64_DTPREL64:
737 write64(Loc, Val - DynamicThreadPointerOffset);
740 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
744 bool PPC64::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
745 uint64_t BranchAddr, const Symbol &S) const {
746 if (Type != R_PPC64_REL14 && Type != R_PPC64_REL24)
749 // If a function is in the Plt it needs to be called with a call-stub.
753 // If a symbol is a weak undefined and we are compiling an executable
754 // it doesn't need a range-extending thunk since it can't be called.
755 if (S.isUndefWeak() && !Config->Shared)
758 // If the offset exceeds the range of the branch type then it will need
759 // a range-extending thunk.
760 // See the comment in getRelocTargetVA() about R_PPC64_CALL.
761 return !inBranchRange(Type, BranchAddr,
763 getPPC64GlobalEntryToLocalEntryOffset(S.StOther));
766 uint32_t PPC64::getThunkSectionSpacing() const {
767 // See comment in Arch/ARM.cpp for a more detailed explanation of
768 // getThunkSectionSpacing(). For PPC64 we pick the constant here based on
769 // R_PPC64_REL24, which is used by unconditional branch instructions.
770 // 0x2000000 = (1 << 24-1) * 4
774 bool PPC64::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
775 int64_t Offset = Dst - Src;
776 if (Type == R_PPC64_REL14)
777 return isInt<16>(Offset);
778 if (Type == R_PPC64_REL24)
779 return isInt<26>(Offset);
780 llvm_unreachable("unsupported relocation type used in branch");
783 RelExpr PPC64::adjustRelaxExpr(RelType Type, const uint8_t *Data,
784 RelExpr Expr) const {
785 if (Expr == R_RELAX_TLS_GD_TO_IE)
786 return R_RELAX_TLS_GD_TO_IE_GOT_OFF;
787 if (Expr == R_RELAX_TLS_LD_TO_LE)
788 return R_RELAX_TLS_LD_TO_LE_ABS;
792 // Reference: 3.7.4.1 of the 64-bit ELF V2 abi supplement.
793 // The general dynamic code sequence for a global `x` uses 4 instructions.
794 // Instruction Relocation Symbol
795 // addis r3, r2, x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x
796 // addi r3, r3, x@got@tlsgd@l R_PPC64_GOT_TLSGD16_LO x
797 // bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x
798 // R_PPC64_REL24 __tls_get_addr
801 // Relaxing to initial-exec entails:
802 // 1) Convert the addis/addi pair that builds the address of the tls_index
803 // struct for 'x' to an addis/ld pair that loads an offset from a got-entry.
804 // 2) Convert the call to __tls_get_addr to a nop.
805 // 3) Convert the nop following the call to an add of the loaded offset to the
807 // Since the nop must directly follow the call, the R_PPC64_TLSGD relocation is
808 // used as the relaxation hint for both steps 2 and 3.
809 void PPC64::relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const {
811 case R_PPC64_GOT_TLSGD16_HA:
812 // This is relaxed from addis rT, r2, sym@got@tlsgd@ha to
813 // addis rT, r2, sym@got@tprel@ha.
814 relocateOne(Loc, R_PPC64_GOT_TPREL16_HA, Val);
816 case R_PPC64_GOT_TLSGD16_LO: {
817 // Relax from addi r3, rA, sym@got@tlsgd@l to
818 // ld r3, sym@got@tprel@l(rA)
819 uint32_t InputRegister = (readInstrFromHalf16(Loc) & (0x1f << 16));
820 writeInstrFromHalf16(Loc, 0xE8600000 | InputRegister);
821 relocateOne(Loc, R_PPC64_GOT_TPREL16_LO_DS, Val);
825 write32(Loc, 0x60000000); // bl __tls_get_addr(sym@tlsgd) --> nop
826 write32(Loc + 4, 0x7c636A14); // nop --> add r3, r3, r13
829 llvm_unreachable("unsupported relocation for TLS GD to IE relaxation");
833 // The prologue for a split-stack function is expected to look roughly
835 // .Lglobal_entry_point:
836 // # TOC pointer initalization.
838 // .Llocal_entry_point:
839 // # load the __private_ss member of the threads tcbhead.
840 // ld r0,-0x7000-64(r13)
841 // # subtract the functions stack size from the stack pointer.
842 // addis r12, r1, ha(-stack-frame size)
843 // addi r12, r12, l(-stack-frame size)
844 // # compare needed to actual and branch to allocate_more_stack if more
845 // # space is needed, otherwise fallthrough to 'normal' function body.
847 // blt- cr7, .Lallocate_more_stack
849 // -) The allocate_more_stack block might be placed after the split-stack
850 // prologue and the `blt-` replaced with a `bge+ .Lnormal_func_body`
852 // -) If either the addis or addi is not needed due to the stack size being
853 // smaller then 32K or a multiple of 64K they will be replaced with a nop,
854 // but there will always be 2 instructions the linker can overwrite for the
855 // adjusted stack size.
857 // The linkers job here is to increase the stack size used in the addis/addi
858 // pair by split-stack-size-adjust.
859 // addis r12, r1, ha(-stack-frame size - split-stack-adjust-size)
860 // addi r12, r12, l(-stack-frame size - split-stack-adjust-size)
861 bool PPC64::adjustPrologueForCrossSplitStack(uint8_t *Loc, uint8_t *End,
862 uint8_t StOther) const {
863 // If the caller has a global entry point adjust the buffer past it. The start
864 // of the split-stack prologue will be at the local entry point.
865 Loc += getPPC64GlobalEntryToLocalEntryOffset(StOther);
867 // At the very least we expect to see a load of some split-stack data from the
868 // tcb, and 2 instructions that calculate the ending stack address this
869 // function will require. If there is not enough room for at least 3
870 // instructions it can't be a split-stack prologue.
874 // First instruction must be `ld r0, -0x7000-64(r13)`
875 if (read32(Loc) != 0xe80d8fc0)
880 // First instruction can be either an addis if the frame size is larger then
881 // 32K, or an addi if the size is less then 32K.
882 int32_t FirstInstr = read32(Loc + 4);
883 if (getPrimaryOpCode(FirstInstr) == 15) {
884 HiImm = FirstInstr & 0xFFFF;
885 } else if (getPrimaryOpCode(FirstInstr) == 14) {
886 LoImm = FirstInstr & 0xFFFF;
891 // Second instruction is either an addi or a nop. If the first instruction was
892 // an addi then LoImm is set and the second instruction must be a nop.
893 uint32_t SecondInstr = read32(Loc + 8);
894 if (!LoImm && getPrimaryOpCode(SecondInstr) == 14) {
895 LoImm = SecondInstr & 0xFFFF;
896 } else if (SecondInstr != 0x60000000) {
900 // The register operands of the first instruction should be the stack-pointer
901 // (r1) as the input (RA) and r12 as the output (RT). If the second
902 // instruction is not a nop, then it should use r12 as both input and output.
903 auto CheckRegOperands = [](uint32_t Instr, uint8_t ExpectedRT,
904 uint8_t ExpectedRA) {
905 return ((Instr & 0x3E00000) >> 21 == ExpectedRT) &&
906 ((Instr & 0x1F0000) >> 16 == ExpectedRA);
908 if (!CheckRegOperands(FirstInstr, 12, 1))
910 if (SecondInstr != 0x60000000 && !CheckRegOperands(SecondInstr, 12, 12))
913 int32_t StackFrameSize = (HiImm * 65536) + LoImm;
914 // Check that the adjusted size doesn't overflow what we can represent with 2
916 if (StackFrameSize < Config->SplitStackAdjustSize + INT32_MIN) {
917 error(getErrorLocation(Loc) + "split-stack prologue adjustment overflows");
921 int32_t AdjustedStackFrameSize =
922 StackFrameSize - Config->SplitStackAdjustSize;
924 LoImm = AdjustedStackFrameSize & 0xFFFF;
925 HiImm = (AdjustedStackFrameSize + 0x8000) >> 16;
927 write32(Loc + 4, 0x3D810000 | (uint16_t)HiImm);
928 // If the low immediate is zero the second instruction will be a nop.
929 SecondInstr = LoImm ? 0x398C0000 | (uint16_t)LoImm : 0x60000000;
930 write32(Loc + 8, SecondInstr);
933 write32(Loc + 4, (0x39810000) | (uint16_t)LoImm);
934 write32(Loc + 8, 0x60000000);
940 TargetInfo *elf::getPPC64TargetInfo() {