1 //===- X86_64.cpp ---------------------------------------------------------===//
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "InputFiles.h"
12 #include "SyntheticSections.h"
14 #include "lld/Common/ErrorHandler.h"
15 #include "llvm/Object/ELF.h"
16 #include "llvm/Support/Endian.h"
19 using namespace llvm::object;
20 using namespace llvm::support::endian;
21 using namespace llvm::ELF;
23 using namespace lld::elf;
26 template <class ELFT> class X86_64 : public TargetInfo {
29 RelExpr getRelExpr(RelType Type, const Symbol &S,
30 const uint8_t *Loc) const override;
31 RelType getDynRel(RelType Type) const override;
32 void writeGotPltHeader(uint8_t *Buf) const override;
33 void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
34 void writePltHeader(uint8_t *Buf) const override;
35 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
36 int32_t Index, unsigned RelOff) const override;
37 void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
39 RelExpr adjustRelaxExpr(RelType Type, const uint8_t *Data,
40 RelExpr Expr) const override;
41 void relaxGot(uint8_t *Loc, uint64_t Val) const override;
42 void relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
43 void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
44 void relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
45 void relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
46 bool adjustPrologueForCrossSplitStack(uint8_t *Loc,
47 uint8_t *End) const override;
50 void relaxGotNoPic(uint8_t *Loc, uint64_t Val, uint8_t Op,
55 template <class ELFT> X86_64<ELFT>::X86_64() {
56 CopyRel = R_X86_64_COPY;
57 GotRel = R_X86_64_GLOB_DAT;
58 PltRel = R_X86_64_JUMP_SLOT;
59 RelativeRel = R_X86_64_RELATIVE;
60 IRelativeRel = R_X86_64_IRELATIVE;
61 TlsGotRel = R_X86_64_TPOFF64;
62 TlsModuleIndexRel = R_X86_64_DTPMOD64;
63 TlsOffsetRel = R_X86_64_DTPOFF64;
69 TrapInstr = 0xcccccccc; // 0xcc = INT3
71 // Align to the large page size (known as a superpage or huge page).
72 // FreeBSD automatically promotes large, superpage-aligned allocations.
73 DefaultImageBase = 0x200000;
77 RelExpr X86_64<ELFT>::getRelExpr(RelType Type, const Symbol &S,
78 const uint8_t *Loc) const {
79 if (Type == R_X86_64_GOTTPOFF)
80 Config->HasStaticTlsModel = true;
88 case R_X86_64_DTPOFF32:
89 case R_X86_64_DTPOFF64:
91 case R_X86_64_TPOFF32:
107 return R_GOT_FROM_END;
108 case R_X86_64_GOTPCREL:
109 case R_X86_64_GOTPCRELX:
110 case R_X86_64_REX_GOTPCRELX:
111 case R_X86_64_GOTTPOFF:
113 case R_X86_64_GOTOFF64:
114 return R_GOTREL_FROM_END;
115 case R_X86_64_GOTPC32:
116 case R_X86_64_GOTPC64:
117 return R_GOTONLY_PC_FROM_END;
125 template <class ELFT> void X86_64<ELFT>::writeGotPltHeader(uint8_t *Buf) const {
126 // The first entry holds the value of _DYNAMIC. It is not clear why that is
127 // required, but it is documented in the psabi and the glibc dynamic linker
128 // seems to use it (note that this is relevant for linking ld.so, not any
130 write64le(Buf, InX::Dynamic->getVA());
133 template <class ELFT>
134 void X86_64<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &S) const {
135 // See comments in X86::writeGotPlt.
136 write64le(Buf, S.getPltVA() + 6);
139 template <class ELFT> void X86_64<ELFT>::writePltHeader(uint8_t *Buf) const {
140 const uint8_t PltData[] = {
141 0xff, 0x35, 0, 0, 0, 0, // pushq GOTPLT+8(%rip)
142 0xff, 0x25, 0, 0, 0, 0, // jmp *GOTPLT+16(%rip)
143 0x0f, 0x1f, 0x40, 0x00, // nop
145 memcpy(Buf, PltData, sizeof(PltData));
146 uint64_t GotPlt = InX::GotPlt->getVA();
147 uint64_t Plt = InX::Plt->getVA();
148 write32le(Buf + 2, GotPlt - Plt + 2); // GOTPLT+8
149 write32le(Buf + 8, GotPlt - Plt + 4); // GOTPLT+16
152 template <class ELFT>
153 void X86_64<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
154 uint64_t PltEntryAddr, int32_t Index,
155 unsigned RelOff) const {
156 const uint8_t Inst[] = {
157 0xff, 0x25, 0, 0, 0, 0, // jmpq *got(%rip)
158 0x68, 0, 0, 0, 0, // pushq <relocation index>
159 0xe9, 0, 0, 0, 0, // jmpq plt[0]
161 memcpy(Buf, Inst, sizeof(Inst));
163 write32le(Buf + 2, GotPltEntryAddr - PltEntryAddr - 6);
164 write32le(Buf + 7, Index);
165 write32le(Buf + 12, -getPltEntryOffset(Index) - 16);
168 template <class ELFT> RelType X86_64<ELFT>::getDynRel(RelType Type) const {
169 if (Type == R_X86_64_64 || Type == R_X86_64_PC64 || Type == R_X86_64_SIZE32 ||
170 Type == R_X86_64_SIZE64)
172 return R_X86_64_NONE;
175 template <class ELFT>
176 void X86_64<ELFT>::relaxTlsGdToLe(uint8_t *Loc, RelType Type,
177 uint64_t Val) const {
180 // leaq x@tlsgd(%rip), %rdi
183 // call __tls_get_addr@plt
187 const uint8_t Inst[] = {
188 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax
189 0x48, 0x8d, 0x80, 0, 0, 0, 0, // lea x@tpoff,%rax
191 memcpy(Loc - 4, Inst, sizeof(Inst));
193 // The original code used a pc relative relocation and so we have to
194 // compensate for the -4 in had in the addend.
195 write32le(Loc + 8, Val + 4);
198 template <class ELFT>
199 void X86_64<ELFT>::relaxTlsGdToIe(uint8_t *Loc, RelType Type,
200 uint64_t Val) const {
203 // leaq x@tlsgd(%rip), %rdi
206 // call __tls_get_addr@plt
210 const uint8_t Inst[] = {
211 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax
212 0x48, 0x03, 0x05, 0, 0, 0, 0, // addq x@tpoff,%rax
214 memcpy(Loc - 4, Inst, sizeof(Inst));
216 // Both code sequences are PC relatives, but since we are moving the constant
217 // forward by 8 bytes we have to subtract the value by 8.
218 write32le(Loc + 8, Val - 8);
221 // In some conditions, R_X86_64_GOTTPOFF relocation can be optimized to
222 // R_X86_64_TPOFF32 so that it does not use GOT.
223 template <class ELFT>
224 void X86_64<ELFT>::relaxTlsIeToLe(uint8_t *Loc, RelType Type,
225 uint64_t Val) const {
226 uint8_t *Inst = Loc - 3;
227 uint8_t Reg = Loc[-1] >> 3;
228 uint8_t *RegSlot = Loc - 1;
230 // Note that ADD with RSP or R12 is converted to ADD instead of LEA
231 // because LEA with these registers needs 4 bytes to encode and thus
232 // wouldn't fit the space.
234 if (memcmp(Inst, "\x48\x03\x25", 3) == 0) {
235 // "addq foo@gottpoff(%rip),%rsp" -> "addq $foo,%rsp"
236 memcpy(Inst, "\x48\x81\xc4", 3);
237 } else if (memcmp(Inst, "\x4c\x03\x25", 3) == 0) {
238 // "addq foo@gottpoff(%rip),%r12" -> "addq $foo,%r12"
239 memcpy(Inst, "\x49\x81\xc4", 3);
240 } else if (memcmp(Inst, "\x4c\x03", 2) == 0) {
241 // "addq foo@gottpoff(%rip),%r[8-15]" -> "leaq foo(%r[8-15]),%r[8-15]"
242 memcpy(Inst, "\x4d\x8d", 2);
243 *RegSlot = 0x80 | (Reg << 3) | Reg;
244 } else if (memcmp(Inst, "\x48\x03", 2) == 0) {
245 // "addq foo@gottpoff(%rip),%reg -> "leaq foo(%reg),%reg"
246 memcpy(Inst, "\x48\x8d", 2);
247 *RegSlot = 0x80 | (Reg << 3) | Reg;
248 } else if (memcmp(Inst, "\x4c\x8b", 2) == 0) {
249 // "movq foo@gottpoff(%rip),%r[8-15]" -> "movq $foo,%r[8-15]"
250 memcpy(Inst, "\x49\xc7", 2);
251 *RegSlot = 0xc0 | Reg;
252 } else if (memcmp(Inst, "\x48\x8b", 2) == 0) {
253 // "movq foo@gottpoff(%rip),%reg" -> "movq $foo,%reg"
254 memcpy(Inst, "\x48\xc7", 2);
255 *RegSlot = 0xc0 | Reg;
257 error(getErrorLocation(Loc - 3) +
258 "R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions only");
261 // The original code used a PC relative relocation.
262 // Need to compensate for the -4 it had in the addend.
263 write32le(Loc, Val + 4);
266 template <class ELFT>
267 void X86_64<ELFT>::relaxTlsLdToLe(uint8_t *Loc, RelType Type,
268 uint64_t Val) const {
270 // leaq bar@tlsld(%rip), %rdi
271 // callq __tls_get_addr@PLT
272 // leaq bar@dtpoff(%rax), %rcx
277 // leaq bar@tpoff(%rax), %rcx
278 if (Type == R_X86_64_DTPOFF64) {
282 if (Type == R_X86_64_DTPOFF32) {
287 const uint8_t Inst[] = {
288 0x66, 0x66, // .word 0x6666
290 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0,%rax
292 memcpy(Loc - 3, Inst, sizeof(Inst));
295 template <class ELFT>
296 void X86_64<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
299 checkUInt(Loc, Val, 8, Type);
303 checkUInt(Loc, Val, 16, Type);
307 checkUInt(Loc, Val, 32, Type);
311 case R_X86_64_TPOFF32:
313 case R_X86_64_GOTPC32:
314 case R_X86_64_GOTPCREL:
315 case R_X86_64_GOTPCRELX:
316 case R_X86_64_REX_GOTPCRELX:
318 case R_X86_64_GOTTPOFF:
322 case R_X86_64_DTPOFF32:
323 case R_X86_64_SIZE32:
324 checkInt(Loc, Val, 32, Type);
328 case R_X86_64_DTPOFF64:
329 case R_X86_64_GLOB_DAT:
331 case R_X86_64_SIZE64:
333 case R_X86_64_GOTOFF64:
334 case R_X86_64_GOTPC64:
338 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
342 template <class ELFT>
343 RelExpr X86_64<ELFT>::adjustRelaxExpr(RelType Type, const uint8_t *Data,
344 RelExpr RelExpr) const {
345 if (Type != R_X86_64_GOTPCRELX && Type != R_X86_64_REX_GOTPCRELX)
347 const uint8_t Op = Data[-2];
348 const uint8_t ModRm = Data[-1];
350 // FIXME: When PIC is disabled and foo is defined locally in the
351 // lower 32 bit address space, memory operand in mov can be converted into
352 // immediate operand. Otherwise, mov must be changed to lea. We support only
353 // latter relaxation at this moment.
355 return R_RELAX_GOT_PC;
357 // Relax call and jmp.
358 if (Op == 0xff && (ModRm == 0x15 || ModRm == 0x25))
359 return R_RELAX_GOT_PC;
361 // Relaxation of test, adc, add, and, cmp, or, sbb, sub, xor.
362 // If PIC then no relaxation is available.
363 // We also don't relax test/binop instructions without REX byte,
364 // they are 32bit operations and not common to have.
365 assert(Type == R_X86_64_REX_GOTPCRELX);
366 return Config->Pic ? RelExpr : R_RELAX_GOT_PC_NOPIC;
369 // A subset of relaxations can only be applied for no-PIC. This method
370 // handles such relaxations. Instructions encoding information was taken from:
371 // "Intel 64 and IA-32 Architectures Software Developer's Manual V2"
372 // (http://www.intel.com/content/dam/www/public/us/en/documents/manuals/
373 // 64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf)
374 template <class ELFT>
375 void X86_64<ELFT>::relaxGotNoPic(uint8_t *Loc, uint64_t Val, uint8_t Op,
376 uint8_t ModRm) const {
377 const uint8_t Rex = Loc[-3];
378 // Convert "test %reg, foo@GOTPCREL(%rip)" to "test $foo, %reg".
380 // See "TEST-Logical Compare" (4-428 Vol. 2B),
381 // TEST r/m64, r64 uses "full" ModR / M byte (no opcode extension).
383 // ModR/M byte has form XX YYY ZZZ, where
384 // YYY is MODRM.reg(register 2), ZZZ is MODRM.rm(register 1).
385 // XX has different meanings:
386 // 00: The operand's memory address is in reg1.
387 // 01: The operand's memory address is reg1 + a byte-sized displacement.
388 // 10: The operand's memory address is reg1 + a word-sized displacement.
389 // 11: The operand is reg1 itself.
390 // If an instruction requires only one operand, the unused reg2 field
391 // holds extra opcode bits rather than a register code
392 // 0xC0 == 11 000 000 binary.
393 // 0x38 == 00 111 000 binary.
394 // We transfer reg2 to reg1 here as operand.
395 // See "2.1.3 ModR/M and SIB Bytes" (Vol. 2A 2-3).
396 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3; // ModR/M byte.
398 // Change opcode from TEST r/m64, r64 to TEST r/m64, imm32
399 // See "TEST-Logical Compare" (4-428 Vol. 2B).
402 // Move R bit to the B bit in REX byte.
403 // REX byte is encoded as 0100WRXB, where
404 // 0100 is 4bit fixed pattern.
405 // REX.W When 1, a 64-bit operand size is used. Otherwise, when 0, the
406 // default operand size is used (which is 32-bit for most but not all
408 // REX.R This 1-bit value is an extension to the MODRM.reg field.
409 // REX.X This 1-bit value is an extension to the SIB.index field.
410 // REX.B This 1-bit value is an extension to the MODRM.rm field or the
412 // See "2.2.1.2 More on REX Prefix Fields " (2-8 Vol. 2A).
413 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2;
418 // If we are here then we need to relax the adc, add, and, cmp, or, sbb, sub
419 // or xor operations.
421 // Convert "binop foo@GOTPCREL(%rip), %reg" to "binop $foo, %reg".
422 // Logic is close to one for test instruction above, but we also
423 // write opcode extension here, see below for details.
424 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3 | (Op & 0x3c); // ModR/M byte.
426 // Primary opcode is 0x81, opcode extension is one of:
427 // 000b = ADD, 001b is OR, 010b is ADC, 011b is SBB,
428 // 100b is AND, 101b is SUB, 110b is XOR, 111b is CMP.
429 // This value was wrote to MODRM.reg in a line above.
430 // See "3.2 INSTRUCTIONS (A-M)" (Vol. 2A 3-15),
431 // "INSTRUCTION SET REFERENCE, N-Z" (Vol. 2B 4-1) for
432 // descriptions about each operation.
434 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2;
438 template <class ELFT>
439 void X86_64<ELFT>::relaxGot(uint8_t *Loc, uint64_t Val) const {
440 const uint8_t Op = Loc[-2];
441 const uint8_t ModRm = Loc[-1];
443 // Convert "mov foo@GOTPCREL(%rip),%reg" to "lea foo(%rip),%reg".
451 // We are relaxing a rip relative to an absolute, so compensate
452 // for the old -4 addend.
453 assert(!Config->Pic);
454 relaxGotNoPic(Loc, Val + 4, Op, ModRm);
458 // Convert call/jmp instructions.
460 // ABI says we can convert "call *foo@GOTPCREL(%rip)" to "nop; call foo".
461 // Instead we convert to "addr32 call foo" where addr32 is an instruction
462 // prefix. That makes result expression to be a single instruction.
463 Loc[-2] = 0x67; // addr32 prefix
464 Loc[-1] = 0xe8; // call
469 // Convert "jmp *foo@GOTPCREL(%rip)" to "jmp foo; nop".
470 // jmp doesn't return, so it is fine to use nop here, it is just a stub.
471 assert(ModRm == 0x25);
472 Loc[-2] = 0xe9; // jmp
473 Loc[3] = 0x90; // nop
474 write32le(Loc - 1, Val + 1);
477 // This anonymous namespace works around a warning bug in
478 // old versions of gcc. See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56480
481 // A split-stack prologue starts by checking the amount of stack remaining
482 // in one of two ways:
483 // A) Comparing of the stack pointer to a field in the tcb.
484 // B) Or a load of a stack pointer offset with an lea to r10 or r11.
486 bool X86_64<ELF64LE>::adjustPrologueForCrossSplitStack(uint8_t *Loc,
487 uint8_t *End) const {
488 // Replace "cmp %fs:0x70,%rsp" and subsequent branch
489 // with "stc, nopl 0x0(%rax,%rax,1)"
490 if (Loc + 8 < End && memcmp(Loc, "\x64\x48\x3b\x24\x25", 4) == 0) {
491 memcpy(Loc, "\xf9\x0f\x1f\x84\x00\x00\x00\x00", 8);
495 // Adjust "lea -0x200(%rsp),%r10" to lea "-0x4200(%rsp),%r10"
496 if (Loc + 7 < End && memcmp(Loc, "\x4c\x8d\x94\x24\x00\xfe\xff", 7) == 0) {
497 memcpy(Loc, "\x4c\x8d\x94\x24\x00\xbe\xff", 7);
501 // Adjust "lea -0x200(%rsp),%r11" to lea "-0x4200(%rsp),%r11"
502 if (Loc + 7 < End && memcmp(Loc, "\x4c\x8d\x9c\x24\x00\xfe\xff", 7) == 0) {
503 memcpy(Loc, "\x4c\x8d\x9c\x24\x00\xbe\xff", 7);
510 bool X86_64<ELF32LE>::adjustPrologueForCrossSplitStack(uint8_t *Loc,
511 uint8_t *End) const {
512 llvm_unreachable("Target doesn't support split stacks.");
517 // These nonstandard PLT entries are to migtigate Spectre v2 security
518 // vulnerability. In order to mitigate Spectre v2, we want to avoid indirect
519 // branch instructions such as `jmp *GOTPLT(%rip)`. So, in the following PLT
520 // entries, we use a CALL followed by MOV and RET to do the same thing as an
521 // indirect jump. That instruction sequence is so-called "retpoline".
523 // We have two types of retpoline PLTs as a size optimization. If `-z now`
524 // is specified, all dynamic symbols are resolved at load-time. Thus, when
525 // that option is given, we can omit code for symbol lazy resolution.
527 template <class ELFT> class Retpoline : public X86_64<ELFT> {
530 void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
531 void writePltHeader(uint8_t *Buf) const override;
532 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
533 int32_t Index, unsigned RelOff) const override;
536 template <class ELFT> class RetpolineZNow : public X86_64<ELFT> {
539 void writeGotPlt(uint8_t *Buf, const Symbol &S) const override {}
540 void writePltHeader(uint8_t *Buf) const override;
541 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
542 int32_t Index, unsigned RelOff) const override;
546 template <class ELFT> Retpoline<ELFT>::Retpoline() {
547 TargetInfo::PltHeaderSize = 48;
548 TargetInfo::PltEntrySize = 32;
551 template <class ELFT>
552 void Retpoline<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &S) const {
553 write64le(Buf, S.getPltVA() + 17);
556 template <class ELFT> void Retpoline<ELFT>::writePltHeader(uint8_t *Buf) const {
557 const uint8_t Insn[] = {
558 0xff, 0x35, 0, 0, 0, 0, // 0: pushq GOTPLT+8(%rip)
559 0x4c, 0x8b, 0x1d, 0, 0, 0, 0, // 6: mov GOTPLT+16(%rip), %r11
560 0xe8, 0x0e, 0x00, 0x00, 0x00, // d: callq next
561 0xf3, 0x90, // 12: loop: pause
562 0x0f, 0xae, 0xe8, // 14: lfence
563 0xeb, 0xf9, // 17: jmp loop
564 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, // 19: int3; .align 16
565 0x4c, 0x89, 0x1c, 0x24, // 20: next: mov %r11, (%rsp)
567 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, // 25: int3; padding
568 0xcc, 0xcc, 0xcc, 0xcc, // 2c: int3; padding
570 memcpy(Buf, Insn, sizeof(Insn));
572 uint64_t GotPlt = InX::GotPlt->getVA();
573 uint64_t Plt = InX::Plt->getVA();
574 write32le(Buf + 2, GotPlt - Plt - 6 + 8);
575 write32le(Buf + 9, GotPlt - Plt - 13 + 16);
578 template <class ELFT>
579 void Retpoline<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
580 uint64_t PltEntryAddr, int32_t Index,
581 unsigned RelOff) const {
582 const uint8_t Insn[] = {
583 0x4c, 0x8b, 0x1d, 0, 0, 0, 0, // 0: mov foo@GOTPLT(%rip), %r11
584 0xe8, 0, 0, 0, 0, // 7: callq plt+0x20
585 0xe9, 0, 0, 0, 0, // c: jmp plt+0x12
586 0x68, 0, 0, 0, 0, // 11: pushq <relocation index>
587 0xe9, 0, 0, 0, 0, // 16: jmp plt+0
588 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, // 1b: int3; padding
590 memcpy(Buf, Insn, sizeof(Insn));
592 uint64_t Off = TargetInfo::getPltEntryOffset(Index);
594 write32le(Buf + 3, GotPltEntryAddr - PltEntryAddr - 7);
595 write32le(Buf + 8, -Off - 12 + 32);
596 write32le(Buf + 13, -Off - 17 + 18);
597 write32le(Buf + 18, Index);
598 write32le(Buf + 23, -Off - 27);
601 template <class ELFT> RetpolineZNow<ELFT>::RetpolineZNow() {
602 TargetInfo::PltHeaderSize = 32;
603 TargetInfo::PltEntrySize = 16;
606 template <class ELFT>
607 void RetpolineZNow<ELFT>::writePltHeader(uint8_t *Buf) const {
608 const uint8_t Insn[] = {
609 0xe8, 0x0b, 0x00, 0x00, 0x00, // 0: call next
610 0xf3, 0x90, // 5: loop: pause
611 0x0f, 0xae, 0xe8, // 7: lfence
612 0xeb, 0xf9, // a: jmp loop
613 0xcc, 0xcc, 0xcc, 0xcc, // c: int3; .align 16
614 0x4c, 0x89, 0x1c, 0x24, // 10: next: mov %r11, (%rsp)
616 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, // 15: int3; padding
617 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, // 1a: int3; padding
618 0xcc, // 1f: int3; padding
620 memcpy(Buf, Insn, sizeof(Insn));
623 template <class ELFT>
624 void RetpolineZNow<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
625 uint64_t PltEntryAddr, int32_t Index,
626 unsigned RelOff) const {
627 const uint8_t Insn[] = {
628 0x4c, 0x8b, 0x1d, 0, 0, 0, 0, // mov foo@GOTPLT(%rip), %r11
629 0xe9, 0, 0, 0, 0, // jmp plt+0
630 0xcc, 0xcc, 0xcc, 0xcc, // int3; padding
632 memcpy(Buf, Insn, sizeof(Insn));
634 write32le(Buf + 3, GotPltEntryAddr - PltEntryAddr - 7);
635 write32le(Buf + 8, -TargetInfo::getPltEntryOffset(Index) - 12);
638 template <class ELFT> static TargetInfo *getTargetInfo() {
639 if (Config->ZRetpolineplt) {
641 static RetpolineZNow<ELFT> T;
644 static Retpoline<ELFT> T;
648 static X86_64<ELFT> T;
652 TargetInfo *elf::getX32TargetInfo() { return getTargetInfo<ELF32LE>(); }
653 TargetInfo *elf::getX86_64TargetInfo() { return getTargetInfo<ELF64LE>(); }