1 //===- Target.cpp ---------------------------------------------------------===//
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Machine-specific things, such as applying relocations, creation of
11 // GOT or PLT entries, etc., are handled in this file.
13 // Refer the ELF spec for the single letter variables, S, A or P, used
16 // Some functions defined in this file has "relaxTls" as part of their names.
17 // They do peephole optimization for TLS variables by rewriting instructions.
18 // They are not part of the ABI but optional optimization, so you can skip
19 // them if you are not interested in how TLS variables are optimized.
20 // See the following paper for the details.
22 // Ulrich Drepper, ELF Handling For Thread-Local Storage
23 // http://www.akkadia.org/drepper/tls.pdf
25 //===----------------------------------------------------------------------===//
29 #include "InputFiles.h"
31 #include "OutputSections.h"
32 #include "SymbolTable.h"
34 #include "SyntheticSections.h"
37 #include "llvm/ADT/ArrayRef.h"
38 #include "llvm/Object/ELF.h"
39 #include "llvm/Support/ELF.h"
40 #include "llvm/Support/Endian.h"
43 using namespace llvm::object;
44 using namespace llvm::support::endian;
45 using namespace llvm::ELF;
47 std::string lld::toString(uint32_t Type) {
48 return getELFRelocationTypeName(elf::Config->EMachine, Type);
56 static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
57 static void or32be(uint8_t *P, int32_t V) { write32be(P, read32be(P) | V); }
59 template <class ELFT> static std::string getErrorLoc(uint8_t *Loc) {
60 for (InputSectionData *D : Symtab<ELFT>::X->Sections) {
61 auto *IS = dyn_cast_or_null<InputSection<ELFT>>(D);
62 if (!IS || !IS->OutSec)
65 uint8_t *ISLoc = cast<OutputSection<ELFT>>(IS->OutSec)->Loc + IS->OutSecOff;
66 if (ISLoc <= Loc && Loc < ISLoc + IS->getSize())
67 return IS->getLocation(Loc - ISLoc) + ": ";
72 static std::string getErrorLocation(uint8_t *Loc) {
73 switch (Config->EKind) {
75 return getErrorLoc<ELF32LE>(Loc);
77 return getErrorLoc<ELF32BE>(Loc);
79 return getErrorLoc<ELF64LE>(Loc);
81 return getErrorLoc<ELF64BE>(Loc);
83 llvm_unreachable("unknown ELF type");
88 static void checkInt(uint8_t *Loc, int64_t V, uint32_t Type) {
90 error(getErrorLocation(Loc) + "relocation " + toString(Type) +
95 static void checkUInt(uint8_t *Loc, uint64_t V, uint32_t Type) {
97 error(getErrorLocation(Loc) + "relocation " + toString(Type) +
101 template <unsigned N>
102 static void checkIntUInt(uint8_t *Loc, uint64_t V, uint32_t Type) {
103 if (!isInt<N>(V) && !isUInt<N>(V))
104 error(getErrorLocation(Loc) + "relocation " + toString(Type) +
108 template <unsigned N>
109 static void checkAlignment(uint8_t *Loc, uint64_t V, uint32_t Type) {
110 if ((V & (N - 1)) != 0)
111 error(getErrorLocation(Loc) + "improper alignment for relocation " +
116 class X86TargetInfo final : public TargetInfo {
119 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
120 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
121 void writeGotPltHeader(uint8_t *Buf) const override;
122 uint32_t getDynRel(uint32_t Type) const override;
123 bool isTlsLocalDynamicRel(uint32_t Type) const override;
124 bool isTlsGlobalDynamicRel(uint32_t Type) const override;
125 bool isTlsInitialExecRel(uint32_t Type) const override;
126 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
127 void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override;
128 void writePltHeader(uint8_t *Buf) const override;
129 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
130 int32_t Index, unsigned RelOff) const override;
131 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
133 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
134 RelExpr Expr) const override;
135 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
136 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
137 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
138 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
141 template <class ELFT> class X86_64TargetInfo final : public TargetInfo {
144 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
145 bool isPicRel(uint32_t Type) const override;
146 bool isTlsLocalDynamicRel(uint32_t Type) const override;
147 bool isTlsGlobalDynamicRel(uint32_t Type) const override;
148 bool isTlsInitialExecRel(uint32_t Type) const override;
149 void writeGotPltHeader(uint8_t *Buf) const override;
150 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
151 void writePltHeader(uint8_t *Buf) const override;
152 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
153 int32_t Index, unsigned RelOff) const override;
154 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
156 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
157 RelExpr Expr) const override;
158 void relaxGot(uint8_t *Loc, uint64_t Val) const override;
159 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
160 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
161 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
162 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
165 void relaxGotNoPic(uint8_t *Loc, uint64_t Val, uint8_t Op,
166 uint8_t ModRm) const;
169 class PPCTargetInfo final : public TargetInfo {
172 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
173 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
176 class PPC64TargetInfo final : public TargetInfo {
179 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
180 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
181 int32_t Index, unsigned RelOff) const override;
182 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
185 class AArch64TargetInfo final : public TargetInfo {
188 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
189 bool isPicRel(uint32_t Type) const override;
190 bool isTlsInitialExecRel(uint32_t Type) const override;
191 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
192 void writePltHeader(uint8_t *Buf) const override;
193 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
194 int32_t Index, unsigned RelOff) const override;
195 bool usesOnlyLowPageBits(uint32_t Type) const override;
196 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
197 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
198 RelExpr Expr) const override;
199 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
200 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
201 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
204 class AMDGPUTargetInfo final : public TargetInfo {
207 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
208 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
211 class ARMTargetInfo final : public TargetInfo {
214 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
215 bool isPicRel(uint32_t Type) const override;
216 uint32_t getDynRel(uint32_t Type) const override;
217 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
218 bool isTlsLocalDynamicRel(uint32_t Type) const override;
219 bool isTlsGlobalDynamicRel(uint32_t Type) const override;
220 bool isTlsInitialExecRel(uint32_t Type) const override;
221 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
222 void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override;
223 void writePltHeader(uint8_t *Buf) const override;
224 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
225 int32_t Index, unsigned RelOff) const override;
226 RelExpr getThunkExpr(RelExpr Expr, uint32_t RelocType, const InputFile &File,
227 const SymbolBody &S) const override;
228 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
231 template <class ELFT> class MipsTargetInfo final : public TargetInfo {
234 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
235 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
236 bool isPicRel(uint32_t Type) const override;
237 uint32_t getDynRel(uint32_t Type) const override;
238 bool isTlsLocalDynamicRel(uint32_t Type) const override;
239 bool isTlsGlobalDynamicRel(uint32_t Type) const override;
240 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
241 void writePltHeader(uint8_t *Buf) const override;
242 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
243 int32_t Index, unsigned RelOff) const override;
244 RelExpr getThunkExpr(RelExpr Expr, uint32_t RelocType, const InputFile &File,
245 const SymbolBody &S) const override;
246 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
247 bool usesOnlyLowPageBits(uint32_t Type) const override;
249 } // anonymous namespace
251 TargetInfo *createTarget() {
252 switch (Config->EMachine) {
255 return make<X86TargetInfo>();
257 return make<AArch64TargetInfo>();
259 return make<AMDGPUTargetInfo>();
261 return make<ARMTargetInfo>();
263 switch (Config->EKind) {
265 return make<MipsTargetInfo<ELF32LE>>();
267 return make<MipsTargetInfo<ELF32BE>>();
269 return make<MipsTargetInfo<ELF64LE>>();
271 return make<MipsTargetInfo<ELF64BE>>();
273 fatal("unsupported MIPS target");
276 return make<PPCTargetInfo>();
278 return make<PPC64TargetInfo>();
280 if (Config->EKind == ELF32LEKind)
281 return make<X86_64TargetInfo<ELF32LE>>();
282 return make<X86_64TargetInfo<ELF64LE>>();
284 fatal("unknown target machine");
287 TargetInfo::~TargetInfo() {}
289 uint64_t TargetInfo::getImplicitAddend(const uint8_t *Buf,
290 uint32_t Type) const {
294 bool TargetInfo::usesOnlyLowPageBits(uint32_t Type) const { return false; }
296 RelExpr TargetInfo::getThunkExpr(RelExpr Expr, uint32_t RelocType,
297 const InputFile &File,
298 const SymbolBody &S) const {
302 bool TargetInfo::isTlsInitialExecRel(uint32_t Type) const { return false; }
304 bool TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { return false; }
306 bool TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { return false; }
308 void TargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const {
312 RelExpr TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
313 RelExpr Expr) const {
317 void TargetInfo::relaxGot(uint8_t *Loc, uint64_t Val) const {
318 llvm_unreachable("Should not have claimed to be relaxable");
321 void TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type,
322 uint64_t Val) const {
323 llvm_unreachable("Should not have claimed to be relaxable");
326 void TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type,
327 uint64_t Val) const {
328 llvm_unreachable("Should not have claimed to be relaxable");
331 void TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type,
332 uint64_t Val) const {
333 llvm_unreachable("Should not have claimed to be relaxable");
336 void TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type,
337 uint64_t Val) const {
338 llvm_unreachable("Should not have claimed to be relaxable");
341 X86TargetInfo::X86TargetInfo() {
342 CopyRel = R_386_COPY;
343 GotRel = R_386_GLOB_DAT;
344 PltRel = R_386_JUMP_SLOT;
345 IRelativeRel = R_386_IRELATIVE;
346 RelativeRel = R_386_RELATIVE;
347 TlsGotRel = R_386_TLS_TPOFF;
348 TlsModuleIndexRel = R_386_TLS_DTPMOD32;
349 TlsOffsetRel = R_386_TLS_DTPOFF32;
357 RelExpr X86TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
371 return R_GOTONLY_PC_FROM_END;
376 case R_386_TLS_GOTIE:
377 return R_GOT_FROM_END;
379 return R_GOTREL_FROM_END;
382 case R_386_TLS_LE_32:
387 RelExpr X86TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
388 RelExpr Expr) const {
392 case R_RELAX_TLS_GD_TO_IE:
393 return R_RELAX_TLS_GD_TO_IE_END;
394 case R_RELAX_TLS_GD_TO_LE:
395 return R_RELAX_TLS_GD_TO_LE_NEG;
399 void X86TargetInfo::writeGotPltHeader(uint8_t *Buf) const {
400 write32le(Buf, In<ELF32LE>::Dynamic->getVA());
403 void X86TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &S) const {
404 // Entries in .got.plt initially points back to the corresponding
405 // PLT entries with a fixed offset to skip the first instruction.
406 write32le(Buf, S.getPltVA<ELF32LE>() + 6);
409 void X86TargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const {
410 // An x86 entry is the address of the ifunc resolver function.
411 write32le(Buf, S.getVA<ELF32LE>());
414 uint32_t X86TargetInfo::getDynRel(uint32_t Type) const {
415 if (Type == R_386_TLS_LE)
416 return R_386_TLS_TPOFF;
417 if (Type == R_386_TLS_LE_32)
418 return R_386_TLS_TPOFF32;
422 bool X86TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const {
423 return Type == R_386_TLS_GD;
426 bool X86TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const {
427 return Type == R_386_TLS_LDO_32 || Type == R_386_TLS_LDM;
430 bool X86TargetInfo::isTlsInitialExecRel(uint32_t Type) const {
431 return Type == R_386_TLS_IE || Type == R_386_TLS_GOTIE;
434 void X86TargetInfo::writePltHeader(uint8_t *Buf) const {
435 // Executable files and shared object files have
436 // separate procedure linkage tables.
438 const uint8_t V[] = {
439 0xff, 0xb3, 0x04, 0x00, 0x00, 0x00, // pushl 4(%ebx)
440 0xff, 0xa3, 0x08, 0x00, 0x00, 0x00, // jmp *8(%ebx)
441 0x90, 0x90, 0x90, 0x90 // nop; nop; nop; nop
443 memcpy(Buf, V, sizeof(V));
447 const uint8_t PltData[] = {
448 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushl (GOT+4)
449 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *(GOT+8)
450 0x90, 0x90, 0x90, 0x90 // nop; nop; nop; nop
452 memcpy(Buf, PltData, sizeof(PltData));
453 uint32_t Got = In<ELF32LE>::GotPlt->getVA();
454 write32le(Buf + 2, Got + 4);
455 write32le(Buf + 8, Got + 8);
458 void X86TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr,
459 uint64_t PltEntryAddr, int32_t Index,
460 unsigned RelOff) const {
461 const uint8_t Inst[] = {
462 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, // jmp *foo_in_GOT|*foo@GOT(%ebx)
463 0x68, 0x00, 0x00, 0x00, 0x00, // pushl $reloc_offset
464 0xe9, 0x00, 0x00, 0x00, 0x00 // jmp .PLT0@PC
466 memcpy(Buf, Inst, sizeof(Inst));
468 // jmp *foo@GOT(%ebx) or jmp *foo_in_GOT
469 Buf[1] = Config->Pic ? 0xa3 : 0x25;
470 uint32_t Got = In<ELF32LE>::GotPlt->getVA();
471 write32le(Buf + 2, Config->Shared ? GotEntryAddr - Got : GotEntryAddr);
472 write32le(Buf + 7, RelOff);
473 write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16);
476 uint64_t X86TargetInfo::getImplicitAddend(const uint8_t *Buf,
477 uint32_t Type) const {
483 return read16le(Buf);
492 return read32le(Buf);
496 void X86TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
497 uint64_t Val) const {
498 checkInt<32>(Loc, Val, Type);
500 // R_386_PC16 and R_386_16 are not part of the current i386 psABI. They are
501 // used by 16-bit x86 objects, like boot loaders.
502 if (Type == R_386_16 || Type == R_386_PC16) {
509 void X86TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type,
510 uint64_t Val) const {
512 // leal x@tlsgd(, %ebx, 1),
513 // call __tls_get_addr@plt
516 // subl $x@ntpoff,%eax
517 const uint8_t Inst[] = {
518 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax
519 0x81, 0xe8, 0x00, 0x00, 0x00, 0x00 // subl 0(%ebx), %eax
521 memcpy(Loc - 3, Inst, sizeof(Inst));
522 relocateOne(Loc + 5, R_386_32, Val);
525 void X86TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type,
526 uint64_t Val) const {
528 // leal x@tlsgd(, %ebx, 1),
529 // call __tls_get_addr@plt
532 // addl x@gotntpoff(%ebx), %eax
533 const uint8_t Inst[] = {
534 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax
535 0x03, 0x83, 0x00, 0x00, 0x00, 0x00 // addl 0(%ebx), %eax
537 memcpy(Loc - 3, Inst, sizeof(Inst));
538 relocateOne(Loc + 5, R_386_32, Val);
541 // In some conditions, relocations can be optimized to avoid using GOT.
542 // This function does that for Initial Exec to Local Exec case.
543 void X86TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type,
544 uint64_t Val) const {
545 // Ulrich's document section 6.2 says that @gotntpoff can
546 // be used with MOVL or ADDL instructions.
547 // @indntpoff is similar to @gotntpoff, but for use in
548 // position dependent code.
549 uint8_t Reg = (Loc[-1] >> 3) & 7;
551 if (Type == R_386_TLS_IE) {
552 if (Loc[-1] == 0xa1) {
553 // "movl foo@indntpoff,%eax" -> "movl $foo,%eax"
554 // This case is different from the generic case below because
555 // this is a 5 byte instruction while below is 6 bytes.
557 } else if (Loc[-2] == 0x8b) {
558 // "movl foo@indntpoff,%reg" -> "movl $foo,%reg"
560 Loc[-1] = 0xc0 | Reg;
562 // "addl foo@indntpoff,%reg" -> "addl $foo,%reg"
564 Loc[-1] = 0xc0 | Reg;
567 assert(Type == R_386_TLS_GOTIE);
568 if (Loc[-2] == 0x8b) {
569 // "movl foo@gottpoff(%rip),%reg" -> "movl $foo,%reg"
571 Loc[-1] = 0xc0 | Reg;
573 // "addl foo@gotntpoff(%rip),%reg" -> "leal foo(%reg),%reg"
575 Loc[-1] = 0x80 | (Reg << 3) | Reg;
578 relocateOne(Loc, R_386_TLS_LE, Val);
581 void X86TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type,
582 uint64_t Val) const {
583 if (Type == R_386_TLS_LDO_32) {
584 relocateOne(Loc, R_386_TLS_LE, Val);
589 // leal foo(%reg),%eax
590 // call ___tls_get_addr
594 // leal 0(%esi,1),%esi
595 const uint8_t Inst[] = {
596 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0,%eax
598 0x8d, 0x74, 0x26, 0x00 // leal 0(%esi,1),%esi
600 memcpy(Loc - 2, Inst, sizeof(Inst));
603 template <class ELFT> X86_64TargetInfo<ELFT>::X86_64TargetInfo() {
604 CopyRel = R_X86_64_COPY;
605 GotRel = R_X86_64_GLOB_DAT;
606 PltRel = R_X86_64_JUMP_SLOT;
607 RelativeRel = R_X86_64_RELATIVE;
608 IRelativeRel = R_X86_64_IRELATIVE;
609 TlsGotRel = R_X86_64_TPOFF64;
610 TlsModuleIndexRel = R_X86_64_DTPMOD64;
611 TlsOffsetRel = R_X86_64_DTPOFF64;
617 // Align to the large page size (known as a superpage or huge page).
618 // FreeBSD automatically promotes large, superpage-aligned allocations.
619 DefaultImageBase = 0x200000;
622 template <class ELFT>
623 RelExpr X86_64TargetInfo<ELFT>::getRelExpr(uint32_t Type,
624 const SymbolBody &S) const {
628 case R_X86_64_TPOFF32:
634 case R_X86_64_SIZE32:
635 case R_X86_64_SIZE64:
644 return R_GOT_FROM_END;
645 case R_X86_64_GOTPCREL:
646 case R_X86_64_GOTPCRELX:
647 case R_X86_64_REX_GOTPCRELX:
648 case R_X86_64_GOTTPOFF:
655 template <class ELFT>
656 void X86_64TargetInfo<ELFT>::writeGotPltHeader(uint8_t *Buf) const {
657 // The first entry holds the value of _DYNAMIC. It is not clear why that is
658 // required, but it is documented in the psabi and the glibc dynamic linker
659 // seems to use it (note that this is relevant for linking ld.so, not any
661 write64le(Buf, In<ELFT>::Dynamic->getVA());
664 template <class ELFT>
665 void X86_64TargetInfo<ELFT>::writeGotPlt(uint8_t *Buf,
666 const SymbolBody &S) const {
667 // See comments in X86TargetInfo::writeGotPlt.
668 write32le(Buf, S.getPltVA<ELFT>() + 6);
671 template <class ELFT>
672 void X86_64TargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const {
673 const uint8_t PltData[] = {
674 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushq GOT+8(%rip)
675 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *GOT+16(%rip)
676 0x0f, 0x1f, 0x40, 0x00 // nopl 0x0(rax)
678 memcpy(Buf, PltData, sizeof(PltData));
679 uint64_t Got = In<ELFT>::GotPlt->getVA();
680 uint64_t Plt = In<ELFT>::Plt->getVA();
681 write32le(Buf + 2, Got - Plt + 2); // GOT+8
682 write32le(Buf + 8, Got - Plt + 4); // GOT+16
685 template <class ELFT>
686 void X86_64TargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr,
687 uint64_t PltEntryAddr, int32_t Index,
688 unsigned RelOff) const {
689 const uint8_t Inst[] = {
690 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmpq *got(%rip)
691 0x68, 0x00, 0x00, 0x00, 0x00, // pushq <relocation index>
692 0xe9, 0x00, 0x00, 0x00, 0x00 // jmpq plt[0]
694 memcpy(Buf, Inst, sizeof(Inst));
696 write32le(Buf + 2, GotEntryAddr - PltEntryAddr - 6);
697 write32le(Buf + 7, Index);
698 write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16);
701 template <class ELFT>
702 bool X86_64TargetInfo<ELFT>::isPicRel(uint32_t Type) const {
703 return Type != R_X86_64_PC32 && Type != R_X86_64_32;
706 template <class ELFT>
707 bool X86_64TargetInfo<ELFT>::isTlsInitialExecRel(uint32_t Type) const {
708 return Type == R_X86_64_GOTTPOFF;
711 template <class ELFT>
712 bool X86_64TargetInfo<ELFT>::isTlsGlobalDynamicRel(uint32_t Type) const {
713 return Type == R_X86_64_TLSGD;
716 template <class ELFT>
717 bool X86_64TargetInfo<ELFT>::isTlsLocalDynamicRel(uint32_t Type) const {
718 return Type == R_X86_64_DTPOFF32 || Type == R_X86_64_DTPOFF64 ||
719 Type == R_X86_64_TLSLD;
722 template <class ELFT>
723 void X86_64TargetInfo<ELFT>::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type,
724 uint64_t Val) const {
727 // leaq x@tlsgd(%rip), %rdi
730 // call __tls_get_addr@plt
734 const uint8_t Inst[] = {
735 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax
736 0x48, 0x8d, 0x80, 0x00, 0x00, 0x00, 0x00 // lea x@tpoff,%rax
738 memcpy(Loc - 4, Inst, sizeof(Inst));
739 // The original code used a pc relative relocation and so we have to
740 // compensate for the -4 in had in the addend.
741 relocateOne(Loc + 8, R_X86_64_TPOFF32, Val + 4);
744 template <class ELFT>
745 void X86_64TargetInfo<ELFT>::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type,
746 uint64_t Val) const {
749 // leaq x@tlsgd(%rip), %rdi
752 // call __tls_get_addr@plt
756 const uint8_t Inst[] = {
757 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax
758 0x48, 0x03, 0x05, 0x00, 0x00, 0x00, 0x00 // addq x@tpoff,%rax
760 memcpy(Loc - 4, Inst, sizeof(Inst));
761 // Both code sequences are PC relatives, but since we are moving the constant
762 // forward by 8 bytes we have to subtract the value by 8.
763 relocateOne(Loc + 8, R_X86_64_PC32, Val - 8);
766 // In some conditions, R_X86_64_GOTTPOFF relocation can be optimized to
767 // R_X86_64_TPOFF32 so that it does not use GOT.
768 template <class ELFT>
769 void X86_64TargetInfo<ELFT>::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type,
770 uint64_t Val) const {
771 uint8_t *Inst = Loc - 3;
772 uint8_t Reg = Loc[-1] >> 3;
773 uint8_t *RegSlot = Loc - 1;
775 // Note that ADD with RSP or R12 is converted to ADD instead of LEA
776 // because LEA with these registers needs 4 bytes to encode and thus
777 // wouldn't fit the space.
779 if (memcmp(Inst, "\x48\x03\x25", 3) == 0) {
780 // "addq foo@gottpoff(%rip),%rsp" -> "addq $foo,%rsp"
781 memcpy(Inst, "\x48\x81\xc4", 3);
782 } else if (memcmp(Inst, "\x4c\x03\x25", 3) == 0) {
783 // "addq foo@gottpoff(%rip),%r12" -> "addq $foo,%r12"
784 memcpy(Inst, "\x49\x81\xc4", 3);
785 } else if (memcmp(Inst, "\x4c\x03", 2) == 0) {
786 // "addq foo@gottpoff(%rip),%r[8-15]" -> "leaq foo(%r[8-15]),%r[8-15]"
787 memcpy(Inst, "\x4d\x8d", 2);
788 *RegSlot = 0x80 | (Reg << 3) | Reg;
789 } else if (memcmp(Inst, "\x48\x03", 2) == 0) {
790 // "addq foo@gottpoff(%rip),%reg -> "leaq foo(%reg),%reg"
791 memcpy(Inst, "\x48\x8d", 2);
792 *RegSlot = 0x80 | (Reg << 3) | Reg;
793 } else if (memcmp(Inst, "\x4c\x8b", 2) == 0) {
794 // "movq foo@gottpoff(%rip),%r[8-15]" -> "movq $foo,%r[8-15]"
795 memcpy(Inst, "\x49\xc7", 2);
796 *RegSlot = 0xc0 | Reg;
797 } else if (memcmp(Inst, "\x48\x8b", 2) == 0) {
798 // "movq foo@gottpoff(%rip),%reg" -> "movq $foo,%reg"
799 memcpy(Inst, "\x48\xc7", 2);
800 *RegSlot = 0xc0 | Reg;
802 error(getErrorLocation(Loc - 3) +
803 "R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions only");
806 // The original code used a PC relative relocation.
807 // Need to compensate for the -4 it had in the addend.
808 relocateOne(Loc, R_X86_64_TPOFF32, Val + 4);
811 template <class ELFT>
812 void X86_64TargetInfo<ELFT>::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type,
813 uint64_t Val) const {
815 // leaq bar@tlsld(%rip), %rdi
816 // callq __tls_get_addr@PLT
817 // leaq bar@dtpoff(%rax), %rcx
822 // leaq bar@tpoff(%rax), %rcx
823 if (Type == R_X86_64_DTPOFF64) {
827 if (Type == R_X86_64_DTPOFF32) {
828 relocateOne(Loc, R_X86_64_TPOFF32, Val);
832 const uint8_t Inst[] = {
833 0x66, 0x66, // .word 0x6666
835 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00 // mov %fs:0,%rax
837 memcpy(Loc - 3, Inst, sizeof(Inst));
840 template <class ELFT>
841 void X86_64TargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type,
842 uint64_t Val) const {
845 checkUInt<32>(Loc, Val, Type);
849 case R_X86_64_TPOFF32:
851 case R_X86_64_GOTPCREL:
852 case R_X86_64_GOTPCRELX:
853 case R_X86_64_REX_GOTPCRELX:
855 case R_X86_64_GOTTPOFF:
859 case R_X86_64_DTPOFF32:
860 case R_X86_64_SIZE32:
861 checkInt<32>(Loc, Val, Type);
865 case R_X86_64_DTPOFF64:
866 case R_X86_64_GLOB_DAT:
868 case R_X86_64_SIZE64:
873 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
877 template <class ELFT>
878 RelExpr X86_64TargetInfo<ELFT>::adjustRelaxExpr(uint32_t Type,
880 RelExpr RelExpr) const {
881 if (Type != R_X86_64_GOTPCRELX && Type != R_X86_64_REX_GOTPCRELX)
883 const uint8_t Op = Data[-2];
884 const uint8_t ModRm = Data[-1];
885 // FIXME: When PIC is disabled and foo is defined locally in the
886 // lower 32 bit address space, memory operand in mov can be converted into
887 // immediate operand. Otherwise, mov must be changed to lea. We support only
888 // latter relaxation at this moment.
890 return R_RELAX_GOT_PC;
891 // Relax call and jmp.
892 if (Op == 0xff && (ModRm == 0x15 || ModRm == 0x25))
893 return R_RELAX_GOT_PC;
895 // Relaxation of test, adc, add, and, cmp, or, sbb, sub, xor.
896 // If PIC then no relaxation is available.
897 // We also don't relax test/binop instructions without REX byte,
898 // they are 32bit operations and not common to have.
899 assert(Type == R_X86_64_REX_GOTPCRELX);
900 return Config->Pic ? RelExpr : R_RELAX_GOT_PC_NOPIC;
903 // A subset of relaxations can only be applied for no-PIC. This method
904 // handles such relaxations. Instructions encoding information was taken from:
905 // "Intel 64 and IA-32 Architectures Software Developer's Manual V2"
906 // (http://www.intel.com/content/dam/www/public/us/en/documents/manuals/
907 // 64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf)
908 template <class ELFT>
909 void X86_64TargetInfo<ELFT>::relaxGotNoPic(uint8_t *Loc, uint64_t Val,
910 uint8_t Op, uint8_t ModRm) const {
911 const uint8_t Rex = Loc[-3];
912 // Convert "test %reg, foo@GOTPCREL(%rip)" to "test $foo, %reg".
914 // See "TEST-Logical Compare" (4-428 Vol. 2B),
915 // TEST r/m64, r64 uses "full" ModR / M byte (no opcode extension).
917 // ModR/M byte has form XX YYY ZZZ, where
918 // YYY is MODRM.reg(register 2), ZZZ is MODRM.rm(register 1).
919 // XX has different meanings:
920 // 00: The operand's memory address is in reg1.
921 // 01: The operand's memory address is reg1 + a byte-sized displacement.
922 // 10: The operand's memory address is reg1 + a word-sized displacement.
923 // 11: The operand is reg1 itself.
924 // If an instruction requires only one operand, the unused reg2 field
925 // holds extra opcode bits rather than a register code
926 // 0xC0 == 11 000 000 binary.
927 // 0x38 == 00 111 000 binary.
928 // We transfer reg2 to reg1 here as operand.
929 // See "2.1.3 ModR/M and SIB Bytes" (Vol. 2A 2-3).
930 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3; // ModR/M byte.
932 // Change opcode from TEST r/m64, r64 to TEST r/m64, imm32
933 // See "TEST-Logical Compare" (4-428 Vol. 2B).
936 // Move R bit to the B bit in REX byte.
937 // REX byte is encoded as 0100WRXB, where
938 // 0100 is 4bit fixed pattern.
939 // REX.W When 1, a 64-bit operand size is used. Otherwise, when 0, the
940 // default operand size is used (which is 32-bit for most but not all
942 // REX.R This 1-bit value is an extension to the MODRM.reg field.
943 // REX.X This 1-bit value is an extension to the SIB.index field.
944 // REX.B This 1-bit value is an extension to the MODRM.rm field or the
946 // See "2.2.1.2 More on REX Prefix Fields " (2-8 Vol. 2A).
947 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2;
948 relocateOne(Loc, R_X86_64_PC32, Val);
952 // If we are here then we need to relax the adc, add, and, cmp, or, sbb, sub
953 // or xor operations.
955 // Convert "binop foo@GOTPCREL(%rip), %reg" to "binop $foo, %reg".
956 // Logic is close to one for test instruction above, but we also
957 // write opcode extension here, see below for details.
958 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3 | (Op & 0x3c); // ModR/M byte.
960 // Primary opcode is 0x81, opcode extension is one of:
961 // 000b = ADD, 001b is OR, 010b is ADC, 011b is SBB,
962 // 100b is AND, 101b is SUB, 110b is XOR, 111b is CMP.
963 // This value was wrote to MODRM.reg in a line above.
964 // See "3.2 INSTRUCTIONS (A-M)" (Vol. 2A 3-15),
965 // "INSTRUCTION SET REFERENCE, N-Z" (Vol. 2B 4-1) for
966 // descriptions about each operation.
968 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2;
969 relocateOne(Loc, R_X86_64_PC32, Val);
972 template <class ELFT>
973 void X86_64TargetInfo<ELFT>::relaxGot(uint8_t *Loc, uint64_t Val) const {
974 const uint8_t Op = Loc[-2];
975 const uint8_t ModRm = Loc[-1];
977 // Convert "mov foo@GOTPCREL(%rip),%reg" to "lea foo(%rip),%reg".
980 relocateOne(Loc, R_X86_64_PC32, Val);
985 // We are relaxing a rip relative to an absolute, so compensate
986 // for the old -4 addend.
987 assert(!Config->Pic);
988 relaxGotNoPic(Loc, Val + 4, Op, ModRm);
992 // Convert call/jmp instructions.
994 // ABI says we can convert "call *foo@GOTPCREL(%rip)" to "nop; call foo".
995 // Instead we convert to "addr32 call foo" where addr32 is an instruction
996 // prefix. That makes result expression to be a single instruction.
997 Loc[-2] = 0x67; // addr32 prefix
998 Loc[-1] = 0xe8; // call
999 relocateOne(Loc, R_X86_64_PC32, Val);
1003 // Convert "jmp *foo@GOTPCREL(%rip)" to "jmp foo; nop".
1004 // jmp doesn't return, so it is fine to use nop here, it is just a stub.
1005 assert(ModRm == 0x25);
1006 Loc[-2] = 0xe9; // jmp
1007 Loc[3] = 0x90; // nop
1008 relocateOne(Loc - 1, R_X86_64_PC32, Val + 1);
1011 // Relocation masks following the #lo(value), #hi(value), #ha(value),
1012 // #higher(value), #highera(value), #highest(value), and #highesta(value)
1013 // macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi
1015 static uint16_t applyPPCLo(uint64_t V) { return V; }
1016 static uint16_t applyPPCHi(uint64_t V) { return V >> 16; }
1017 static uint16_t applyPPCHa(uint64_t V) { return (V + 0x8000) >> 16; }
1018 static uint16_t applyPPCHigher(uint64_t V) { return V >> 32; }
1019 static uint16_t applyPPCHighera(uint64_t V) { return (V + 0x8000) >> 32; }
1020 static uint16_t applyPPCHighest(uint64_t V) { return V >> 48; }
1021 static uint16_t applyPPCHighesta(uint64_t V) { return (V + 0x8000) >> 48; }
1023 PPCTargetInfo::PPCTargetInfo() {}
1025 void PPCTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
1026 uint64_t Val) const {
1028 case R_PPC_ADDR16_HA:
1029 write16be(Loc, applyPPCHa(Val));
1031 case R_PPC_ADDR16_LO:
1032 write16be(Loc, applyPPCLo(Val));
1036 write32be(Loc, Val);
1039 or32be(Loc, Val & 0x3FFFFFC);
1042 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
1046 RelExpr PPCTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
1056 PPC64TargetInfo::PPC64TargetInfo() {
1057 PltRel = GotRel = R_PPC64_GLOB_DAT;
1058 RelativeRel = R_PPC64_RELATIVE;
1060 GotPltEntrySize = 8;
1064 // We need 64K pages (at least under glibc/Linux, the loader won't
1065 // set different permissions on a finer granularity than that).
1066 DefaultMaxPageSize = 65536;
1068 // The PPC64 ELF ABI v1 spec, says:
1070 // It is normally desirable to put segments with different characteristics
1071 // in separate 256 Mbyte portions of the address space, to give the
1072 // operating system full paging flexibility in the 64-bit address space.
1074 // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers
1075 // use 0x10000000 as the starting address.
1076 DefaultImageBase = 0x10000000;
1079 static uint64_t PPC64TocOffset = 0x8000;
1081 uint64_t getPPC64TocBase() {
1082 // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The
1083 // TOC starts where the first of these sections starts. We always create a
1084 // .got when we see a relocation that uses it, so for us the start is always
1086 uint64_t TocVA = In<ELF64BE>::Got->getVA();
1088 // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000
1089 // thus permitting a full 64 Kbytes segment. Note that the glibc startup
1090 // code (crt1.o) assumes that you can get from the TOC base to the
1091 // start of the .toc section with only a single (signed) 16-bit relocation.
1092 return TocVA + PPC64TocOffset;
1095 RelExpr PPC64TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
1100 case R_PPC64_TOC16_DS:
1101 case R_PPC64_TOC16_HA:
1102 case R_PPC64_TOC16_HI:
1103 case R_PPC64_TOC16_LO:
1104 case R_PPC64_TOC16_LO_DS:
1109 return R_PPC_PLT_OPD;
1113 void PPC64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr,
1114 uint64_t PltEntryAddr, int32_t Index,
1115 unsigned RelOff) const {
1116 uint64_t Off = GotEntryAddr - getPPC64TocBase();
1118 // FIXME: What we should do, in theory, is get the offset of the function
1119 // descriptor in the .opd section, and use that as the offset from %r2 (the
1120 // TOC-base pointer). Instead, we have the GOT-entry offset, and that will
1121 // be a pointer to the function descriptor in the .opd section. Using
1122 // this scheme is simpler, but requires an extra indirection per PLT dispatch.
1124 write32be(Buf, 0xf8410028); // std %r2, 40(%r1)
1125 write32be(Buf + 4, 0x3d620000 | applyPPCHa(Off)); // addis %r11, %r2, X@ha
1126 write32be(Buf + 8, 0xe98b0000 | applyPPCLo(Off)); // ld %r12, X@l(%r11)
1127 write32be(Buf + 12, 0xe96c0000); // ld %r11,0(%r12)
1128 write32be(Buf + 16, 0x7d6903a6); // mtctr %r11
1129 write32be(Buf + 20, 0xe84c0008); // ld %r2,8(%r12)
1130 write32be(Buf + 24, 0xe96c0010); // ld %r11,16(%r12)
1131 write32be(Buf + 28, 0x4e800420); // bctr
1134 static std::pair<uint32_t, uint64_t> toAddr16Rel(uint32_t Type, uint64_t Val) {
1135 uint64_t V = Val - PPC64TocOffset;
1138 return {R_PPC64_ADDR16, V};
1139 case R_PPC64_TOC16_DS:
1140 return {R_PPC64_ADDR16_DS, V};
1141 case R_PPC64_TOC16_HA:
1142 return {R_PPC64_ADDR16_HA, V};
1143 case R_PPC64_TOC16_HI:
1144 return {R_PPC64_ADDR16_HI, V};
1145 case R_PPC64_TOC16_LO:
1146 return {R_PPC64_ADDR16_LO, V};
1147 case R_PPC64_TOC16_LO_DS:
1148 return {R_PPC64_ADDR16_LO_DS, V};
1154 void PPC64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
1155 uint64_t Val) const {
1156 // For a TOC-relative relocation, proceed in terms of the corresponding
1157 // ADDR16 relocation type.
1158 std::tie(Type, Val) = toAddr16Rel(Type, Val);
1161 case R_PPC64_ADDR14: {
1162 checkAlignment<4>(Loc, Val, Type);
1163 // Preserve the AA/LK bits in the branch instruction
1164 uint8_t AALK = Loc[3];
1165 write16be(Loc + 2, (AALK & 3) | (Val & 0xfffc));
1168 case R_PPC64_ADDR16:
1169 checkInt<16>(Loc, Val, Type);
1170 write16be(Loc, Val);
1172 case R_PPC64_ADDR16_DS:
1173 checkInt<16>(Loc, Val, Type);
1174 write16be(Loc, (read16be(Loc) & 3) | (Val & ~3));
1176 case R_PPC64_ADDR16_HA:
1177 case R_PPC64_REL16_HA:
1178 write16be(Loc, applyPPCHa(Val));
1180 case R_PPC64_ADDR16_HI:
1181 case R_PPC64_REL16_HI:
1182 write16be(Loc, applyPPCHi(Val));
1184 case R_PPC64_ADDR16_HIGHER:
1185 write16be(Loc, applyPPCHigher(Val));
1187 case R_PPC64_ADDR16_HIGHERA:
1188 write16be(Loc, applyPPCHighera(Val));
1190 case R_PPC64_ADDR16_HIGHEST:
1191 write16be(Loc, applyPPCHighest(Val));
1193 case R_PPC64_ADDR16_HIGHESTA:
1194 write16be(Loc, applyPPCHighesta(Val));
1196 case R_PPC64_ADDR16_LO:
1197 write16be(Loc, applyPPCLo(Val));
1199 case R_PPC64_ADDR16_LO_DS:
1200 case R_PPC64_REL16_LO:
1201 write16be(Loc, (read16be(Loc) & 3) | (applyPPCLo(Val) & ~3));
1203 case R_PPC64_ADDR32:
1205 checkInt<32>(Loc, Val, Type);
1206 write32be(Loc, Val);
1208 case R_PPC64_ADDR64:
1211 write64be(Loc, Val);
1213 case R_PPC64_REL24: {
1214 uint32_t Mask = 0x03FFFFFC;
1215 checkInt<24>(Loc, Val, Type);
1216 write32be(Loc, (read32be(Loc) & ~Mask) | (Val & Mask));
1220 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
1224 AArch64TargetInfo::AArch64TargetInfo() {
1225 CopyRel = R_AARCH64_COPY;
1226 RelativeRel = R_AARCH64_RELATIVE;
1227 IRelativeRel = R_AARCH64_IRELATIVE;
1228 GotRel = R_AARCH64_GLOB_DAT;
1229 PltRel = R_AARCH64_JUMP_SLOT;
1230 TlsDescRel = R_AARCH64_TLSDESC;
1231 TlsGotRel = R_AARCH64_TLS_TPREL64;
1233 GotPltEntrySize = 8;
1236 DefaultMaxPageSize = 65536;
1238 // It doesn't seem to be documented anywhere, but tls on aarch64 uses variant
1239 // 1 of the tls structures and the tcb size is 16.
1243 RelExpr AArch64TargetInfo::getRelExpr(uint32_t Type,
1244 const SymbolBody &S) const {
1248 case R_AARCH64_TLSDESC_ADR_PAGE21:
1249 return R_TLSDESC_PAGE;
1250 case R_AARCH64_TLSDESC_LD64_LO12_NC:
1251 case R_AARCH64_TLSDESC_ADD_LO12_NC:
1253 case R_AARCH64_TLSDESC_CALL:
1254 return R_TLSDESC_CALL;
1255 case R_AARCH64_TLSLE_ADD_TPREL_HI12:
1256 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
1258 case R_AARCH64_CALL26:
1259 case R_AARCH64_CONDBR19:
1260 case R_AARCH64_JUMP26:
1261 case R_AARCH64_TSTBR14:
1263 case R_AARCH64_PREL16:
1264 case R_AARCH64_PREL32:
1265 case R_AARCH64_PREL64:
1266 case R_AARCH64_ADR_PREL_LO21:
1268 case R_AARCH64_ADR_PREL_PG_HI21:
1270 case R_AARCH64_LD64_GOT_LO12_NC:
1271 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
1273 case R_AARCH64_ADR_GOT_PAGE:
1274 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
1275 return R_GOT_PAGE_PC;
1279 RelExpr AArch64TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
1280 RelExpr Expr) const {
1281 if (Expr == R_RELAX_TLS_GD_TO_IE) {
1282 if (Type == R_AARCH64_TLSDESC_ADR_PAGE21)
1283 return R_RELAX_TLS_GD_TO_IE_PAGE_PC;
1284 return R_RELAX_TLS_GD_TO_IE_ABS;
1289 bool AArch64TargetInfo::usesOnlyLowPageBits(uint32_t Type) const {
1293 case R_AARCH64_ADD_ABS_LO12_NC:
1294 case R_AARCH64_LD64_GOT_LO12_NC:
1295 case R_AARCH64_LDST128_ABS_LO12_NC:
1296 case R_AARCH64_LDST16_ABS_LO12_NC:
1297 case R_AARCH64_LDST32_ABS_LO12_NC:
1298 case R_AARCH64_LDST64_ABS_LO12_NC:
1299 case R_AARCH64_LDST8_ABS_LO12_NC:
1300 case R_AARCH64_TLSDESC_ADD_LO12_NC:
1301 case R_AARCH64_TLSDESC_LD64_LO12_NC:
1302 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
1307 bool AArch64TargetInfo::isTlsInitialExecRel(uint32_t Type) const {
1308 return Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 ||
1309 Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
1312 bool AArch64TargetInfo::isPicRel(uint32_t Type) const {
1313 return Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64;
1316 void AArch64TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
1317 write64le(Buf, In<ELF64LE>::Plt->getVA());
1320 // Page(Expr) is the page address of the expression Expr, defined
1321 // as (Expr & ~0xFFF). (This applies even if the machine page size
1322 // supported by the platform has a different value.)
1323 uint64_t getAArch64Page(uint64_t Expr) {
1324 return Expr & (~static_cast<uint64_t>(0xFFF));
1327 void AArch64TargetInfo::writePltHeader(uint8_t *Buf) const {
1328 const uint8_t PltData[] = {
1329 0xf0, 0x7b, 0xbf, 0xa9, // stp x16, x30, [sp,#-16]!
1330 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[2]))
1331 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[2]))]
1332 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[2]))
1333 0x20, 0x02, 0x1f, 0xd6, // br x17
1334 0x1f, 0x20, 0x03, 0xd5, // nop
1335 0x1f, 0x20, 0x03, 0xd5, // nop
1336 0x1f, 0x20, 0x03, 0xd5 // nop
1338 memcpy(Buf, PltData, sizeof(PltData));
1340 uint64_t Got = In<ELF64LE>::GotPlt->getVA();
1341 uint64_t Plt = In<ELF64LE>::Plt->getVA();
1342 relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21,
1343 getAArch64Page(Got + 16) - getAArch64Page(Plt + 4));
1344 relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16);
1345 relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16);
1348 void AArch64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr,
1349 uint64_t PltEntryAddr, int32_t Index,
1350 unsigned RelOff) const {
1351 const uint8_t Inst[] = {
1352 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n]))
1353 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[n]))]
1354 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[n]))
1355 0x20, 0x02, 0x1f, 0xd6 // br x17
1357 memcpy(Buf, Inst, sizeof(Inst));
1359 relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21,
1360 getAArch64Page(GotEntryAddr) - getAArch64Page(PltEntryAddr));
1361 relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotEntryAddr);
1362 relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotEntryAddr);
1365 static void write32AArch64Addr(uint8_t *L, uint64_t Imm) {
1366 uint32_t ImmLo = (Imm & 0x3) << 29;
1367 uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
1368 uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3);
1369 write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi);
1372 // Return the bits [Start, End] from Val shifted Start bits.
1373 // For instance, getBits(0xF0, 4, 8) returns 0xF.
1374 static uint64_t getBits(uint64_t Val, int Start, int End) {
1375 uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1;
1376 return (Val >> Start) & Mask;
1379 // Update the immediate field in a AARCH64 ldr, str, and add instruction.
1380 static void or32AArch64Imm(uint8_t *L, uint64_t Imm) {
1381 or32le(L, (Imm & 0xFFF) << 10);
1384 void AArch64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
1385 uint64_t Val) const {
1387 case R_AARCH64_ABS16:
1388 case R_AARCH64_PREL16:
1389 checkIntUInt<16>(Loc, Val, Type);
1390 write16le(Loc, Val);
1392 case R_AARCH64_ABS32:
1393 case R_AARCH64_PREL32:
1394 checkIntUInt<32>(Loc, Val, Type);
1395 write32le(Loc, Val);
1397 case R_AARCH64_ABS64:
1398 case R_AARCH64_GLOB_DAT:
1399 case R_AARCH64_PREL64:
1400 write64le(Loc, Val);
1402 case R_AARCH64_ADD_ABS_LO12_NC:
1403 or32AArch64Imm(Loc, Val);
1405 case R_AARCH64_ADR_GOT_PAGE:
1406 case R_AARCH64_ADR_PREL_PG_HI21:
1407 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
1408 case R_AARCH64_TLSDESC_ADR_PAGE21:
1409 checkInt<33>(Loc, Val, Type);
1410 write32AArch64Addr(Loc, Val >> 12);
1412 case R_AARCH64_ADR_PREL_LO21:
1413 checkInt<21>(Loc, Val, Type);
1414 write32AArch64Addr(Loc, Val);
1416 case R_AARCH64_CALL26:
1417 case R_AARCH64_JUMP26:
1418 checkInt<28>(Loc, Val, Type);
1419 or32le(Loc, (Val & 0x0FFFFFFC) >> 2);
1421 case R_AARCH64_CONDBR19:
1422 checkInt<21>(Loc, Val, Type);
1423 or32le(Loc, (Val & 0x1FFFFC) << 3);
1425 case R_AARCH64_LD64_GOT_LO12_NC:
1426 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
1427 case R_AARCH64_TLSDESC_LD64_LO12_NC:
1428 checkAlignment<8>(Loc, Val, Type);
1429 or32le(Loc, (Val & 0xFF8) << 7);
1431 case R_AARCH64_LDST8_ABS_LO12_NC:
1432 or32AArch64Imm(Loc, getBits(Val, 0, 11));
1434 case R_AARCH64_LDST16_ABS_LO12_NC:
1435 or32AArch64Imm(Loc, getBits(Val, 1, 11));
1437 case R_AARCH64_LDST32_ABS_LO12_NC:
1438 or32AArch64Imm(Loc, getBits(Val, 2, 11));
1440 case R_AARCH64_LDST64_ABS_LO12_NC:
1441 or32AArch64Imm(Loc, getBits(Val, 3, 11));
1443 case R_AARCH64_LDST128_ABS_LO12_NC:
1444 or32AArch64Imm(Loc, getBits(Val, 4, 11));
1446 case R_AARCH64_MOVW_UABS_G0_NC:
1447 or32le(Loc, (Val & 0xFFFF) << 5);
1449 case R_AARCH64_MOVW_UABS_G1_NC:
1450 or32le(Loc, (Val & 0xFFFF0000) >> 11);
1452 case R_AARCH64_MOVW_UABS_G2_NC:
1453 or32le(Loc, (Val & 0xFFFF00000000) >> 27);
1455 case R_AARCH64_MOVW_UABS_G3:
1456 or32le(Loc, (Val & 0xFFFF000000000000) >> 43);
1458 case R_AARCH64_TSTBR14:
1459 checkInt<16>(Loc, Val, Type);
1460 or32le(Loc, (Val & 0xFFFC) << 3);
1462 case R_AARCH64_TLSLE_ADD_TPREL_HI12:
1463 checkInt<24>(Loc, Val, Type);
1464 or32AArch64Imm(Loc, Val >> 12);
1466 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
1467 case R_AARCH64_TLSDESC_ADD_LO12_NC:
1468 or32AArch64Imm(Loc, Val);
1471 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
1475 void AArch64TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type,
1476 uint64_t Val) const {
1477 // TLSDESC Global-Dynamic relocation are in the form:
1478 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21]
1479 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12_NC]
1480 // add x0, x0, :tlsdesc_los:v [_AARCH64_TLSDESC_ADD_LO12_NC]
1481 // .tlsdesccall [R_AARCH64_TLSDESC_CALL]
1483 // And it can optimized to:
1484 // movz x0, #0x0, lsl #16
1488 checkUInt<32>(Loc, Val, Type);
1491 case R_AARCH64_TLSDESC_ADD_LO12_NC:
1492 case R_AARCH64_TLSDESC_CALL:
1493 write32le(Loc, 0xd503201f); // nop
1495 case R_AARCH64_TLSDESC_ADR_PAGE21:
1496 write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz
1498 case R_AARCH64_TLSDESC_LD64_LO12_NC:
1499 write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk
1502 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
1506 void AArch64TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type,
1507 uint64_t Val) const {
1508 // TLSDESC Global-Dynamic relocation are in the form:
1509 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21]
1510 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12_NC]
1511 // add x0, x0, :tlsdesc_los:v [_AARCH64_TLSDESC_ADD_LO12_NC]
1512 // .tlsdesccall [R_AARCH64_TLSDESC_CALL]
1514 // And it can optimized to:
1515 // adrp x0, :gottprel:v
1516 // ldr x0, [x0, :gottprel_lo12:v]
1521 case R_AARCH64_TLSDESC_ADD_LO12_NC:
1522 case R_AARCH64_TLSDESC_CALL:
1523 write32le(Loc, 0xd503201f); // nop
1525 case R_AARCH64_TLSDESC_ADR_PAGE21:
1526 write32le(Loc, 0x90000000); // adrp
1527 relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val);
1529 case R_AARCH64_TLSDESC_LD64_LO12_NC:
1530 write32le(Loc, 0xf9400000); // ldr
1531 relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val);
1534 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
1538 void AArch64TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type,
1539 uint64_t Val) const {
1540 checkUInt<32>(Loc, Val, Type);
1542 if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) {
1544 uint32_t RegNo = read32le(Loc) & 0x1f;
1545 write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5));
1548 if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) {
1550 uint32_t RegNo = read32le(Loc) & 0x1f;
1551 write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5));
1554 llvm_unreachable("invalid relocation for TLS IE to LE relaxation");
1557 AMDGPUTargetInfo::AMDGPUTargetInfo() {
1558 RelativeRel = R_AMDGPU_REL64;
1559 GotRel = R_AMDGPU_ABS64;
1563 void AMDGPUTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
1564 uint64_t Val) const {
1566 case R_AMDGPU_ABS32:
1567 case R_AMDGPU_GOTPCREL:
1568 case R_AMDGPU_GOTPCREL32_LO:
1569 case R_AMDGPU_REL32:
1570 case R_AMDGPU_REL32_LO:
1571 write32le(Loc, Val);
1573 case R_AMDGPU_ABS64:
1574 write64le(Loc, Val);
1576 case R_AMDGPU_GOTPCREL32_HI:
1577 case R_AMDGPU_REL32_HI:
1578 write32le(Loc, Val >> 32);
1581 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
1585 RelExpr AMDGPUTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
1587 case R_AMDGPU_ABS32:
1588 case R_AMDGPU_ABS64:
1590 case R_AMDGPU_REL32:
1591 case R_AMDGPU_REL32_LO:
1592 case R_AMDGPU_REL32_HI:
1594 case R_AMDGPU_GOTPCREL:
1595 case R_AMDGPU_GOTPCREL32_LO:
1596 case R_AMDGPU_GOTPCREL32_HI:
1599 fatal("do not know how to handle relocation " + Twine(Type));
1603 ARMTargetInfo::ARMTargetInfo() {
1604 CopyRel = R_ARM_COPY;
1605 RelativeRel = R_ARM_RELATIVE;
1606 IRelativeRel = R_ARM_IRELATIVE;
1607 GotRel = R_ARM_GLOB_DAT;
1608 PltRel = R_ARM_JUMP_SLOT;
1609 TlsGotRel = R_ARM_TLS_TPOFF32;
1610 TlsModuleIndexRel = R_ARM_TLS_DTPMOD32;
1611 TlsOffsetRel = R_ARM_TLS_DTPOFF32;
1613 GotPltEntrySize = 4;
1616 // ARM uses Variant 1 TLS
1621 RelExpr ARMTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
1625 case R_ARM_THM_JUMP11:
1632 case R_ARM_THM_JUMP19:
1633 case R_ARM_THM_JUMP24:
1634 case R_ARM_THM_CALL:
1636 case R_ARM_GOTOFF32:
1637 // (S + A) - GOT_ORG
1639 case R_ARM_GOT_BREL:
1640 // GOT(S) + A - GOT_ORG
1642 case R_ARM_GOT_PREL:
1643 case R_ARM_TLS_IE32:
1647 return Config->Target1Rel ? R_PC : R_ABS;
1649 if (Config->Target2 == Target2Policy::Rel)
1651 if (Config->Target2 == Target2Policy::Abs)
1654 case R_ARM_TLS_GD32:
1656 case R_ARM_TLS_LDM32:
1658 case R_ARM_BASE_PREL:
1660 // FIXME: currently B(S) assumed to be .got, this may not hold for all
1662 return R_GOTONLY_PC;
1663 case R_ARM_MOVW_PREL_NC:
1664 case R_ARM_MOVT_PREL:
1666 case R_ARM_THM_MOVW_PREL_NC:
1667 case R_ARM_THM_MOVT_PREL:
1671 case R_ARM_TLS_LE32:
1676 bool ARMTargetInfo::isPicRel(uint32_t Type) const {
1677 return (Type == R_ARM_TARGET1 && !Config->Target1Rel) ||
1678 (Type == R_ARM_ABS32);
1681 uint32_t ARMTargetInfo::getDynRel(uint32_t Type) const {
1682 if (Type == R_ARM_TARGET1 && !Config->Target1Rel)
1684 if (Type == R_ARM_ABS32)
1686 // Keep it going with a dummy value so that we can find more reloc errors.
1690 void ARMTargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
1691 write32le(Buf, In<ELF32LE>::Plt->getVA());
1694 void ARMTargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const {
1695 // An ARM entry is the address of the ifunc resolver function.
1696 write32le(Buf, S.getVA<ELF32LE>());
1699 void ARMTargetInfo::writePltHeader(uint8_t *Buf) const {
1700 const uint8_t PltData[] = {
1701 0x04, 0xe0, 0x2d, 0xe5, // str lr, [sp,#-4]!
1702 0x04, 0xe0, 0x9f, 0xe5, // ldr lr, L2
1703 0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr
1704 0x08, 0xf0, 0xbe, 0xe5, // ldr pc, [lr, #8]
1705 0x00, 0x00, 0x00, 0x00, // L2: .word &(.got.plt) - L1 - 8
1707 memcpy(Buf, PltData, sizeof(PltData));
1708 uint64_t GotPlt = In<ELF32LE>::GotPlt->getVA();
1709 uint64_t L1 = In<ELF32LE>::Plt->getVA() + 8;
1710 write32le(Buf + 16, GotPlt - L1 - 8);
1713 void ARMTargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr,
1714 uint64_t PltEntryAddr, int32_t Index,
1715 unsigned RelOff) const {
1716 // FIXME: Using simple code sequence with simple relocations.
1717 // There is a more optimal sequence but it requires support for the group
1718 // relocations. See ELF for the ARM Architecture Appendix A.3
1719 const uint8_t PltData[] = {
1720 0x04, 0xc0, 0x9f, 0xe5, // ldr ip, L2
1721 0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc
1722 0x00, 0xf0, 0x9c, 0xe5, // ldr pc, [ip]
1723 0x00, 0x00, 0x00, 0x00, // L2: .word Offset(&(.plt.got) - L1 - 8
1725 memcpy(Buf, PltData, sizeof(PltData));
1726 uint64_t L1 = PltEntryAddr + 4;
1727 write32le(Buf + 12, GotEntryAddr - L1 - 8);
1730 RelExpr ARMTargetInfo::getThunkExpr(RelExpr Expr, uint32_t RelocType,
1731 const InputFile &File,
1732 const SymbolBody &S) const {
1733 // If S is an undefined weak symbol in an executable we don't need a Thunk.
1734 // In a DSO calls to undefined symbols, including weak ones get PLT entries
1735 // which may need a thunk.
1736 if (S.isUndefined() && !S.isLocal() && S.symbol()->isWeak()
1739 // A state change from ARM to Thumb and vice versa must go through an
1740 // interworking thunk if the relocation type is not R_ARM_CALL or
1742 switch (RelocType) {
1746 // Source is ARM, all PLT entries are ARM so no interworking required.
1747 // Otherwise we need to interwork if Symbol has bit 0 set (Thumb).
1748 if (Expr == R_PC && ((S.getVA<ELF32LE>() & 1) == 1))
1751 case R_ARM_THM_JUMP19:
1752 case R_ARM_THM_JUMP24:
1753 // Source is Thumb, all PLT entries are ARM so interworking is required.
1754 // Otherwise we need to interwork if Symbol has bit 0 clear (ARM).
1755 if (Expr == R_PLT_PC)
1756 return R_THUNK_PLT_PC;
1757 if ((S.getVA<ELF32LE>() & 1) == 0)
1764 void ARMTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
1765 uint64_t Val) const {
1768 case R_ARM_BASE_PREL:
1769 case R_ARM_GLOB_DAT:
1770 case R_ARM_GOTOFF32:
1771 case R_ARM_GOT_BREL:
1772 case R_ARM_GOT_PREL:
1774 case R_ARM_RELATIVE:
1777 case R_ARM_TLS_GD32:
1778 case R_ARM_TLS_IE32:
1779 case R_ARM_TLS_LDM32:
1780 case R_ARM_TLS_LDO32:
1781 case R_ARM_TLS_LE32:
1782 case R_ARM_TLS_TPOFF32:
1783 write32le(Loc, Val);
1785 case R_ARM_TLS_DTPMOD32:
1789 checkInt<31>(Loc, Val, Type);
1790 write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000));
1793 // R_ARM_CALL is used for BL and BLX instructions, depending on the
1794 // value of bit 0 of Val, we must select a BL or BLX instruction
1796 // If bit 0 of Val is 1 the target is Thumb, we must select a BLX.
1797 // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
1798 checkInt<26>(Loc, Val, Type);
1799 write32le(Loc, 0xfa000000 | // opcode
1800 ((Val & 2) << 23) | // H
1801 ((Val >> 2) & 0x00ffffff)); // imm24
1804 if ((read32le(Loc) & 0xfe000000) == 0xfa000000)
1805 // BLX (always unconditional) instruction to an ARM Target, select an
1806 // unconditional BL.
1807 write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff));
1808 // fall through as BL encoding is shared with B
1812 checkInt<26>(Loc, Val, Type);
1813 write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff));
1815 case R_ARM_THM_JUMP11:
1816 checkInt<12>(Loc, Val, Type);
1817 write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff));
1819 case R_ARM_THM_JUMP19:
1820 // Encoding T3: Val = S:J2:J1:imm6:imm11:0
1821 checkInt<21>(Loc, Val, Type);
1823 (read16le(Loc) & 0xfbc0) | // opcode cond
1824 ((Val >> 10) & 0x0400) | // S
1825 ((Val >> 12) & 0x003f)); // imm6
1828 ((Val >> 8) & 0x0800) | // J2
1829 ((Val >> 5) & 0x2000) | // J1
1830 ((Val >> 1) & 0x07ff)); // imm11
1832 case R_ARM_THM_CALL:
1833 // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the
1834 // value of bit 0 of Val, we must select a BL or BLX instruction
1835 if ((Val & 1) == 0) {
1836 // Ensure BLX destination is 4-byte aligned. As BLX instruction may
1837 // only be two byte aligned. This must be done before overflow check
1838 Val = alignTo(Val, 4);
1840 // Bit 12 is 0 for BLX, 1 for BL
1841 write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12);
1842 // Fall through as rest of encoding is the same as B.W
1843 case R_ARM_THM_JUMP24:
1844 // Encoding B T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0
1845 // FIXME: Use of I1 and I2 require v6T2ops
1846 checkInt<25>(Loc, Val, Type);
1849 ((Val >> 14) & 0x0400) | // S
1850 ((Val >> 12) & 0x03ff)); // imm10
1852 (read16le(Loc + 2) & 0xd000) | // opcode
1853 (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1
1854 (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2
1855 ((Val >> 1) & 0x07ff)); // imm11
1857 case R_ARM_MOVW_ABS_NC:
1858 case R_ARM_MOVW_PREL_NC:
1859 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) |
1862 case R_ARM_MOVT_ABS:
1863 case R_ARM_MOVT_PREL:
1864 checkInt<32>(Loc, Val, Type);
1865 write32le(Loc, (read32le(Loc) & ~0x000f0fff) |
1866 (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff));
1868 case R_ARM_THM_MOVT_ABS:
1869 case R_ARM_THM_MOVT_PREL:
1870 // Encoding T1: A = imm4:i:imm3:imm8
1871 checkInt<32>(Loc, Val, Type);
1874 ((Val >> 17) & 0x0400) | // i
1875 ((Val >> 28) & 0x000f)); // imm4
1877 (read16le(Loc + 2) & 0x8f00) | // opcode
1878 ((Val >> 12) & 0x7000) | // imm3
1879 ((Val >> 16) & 0x00ff)); // imm8
1881 case R_ARM_THM_MOVW_ABS_NC:
1882 case R_ARM_THM_MOVW_PREL_NC:
1883 // Encoding T3: A = imm4:i:imm3:imm8
1886 ((Val >> 1) & 0x0400) | // i
1887 ((Val >> 12) & 0x000f)); // imm4
1889 (read16le(Loc + 2) & 0x8f00) | // opcode
1890 ((Val << 4) & 0x7000) | // imm3
1891 (Val & 0x00ff)); // imm8
1894 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
1898 uint64_t ARMTargetInfo::getImplicitAddend(const uint8_t *Buf,
1899 uint32_t Type) const {
1904 case R_ARM_BASE_PREL:
1905 case R_ARM_GOTOFF32:
1906 case R_ARM_GOT_BREL:
1907 case R_ARM_GOT_PREL:
1911 case R_ARM_TLS_GD32:
1912 case R_ARM_TLS_LDM32:
1913 case R_ARM_TLS_LDO32:
1914 case R_ARM_TLS_IE32:
1915 case R_ARM_TLS_LE32:
1916 return SignExtend64<32>(read32le(Buf));
1918 return SignExtend64<31>(read32le(Buf));
1923 return SignExtend64<26>(read32le(Buf) << 2);
1924 case R_ARM_THM_JUMP11:
1925 return SignExtend64<12>(read16le(Buf) << 1);
1926 case R_ARM_THM_JUMP19: {
1927 // Encoding T3: A = S:J2:J1:imm10:imm6:0
1928 uint16_t Hi = read16le(Buf);
1929 uint16_t Lo = read16le(Buf + 2);
1930 return SignExtend64<20>(((Hi & 0x0400) << 10) | // S
1931 ((Lo & 0x0800) << 8) | // J2
1932 ((Lo & 0x2000) << 5) | // J1
1933 ((Hi & 0x003f) << 12) | // imm6
1934 ((Lo & 0x07ff) << 1)); // imm11:0
1936 case R_ARM_THM_CALL:
1937 case R_ARM_THM_JUMP24: {
1938 // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0
1939 // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S)
1940 // FIXME: I1 and I2 require v6T2ops
1941 uint16_t Hi = read16le(Buf);
1942 uint16_t Lo = read16le(Buf + 2);
1943 return SignExtend64<24>(((Hi & 0x0400) << 14) | // S
1944 (~((Lo ^ (Hi << 3)) << 10) & 0x00800000) | // I1
1945 (~((Lo ^ (Hi << 1)) << 11) & 0x00400000) | // I2
1946 ((Hi & 0x003ff) << 12) | // imm0
1947 ((Lo & 0x007ff) << 1)); // imm11:0
1949 // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and
1950 // MOVT is in the range -32768 <= A < 32768
1951 case R_ARM_MOVW_ABS_NC:
1952 case R_ARM_MOVT_ABS:
1953 case R_ARM_MOVW_PREL_NC:
1954 case R_ARM_MOVT_PREL: {
1955 uint64_t Val = read32le(Buf) & 0x000f0fff;
1956 return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff));
1958 case R_ARM_THM_MOVW_ABS_NC:
1959 case R_ARM_THM_MOVT_ABS:
1960 case R_ARM_THM_MOVW_PREL_NC:
1961 case R_ARM_THM_MOVT_PREL: {
1962 // Encoding T3: A = imm4:i:imm3:imm8
1963 uint16_t Hi = read16le(Buf);
1964 uint16_t Lo = read16le(Buf + 2);
1965 return SignExtend64<16>(((Hi & 0x000f) << 12) | // imm4
1966 ((Hi & 0x0400) << 1) | // i
1967 ((Lo & 0x7000) >> 4) | // imm3
1968 (Lo & 0x00ff)); // imm8
1973 bool ARMTargetInfo::isTlsLocalDynamicRel(uint32_t Type) const {
1974 return Type == R_ARM_TLS_LDO32 || Type == R_ARM_TLS_LDM32;
1977 bool ARMTargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const {
1978 return Type == R_ARM_TLS_GD32;
1981 bool ARMTargetInfo::isTlsInitialExecRel(uint32_t Type) const {
1982 return Type == R_ARM_TLS_IE32;
1985 template <class ELFT> MipsTargetInfo<ELFT>::MipsTargetInfo() {
1986 GotPltHeaderEntriesNum = 2;
1987 DefaultMaxPageSize = 65536;
1988 GotEntrySize = sizeof(typename ELFT::uint);
1989 GotPltEntrySize = sizeof(typename ELFT::uint);
1992 CopyRel = R_MIPS_COPY;
1993 PltRel = R_MIPS_JUMP_SLOT;
1995 if (ELFT::Is64Bits) {
1996 RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
1997 TlsGotRel = R_MIPS_TLS_TPREL64;
1998 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
1999 TlsOffsetRel = R_MIPS_TLS_DTPREL64;
2001 RelativeRel = R_MIPS_REL32;
2002 TlsGotRel = R_MIPS_TLS_TPREL32;
2003 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
2004 TlsOffsetRel = R_MIPS_TLS_DTPREL32;
2008 template <class ELFT>
2009 RelExpr MipsTargetInfo<ELFT>::getRelExpr(uint32_t Type,
2010 const SymbolBody &S) const {
2011 // See comment in the calculateMipsRelChain.
2012 if (ELFT::Is64Bits || Config->MipsN32Abi)
2019 case R_MIPS_GPREL16:
2020 case R_MIPS_GPREL32:
2021 return R_MIPS_GOTREL;
2026 case R_MIPS_GOT_OFST:
2027 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
2028 // offset between start of function and 'gp' value which by default
2029 // equal to the start of .got section. In that case we consider these
2030 // relocations as relative.
2031 if (&S == ElfSym<ELFT>::MipsGpDisp)
2036 case R_MIPS_PC19_S2:
2037 case R_MIPS_PC21_S2:
2038 case R_MIPS_PC26_S2:
2044 return R_MIPS_GOT_LOCAL_PAGE;
2047 case R_MIPS_GOT_DISP:
2048 case R_MIPS_TLS_GOTTPREL:
2049 return R_MIPS_GOT_OFF;
2050 case R_MIPS_CALL_HI16:
2051 case R_MIPS_CALL_LO16:
2052 case R_MIPS_GOT_HI16:
2053 case R_MIPS_GOT_LO16:
2054 return R_MIPS_GOT_OFF32;
2055 case R_MIPS_GOT_PAGE:
2056 return R_MIPS_GOT_LOCAL_PAGE;
2058 return R_MIPS_TLSGD;
2059 case R_MIPS_TLS_LDM:
2060 return R_MIPS_TLSLD;
2064 template <class ELFT> bool MipsTargetInfo<ELFT>::isPicRel(uint32_t Type) const {
2065 return Type == R_MIPS_32 || Type == R_MIPS_64;
2068 template <class ELFT>
2069 uint32_t MipsTargetInfo<ELFT>::getDynRel(uint32_t Type) const {
2073 template <class ELFT>
2074 bool MipsTargetInfo<ELFT>::isTlsLocalDynamicRel(uint32_t Type) const {
2075 return Type == R_MIPS_TLS_LDM;
2078 template <class ELFT>
2079 bool MipsTargetInfo<ELFT>::isTlsGlobalDynamicRel(uint32_t Type) const {
2080 return Type == R_MIPS_TLS_GD;
2083 template <class ELFT>
2084 void MipsTargetInfo<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
2085 write32<ELFT::TargetEndianness>(Buf, In<ELFT>::Plt->getVA());
2088 template <endianness E, uint8_t BSIZE, uint8_t SHIFT>
2089 static int64_t getPcRelocAddend(const uint8_t *Loc) {
2090 uint32_t Instr = read32<E>(Loc);
2091 uint32_t Mask = 0xffffffff >> (32 - BSIZE);
2092 return SignExtend64<BSIZE + SHIFT>((Instr & Mask) << SHIFT);
2095 template <endianness E, uint8_t BSIZE, uint8_t SHIFT>
2096 static void applyMipsPcReloc(uint8_t *Loc, uint32_t Type, uint64_t V) {
2097 uint32_t Mask = 0xffffffff >> (32 - BSIZE);
2098 uint32_t Instr = read32<E>(Loc);
2100 checkAlignment<(1 << SHIFT)>(Loc, V, Type);
2101 checkInt<BSIZE + SHIFT>(Loc, V, Type);
2102 write32<E>(Loc, (Instr & ~Mask) | ((V >> SHIFT) & Mask));
2105 template <endianness E> static void writeMipsHi16(uint8_t *Loc, uint64_t V) {
2106 uint32_t Instr = read32<E>(Loc);
2107 uint16_t Res = ((V + 0x8000) >> 16) & 0xffff;
2108 write32<E>(Loc, (Instr & 0xffff0000) | Res);
2111 template <endianness E> static void writeMipsHigher(uint8_t *Loc, uint64_t V) {
2112 uint32_t Instr = read32<E>(Loc);
2113 uint16_t Res = ((V + 0x80008000) >> 32) & 0xffff;
2114 write32<E>(Loc, (Instr & 0xffff0000) | Res);
2117 template <endianness E> static void writeMipsHighest(uint8_t *Loc, uint64_t V) {
2118 uint32_t Instr = read32<E>(Loc);
2119 uint16_t Res = ((V + 0x800080008000) >> 48) & 0xffff;
2120 write32<E>(Loc, (Instr & 0xffff0000) | Res);
2123 template <endianness E> static void writeMipsLo16(uint8_t *Loc, uint64_t V) {
2124 uint32_t Instr = read32<E>(Loc);
2125 write32<E>(Loc, (Instr & 0xffff0000) | (V & 0xffff));
2128 template <class ELFT> static bool isMipsR6() {
2129 const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf);
2130 uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH;
2131 return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6;
2134 template <class ELFT>
2135 void MipsTargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const {
2136 const endianness E = ELFT::TargetEndianness;
2137 if (Config->MipsN32Abi) {
2138 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0])
2139 write32<E>(Buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14)
2140 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0])
2141 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14
2143 write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0])
2144 write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28)
2145 write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0])
2146 write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28
2148 write32<E>(Buf + 16, 0x03e07825); // move $15, $31
2149 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2
2150 write32<E>(Buf + 24, 0x0320f809); // jalr $25
2151 write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2
2152 uint64_t Got = In<ELFT>::GotPlt->getVA();
2153 writeMipsHi16<E>(Buf, Got);
2154 writeMipsLo16<E>(Buf + 4, Got);
2155 writeMipsLo16<E>(Buf + 8, Got);
2158 template <class ELFT>
2159 void MipsTargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr,
2160 uint64_t PltEntryAddr, int32_t Index,
2161 unsigned RelOff) const {
2162 const endianness E = ELFT::TargetEndianness;
2163 write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry)
2164 write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
2166 write32<E>(Buf + 8, isMipsR6<ELFT>() ? 0x03200009 : 0x03200008);
2167 write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
2168 writeMipsHi16<E>(Buf, GotEntryAddr);
2169 writeMipsLo16<E>(Buf + 4, GotEntryAddr);
2170 writeMipsLo16<E>(Buf + 12, GotEntryAddr);
2173 template <class ELFT>
2174 RelExpr MipsTargetInfo<ELFT>::getThunkExpr(RelExpr Expr, uint32_t Type,
2175 const InputFile &File,
2176 const SymbolBody &S) const {
2177 // Any MIPS PIC code function is invoked with its address in register $t9.
2178 // So if we have a branch instruction from non-PIC code to the PIC one
2179 // we cannot make the jump directly and need to create a small stubs
2180 // to save the target function address.
2181 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
2182 if (Type != R_MIPS_26)
2184 auto *F = dyn_cast<ELFFileBase<ELFT>>(&File);
2187 // If current file has PIC code, LA25 stub is not required.
2188 if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
2190 auto *D = dyn_cast<DefinedRegular<ELFT>>(&S);
2191 // LA25 is required if target file has PIC code
2192 // or target symbol is a PIC symbol.
2193 return D && D->isMipsPIC() ? R_THUNK_ABS : Expr;
2196 template <class ELFT>
2197 uint64_t MipsTargetInfo<ELFT>::getImplicitAddend(const uint8_t *Buf,
2198 uint32_t Type) const {
2199 const endianness E = ELFT::TargetEndianness;
2204 case R_MIPS_GPREL32:
2205 case R_MIPS_TLS_DTPREL32:
2206 case R_MIPS_TLS_TPREL32:
2207 return read32<E>(Buf);
2209 // FIXME (simon): If the relocation target symbol is not a PLT entry
2210 // we should use another expression for calculation:
2211 // ((A << 2) | (P & 0xf0000000)) >> 2
2212 return SignExtend64<28>((read32<E>(Buf) & 0x3ffffff) << 2);
2213 case R_MIPS_GPREL16:
2216 case R_MIPS_TLS_DTPREL_HI16:
2217 case R_MIPS_TLS_DTPREL_LO16:
2218 case R_MIPS_TLS_TPREL_HI16:
2219 case R_MIPS_TLS_TPREL_LO16:
2220 return SignExtend64<16>(read32<E>(Buf));
2222 return getPcRelocAddend<E, 16, 2>(Buf);
2223 case R_MIPS_PC19_S2:
2224 return getPcRelocAddend<E, 19, 2>(Buf);
2225 case R_MIPS_PC21_S2:
2226 return getPcRelocAddend<E, 21, 2>(Buf);
2227 case R_MIPS_PC26_S2:
2228 return getPcRelocAddend<E, 26, 2>(Buf);
2230 return getPcRelocAddend<E, 32, 0>(Buf);
2234 static std::pair<uint32_t, uint64_t>
2235 calculateMipsRelChain(uint8_t *Loc, uint32_t Type, uint64_t Val) {
2236 // MIPS N64 ABI packs multiple relocations into the single relocation
2237 // record. In general, all up to three relocations can have arbitrary
2238 // types. In fact, Clang and GCC uses only a few combinations. For now,
2239 // we support two of them. That is allow to pass at least all LLVM
2240 // test suite cases.
2241 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16
2242 // <any relocation> / R_MIPS_64 / R_MIPS_NONE
2243 // The first relocation is a 'real' relocation which is calculated
2244 // using the corresponding symbol's value. The second and the third
2245 // relocations used to modify result of the first one: extend it to
2246 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation
2247 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf
2248 uint32_t Type2 = (Type >> 8) & 0xff;
2249 uint32_t Type3 = (Type >> 16) & 0xff;
2250 if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE)
2251 return std::make_pair(Type, Val);
2252 if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE)
2253 return std::make_pair(Type2, Val);
2254 if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16))
2255 return std::make_pair(Type3, -Val);
2256 error(getErrorLocation(Loc) + "unsupported relocations combination " +
2258 return std::make_pair(Type & 0xff, Val);
2261 template <class ELFT>
2262 void MipsTargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type,
2263 uint64_t Val) const {
2264 const endianness E = ELFT::TargetEndianness;
2265 // Thread pointer and DRP offsets from the start of TLS data area.
2266 // https://www.linux-mips.org/wiki/NPTL
2267 if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 ||
2268 Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64)
2270 else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 ||
2271 Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64)
2273 if (ELFT::Is64Bits || Config->MipsN32Abi)
2274 std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
2277 case R_MIPS_GPREL32:
2278 case R_MIPS_TLS_DTPREL32:
2279 case R_MIPS_TLS_TPREL32:
2280 write32<E>(Loc, Val);
2283 case R_MIPS_TLS_DTPREL64:
2284 case R_MIPS_TLS_TPREL64:
2285 write64<E>(Loc, Val);
2288 write32<E>(Loc, (read32<E>(Loc) & ~0x3ffffff) | ((Val >> 2) & 0x3ffffff));
2290 case R_MIPS_GOT_DISP:
2291 case R_MIPS_GOT_PAGE:
2293 case R_MIPS_GPREL16:
2295 case R_MIPS_TLS_LDM:
2296 checkInt<16>(Loc, Val, Type);
2299 case R_MIPS_CALL_LO16:
2300 case R_MIPS_GOT_LO16:
2301 case R_MIPS_GOT_OFST:
2304 case R_MIPS_TLS_DTPREL_LO16:
2305 case R_MIPS_TLS_GOTTPREL:
2306 case R_MIPS_TLS_TPREL_LO16:
2307 writeMipsLo16<E>(Loc, Val);
2309 case R_MIPS_CALL_HI16:
2310 case R_MIPS_GOT_HI16:
2313 case R_MIPS_TLS_DTPREL_HI16:
2314 case R_MIPS_TLS_TPREL_HI16:
2315 writeMipsHi16<E>(Loc, Val);
2318 writeMipsHigher<E>(Loc, Val);
2320 case R_MIPS_HIGHEST:
2321 writeMipsHighest<E>(Loc, Val);
2324 // Ignore this optimization relocation for now
2327 applyMipsPcReloc<E, 16, 2>(Loc, Type, Val);
2329 case R_MIPS_PC19_S2:
2330 applyMipsPcReloc<E, 19, 2>(Loc, Type, Val);
2332 case R_MIPS_PC21_S2:
2333 applyMipsPcReloc<E, 21, 2>(Loc, Type, Val);
2335 case R_MIPS_PC26_S2:
2336 applyMipsPcReloc<E, 26, 2>(Loc, Type, Val);
2339 applyMipsPcReloc<E, 32, 0>(Loc, Type, Val);
2342 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
2346 template <class ELFT>
2347 bool MipsTargetInfo<ELFT>::usesOnlyLowPageBits(uint32_t Type) const {
2348 return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST;