1 //===- Target.cpp ---------------------------------------------------------===//
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Machine-specific things, such as applying relocations, creation of
11 // GOT or PLT entries, etc., are handled in this file.
13 // Refer the ELF spec for the single letter varaibles, S, A or P, used
16 // Some functions defined in this file has "relaxTls" as part of their names.
17 // They do peephole optimization for TLS variables by rewriting instructions.
18 // They are not part of the ABI but optional optimization, so you can skip
19 // them if you are not interested in how TLS variables are optimized.
20 // See the following paper for the details.
22 // Ulrich Drepper, ELF Handling For Thread-Local Storage
23 // http://www.akkadia.org/drepper/tls.pdf
25 //===----------------------------------------------------------------------===//
29 #include "InputFiles.h"
30 #include "OutputSections.h"
34 #include "llvm/ADT/ArrayRef.h"
35 #include "llvm/Object/ELF.h"
36 #include "llvm/Support/Endian.h"
37 #include "llvm/Support/ELF.h"
40 using namespace llvm::object;
41 using namespace llvm::support::endian;
42 using namespace llvm::ELF;
49 static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
51 StringRef getRelName(uint32_t Type) {
52 return getELFRelocationTypeName(Config->EMachine, Type);
55 template <unsigned N> static void checkInt(int64_t V, uint32_t Type) {
57 error("relocation " + getRelName(Type) + " out of range");
60 template <unsigned N> static void checkUInt(uint64_t V, uint32_t Type) {
62 error("relocation " + getRelName(Type) + " out of range");
65 template <unsigned N> static void checkIntUInt(uint64_t V, uint32_t Type) {
66 if (!isInt<N>(V) && !isUInt<N>(V))
67 error("relocation " + getRelName(Type) + " out of range");
70 template <unsigned N> static void checkAlignment(uint64_t V, uint32_t Type) {
71 if ((V & (N - 1)) != 0)
72 error("improper alignment for relocation " + getRelName(Type));
75 static void errorDynRel(uint32_t Type) {
76 error("relocation " + getRelName(Type) +
77 " cannot be used against shared object; recompile with -fPIC.");
81 class X86TargetInfo final : public TargetInfo {
84 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
85 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
86 void writeGotPltHeader(uint8_t *Buf) const override;
87 uint32_t getDynRel(uint32_t Type) const override;
88 bool isTlsLocalDynamicRel(uint32_t Type) const override;
89 bool isTlsGlobalDynamicRel(uint32_t Type) const override;
90 bool isTlsInitialExecRel(uint32_t Type) const override;
91 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
92 void writePltHeader(uint8_t *Buf) const override;
93 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
94 int32_t Index, unsigned RelOff) const override;
95 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
97 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
98 RelExpr Expr) const override;
99 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
100 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
101 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
102 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
105 template <class ELFT> class X86_64TargetInfo final : public TargetInfo {
108 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
109 uint32_t getDynRel(uint32_t Type) const override;
110 bool isTlsLocalDynamicRel(uint32_t Type) const override;
111 bool isTlsGlobalDynamicRel(uint32_t Type) const override;
112 bool isTlsInitialExecRel(uint32_t Type) const override;
113 void writeGotPltHeader(uint8_t *Buf) const override;
114 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
115 void writePltHeader(uint8_t *Buf) const override;
116 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
117 int32_t Index, unsigned RelOff) const override;
118 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
120 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
121 RelExpr Expr) const override;
122 void relaxGot(uint8_t *Loc, uint64_t Val) const override;
123 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
124 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
125 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
126 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
129 void relaxGotNoPic(uint8_t *Loc, uint64_t Val, uint8_t Op,
130 uint8_t ModRm) const;
133 class PPCTargetInfo final : public TargetInfo {
136 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
137 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
140 class PPC64TargetInfo final : public TargetInfo {
143 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
144 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
145 int32_t Index, unsigned RelOff) const override;
146 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
149 class AArch64TargetInfo final : public TargetInfo {
152 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
153 uint32_t getDynRel(uint32_t Type) const override;
154 bool isTlsInitialExecRel(uint32_t Type) const override;
155 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
156 void writePltHeader(uint8_t *Buf) const override;
157 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
158 int32_t Index, unsigned RelOff) const override;
159 bool usesOnlyLowPageBits(uint32_t Type) const override;
160 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
161 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
162 RelExpr Expr) const override;
163 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
164 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
165 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
168 class AMDGPUTargetInfo final : public TargetInfo {
171 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
172 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
175 class ARMTargetInfo final : public TargetInfo {
178 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
179 uint32_t getDynRel(uint32_t Type) const override;
180 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
181 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
182 void writePltHeader(uint8_t *Buf) const override;
183 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
184 int32_t Index, unsigned RelOff) const override;
185 RelExpr getThunkExpr(RelExpr Expr, uint32_t RelocType,
186 const InputFile &File,
187 const SymbolBody &S) const override;
188 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
191 template <class ELFT> class MipsTargetInfo final : public TargetInfo {
194 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
195 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
196 uint32_t getDynRel(uint32_t Type) const override;
197 bool isTlsLocalDynamicRel(uint32_t Type) const override;
198 bool isTlsGlobalDynamicRel(uint32_t Type) const override;
199 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
200 void writePltHeader(uint8_t *Buf) const override;
201 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
202 int32_t Index, unsigned RelOff) const override;
203 RelExpr getThunkExpr(RelExpr Expr, uint32_t RelocType,
204 const InputFile &File,
205 const SymbolBody &S) const override;
206 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
207 bool usesOnlyLowPageBits(uint32_t Type) const override;
209 } // anonymous namespace
211 TargetInfo *createTarget() {
212 switch (Config->EMachine) {
214 return new X86TargetInfo();
216 return new AArch64TargetInfo();
218 return new AMDGPUTargetInfo();
220 return new ARMTargetInfo();
222 switch (Config->EKind) {
224 return new MipsTargetInfo<ELF32LE>();
226 return new MipsTargetInfo<ELF32BE>();
228 return new MipsTargetInfo<ELF64LE>();
230 return new MipsTargetInfo<ELF64BE>();
232 fatal("unsupported MIPS target");
235 return new PPCTargetInfo();
237 return new PPC64TargetInfo();
239 if (Config->EKind == ELF32LEKind)
240 return new X86_64TargetInfo<ELF32LE>();
241 return new X86_64TargetInfo<ELF64LE>();
243 fatal("unknown target machine");
246 TargetInfo::~TargetInfo() {}
248 uint64_t TargetInfo::getImplicitAddend(const uint8_t *Buf,
249 uint32_t Type) const {
253 bool TargetInfo::usesOnlyLowPageBits(uint32_t Type) const { return false; }
255 RelExpr TargetInfo::getThunkExpr(RelExpr Expr, uint32_t RelocType,
256 const InputFile &File,
257 const SymbolBody &S) const {
261 bool TargetInfo::isTlsInitialExecRel(uint32_t Type) const { return false; }
263 bool TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { return false; }
265 bool TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const {
269 RelExpr TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
270 RelExpr Expr) const {
274 void TargetInfo::relaxGot(uint8_t *Loc, uint64_t Val) const {
275 llvm_unreachable("Should not have claimed to be relaxable");
278 void TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type,
279 uint64_t Val) const {
280 llvm_unreachable("Should not have claimed to be relaxable");
283 void TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type,
284 uint64_t Val) const {
285 llvm_unreachable("Should not have claimed to be relaxable");
288 void TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type,
289 uint64_t Val) const {
290 llvm_unreachable("Should not have claimed to be relaxable");
293 void TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type,
294 uint64_t Val) const {
295 llvm_unreachable("Should not have claimed to be relaxable");
298 X86TargetInfo::X86TargetInfo() {
299 CopyRel = R_386_COPY;
300 GotRel = R_386_GLOB_DAT;
301 PltRel = R_386_JUMP_SLOT;
302 IRelativeRel = R_386_IRELATIVE;
303 RelativeRel = R_386_RELATIVE;
304 TlsGotRel = R_386_TLS_TPOFF;
305 TlsModuleIndexRel = R_386_TLS_DTPMOD32;
306 TlsOffsetRel = R_386_TLS_DTPOFF32;
314 RelExpr X86TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
332 case R_386_TLS_GOTIE:
333 return R_GOT_FROM_END;
338 case R_386_TLS_LE_32:
343 RelExpr X86TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
344 RelExpr Expr) const {
348 case R_RELAX_TLS_GD_TO_IE:
349 return R_RELAX_TLS_GD_TO_IE_END;
350 case R_RELAX_TLS_GD_TO_LE:
351 return R_RELAX_TLS_GD_TO_LE_NEG;
355 void X86TargetInfo::writeGotPltHeader(uint8_t *Buf) const {
356 write32le(Buf, Out<ELF32LE>::Dynamic->getVA());
359 void X86TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &S) const {
360 // Entries in .got.plt initially points back to the corresponding
361 // PLT entries with a fixed offset to skip the first instruction.
362 write32le(Buf, S.getPltVA<ELF32LE>() + 6);
365 uint32_t X86TargetInfo::getDynRel(uint32_t Type) const {
366 if (Type == R_386_TLS_LE)
367 return R_386_TLS_TPOFF;
368 if (Type == R_386_TLS_LE_32)
369 return R_386_TLS_TPOFF32;
373 bool X86TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const {
374 return Type == R_386_TLS_GD;
377 bool X86TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const {
378 return Type == R_386_TLS_LDO_32 || Type == R_386_TLS_LDM;
381 bool X86TargetInfo::isTlsInitialExecRel(uint32_t Type) const {
382 return Type == R_386_TLS_IE || Type == R_386_TLS_GOTIE;
385 void X86TargetInfo::writePltHeader(uint8_t *Buf) const {
386 // Executable files and shared object files have
387 // separate procedure linkage tables.
389 const uint8_t V[] = {
390 0xff, 0xb3, 0x04, 0x00, 0x00, 0x00, // pushl 4(%ebx)
391 0xff, 0xa3, 0x08, 0x00, 0x00, 0x00, // jmp *8(%ebx)
392 0x90, 0x90, 0x90, 0x90 // nop; nop; nop; nop
394 memcpy(Buf, V, sizeof(V));
398 const uint8_t PltData[] = {
399 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushl (GOT+4)
400 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *(GOT+8)
401 0x90, 0x90, 0x90, 0x90 // nop; nop; nop; nop
403 memcpy(Buf, PltData, sizeof(PltData));
404 uint32_t Got = Out<ELF32LE>::GotPlt->getVA();
405 write32le(Buf + 2, Got + 4);
406 write32le(Buf + 8, Got + 8);
409 void X86TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr,
410 uint64_t PltEntryAddr, int32_t Index,
411 unsigned RelOff) const {
412 const uint8_t Inst[] = {
413 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, // jmp *foo_in_GOT|*foo@GOT(%ebx)
414 0x68, 0x00, 0x00, 0x00, 0x00, // pushl $reloc_offset
415 0xe9, 0x00, 0x00, 0x00, 0x00 // jmp .PLT0@PC
417 memcpy(Buf, Inst, sizeof(Inst));
419 // jmp *foo@GOT(%ebx) or jmp *foo_in_GOT
420 Buf[1] = Config->Pic ? 0xa3 : 0x25;
421 uint32_t Got = Out<ELF32LE>::GotPlt->getVA();
422 write32le(Buf + 2, Config->Shared ? GotEntryAddr - Got : GotEntryAddr);
423 write32le(Buf + 7, RelOff);
424 write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16);
427 uint64_t X86TargetInfo::getImplicitAddend(const uint8_t *Buf,
428 uint32_t Type) const {
440 return read32le(Buf);
444 void X86TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
445 uint64_t Val) const {
446 checkInt<32>(Val, Type);
450 void X86TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type,
451 uint64_t Val) const {
453 // leal x@tlsgd(, %ebx, 1),
454 // call __tls_get_addr@plt
457 // subl $x@ntpoff,%eax
458 const uint8_t Inst[] = {
459 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax
460 0x81, 0xe8, 0x00, 0x00, 0x00, 0x00 // subl 0(%ebx), %eax
462 memcpy(Loc - 3, Inst, sizeof(Inst));
463 relocateOne(Loc + 5, R_386_32, Val);
466 void X86TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type,
467 uint64_t Val) const {
469 // leal x@tlsgd(, %ebx, 1),
470 // call __tls_get_addr@plt
473 // addl x@gotntpoff(%ebx), %eax
474 const uint8_t Inst[] = {
475 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax
476 0x03, 0x83, 0x00, 0x00, 0x00, 0x00 // addl 0(%ebx), %eax
478 memcpy(Loc - 3, Inst, sizeof(Inst));
479 relocateOne(Loc + 5, R_386_32, Val);
482 // In some conditions, relocations can be optimized to avoid using GOT.
483 // This function does that for Initial Exec to Local Exec case.
484 void X86TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type,
485 uint64_t Val) const {
486 // Ulrich's document section 6.2 says that @gotntpoff can
487 // be used with MOVL or ADDL instructions.
488 // @indntpoff is similar to @gotntpoff, but for use in
489 // position dependent code.
490 uint8_t Reg = (Loc[-1] >> 3) & 7;
492 if (Type == R_386_TLS_IE) {
493 if (Loc[-1] == 0xa1) {
494 // "movl foo@indntpoff,%eax" -> "movl $foo,%eax"
495 // This case is different from the generic case below because
496 // this is a 5 byte instruction while below is 6 bytes.
498 } else if (Loc[-2] == 0x8b) {
499 // "movl foo@indntpoff,%reg" -> "movl $foo,%reg"
501 Loc[-1] = 0xc0 | Reg;
503 // "addl foo@indntpoff,%reg" -> "addl $foo,%reg"
505 Loc[-1] = 0xc0 | Reg;
508 assert(Type == R_386_TLS_GOTIE);
509 if (Loc[-2] == 0x8b) {
510 // "movl foo@gottpoff(%rip),%reg" -> "movl $foo,%reg"
512 Loc[-1] = 0xc0 | Reg;
514 // "addl foo@gotntpoff(%rip),%reg" -> "leal foo(%reg),%reg"
516 Loc[-1] = 0x80 | (Reg << 3) | Reg;
519 relocateOne(Loc, R_386_TLS_LE, Val);
522 void X86TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type,
523 uint64_t Val) const {
524 if (Type == R_386_TLS_LDO_32) {
525 relocateOne(Loc, R_386_TLS_LE, Val);
530 // leal foo(%reg),%eax
531 // call ___tls_get_addr
535 // leal 0(%esi,1),%esi
536 const uint8_t Inst[] = {
537 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0,%eax
539 0x8d, 0x74, 0x26, 0x00 // leal 0(%esi,1),%esi
541 memcpy(Loc - 2, Inst, sizeof(Inst));
544 template <class ELFT> X86_64TargetInfo<ELFT>::X86_64TargetInfo() {
545 CopyRel = R_X86_64_COPY;
546 GotRel = R_X86_64_GLOB_DAT;
547 PltRel = R_X86_64_JUMP_SLOT;
548 RelativeRel = R_X86_64_RELATIVE;
549 IRelativeRel = R_X86_64_IRELATIVE;
550 TlsGotRel = R_X86_64_TPOFF64;
551 TlsModuleIndexRel = R_X86_64_DTPMOD64;
552 TlsOffsetRel = R_X86_64_DTPOFF64;
560 template <class ELFT>
561 RelExpr X86_64TargetInfo<ELFT>::getRelExpr(uint32_t Type,
562 const SymbolBody &S) const {
566 case R_X86_64_TPOFF32:
572 case R_X86_64_SIZE32:
573 case R_X86_64_SIZE64:
581 return R_GOT_FROM_END;
582 case R_X86_64_GOTPCREL:
583 case R_X86_64_GOTPCRELX:
584 case R_X86_64_REX_GOTPCRELX:
585 case R_X86_64_GOTTPOFF:
590 template <class ELFT>
591 void X86_64TargetInfo<ELFT>::writeGotPltHeader(uint8_t *Buf) const {
592 // The first entry holds the value of _DYNAMIC. It is not clear why that is
593 // required, but it is documented in the psabi and the glibc dynamic linker
594 // seems to use it (note that this is relevant for linking ld.so, not any
596 write64le(Buf, Out<ELFT>::Dynamic->getVA());
599 template <class ELFT>
600 void X86_64TargetInfo<ELFT>::writeGotPlt(uint8_t *Buf,
601 const SymbolBody &S) const {
602 // See comments in X86TargetInfo::writeGotPlt.
603 write32le(Buf, S.getPltVA<ELFT>() + 6);
606 template <class ELFT>
607 void X86_64TargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const {
608 const uint8_t PltData[] = {
609 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushq GOT+8(%rip)
610 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *GOT+16(%rip)
611 0x0f, 0x1f, 0x40, 0x00 // nopl 0x0(rax)
613 memcpy(Buf, PltData, sizeof(PltData));
614 uint64_t Got = Out<ELFT>::GotPlt->getVA();
615 uint64_t Plt = Out<ELFT>::Plt->getVA();
616 write32le(Buf + 2, Got - Plt + 2); // GOT+8
617 write32le(Buf + 8, Got - Plt + 4); // GOT+16
620 template <class ELFT>
621 void X86_64TargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr,
622 uint64_t PltEntryAddr, int32_t Index,
623 unsigned RelOff) const {
624 const uint8_t Inst[] = {
625 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmpq *got(%rip)
626 0x68, 0x00, 0x00, 0x00, 0x00, // pushq <relocation index>
627 0xe9, 0x00, 0x00, 0x00, 0x00 // jmpq plt[0]
629 memcpy(Buf, Inst, sizeof(Inst));
631 write32le(Buf + 2, GotEntryAddr - PltEntryAddr - 6);
632 write32le(Buf + 7, Index);
633 write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16);
636 template <class ELFT>
637 uint32_t X86_64TargetInfo<ELFT>::getDynRel(uint32_t Type) const {
638 if (Type == R_X86_64_PC32 || Type == R_X86_64_32)
643 template <class ELFT>
644 bool X86_64TargetInfo<ELFT>::isTlsInitialExecRel(uint32_t Type) const {
645 return Type == R_X86_64_GOTTPOFF;
648 template <class ELFT>
649 bool X86_64TargetInfo<ELFT>::isTlsGlobalDynamicRel(uint32_t Type) const {
650 return Type == R_X86_64_TLSGD;
653 template <class ELFT>
654 bool X86_64TargetInfo<ELFT>::isTlsLocalDynamicRel(uint32_t Type) const {
655 return Type == R_X86_64_DTPOFF32 || Type == R_X86_64_DTPOFF64 ||
656 Type == R_X86_64_TLSLD;
659 template <class ELFT>
660 void X86_64TargetInfo<ELFT>::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type,
661 uint64_t Val) const {
664 // leaq x@tlsgd(%rip), %rdi
667 // call __tls_get_addr@plt
671 const uint8_t Inst[] = {
672 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax
673 0x48, 0x8d, 0x80, 0x00, 0x00, 0x00, 0x00 // lea x@tpoff,%rax
675 memcpy(Loc - 4, Inst, sizeof(Inst));
676 // The original code used a pc relative relocation and so we have to
677 // compensate for the -4 in had in the addend.
678 relocateOne(Loc + 8, R_X86_64_TPOFF32, Val + 4);
681 template <class ELFT>
682 void X86_64TargetInfo<ELFT>::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type,
683 uint64_t Val) const {
686 // leaq x@tlsgd(%rip), %rdi
689 // call __tls_get_addr@plt
693 const uint8_t Inst[] = {
694 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax
695 0x48, 0x03, 0x05, 0x00, 0x00, 0x00, 0x00 // addq x@tpoff,%rax
697 memcpy(Loc - 4, Inst, sizeof(Inst));
698 // Both code sequences are PC relatives, but since we are moving the constant
699 // forward by 8 bytes we have to subtract the value by 8.
700 relocateOne(Loc + 8, R_X86_64_PC32, Val - 8);
703 // In some conditions, R_X86_64_GOTTPOFF relocation can be optimized to
704 // R_X86_64_TPOFF32 so that it does not use GOT.
705 template <class ELFT>
706 void X86_64TargetInfo<ELFT>::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type,
707 uint64_t Val) const {
708 uint8_t *Inst = Loc - 3;
709 uint8_t Reg = Loc[-1] >> 3;
710 uint8_t *RegSlot = Loc - 1;
712 // Note that ADD with RSP or R12 is converted to ADD instead of LEA
713 // because LEA with these registers needs 4 bytes to encode and thus
714 // wouldn't fit the space.
716 if (memcmp(Inst, "\x48\x03\x25", 3) == 0) {
717 // "addq foo@gottpoff(%rip),%rsp" -> "addq $foo,%rsp"
718 memcpy(Inst, "\x48\x81\xc4", 3);
719 } else if (memcmp(Inst, "\x4c\x03\x25", 3) == 0) {
720 // "addq foo@gottpoff(%rip),%r12" -> "addq $foo,%r12"
721 memcpy(Inst, "\x49\x81\xc4", 3);
722 } else if (memcmp(Inst, "\x4c\x03", 2) == 0) {
723 // "addq foo@gottpoff(%rip),%r[8-15]" -> "leaq foo(%r[8-15]),%r[8-15]"
724 memcpy(Inst, "\x4d\x8d", 2);
725 *RegSlot = 0x80 | (Reg << 3) | Reg;
726 } else if (memcmp(Inst, "\x48\x03", 2) == 0) {
727 // "addq foo@gottpoff(%rip),%reg -> "leaq foo(%reg),%reg"
728 memcpy(Inst, "\x48\x8d", 2);
729 *RegSlot = 0x80 | (Reg << 3) | Reg;
730 } else if (memcmp(Inst, "\x4c\x8b", 2) == 0) {
731 // "movq foo@gottpoff(%rip),%r[8-15]" -> "movq $foo,%r[8-15]"
732 memcpy(Inst, "\x49\xc7", 2);
733 *RegSlot = 0xc0 | Reg;
734 } else if (memcmp(Inst, "\x48\x8b", 2) == 0) {
735 // "movq foo@gottpoff(%rip),%reg" -> "movq $foo,%reg"
736 memcpy(Inst, "\x48\xc7", 2);
737 *RegSlot = 0xc0 | Reg;
739 fatal("R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions only");
742 // The original code used a PC relative relocation.
743 // Need to compensate for the -4 it had in the addend.
744 relocateOne(Loc, R_X86_64_TPOFF32, Val + 4);
747 template <class ELFT>
748 void X86_64TargetInfo<ELFT>::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type,
749 uint64_t Val) const {
751 // leaq bar@tlsld(%rip), %rdi
752 // callq __tls_get_addr@PLT
753 // leaq bar@dtpoff(%rax), %rcx
758 // leaq bar@tpoff(%rax), %rcx
759 if (Type == R_X86_64_DTPOFF64) {
763 if (Type == R_X86_64_DTPOFF32) {
764 relocateOne(Loc, R_X86_64_TPOFF32, Val);
768 const uint8_t Inst[] = {
769 0x66, 0x66, // .word 0x6666
771 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00 // mov %fs:0,%rax
773 memcpy(Loc - 3, Inst, sizeof(Inst));
776 template <class ELFT>
777 void X86_64TargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type,
778 uint64_t Val) const {
781 checkUInt<32>(Val, Type);
785 case R_X86_64_TPOFF32:
787 case R_X86_64_GOTPCREL:
788 case R_X86_64_GOTPCRELX:
789 case R_X86_64_REX_GOTPCRELX:
791 case R_X86_64_GOTTPOFF:
795 case R_X86_64_DTPOFF32:
796 case R_X86_64_SIZE32:
797 checkInt<32>(Val, Type);
801 case R_X86_64_DTPOFF64:
802 case R_X86_64_SIZE64:
807 fatal("unrecognized reloc " + Twine(Type));
811 template <class ELFT>
812 RelExpr X86_64TargetInfo<ELFT>::adjustRelaxExpr(uint32_t Type,
814 RelExpr RelExpr) const {
815 if (Type != R_X86_64_GOTPCRELX && Type != R_X86_64_REX_GOTPCRELX)
817 const uint8_t Op = Data[-2];
818 const uint8_t ModRm = Data[-1];
819 // FIXME: When PIC is disabled and foo is defined locally in the
820 // lower 32 bit address space, memory operand in mov can be converted into
821 // immediate operand. Otherwise, mov must be changed to lea. We support only
822 // latter relaxation at this moment.
824 return R_RELAX_GOT_PC;
825 // Relax call and jmp.
826 if (Op == 0xff && (ModRm == 0x15 || ModRm == 0x25))
827 return R_RELAX_GOT_PC;
829 // Relaxation of test, adc, add, and, cmp, or, sbb, sub, xor.
830 // If PIC then no relaxation is available.
831 // We also don't relax test/binop instructions without REX byte,
832 // they are 32bit operations and not common to have.
833 assert(Type == R_X86_64_REX_GOTPCRELX);
834 return Config->Pic ? RelExpr : R_RELAX_GOT_PC_NOPIC;
837 // A subset of relaxations can only be applied for no-PIC. This method
838 // handles such relaxations. Instructions encoding information was taken from:
839 // "Intel 64 and IA-32 Architectures Software Developer's Manual V2"
840 // (http://www.intel.com/content/dam/www/public/us/en/documents/manuals/
841 // 64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf)
842 template <class ELFT>
843 void X86_64TargetInfo<ELFT>::relaxGotNoPic(uint8_t *Loc, uint64_t Val,
844 uint8_t Op, uint8_t ModRm) const {
845 const uint8_t Rex = Loc[-3];
846 // Convert "test %reg, foo@GOTPCREL(%rip)" to "test $foo, %reg".
848 // See "TEST-Logical Compare" (4-428 Vol. 2B),
849 // TEST r/m64, r64 uses "full" ModR / M byte (no opcode extension).
851 // ModR/M byte has form XX YYY ZZZ, where
852 // YYY is MODRM.reg(register 2), ZZZ is MODRM.rm(register 1).
853 // XX has different meanings:
854 // 00: The operand's memory address is in reg1.
855 // 01: The operand's memory address is reg1 + a byte-sized displacement.
856 // 10: The operand's memory address is reg1 + a word-sized displacement.
857 // 11: The operand is reg1 itself.
858 // If an instruction requires only one operand, the unused reg2 field
859 // holds extra opcode bits rather than a register code
860 // 0xC0 == 11 000 000 binary.
861 // 0x38 == 00 111 000 binary.
862 // We transfer reg2 to reg1 here as operand.
863 // See "2.1.3 ModR/M and SIB Bytes" (Vol. 2A 2-3).
864 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3; // ModR/M byte.
866 // Change opcode from TEST r/m64, r64 to TEST r/m64, imm32
867 // See "TEST-Logical Compare" (4-428 Vol. 2B).
870 // Move R bit to the B bit in REX byte.
871 // REX byte is encoded as 0100WRXB, where
872 // 0100 is 4bit fixed pattern.
873 // REX.W When 1, a 64-bit operand size is used. Otherwise, when 0, the
874 // default operand size is used (which is 32-bit for most but not all
876 // REX.R This 1-bit value is an extension to the MODRM.reg field.
877 // REX.X This 1-bit value is an extension to the SIB.index field.
878 // REX.B This 1-bit value is an extension to the MODRM.rm field or the
880 // See "2.2.1.2 More on REX Prefix Fields " (2-8 Vol. 2A).
881 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2;
882 relocateOne(Loc, R_X86_64_PC32, Val);
886 // If we are here then we need to relax the adc, add, and, cmp, or, sbb, sub
887 // or xor operations.
889 // Convert "binop foo@GOTPCREL(%rip), %reg" to "binop $foo, %reg".
890 // Logic is close to one for test instruction above, but we also
891 // write opcode extension here, see below for details.
892 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3 | (Op & 0x3c); // ModR/M byte.
894 // Primary opcode is 0x81, opcode extension is one of:
895 // 000b = ADD, 001b is OR, 010b is ADC, 011b is SBB,
896 // 100b is AND, 101b is SUB, 110b is XOR, 111b is CMP.
897 // This value was wrote to MODRM.reg in a line above.
898 // See "3.2 INSTRUCTIONS (A-M)" (Vol. 2A 3-15),
899 // "INSTRUCTION SET REFERENCE, N-Z" (Vol. 2B 4-1) for
900 // descriptions about each operation.
902 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2;
903 relocateOne(Loc, R_X86_64_PC32, Val);
906 template <class ELFT>
907 void X86_64TargetInfo<ELFT>::relaxGot(uint8_t *Loc, uint64_t Val) const {
908 const uint8_t Op = Loc[-2];
909 const uint8_t ModRm = Loc[-1];
911 // Convert "mov foo@GOTPCREL(%rip),%reg" to "lea foo(%rip),%reg".
914 relocateOne(Loc, R_X86_64_PC32, Val);
919 // We are relaxing a rip relative to an absolute, so compensate
920 // for the old -4 addend.
921 assert(!Config->Pic);
922 relaxGotNoPic(Loc, Val + 4, Op, ModRm);
926 // Convert call/jmp instructions.
928 // ABI says we can convert "call *foo@GOTPCREL(%rip)" to "nop; call foo".
929 // Instead we convert to "addr32 call foo" where addr32 is an instruction
930 // prefix. That makes result expression to be a single instruction.
931 Loc[-2] = 0x67; // addr32 prefix
932 Loc[-1] = 0xe8; // call
933 relocateOne(Loc, R_X86_64_PC32, Val);
937 // Convert "jmp *foo@GOTPCREL(%rip)" to "jmp foo; nop".
938 // jmp doesn't return, so it is fine to use nop here, it is just a stub.
939 assert(ModRm == 0x25);
940 Loc[-2] = 0xe9; // jmp
941 Loc[3] = 0x90; // nop
942 relocateOne(Loc - 1, R_X86_64_PC32, Val + 1);
945 // Relocation masks following the #lo(value), #hi(value), #ha(value),
946 // #higher(value), #highera(value), #highest(value), and #highesta(value)
947 // macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi
949 static uint16_t applyPPCLo(uint64_t V) { return V; }
950 static uint16_t applyPPCHi(uint64_t V) { return V >> 16; }
951 static uint16_t applyPPCHa(uint64_t V) { return (V + 0x8000) >> 16; }
952 static uint16_t applyPPCHigher(uint64_t V) { return V >> 32; }
953 static uint16_t applyPPCHighera(uint64_t V) { return (V + 0x8000) >> 32; }
954 static uint16_t applyPPCHighest(uint64_t V) { return V >> 48; }
955 static uint16_t applyPPCHighesta(uint64_t V) { return (V + 0x8000) >> 48; }
957 PPCTargetInfo::PPCTargetInfo() {}
959 void PPCTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
960 uint64_t Val) const {
962 case R_PPC_ADDR16_HA:
963 write16be(Loc, applyPPCHa(Val));
965 case R_PPC_ADDR16_LO:
966 write16be(Loc, applyPPCLo(Val));
969 fatal("unrecognized reloc " + Twine(Type));
973 RelExpr PPCTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
977 PPC64TargetInfo::PPC64TargetInfo() {
978 PltRel = GotRel = R_PPC64_GLOB_DAT;
979 RelativeRel = R_PPC64_RELATIVE;
985 // We need 64K pages (at least under glibc/Linux, the loader won't
986 // set different permissions on a finer granularity than that).
989 // The PPC64 ELF ABI v1 spec, says:
991 // It is normally desirable to put segments with different characteristics
992 // in separate 256 Mbyte portions of the address space, to give the
993 // operating system full paging flexibility in the 64-bit address space.
995 // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers
996 // use 0x10000000 as the starting address.
997 DefaultImageBase = 0x10000000;
1000 static uint64_t PPC64TocOffset = 0x8000;
1002 uint64_t getPPC64TocBase() {
1003 // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The
1004 // TOC starts where the first of these sections starts. We always create a
1005 // .got when we see a relocation that uses it, so for us the start is always
1007 uint64_t TocVA = Out<ELF64BE>::Got->getVA();
1009 // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000
1010 // thus permitting a full 64 Kbytes segment. Note that the glibc startup
1011 // code (crt1.o) assumes that you can get from the TOC base to the
1012 // start of the .toc section with only a single (signed) 16-bit relocation.
1013 return TocVA + PPC64TocOffset;
1016 RelExpr PPC64TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
1021 case R_PPC64_TOC16_DS:
1022 case R_PPC64_TOC16_HA:
1023 case R_PPC64_TOC16_HI:
1024 case R_PPC64_TOC16_LO:
1025 case R_PPC64_TOC16_LO_DS:
1030 return R_PPC_PLT_OPD;
1034 void PPC64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr,
1035 uint64_t PltEntryAddr, int32_t Index,
1036 unsigned RelOff) const {
1037 uint64_t Off = GotEntryAddr - getPPC64TocBase();
1039 // FIXME: What we should do, in theory, is get the offset of the function
1040 // descriptor in the .opd section, and use that as the offset from %r2 (the
1041 // TOC-base pointer). Instead, we have the GOT-entry offset, and that will
1042 // be a pointer to the function descriptor in the .opd section. Using
1043 // this scheme is simpler, but requires an extra indirection per PLT dispatch.
1045 write32be(Buf, 0xf8410028); // std %r2, 40(%r1)
1046 write32be(Buf + 4, 0x3d620000 | applyPPCHa(Off)); // addis %r11, %r2, X@ha
1047 write32be(Buf + 8, 0xe98b0000 | applyPPCLo(Off)); // ld %r12, X@l(%r11)
1048 write32be(Buf + 12, 0xe96c0000); // ld %r11,0(%r12)
1049 write32be(Buf + 16, 0x7d6903a6); // mtctr %r11
1050 write32be(Buf + 20, 0xe84c0008); // ld %r2,8(%r12)
1051 write32be(Buf + 24, 0xe96c0010); // ld %r11,16(%r12)
1052 write32be(Buf + 28, 0x4e800420); // bctr
1055 static std::pair<uint32_t, uint64_t> toAddr16Rel(uint32_t Type, uint64_t Val) {
1056 uint64_t V = Val - PPC64TocOffset;
1058 case R_PPC64_TOC16: return {R_PPC64_ADDR16, V};
1059 case R_PPC64_TOC16_DS: return {R_PPC64_ADDR16_DS, V};
1060 case R_PPC64_TOC16_HA: return {R_PPC64_ADDR16_HA, V};
1061 case R_PPC64_TOC16_HI: return {R_PPC64_ADDR16_HI, V};
1062 case R_PPC64_TOC16_LO: return {R_PPC64_ADDR16_LO, V};
1063 case R_PPC64_TOC16_LO_DS: return {R_PPC64_ADDR16_LO_DS, V};
1064 default: return {Type, Val};
1068 void PPC64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
1069 uint64_t Val) const {
1070 // For a TOC-relative relocation, proceed in terms of the corresponding
1071 // ADDR16 relocation type.
1072 std::tie(Type, Val) = toAddr16Rel(Type, Val);
1075 case R_PPC64_ADDR14: {
1076 checkAlignment<4>(Val, Type);
1077 // Preserve the AA/LK bits in the branch instruction
1078 uint8_t AALK = Loc[3];
1079 write16be(Loc + 2, (AALK & 3) | (Val & 0xfffc));
1082 case R_PPC64_ADDR16:
1083 checkInt<16>(Val, Type);
1084 write16be(Loc, Val);
1086 case R_PPC64_ADDR16_DS:
1087 checkInt<16>(Val, Type);
1088 write16be(Loc, (read16be(Loc) & 3) | (Val & ~3));
1090 case R_PPC64_ADDR16_HA:
1091 case R_PPC64_REL16_HA:
1092 write16be(Loc, applyPPCHa(Val));
1094 case R_PPC64_ADDR16_HI:
1095 case R_PPC64_REL16_HI:
1096 write16be(Loc, applyPPCHi(Val));
1098 case R_PPC64_ADDR16_HIGHER:
1099 write16be(Loc, applyPPCHigher(Val));
1101 case R_PPC64_ADDR16_HIGHERA:
1102 write16be(Loc, applyPPCHighera(Val));
1104 case R_PPC64_ADDR16_HIGHEST:
1105 write16be(Loc, applyPPCHighest(Val));
1107 case R_PPC64_ADDR16_HIGHESTA:
1108 write16be(Loc, applyPPCHighesta(Val));
1110 case R_PPC64_ADDR16_LO:
1111 write16be(Loc, applyPPCLo(Val));
1113 case R_PPC64_ADDR16_LO_DS:
1114 case R_PPC64_REL16_LO:
1115 write16be(Loc, (read16be(Loc) & 3) | (applyPPCLo(Val) & ~3));
1117 case R_PPC64_ADDR32:
1119 checkInt<32>(Val, Type);
1120 write32be(Loc, Val);
1122 case R_PPC64_ADDR64:
1125 write64be(Loc, Val);
1127 case R_PPC64_REL24: {
1128 uint32_t Mask = 0x03FFFFFC;
1129 checkInt<24>(Val, Type);
1130 write32be(Loc, (read32be(Loc) & ~Mask) | (Val & Mask));
1134 fatal("unrecognized reloc " + Twine(Type));
1138 AArch64TargetInfo::AArch64TargetInfo() {
1139 CopyRel = R_AARCH64_COPY;
1140 RelativeRel = R_AARCH64_RELATIVE;
1141 IRelativeRel = R_AARCH64_IRELATIVE;
1142 GotRel = R_AARCH64_GLOB_DAT;
1143 PltRel = R_AARCH64_JUMP_SLOT;
1144 TlsDescRel = R_AARCH64_TLSDESC;
1145 TlsGotRel = R_AARCH64_TLS_TPREL64;
1147 GotPltEntrySize = 8;
1151 // It doesn't seem to be documented anywhere, but tls on aarch64 uses variant
1152 // 1 of the tls structures and the tcb size is 16.
1156 RelExpr AArch64TargetInfo::getRelExpr(uint32_t Type,
1157 const SymbolBody &S) const {
1161 case R_AARCH64_TLSDESC_ADR_PAGE21:
1162 return R_TLSDESC_PAGE;
1163 case R_AARCH64_TLSDESC_LD64_LO12_NC:
1164 case R_AARCH64_TLSDESC_ADD_LO12_NC:
1166 case R_AARCH64_TLSDESC_CALL:
1168 case R_AARCH64_TLSLE_ADD_TPREL_HI12:
1169 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
1171 case R_AARCH64_CALL26:
1172 case R_AARCH64_CONDBR19:
1173 case R_AARCH64_JUMP26:
1174 case R_AARCH64_TSTBR14:
1176 case R_AARCH64_PREL16:
1177 case R_AARCH64_PREL32:
1178 case R_AARCH64_PREL64:
1179 case R_AARCH64_ADR_PREL_LO21:
1181 case R_AARCH64_ADR_PREL_PG_HI21:
1183 case R_AARCH64_LD64_GOT_LO12_NC:
1184 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
1186 case R_AARCH64_ADR_GOT_PAGE:
1187 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
1188 return R_GOT_PAGE_PC;
1192 RelExpr AArch64TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
1193 RelExpr Expr) const {
1194 if (Expr == R_RELAX_TLS_GD_TO_IE) {
1195 if (Type == R_AARCH64_TLSDESC_ADR_PAGE21)
1196 return R_RELAX_TLS_GD_TO_IE_PAGE_PC;
1197 return R_RELAX_TLS_GD_TO_IE_ABS;
1202 bool AArch64TargetInfo::usesOnlyLowPageBits(uint32_t Type) const {
1206 case R_AARCH64_ADD_ABS_LO12_NC:
1207 case R_AARCH64_LD64_GOT_LO12_NC:
1208 case R_AARCH64_LDST128_ABS_LO12_NC:
1209 case R_AARCH64_LDST16_ABS_LO12_NC:
1210 case R_AARCH64_LDST32_ABS_LO12_NC:
1211 case R_AARCH64_LDST64_ABS_LO12_NC:
1212 case R_AARCH64_LDST8_ABS_LO12_NC:
1213 case R_AARCH64_TLSDESC_ADD_LO12_NC:
1214 case R_AARCH64_TLSDESC_LD64_LO12_NC:
1215 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
1220 bool AArch64TargetInfo::isTlsInitialExecRel(uint32_t Type) const {
1221 return Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 ||
1222 Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
1225 uint32_t AArch64TargetInfo::getDynRel(uint32_t Type) const {
1226 if (Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64)
1228 // Keep it going with a dummy value so that we can find more reloc errors.
1230 return R_AARCH64_ABS32;
1233 void AArch64TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
1234 write64le(Buf, Out<ELF64LE>::Plt->getVA());
1237 static uint64_t getAArch64Page(uint64_t Expr) {
1238 return Expr & (~static_cast<uint64_t>(0xFFF));
1241 void AArch64TargetInfo::writePltHeader(uint8_t *Buf) const {
1242 const uint8_t PltData[] = {
1243 0xf0, 0x7b, 0xbf, 0xa9, // stp x16, x30, [sp,#-16]!
1244 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[2]))
1245 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[2]))]
1246 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[2]))
1247 0x20, 0x02, 0x1f, 0xd6, // br x17
1248 0x1f, 0x20, 0x03, 0xd5, // nop
1249 0x1f, 0x20, 0x03, 0xd5, // nop
1250 0x1f, 0x20, 0x03, 0xd5 // nop
1252 memcpy(Buf, PltData, sizeof(PltData));
1254 uint64_t Got = Out<ELF64LE>::GotPlt->getVA();
1255 uint64_t Plt = Out<ELF64LE>::Plt->getVA();
1256 relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21,
1257 getAArch64Page(Got + 16) - getAArch64Page(Plt + 4));
1258 relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16);
1259 relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16);
1262 void AArch64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr,
1263 uint64_t PltEntryAddr, int32_t Index,
1264 unsigned RelOff) const {
1265 const uint8_t Inst[] = {
1266 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n]))
1267 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[n]))]
1268 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[n]))
1269 0x20, 0x02, 0x1f, 0xd6 // br x17
1271 memcpy(Buf, Inst, sizeof(Inst));
1273 relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21,
1274 getAArch64Page(GotEntryAddr) - getAArch64Page(PltEntryAddr));
1275 relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotEntryAddr);
1276 relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotEntryAddr);
1279 static void updateAArch64Addr(uint8_t *L, uint64_t Imm) {
1280 uint32_t ImmLo = (Imm & 0x3) << 29;
1281 uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
1282 uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3);
1283 write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi);
1286 static inline void updateAArch64Add(uint8_t *L, uint64_t Imm) {
1287 or32le(L, (Imm & 0xFFF) << 10);
1290 void AArch64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
1291 uint64_t Val) const {
1293 case R_AARCH64_ABS16:
1294 case R_AARCH64_PREL16:
1295 checkIntUInt<16>(Val, Type);
1296 write16le(Loc, Val);
1298 case R_AARCH64_ABS32:
1299 case R_AARCH64_PREL32:
1300 checkIntUInt<32>(Val, Type);
1301 write32le(Loc, Val);
1303 case R_AARCH64_ABS64:
1304 case R_AARCH64_PREL64:
1305 write64le(Loc, Val);
1307 case R_AARCH64_ADD_ABS_LO12_NC:
1308 // This relocation stores 12 bits and there's no instruction
1309 // to do it. Instead, we do a 32 bits store of the value
1310 // of r_addend bitwise-or'ed Loc. This assumes that the addend
1311 // bits in Loc are zero.
1312 or32le(Loc, (Val & 0xFFF) << 10);
1314 case R_AARCH64_ADR_GOT_PAGE:
1315 case R_AARCH64_ADR_PREL_PG_HI21:
1316 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
1317 case R_AARCH64_TLSDESC_ADR_PAGE21:
1318 checkInt<33>(Val, Type);
1319 updateAArch64Addr(Loc, Val >> 12);
1321 case R_AARCH64_ADR_PREL_LO21:
1322 checkInt<21>(Val, Type);
1323 updateAArch64Addr(Loc, Val);
1325 case R_AARCH64_CALL26:
1326 case R_AARCH64_JUMP26:
1327 checkInt<28>(Val, Type);
1328 or32le(Loc, (Val & 0x0FFFFFFC) >> 2);
1330 case R_AARCH64_CONDBR19:
1331 checkInt<21>(Val, Type);
1332 or32le(Loc, (Val & 0x1FFFFC) << 3);
1334 case R_AARCH64_LD64_GOT_LO12_NC:
1335 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
1336 case R_AARCH64_TLSDESC_LD64_LO12_NC:
1337 checkAlignment<8>(Val, Type);
1338 or32le(Loc, (Val & 0xFF8) << 7);
1340 case R_AARCH64_LDST128_ABS_LO12_NC:
1341 or32le(Loc, (Val & 0x0FF8) << 6);
1343 case R_AARCH64_LDST16_ABS_LO12_NC:
1344 or32le(Loc, (Val & 0x0FFC) << 9);
1346 case R_AARCH64_LDST8_ABS_LO12_NC:
1347 or32le(Loc, (Val & 0xFFF) << 10);
1349 case R_AARCH64_LDST32_ABS_LO12_NC:
1350 or32le(Loc, (Val & 0xFFC) << 8);
1352 case R_AARCH64_LDST64_ABS_LO12_NC:
1353 or32le(Loc, (Val & 0xFF8) << 7);
1355 case R_AARCH64_TSTBR14:
1356 checkInt<16>(Val, Type);
1357 or32le(Loc, (Val & 0xFFFC) << 3);
1359 case R_AARCH64_TLSLE_ADD_TPREL_HI12:
1360 checkInt<24>(Val, Type);
1361 updateAArch64Add(Loc, Val >> 12);
1363 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
1364 case R_AARCH64_TLSDESC_ADD_LO12_NC:
1365 updateAArch64Add(Loc, Val);
1368 fatal("unrecognized reloc " + Twine(Type));
1372 void AArch64TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type,
1373 uint64_t Val) const {
1374 // TLSDESC Global-Dynamic relocation are in the form:
1375 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21]
1376 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12_NC]
1377 // add x0, x0, :tlsdesc_los:v [_AARCH64_TLSDESC_ADD_LO12_NC]
1378 // .tlsdesccall [R_AARCH64_TLSDESC_CALL]
1380 // And it can optimized to:
1381 // movz x0, #0x0, lsl #16
1385 checkUInt<32>(Val, Type);
1388 case R_AARCH64_TLSDESC_ADD_LO12_NC:
1389 case R_AARCH64_TLSDESC_CALL:
1390 write32le(Loc, 0xd503201f); // nop
1392 case R_AARCH64_TLSDESC_ADR_PAGE21:
1393 write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz
1395 case R_AARCH64_TLSDESC_LD64_LO12_NC:
1396 write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk
1399 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
1403 void AArch64TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type,
1404 uint64_t Val) const {
1405 // TLSDESC Global-Dynamic relocation are in the form:
1406 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21]
1407 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12_NC]
1408 // add x0, x0, :tlsdesc_los:v [_AARCH64_TLSDESC_ADD_LO12_NC]
1409 // .tlsdesccall [R_AARCH64_TLSDESC_CALL]
1411 // And it can optimized to:
1412 // adrp x0, :gottprel:v
1413 // ldr x0, [x0, :gottprel_lo12:v]
1418 case R_AARCH64_TLSDESC_ADD_LO12_NC:
1419 case R_AARCH64_TLSDESC_CALL:
1420 write32le(Loc, 0xd503201f); // nop
1422 case R_AARCH64_TLSDESC_ADR_PAGE21:
1423 write32le(Loc, 0x90000000); // adrp
1424 relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val);
1426 case R_AARCH64_TLSDESC_LD64_LO12_NC:
1427 write32le(Loc, 0xf9400000); // ldr
1428 relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val);
1431 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
1435 void AArch64TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type,
1436 uint64_t Val) const {
1437 checkUInt<32>(Val, Type);
1439 if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) {
1441 uint32_t RegNo = read32le(Loc) & 0x1f;
1442 write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5));
1445 if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) {
1447 uint32_t RegNo = read32le(Loc) & 0x1f;
1448 write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5));
1451 llvm_unreachable("invalid relocation for TLS IE to LE relaxation");
1454 AMDGPUTargetInfo::AMDGPUTargetInfo() {
1455 GotRel = R_AMDGPU_ABS64;
1459 void AMDGPUTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
1460 uint64_t Val) const {
1462 case R_AMDGPU_GOTPCREL:
1463 case R_AMDGPU_REL32:
1464 write32le(Loc, Val);
1467 fatal("unrecognized reloc " + Twine(Type));
1471 RelExpr AMDGPUTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
1473 case R_AMDGPU_REL32:
1475 case R_AMDGPU_GOTPCREL:
1478 fatal("do not know how to handle relocation " + Twine(Type));
1482 ARMTargetInfo::ARMTargetInfo() {
1483 CopyRel = R_ARM_COPY;
1484 RelativeRel = R_ARM_RELATIVE;
1485 IRelativeRel = R_ARM_IRELATIVE;
1486 GotRel = R_ARM_GLOB_DAT;
1487 PltRel = R_ARM_JUMP_SLOT;
1488 TlsGotRel = R_ARM_TLS_TPOFF32;
1489 TlsModuleIndexRel = R_ARM_TLS_DTPMOD32;
1490 TlsOffsetRel = R_ARM_TLS_DTPOFF32;
1492 GotPltEntrySize = 4;
1497 RelExpr ARMTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
1501 case R_ARM_THM_JUMP11:
1507 case R_ARM_THM_JUMP19:
1508 case R_ARM_THM_JUMP24:
1509 case R_ARM_THM_CALL:
1511 case R_ARM_GOTOFF32:
1512 // (S + A) - GOT_ORG
1514 case R_ARM_GOT_BREL:
1515 // GOT(S) + A - GOT_ORG
1517 case R_ARM_GOT_PREL:
1518 // GOT(S) + - GOT_ORG
1520 case R_ARM_BASE_PREL:
1522 // FIXME: currently B(S) assumed to be .got, this may not hold for all
1524 return R_GOTONLY_PC;
1525 case R_ARM_MOVW_PREL_NC:
1526 case R_ARM_MOVT_PREL:
1529 case R_ARM_THM_MOVW_PREL_NC:
1530 case R_ARM_THM_MOVT_PREL:
1535 uint32_t ARMTargetInfo::getDynRel(uint32_t Type) const {
1536 if (Type == R_ARM_ABS32)
1538 // Keep it going with a dummy value so that we can find more reloc errors.
1543 void ARMTargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
1544 write32le(Buf, Out<ELF32LE>::Plt->getVA());
1547 void ARMTargetInfo::writePltHeader(uint8_t *Buf) const {
1548 const uint8_t PltData[] = {
1549 0x04, 0xe0, 0x2d, 0xe5, // str lr, [sp,#-4]!
1550 0x04, 0xe0, 0x9f, 0xe5, // ldr lr, L2
1551 0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr
1552 0x08, 0xf0, 0xbe, 0xe5, // ldr pc, [lr, #8]
1553 0x00, 0x00, 0x00, 0x00, // L2: .word &(.got.plt) - L1 - 8
1555 memcpy(Buf, PltData, sizeof(PltData));
1556 uint64_t GotPlt = Out<ELF32LE>::GotPlt->getVA();
1557 uint64_t L1 = Out<ELF32LE>::Plt->getVA() + 8;
1558 write32le(Buf + 16, GotPlt - L1 - 8);
1561 void ARMTargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr,
1562 uint64_t PltEntryAddr, int32_t Index,
1563 unsigned RelOff) const {
1564 // FIXME: Using simple code sequence with simple relocations.
1565 // There is a more optimal sequence but it requires support for the group
1566 // relocations. See ELF for the ARM Architecture Appendix A.3
1567 const uint8_t PltData[] = {
1568 0x04, 0xc0, 0x9f, 0xe5, // ldr ip, L2
1569 0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc
1570 0x00, 0xf0, 0x9c, 0xe5, // ldr pc, [ip]
1571 0x00, 0x00, 0x00, 0x00, // L2: .word Offset(&(.plt.got) - L1 - 8
1573 memcpy(Buf, PltData, sizeof(PltData));
1574 uint64_t L1 = PltEntryAddr + 4;
1575 write32le(Buf + 12, GotEntryAddr - L1 - 8);
1578 RelExpr ARMTargetInfo::getThunkExpr(RelExpr Expr, uint32_t RelocType,
1579 const InputFile &File,
1580 const SymbolBody &S) const {
1581 // A state change from ARM to Thumb and vice versa must go through an
1582 // interworking thunk if the relocation type is not R_ARM_CALL or
1584 switch (RelocType) {
1588 // Source is ARM, all PLT entries are ARM so no interworking required.
1589 // Otherwise we need to interwork if Symbol has bit 0 set (Thumb).
1590 if (Expr == R_PC && ((S.getVA<ELF32LE>() & 1) == 1))
1593 case R_ARM_THM_JUMP19:
1594 case R_ARM_THM_JUMP24:
1595 // Source is Thumb, all PLT entries are ARM so interworking is required.
1596 // Otherwise we need to interwork if Symbol has bit 0 clear (ARM).
1597 if (Expr == R_PLT_PC)
1598 return R_THUNK_PLT_PC;
1599 if ((S.getVA<ELF32LE>() & 1) == 0)
1606 void ARMTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
1607 uint64_t Val) const {
1612 case R_ARM_BASE_PREL:
1613 case R_ARM_GOTOFF32:
1614 case R_ARM_GOT_BREL:
1615 case R_ARM_GOT_PREL:
1617 write32le(Loc, Val);
1620 checkInt<31>(Val, Type);
1621 write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000));
1624 // R_ARM_CALL is used for BL and BLX instructions, depending on the
1625 // value of bit 0 of Val, we must select a BL or BLX instruction
1627 // If bit 0 of Val is 1 the target is Thumb, we must select a BLX.
1628 // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
1629 checkInt<26>(Val, Type);
1630 write32le(Loc, 0xfa000000 | // opcode
1631 ((Val & 2) << 23) | // H
1632 ((Val >> 2) & 0x00ffffff)); // imm24
1635 if ((read32le(Loc) & 0xfe000000) == 0xfa000000)
1636 // BLX (always unconditional) instruction to an ARM Target, select an
1637 // unconditional BL.
1638 write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff));
1639 // fall through as BL encoding is shared with B
1643 checkInt<26>(Val, Type);
1644 write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff));
1646 case R_ARM_THM_JUMP11:
1647 checkInt<12>(Val, Type);
1648 write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff));
1650 case R_ARM_THM_JUMP19:
1651 // Encoding T3: Val = S:J2:J1:imm6:imm11:0
1652 checkInt<21>(Val, Type);
1654 (read16le(Loc) & 0xfbc0) | // opcode cond
1655 ((Val >> 10) & 0x0400) | // S
1656 ((Val >> 12) & 0x003f)); // imm6
1659 ((Val >> 8) & 0x0800) | // J2
1660 ((Val >> 5) & 0x2000) | // J1
1661 ((Val >> 1) & 0x07ff)); // imm11
1663 case R_ARM_THM_CALL:
1664 // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the
1665 // value of bit 0 of Val, we must select a BL or BLX instruction
1666 if ((Val & 1) == 0) {
1667 // Ensure BLX destination is 4-byte aligned. As BLX instruction may
1668 // only be two byte aligned. This must be done before overflow check
1669 Val = alignTo(Val, 4);
1671 // Bit 12 is 0 for BLX, 1 for BL
1672 write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12);
1673 // Fall through as rest of encoding is the same as B.W
1674 case R_ARM_THM_JUMP24:
1675 // Encoding B T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0
1676 // FIXME: Use of I1 and I2 require v6T2ops
1677 checkInt<25>(Val, Type);
1680 ((Val >> 14) & 0x0400) | // S
1681 ((Val >> 12) & 0x03ff)); // imm10
1683 (read16le(Loc + 2) & 0xd000) | // opcode
1684 (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1
1685 (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2
1686 ((Val >> 1) & 0x07ff)); // imm11
1688 case R_ARM_MOVW_ABS_NC:
1689 case R_ARM_MOVW_PREL_NC:
1690 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) |
1693 case R_ARM_MOVT_ABS:
1694 case R_ARM_MOVT_PREL:
1695 checkInt<32>(Val, Type);
1696 write32le(Loc, (read32le(Loc) & ~0x000f0fff) |
1697 (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff));
1699 case R_ARM_THM_MOVT_ABS:
1700 case R_ARM_THM_MOVT_PREL:
1701 // Encoding T1: A = imm4:i:imm3:imm8
1702 checkInt<32>(Val, Type);
1705 ((Val >> 17) & 0x0400) | // i
1706 ((Val >> 28) & 0x000f)); // imm4
1708 (read16le(Loc + 2) & 0x8f00) | // opcode
1709 ((Val >> 12) & 0x7000) | // imm3
1710 ((Val >> 16) & 0x00ff)); // imm8
1712 case R_ARM_THM_MOVW_ABS_NC:
1713 case R_ARM_THM_MOVW_PREL_NC:
1714 // Encoding T3: A = imm4:i:imm3:imm8
1717 ((Val >> 1) & 0x0400) | // i
1718 ((Val >> 12) & 0x000f)); // imm4
1720 (read16le(Loc + 2) & 0x8f00) | // opcode
1721 ((Val << 4) & 0x7000) | // imm3
1722 (Val & 0x00ff)); // imm8
1725 fatal("unrecognized reloc " + Twine(Type));
1729 uint64_t ARMTargetInfo::getImplicitAddend(const uint8_t *Buf,
1730 uint32_t Type) const {
1735 case R_ARM_BASE_PREL:
1736 case R_ARM_GOTOFF32:
1737 case R_ARM_GOT_BREL:
1738 case R_ARM_GOT_PREL:
1740 return SignExtend64<32>(read32le(Buf));
1742 return SignExtend64<31>(read32le(Buf));
1747 return SignExtend64<26>(read32le(Buf) << 2);
1748 case R_ARM_THM_JUMP11:
1749 return SignExtend64<12>(read16le(Buf) << 1);
1750 case R_ARM_THM_JUMP19: {
1751 // Encoding T3: A = S:J2:J1:imm10:imm6:0
1752 uint16_t Hi = read16le(Buf);
1753 uint16_t Lo = read16le(Buf + 2);
1754 return SignExtend64<20>(((Hi & 0x0400) << 10) | // S
1755 ((Lo & 0x0800) << 8) | // J2
1756 ((Lo & 0x2000) << 5) | // J1
1757 ((Hi & 0x003f) << 12) | // imm6
1758 ((Lo & 0x07ff) << 1)); // imm11:0
1760 case R_ARM_THM_CALL:
1761 case R_ARM_THM_JUMP24: {
1762 // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0
1763 // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S)
1764 // FIXME: I1 and I2 require v6T2ops
1765 uint16_t Hi = read16le(Buf);
1766 uint16_t Lo = read16le(Buf + 2);
1767 return SignExtend64<24>(((Hi & 0x0400) << 14) | // S
1768 (~((Lo ^ (Hi << 3)) << 10) & 0x00800000) | // I1
1769 (~((Lo ^ (Hi << 1)) << 11) & 0x00400000) | // I2
1770 ((Hi & 0x003ff) << 12) | // imm0
1771 ((Lo & 0x007ff) << 1)); // imm11:0
1773 // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and
1774 // MOVT is in the range -32768 <= A < 32768
1775 case R_ARM_MOVW_ABS_NC:
1776 case R_ARM_MOVT_ABS:
1777 case R_ARM_MOVW_PREL_NC:
1778 case R_ARM_MOVT_PREL: {
1779 uint64_t Val = read32le(Buf) & 0x000f0fff;
1780 return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff));
1782 case R_ARM_THM_MOVW_ABS_NC:
1783 case R_ARM_THM_MOVT_ABS:
1784 case R_ARM_THM_MOVW_PREL_NC:
1785 case R_ARM_THM_MOVT_PREL: {
1786 // Encoding T3: A = imm4:i:imm3:imm8
1787 uint16_t Hi = read16le(Buf);
1788 uint16_t Lo = read16le(Buf + 2);
1789 return SignExtend64<16>(((Hi & 0x000f) << 12) | // imm4
1790 ((Hi & 0x0400) << 1) | // i
1791 ((Lo & 0x7000) >> 4) | // imm3
1792 (Lo & 0x00ff)); // imm8
1797 template <class ELFT> MipsTargetInfo<ELFT>::MipsTargetInfo() {
1798 GotPltHeaderEntriesNum = 2;
1800 GotEntrySize = sizeof(typename ELFT::uint);
1801 GotPltEntrySize = sizeof(typename ELFT::uint);
1804 CopyRel = R_MIPS_COPY;
1805 PltRel = R_MIPS_JUMP_SLOT;
1806 if (ELFT::Is64Bits) {
1807 RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
1808 TlsGotRel = R_MIPS_TLS_TPREL64;
1809 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
1810 TlsOffsetRel = R_MIPS_TLS_DTPREL64;
1812 RelativeRel = R_MIPS_REL32;
1813 TlsGotRel = R_MIPS_TLS_TPREL32;
1814 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
1815 TlsOffsetRel = R_MIPS_TLS_DTPREL32;
1819 template <class ELFT>
1820 RelExpr MipsTargetInfo<ELFT>::getRelExpr(uint32_t Type,
1821 const SymbolBody &S) const {
1823 // See comment in the calculateMips64RelChain.
1830 case R_MIPS_GPREL16:
1831 case R_MIPS_GPREL32:
1837 case R_MIPS_GOT_OFST:
1838 // MIPS _gp_disp designates offset between start of function and 'gp'
1839 // pointer into GOT. __gnu_local_gp is equal to the current value of
1840 // the 'gp'. Therefore any relocations against them do not require
1841 // dynamic relocation.
1842 if (&S == ElfSym<ELFT>::MipsGpDisp)
1847 case R_MIPS_PC19_S2:
1848 case R_MIPS_PC21_S2:
1849 case R_MIPS_PC26_S2:
1855 return R_MIPS_GOT_LOCAL_PAGE;
1858 case R_MIPS_GOT_DISP:
1859 case R_MIPS_TLS_GOTTPREL:
1860 return R_MIPS_GOT_OFF;
1861 case R_MIPS_GOT_PAGE:
1862 return R_MIPS_GOT_LOCAL_PAGE;
1864 return R_MIPS_TLSGD;
1865 case R_MIPS_TLS_LDM:
1866 return R_MIPS_TLSLD;
1870 template <class ELFT>
1871 uint32_t MipsTargetInfo<ELFT>::getDynRel(uint32_t Type) const {
1872 if (Type == R_MIPS_32 || Type == R_MIPS_64)
1874 // Keep it going with a dummy value so that we can find more reloc errors.
1879 template <class ELFT>
1880 bool MipsTargetInfo<ELFT>::isTlsLocalDynamicRel(uint32_t Type) const {
1881 return Type == R_MIPS_TLS_LDM;
1884 template <class ELFT>
1885 bool MipsTargetInfo<ELFT>::isTlsGlobalDynamicRel(uint32_t Type) const {
1886 return Type == R_MIPS_TLS_GD;
1889 template <class ELFT>
1890 void MipsTargetInfo<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
1891 write32<ELFT::TargetEndianness>(Buf, Out<ELFT>::Plt->getVA());
1894 static uint16_t mipsHigh(uint64_t V) { return (V + 0x8000) >> 16; }
1896 template <endianness E, uint8_t BSIZE, uint8_t SHIFT>
1897 static int64_t getPcRelocAddend(const uint8_t *Loc) {
1898 uint32_t Instr = read32<E>(Loc);
1899 uint32_t Mask = 0xffffffff >> (32 - BSIZE);
1900 return SignExtend64<BSIZE + SHIFT>((Instr & Mask) << SHIFT);
1903 template <endianness E, uint8_t BSIZE, uint8_t SHIFT>
1904 static void applyMipsPcReloc(uint8_t *Loc, uint32_t Type, uint64_t V) {
1905 uint32_t Mask = 0xffffffff >> (32 - BSIZE);
1906 uint32_t Instr = read32<E>(Loc);
1908 checkAlignment<(1 << SHIFT)>(V, Type);
1909 checkInt<BSIZE + SHIFT>(V, Type);
1910 write32<E>(Loc, (Instr & ~Mask) | ((V >> SHIFT) & Mask));
1913 template <endianness E>
1914 static void writeMipsHi16(uint8_t *Loc, uint64_t V) {
1915 uint32_t Instr = read32<E>(Loc);
1916 write32<E>(Loc, (Instr & 0xffff0000) | mipsHigh(V));
1919 template <endianness E>
1920 static void writeMipsLo16(uint8_t *Loc, uint64_t V) {
1921 uint32_t Instr = read32<E>(Loc);
1922 write32<E>(Loc, (Instr & 0xffff0000) | (V & 0xffff));
1925 template <class ELFT>
1926 void MipsTargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const {
1927 const endianness E = ELFT::TargetEndianness;
1928 write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0])
1929 write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28)
1930 write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0])
1931 write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28
1932 write32<E>(Buf + 16, 0x03e07825); // move $15, $31
1933 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2
1934 write32<E>(Buf + 24, 0x0320f809); // jalr $25
1935 write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2
1936 uint64_t Got = Out<ELFT>::GotPlt->getVA();
1937 writeMipsHi16<E>(Buf, Got);
1938 writeMipsLo16<E>(Buf + 4, Got);
1939 writeMipsLo16<E>(Buf + 8, Got);
1942 template <class ELFT>
1943 void MipsTargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr,
1944 uint64_t PltEntryAddr, int32_t Index,
1945 unsigned RelOff) const {
1946 const endianness E = ELFT::TargetEndianness;
1947 write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry)
1948 write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
1949 write32<E>(Buf + 8, 0x03200008); // jr $25
1950 write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
1951 writeMipsHi16<E>(Buf, GotEntryAddr);
1952 writeMipsLo16<E>(Buf + 4, GotEntryAddr);
1953 writeMipsLo16<E>(Buf + 12, GotEntryAddr);
1956 template <class ELFT>
1957 RelExpr MipsTargetInfo<ELFT>::getThunkExpr(RelExpr Expr, uint32_t Type,
1958 const InputFile &File,
1959 const SymbolBody &S) const {
1960 // Any MIPS PIC code function is invoked with its address in register $t9.
1961 // So if we have a branch instruction from non-PIC code to the PIC one
1962 // we cannot make the jump directly and need to create a small stubs
1963 // to save the target function address.
1964 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
1965 if (Type != R_MIPS_26)
1967 auto *F = dyn_cast<ELFFileBase<ELFT>>(&File);
1970 // If current file has PIC code, LA25 stub is not required.
1971 if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
1973 auto *D = dyn_cast<DefinedRegular<ELFT>>(&S);
1974 if (!D || !D->Section)
1976 // LA25 is required if target file has PIC code
1977 // or target symbol is a PIC symbol.
1978 const ELFFile<ELFT> &DefFile = D->Section->getFile()->getObj();
1979 bool PicFile = DefFile.getHeader()->e_flags & EF_MIPS_PIC;
1980 bool PicSym = (D->StOther & STO_MIPS_MIPS16) == STO_MIPS_PIC;
1981 return (PicFile || PicSym) ? R_THUNK_ABS : Expr;
1984 template <class ELFT>
1985 uint64_t MipsTargetInfo<ELFT>::getImplicitAddend(const uint8_t *Buf,
1986 uint32_t Type) const {
1987 const endianness E = ELFT::TargetEndianness;
1992 case R_MIPS_GPREL32:
1993 return read32<E>(Buf);
1995 // FIXME (simon): If the relocation target symbol is not a PLT entry
1996 // we should use another expression for calculation:
1997 // ((A << 2) | (P & 0xf0000000)) >> 2
1998 return SignExtend64<28>(read32<E>(Buf) << 2);
1999 case R_MIPS_GPREL16:
2002 case R_MIPS_TLS_DTPREL_HI16:
2003 case R_MIPS_TLS_DTPREL_LO16:
2004 case R_MIPS_TLS_TPREL_HI16:
2005 case R_MIPS_TLS_TPREL_LO16:
2006 return SignExtend64<16>(read32<E>(Buf));
2008 return getPcRelocAddend<E, 16, 2>(Buf);
2009 case R_MIPS_PC19_S2:
2010 return getPcRelocAddend<E, 19, 2>(Buf);
2011 case R_MIPS_PC21_S2:
2012 return getPcRelocAddend<E, 21, 2>(Buf);
2013 case R_MIPS_PC26_S2:
2014 return getPcRelocAddend<E, 26, 2>(Buf);
2016 return getPcRelocAddend<E, 32, 0>(Buf);
2020 static std::pair<uint32_t, uint64_t> calculateMips64RelChain(uint32_t Type,
2022 // MIPS N64 ABI packs multiple relocations into the single relocation
2023 // record. In general, all up to three relocations can have arbitrary
2024 // types. In fact, Clang and GCC uses only a few combinations. For now,
2025 // we support two of them. That is allow to pass at least all LLVM
2026 // test suite cases.
2027 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16
2028 // <any relocation> / R_MIPS_64 / R_MIPS_NONE
2029 // The first relocation is a 'real' relocation which is calculated
2030 // using the corresponding symbol's value. The second and the third
2031 // relocations used to modify result of the first one: extend it to
2032 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation
2033 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf
2034 uint32_t Type2 = (Type >> 8) & 0xff;
2035 uint32_t Type3 = (Type >> 16) & 0xff;
2036 if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE)
2037 return std::make_pair(Type, Val);
2038 if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE)
2039 return std::make_pair(Type2, Val);
2040 if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16))
2041 return std::make_pair(Type3, -Val);
2042 error("unsupported relocations combination " + Twine(Type));
2043 return std::make_pair(Type & 0xff, Val);
2046 template <class ELFT>
2047 void MipsTargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type,
2048 uint64_t Val) const {
2049 const endianness E = ELFT::TargetEndianness;
2050 // Thread pointer and DRP offsets from the start of TLS data area.
2051 // https://www.linux-mips.org/wiki/NPTL
2052 if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16)
2054 else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16)
2057 std::tie(Type, Val) = calculateMips64RelChain(Type, Val);
2060 case R_MIPS_GPREL32:
2061 write32<E>(Loc, Val);
2064 write64<E>(Loc, Val);
2067 write32<E>(Loc, (read32<E>(Loc) & ~0x3ffffff) | (Val >> 2));
2069 case R_MIPS_GOT_DISP:
2070 case R_MIPS_GOT_PAGE:
2072 case R_MIPS_GPREL16:
2074 case R_MIPS_TLS_LDM:
2075 checkInt<16>(Val, Type);
2078 case R_MIPS_GOT_OFST:
2081 case R_MIPS_TLS_DTPREL_LO16:
2082 case R_MIPS_TLS_GOTTPREL:
2083 case R_MIPS_TLS_TPREL_LO16:
2084 writeMipsLo16<E>(Loc, Val);
2088 case R_MIPS_TLS_DTPREL_HI16:
2089 case R_MIPS_TLS_TPREL_HI16:
2090 writeMipsHi16<E>(Loc, Val);
2093 // Ignore this optimization relocation for now
2096 applyMipsPcReloc<E, 16, 2>(Loc, Type, Val);
2098 case R_MIPS_PC19_S2:
2099 applyMipsPcReloc<E, 19, 2>(Loc, Type, Val);
2101 case R_MIPS_PC21_S2:
2102 applyMipsPcReloc<E, 21, 2>(Loc, Type, Val);
2104 case R_MIPS_PC26_S2:
2105 applyMipsPcReloc<E, 26, 2>(Loc, Type, Val);
2108 applyMipsPcReloc<E, 32, 0>(Loc, Type, Val);
2111 fatal("unrecognized reloc " + Twine(Type));
2115 template <class ELFT>
2116 bool MipsTargetInfo<ELFT>::usesOnlyLowPageBits(uint32_t Type) const {
2117 return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST;