1 //===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "lldb/Core/ArchSpec.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/Support/COFF.h"
19 #include "llvm/Support/ELF.h"
20 #include "llvm/Support/Host.h"
21 #include "lldb/Utility/SafeMachO.h"
22 #include "lldb/Core/RegularExpression.h"
23 #include "lldb/Core/StringList.h"
24 #include "lldb/Host/Endian.h"
25 #include "lldb/Host/HostInfo.h"
26 #include "lldb/Target/Platform.h"
27 #include "lldb/Target/Process.h"
28 #include "lldb/Target/RegisterContext.h"
29 #include "lldb/Target/Thread.h"
30 #include "Plugins/Process/Utility/ARMDefines.h"
31 #include "Plugins/Process/Utility/InstructionUtils.h"
34 using namespace lldb_private;
36 #define ARCH_SPEC_SEPARATOR_CHAR '-'
39 static bool cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match);
41 namespace lldb_private {
45 ByteOrder default_byte_order;
46 uint32_t addr_byte_size;
47 uint32_t min_opcode_byte_size;
48 uint32_t max_opcode_byte_size;
49 llvm::Triple::ArchType machine;
51 const char * const name;
56 // This core information can be looked using the ArchSpec::Core as the index
57 static const CoreDefinition g_core_definitions[] =
59 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_generic , "arm" },
60 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv4 , "armv4" },
61 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv4t , "armv4t" },
62 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5 , "armv5" },
63 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5e , "armv5e" },
64 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5t , "armv5t" },
65 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv6 , "armv6" },
66 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv6m , "armv6m" },
67 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7 , "armv7" },
68 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7f , "armv7f" },
69 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7s , "armv7s" },
70 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7k , "armv7k" },
71 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7m , "armv7m" },
72 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7em , "armv7em" },
73 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_xscale , "xscale" },
74 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumb , "thumb" },
75 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv4t , "thumbv4t" },
76 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv5 , "thumbv5" },
77 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv5e , "thumbv5e" },
78 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv6 , "thumbv6" },
79 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv6m , "thumbv6m" },
80 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7 , "thumbv7" },
81 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7f , "thumbv7f" },
82 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7s , "thumbv7s" },
83 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7k , "thumbv7k" },
84 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7m , "thumbv7m" },
85 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7em , "thumbv7em" },
86 { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_arm64 , "arm64" },
87 { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_armv8 , "armv8" },
88 { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_aarch64 , "aarch64" },
90 { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64 , "mips64" },
92 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_generic , "powerpc" },
93 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc601 , "ppc601" },
94 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc602 , "ppc602" },
95 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603 , "ppc603" },
96 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603e , "ppc603e" },
97 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603ev , "ppc603ev" },
98 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc604 , "ppc604" },
99 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc604e , "ppc604e" },
100 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc620 , "ppc620" },
101 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc750 , "ppc750" },
102 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc7400 , "ppc7400" },
103 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc7450 , "ppc7450" },
104 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc970 , "ppc970" },
106 { eByteOrderBig , 8, 4, 4, llvm::Triple::ppc64 , ArchSpec::eCore_ppc64_generic , "powerpc64" },
107 { eByteOrderBig , 8, 4, 4, llvm::Triple::ppc64 , ArchSpec::eCore_ppc64_ppc970_64 , "ppc970-64" },
109 { eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc , ArchSpec::eCore_sparc_generic , "sparc" },
110 { eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, ArchSpec::eCore_sparc9_generic , "sparcv9" },
112 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i386 , "i386" },
113 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i486 , "i486" },
114 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i486sx , "i486sx" },
115 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i686 , "i686" },
117 { eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64 , "x86_64" },
118 { eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64h , "x86_64h" },
119 { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_generic, "hexagon" },
120 { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4" },
121 { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5" },
123 { eByteOrderLittle, 4, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach32 , "unknown-mach-32" },
124 { eByteOrderLittle, 8, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach64 , "unknown-mach-64" },
126 { eByteOrderBig , 4, 1, 1 , llvm::Triple::kalimba , ArchSpec::eCore_kalimba3 , "kalimba3" },
127 { eByteOrderLittle, 4, 1, 1 , llvm::Triple::kalimba , ArchSpec::eCore_kalimba4 , "kalimba4" },
128 { eByteOrderLittle, 4, 1, 1 , llvm::Triple::kalimba , ArchSpec::eCore_kalimba5 , "kalimba5" }
131 // Ensure that we have an entry in the g_core_definitions for each core. If you comment out an entry above,
132 // you will need to comment out the corresponding ArchSpec::Core enumeration.
133 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == ArchSpec::kNumCores, "make sure we have one core definition for each core");
136 struct ArchDefinitionEntry
145 struct ArchDefinition
147 ArchitectureType type;
149 const ArchDefinitionEntry *entries;
155 ArchSpec::AutoComplete (const char *name, StringList &matches)
160 for (i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
162 if (NameMatches(g_core_definitions[i].name, eNameMatchStartsWith, name))
163 matches.AppendString (g_core_definitions[i].name);
168 for (i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
169 matches.AppendString (g_core_definitions[i].name);
171 return matches.GetSize();
176 #define CPU_ANY (UINT32_MAX)
178 //===----------------------------------------------------------------------===//
179 // A table that gets searched linearly for matches. This table is used to
180 // convert cpu type and subtypes to architecture names, and to convert
181 // architecture names to cpu types and subtypes. The ordering is important and
182 // allows the precedence to be set when the table is built.
183 #define SUBTYPE_MASK 0x00FFFFFFu
184 static const ArchDefinitionEntry g_macho_arch_entries[] =
186 { ArchSpec::eCore_arm_generic , llvm::MachO::CPU_TYPE_ARM , CPU_ANY, UINT32_MAX , UINT32_MAX },
187 { ArchSpec::eCore_arm_generic , llvm::MachO::CPU_TYPE_ARM , 0 , UINT32_MAX , SUBTYPE_MASK },
188 { ArchSpec::eCore_arm_armv4 , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK },
189 { ArchSpec::eCore_arm_armv4t , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK },
190 { ArchSpec::eCore_arm_armv6 , llvm::MachO::CPU_TYPE_ARM , 6 , UINT32_MAX , SUBTYPE_MASK },
191 { ArchSpec::eCore_arm_armv6m , llvm::MachO::CPU_TYPE_ARM , 14 , UINT32_MAX , SUBTYPE_MASK },
192 { ArchSpec::eCore_arm_armv5 , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
193 { ArchSpec::eCore_arm_armv5e , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
194 { ArchSpec::eCore_arm_armv5t , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
195 { ArchSpec::eCore_arm_xscale , llvm::MachO::CPU_TYPE_ARM , 8 , UINT32_MAX , SUBTYPE_MASK },
196 { ArchSpec::eCore_arm_armv7 , llvm::MachO::CPU_TYPE_ARM , 9 , UINT32_MAX , SUBTYPE_MASK },
197 { ArchSpec::eCore_arm_armv7f , llvm::MachO::CPU_TYPE_ARM , 10 , UINT32_MAX , SUBTYPE_MASK },
198 { ArchSpec::eCore_arm_armv7s , llvm::MachO::CPU_TYPE_ARM , 11 , UINT32_MAX , SUBTYPE_MASK },
199 { ArchSpec::eCore_arm_armv7k , llvm::MachO::CPU_TYPE_ARM , 12 , UINT32_MAX , SUBTYPE_MASK },
200 { ArchSpec::eCore_arm_armv7m , llvm::MachO::CPU_TYPE_ARM , 15 , UINT32_MAX , SUBTYPE_MASK },
201 { ArchSpec::eCore_arm_armv7em , llvm::MachO::CPU_TYPE_ARM , 16 , UINT32_MAX , SUBTYPE_MASK },
202 { ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , 1 , UINT32_MAX , SUBTYPE_MASK },
203 { ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , 0 , UINT32_MAX , SUBTYPE_MASK },
204 { ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , 13 , UINT32_MAX , SUBTYPE_MASK },
205 { ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , CPU_ANY, UINT32_MAX , SUBTYPE_MASK },
206 { ArchSpec::eCore_thumb , llvm::MachO::CPU_TYPE_ARM , 0 , UINT32_MAX , SUBTYPE_MASK },
207 { ArchSpec::eCore_thumbv4t , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK },
208 { ArchSpec::eCore_thumbv5 , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
209 { ArchSpec::eCore_thumbv5e , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
210 { ArchSpec::eCore_thumbv6 , llvm::MachO::CPU_TYPE_ARM , 6 , UINT32_MAX , SUBTYPE_MASK },
211 { ArchSpec::eCore_thumbv6m , llvm::MachO::CPU_TYPE_ARM , 14 , UINT32_MAX , SUBTYPE_MASK },
212 { ArchSpec::eCore_thumbv7 , llvm::MachO::CPU_TYPE_ARM , 9 , UINT32_MAX , SUBTYPE_MASK },
213 { ArchSpec::eCore_thumbv7f , llvm::MachO::CPU_TYPE_ARM , 10 , UINT32_MAX , SUBTYPE_MASK },
214 { ArchSpec::eCore_thumbv7s , llvm::MachO::CPU_TYPE_ARM , 11 , UINT32_MAX , SUBTYPE_MASK },
215 { ArchSpec::eCore_thumbv7k , llvm::MachO::CPU_TYPE_ARM , 12 , UINT32_MAX , SUBTYPE_MASK },
216 { ArchSpec::eCore_thumbv7m , llvm::MachO::CPU_TYPE_ARM , 15 , UINT32_MAX , SUBTYPE_MASK },
217 { ArchSpec::eCore_thumbv7em , llvm::MachO::CPU_TYPE_ARM , 16 , UINT32_MAX , SUBTYPE_MASK },
218 { ArchSpec::eCore_ppc_generic , llvm::MachO::CPU_TYPE_POWERPC , CPU_ANY, UINT32_MAX , UINT32_MAX },
219 { ArchSpec::eCore_ppc_generic , llvm::MachO::CPU_TYPE_POWERPC , 0 , UINT32_MAX , SUBTYPE_MASK },
220 { ArchSpec::eCore_ppc_ppc601 , llvm::MachO::CPU_TYPE_POWERPC , 1 , UINT32_MAX , SUBTYPE_MASK },
221 { ArchSpec::eCore_ppc_ppc602 , llvm::MachO::CPU_TYPE_POWERPC , 2 , UINT32_MAX , SUBTYPE_MASK },
222 { ArchSpec::eCore_ppc_ppc603 , llvm::MachO::CPU_TYPE_POWERPC , 3 , UINT32_MAX , SUBTYPE_MASK },
223 { ArchSpec::eCore_ppc_ppc603e , llvm::MachO::CPU_TYPE_POWERPC , 4 , UINT32_MAX , SUBTYPE_MASK },
224 { ArchSpec::eCore_ppc_ppc603ev , llvm::MachO::CPU_TYPE_POWERPC , 5 , UINT32_MAX , SUBTYPE_MASK },
225 { ArchSpec::eCore_ppc_ppc604 , llvm::MachO::CPU_TYPE_POWERPC , 6 , UINT32_MAX , SUBTYPE_MASK },
226 { ArchSpec::eCore_ppc_ppc604e , llvm::MachO::CPU_TYPE_POWERPC , 7 , UINT32_MAX , SUBTYPE_MASK },
227 { ArchSpec::eCore_ppc_ppc620 , llvm::MachO::CPU_TYPE_POWERPC , 8 , UINT32_MAX , SUBTYPE_MASK },
228 { ArchSpec::eCore_ppc_ppc750 , llvm::MachO::CPU_TYPE_POWERPC , 9 , UINT32_MAX , SUBTYPE_MASK },
229 { ArchSpec::eCore_ppc_ppc7400 , llvm::MachO::CPU_TYPE_POWERPC , 10 , UINT32_MAX , SUBTYPE_MASK },
230 { ArchSpec::eCore_ppc_ppc7450 , llvm::MachO::CPU_TYPE_POWERPC , 11 , UINT32_MAX , SUBTYPE_MASK },
231 { ArchSpec::eCore_ppc_ppc970 , llvm::MachO::CPU_TYPE_POWERPC , 100 , UINT32_MAX , SUBTYPE_MASK },
232 { ArchSpec::eCore_ppc64_generic , llvm::MachO::CPU_TYPE_POWERPC64 , 0 , UINT32_MAX , SUBTYPE_MASK },
233 { ArchSpec::eCore_ppc64_ppc970_64 , llvm::MachO::CPU_TYPE_POWERPC64 , 100 , UINT32_MAX , SUBTYPE_MASK },
234 { ArchSpec::eCore_x86_32_i386 , llvm::MachO::CPU_TYPE_I386 , 3 , UINT32_MAX , SUBTYPE_MASK },
235 { ArchSpec::eCore_x86_32_i486 , llvm::MachO::CPU_TYPE_I386 , 4 , UINT32_MAX , SUBTYPE_MASK },
236 { ArchSpec::eCore_x86_32_i486sx , llvm::MachO::CPU_TYPE_I386 , 0x84 , UINT32_MAX , SUBTYPE_MASK },
237 { ArchSpec::eCore_x86_32_i386 , llvm::MachO::CPU_TYPE_I386 , CPU_ANY, UINT32_MAX , UINT32_MAX },
238 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , 3 , UINT32_MAX , SUBTYPE_MASK },
239 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , 4 , UINT32_MAX , SUBTYPE_MASK },
240 { ArchSpec::eCore_x86_64_x86_64h , llvm::MachO::CPU_TYPE_X86_64 , 8 , UINT32_MAX , SUBTYPE_MASK },
241 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , CPU_ANY, UINT32_MAX , UINT32_MAX },
242 // Catch any unknown mach architectures so we can always use the object and symbol mach-o files
243 { ArchSpec::eCore_uknownMach32 , 0 , 0 , 0xFF000000u, 0x00000000u },
244 { ArchSpec::eCore_uknownMach64 , llvm::MachO::CPU_ARCH_ABI64 , 0 , 0xFF000000u, 0x00000000u }
246 static const ArchDefinition g_macho_arch_def = {
248 llvm::array_lengthof(g_macho_arch_entries),
249 g_macho_arch_entries,
253 //===----------------------------------------------------------------------===//
254 // A table that gets searched linearly for matches. This table is used to
255 // convert cpu type and subtypes to architecture names, and to convert
256 // architecture names to cpu types and subtypes. The ordering is important and
257 // allows the precedence to be set when the table is built.
258 static const ArchDefinitionEntry g_elf_arch_entries[] =
260 { ArchSpec::eCore_sparc_generic , llvm::ELF::EM_SPARC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Sparc
261 { ArchSpec::eCore_x86_32_i386 , llvm::ELF::EM_386 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 80386
262 { ArchSpec::eCore_x86_32_i486 , llvm::ELF::EM_486 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 486 (deprecated)
263 { ArchSpec::eCore_ppc_generic , llvm::ELF::EM_PPC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC
264 { ArchSpec::eCore_ppc64_generic , llvm::ELF::EM_PPC64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC64
265 { ArchSpec::eCore_arm_generic , llvm::ELF::EM_ARM , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM
266 { ArchSpec::eCore_arm_aarch64 , llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM64
267 { ArchSpec::eCore_sparc9_generic , llvm::ELF::EM_SPARCV9, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // SPARC V9
268 { ArchSpec::eCore_x86_64_x86_64 , llvm::ELF::EM_X86_64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // AMD64
269 { ArchSpec::eCore_mips64 , llvm::ELF::EM_MIPS , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // MIPS
270 { ArchSpec::eCore_hexagon_generic , llvm::ELF::EM_HEXAGON, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // HEXAGON
271 { ArchSpec::eCore_kalimba3 , llvm::ELF::EM_CSR_KALIMBA, llvm::Triple::KalimbaSubArch_v3, 0xFFFFFFFFu, 0xFFFFFFFFu }, // KALIMBA
272 { ArchSpec::eCore_kalimba4 , llvm::ELF::EM_CSR_KALIMBA, llvm::Triple::KalimbaSubArch_v4, 0xFFFFFFFFu, 0xFFFFFFFFu }, // KALIMBA
273 { ArchSpec::eCore_kalimba5 , llvm::ELF::EM_CSR_KALIMBA, llvm::Triple::KalimbaSubArch_v5, 0xFFFFFFFFu, 0xFFFFFFFFu } // KALIMBA
276 static const ArchDefinition g_elf_arch_def = {
278 llvm::array_lengthof(g_elf_arch_entries),
283 static const ArchDefinitionEntry g_coff_arch_entries[] =
285 { ArchSpec::eCore_x86_32_i386 , llvm::COFF::IMAGE_FILE_MACHINE_I386 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 80x86
286 { ArchSpec::eCore_ppc_generic , llvm::COFF::IMAGE_FILE_MACHINE_POWERPC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC
287 { ArchSpec::eCore_ppc_generic , llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC (with FPU)
288 { ArchSpec::eCore_arm_generic , llvm::COFF::IMAGE_FILE_MACHINE_ARM , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM
289 { ArchSpec::eCore_arm_armv7 , llvm::COFF::IMAGE_FILE_MACHINE_ARMNT , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARMv7
290 { ArchSpec::eCore_thumb , llvm::COFF::IMAGE_FILE_MACHINE_THUMB , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARMv7
291 { ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu } // AMD64
294 static const ArchDefinition g_coff_arch_def = {
296 llvm::array_lengthof(g_coff_arch_entries),
301 //===----------------------------------------------------------------------===//
302 // Table of all ArchDefinitions
303 static const ArchDefinition *g_arch_definitions[] = {
309 static const size_t k_num_arch_definitions = llvm::array_lengthof(g_arch_definitions);
311 //===----------------------------------------------------------------------===//
312 // Static helper functions.
315 // Get the architecture definition for a given object type.
316 static const ArchDefinition *
317 FindArchDefinition (ArchitectureType arch_type)
319 for (unsigned int i = 0; i < k_num_arch_definitions; ++i)
321 const ArchDefinition *def = g_arch_definitions[i];
322 if (def->type == arch_type)
328 // Get an architecture definition by name.
329 static const CoreDefinition *
330 FindCoreDefinition (llvm::StringRef name)
332 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
334 if (name.equals_lower(g_core_definitions[i].name))
335 return &g_core_definitions[i];
340 static inline const CoreDefinition *
341 FindCoreDefinition (ArchSpec::Core core)
343 if (core >= 0 && core < llvm::array_lengthof(g_core_definitions))
344 return &g_core_definitions[core];
348 // Get a definition entry by cpu type and subtype.
349 static const ArchDefinitionEntry *
350 FindArchDefinitionEntry (const ArchDefinition *def, uint32_t cpu, uint32_t sub)
355 const ArchDefinitionEntry *entries = def->entries;
356 for (size_t i = 0; i < def->num_entries; ++i)
358 if (entries[i].cpu == (cpu & entries[i].cpu_mask))
359 if (entries[i].sub == (sub & entries[i].sub_mask))
365 static const ArchDefinitionEntry *
366 FindArchDefinitionEntry (const ArchDefinition *def, ArchSpec::Core core)
371 const ArchDefinitionEntry *entries = def->entries;
372 for (size_t i = 0; i < def->num_entries; ++i)
374 if (entries[i].core == core)
380 //===----------------------------------------------------------------------===//
381 // Constructors and destructors.
383 ArchSpec::ArchSpec() :
385 m_core (kCore_invalid),
386 m_byte_order (eByteOrderInvalid),
391 ArchSpec::ArchSpec (const char *triple_cstr, Platform *platform) :
393 m_core (kCore_invalid),
394 m_byte_order (eByteOrderInvalid),
398 SetTriple(triple_cstr, platform);
402 ArchSpec::ArchSpec (const char *triple_cstr) :
404 m_core (kCore_invalid),
405 m_byte_order (eByteOrderInvalid),
409 SetTriple(triple_cstr);
412 ArchSpec::ArchSpec(const llvm::Triple &triple) :
414 m_core (kCore_invalid),
415 m_byte_order (eByteOrderInvalid),
421 ArchSpec::ArchSpec (ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) :
423 m_core (kCore_invalid),
424 m_byte_order (eByteOrderInvalid),
427 SetArchitecture (arch_type, cpu, subtype);
430 ArchSpec::~ArchSpec()
434 //===----------------------------------------------------------------------===//
435 // Assignment and initialization.
438 ArchSpec::operator= (const ArchSpec& rhs)
442 m_triple = rhs.m_triple;
444 m_byte_order = rhs.m_byte_order;
445 m_distribution_id = rhs.m_distribution_id;
453 m_triple = llvm::Triple();
454 m_core = kCore_invalid;
455 m_byte_order = eByteOrderInvalid;
456 m_distribution_id.Clear ();
459 //===----------------------------------------------------------------------===//
464 ArchSpec::GetArchitectureName () const
466 const CoreDefinition *core_def = FindCoreDefinition (m_core);
468 return core_def->name;
473 ArchSpec::GetMachOCPUType () const
475 const CoreDefinition *core_def = FindCoreDefinition (m_core);
478 const ArchDefinitionEntry *arch_def = FindArchDefinitionEntry (&g_macho_arch_def, core_def->core);
481 return arch_def->cpu;
484 return LLDB_INVALID_CPUTYPE;
488 ArchSpec::GetMachOCPUSubType () const
490 const CoreDefinition *core_def = FindCoreDefinition (m_core);
493 const ArchDefinitionEntry *arch_def = FindArchDefinitionEntry (&g_macho_arch_def, core_def->core);
496 return arch_def->sub;
499 return LLDB_INVALID_CPUTYPE;
503 ArchSpec::GetDataByteSize () const
520 ArchSpec::GetCodeByteSize () const
536 llvm::Triple::ArchType
537 ArchSpec::GetMachine () const
539 const CoreDefinition *core_def = FindCoreDefinition (m_core);
541 return core_def->machine;
543 return llvm::Triple::UnknownArch;
547 ArchSpec::GetDistributionId () const
549 return m_distribution_id;
553 ArchSpec::SetDistributionId (const char* distribution_id)
555 m_distribution_id.SetCString (distribution_id);
559 ArchSpec::GetAddressByteSize() const
561 const CoreDefinition *core_def = FindCoreDefinition (m_core);
563 return core_def->addr_byte_size;
568 ArchSpec::GetDefaultEndian () const
570 const CoreDefinition *core_def = FindCoreDefinition (m_core);
572 return core_def->default_byte_order;
573 return eByteOrderInvalid;
577 ArchSpec::GetByteOrder () const
579 if (m_byte_order == eByteOrderInvalid)
580 return GetDefaultEndian();
584 //===----------------------------------------------------------------------===//
588 ArchSpec::SetTriple (const llvm::Triple &triple)
592 llvm::StringRef arch_name (m_triple.getArchName());
593 const CoreDefinition *core_def = FindCoreDefinition (arch_name);
596 m_core = core_def->core;
597 // Set the byte order to the default byte order for an architecture.
598 // This can be modified if needed for cases when cores handle both
599 // big and little endian
600 m_byte_order = core_def->default_byte_order;
612 ParseMachCPUDashSubtypeTriple (const char *triple_cstr, ArchSpec &arch)
614 // Accept "12-10" or "12.10" as cpu type/subtype
615 if (isdigit(triple_cstr[0]))
619 uint32_t cpu = (uint32_t)::strtoul (triple_cstr, &end, 0);
620 if (errno == 0 && cpu != 0 && end && ((*end == '-') || (*end == '.')))
623 uint32_t sub = (uint32_t)::strtoul (end + 1, &end, 0);
624 if (errno == 0 && end && ((*end == '-') || (*end == '.') || (*end == '\0')))
626 if (arch.SetArchitecture (eArchTypeMachO, cpu, sub))
630 llvm::StringRef vendor_os (end + 1);
631 size_t dash_pos = vendor_os.find('-');
632 if (dash_pos != llvm::StringRef::npos)
634 llvm::StringRef vendor_str(vendor_os.substr(0, dash_pos));
635 arch.GetTriple().setVendorName(vendor_str);
636 const size_t vendor_start_pos = dash_pos+1;
637 dash_pos = vendor_os.find('-', vendor_start_pos);
638 if (dash_pos == llvm::StringRef::npos)
640 if (vendor_start_pos < vendor_os.size())
641 arch.GetTriple().setOSName(vendor_os.substr(vendor_start_pos));
645 arch.GetTriple().setOSName(vendor_os.substr(vendor_start_pos, dash_pos - vendor_start_pos));
657 ArchSpec::SetTriple (const char *triple_cstr)
659 if (triple_cstr && triple_cstr[0])
661 if (ParseMachCPUDashSubtypeTriple (triple_cstr, *this))
664 llvm::StringRef triple_stref (triple_cstr);
665 if (triple_stref.startswith (LLDB_ARCH_DEFAULT))
667 // Special case for the current host default architectures...
668 if (triple_stref.equals (LLDB_ARCH_DEFAULT_32BIT))
669 *this = HostInfo::GetArchitecture(HostInfo::eArchKind32);
670 else if (triple_stref.equals (LLDB_ARCH_DEFAULT_64BIT))
671 *this = HostInfo::GetArchitecture(HostInfo::eArchKind64);
672 else if (triple_stref.equals (LLDB_ARCH_DEFAULT))
673 *this = HostInfo::GetArchitecture(HostInfo::eArchKindDefault);
677 std::string normalized_triple_sstr (llvm::Triple::normalize(triple_stref));
678 triple_stref = normalized_triple_sstr;
679 SetTriple (llvm::Triple (triple_stref));
688 ArchSpec::SetTriple (const char *triple_cstr, Platform *platform)
690 if (triple_cstr && triple_cstr[0])
692 if (ParseMachCPUDashSubtypeTriple (triple_cstr, *this))
695 llvm::StringRef triple_stref (triple_cstr);
696 if (triple_stref.startswith (LLDB_ARCH_DEFAULT))
698 // Special case for the current host default architectures...
699 if (triple_stref.equals (LLDB_ARCH_DEFAULT_32BIT))
700 *this = HostInfo::GetArchitecture(HostInfo::eArchKind32);
701 else if (triple_stref.equals (LLDB_ARCH_DEFAULT_64BIT))
702 *this = HostInfo::GetArchitecture(HostInfo::eArchKind64);
703 else if (triple_stref.equals (LLDB_ARCH_DEFAULT))
704 *this = HostInfo::GetArchitecture(HostInfo::eArchKindDefault);
708 ArchSpec raw_arch (triple_cstr);
710 std::string normalized_triple_sstr (llvm::Triple::normalize(triple_stref));
711 triple_stref = normalized_triple_sstr;
712 llvm::Triple normalized_triple (triple_stref);
714 const bool os_specified = normalized_triple.getOSName().size() > 0;
715 const bool vendor_specified = normalized_triple.getVendorName().size() > 0;
716 const bool env_specified = normalized_triple.getEnvironmentName().size() > 0;
718 // If we got an arch only, then default the vendor, os, environment
719 // to match the platform if one is supplied
720 if (!(os_specified || vendor_specified || env_specified))
724 // If we were given a platform, use the platform's system
725 // architecture. If this is not available (might not be
726 // connected) use the first supported architecture.
727 ArchSpec compatible_arch;
728 if (platform->IsCompatibleArchitecture (raw_arch, false, &compatible_arch))
730 if (compatible_arch.IsValid())
732 const llvm::Triple &compatible_triple = compatible_arch.GetTriple();
733 if (!vendor_specified)
734 normalized_triple.setVendor(compatible_triple.getVendor());
736 normalized_triple.setOS(compatible_triple.getOS());
737 if (!env_specified && compatible_triple.getEnvironmentName().size())
738 normalized_triple.setEnvironment(compatible_triple.getEnvironment());
749 // No platform specified, fall back to the host system for
750 // the default vendor, os, and environment.
751 llvm::Triple host_triple(llvm::sys::getDefaultTargetTriple());
752 if (!vendor_specified)
753 normalized_triple.setVendor(host_triple.getVendor());
754 if (!vendor_specified)
755 normalized_triple.setOS(host_triple.getOS());
756 if (!env_specified && host_triple.getEnvironmentName().size())
757 normalized_triple.setEnvironment(host_triple.getEnvironment());
760 SetTriple (normalized_triple);
769 ArchSpec::SetArchitecture (ArchitectureType arch_type, uint32_t cpu, uint32_t sub)
771 m_core = kCore_invalid;
772 bool update_triple = true;
773 const ArchDefinition *arch_def = FindArchDefinition(arch_type);
776 const ArchDefinitionEntry *arch_def_entry = FindArchDefinitionEntry (arch_def, cpu, sub);
779 const CoreDefinition *core_def = FindCoreDefinition (arch_def_entry->core);
782 m_core = core_def->core;
783 update_triple = false;
784 // Always use the architecture name because it might be more descriptive
785 // than the architecture enum ("armv7" -> llvm::Triple::arm).
786 m_triple.setArchName(llvm::StringRef(core_def->name));
787 if (arch_type == eArchTypeMachO)
789 m_triple.setVendor (llvm::Triple::Apple);
791 switch (core_def->machine)
793 case llvm::Triple::aarch64:
794 case llvm::Triple::arm:
795 case llvm::Triple::thumb:
796 m_triple.setOS (llvm::Triple::IOS);
799 case llvm::Triple::x86:
800 case llvm::Triple::x86_64:
801 // Don't set the OS for x86_64 or for x86 as we want to leave it as an "unspecified unknown"
802 // which means if we ask for the OS from the llvm::Triple we get back llvm::Triple::UnknownOS, but
803 // if we ask for the string value for the OS it will come back empty (unspecified).
804 // We do this because we now have iOS and MacOSX as the OS values for x86 and x86_64 for
805 // normal desktop and simulator binaries. And if we compare a "x86_64-apple-ios" to a "x86_64-apple-"
806 // triple, it will say it is compatible (because the OS is unspecified in the second one and will match
807 // anything in the first
811 m_triple.setOS (llvm::Triple::MacOSX);
817 m_triple.setVendor (llvm::Triple::UnknownVendor);
818 m_triple.setOS (llvm::Triple::UnknownOS);
820 // Fall back onto setting the machine type if the arch by name failed...
821 if (m_triple.getArch () == llvm::Triple::UnknownArch)
822 m_triple.setArch (core_def->machine);
826 CoreUpdated(update_triple);
831 ArchSpec::GetMinimumOpcodeByteSize() const
833 const CoreDefinition *core_def = FindCoreDefinition (m_core);
835 return core_def->min_opcode_byte_size;
840 ArchSpec::GetMaximumOpcodeByteSize() const
842 const CoreDefinition *core_def = FindCoreDefinition (m_core);
844 return core_def->max_opcode_byte_size;
849 ArchSpec::IsExactMatch (const ArchSpec& rhs) const
851 return IsEqualTo (rhs, true);
855 ArchSpec::IsCompatibleMatch (const ArchSpec& rhs) const
857 return IsEqualTo (rhs, false);
861 ArchSpec::IsEqualTo (const ArchSpec& rhs, bool exact_match) const
863 // explicitly ignoring m_distribution_id in this method.
865 if (GetByteOrder() != rhs.GetByteOrder())
868 const ArchSpec::Core lhs_core = GetCore ();
869 const ArchSpec::Core rhs_core = rhs.GetCore ();
871 const bool core_match = cores_match (lhs_core, rhs_core, true, exact_match);
875 const llvm::Triple &lhs_triple = GetTriple();
876 const llvm::Triple &rhs_triple = rhs.GetTriple();
878 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor();
879 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor();
880 if (lhs_triple_vendor != rhs_triple_vendor)
884 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified();
885 const bool lhs_vendor_specified = TripleVendorWasSpecified();
886 // Both architectures had the vendor specified, so if they aren't
887 // equal then we return false
888 if (rhs_vendor_specified && lhs_vendor_specified)
892 // Only fail if both vendor types are not unknown
893 if (lhs_triple_vendor != llvm::Triple::UnknownVendor &&
894 rhs_triple_vendor != llvm::Triple::UnknownVendor)
898 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS();
899 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS();
900 if (lhs_triple_os != rhs_triple_os)
904 const bool rhs_os_specified = rhs.TripleOSWasSpecified();
905 const bool lhs_os_specified = TripleOSWasSpecified();
906 // Both architectures had the OS specified, so if they aren't
907 // equal then we return false
908 if (rhs_os_specified && lhs_os_specified)
912 // Only fail if both os types are not unknown
913 if (lhs_triple_os != llvm::Triple::UnknownOS &&
914 rhs_triple_os != llvm::Triple::UnknownOS)
918 const llvm::Triple::EnvironmentType lhs_triple_env = lhs_triple.getEnvironment();
919 const llvm::Triple::EnvironmentType rhs_triple_env = rhs_triple.getEnvironment();
921 if (lhs_triple_env != rhs_triple_env)
923 // Only fail if both environment types are not unknown
924 if (lhs_triple_env != llvm::Triple::UnknownEnvironment &&
925 rhs_triple_env != llvm::Triple::UnknownEnvironment)
933 //===----------------------------------------------------------------------===//
937 ArchSpec::CoreUpdated (bool update_triple)
939 const CoreDefinition *core_def = FindCoreDefinition (m_core);
943 m_triple = llvm::Triple(core_def->name, "unknown", "unknown");
944 m_byte_order = core_def->default_byte_order;
949 m_triple = llvm::Triple();
950 m_byte_order = eByteOrderInvalid;
954 //===----------------------------------------------------------------------===//
958 cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match)
965 case ArchSpec::kCore_any:
968 case ArchSpec::eCore_arm_generic:
969 if (enforce_exact_match)
971 // Fall through to case below
972 case ArchSpec::kCore_arm_any:
973 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last)
975 if (core2 >= ArchSpec::kCore_thumb_first && core2 <= ArchSpec::kCore_thumb_last)
977 if (core2 == ArchSpec::kCore_arm_any)
981 case ArchSpec::kCore_x86_32_any:
982 if ((core2 >= ArchSpec::kCore_x86_32_first && core2 <= ArchSpec::kCore_x86_32_last) || (core2 == ArchSpec::kCore_x86_32_any))
986 case ArchSpec::kCore_x86_64_any:
987 if ((core2 >= ArchSpec::kCore_x86_64_first && core2 <= ArchSpec::kCore_x86_64_last) || (core2 == ArchSpec::kCore_x86_64_any))
991 case ArchSpec::kCore_ppc_any:
992 if ((core2 >= ArchSpec::kCore_ppc_first && core2 <= ArchSpec::kCore_ppc_last) || (core2 == ArchSpec::kCore_ppc_any))
996 case ArchSpec::kCore_ppc64_any:
997 if ((core2 >= ArchSpec::kCore_ppc64_first && core2 <= ArchSpec::kCore_ppc64_last) || (core2 == ArchSpec::kCore_ppc64_any))
1001 case ArchSpec::eCore_arm_armv6m:
1002 if (!enforce_exact_match)
1004 if (core2 == ArchSpec::eCore_arm_generic)
1006 try_inverse = false;
1007 if (core2 == ArchSpec::eCore_arm_armv7)
1012 case ArchSpec::kCore_hexagon_any:
1013 if ((core2 >= ArchSpec::kCore_hexagon_first && core2 <= ArchSpec::kCore_hexagon_last) || (core2 == ArchSpec::kCore_hexagon_any))
1017 case ArchSpec::eCore_arm_armv7m:
1018 case ArchSpec::eCore_arm_armv7em:
1019 case ArchSpec::eCore_arm_armv7f:
1020 case ArchSpec::eCore_arm_armv7k:
1021 case ArchSpec::eCore_arm_armv7s:
1022 if (!enforce_exact_match)
1024 if (core2 == ArchSpec::eCore_arm_generic)
1026 if (core2 == ArchSpec::eCore_arm_armv7)
1028 try_inverse = false;
1032 case ArchSpec::eCore_x86_64_x86_64h:
1033 if (!enforce_exact_match)
1035 try_inverse = false;
1036 if (core2 == ArchSpec::eCore_x86_64_x86_64)
1041 case ArchSpec::eCore_arm_armv8:
1042 if (!enforce_exact_match)
1044 if (core2 == ArchSpec::eCore_arm_arm64)
1046 if (core2 == ArchSpec::eCore_arm_aarch64)
1048 try_inverse = false;
1052 case ArchSpec::eCore_arm_aarch64:
1053 if (!enforce_exact_match)
1055 if (core2 == ArchSpec::eCore_arm_arm64)
1057 if (core2 == ArchSpec::eCore_arm_armv8)
1059 try_inverse = false;
1063 case ArchSpec::eCore_arm_arm64:
1064 if (!enforce_exact_match)
1066 if (core2 == ArchSpec::eCore_arm_aarch64)
1068 if (core2 == ArchSpec::eCore_arm_armv8)
1070 try_inverse = false;
1078 return cores_match (core2, core1, false, enforce_exact_match);
1083 lldb_private::operator<(const ArchSpec& lhs, const ArchSpec& rhs)
1085 const ArchSpec::Core lhs_core = lhs.GetCore ();
1086 const ArchSpec::Core rhs_core = rhs.GetCore ();
1087 return lhs_core < rhs_core;
1091 StopInfoOverrideCallbackTypeARM(lldb_private::Thread &thread)
1093 // We need to check if we are stopped in Thumb mode in a IT instruction
1094 // and detect if the condition doesn't pass. If this is the case it means
1095 // we won't actually execute this instruction. If this happens we need to
1096 // clear the stop reason to no thread plans think we are stopped for a
1097 // reason and the plans should keep going.
1099 // We do this because when single stepping many ARM processes, debuggers
1100 // often use the BVR/BCR registers that says "stop when the PC is not
1101 // equal to its current value". This method of stepping means we can end
1102 // up stopping on instructions inside an if/then block that wouldn't get
1103 // executed. By fixing this we can stop the debugger from seeming like
1104 // you stepped through both the "if" _and_ the "else" clause when source
1105 // level stepping because the debugger stops regardless due to the BVR/BCR
1106 // triggering a stop.
1108 // It also means we can set breakpoints on instructions inside an an
1109 // if/then block and correctly skip them if we use the BKPT instruction.
1110 // The ARM and Thumb BKPT instructions are unconditional even when executed
1111 // in a Thumb IT block.
1113 // If your debugger inserts software traps in ARM/Thumb code, it will
1114 // need to use 16 and 32 bit instruction for 16 and 32 bit thumb
1115 // instructions respectively. If your debugger inserts a 16 bit thumb
1116 // trap on top of a 32 bit thumb instruction for an opcode that is inside
1117 // an if/then, it will change the it/then to conditionally execute your
1118 // 16 bit trap and then cause your program to crash if it executes the
1119 // trailing 16 bits (the second half of the 32 bit thumb instruction you
1120 // partially overwrote).
1122 RegisterContextSP reg_ctx_sp (thread.GetRegisterContext());
1125 const uint32_t cpsr = reg_ctx_sp->GetFlags(0);
1128 // Read the J and T bits to get the ISETSTATE
1129 const uint32_t J = Bit32(cpsr, 24);
1130 const uint32_t T = Bit32(cpsr, 5);
1131 const uint32_t ISETSTATE = J << 1 | T;
1134 // NOTE: I am pretty sure we want to enable the code below
1135 // that detects when we stop on an instruction in ARM mode
1136 // that is conditional and the condition doesn't pass. This
1137 // can happen if you set a breakpoint on an instruction that
1138 // is conditional. We currently will _always_ stop on the
1139 // instruction which is bad. You can also run into this while
1140 // single stepping and you could appear to run code in the "if"
1141 // and in the "else" clause because it would stop at all of the
1142 // conditional instructions in both.
1143 // In such cases, we really don't want to stop at this location.
1144 // I will check with the lldb-dev list first before I enable this.
1146 // ARM mode: check for condition on intsruction
1147 const addr_t pc = reg_ctx_sp->GetPC();
1149 // If we fail to read the opcode we will get UINT64_MAX as the
1150 // result in "opcode" which we can use to detect if we read a
1152 const uint64_t opcode = thread.GetProcess()->ReadUnsignedIntegerFromMemory(pc, 4, UINT64_MAX, error);
1153 if (opcode <= UINT32_MAX)
1155 const uint32_t condition = Bits32((uint32_t)opcode, 31, 28);
1156 if (ARMConditionPassed(condition, cpsr) == false)
1158 // We ARE stopped on an ARM instruction whose condition doesn't
1159 // pass so this instruction won't get executed.
1160 // Regardless of why it stopped, we need to clear the stop info
1161 thread.SetStopInfo (StopInfoSP());
1166 else if (ISETSTATE == 1)
1169 const uint32_t ITSTATE = Bits32 (cpsr, 15, 10) << 2 | Bits32 (cpsr, 26, 25);
1172 const uint32_t condition = Bits32(ITSTATE, 7, 4);
1173 if (ARMConditionPassed(condition, cpsr) == false)
1175 // We ARE stopped in a Thumb IT instruction on an instruction whose
1176 // condition doesn't pass so this instruction won't get executed.
1177 // Regardless of why it stopped, we need to clear the stop info
1178 thread.SetStopInfo (StopInfoSP());
1186 ArchSpec::StopInfoOverrideCallbackType
1187 ArchSpec::GetStopInfoOverrideCallback () const
1189 const llvm::Triple::ArchType machine = GetMachine();
1190 if (machine == llvm::Triple::arm)
1191 return StopInfoOverrideCallbackTypeARM;