1 //===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "lldb/Core/ArchSpec.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/Support/COFF.h"
19 #include "llvm/Support/ELF.h"
20 #include "llvm/Support/Host.h"
21 #include "lldb/Utility/SafeMachO.h"
22 #include "lldb/Core/RegularExpression.h"
23 #include "lldb/Core/StringList.h"
24 #include "lldb/Host/Endian.h"
25 #include "lldb/Host/HostInfo.h"
26 #include "lldb/Target/Platform.h"
29 using namespace lldb_private;
31 #define ARCH_SPEC_SEPARATOR_CHAR '-'
34 static bool cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match);
36 namespace lldb_private {
40 ByteOrder default_byte_order;
41 uint32_t addr_byte_size;
42 uint32_t min_opcode_byte_size;
43 uint32_t max_opcode_byte_size;
44 llvm::Triple::ArchType machine;
46 const char * const name;
51 // This core information can be looked using the ArchSpec::Core as the index
52 static const CoreDefinition g_core_definitions[] =
54 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_generic , "arm" },
55 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv4 , "armv4" },
56 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv4t , "armv4t" },
57 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5 , "armv5" },
58 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5e , "armv5e" },
59 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5t , "armv5t" },
60 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv6 , "armv6" },
61 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv6m , "armv6m" },
62 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7 , "armv7" },
63 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7f , "armv7f" },
64 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7s , "armv7s" },
65 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7k , "armv7k" },
66 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7m , "armv7m" },
67 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7em , "armv7em" },
68 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_xscale , "xscale" },
69 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumb , "thumb" },
70 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv4t , "thumbv4t" },
71 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv5 , "thumbv5" },
72 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv5e , "thumbv5e" },
73 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv6 , "thumbv6" },
74 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv6m , "thumbv6m" },
75 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7 , "thumbv7" },
76 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7f , "thumbv7f" },
77 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7s , "thumbv7s" },
78 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7k , "thumbv7k" },
79 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7m , "thumbv7m" },
80 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7em , "thumbv7em" },
81 { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_arm64 , "arm64" },
82 { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_armv8 , "armv8" },
83 { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_aarch64 , "aarch64" },
85 { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64 , "mips64" },
87 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_generic , "ppc" },
88 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc601 , "ppc601" },
89 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc602 , "ppc602" },
90 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603 , "ppc603" },
91 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603e , "ppc603e" },
92 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603ev , "ppc603ev" },
93 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc604 , "ppc604" },
94 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc604e , "ppc604e" },
95 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc620 , "ppc620" },
96 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc750 , "ppc750" },
97 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc7400 , "ppc7400" },
98 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc7450 , "ppc7450" },
99 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc970 , "ppc970" },
101 { eByteOrderBig , 8, 4, 4, llvm::Triple::ppc64 , ArchSpec::eCore_ppc64_generic , "ppc64" },
102 { eByteOrderBig , 8, 4, 4, llvm::Triple::ppc64 , ArchSpec::eCore_ppc64_ppc970_64 , "ppc970-64" },
104 { eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc , ArchSpec::eCore_sparc_generic , "sparc" },
105 { eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, ArchSpec::eCore_sparc9_generic , "sparcv9" },
107 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i386 , "i386" },
108 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i486 , "i486" },
109 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i486sx , "i486sx" },
110 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i686 , "i686" },
112 { eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64 , "x86_64" },
113 { eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64h , "x86_64h" },
114 { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_generic, "hexagon" },
115 { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4" },
116 { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5" },
118 { eByteOrderLittle, 4, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach32 , "unknown-mach-32" },
119 { eByteOrderLittle, 8, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach64 , "unknown-mach-64" },
121 { eByteOrderLittle, 4, 1, 1 , llvm::Triple::kalimba , ArchSpec::eCore_kalimba , "kalimba" },
122 { eByteOrderBig , 4, 1, 1 , llvm::Triple::kalimba , ArchSpec::eCore_kalimba3 , "kalimba3" },
123 { eByteOrderLittle, 4, 1, 1 , llvm::Triple::kalimba , ArchSpec::eCore_kalimba4 , "kalimba4" },
124 { eByteOrderLittle, 4, 1, 1 , llvm::Triple::kalimba , ArchSpec::eCore_kalimba5 , "kalimba5" }
127 // Ensure that we have an entry in the g_core_definitions for each core. If you comment out an entry above,
128 // you will need to comment out the corresponding ArchSpec::Core enumeration.
129 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == ArchSpec::kNumCores, "make sure we have one core definition for each core");
132 struct ArchDefinitionEntry
141 struct ArchDefinition
143 ArchitectureType type;
145 const ArchDefinitionEntry *entries;
151 ArchSpec::AutoComplete (const char *name, StringList &matches)
156 for (i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
158 if (NameMatches(g_core_definitions[i].name, eNameMatchStartsWith, name))
159 matches.AppendString (g_core_definitions[i].name);
164 for (i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
165 matches.AppendString (g_core_definitions[i].name);
167 return matches.GetSize();
172 #define CPU_ANY (UINT32_MAX)
174 //===----------------------------------------------------------------------===//
175 // A table that gets searched linearly for matches. This table is used to
176 // convert cpu type and subtypes to architecture names, and to convert
177 // architecture names to cpu types and subtypes. The ordering is important and
178 // allows the precedence to be set when the table is built.
179 #define SUBTYPE_MASK 0x00FFFFFFu
180 static const ArchDefinitionEntry g_macho_arch_entries[] =
182 { ArchSpec::eCore_arm_generic , llvm::MachO::CPU_TYPE_ARM , CPU_ANY, UINT32_MAX , UINT32_MAX },
183 { ArchSpec::eCore_arm_generic , llvm::MachO::CPU_TYPE_ARM , 0 , UINT32_MAX , SUBTYPE_MASK },
184 { ArchSpec::eCore_arm_armv4 , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK },
185 { ArchSpec::eCore_arm_armv4t , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK },
186 { ArchSpec::eCore_arm_armv6 , llvm::MachO::CPU_TYPE_ARM , 6 , UINT32_MAX , SUBTYPE_MASK },
187 { ArchSpec::eCore_arm_armv6m , llvm::MachO::CPU_TYPE_ARM , 14 , UINT32_MAX , SUBTYPE_MASK },
188 { ArchSpec::eCore_arm_armv5 , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
189 { ArchSpec::eCore_arm_armv5e , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
190 { ArchSpec::eCore_arm_armv5t , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
191 { ArchSpec::eCore_arm_xscale , llvm::MachO::CPU_TYPE_ARM , 8 , UINT32_MAX , SUBTYPE_MASK },
192 { ArchSpec::eCore_arm_armv7 , llvm::MachO::CPU_TYPE_ARM , 9 , UINT32_MAX , SUBTYPE_MASK },
193 { ArchSpec::eCore_arm_armv7f , llvm::MachO::CPU_TYPE_ARM , 10 , UINT32_MAX , SUBTYPE_MASK },
194 { ArchSpec::eCore_arm_armv7s , llvm::MachO::CPU_TYPE_ARM , 11 , UINT32_MAX , SUBTYPE_MASK },
195 { ArchSpec::eCore_arm_armv7k , llvm::MachO::CPU_TYPE_ARM , 12 , UINT32_MAX , SUBTYPE_MASK },
196 { ArchSpec::eCore_arm_armv7m , llvm::MachO::CPU_TYPE_ARM , 15 , UINT32_MAX , SUBTYPE_MASK },
197 { ArchSpec::eCore_arm_armv7em , llvm::MachO::CPU_TYPE_ARM , 16 , UINT32_MAX , SUBTYPE_MASK },
198 { ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , CPU_ANY, UINT32_MAX , SUBTYPE_MASK },
199 { ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , 0 , UINT32_MAX , SUBTYPE_MASK },
200 { ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , 1 , UINT32_MAX , SUBTYPE_MASK },
201 { ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , 13 , UINT32_MAX , SUBTYPE_MASK },
202 { ArchSpec::eCore_thumb , llvm::MachO::CPU_TYPE_ARM , 0 , UINT32_MAX , SUBTYPE_MASK },
203 { ArchSpec::eCore_thumbv4t , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK },
204 { ArchSpec::eCore_thumbv5 , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
205 { ArchSpec::eCore_thumbv5e , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
206 { ArchSpec::eCore_thumbv6 , llvm::MachO::CPU_TYPE_ARM , 6 , UINT32_MAX , SUBTYPE_MASK },
207 { ArchSpec::eCore_thumbv6m , llvm::MachO::CPU_TYPE_ARM , 14 , UINT32_MAX , SUBTYPE_MASK },
208 { ArchSpec::eCore_thumbv7 , llvm::MachO::CPU_TYPE_ARM , 9 , UINT32_MAX , SUBTYPE_MASK },
209 { ArchSpec::eCore_thumbv7f , llvm::MachO::CPU_TYPE_ARM , 10 , UINT32_MAX , SUBTYPE_MASK },
210 { ArchSpec::eCore_thumbv7s , llvm::MachO::CPU_TYPE_ARM , 11 , UINT32_MAX , SUBTYPE_MASK },
211 { ArchSpec::eCore_thumbv7k , llvm::MachO::CPU_TYPE_ARM , 12 , UINT32_MAX , SUBTYPE_MASK },
212 { ArchSpec::eCore_thumbv7m , llvm::MachO::CPU_TYPE_ARM , 15 , UINT32_MAX , SUBTYPE_MASK },
213 { ArchSpec::eCore_thumbv7em , llvm::MachO::CPU_TYPE_ARM , 16 , UINT32_MAX , SUBTYPE_MASK },
214 { ArchSpec::eCore_ppc_generic , llvm::MachO::CPU_TYPE_POWERPC , CPU_ANY, UINT32_MAX , UINT32_MAX },
215 { ArchSpec::eCore_ppc_generic , llvm::MachO::CPU_TYPE_POWERPC , 0 , UINT32_MAX , SUBTYPE_MASK },
216 { ArchSpec::eCore_ppc_ppc601 , llvm::MachO::CPU_TYPE_POWERPC , 1 , UINT32_MAX , SUBTYPE_MASK },
217 { ArchSpec::eCore_ppc_ppc602 , llvm::MachO::CPU_TYPE_POWERPC , 2 , UINT32_MAX , SUBTYPE_MASK },
218 { ArchSpec::eCore_ppc_ppc603 , llvm::MachO::CPU_TYPE_POWERPC , 3 , UINT32_MAX , SUBTYPE_MASK },
219 { ArchSpec::eCore_ppc_ppc603e , llvm::MachO::CPU_TYPE_POWERPC , 4 , UINT32_MAX , SUBTYPE_MASK },
220 { ArchSpec::eCore_ppc_ppc603ev , llvm::MachO::CPU_TYPE_POWERPC , 5 , UINT32_MAX , SUBTYPE_MASK },
221 { ArchSpec::eCore_ppc_ppc604 , llvm::MachO::CPU_TYPE_POWERPC , 6 , UINT32_MAX , SUBTYPE_MASK },
222 { ArchSpec::eCore_ppc_ppc604e , llvm::MachO::CPU_TYPE_POWERPC , 7 , UINT32_MAX , SUBTYPE_MASK },
223 { ArchSpec::eCore_ppc_ppc620 , llvm::MachO::CPU_TYPE_POWERPC , 8 , UINT32_MAX , SUBTYPE_MASK },
224 { ArchSpec::eCore_ppc_ppc750 , llvm::MachO::CPU_TYPE_POWERPC , 9 , UINT32_MAX , SUBTYPE_MASK },
225 { ArchSpec::eCore_ppc_ppc7400 , llvm::MachO::CPU_TYPE_POWERPC , 10 , UINT32_MAX , SUBTYPE_MASK },
226 { ArchSpec::eCore_ppc_ppc7450 , llvm::MachO::CPU_TYPE_POWERPC , 11 , UINT32_MAX , SUBTYPE_MASK },
227 { ArchSpec::eCore_ppc_ppc970 , llvm::MachO::CPU_TYPE_POWERPC , 100 , UINT32_MAX , SUBTYPE_MASK },
228 { ArchSpec::eCore_ppc64_generic , llvm::MachO::CPU_TYPE_POWERPC64 , 0 , UINT32_MAX , SUBTYPE_MASK },
229 { ArchSpec::eCore_ppc64_ppc970_64 , llvm::MachO::CPU_TYPE_POWERPC64 , 100 , UINT32_MAX , SUBTYPE_MASK },
230 { ArchSpec::eCore_x86_32_i386 , llvm::MachO::CPU_TYPE_I386 , 3 , UINT32_MAX , SUBTYPE_MASK },
231 { ArchSpec::eCore_x86_32_i486 , llvm::MachO::CPU_TYPE_I386 , 4 , UINT32_MAX , SUBTYPE_MASK },
232 { ArchSpec::eCore_x86_32_i486sx , llvm::MachO::CPU_TYPE_I386 , 0x84 , UINT32_MAX , SUBTYPE_MASK },
233 { ArchSpec::eCore_x86_32_i386 , llvm::MachO::CPU_TYPE_I386 , CPU_ANY, UINT32_MAX , UINT32_MAX },
234 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , 3 , UINT32_MAX , SUBTYPE_MASK },
235 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , 4 , UINT32_MAX , SUBTYPE_MASK },
236 { ArchSpec::eCore_x86_64_x86_64h , llvm::MachO::CPU_TYPE_X86_64 , 8 , UINT32_MAX , SUBTYPE_MASK },
237 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , CPU_ANY, UINT32_MAX , UINT32_MAX },
238 // Catch any unknown mach architectures so we can always use the object and symbol mach-o files
239 { ArchSpec::eCore_uknownMach32 , 0 , 0 , 0xFF000000u, 0x00000000u },
240 { ArchSpec::eCore_uknownMach64 , llvm::MachO::CPU_ARCH_ABI64 , 0 , 0xFF000000u, 0x00000000u }
242 static const ArchDefinition g_macho_arch_def = {
244 llvm::array_lengthof(g_macho_arch_entries),
245 g_macho_arch_entries,
249 //===----------------------------------------------------------------------===//
250 // A table that gets searched linearly for matches. This table is used to
251 // convert cpu type and subtypes to architecture names, and to convert
252 // architecture names to cpu types and subtypes. The ordering is important and
253 // allows the precedence to be set when the table is built.
254 static const ArchDefinitionEntry g_elf_arch_entries[] =
256 { ArchSpec::eCore_sparc_generic , llvm::ELF::EM_SPARC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Sparc
257 { ArchSpec::eCore_x86_32_i386 , llvm::ELF::EM_386 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 80386
258 { ArchSpec::eCore_x86_32_i486 , llvm::ELF::EM_486 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 486 (deprecated)
259 { ArchSpec::eCore_ppc_generic , llvm::ELF::EM_PPC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC
260 { ArchSpec::eCore_ppc64_generic , llvm::ELF::EM_PPC64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC64
261 { ArchSpec::eCore_arm_generic , llvm::ELF::EM_ARM , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM
262 { ArchSpec::eCore_arm_aarch64 , llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM64
263 { ArchSpec::eCore_sparc9_generic , llvm::ELF::EM_SPARCV9, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // SPARC V9
264 { ArchSpec::eCore_x86_64_x86_64 , llvm::ELF::EM_X86_64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // AMD64
265 { ArchSpec::eCore_mips64 , llvm::ELF::EM_MIPS , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // MIPS
266 { ArchSpec::eCore_hexagon_generic , llvm::ELF::EM_HEXAGON, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // HEXAGON
267 { ArchSpec::eCore_kalimba , llvm::ELF::EM_CSR_KALIMBA, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // KALIMBA
268 { ArchSpec::eCore_kalimba3 , llvm::ELF::EM_CSR_KALIMBA, 3, 0xFFFFFFFFu, 0xFFFFFFFFu }, // KALIMBA
269 { ArchSpec::eCore_kalimba4 , llvm::ELF::EM_CSR_KALIMBA, 4, 0xFFFFFFFFu, 0xFFFFFFFFu }, // KALIMBA
270 { ArchSpec::eCore_kalimba5 , llvm::ELF::EM_CSR_KALIMBA, 5, 0xFFFFFFFFu, 0xFFFFFFFFu } // KALIMBA
274 static const ArchDefinition g_elf_arch_def = {
276 llvm::array_lengthof(g_elf_arch_entries),
281 static const ArchDefinitionEntry g_coff_arch_entries[] =
283 { ArchSpec::eCore_x86_32_i386 , llvm::COFF::IMAGE_FILE_MACHINE_I386 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 80x86
284 { ArchSpec::eCore_ppc_generic , llvm::COFF::IMAGE_FILE_MACHINE_POWERPC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC
285 { ArchSpec::eCore_ppc_generic , llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC (with FPU)
286 { ArchSpec::eCore_arm_generic , llvm::COFF::IMAGE_FILE_MACHINE_ARM , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM
287 { ArchSpec::eCore_arm_armv7 , llvm::COFF::IMAGE_FILE_MACHINE_ARMNT , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARMv7
288 { ArchSpec::eCore_thumb , llvm::COFF::IMAGE_FILE_MACHINE_THUMB , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARMv7
289 { ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu } // AMD64
292 static const ArchDefinition g_coff_arch_def = {
294 llvm::array_lengthof(g_coff_arch_entries),
299 //===----------------------------------------------------------------------===//
300 // Table of all ArchDefinitions
301 static const ArchDefinition *g_arch_definitions[] = {
307 static const size_t k_num_arch_definitions = llvm::array_lengthof(g_arch_definitions);
309 //===----------------------------------------------------------------------===//
310 // Static helper functions.
313 // Get the architecture definition for a given object type.
314 static const ArchDefinition *
315 FindArchDefinition (ArchitectureType arch_type)
317 for (unsigned int i = 0; i < k_num_arch_definitions; ++i)
319 const ArchDefinition *def = g_arch_definitions[i];
320 if (def->type == arch_type)
326 // Get an architecture definition by name.
327 static const CoreDefinition *
328 FindCoreDefinition (llvm::StringRef name)
330 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
332 if (name.equals_lower(g_core_definitions[i].name))
333 return &g_core_definitions[i];
338 static inline const CoreDefinition *
339 FindCoreDefinition (ArchSpec::Core core)
341 if (core >= 0 && core < llvm::array_lengthof(g_core_definitions))
342 return &g_core_definitions[core];
346 // Get a definition entry by cpu type and subtype.
347 static const ArchDefinitionEntry *
348 FindArchDefinitionEntry (const ArchDefinition *def, uint32_t cpu, uint32_t sub)
353 const ArchDefinitionEntry *entries = def->entries;
354 for (size_t i = 0; i < def->num_entries; ++i)
356 if (entries[i].cpu == (cpu & entries[i].cpu_mask))
357 if (entries[i].sub == (sub & entries[i].sub_mask))
363 static const ArchDefinitionEntry *
364 FindArchDefinitionEntry (const ArchDefinition *def, ArchSpec::Core core)
369 const ArchDefinitionEntry *entries = def->entries;
370 for (size_t i = 0; i < def->num_entries; ++i)
372 if (entries[i].core == core)
378 //===----------------------------------------------------------------------===//
379 // Constructors and destructors.
381 ArchSpec::ArchSpec() :
383 m_core (kCore_invalid),
384 m_byte_order (eByteOrderInvalid),
389 ArchSpec::ArchSpec (const char *triple_cstr, Platform *platform) :
391 m_core (kCore_invalid),
392 m_byte_order (eByteOrderInvalid),
396 SetTriple(triple_cstr, platform);
400 ArchSpec::ArchSpec (const char *triple_cstr) :
402 m_core (kCore_invalid),
403 m_byte_order (eByteOrderInvalid),
407 SetTriple(triple_cstr);
410 ArchSpec::ArchSpec(const llvm::Triple &triple) :
412 m_core (kCore_invalid),
413 m_byte_order (eByteOrderInvalid),
419 ArchSpec::ArchSpec (ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) :
421 m_core (kCore_invalid),
422 m_byte_order (eByteOrderInvalid),
425 SetArchitecture (arch_type, cpu, subtype);
428 ArchSpec::~ArchSpec()
432 //===----------------------------------------------------------------------===//
433 // Assignment and initialization.
436 ArchSpec::operator= (const ArchSpec& rhs)
440 m_triple = rhs.m_triple;
442 m_byte_order = rhs.m_byte_order;
443 m_distribution_id = rhs.m_distribution_id;
451 m_triple = llvm::Triple();
452 m_core = kCore_invalid;
453 m_byte_order = eByteOrderInvalid;
454 m_distribution_id.Clear ();
457 //===----------------------------------------------------------------------===//
462 ArchSpec::GetArchitectureName () const
464 const CoreDefinition *core_def = FindCoreDefinition (m_core);
466 return core_def->name;
471 ArchSpec::GetMachOCPUType () const
473 const CoreDefinition *core_def = FindCoreDefinition (m_core);
476 const ArchDefinitionEntry *arch_def = FindArchDefinitionEntry (&g_macho_arch_def, core_def->core);
479 return arch_def->cpu;
482 return LLDB_INVALID_CPUTYPE;
486 ArchSpec::GetMachOCPUSubType () const
488 const CoreDefinition *core_def = FindCoreDefinition (m_core);
491 const ArchDefinitionEntry *arch_def = FindArchDefinitionEntry (&g_macho_arch_def, core_def->core);
494 return arch_def->sub;
497 return LLDB_INVALID_CPUTYPE;
501 ArchSpec::GetDataByteSize () const
518 ArchSpec::GetCodeByteSize () const
534 llvm::Triple::ArchType
535 ArchSpec::GetMachine () const
537 const CoreDefinition *core_def = FindCoreDefinition (m_core);
539 return core_def->machine;
541 return llvm::Triple::UnknownArch;
545 ArchSpec::GetDistributionId () const
547 return m_distribution_id;
551 ArchSpec::SetDistributionId (const char* distribution_id)
553 m_distribution_id.SetCString (distribution_id);
557 ArchSpec::GetAddressByteSize() const
559 const CoreDefinition *core_def = FindCoreDefinition (m_core);
561 return core_def->addr_byte_size;
566 ArchSpec::GetDefaultEndian () const
568 const CoreDefinition *core_def = FindCoreDefinition (m_core);
570 return core_def->default_byte_order;
571 return eByteOrderInvalid;
575 ArchSpec::GetByteOrder () const
577 if (m_byte_order == eByteOrderInvalid)
578 return GetDefaultEndian();
582 //===----------------------------------------------------------------------===//
586 ArchSpec::SetTriple (const llvm::Triple &triple)
590 llvm::StringRef arch_name (m_triple.getArchName());
591 const CoreDefinition *core_def = FindCoreDefinition (arch_name);
594 m_core = core_def->core;
595 // Set the byte order to the default byte order for an architecture.
596 // This can be modified if needed for cases when cores handle both
597 // big and little endian
598 m_byte_order = core_def->default_byte_order;
610 ParseMachCPUDashSubtypeTriple (const char *triple_cstr, ArchSpec &arch)
612 // Accept "12-10" or "12.10" as cpu type/subtype
613 if (isdigit(triple_cstr[0]))
617 uint32_t cpu = (uint32_t)::strtoul (triple_cstr, &end, 0);
618 if (errno == 0 && cpu != 0 && end && ((*end == '-') || (*end == '.')))
621 uint32_t sub = (uint32_t)::strtoul (end + 1, &end, 0);
622 if (errno == 0 && end && ((*end == '-') || (*end == '.') || (*end == '\0')))
624 if (arch.SetArchitecture (eArchTypeMachO, cpu, sub))
628 llvm::StringRef vendor_os (end + 1);
629 size_t dash_pos = vendor_os.find('-');
630 if (dash_pos != llvm::StringRef::npos)
632 llvm::StringRef vendor_str(vendor_os.substr(0, dash_pos));
633 arch.GetTriple().setVendorName(vendor_str);
634 const size_t vendor_start_pos = dash_pos+1;
635 dash_pos = vendor_os.find('-', vendor_start_pos);
636 if (dash_pos == llvm::StringRef::npos)
638 if (vendor_start_pos < vendor_os.size())
639 arch.GetTriple().setOSName(vendor_os.substr(vendor_start_pos));
643 arch.GetTriple().setOSName(vendor_os.substr(vendor_start_pos, dash_pos - vendor_start_pos));
655 ArchSpec::SetTriple (const char *triple_cstr)
657 if (triple_cstr && triple_cstr[0])
659 if (ParseMachCPUDashSubtypeTriple (triple_cstr, *this))
662 llvm::StringRef triple_stref (triple_cstr);
663 if (triple_stref.startswith (LLDB_ARCH_DEFAULT))
665 // Special case for the current host default architectures...
666 if (triple_stref.equals (LLDB_ARCH_DEFAULT_32BIT))
667 *this = HostInfo::GetArchitecture(HostInfo::eArchKind32);
668 else if (triple_stref.equals (LLDB_ARCH_DEFAULT_64BIT))
669 *this = HostInfo::GetArchitecture(HostInfo::eArchKind64);
670 else if (triple_stref.equals (LLDB_ARCH_DEFAULT))
671 *this = HostInfo::GetArchitecture(HostInfo::eArchKindDefault);
675 std::string normalized_triple_sstr (llvm::Triple::normalize(triple_stref));
676 triple_stref = normalized_triple_sstr;
677 SetTriple (llvm::Triple (triple_stref));
686 ArchSpec::SetTriple (const char *triple_cstr, Platform *platform)
688 if (triple_cstr && triple_cstr[0])
690 if (ParseMachCPUDashSubtypeTriple (triple_cstr, *this))
693 llvm::StringRef triple_stref (triple_cstr);
694 if (triple_stref.startswith (LLDB_ARCH_DEFAULT))
696 // Special case for the current host default architectures...
697 if (triple_stref.equals (LLDB_ARCH_DEFAULT_32BIT))
698 *this = HostInfo::GetArchitecture(HostInfo::eArchKind32);
699 else if (triple_stref.equals (LLDB_ARCH_DEFAULT_64BIT))
700 *this = HostInfo::GetArchitecture(HostInfo::eArchKind64);
701 else if (triple_stref.equals (LLDB_ARCH_DEFAULT))
702 *this = HostInfo::GetArchitecture(HostInfo::eArchKindDefault);
706 ArchSpec raw_arch (triple_cstr);
708 std::string normalized_triple_sstr (llvm::Triple::normalize(triple_stref));
709 triple_stref = normalized_triple_sstr;
710 llvm::Triple normalized_triple (triple_stref);
712 const bool os_specified = normalized_triple.getOSName().size() > 0;
713 const bool vendor_specified = normalized_triple.getVendorName().size() > 0;
714 const bool env_specified = normalized_triple.getEnvironmentName().size() > 0;
716 // If we got an arch only, then default the vendor, os, environment
717 // to match the platform if one is supplied
718 if (!(os_specified || vendor_specified || env_specified))
722 // If we were given a platform, use the platform's system
723 // architecture. If this is not available (might not be
724 // connected) use the first supported architecture.
725 ArchSpec compatible_arch;
726 if (platform->IsCompatibleArchitecture (raw_arch, false, &compatible_arch))
728 if (compatible_arch.IsValid())
730 const llvm::Triple &compatible_triple = compatible_arch.GetTriple();
731 if (!vendor_specified)
732 normalized_triple.setVendor(compatible_triple.getVendor());
734 normalized_triple.setOS(compatible_triple.getOS());
735 if (!env_specified && compatible_triple.getEnvironmentName().size())
736 normalized_triple.setEnvironment(compatible_triple.getEnvironment());
747 // No platform specified, fall back to the host system for
748 // the default vendor, os, and environment.
749 llvm::Triple host_triple(llvm::sys::getDefaultTargetTriple());
750 if (!vendor_specified)
751 normalized_triple.setVendor(host_triple.getVendor());
752 if (!vendor_specified)
753 normalized_triple.setOS(host_triple.getOS());
754 if (!env_specified && host_triple.getEnvironmentName().size())
755 normalized_triple.setEnvironment(host_triple.getEnvironment());
758 SetTriple (normalized_triple);
767 ArchSpec::SetArchitecture (ArchitectureType arch_type, uint32_t cpu, uint32_t sub)
769 m_core = kCore_invalid;
770 bool update_triple = true;
771 const ArchDefinition *arch_def = FindArchDefinition(arch_type);
774 const ArchDefinitionEntry *arch_def_entry = FindArchDefinitionEntry (arch_def, cpu, sub);
777 const CoreDefinition *core_def = FindCoreDefinition (arch_def_entry->core);
780 m_core = core_def->core;
781 update_triple = false;
782 // Always use the architecture name because it might be more descriptive
783 // than the architecture enum ("armv7" -> llvm::Triple::arm).
784 m_triple.setArchName(llvm::StringRef(core_def->name));
785 if (arch_type == eArchTypeMachO)
787 m_triple.setVendor (llvm::Triple::Apple);
789 switch (core_def->machine)
791 case llvm::Triple::aarch64:
792 case llvm::Triple::arm:
793 case llvm::Triple::thumb:
794 m_triple.setOS (llvm::Triple::IOS);
797 case llvm::Triple::x86:
798 case llvm::Triple::x86_64:
799 // Don't set the OS for x86_64 or for x86 as we want to leave it as an "unspecified unknown"
800 // which means if we ask for the OS from the llvm::Triple we get back llvm::Triple::UnknownOS, but
801 // if we ask for the string value for the OS it will come back empty (unspecified).
802 // We do this because we now have iOS and MacOSX as the OS values for x86 and x86_64 for
803 // normal desktop and simulator binaries. And if we compare a "x86_64-apple-ios" to a "x86_64-apple-"
804 // triple, it will say it is compatible (because the OS is unspecified in the second one and will match
805 // anything in the first
809 m_triple.setOS (llvm::Triple::MacOSX);
815 m_triple.setVendor (llvm::Triple::UnknownVendor);
816 m_triple.setOS (llvm::Triple::UnknownOS);
818 // Fall back onto setting the machine type if the arch by name failed...
819 if (m_triple.getArch () == llvm::Triple::UnknownArch)
820 m_triple.setArch (core_def->machine);
824 CoreUpdated(update_triple);
829 ArchSpec::GetMinimumOpcodeByteSize() const
831 const CoreDefinition *core_def = FindCoreDefinition (m_core);
833 return core_def->min_opcode_byte_size;
838 ArchSpec::GetMaximumOpcodeByteSize() const
840 const CoreDefinition *core_def = FindCoreDefinition (m_core);
842 return core_def->max_opcode_byte_size;
847 ArchSpec::IsExactMatch (const ArchSpec& rhs) const
849 return IsEqualTo (rhs, true);
853 ArchSpec::IsCompatibleMatch (const ArchSpec& rhs) const
855 return IsEqualTo (rhs, false);
859 ArchSpec::IsEqualTo (const ArchSpec& rhs, bool exact_match) const
861 // explicitly ignoring m_distribution_id in this method.
863 if (GetByteOrder() != rhs.GetByteOrder())
866 const ArchSpec::Core lhs_core = GetCore ();
867 const ArchSpec::Core rhs_core = rhs.GetCore ();
869 const bool core_match = cores_match (lhs_core, rhs_core, true, exact_match);
873 const llvm::Triple &lhs_triple = GetTriple();
874 const llvm::Triple &rhs_triple = rhs.GetTriple();
876 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor();
877 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor();
878 if (lhs_triple_vendor != rhs_triple_vendor)
882 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified();
883 const bool lhs_vendor_specified = TripleVendorWasSpecified();
884 // Both architectures had the vendor specified, so if they aren't
885 // equal then we return false
886 if (rhs_vendor_specified && lhs_vendor_specified)
890 // Only fail if both vendor types are not unknown
891 if (lhs_triple_vendor != llvm::Triple::UnknownVendor &&
892 rhs_triple_vendor != llvm::Triple::UnknownVendor)
896 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS();
897 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS();
898 if (lhs_triple_os != rhs_triple_os)
902 const bool rhs_os_specified = rhs.TripleOSWasSpecified();
903 const bool lhs_os_specified = TripleOSWasSpecified();
904 // Both architectures had the OS specified, so if they aren't
905 // equal then we return false
906 if (rhs_os_specified && lhs_os_specified)
910 // Only fail if both os types are not unknown
911 if (lhs_triple_os != llvm::Triple::UnknownOS &&
912 rhs_triple_os != llvm::Triple::UnknownOS)
916 const llvm::Triple::EnvironmentType lhs_triple_env = lhs_triple.getEnvironment();
917 const llvm::Triple::EnvironmentType rhs_triple_env = rhs_triple.getEnvironment();
919 if (lhs_triple_env != rhs_triple_env)
921 // Only fail if both environment types are not unknown
922 if (lhs_triple_env != llvm::Triple::UnknownEnvironment &&
923 rhs_triple_env != llvm::Triple::UnknownEnvironment)
931 //===----------------------------------------------------------------------===//
935 ArchSpec::CoreUpdated (bool update_triple)
937 const CoreDefinition *core_def = FindCoreDefinition (m_core);
941 m_triple = llvm::Triple(core_def->name, "unknown", "unknown");
942 m_byte_order = core_def->default_byte_order;
947 m_triple = llvm::Triple();
948 m_byte_order = eByteOrderInvalid;
952 //===----------------------------------------------------------------------===//
956 cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match)
963 case ArchSpec::kCore_any:
966 case ArchSpec::eCore_arm_generic:
967 if (enforce_exact_match)
969 // Fall through to case below
970 case ArchSpec::kCore_arm_any:
971 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last)
973 if (core2 >= ArchSpec::kCore_thumb_first && core2 <= ArchSpec::kCore_thumb_last)
975 if (core2 == ArchSpec::kCore_arm_any)
979 case ArchSpec::kCore_x86_32_any:
980 if ((core2 >= ArchSpec::kCore_x86_32_first && core2 <= ArchSpec::kCore_x86_32_last) || (core2 == ArchSpec::kCore_x86_32_any))
984 case ArchSpec::kCore_x86_64_any:
985 if ((core2 >= ArchSpec::kCore_x86_64_first && core2 <= ArchSpec::kCore_x86_64_last) || (core2 == ArchSpec::kCore_x86_64_any))
989 case ArchSpec::kCore_ppc_any:
990 if ((core2 >= ArchSpec::kCore_ppc_first && core2 <= ArchSpec::kCore_ppc_last) || (core2 == ArchSpec::kCore_ppc_any))
994 case ArchSpec::kCore_ppc64_any:
995 if ((core2 >= ArchSpec::kCore_ppc64_first && core2 <= ArchSpec::kCore_ppc64_last) || (core2 == ArchSpec::kCore_ppc64_any))
999 case ArchSpec::eCore_arm_armv6m:
1000 if (!enforce_exact_match)
1002 if (core2 == ArchSpec::eCore_arm_generic)
1004 try_inverse = false;
1005 if (core2 == ArchSpec::eCore_arm_armv7)
1010 case ArchSpec::kCore_hexagon_any:
1011 if ((core2 >= ArchSpec::kCore_hexagon_first && core2 <= ArchSpec::kCore_hexagon_last) || (core2 == ArchSpec::kCore_hexagon_any))
1015 case ArchSpec::eCore_arm_armv7m:
1016 case ArchSpec::eCore_arm_armv7em:
1017 case ArchSpec::eCore_arm_armv7f:
1018 case ArchSpec::eCore_arm_armv7k:
1019 case ArchSpec::eCore_arm_armv7s:
1020 if (!enforce_exact_match)
1022 if (core2 == ArchSpec::eCore_arm_generic)
1024 if (core2 == ArchSpec::eCore_arm_armv7)
1026 try_inverse = false;
1030 case ArchSpec::eCore_x86_64_x86_64h:
1031 if (!enforce_exact_match)
1033 try_inverse = false;
1034 if (core2 == ArchSpec::eCore_x86_64_x86_64)
1039 case ArchSpec::eCore_kalimba:
1040 case ArchSpec::eCore_kalimba3:
1041 case ArchSpec::eCore_kalimba4:
1042 case ArchSpec::eCore_kalimba5:
1043 if (core2 >= ArchSpec::kCore_kalimba_first && core2 <= ArchSpec::kCore_kalimba_last)
1049 case ArchSpec::eCore_arm_armv8:
1050 if (!enforce_exact_match)
1052 if (core2 == ArchSpec::eCore_arm_arm64)
1054 if (core2 == ArchSpec::eCore_arm_aarch64)
1056 try_inverse = false;
1060 case ArchSpec::eCore_arm_aarch64:
1061 if (!enforce_exact_match)
1063 if (core2 == ArchSpec::eCore_arm_arm64)
1065 if (core2 == ArchSpec::eCore_arm_armv8)
1067 try_inverse = false;
1071 case ArchSpec::eCore_arm_arm64:
1072 if (!enforce_exact_match)
1074 if (core2 == ArchSpec::eCore_arm_aarch64)
1076 if (core2 == ArchSpec::eCore_arm_armv8)
1078 try_inverse = false;
1086 return cores_match (core2, core1, false, enforce_exact_match);
1091 lldb_private::operator<(const ArchSpec& lhs, const ArchSpec& rhs)
1093 const ArchSpec::Core lhs_core = lhs.GetCore ();
1094 const ArchSpec::Core rhs_core = rhs.GetCore ();
1095 return lhs_core < rhs_core;