1 //===-- ArchitectureArm.cpp -------------------------------------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 #include "Plugins/Architecture/Arm/ArchitectureArm.h"
10 #include "Plugins/Process/Utility/ARMDefines.h"
11 #include "Plugins/Process/Utility/InstructionUtils.h"
12 #include "lldb/Core/PluginManager.h"
13 #include "lldb/Target/RegisterContext.h"
14 #include "lldb/Target/Thread.h"
15 #include "lldb/Utility/ArchSpec.h"
17 using namespace lldb_private;
20 ConstString ArchitectureArm::GetPluginNameStatic() {
21 return ConstString("arm");
24 void ArchitectureArm::Initialize() {
25 PluginManager::RegisterPlugin(GetPluginNameStatic(),
26 "Arm-specific algorithms",
27 &ArchitectureArm::Create);
30 void ArchitectureArm::Terminate() {
31 PluginManager::UnregisterPlugin(&ArchitectureArm::Create);
34 std::unique_ptr<Architecture> ArchitectureArm::Create(const ArchSpec &arch) {
35 if (arch.GetMachine() != llvm::Triple::arm)
37 return std::unique_ptr<Architecture>(new ArchitectureArm());
40 ConstString ArchitectureArm::GetPluginName() { return GetPluginNameStatic(); }
41 uint32_t ArchitectureArm::GetPluginVersion() { return 1; }
43 void ArchitectureArm::OverrideStopInfo(Thread &thread) const {
44 // We need to check if we are stopped in Thumb mode in a IT instruction and
45 // detect if the condition doesn't pass. If this is the case it means we
46 // won't actually execute this instruction. If this happens we need to clear
47 // the stop reason to no thread plans think we are stopped for a reason and
48 // the plans should keep going.
50 // We do this because when single stepping many ARM processes, debuggers
51 // often use the BVR/BCR registers that says "stop when the PC is not equal
52 // to its current value". This method of stepping means we can end up
53 // stopping on instructions inside an if/then block that wouldn't get
54 // executed. By fixing this we can stop the debugger from seeming like you
55 // stepped through both the "if" _and_ the "else" clause when source level
56 // stepping because the debugger stops regardless due to the BVR/BCR
59 // It also means we can set breakpoints on instructions inside an an if/then
60 // block and correctly skip them if we use the BKPT instruction. The ARM and
61 // Thumb BKPT instructions are unconditional even when executed in a Thumb IT
64 // If your debugger inserts software traps in ARM/Thumb code, it will need to
65 // use 16 and 32 bit instruction for 16 and 32 bit thumb instructions
66 // respectively. If your debugger inserts a 16 bit thumb trap on top of a 32
67 // bit thumb instruction for an opcode that is inside an if/then, it will
68 // change the it/then to conditionally execute your
69 // 16 bit trap and then cause your program to crash if it executes the
70 // trailing 16 bits (the second half of the 32 bit thumb instruction you
71 // partially overwrote).
73 RegisterContextSP reg_ctx_sp(thread.GetRegisterContext());
77 const uint32_t cpsr = reg_ctx_sp->GetFlags(0);
81 // Read the J and T bits to get the ISETSTATE
82 const uint32_t J = Bit32(cpsr, 24);
83 const uint32_t T = Bit32(cpsr, 5);
84 const uint32_t ISETSTATE = J << 1 | T;
86 // NOTE: I am pretty sure we want to enable the code below
87 // that detects when we stop on an instruction in ARM mode that is conditional
88 // and the condition doesn't pass. This can happen if you set a breakpoint on
89 // an instruction that is conditional. We currently will _always_ stop on the
90 // instruction which is bad. You can also run into this while single stepping
91 // and you could appear to run code in the "if" and in the "else" clause
92 // because it would stop at all of the conditional instructions in both. In
93 // such cases, we really don't want to stop at this location.
94 // I will check with the lldb-dev list first before I enable this.
96 // ARM mode: check for condition on instruction
97 const addr_t pc = reg_ctx_sp->GetPC();
99 // If we fail to read the opcode we will get UINT64_MAX as the result in
100 // "opcode" which we can use to detect if we read a valid opcode.
101 const uint64_t opcode = thread.GetProcess()->ReadUnsignedIntegerFromMemory(pc, 4, UINT64_MAX, error);
102 if (opcode <= UINT32_MAX)
104 const uint32_t condition = Bits32((uint32_t)opcode, 31, 28);
105 if (!ARMConditionPassed(condition, cpsr))
107 // We ARE stopped on an ARM instruction whose condition doesn't
108 // pass so this instruction won't get executed. Regardless of why
109 // it stopped, we need to clear the stop info
110 thread.SetStopInfo (StopInfoSP());
114 } else if (ISETSTATE == 1) {
116 const uint32_t ITSTATE = Bits32(cpsr, 15, 10) << 2 | Bits32(cpsr, 26, 25);
118 const uint32_t condition = Bits32(ITSTATE, 7, 4);
119 if (!ARMConditionPassed(condition, cpsr)) {
120 // We ARE stopped in a Thumb IT instruction on an instruction whose
121 // condition doesn't pass so this instruction won't get executed.
122 // Regardless of why it stopped, we need to clear the stop info
123 thread.SetStopInfo(StopInfoSP());
129 addr_t ArchitectureArm::GetCallableLoadAddress(addr_t code_addr,
130 AddressClass addr_class) const {
131 bool is_alternate_isa = false;
133 switch (addr_class) {
134 case AddressClass::eData:
135 case AddressClass::eDebug:
136 return LLDB_INVALID_ADDRESS;
137 case AddressClass::eCodeAlternateISA:
138 is_alternate_isa = true;
143 if ((code_addr & 2u) || is_alternate_isa)
144 return code_addr | 1u;
148 addr_t ArchitectureArm::GetOpcodeLoadAddress(addr_t opcode_addr,
149 AddressClass addr_class) const {
150 switch (addr_class) {
151 case AddressClass::eData:
152 case AddressClass::eDebug:
153 return LLDB_INVALID_ADDRESS;
156 return opcode_addr & ~(1ull);