1 //===-- ArchitectureArm.cpp -------------------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "Plugins/Architecture/Arm/ArchitectureArm.h"
11 #include "Plugins/Process/Utility/ARMDefines.h"
12 #include "Plugins/Process/Utility/InstructionUtils.h"
13 #include "lldb/Core/PluginManager.h"
14 #include "lldb/Target/RegisterContext.h"
15 #include "lldb/Target/Thread.h"
16 #include "lldb/Utility/ArchSpec.h"
18 using namespace lldb_private;
21 ConstString ArchitectureArm::GetPluginNameStatic() {
22 return ConstString("arm");
25 void ArchitectureArm::Initialize() {
26 PluginManager::RegisterPlugin(GetPluginNameStatic(),
27 "Arm-specific algorithms",
28 &ArchitectureArm::Create);
31 void ArchitectureArm::Terminate() {
32 PluginManager::UnregisterPlugin(&ArchitectureArm::Create);
35 std::unique_ptr<Architecture> ArchitectureArm::Create(const ArchSpec &arch) {
36 if (arch.GetMachine() != llvm::Triple::arm)
38 return std::unique_ptr<Architecture>(new ArchitectureArm());
41 ConstString ArchitectureArm::GetPluginName() { return GetPluginNameStatic(); }
42 uint32_t ArchitectureArm::GetPluginVersion() { return 1; }
44 void ArchitectureArm::OverrideStopInfo(Thread &thread) const {
45 // We need to check if we are stopped in Thumb mode in a IT instruction and
46 // detect if the condition doesn't pass. If this is the case it means we
47 // won't actually execute this instruction. If this happens we need to clear
48 // the stop reason to no thread plans think we are stopped for a reason and
49 // the plans should keep going.
51 // We do this because when single stepping many ARM processes, debuggers
52 // often use the BVR/BCR registers that says "stop when the PC is not equal
53 // to its current value". This method of stepping means we can end up
54 // stopping on instructions inside an if/then block that wouldn't get
55 // executed. By fixing this we can stop the debugger from seeming like you
56 // stepped through both the "if" _and_ the "else" clause when source level
57 // stepping because the debugger stops regardless due to the BVR/BCR
60 // It also means we can set breakpoints on instructions inside an an if/then
61 // block and correctly skip them if we use the BKPT instruction. The ARM and
62 // Thumb BKPT instructions are unconditional even when executed in a Thumb IT
65 // If your debugger inserts software traps in ARM/Thumb code, it will need to
66 // use 16 and 32 bit instruction for 16 and 32 bit thumb instructions
67 // respectively. If your debugger inserts a 16 bit thumb trap on top of a 32
68 // bit thumb instruction for an opcode that is inside an if/then, it will
69 // change the it/then to conditionally execute your
70 // 16 bit trap and then cause your program to crash if it executes the
71 // trailing 16 bits (the second half of the 32 bit thumb instruction you
72 // partially overwrote).
74 RegisterContextSP reg_ctx_sp(thread.GetRegisterContext());
78 const uint32_t cpsr = reg_ctx_sp->GetFlags(0);
82 // Read the J and T bits to get the ISETSTATE
83 const uint32_t J = Bit32(cpsr, 24);
84 const uint32_t T = Bit32(cpsr, 5);
85 const uint32_t ISETSTATE = J << 1 | T;
87 // NOTE: I am pretty sure we want to enable the code below
88 // that detects when we stop on an instruction in ARM mode that is conditional
89 // and the condition doesn't pass. This can happen if you set a breakpoint on
90 // an instruction that is conditional. We currently will _always_ stop on the
91 // instruction which is bad. You can also run into this while single stepping
92 // and you could appear to run code in the "if" and in the "else" clause
93 // because it would stop at all of the conditional instructions in both. In
94 // such cases, we really don't want to stop at this location.
95 // I will check with the lldb-dev list first before I enable this.
97 // ARM mode: check for condition on instruction
98 const addr_t pc = reg_ctx_sp->GetPC();
100 // If we fail to read the opcode we will get UINT64_MAX as the result in
101 // "opcode" which we can use to detect if we read a valid opcode.
102 const uint64_t opcode = thread.GetProcess()->ReadUnsignedIntegerFromMemory(pc, 4, UINT64_MAX, error);
103 if (opcode <= UINT32_MAX)
105 const uint32_t condition = Bits32((uint32_t)opcode, 31, 28);
106 if (!ARMConditionPassed(condition, cpsr))
108 // We ARE stopped on an ARM instruction whose condition doesn't
109 // pass so this instruction won't get executed. Regardless of why
110 // it stopped, we need to clear the stop info
111 thread.SetStopInfo (StopInfoSP());
115 } else if (ISETSTATE == 1) {
117 const uint32_t ITSTATE = Bits32(cpsr, 15, 10) << 2 | Bits32(cpsr, 26, 25);
119 const uint32_t condition = Bits32(ITSTATE, 7, 4);
120 if (!ARMConditionPassed(condition, cpsr)) {
121 // We ARE stopped in a Thumb IT instruction on an instruction whose
122 // condition doesn't pass so this instruction won't get executed.
123 // Regardless of why it stopped, we need to clear the stop info
124 thread.SetStopInfo(StopInfoSP());
130 addr_t ArchitectureArm::GetCallableLoadAddress(addr_t code_addr,
131 AddressClass addr_class) const {
132 bool is_alternate_isa = false;
134 switch (addr_class) {
135 case AddressClass::eData:
136 case AddressClass::eDebug:
137 return LLDB_INVALID_ADDRESS;
138 case AddressClass::eCodeAlternateISA:
139 is_alternate_isa = true;
144 if ((code_addr & 2u) || is_alternate_isa)
145 return code_addr | 1u;
149 addr_t ArchitectureArm::GetOpcodeLoadAddress(addr_t opcode_addr,
150 AddressClass addr_class) const {
151 switch (addr_class) {
152 case AddressClass::eData:
153 case AddressClass::eDebug:
154 return LLDB_INVALID_ADDRESS;
157 return opcode_addr & ~(1ull);