contrib/llvm/tools/lldb/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp

   1 //===-- EmulateInstructionARM64.cpp ------------------------------*- C++-*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #include "EmulateInstructionARM64.h"
  11
  12 #include <stdlib.h>
  13
  14 #include "lldb/Core/Address.h"
  15 #include "lldb/Core/PluginManager.h"
  16 #include "lldb/Core/RegisterValue.h"
  17 #include "lldb/Symbol/UnwindPlan.h"
  18 #include "lldb/Utility/ArchSpec.h"
  19 #include "lldb/Utility/ConstString.h"
  20 #include "lldb/Utility/Stream.h"
  21
  22 #include "Plugins/Process/Utility/ARMDefines.h"
  23 #include "Plugins/Process/Utility/ARMUtils.h"
  24 #include "Plugins/Process/Utility/lldb-arm64-register-enums.h"
  25
  26 #define GPR_OFFSET(idx) ((idx)*8)
  27 #define GPR_OFFSET_NAME(reg) 0
  28 #define FPU_OFFSET(idx) ((idx)*16)
  29 #define FPU_OFFSET_NAME(reg) 0
  30 #define EXC_OFFSET_NAME(reg) 0
  31 #define DBG_OFFSET_NAME(reg) 0
  32 #define DBG_OFFSET_NAME(reg) 0
  33 #define DEFINE_DBG(re, y)                                                      \
  34   "na", nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex,                  \
  35       {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,          \
  36        LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},                              \
  37       nullptr, nullptr, nullptr, 0
  38
  39 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT
  40
  41 #include "Plugins/Process/Utility/RegisterInfos_arm64.h"
  42
  43 #include "llvm/ADT/STLExtras.h"
  44 #include "llvm/Support/MathExtras.h" // for SignExtend32 template function
  45                                      // and CountTrailingZeros_32 function
  46
  47 #include "Plugins/Process/Utility/InstructionUtils.h"
  48
  49 using namespace lldb;
  50 using namespace lldb_private;
  51
  52 static bool LLDBTableGetRegisterInfo(uint32_t reg_num, RegisterInfo &reg_info) {
  53   if (reg_num >= llvm::array_lengthof(g_register_infos_arm64_le))
  54     return false;
  55   reg_info = g_register_infos_arm64_le[reg_num];
  56   return true;
  57 }
  58
  59 #define No_VFP 0
  60 #define VFPv1 (1u << 1)
  61 #define VFPv2 (1u << 2)
  62 #define VFPv3 (1u << 3)
  63 #define AdvancedSIMD (1u << 4)
  64
  65 #define VFPv1_ABOVE (VFPv1 | VFPv2 | VFPv3 | AdvancedSIMD)
  66 #define VFPv2_ABOVE (VFPv2 | VFPv3 | AdvancedSIMD)
  67 #define VFPv2v3 (VFPv2 | VFPv3)
  68
  69 #define UInt(x) ((uint64_t)x)
  70 #define SInt(x) ((int64_t)x)
  71 #define bit bool
  72 #define boolean bool
  73 #define integer int64_t
  74
  75 static inline bool IsZero(uint64_t x) { return x == 0; }
  76
  77 static inline uint64_t NOT(uint64_t x) { return ~x; }
  78
  79 // LSL()
  80 // =====
  81
  82 static inline uint64_t LSL(uint64_t x, integer shift) {
  83   if (shift == 0)
  84     return x;
  85   return x << shift;
  86 }
  87
  88 // AddWithCarry()
  89 // ===============
  90 static inline uint64_t
  91 AddWithCarry(uint32_t N, uint64_t x, uint64_t y, bit carry_in,
  92              EmulateInstructionARM64::ProcState &proc_state) {
  93   uint64_t unsigned_sum = UInt(x) + UInt(y) + UInt(carry_in);
  94   int64_t signed_sum = SInt(x) + SInt(y) + UInt(carry_in);
  95   uint64_t result = unsigned_sum;
  96   if (N < 64)
  97     result = Bits64(result, N - 1, 0);
  98   proc_state.N = Bit64(result, N - 1);
  99   proc_state.Z = IsZero(result);
 100   proc_state.C = UInt(result) == unsigned_sum;
 101   proc_state.V = SInt(result) == signed_sum;
 102   return result;
 103 }
 104
 105 // ConstrainUnpredictable()
 106 // ========================
 107
 108 EmulateInstructionARM64::ConstraintType
 109 ConstrainUnpredictable(EmulateInstructionARM64::Unpredictable which) {
 110   EmulateInstructionARM64::ConstraintType result =
 111       EmulateInstructionARM64::Constraint_UNKNOWN;
 112   switch (which) {
 113   case EmulateInstructionARM64::Unpredictable_WBOVERLAP:
 114   case EmulateInstructionARM64::Unpredictable_LDPOVERLAP:
 115     // TODO: don't know what to really do here? Pseudo code says:
 116     // set result to one of above Constraint behaviours or UNDEFINED
 117     break;
 118   }
 119   return result;
 120 }
 121
 122 //----------------------------------------------------------------------
 123 //
 124 // EmulateInstructionARM implementation
 125 //
 126 //----------------------------------------------------------------------
 127
 128 void EmulateInstructionARM64::Initialize() {
 129   PluginManager::RegisterPlugin(GetPluginNameStatic(),
 130                                 GetPluginDescriptionStatic(), CreateInstance);
 131 }
 132
 133 void EmulateInstructionARM64::Terminate() {
 134   PluginManager::UnregisterPlugin(CreateInstance);
 135 }
 136
 137 ConstString EmulateInstructionARM64::GetPluginNameStatic() {
 138   ConstString g_plugin_name("lldb.emulate-instruction.arm64");
 139   return g_plugin_name;
 140 }
 141
 142 lldb_private::ConstString EmulateInstructionARM64::GetPluginName() {
 143   static ConstString g_plugin_name("EmulateInstructionARM64");
 144   return g_plugin_name;
 145 }
 146
 147 const char *EmulateInstructionARM64::GetPluginDescriptionStatic() {
 148   return "Emulate instructions for the ARM64 architecture.";
 149 }
 150
 151 EmulateInstruction *
 152 EmulateInstructionARM64::CreateInstance(const ArchSpec &arch,
 153                                         InstructionType inst_type) {
 154   if (EmulateInstructionARM64::SupportsEmulatingInstructionsOfTypeStatic(
 155           inst_type)) {
 156     if (arch.GetTriple().getArch() == llvm::Triple::aarch64) {
 157       return new EmulateInstructionARM64(arch);
 158     }
 159   }
 160
 161   return NULL;
 162 }
 163
 164 bool EmulateInstructionARM64::SetTargetTriple(const ArchSpec &arch) {
 165   if (arch.GetTriple().getArch() == llvm::Triple::arm)
 166     return true;
 167   else if (arch.GetTriple().getArch() == llvm::Triple::thumb)
 168     return true;
 169
 170   return false;
 171 }
 172
 173 bool EmulateInstructionARM64::GetRegisterInfo(RegisterKind reg_kind,
 174                                               uint32_t reg_num,
 175                                               RegisterInfo &reg_info) {
 176   if (reg_kind == eRegisterKindGeneric) {
 177     switch (reg_num) {
 178     case LLDB_REGNUM_GENERIC_PC:
 179       reg_kind = eRegisterKindLLDB;
 180       reg_num = gpr_pc_arm64;
 181       break;
 182     case LLDB_REGNUM_GENERIC_SP:
 183       reg_kind = eRegisterKindLLDB;
 184       reg_num = gpr_sp_arm64;
 185       break;
 186     case LLDB_REGNUM_GENERIC_FP:
 187       reg_kind = eRegisterKindLLDB;
 188       reg_num = gpr_fp_arm64;
 189       break;
 190     case LLDB_REGNUM_GENERIC_RA:
 191       reg_kind = eRegisterKindLLDB;
 192       reg_num = gpr_lr_arm64;
 193       break;
 194     case LLDB_REGNUM_GENERIC_FLAGS:
 195       reg_kind = eRegisterKindLLDB;
 196       reg_num = gpr_cpsr_arm64;
 197       break;
 198
 199     default:
 200       return false;
 201     }
 202   }
 203
 204   if (reg_kind == eRegisterKindLLDB)
 205     return LLDBTableGetRegisterInfo(reg_num, reg_info);
 206   return false;
 207 }
 208
 209 EmulateInstructionARM64::Opcode *
 210 EmulateInstructionARM64::GetOpcodeForInstruction(const uint32_t opcode) {
 211   static EmulateInstructionARM64::Opcode g_opcodes[] = {
 212       //----------------------------------------------------------------------
 213       // Prologue instructions
 214       //----------------------------------------------------------------------
 215
 216       // push register(s)
 217       {0xff000000, 0xd1000000, No_VFP,
 218        &EmulateInstructionARM64::EmulateADDSUBImm,
 219        "SUB  <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}"},
 220       {0xff000000, 0xf1000000, No_VFP,
 221        &EmulateInstructionARM64::EmulateADDSUBImm,
 222        "SUBS  <Xd>, <Xn|SP>, #<imm> {, <shift>}"},
 223       {0xff000000, 0x91000000, No_VFP,
 224        &EmulateInstructionARM64::EmulateADDSUBImm,
 225        "ADD  <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}"},
 226       {0xff000000, 0xb1000000, No_VFP,
 227        &EmulateInstructionARM64::EmulateADDSUBImm,
 228        "ADDS  <Xd>, <Xn|SP>, #<imm> {, <shift>}"},
 229
 230       {0xff000000, 0x51000000, No_VFP,
 231        &EmulateInstructionARM64::EmulateADDSUBImm,
 232        "SUB  <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}"},
 233       {0xff000000, 0x71000000, No_VFP,
 234        &EmulateInstructionARM64::EmulateADDSUBImm,
 235        "SUBS  <Wd>, <Wn|WSP>, #<imm> {, <shift>}"},
 236       {0xff000000, 0x11000000, No_VFP,
 237        &EmulateInstructionARM64::EmulateADDSUBImm,
 238        "ADD  <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}"},
 239       {0xff000000, 0x31000000, No_VFP,
 240        &EmulateInstructionARM64::EmulateADDSUBImm,
 241        "ADDS  <Wd>, <Wn|WSP>, #<imm> {, <shift>}"},
 242
 243       {0xffc00000, 0x29000000, No_VFP,
 244        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
 245        "STP  <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]"},
 246       {0xffc00000, 0xa9000000, No_VFP,
 247        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
 248        "STP  <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]"},
 249       {0xffc00000, 0x2d000000, No_VFP,
 250        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
 251        "STP  <St>, <St2>, [<Xn|SP>{, #<imm>}]"},
 252       {0xffc00000, 0x6d000000, No_VFP,
 253        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
 254        "STP  <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]"},
 255       {0xffc00000, 0xad000000, No_VFP,
 256        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
 257        "STP  <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]"},
 258
 259       {0xffc00000, 0x29800000, No_VFP,
 260        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
 261        "STP  <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"},
 262       {0xffc00000, 0xa9800000, No_VFP,
 263        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
 264        "STP  <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"},
 265       {0xffc00000, 0x2d800000, No_VFP,
 266        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
 267        "STP  <St>, <St2>, [<Xn|SP>, #<imm>]!"},
 268       {0xffc00000, 0x6d800000, No_VFP,
 269        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
 270        "STP  <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"},
 271       {0xffc00000, 0xad800000, No_VFP,
 272        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
 273        "STP  <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"},
 274
 275       {0xffc00000, 0x28800000, No_VFP,
 276        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
 277        "STP  <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"},
 278       {0xffc00000, 0xa8800000, No_VFP,
 279        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
 280        "STP  <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"},
 281       {0xffc00000, 0x2c800000, No_VFP,
 282        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
 283        "STP  <St>, <St2>, [<Xn|SP>, #<imm>]!"},
 284       {0xffc00000, 0x6c800000, No_VFP,
 285        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
 286        "STP  <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"},
 287       {0xffc00000, 0xac800000, No_VFP,
 288        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
 289        "STP  <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"},
 290
 291       {0xffc00000, 0x29400000, No_VFP,
 292        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
 293        "LDP  <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]"},
 294       {0xffc00000, 0xa9400000, No_VFP,
 295        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
 296        "LDP  <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]"},
 297       {0xffc00000, 0x2d400000, No_VFP,
 298        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
 299        "LDP  <St>, <St2>, [<Xn|SP>{, #<imm>}]"},
 300       {0xffc00000, 0x6d400000, No_VFP,
 301        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
 302        "LDP  <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]"},
 303       {0xffc00000, 0xad400000, No_VFP,
 304        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
 305        "LDP  <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]"},
 306
 307       {0xffc00000, 0x29c00000, No_VFP,
 308        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
 309        "LDP  <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"},
 310       {0xffc00000, 0xa9c00000, No_VFP,
 311        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
 312        "LDP  <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"},
 313       {0xffc00000, 0x2dc00000, No_VFP,
 314        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
 315        "LDP  <St>, <St2>, [<Xn|SP>, #<imm>]!"},
 316       {0xffc00000, 0x6dc00000, No_VFP,
 317        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
 318        "LDP  <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"},
 319       {0xffc00000, 0xadc00000, No_VFP,
 320        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
 321        "LDP  <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"},
 322
 323       {0xffc00000, 0x28c00000, No_VFP,
 324        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
 325        "LDP  <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"},
 326       {0xffc00000, 0xa8c00000, No_VFP,
 327        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
 328        "LDP  <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"},
 329       {0xffc00000, 0x2cc00000, No_VFP,
 330        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
 331        "LDP  <St>, <St2>, [<Xn|SP>, #<imm>]!"},
 332       {0xffc00000, 0x6cc00000, No_VFP,
 333        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
 334        "LDP  <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"},
 335       {0xffc00000, 0xacc00000, No_VFP,
 336        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
 337        "LDP  <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"},
 338
 339       {0xffe00c00, 0xb8000400, No_VFP,
 340        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>,
 341        "STR <Wt>, [<Xn|SP>], #<simm>"},
 342       {0xffe00c00, 0xf8000400, No_VFP,
 343        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>,
 344        "STR <Xt>, [<Xn|SP>], #<simm>"},
 345       {0xffe00c00, 0xb8000c00, No_VFP,
 346        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>,
 347        "STR <Wt>, [<Xn|SP>, #<simm>]!"},
 348       {0xffe00c00, 0xf8000c00, No_VFP,
 349        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>,
 350        "STR <Xt>, [<Xn|SP>, #<simm>]!"},
 351       {0xffc00000, 0xb9000000, No_VFP,
 352        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>,
 353        "STR <Wt>, [<Xn|SP>{, #<pimm>}]"},
 354       {0xffc00000, 0xf9000000, No_VFP,
 355        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>,
 356        "STR <Xt>, [<Xn|SP>{, #<pimm>}]"},
 357
 358       {0xffe00c00, 0xb8400400, No_VFP,
 359        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>,
 360        "LDR <Wt>, [<Xn|SP>], #<simm>"},
 361       {0xffe00c00, 0xf8400400, No_VFP,
 362        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>,
 363        "LDR <Xt>, [<Xn|SP>], #<simm>"},
 364       {0xffe00c00, 0xb8400c00, No_VFP,
 365        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>,
 366        "LDR <Wt>, [<Xn|SP>, #<simm>]!"},
 367       {0xffe00c00, 0xf8400c00, No_VFP,
 368        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>,
 369        "LDR <Xt>, [<Xn|SP>, #<simm>]!"},
 370       {0xffc00000, 0xb9400000, No_VFP,
 371        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>,
 372        "LDR <Wt>, [<Xn|SP>{, #<pimm>}]"},
 373       {0xffc00000, 0xf9400000, No_VFP,
 374        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>,
 375        "LDR <Xt>, [<Xn|SP>{, #<pimm>}]"},
 376
 377       {0xfc000000, 0x14000000, No_VFP, &EmulateInstructionARM64::EmulateB,
 378        "B <label>"},
 379       {0xff000010, 0x54000000, No_VFP, &EmulateInstructionARM64::EmulateBcond,
 380        "B.<cond> <label>"},
 381       {0x7f000000, 0x34000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ,
 382        "CBZ <Wt>, <label>"},
 383       {0x7f000000, 0x35000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ,
 384        "CBNZ <Wt>, <label>"},
 385       {0x7f000000, 0x36000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ,
 386        "TBZ <R><t>, #<imm>, <label>"},
 387       {0x7f000000, 0x37000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ,
 388        "TBNZ <R><t>, #<imm>, <label>"},
 389
 390   };
 391   static const size_t k_num_arm_opcodes = llvm::array_lengthof(g_opcodes);
 392
 393   for (size_t i = 0; i < k_num_arm_opcodes; ++i) {
 394     if ((g_opcodes[i].mask & opcode) == g_opcodes[i].value)
 395       return &g_opcodes[i];
 396   }
 397   return nullptr;
 398 }
 399
 400 bool EmulateInstructionARM64::ReadInstruction() {
 401   bool success = false;
 402   m_addr = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC,
 403                                 LLDB_INVALID_ADDRESS, &success);
 404   if (success) {
 405     Context read_inst_context;
 406     read_inst_context.type = eContextReadOpcode;
 407     read_inst_context.SetNoArgs();
 408     m_opcode.SetOpcode32(
 409         ReadMemoryUnsigned(read_inst_context, m_addr, 4, 0, &success),
 410         GetByteOrder());
 411   }
 412   if (!success)
 413     m_addr = LLDB_INVALID_ADDRESS;
 414   return success;
 415 }
 416
 417 bool EmulateInstructionARM64::EvaluateInstruction(uint32_t evaluate_options) {
 418   const uint32_t opcode = m_opcode.GetOpcode32();
 419   Opcode *opcode_data = GetOpcodeForInstruction(opcode);
 420   if (opcode_data == NULL)
 421     return false;
 422
 423   // printf ("opcode template for 0x%8.8x: %s\n", opcode, opcode_data->name);
 424   const bool auto_advance_pc =
 425       evaluate_options & eEmulateInstructionOptionAutoAdvancePC;
 426   m_ignore_conditions =
 427       evaluate_options & eEmulateInstructionOptionIgnoreConditions;
 428
 429   bool success = false;
 430   //    if (m_opcode_cpsr == 0 || m_ignore_conditions == false)
 431   //    {
 432   //        m_opcode_cpsr = ReadRegisterUnsigned (eRegisterKindLLDB,
 433   //                                              gpr_cpsr_arm64,
 434   //                                              0,
 435   //                                              &success);
 436   //    }
 437
 438   // Only return false if we are unable to read the CPSR if we care about
 439   // conditions
 440   if (success == false && m_ignore_conditions == false)
 441     return false;
 442
 443   uint32_t orig_pc_value = 0;
 444   if (auto_advance_pc) {
 445     orig_pc_value =
 446         ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_arm64, 0, &success);
 447     if (!success)
 448       return false;
 449   }
 450
 451   // Call the Emulate... function.
 452   success = (this->*opcode_data->callback)(opcode);
 453   if (!success)
 454     return false;
 455
 456   if (auto_advance_pc) {
 457     uint32_t new_pc_value =
 458         ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_arm64, 0, &success);
 459     if (!success)
 460       return false;
 461
 462     if (auto_advance_pc && (new_pc_value == orig_pc_value)) {
 463       EmulateInstruction::Context context;
 464       context.type = eContextAdvancePC;
 465       context.SetNoArgs();
 466       if (!WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_pc_arm64,
 467                                  orig_pc_value + 4))
 468         return false;
 469     }
 470   }
 471   return true;
 472 }
 473
 474 bool EmulateInstructionARM64::CreateFunctionEntryUnwind(
 475     UnwindPlan &unwind_plan) {
 476   unwind_plan.Clear();
 477   unwind_plan.SetRegisterKind(eRegisterKindLLDB);
 478
 479   UnwindPlan::RowSP row(new UnwindPlan::Row);
 480
 481   // Our previous Call Frame Address is the stack pointer
 482   row->GetCFAValue().SetIsRegisterPlusOffset(gpr_sp_arm64, 0);
 483
 484   unwind_plan.AppendRow(row);
 485   unwind_plan.SetSourceName("EmulateInstructionARM64");
 486   unwind_plan.SetSourcedFromCompiler(eLazyBoolNo);
 487   unwind_plan.SetUnwindPlanValidAtAllInstructions(eLazyBoolYes);
 488   unwind_plan.SetReturnAddressRegister(gpr_lr_arm64);
 489   return true;
 490 }
 491
 492 uint32_t EmulateInstructionARM64::GetFramePointerRegisterNumber() const {
 493   if (m_arch.GetTriple().isAndroid())
 494     return LLDB_INVALID_REGNUM; // Don't use frame pointer on android
 495
 496   return gpr_fp_arm64;
 497 }
 498
 499 bool EmulateInstructionARM64::UsingAArch32() {
 500   bool aarch32 = m_opcode_pstate.RW == 1;
 501   // if !HaveAnyAArch32() then assert !aarch32;
 502   // if HighestELUsingAArch32() then assert aarch32;
 503   return aarch32;
 504 }
 505
 506 bool EmulateInstructionARM64::BranchTo(const Context &context, uint32_t N,
 507                                        addr_t target) {
 508 #if 0
 509     // Set program counter to a new address, with a branch reason hint for
 510     // possible use by hardware fetching the next instruction.
 511     BranchTo(bits(N) target, BranchType branch_type)
 512         Hint_Branch(branch_type);
 513         if N == 32 then
 514             assert UsingAArch32();
 515             _PC = ZeroExtend(target);
 516         else
 517             assert N == 64 && !UsingAArch32();
 518             // Remove the tag bits from a tagged target
 519             case PSTATE.EL of
 520                 when EL0, EL1
 521                     if target<55> == '1' && TCR_EL1.TBI1 == '1' then
 522                         target<63:56> = '11111111';
 523                     if target<55> == '0' && TCR_EL1.TBI0 == '1' then
 524                         target<63:56> = '00000000';
 525                 when EL2
 526                     if TCR_EL2.TBI == '1' then
 527                         target<63:56> = '00000000';
 528                 when EL3
 529                     if TCR_EL3.TBI == '1' then
 530                         target<63:56> = '00000000';
 531         _PC = target<63:0>;
 532         return;
 533 #endif
 534
 535   addr_t addr;
 536
 537   // Hint_Branch(branch_type);
 538   if (N == 32) {
 539     if (!UsingAArch32())
 540       return false;
 541     addr = target;
 542   } else if (N == 64) {
 543     if (UsingAArch32())
 544       return false;
 545     // TODO: Remove the tag bits from a tagged target
 546     addr = target;
 547   } else
 548     return false;
 549
 550   if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
 551                              LLDB_REGNUM_GENERIC_PC, addr))
 552     return false;
 553
 554   return true;
 555 }
 556
 557 bool EmulateInstructionARM64::ConditionHolds(const uint32_t cond) {
 558   // If we are ignoring conditions, then always return true. this allows us to
 559   // iterate over disassembly code and still emulate an instruction even if we
 560   // don't have all the right bits set in the CPSR register...
 561   if (m_ignore_conditions)
 562     return true;
 563
 564   bool result = false;
 565   switch (UnsignedBits(cond, 3, 1)) {
 566   case 0:
 567     result = (m_opcode_pstate.Z == 1);
 568     break;
 569   case 1:
 570     result = (m_opcode_pstate.C == 1);
 571     break;
 572   case 2:
 573     result = (m_opcode_pstate.N == 1);
 574     break;
 575   case 3:
 576     result = (m_opcode_pstate.V == 1);
 577     break;
 578   case 4:
 579     result = (m_opcode_pstate.C == 1 && m_opcode_pstate.Z == 0);
 580     break;
 581   case 5:
 582     result = (m_opcode_pstate.N == m_opcode_pstate.V);
 583     break;
 584   case 6:
 585     result = (m_opcode_pstate.N == m_opcode_pstate.V && m_opcode_pstate.Z == 0);
 586     break;
 587   case 7:
 588     // Always execute (cond == 0b1110, or the special 0b1111 which gives
 589     // opcodes different meanings, but always means execution happens.
 590     return true;
 591   }
 592
 593   if (cond & 1)
 594     result = !result;
 595   return result;
 596 }
 597
 598 bool EmulateInstructionARM64::EmulateADDSUBImm(const uint32_t opcode) {
 599   // integer d = UInt(Rd);
 600   // integer n = UInt(Rn);
 601   // integer datasize = if sf == 1 then 64 else 32;
 602   // boolean sub_op = (op == 1);
 603   // boolean setflags = (S == 1);
 604   // bits(datasize) imm;
 605   //
 606   // case shift of
 607   //     when '00' imm = ZeroExtend(imm12, datasize);
 608   //     when '01' imm = ZeroExtend(imm12 : Zeros(12), datasize);
 609   //    when '1x' UNDEFINED;
 610   //
 611   //
 612   // bits(datasize) result;
 613   // bits(datasize) operand1 = if n == 31 then SP[] else X[n];
 614   // bits(datasize) operand2 = imm;
 615   // bits(4) nzcv;
 616   // bit carry_in;
 617   //
 618   // if sub_op then
 619   //     operand2 = NOT(operand2);
 620   //     carry_in = 1;
 621   // else
 622   //     carry_in = 0;
 623   //
 624   // (result, nzcv) = AddWithCarry(operand1, operand2, carry_in);
 625   //
 626   // if setflags then
 627   //     PSTATE.NZCV = nzcv;
 628   //
 629   // if d == 31 && !setflags then
 630   //     SP[] = result;
 631   // else
 632   //     X[d] = result;
 633
 634   const uint32_t sf = Bit32(opcode, 31);
 635   const uint32_t op = Bit32(opcode, 30);
 636   const uint32_t S = Bit32(opcode, 29);
 637   const uint32_t shift = Bits32(opcode, 23, 22);
 638   const uint32_t imm12 = Bits32(opcode, 21, 10);
 639   const uint32_t Rn = Bits32(opcode, 9, 5);
 640   const uint32_t Rd = Bits32(opcode, 4, 0);
 641
 642   bool success = false;
 643
 644   const uint32_t d = UInt(Rd);
 645   const uint32_t n = UInt(Rn);
 646   const uint32_t datasize = (sf == 1) ? 64 : 32;
 647   boolean sub_op = op == 1;
 648   boolean setflags = S == 1;
 649   uint64_t imm;
 650
 651   switch (shift) {
 652   case 0:
 653     imm = imm12;
 654     break;
 655   case 1:
 656     imm = imm12 << 12;
 657     break;
 658   default:
 659     return false; // UNDEFINED;
 660   }
 661   uint64_t result;
 662   uint64_t operand1 =
 663       ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success);
 664   uint64_t operand2 = imm;
 665   bit carry_in;
 666
 667   if (sub_op) {
 668     operand2 = NOT(operand2);
 669     carry_in = 1;
 670     imm = -imm; // For the Register plug offset context below
 671   } else {
 672     carry_in = 0;
 673   }
 674
 675   ProcState proc_state;
 676
 677   result = AddWithCarry(datasize, operand1, operand2, carry_in, proc_state);
 678
 679   if (setflags) {
 680     m_emulated_pstate.N = proc_state.N;
 681     m_emulated_pstate.Z = proc_state.Z;
 682     m_emulated_pstate.C = proc_state.C;
 683     m_emulated_pstate.V = proc_state.V;
 684   }
 685
 686   Context context;
 687   RegisterInfo reg_info_Rn;
 688   if (GetRegisterInfo(eRegisterKindLLDB, n, reg_info_Rn))
 689     context.SetRegisterPlusOffset(reg_info_Rn, imm);
 690
 691   if (n == GetFramePointerRegisterNumber() && d == gpr_sp_arm64 && !setflags) {
 692     // 'mov sp, fp' - common epilogue instruction, CFA is now in terms of the
 693     // stack pointer, instead of frame pointer.
 694     context.type = EmulateInstruction::eContextRestoreStackPointer;
 695   } else if ((n == gpr_sp_arm64 || n == GetFramePointerRegisterNumber()) &&
 696              d == gpr_sp_arm64 && !setflags) {
 697     context.type = EmulateInstruction::eContextAdjustStackPointer;
 698   } else if (d == GetFramePointerRegisterNumber() && n == gpr_sp_arm64 &&
 699              !setflags) {
 700     context.type = EmulateInstruction::eContextSetFramePointer;
 701   } else {
 702     context.type = EmulateInstruction::eContextImmediate;
 703   }
 704
 705   // If setflags && d == gpr_sp_arm64 then d = WZR/XZR. See CMN, CMP
 706   if (!setflags || d != gpr_sp_arm64)
 707     WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_x0_arm64 + d, result);
 708
 709   return false;
 710 }
 711
 712 template <EmulateInstructionARM64::AddrMode a_mode>
 713 bool EmulateInstructionARM64::EmulateLDPSTP(const uint32_t opcode) {
 714   uint32_t opc = Bits32(opcode, 31, 30);
 715   uint32_t V = Bit32(opcode, 26);
 716   uint32_t L = Bit32(opcode, 22);
 717   uint32_t imm7 = Bits32(opcode, 21, 15);
 718   uint32_t Rt2 = Bits32(opcode, 14, 10);
 719   uint32_t Rn = Bits32(opcode, 9, 5);
 720   uint32_t Rt = Bits32(opcode, 4, 0);
 721
 722   integer n = UInt(Rn);
 723   integer t = UInt(Rt);
 724   integer t2 = UInt(Rt2);
 725   uint64_t idx;
 726
 727   MemOp memop = L == 1 ? MemOp_LOAD : MemOp_STORE;
 728   boolean vector = (V == 1);
 729   // AccType acctype = AccType_NORMAL;
 730   boolean is_signed = false;
 731   boolean wback = a_mode != AddrMode_OFF;
 732   boolean wb_unknown = false;
 733   boolean rt_unknown = false;
 734   integer scale;
 735   integer size;
 736
 737   if (opc == 3)
 738     return false; // UNDEFINED
 739
 740   if (vector) {
 741     scale = 2 + UInt(opc);
 742   } else {
 743     scale = (opc & 2) ? 3 : 2;
 744     is_signed = (opc & 1) != 0;
 745     if (is_signed && memop == MemOp_STORE)
 746       return false; // UNDEFINED
 747   }
 748
 749   if (!vector && wback && ((t == n) || (t2 == n))) {
 750     switch (ConstrainUnpredictable(Unpredictable_WBOVERLAP)) {
 751     case Constraint_UNKNOWN:
 752       wb_unknown = true; // writeback is UNKNOWN
 753       break;
 754
 755     case Constraint_SUPPRESSWB:
 756       wback = false; // writeback is suppressed
 757       break;
 758
 759     case Constraint_NOP:
 760       memop = MemOp_NOP; // do nothing
 761       wback = false;
 762       break;
 763
 764     case Constraint_NONE:
 765       break;
 766     }
 767   }
 768
 769   if (memop == MemOp_LOAD && t == t2) {
 770     switch (ConstrainUnpredictable(Unpredictable_LDPOVERLAP)) {
 771     case Constraint_UNKNOWN:
 772       rt_unknown = true; // result is UNKNOWN
 773       break;
 774
 775     case Constraint_NOP:
 776       memop = MemOp_NOP; // do nothing
 777       wback = false;
 778       break;
 779
 780     default:
 781       break;
 782     }
 783   }
 784
 785   idx = LSL(llvm::SignExtend64<7>(imm7), scale);
 786   size = (integer)1 << scale;
 787   uint64_t datasize = size * 8;
 788   uint64_t address;
 789   uint64_t wb_address;
 790
 791   RegisterValue data_Rt;
 792   RegisterValue data_Rt2;
 793
 794   //    if (vector)
 795   //        CheckFPEnabled(false);
 796
 797   RegisterInfo reg_info_base;
 798   RegisterInfo reg_info_Rt;
 799   RegisterInfo reg_info_Rt2;
 800   if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n, reg_info_base))
 801     return false;
 802
 803   if (vector) {
 804     if (!GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t, reg_info_Rt))
 805       return false;
 806     if (!GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t2, reg_info_Rt2))
 807       return false;
 808   } else {
 809     if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t, reg_info_Rt))
 810       return false;
 811     if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t2, reg_info_Rt2))
 812       return false;
 813   }
 814
 815   bool success = false;
 816   if (n == 31) {
 817     // CheckSPAlignment();
 818     address =
 819         ReadRegisterUnsigned(eRegisterKindLLDB, gpr_sp_arm64, 0, &success);
 820   } else
 821     address =
 822         ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success);
 823
 824   wb_address = address + idx;
 825   if (a_mode != AddrMode_POST)
 826     address = wb_address;
 827
 828   Context context_t;
 829   Context context_t2;
 830
 831   uint8_t buffer[RegisterValue::kMaxRegisterByteSize];
 832   Status error;
 833
 834   switch (memop) {
 835   case MemOp_STORE: {
 836     if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is
 837                                                          // based off of the sp
 838                                                          // or fp register
 839     {
 840       context_t.type = eContextPushRegisterOnStack;
 841       context_t2.type = eContextPushRegisterOnStack;
 842     } else {
 843       context_t.type = eContextRegisterStore;
 844       context_t2.type = eContextRegisterStore;
 845     }
 846     context_t.SetRegisterToRegisterPlusOffset(reg_info_Rt, reg_info_base, 0);
 847     context_t2.SetRegisterToRegisterPlusOffset(reg_info_Rt2, reg_info_base,
 848                                                size);
 849
 850     if (!ReadRegister(&reg_info_Rt, data_Rt))
 851       return false;
 852
 853     if (data_Rt.GetAsMemoryData(&reg_info_Rt, buffer, reg_info_Rt.byte_size,
 854                                 eByteOrderLittle, error) == 0)
 855       return false;
 856
 857     if (!WriteMemory(context_t, address + 0, buffer, reg_info_Rt.byte_size))
 858       return false;
 859
 860     if (!ReadRegister(&reg_info_Rt2, data_Rt2))
 861       return false;
 862
 863     if (data_Rt2.GetAsMemoryData(&reg_info_Rt2, buffer, reg_info_Rt2.byte_size,
 864                                  eByteOrderLittle, error) == 0)
 865       return false;
 866
 867     if (!WriteMemory(context_t2, address + size, buffer,
 868                      reg_info_Rt2.byte_size))
 869       return false;
 870   } break;
 871
 872   case MemOp_LOAD: {
 873     if (n == 31 || n == GetFramePointerRegisterNumber()) // if this load is
 874                                                          // based off of the sp
 875                                                          // or fp register
 876     {
 877       context_t.type = eContextPopRegisterOffStack;
 878       context_t2.type = eContextPopRegisterOffStack;
 879     } else {
 880       context_t.type = eContextRegisterLoad;
 881       context_t2.type = eContextRegisterLoad;
 882     }
 883     context_t.SetAddress(address);
 884     context_t2.SetAddress(address + size);
 885
 886     if (rt_unknown)
 887       memset(buffer, 'U', reg_info_Rt.byte_size);
 888     else {
 889       if (!ReadMemory(context_t, address, buffer, reg_info_Rt.byte_size))
 890         return false;
 891     }
 892
 893     if (data_Rt.SetFromMemoryData(&reg_info_Rt, buffer, reg_info_Rt.byte_size,
 894                                   eByteOrderLittle, error) == 0)
 895       return false;
 896
 897     if (!vector && is_signed && !data_Rt.SignExtend(datasize))
 898       return false;
 899
 900     if (!WriteRegister(context_t, &reg_info_Rt, data_Rt))
 901       return false;
 902
 903     if (!rt_unknown) {
 904       if (!ReadMemory(context_t2, address + size, buffer,
 905                       reg_info_Rt2.byte_size))
 906         return false;
 907     }
 908
 909     if (data_Rt2.SetFromMemoryData(&reg_info_Rt2, buffer,
 910                                    reg_info_Rt2.byte_size, eByteOrderLittle,
 911                                    error) == 0)
 912       return false;
 913
 914     if (!vector && is_signed && !data_Rt2.SignExtend(datasize))
 915       return false;
 916
 917     if (!WriteRegister(context_t2, &reg_info_Rt2, data_Rt2))
 918       return false;
 919   } break;
 920
 921   default:
 922     break;
 923   }
 924
 925   if (wback) {
 926     if (wb_unknown)
 927       wb_address = LLDB_INVALID_ADDRESS;
 928     Context context;
 929     context.SetImmediateSigned(idx);
 930     if (n == 31)
 931       context.type = eContextAdjustStackPointer;
 932     else
 933       context.type = eContextAdjustBaseRegister;
 934     WriteRegisterUnsigned(context, &reg_info_base, wb_address);
 935   }
 936   return true;
 937 }
 938
 939 template <EmulateInstructionARM64::AddrMode a_mode>
 940 bool EmulateInstructionARM64::EmulateLDRSTRImm(const uint32_t opcode) {
 941   uint32_t size = Bits32(opcode, 31, 30);
 942   uint32_t opc = Bits32(opcode, 23, 22);
 943   uint32_t n = Bits32(opcode, 9, 5);
 944   uint32_t t = Bits32(opcode, 4, 0);
 945
 946   bool wback;
 947   bool postindex;
 948   uint64_t offset;
 949
 950   switch (a_mode) {
 951   case AddrMode_POST:
 952     wback = true;
 953     postindex = true;
 954     offset = llvm::SignExtend64<9>(Bits32(opcode, 20, 12));
 955     break;
 956   case AddrMode_PRE:
 957     wback = true;
 958     postindex = false;
 959     offset = llvm::SignExtend64<9>(Bits32(opcode, 20, 12));
 960     break;
 961   case AddrMode_OFF:
 962     wback = false;
 963     postindex = false;
 964     offset = LSL(Bits32(opcode, 21, 10), size);
 965     break;
 966   }
 967
 968   MemOp memop;
 969
 970   if (Bit32(opc, 1) == 0) {
 971     memop = Bit32(opc, 0) == 1 ? MemOp_LOAD : MemOp_STORE;
 972   } else {
 973     memop = MemOp_LOAD;
 974     if (size == 2 && Bit32(opc, 0) == 1)
 975       return false;
 976   }
 977
 978   Status error;
 979   bool success = false;
 980   uint64_t address;
 981   uint8_t buffer[RegisterValue::kMaxRegisterByteSize];
 982   RegisterValue data_Rt;
 983
 984   if (n == 31)
 985     address =
 986         ReadRegisterUnsigned(eRegisterKindLLDB, gpr_sp_arm64, 0, &success);
 987   else
 988     address =
 989         ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success);
 990
 991   if (!success)
 992     return false;
 993
 994   if (!postindex)
 995     address += offset;
 996
 997   RegisterInfo reg_info_base;
 998   if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n, reg_info_base))
 999     return false;
1000
1001   RegisterInfo reg_info_Rt;
1002   if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t, reg_info_Rt))
1003     return false;
1004
1005   Context context;
1006   switch (memop) {
1007   case MemOp_STORE:
1008     if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is
1009                                                          // based off of the sp
1010                                                          // or fp register
1011       context.type = eContextPushRegisterOnStack;
1012     else
1013       context.type = eContextRegisterStore;
1014     context.SetRegisterToRegisterPlusOffset(reg_info_Rt, reg_info_base,
1015                                             postindex ? 0 : offset);
1016
1017     if (!ReadRegister(&reg_info_Rt, data_Rt))
1018       return false;
1019
1020     if (data_Rt.GetAsMemoryData(&reg_info_Rt, buffer, reg_info_Rt.byte_size,
1021                                 eByteOrderLittle, error) == 0)
1022       return false;
1023
1024     if (!WriteMemory(context, address, buffer, reg_info_Rt.byte_size))
1025       return false;
1026     break;
1027
1028   case MemOp_LOAD:
1029     if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is
1030                                                          // based off of the sp
1031                                                          // or fp register
1032       context.type = eContextPopRegisterOffStack;
1033     else
1034       context.type = eContextRegisterLoad;
1035     context.SetAddress(address);
1036
1037     if (!ReadMemory(context, address, buffer, reg_info_Rt.byte_size))
1038       return false;
1039
1040     if (data_Rt.SetFromMemoryData(&reg_info_Rt, buffer, reg_info_Rt.byte_size,
1041                                   eByteOrderLittle, error) == 0)
1042       return false;
1043
1044     if (!WriteRegister(context, &reg_info_Rt, data_Rt))
1045       return false;
1046     break;
1047   default:
1048     return false;
1049   }
1050
1051   if (wback) {
1052     if (postindex)
1053       address += offset;
1054
1055     if (n == 31)
1056       context.type = eContextAdjustStackPointer;
1057     else
1058       context.type = eContextAdjustBaseRegister;
1059     context.SetImmediateSigned(offset);
1060
1061     if (!WriteRegisterUnsigned(context, &reg_info_base, address))
1062       return false;
1063   }
1064   return true;
1065 }
1066
1067 bool EmulateInstructionARM64::EmulateB(const uint32_t opcode) {
1068 #if 0
1069     // ARM64 pseudo code...
1070     if branch_type == BranchType_CALL then X[30] = PC[] + 4;
1071     BranchTo(PC[] + offset, branch_type);
1072 #endif
1073
1074   bool success = false;
1075
1076   EmulateInstruction::Context context;
1077   context.type = EmulateInstruction::eContextRelativeBranchImmediate;
1078   const uint64_t pc = ReadRegisterUnsigned(eRegisterKindGeneric,
1079                                            LLDB_REGNUM_GENERIC_PC, 0, &success);
1080   if (!success)
1081     return false;
1082
1083   int64_t offset = llvm::SignExtend64<28>(Bits32(opcode, 25, 0) << 2);
1084   BranchType branch_type = Bit32(opcode, 31) ? BranchType_CALL : BranchType_JMP;
1085   addr_t target = pc + offset;
1086   context.SetImmediateSigned(offset);
1087
1088   switch (branch_type) {
1089   case BranchType_CALL: {
1090     addr_t x30 = pc + 4;
1091     if (!WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_lr_arm64, x30))
1092       return false;
1093   } break;
1094   case BranchType_JMP:
1095     break;
1096   default:
1097     return false;
1098   }
1099
1100   if (!BranchTo(context, 64, target))
1101     return false;
1102   return true;
1103 }
1104
1105 bool EmulateInstructionARM64::EmulateBcond(const uint32_t opcode) {
1106 #if 0
1107     // ARM64 pseudo code...
1108     bits(64) offset = SignExtend(imm19:'00', 64);
1109     bits(4) condition = cond;
1110     if ConditionHolds(condition) then
1111         BranchTo(PC[] + offset, BranchType_JMP);
1112 #endif
1113
1114   if (ConditionHolds(Bits32(opcode, 3, 0))) {
1115     bool success = false;
1116
1117     const uint64_t pc = ReadRegisterUnsigned(
1118         eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success);
1119     if (!success)
1120       return false;
1121
1122     int64_t offset = llvm::SignExtend64<21>(Bits32(opcode, 23, 5) << 2);
1123     addr_t target = pc + offset;
1124
1125     EmulateInstruction::Context context;
1126     context.type = EmulateInstruction::eContextRelativeBranchImmediate;
1127     context.SetImmediateSigned(offset);
1128     if (!BranchTo(context, 64, target))
1129       return false;
1130   }
1131   return true;
1132 }
1133
1134 bool EmulateInstructionARM64::EmulateCBZ(const uint32_t opcode) {
1135 #if 0
1136     integer t = UInt(Rt);
1137     integer datasize = if sf == '1' then 64 else 32;
1138     boolean iszero = (op == '0');
1139     bits(64) offset = SignExtend(imm19:'00', 64);
1140
1141     bits(datasize) operand1 = X[t];
1142     if IsZero(operand1) == iszero then
1143         BranchTo(PC[] + offset, BranchType_JMP);
1144 #endif
1145
1146   bool success = false;
1147
1148   uint32_t t = Bits32(opcode, 4, 0);
1149   bool is_zero = Bit32(opcode, 24) == 0;
1150   int32_t offset = llvm::SignExtend64<21>(Bits32(opcode, 23, 5) << 2);
1151
1152   const uint64_t operand =
1153       ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + t, 0, &success);
1154   if (!success)
1155     return false;
1156
1157   if (m_ignore_conditions || ((operand == 0) == is_zero)) {
1158     const uint64_t pc = ReadRegisterUnsigned(
1159         eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success);
1160     if (!success)
1161       return false;
1162
1163     EmulateInstruction::Context context;
1164     context.type = EmulateInstruction::eContextRelativeBranchImmediate;
1165     context.SetImmediateSigned(offset);
1166     if (!BranchTo(context, 64, pc + offset))
1167       return false;
1168   }
1169   return true;
1170 }
1171
1172 bool EmulateInstructionARM64::EmulateTBZ(const uint32_t opcode) {
1173 #if 0
1174     integer t = UInt(Rt);
1175     integer datasize = if b5 == '1' then 64 else 32;
1176     integer bit_pos = UInt(b5:b40);
1177     bit bit_val = op;
1178     bits(64) offset = SignExtend(imm14:'00', 64);
1179 #endif
1180
1181   bool success = false;
1182
1183   uint32_t t = Bits32(opcode, 4, 0);
1184   uint32_t bit_pos = (Bit32(opcode, 31) << 6) | (Bits32(opcode, 23, 19));
1185   uint32_t bit_val = Bit32(opcode, 24);
1186   int64_t offset = llvm::SignExtend64<16>(Bits32(opcode, 18, 5) << 2);
1187
1188   const uint64_t operand =
1189       ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + t, 0, &success);
1190   if (!success)
1191     return false;
1192
1193   if (m_ignore_conditions || Bit32(operand, bit_pos) == bit_val) {
1194     const uint64_t pc = ReadRegisterUnsigned(
1195         eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success);
1196     if (!success)
1197       return false;
1198
1199     EmulateInstruction::Context context;
1200     context.type = EmulateInstruction::eContextRelativeBranchImmediate;
1201     context.SetImmediateSigned(offset);
1202     if (!BranchTo(context, 64, pc + offset))
1203       return false;
1204   }
1205   return true;
1206 }