1 //===-- RegisterContextDarwin_arm.cpp ---------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #if defined(__APPLE__)
12 #include "RegisterContextDarwin_arm.h"
15 #include <mach/mach_types.h>
16 #include <mach/thread_act.h>
19 // Other libraries and framework includes
20 #include "lldb/Core/DataBufferHeap.h"
21 #include "lldb/Core/DataExtractor.h"
22 #include "lldb/Core/Log.h"
23 #include "lldb/Core/RegisterValue.h"
24 #include "lldb/Core/Scalar.h"
25 #include "lldb/Host/Endian.h"
26 #include "llvm/Support/Compiler.h"
28 #include "Plugins/Process/Utility/InstructionUtils.h"
30 // Support building against older versions of LLVM, this macro was added
32 #ifndef LLVM_EXTENSION
33 #define LLVM_EXTENSION
37 #include "ARM_DWARF_Registers.h"
38 #include "Utility/ARM_ehframe_Registers.h"
40 #include "llvm/ADT/STLExtras.h"
43 using namespace lldb_private;
60 gpr_r13, gpr_sp = gpr_r13,
61 gpr_r14, gpr_lr = gpr_r14,
62 gpr_r15, gpr_pc = gpr_r15,
175 #define GPR_OFFSET(idx) ((idx) * 4)
176 #define FPU_OFFSET(idx) ((idx) * 4 + sizeof (RegisterContextDarwin_arm::GPR))
177 #define EXC_OFFSET(idx) ((idx) * 4 + sizeof (RegisterContextDarwin_arm::GPR) + sizeof (RegisterContextDarwin_arm::FPU))
178 #define DBG_OFFSET(reg) ((LLVM_EXTENSION offsetof (RegisterContextDarwin_arm::DBG, reg) + sizeof (RegisterContextDarwin_arm::GPR) + sizeof (RegisterContextDarwin_arm::FPU) + sizeof (RegisterContextDarwin_arm::EXC)))
180 #define DEFINE_DBG(reg, i) #reg, NULL, sizeof(((RegisterContextDarwin_arm::DBG *)NULL)->reg[i]), DBG_OFFSET(reg[i]), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, NULL, NULL
181 #define REG_CONTEXT_SIZE (sizeof (RegisterContextDarwin_arm::GPR) + sizeof (RegisterContextDarwin_arm::FPU) + sizeof (RegisterContextDarwin_arm::EXC))
183 static RegisterInfo g_register_infos[] = {
184 // General purpose registers
185 // NAME ALT SZ OFFSET ENCODING FORMAT EH_FRAME DWARF GENERIC PROCESS PLUGIN LLDB NATIVE VALUE REGS INVALIDATE REGS
186 // ====== ======= == ============= ============= ============ =============== =============== ========================= ===================== ============= ========== ===============
187 { "r0", NULL, 4, GPR_OFFSET(0), eEncodingUint, eFormatHex, { ehframe_r0, dwarf_r0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r0 }, NULL, NULL},
188 { "r1", NULL, 4, GPR_OFFSET(1), eEncodingUint, eFormatHex, { ehframe_r1, dwarf_r1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r1 }, NULL, NULL},
189 { "r2", NULL, 4, GPR_OFFSET(2), eEncodingUint, eFormatHex, { ehframe_r2, dwarf_r2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r2 }, NULL, NULL},
190 { "r3", NULL, 4, GPR_OFFSET(3), eEncodingUint, eFormatHex, { ehframe_r3, dwarf_r3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r3 }, NULL, NULL},
191 { "r4", NULL, 4, GPR_OFFSET(4), eEncodingUint, eFormatHex, { ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r4 }, NULL, NULL},
192 { "r5", NULL, 4, GPR_OFFSET(5), eEncodingUint, eFormatHex, { ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r5 }, NULL, NULL},
193 { "r6", NULL, 4, GPR_OFFSET(6), eEncodingUint, eFormatHex, { ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r6 }, NULL, NULL},
194 { "r7", NULL, 4, GPR_OFFSET(7), eEncodingUint, eFormatHex, { ehframe_r7, dwarf_r7, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM, gpr_r7 }, NULL, NULL},
195 { "r8", NULL, 4, GPR_OFFSET(8), eEncodingUint, eFormatHex, { ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r8 }, NULL, NULL},
196 { "r9", NULL, 4, GPR_OFFSET(9), eEncodingUint, eFormatHex, { ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r9 }, NULL, NULL},
197 { "r10", NULL, 4, GPR_OFFSET(10), eEncodingUint, eFormatHex, { ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r10 }, NULL, NULL},
198 { "r11", NULL, 4, GPR_OFFSET(11), eEncodingUint, eFormatHex, { ehframe_r11, dwarf_r11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r11 }, NULL, NULL},
199 { "r12", NULL, 4, GPR_OFFSET(12), eEncodingUint, eFormatHex, { ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r12 }, NULL, NULL},
200 { "sp", "r13", 4, GPR_OFFSET(13), eEncodingUint, eFormatHex, { ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM, gpr_sp }, NULL, NULL},
201 { "lr", "r14", 4, GPR_OFFSET(14), eEncodingUint, eFormatHex, { ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM, gpr_lr }, NULL, NULL},
202 { "pc", "r15", 4, GPR_OFFSET(15), eEncodingUint, eFormatHex, { ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM, gpr_pc }, NULL, NULL},
203 { "cpsr", "psr", 4, GPR_OFFSET(16), eEncodingUint, eFormatHex, { ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM, gpr_cpsr }, NULL, NULL},
205 { "s0", NULL, 4, FPU_OFFSET(0), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s0 }, NULL, NULL},
206 { "s1", NULL, 4, FPU_OFFSET(1), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s1 }, NULL, NULL},
207 { "s2", NULL, 4, FPU_OFFSET(2), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s2 }, NULL, NULL},
208 { "s3", NULL, 4, FPU_OFFSET(3), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s3 }, NULL, NULL},
209 { "s4", NULL, 4, FPU_OFFSET(4), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s4 }, NULL, NULL},
210 { "s5", NULL, 4, FPU_OFFSET(5), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s5 }, NULL, NULL},
211 { "s6", NULL, 4, FPU_OFFSET(6), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s6 }, NULL, NULL},
212 { "s7", NULL, 4, FPU_OFFSET(7), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s7 }, NULL, NULL},
213 { "s8", NULL, 4, FPU_OFFSET(8), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s8 }, NULL, NULL},
214 { "s9", NULL, 4, FPU_OFFSET(9), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s9 }, NULL, NULL},
215 { "s10", NULL, 4, FPU_OFFSET(10), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s10 }, NULL, NULL},
216 { "s11", NULL, 4, FPU_OFFSET(11), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s11 }, NULL, NULL},
217 { "s12", NULL, 4, FPU_OFFSET(12), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s12 }, NULL, NULL},
218 { "s13", NULL, 4, FPU_OFFSET(13), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s13 }, NULL, NULL},
219 { "s14", NULL, 4, FPU_OFFSET(14), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s14 }, NULL, NULL},
220 { "s15", NULL, 4, FPU_OFFSET(15), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s15 }, NULL, NULL},
221 { "s16", NULL, 4, FPU_OFFSET(16), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s16 }, NULL, NULL},
222 { "s17", NULL, 4, FPU_OFFSET(17), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s17 }, NULL, NULL},
223 { "s18", NULL, 4, FPU_OFFSET(18), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s18 }, NULL, NULL},
224 { "s19", NULL, 4, FPU_OFFSET(19), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s19 }, NULL, NULL},
225 { "s20", NULL, 4, FPU_OFFSET(20), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s20 }, NULL, NULL},
226 { "s21", NULL, 4, FPU_OFFSET(21), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s21 }, NULL, NULL},
227 { "s22", NULL, 4, FPU_OFFSET(22), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s22 }, NULL, NULL},
228 { "s23", NULL, 4, FPU_OFFSET(23), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s23 }, NULL, NULL},
229 { "s24", NULL, 4, FPU_OFFSET(24), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s24 }, NULL, NULL},
230 { "s25", NULL, 4, FPU_OFFSET(25), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s25 }, NULL, NULL},
231 { "s26", NULL, 4, FPU_OFFSET(26), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s26 }, NULL, NULL},
232 { "s27", NULL, 4, FPU_OFFSET(27), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s27 }, NULL, NULL},
233 { "s28", NULL, 4, FPU_OFFSET(28), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s28 }, NULL, NULL},
234 { "s29", NULL, 4, FPU_OFFSET(29), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s29 }, NULL, NULL},
235 { "s30", NULL, 4, FPU_OFFSET(30), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s30 }, NULL, NULL},
236 { "s31", NULL, 4, FPU_OFFSET(31), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s31 }, NULL, NULL},
237 { "fpscr", NULL, 4, FPU_OFFSET(32), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_fpscr }, NULL, NULL},
239 { "exception",NULL, 4, EXC_OFFSET(0), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, exc_exception }, NULL, NULL},
240 { "fsr", NULL, 4, EXC_OFFSET(1), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, exc_fsr }, NULL, NULL},
241 { "far", NULL, 4, EXC_OFFSET(2), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, exc_far }, NULL, NULL},
243 { DEFINE_DBG (bvr, 0) },
244 { DEFINE_DBG (bvr, 1) },
245 { DEFINE_DBG (bvr, 2) },
246 { DEFINE_DBG (bvr, 3) },
247 { DEFINE_DBG (bvr, 4) },
248 { DEFINE_DBG (bvr, 5) },
249 { DEFINE_DBG (bvr, 6) },
250 { DEFINE_DBG (bvr, 7) },
251 { DEFINE_DBG (bvr, 8) },
252 { DEFINE_DBG (bvr, 9) },
253 { DEFINE_DBG (bvr, 10) },
254 { DEFINE_DBG (bvr, 11) },
255 { DEFINE_DBG (bvr, 12) },
256 { DEFINE_DBG (bvr, 13) },
257 { DEFINE_DBG (bvr, 14) },
258 { DEFINE_DBG (bvr, 15) },
260 { DEFINE_DBG (bcr, 0) },
261 { DEFINE_DBG (bcr, 1) },
262 { DEFINE_DBG (bcr, 2) },
263 { DEFINE_DBG (bcr, 3) },
264 { DEFINE_DBG (bcr, 4) },
265 { DEFINE_DBG (bcr, 5) },
266 { DEFINE_DBG (bcr, 6) },
267 { DEFINE_DBG (bcr, 7) },
268 { DEFINE_DBG (bcr, 8) },
269 { DEFINE_DBG (bcr, 9) },
270 { DEFINE_DBG (bcr, 10) },
271 { DEFINE_DBG (bcr, 11) },
272 { DEFINE_DBG (bcr, 12) },
273 { DEFINE_DBG (bcr, 13) },
274 { DEFINE_DBG (bcr, 14) },
275 { DEFINE_DBG (bcr, 15) },
277 { DEFINE_DBG (wvr, 0) },
278 { DEFINE_DBG (wvr, 1) },
279 { DEFINE_DBG (wvr, 2) },
280 { DEFINE_DBG (wvr, 3) },
281 { DEFINE_DBG (wvr, 4) },
282 { DEFINE_DBG (wvr, 5) },
283 { DEFINE_DBG (wvr, 6) },
284 { DEFINE_DBG (wvr, 7) },
285 { DEFINE_DBG (wvr, 8) },
286 { DEFINE_DBG (wvr, 9) },
287 { DEFINE_DBG (wvr, 10) },
288 { DEFINE_DBG (wvr, 11) },
289 { DEFINE_DBG (wvr, 12) },
290 { DEFINE_DBG (wvr, 13) },
291 { DEFINE_DBG (wvr, 14) },
292 { DEFINE_DBG (wvr, 15) },
294 { DEFINE_DBG (wcr, 0) },
295 { DEFINE_DBG (wcr, 1) },
296 { DEFINE_DBG (wcr, 2) },
297 { DEFINE_DBG (wcr, 3) },
298 { DEFINE_DBG (wcr, 4) },
299 { DEFINE_DBG (wcr, 5) },
300 { DEFINE_DBG (wcr, 6) },
301 { DEFINE_DBG (wcr, 7) },
302 { DEFINE_DBG (wcr, 8) },
303 { DEFINE_DBG (wcr, 9) },
304 { DEFINE_DBG (wcr, 10) },
305 { DEFINE_DBG (wcr, 11) },
306 { DEFINE_DBG (wcr, 12) },
307 { DEFINE_DBG (wcr, 13) },
308 { DEFINE_DBG (wcr, 14) },
309 { DEFINE_DBG (wcr, 15) }
312 // General purpose registers
335 // Floating point registers
374 // Exception registers
384 static size_t k_num_register_infos = llvm::array_lengthof(g_register_infos);
386 RegisterContextDarwin_arm::RegisterContextDarwin_arm(Thread &thread, uint32_t concrete_frame_idx) :
387 RegisterContext(thread, concrete_frame_idx),
393 for (i=0; i<kNumErrors; i++)
401 RegisterContextDarwin_arm::~RegisterContextDarwin_arm()
407 RegisterContextDarwin_arm::InvalidateAllRegisters ()
409 InvalidateAllRegisterStates();
414 RegisterContextDarwin_arm::GetRegisterCount ()
416 assert(k_num_register_infos == k_num_registers);
417 return k_num_registers;
421 RegisterContextDarwin_arm::GetRegisterInfoAtIndex (size_t reg)
423 assert(k_num_register_infos == k_num_registers);
424 if (reg < k_num_registers)
425 return &g_register_infos[reg];
430 RegisterContextDarwin_arm::GetRegisterInfosCount ()
432 return k_num_register_infos;
436 RegisterContextDarwin_arm::GetRegisterInfos ()
438 return g_register_infos;
442 // Number of registers in each register set
443 const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums);
444 const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums);
445 const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums);
447 //----------------------------------------------------------------------
448 // Register set definitions. The first definitions at register set index
449 // of zero is for all registers, followed by other registers sets. The
450 // register information for the all register set need not be filled in.
451 //----------------------------------------------------------------------
452 static const RegisterSet g_reg_sets[] =
454 { "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums, },
455 { "Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums },
456 { "Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums }
459 const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets);
463 RegisterContextDarwin_arm::GetRegisterSetCount ()
465 return k_num_regsets;
469 RegisterContextDarwin_arm::GetRegisterSet (size_t reg_set)
471 if (reg_set < k_num_regsets)
472 return &g_reg_sets[reg_set];
477 //----------------------------------------------------------------------
478 // Register information definitions for 32 bit i386.
479 //----------------------------------------------------------------------
481 RegisterContextDarwin_arm::GetSetForNativeRegNum (int reg)
485 else if (reg < exc_exception)
487 else if (reg < k_num_registers)
493 RegisterContextDarwin_arm::ReadGPR (bool force)
496 if (force || !RegisterSetIsCached(set))
498 SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
500 return GetError(GPRRegSet, Read);
504 RegisterContextDarwin_arm::ReadFPU (bool force)
507 if (force || !RegisterSetIsCached(set))
509 SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu));
511 return GetError(FPURegSet, Read);
515 RegisterContextDarwin_arm::ReadEXC (bool force)
518 if (force || !RegisterSetIsCached(set))
520 SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
522 return GetError(EXCRegSet, Read);
526 RegisterContextDarwin_arm::ReadDBG (bool force)
529 if (force || !RegisterSetIsCached(set))
531 SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg));
533 return GetError(DBGRegSet, Read);
537 RegisterContextDarwin_arm::WriteGPR ()
540 if (!RegisterSetIsCached(set))
542 SetError (set, Write, -1);
543 return KERN_INVALID_ARGUMENT;
545 SetError (set, Write, DoWriteGPR(GetThreadID(), set, gpr));
546 SetError (set, Read, -1);
547 return GetError(GPRRegSet, Write);
551 RegisterContextDarwin_arm::WriteFPU ()
554 if (!RegisterSetIsCached(set))
556 SetError (set, Write, -1);
557 return KERN_INVALID_ARGUMENT;
559 SetError (set, Write, DoWriteFPU(GetThreadID(), set, fpu));
560 SetError (set, Read, -1);
561 return GetError(FPURegSet, Write);
565 RegisterContextDarwin_arm::WriteEXC ()
568 if (!RegisterSetIsCached(set))
570 SetError (set, Write, -1);
571 return KERN_INVALID_ARGUMENT;
573 SetError (set, Write, DoWriteEXC(GetThreadID(), set, exc));
574 SetError (set, Read, -1);
575 return GetError(EXCRegSet, Write);
579 RegisterContextDarwin_arm::WriteDBG ()
582 if (!RegisterSetIsCached(set))
584 SetError (set, Write, -1);
585 return KERN_INVALID_ARGUMENT;
587 SetError (set, Write, DoWriteDBG(GetThreadID(), set, dbg));
588 SetError (set, Read, -1);
589 return GetError(DBGRegSet, Write);
594 RegisterContextDarwin_arm::ReadRegisterSet (uint32_t set, bool force)
598 case GPRRegSet: return ReadGPR(force);
599 case FPURegSet: return ReadFPU(force);
600 case EXCRegSet: return ReadEXC(force);
601 case DBGRegSet: return ReadDBG(force);
604 return KERN_INVALID_ARGUMENT;
608 RegisterContextDarwin_arm::WriteRegisterSet (uint32_t set)
610 // Make sure we have a valid context to set.
611 if (RegisterSetIsCached(set))
615 case GPRRegSet: return WriteGPR();
616 case FPURegSet: return WriteFPU();
617 case EXCRegSet: return WriteEXC();
618 case DBGRegSet: return WriteDBG();
622 return KERN_INVALID_ARGUMENT;
626 RegisterContextDarwin_arm::LogDBGRegisters (Log *log, const DBG& dbg)
630 for (uint32_t i=0; i<16; i++)
631 log->Printf("BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } WVR%-2u/WCR%-2u = { 0x%8.8x, 0x%8.8x }",
632 i, i, dbg.bvr[i], dbg.bcr[i],
633 i, i, dbg.wvr[i], dbg.wcr[i]);
639 RegisterContextDarwin_arm::ReadRegister (const RegisterInfo *reg_info, RegisterValue &value)
641 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
642 int set = RegisterContextDarwin_arm::GetSetForNativeRegNum (reg);
647 if (ReadRegisterSet(set, false) != KERN_SUCCESS)
669 value.SetUInt32 (gpr.r[reg - gpr_r0]);
704 value.SetUInt32 (fpu.floats.s[reg], RegisterValue::eTypeFloat);
708 value.SetUInt32 (fpu.fpscr);
712 value.SetUInt32 (exc.exception);
715 value.SetUInt32 (exc.fsr);
718 value.SetUInt32 (exc.far);
722 value.SetValueToInvalid();
731 RegisterContextDarwin_arm::WriteRegister (const RegisterInfo *reg_info,
732 const RegisterValue &value)
734 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
735 int set = GetSetForNativeRegNum (reg);
740 if (ReadRegisterSet(set, false) != KERN_SUCCESS)
762 gpr.r[reg - gpr_r0] = value.GetAsUInt32();
797 fpu.floats.s[reg] = value.GetAsUInt32();
801 fpu.fpscr = value.GetAsUInt32();
805 exc.exception = value.GetAsUInt32();
808 exc.fsr = value.GetAsUInt32();
811 exc.far = value.GetAsUInt32();
818 return WriteRegisterSet(set) == KERN_SUCCESS;
822 RegisterContextDarwin_arm::ReadAllRegisterValues (lldb::DataBufferSP &data_sp)
824 data_sp.reset (new DataBufferHeap (REG_CONTEXT_SIZE, 0));
826 ReadGPR (false) == KERN_SUCCESS &&
827 ReadFPU (false) == KERN_SUCCESS &&
828 ReadEXC (false) == KERN_SUCCESS)
830 uint8_t *dst = data_sp->GetBytes();
831 ::memcpy (dst, &gpr, sizeof(gpr));
834 ::memcpy (dst, &fpu, sizeof(fpu));
837 ::memcpy (dst, &exc, sizeof(exc));
844 RegisterContextDarwin_arm::WriteAllRegisterValues (const lldb::DataBufferSP &data_sp)
846 if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE)
848 const uint8_t *src = data_sp->GetBytes();
849 ::memcpy (&gpr, src, sizeof(gpr));
852 ::memcpy (&fpu, src, sizeof(fpu));
855 ::memcpy (&exc, src, sizeof(exc));
856 uint32_t success_count = 0;
857 if (WriteGPR() == KERN_SUCCESS)
859 if (WriteFPU() == KERN_SUCCESS)
861 if (WriteEXC() == KERN_SUCCESS)
863 return success_count == 3;
869 RegisterContextDarwin_arm::ConvertRegisterKindToRegisterNumber (lldb::RegisterKind kind, uint32_t reg)
871 if (kind == eRegisterKindGeneric)
875 case LLDB_REGNUM_GENERIC_PC: return gpr_pc;
876 case LLDB_REGNUM_GENERIC_SP: return gpr_sp;
877 case LLDB_REGNUM_GENERIC_FP: return gpr_r7;
878 case LLDB_REGNUM_GENERIC_RA: return gpr_lr;
879 case LLDB_REGNUM_GENERIC_FLAGS: return gpr_cpsr;
884 else if (kind == eRegisterKindDWARF)
888 case dwarf_r0: return gpr_r0;
889 case dwarf_r1: return gpr_r1;
890 case dwarf_r2: return gpr_r2;
891 case dwarf_r3: return gpr_r3;
892 case dwarf_r4: return gpr_r4;
893 case dwarf_r5: return gpr_r5;
894 case dwarf_r6: return gpr_r6;
895 case dwarf_r7: return gpr_r7;
896 case dwarf_r8: return gpr_r8;
897 case dwarf_r9: return gpr_r9;
898 case dwarf_r10: return gpr_r10;
899 case dwarf_r11: return gpr_r11;
900 case dwarf_r12: return gpr_r12;
901 case dwarf_sp: return gpr_sp;
902 case dwarf_lr: return gpr_lr;
903 case dwarf_pc: return gpr_pc;
904 case dwarf_spsr: return gpr_cpsr;
906 case dwarf_s0: return fpu_s0;
907 case dwarf_s1: return fpu_s1;
908 case dwarf_s2: return fpu_s2;
909 case dwarf_s3: return fpu_s3;
910 case dwarf_s4: return fpu_s4;
911 case dwarf_s5: return fpu_s5;
912 case dwarf_s6: return fpu_s6;
913 case dwarf_s7: return fpu_s7;
914 case dwarf_s8: return fpu_s8;
915 case dwarf_s9: return fpu_s9;
916 case dwarf_s10: return fpu_s10;
917 case dwarf_s11: return fpu_s11;
918 case dwarf_s12: return fpu_s12;
919 case dwarf_s13: return fpu_s13;
920 case dwarf_s14: return fpu_s14;
921 case dwarf_s15: return fpu_s15;
922 case dwarf_s16: return fpu_s16;
923 case dwarf_s17: return fpu_s17;
924 case dwarf_s18: return fpu_s18;
925 case dwarf_s19: return fpu_s19;
926 case dwarf_s20: return fpu_s20;
927 case dwarf_s21: return fpu_s21;
928 case dwarf_s22: return fpu_s22;
929 case dwarf_s23: return fpu_s23;
930 case dwarf_s24: return fpu_s24;
931 case dwarf_s25: return fpu_s25;
932 case dwarf_s26: return fpu_s26;
933 case dwarf_s27: return fpu_s27;
934 case dwarf_s28: return fpu_s28;
935 case dwarf_s29: return fpu_s29;
936 case dwarf_s30: return fpu_s30;
937 case dwarf_s31: return fpu_s31;
943 else if (kind == eRegisterKindEHFrame)
947 case ehframe_r0: return gpr_r0;
948 case ehframe_r1: return gpr_r1;
949 case ehframe_r2: return gpr_r2;
950 case ehframe_r3: return gpr_r3;
951 case ehframe_r4: return gpr_r4;
952 case ehframe_r5: return gpr_r5;
953 case ehframe_r6: return gpr_r6;
954 case ehframe_r7: return gpr_r7;
955 case ehframe_r8: return gpr_r8;
956 case ehframe_r9: return gpr_r9;
957 case ehframe_r10: return gpr_r10;
958 case ehframe_r11: return gpr_r11;
959 case ehframe_r12: return gpr_r12;
960 case ehframe_sp: return gpr_sp;
961 case ehframe_lr: return gpr_lr;
962 case ehframe_pc: return gpr_pc;
963 case ehframe_cpsr: return gpr_cpsr;
966 else if (kind == eRegisterKindLLDB)
970 return LLDB_INVALID_REGNUM;
975 RegisterContextDarwin_arm::NumSupportedHardwareBreakpoints ()
977 #if defined (__arm__)
978 // Set the init value to something that will let us know that we need to
979 // autodetect how many breakpoints are supported dynamically...
980 static uint32_t g_num_supported_hw_breakpoints = UINT32_MAX;
981 if (g_num_supported_hw_breakpoints == UINT32_MAX)
983 // Set this to zero in case we can't tell if there are any HW breakpoints
984 g_num_supported_hw_breakpoints = 0;
986 uint32_t register_DBGDIDR;
988 asm("mrc p14, 0, %0, c0, c0, 0" : "=r" (register_DBGDIDR));
989 g_num_supported_hw_breakpoints = Bits32 (register_DBGDIDR, 27, 24);
990 // Zero is reserved for the BRP count, so don't increment it if it is zero
991 if (g_num_supported_hw_breakpoints > 0)
992 g_num_supported_hw_breakpoints++;
993 // if (log) log->Printf ("DBGDIDR=0x%8.8x (number BRP pairs = %u)", register_DBGDIDR, g_num_supported_hw_breakpoints);
996 return g_num_supported_hw_breakpoints;
998 // TODO: figure out remote case here!
1004 RegisterContextDarwin_arm::SetHardwareBreakpoint (lldb::addr_t addr, size_t size)
1006 // Make sure our address isn't bogus
1008 return LLDB_INVALID_INDEX32;
1010 int kret = ReadDBG (false);
1012 if (kret == KERN_SUCCESS)
1014 const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints();
1016 for (i=0; i<num_hw_breakpoints; ++i)
1018 if ((dbg.bcr[i] & BCR_ENABLE) == 0)
1019 break; // We found an available hw breakpoint slot (in i)
1022 // See if we found an available hw breakpoint slot above
1023 if (i < num_hw_breakpoints)
1025 // Make sure bits 1:0 are clear in our address
1026 dbg.bvr[i] = addr & ~((lldb::addr_t)3);
1028 if (size == 2 || addr & 2)
1030 uint32_t byte_addr_select = (addr & 2) ? BAS_IMVA_2_3 : BAS_IMVA_0_1;
1032 // We have a thumb breakpoint
1033 // We have an ARM breakpoint
1034 dbg.bcr[i] = BCR_M_IMVA_MATCH | // Stop on address mismatch
1035 byte_addr_select | // Set the correct byte address select so we only trigger on the correct opcode
1036 S_USER | // Which modes should this breakpoint stop in?
1037 BCR_ENABLE; // Enable this hardware breakpoint
1038 // if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 0x%8.8x (Thumb)",
1048 // We have an ARM breakpoint
1049 dbg.bcr[i] = BCR_M_IMVA_MATCH | // Stop on address mismatch
1050 BAS_IMVA_ALL | // Stop on any of the four bytes following the IMVA
1051 S_USER | // Which modes should this breakpoint stop in?
1052 BCR_ENABLE; // Enable this hardware breakpoint
1053 // if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 0x%8.8x (ARM)",
1063 // if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareBreakpoint() WriteDBG() => 0x%8.8x.", kret);
1065 if (kret == KERN_SUCCESS)
1070 // if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareBreakpoint(addr = %8.8p, size = %u) => all hardware breakpoint resources are being used.", addr, size);
1074 return LLDB_INVALID_INDEX32;
1078 RegisterContextDarwin_arm::ClearHardwareBreakpoint (uint32_t hw_index)
1080 int kret = ReadDBG (false);
1082 const uint32_t num_hw_points = NumSupportedHardwareBreakpoints();
1083 if (kret == KERN_SUCCESS)
1085 if (hw_index < num_hw_points)
1087 dbg.bcr[hw_index] = 0;
1088 // if (log) log->Printf ("RegisterContextDarwin_arm::SetHardwareBreakpoint( %u ) - BVR%u = 0x%8.8x BCR%u = 0x%8.8x",
1091 // dbg.bvr[hw_index],
1093 // dbg.bcr[hw_index]);
1097 if (kret == KERN_SUCCESS)
1105 RegisterContextDarwin_arm::NumSupportedHardwareWatchpoints ()
1107 #if defined (__arm__)
1108 // Set the init value to something that will let us know that we need to
1109 // autodetect how many watchpoints are supported dynamically...
1110 static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX;
1111 if (g_num_supported_hw_watchpoints == UINT32_MAX)
1113 // Set this to zero in case we can't tell if there are any HW breakpoints
1114 g_num_supported_hw_watchpoints = 0;
1116 uint32_t register_DBGDIDR;
1117 asm("mrc p14, 0, %0, c0, c0, 0" : "=r" (register_DBGDIDR));
1118 g_num_supported_hw_watchpoints = Bits32 (register_DBGDIDR, 31, 28) + 1;
1119 // if (log) log->Printf ("DBGDIDR=0x%8.8x (number WRP pairs = %u)", register_DBGDIDR, g_num_supported_hw_watchpoints);
1121 return g_num_supported_hw_watchpoints;
1123 // TODO: figure out remote case here!
1130 RegisterContextDarwin_arm::SetHardwareWatchpoint (lldb::addr_t addr, size_t size, bool read, bool write)
1132 // if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(addr = %8.8p, size = %u, read = %u, write = %u)", addr, size, read, write);
1134 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints();
1136 // Can't watch zero bytes
1138 return LLDB_INVALID_INDEX32;
1140 // We must watch for either read or write
1141 if (read == false && write == false)
1142 return LLDB_INVALID_INDEX32;
1144 // Can't watch more than 4 bytes per WVR/WCR pair
1146 return LLDB_INVALID_INDEX32;
1148 // We can only watch up to four bytes that follow a 4 byte aligned address
1149 // per watchpoint register pair. Since we have at most so we can only watch
1150 // until the next 4 byte boundary and we need to make sure we can properly
1152 uint32_t addr_word_offset = addr % 4;
1153 // if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - addr_word_offset = 0x%8.8x", addr_word_offset);
1155 uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset;
1156 // if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - byte_mask = 0x%8.8x", byte_mask);
1157 if (byte_mask > 0xfu)
1158 return LLDB_INVALID_INDEX32;
1160 // Read the debug state
1161 int kret = ReadDBG (false);
1163 if (kret == KERN_SUCCESS)
1165 // Check to make sure we have the needed hardware support
1168 for (i=0; i<num_hw_watchpoints; ++i)
1170 if ((dbg.wcr[i] & WCR_ENABLE) == 0)
1171 break; // We found an available hw breakpoint slot (in i)
1174 // See if we found an available hw breakpoint slot above
1175 if (i < num_hw_watchpoints)
1177 // Make the byte_mask into a valid Byte Address Select mask
1178 uint32_t byte_address_select = byte_mask << 5;
1179 // Make sure bits 1:0 are clear in our address
1180 dbg.wvr[i] = addr & ~((lldb::addr_t)3);
1181 dbg.wcr[i] = byte_address_select | // Which bytes that follow the IMVA that we will watch
1182 S_USER | // Stop only in user mode
1183 (read ? WCR_LOAD : 0) | // Stop on read access?
1184 (write ? WCR_STORE : 0) | // Stop on write access?
1185 WCR_ENABLE; // Enable this watchpoint;
1188 // if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() WriteDBG() => 0x%8.8x.", kret);
1190 if (kret == KERN_SUCCESS)
1195 // if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(): All hardware resources (%u) are in use.", num_hw_watchpoints);
1198 return LLDB_INVALID_INDEX32;
1202 RegisterContextDarwin_arm::ClearHardwareWatchpoint (uint32_t hw_index)
1204 int kret = ReadDBG (false);
1206 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
1207 if (kret == KERN_SUCCESS)
1209 if (hw_index < num_hw_points)
1211 dbg.wcr[hw_index] = 0;
1212 // if (log) log->Printf ("RegisterContextDarwin_arm::ClearHardwareWatchpoint( %u ) - WVR%u = 0x%8.8x WCR%u = 0x%8.8x",
1215 // dbg.wvr[hw_index],
1217 // dbg.wcr[hw_index]);
1221 if (kret == KERN_SUCCESS)