contrib/llvm/tools/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm.cpp

   1 //===-- RegisterContextDarwin_arm.cpp ---------------------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #include "RegisterContextDarwin_arm.h"
  11 #include "RegisterContextDarwinConstants.h"
  12
  13 // C++ Includes
  14 // Other libraries and framework includes
  15 #include "lldb/Core/RegisterValue.h"
  16 #include "lldb/Core/Scalar.h"
  17 #include "lldb/Utility/DataBufferHeap.h"
  18 #include "lldb/Utility/DataExtractor.h"
  19 #include "lldb/Utility/Endian.h"
  20 #include "lldb/Utility/Log.h"
  21 #include "llvm/Support/Compiler.h"
  22
  23 #include "Plugins/Process/Utility/InstructionUtils.h"
  24
  25 // Support building against older versions of LLVM, this macro was added
  26 // recently.
  27 #ifndef LLVM_EXTENSION
  28 #define LLVM_EXTENSION
  29 #endif
  30
  31 // Project includes
  32 #include "Utility/ARM_DWARF_Registers.h"
  33 #include "Utility/ARM_ehframe_Registers.h"
  34
  35 #include "llvm/ADT/STLExtras.h"
  36
  37 using namespace lldb;
  38 using namespace lldb_private;
  39
  40 enum {
  41   gpr_r0 = 0,
  42   gpr_r1,
  43   gpr_r2,
  44   gpr_r3,
  45   gpr_r4,
  46   gpr_r5,
  47   gpr_r6,
  48   gpr_r7,
  49   gpr_r8,
  50   gpr_r9,
  51   gpr_r10,
  52   gpr_r11,
  53   gpr_r12,
  54   gpr_r13,
  55   gpr_sp = gpr_r13,
  56   gpr_r14,
  57   gpr_lr = gpr_r14,
  58   gpr_r15,
  59   gpr_pc = gpr_r15,
  60   gpr_cpsr,
  61
  62   fpu_s0,
  63   fpu_s1,
  64   fpu_s2,
  65   fpu_s3,
  66   fpu_s4,
  67   fpu_s5,
  68   fpu_s6,
  69   fpu_s7,
  70   fpu_s8,
  71   fpu_s9,
  72   fpu_s10,
  73   fpu_s11,
  74   fpu_s12,
  75   fpu_s13,
  76   fpu_s14,
  77   fpu_s15,
  78   fpu_s16,
  79   fpu_s17,
  80   fpu_s18,
  81   fpu_s19,
  82   fpu_s20,
  83   fpu_s21,
  84   fpu_s22,
  85   fpu_s23,
  86   fpu_s24,
  87   fpu_s25,
  88   fpu_s26,
  89   fpu_s27,
  90   fpu_s28,
  91   fpu_s29,
  92   fpu_s30,
  93   fpu_s31,
  94   fpu_fpscr,
  95
  96   exc_exception,
  97   exc_fsr,
  98   exc_far,
  99
 100   dbg_bvr0,
 101   dbg_bvr1,
 102   dbg_bvr2,
 103   dbg_bvr3,
 104   dbg_bvr4,
 105   dbg_bvr5,
 106   dbg_bvr6,
 107   dbg_bvr7,
 108   dbg_bvr8,
 109   dbg_bvr9,
 110   dbg_bvr10,
 111   dbg_bvr11,
 112   dbg_bvr12,
 113   dbg_bvr13,
 114   dbg_bvr14,
 115   dbg_bvr15,
 116
 117   dbg_bcr0,
 118   dbg_bcr1,
 119   dbg_bcr2,
 120   dbg_bcr3,
 121   dbg_bcr4,
 122   dbg_bcr5,
 123   dbg_bcr6,
 124   dbg_bcr7,
 125   dbg_bcr8,
 126   dbg_bcr9,
 127   dbg_bcr10,
 128   dbg_bcr11,
 129   dbg_bcr12,
 130   dbg_bcr13,
 131   dbg_bcr14,
 132   dbg_bcr15,
 133
 134   dbg_wvr0,
 135   dbg_wvr1,
 136   dbg_wvr2,
 137   dbg_wvr3,
 138   dbg_wvr4,
 139   dbg_wvr5,
 140   dbg_wvr6,
 141   dbg_wvr7,
 142   dbg_wvr8,
 143   dbg_wvr9,
 144   dbg_wvr10,
 145   dbg_wvr11,
 146   dbg_wvr12,
 147   dbg_wvr13,
 148   dbg_wvr14,
 149   dbg_wvr15,
 150
 151   dbg_wcr0,
 152   dbg_wcr1,
 153   dbg_wcr2,
 154   dbg_wcr3,
 155   dbg_wcr4,
 156   dbg_wcr5,
 157   dbg_wcr6,
 158   dbg_wcr7,
 159   dbg_wcr8,
 160   dbg_wcr9,
 161   dbg_wcr10,
 162   dbg_wcr11,
 163   dbg_wcr12,
 164   dbg_wcr13,
 165   dbg_wcr14,
 166   dbg_wcr15,
 167
 168   k_num_registers
 169 };
 170
 171 #define GPR_OFFSET(idx) ((idx)*4)
 172 #define FPU_OFFSET(idx) ((idx)*4 + sizeof(RegisterContextDarwin_arm::GPR))
 173 #define EXC_OFFSET(idx)                                                        \
 174   ((idx)*4 + sizeof(RegisterContextDarwin_arm::GPR) +                          \
 175    sizeof(RegisterContextDarwin_arm::FPU))
 176 #define DBG_OFFSET(reg)                                                        \
 177   ((LLVM_EXTENSION offsetof(RegisterContextDarwin_arm::DBG, reg) +             \
 178     sizeof(RegisterContextDarwin_arm::GPR) +                                   \
 179     sizeof(RegisterContextDarwin_arm::FPU) +                                   \
 180     sizeof(RegisterContextDarwin_arm::EXC)))
 181
 182 #define DEFINE_DBG(reg, i)                                                     \
 183   #reg, NULL, sizeof(((RegisterContextDarwin_arm::DBG *) NULL)->reg[i]),       \
 184                       DBG_OFFSET(reg[i]), eEncodingUint, eFormatHex,           \
 185                                  {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,    \
 186                                   LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,    \
 187                                   LLDB_INVALID_REGNUM },                       \
 188                                   nullptr, nullptr, nullptr, 0
 189 #define REG_CONTEXT_SIZE                                                       \
 190   (sizeof(RegisterContextDarwin_arm::GPR) +                                    \
 191    sizeof(RegisterContextDarwin_arm::FPU) +                                    \
 192    sizeof(RegisterContextDarwin_arm::EXC))
 193
 194 static RegisterInfo g_register_infos[] = {
 195     // General purpose registers
 196     //  NAME        ALT     SZ  OFFSET              ENCODING        FORMAT
 197     //  EH_FRAME                DWARF               GENERIC
 198     //  PROCESS PLUGIN          LLDB NATIVE
 199     //  ======      ======= ==  =============       =============   ============
 200     //  ===============         ===============     =========================
 201     //  =====================   =============
 202     {"r0",
 203      NULL,
 204      4,
 205      GPR_OFFSET(0),
 206      eEncodingUint,
 207      eFormatHex,
 208      {ehframe_r0, dwarf_r0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r0},
 209      nullptr,
 210      nullptr,
 211      nullptr,
 212      0},
 213     {"r1",
 214      NULL,
 215      4,
 216      GPR_OFFSET(1),
 217      eEncodingUint,
 218      eFormatHex,
 219      {ehframe_r1, dwarf_r1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r1},
 220      nullptr,
 221      nullptr,
 222      nullptr,
 223      0},
 224     {"r2",
 225      NULL,
 226      4,
 227      GPR_OFFSET(2),
 228      eEncodingUint,
 229      eFormatHex,
 230      {ehframe_r2, dwarf_r2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r2},
 231      nullptr,
 232      nullptr,
 233      nullptr,
 234      0},
 235     {"r3",
 236      NULL,
 237      4,
 238      GPR_OFFSET(3),
 239      eEncodingUint,
 240      eFormatHex,
 241      {ehframe_r3, dwarf_r3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r3},
 242      nullptr,
 243      nullptr,
 244      nullptr,
 245      0},
 246     {"r4",
 247      NULL,
 248      4,
 249      GPR_OFFSET(4),
 250      eEncodingUint,
 251      eFormatHex,
 252      {ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r4},
 253      nullptr,
 254      nullptr,
 255      nullptr,
 256      0},
 257     {"r5",
 258      NULL,
 259      4,
 260      GPR_OFFSET(5),
 261      eEncodingUint,
 262      eFormatHex,
 263      {ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r5},
 264      nullptr,
 265      nullptr,
 266      nullptr,
 267      0},
 268     {"r6",
 269      NULL,
 270      4,
 271      GPR_OFFSET(6),
 272      eEncodingUint,
 273      eFormatHex,
 274      {ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r6},
 275      nullptr,
 276      nullptr,
 277      nullptr,
 278      0},
 279     {"r7",
 280      NULL,
 281      4,
 282      GPR_OFFSET(7),
 283      eEncodingUint,
 284      eFormatHex,
 285      {ehframe_r7, dwarf_r7, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM,
 286       gpr_r7},
 287      nullptr,
 288      nullptr,
 289      nullptr,
 290      0},
 291     {"r8",
 292      NULL,
 293      4,
 294      GPR_OFFSET(8),
 295      eEncodingUint,
 296      eFormatHex,
 297      {ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r8},
 298      nullptr,
 299      nullptr,
 300      nullptr,
 301      0},
 302     {"r9",
 303      NULL,
 304      4,
 305      GPR_OFFSET(9),
 306      eEncodingUint,
 307      eFormatHex,
 308      {ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r9},
 309      nullptr,
 310      nullptr,
 311      nullptr,
 312      0},
 313     {"r10",
 314      NULL,
 315      4,
 316      GPR_OFFSET(10),
 317      eEncodingUint,
 318      eFormatHex,
 319      {ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 320       gpr_r10},
 321      nullptr,
 322      nullptr,
 323      nullptr,
 324      0},
 325     {"r11",
 326      NULL,
 327      4,
 328      GPR_OFFSET(11),
 329      eEncodingUint,
 330      eFormatHex,
 331      {ehframe_r11, dwarf_r11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 332       gpr_r11},
 333      nullptr,
 334      nullptr,
 335      nullptr,
 336      0},
 337     {"r12",
 338      NULL,
 339      4,
 340      GPR_OFFSET(12),
 341      eEncodingUint,
 342      eFormatHex,
 343      {ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 344       gpr_r12},
 345      nullptr,
 346      nullptr,
 347      nullptr,
 348      0},
 349     {"sp",
 350      "r13",
 351      4,
 352      GPR_OFFSET(13),
 353      eEncodingUint,
 354      eFormatHex,
 355      {ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM,
 356       gpr_sp},
 357      nullptr,
 358      nullptr,
 359      nullptr,
 360      0},
 361     {"lr",
 362      "r14",
 363      4,
 364      GPR_OFFSET(14),
 365      eEncodingUint,
 366      eFormatHex,
 367      {ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM,
 368       gpr_lr},
 369      nullptr,
 370      nullptr,
 371      nullptr,
 372      0},
 373     {"pc",
 374      "r15",
 375      4,
 376      GPR_OFFSET(15),
 377      eEncodingUint,
 378      eFormatHex,
 379      {ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM,
 380       gpr_pc},
 381      nullptr,
 382      nullptr,
 383      nullptr,
 384      0},
 385     {"cpsr",
 386      "psr",
 387      4,
 388      GPR_OFFSET(16),
 389      eEncodingUint,
 390      eFormatHex,
 391      {ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM,
 392       gpr_cpsr},
 393      nullptr,
 394      nullptr,
 395      nullptr,
 396      0},
 397
 398     {"s0",
 399      NULL,
 400      4,
 401      FPU_OFFSET(0),
 402      eEncodingIEEE754,
 403      eFormatFloat,
 404      {LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 405       fpu_s0},
 406      nullptr,
 407      nullptr,
 408      nullptr,
 409      0},
 410     {"s1",
 411      NULL,
 412      4,
 413      FPU_OFFSET(1),
 414      eEncodingIEEE754,
 415      eFormatFloat,
 416      {LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 417       fpu_s1},
 418      nullptr,
 419      nullptr,
 420      nullptr,
 421      0},
 422     {"s2",
 423      NULL,
 424      4,
 425      FPU_OFFSET(2),
 426      eEncodingIEEE754,
 427      eFormatFloat,
 428      {LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 429       fpu_s2},
 430      nullptr,
 431      nullptr,
 432      nullptr,
 433      0},
 434     {"s3",
 435      NULL,
 436      4,
 437      FPU_OFFSET(3),
 438      eEncodingIEEE754,
 439      eFormatFloat,
 440      {LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 441       fpu_s3},
 442      nullptr,
 443      nullptr,
 444      nullptr,
 445      0},
 446     {"s4",
 447      NULL,
 448      4,
 449      FPU_OFFSET(4),
 450      eEncodingIEEE754,
 451      eFormatFloat,
 452      {LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 453       fpu_s4},
 454      nullptr,
 455      nullptr,
 456      nullptr,
 457      0},
 458     {"s5",
 459      NULL,
 460      4,
 461      FPU_OFFSET(5),
 462      eEncodingIEEE754,
 463      eFormatFloat,
 464      {LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 465       fpu_s5},
 466      nullptr,
 467      nullptr,
 468      nullptr,
 469      0},
 470     {"s6",
 471      NULL,
 472      4,
 473      FPU_OFFSET(6),
 474      eEncodingIEEE754,
 475      eFormatFloat,
 476      {LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 477       fpu_s6},
 478      nullptr,
 479      nullptr,
 480      nullptr,
 481      0},
 482     {"s7",
 483      NULL,
 484      4,
 485      FPU_OFFSET(7),
 486      eEncodingIEEE754,
 487      eFormatFloat,
 488      {LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 489       fpu_s7},
 490      nullptr,
 491      nullptr,
 492      nullptr,
 493      0},
 494     {"s8",
 495      NULL,
 496      4,
 497      FPU_OFFSET(8),
 498      eEncodingIEEE754,
 499      eFormatFloat,
 500      {LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 501       fpu_s8},
 502      nullptr,
 503      nullptr,
 504      nullptr,
 505      0},
 506     {"s9",
 507      NULL,
 508      4,
 509      FPU_OFFSET(9),
 510      eEncodingIEEE754,
 511      eFormatFloat,
 512      {LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 513       fpu_s9},
 514      nullptr,
 515      nullptr,
 516      nullptr,
 517      0},
 518     {"s10",
 519      NULL,
 520      4,
 521      FPU_OFFSET(10),
 522      eEncodingIEEE754,
 523      eFormatFloat,
 524      {LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 525       fpu_s10},
 526      nullptr,
 527      nullptr,
 528      nullptr,
 529      0},
 530     {"s11",
 531      NULL,
 532      4,
 533      FPU_OFFSET(11),
 534      eEncodingIEEE754,
 535      eFormatFloat,
 536      {LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 537       fpu_s11},
 538      nullptr,
 539      nullptr,
 540      nullptr,
 541      0},
 542     {"s12",
 543      NULL,
 544      4,
 545      FPU_OFFSET(12),
 546      eEncodingIEEE754,
 547      eFormatFloat,
 548      {LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 549       fpu_s12},
 550      nullptr,
 551      nullptr,
 552      nullptr,
 553      0},
 554     {"s13",
 555      NULL,
 556      4,
 557      FPU_OFFSET(13),
 558      eEncodingIEEE754,
 559      eFormatFloat,
 560      {LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 561       fpu_s13},
 562      nullptr,
 563      nullptr,
 564      nullptr,
 565      0},
 566     {"s14",
 567      NULL,
 568      4,
 569      FPU_OFFSET(14),
 570      eEncodingIEEE754,
 571      eFormatFloat,
 572      {LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 573       fpu_s14},
 574      nullptr,
 575      nullptr,
 576      nullptr,
 577      0},
 578     {"s15",
 579      NULL,
 580      4,
 581      FPU_OFFSET(15),
 582      eEncodingIEEE754,
 583      eFormatFloat,
 584      {LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 585       fpu_s15},
 586      nullptr,
 587      nullptr,
 588      nullptr,
 589      0},
 590     {"s16",
 591      NULL,
 592      4,
 593      FPU_OFFSET(16),
 594      eEncodingIEEE754,
 595      eFormatFloat,
 596      {LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 597       fpu_s16},
 598      nullptr,
 599      nullptr,
 600      nullptr,
 601      0},
 602     {"s17",
 603      NULL,
 604      4,
 605      FPU_OFFSET(17),
 606      eEncodingIEEE754,
 607      eFormatFloat,
 608      {LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 609       fpu_s17},
 610      nullptr,
 611      nullptr,
 612      nullptr,
 613      0},
 614     {"s18",
 615      NULL,
 616      4,
 617      FPU_OFFSET(18),
 618      eEncodingIEEE754,
 619      eFormatFloat,
 620      {LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 621       fpu_s18},
 622      nullptr,
 623      nullptr,
 624      nullptr,
 625      0},
 626     {"s19",
 627      NULL,
 628      4,
 629      FPU_OFFSET(19),
 630      eEncodingIEEE754,
 631      eFormatFloat,
 632      {LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 633       fpu_s19},
 634      nullptr,
 635      nullptr,
 636      nullptr,
 637      0},
 638     {"s20",
 639      NULL,
 640      4,
 641      FPU_OFFSET(20),
 642      eEncodingIEEE754,
 643      eFormatFloat,
 644      {LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 645       fpu_s20},
 646      nullptr,
 647      nullptr,
 648      nullptr,
 649      0},
 650     {"s21",
 651      NULL,
 652      4,
 653      FPU_OFFSET(21),
 654      eEncodingIEEE754,
 655      eFormatFloat,
 656      {LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 657       fpu_s21},
 658      nullptr,
 659      nullptr,
 660      nullptr,
 661      0},
 662     {"s22",
 663      NULL,
 664      4,
 665      FPU_OFFSET(22),
 666      eEncodingIEEE754,
 667      eFormatFloat,
 668      {LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 669       fpu_s22},
 670      nullptr,
 671      nullptr,
 672      nullptr,
 673      0},
 674     {"s23",
 675      NULL,
 676      4,
 677      FPU_OFFSET(23),
 678      eEncodingIEEE754,
 679      eFormatFloat,
 680      {LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 681       fpu_s23},
 682      nullptr,
 683      nullptr,
 684      nullptr,
 685      0},
 686     {"s24",
 687      NULL,
 688      4,
 689      FPU_OFFSET(24),
 690      eEncodingIEEE754,
 691      eFormatFloat,
 692      {LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 693       fpu_s24},
 694      nullptr,
 695      nullptr,
 696      nullptr,
 697      0},
 698     {"s25",
 699      NULL,
 700      4,
 701      FPU_OFFSET(25),
 702      eEncodingIEEE754,
 703      eFormatFloat,
 704      {LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 705       fpu_s25},
 706      nullptr,
 707      nullptr,
 708      nullptr,
 709      0},
 710     {"s26",
 711      NULL,
 712      4,
 713      FPU_OFFSET(26),
 714      eEncodingIEEE754,
 715      eFormatFloat,
 716      {LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 717       fpu_s26},
 718      nullptr,
 719      nullptr,
 720      nullptr,
 721      0},
 722     {"s27",
 723      NULL,
 724      4,
 725      FPU_OFFSET(27),
 726      eEncodingIEEE754,
 727      eFormatFloat,
 728      {LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 729       fpu_s27},
 730      nullptr,
 731      nullptr,
 732      nullptr,
 733      0},
 734     {"s28",
 735      NULL,
 736      4,
 737      FPU_OFFSET(28),
 738      eEncodingIEEE754,
 739      eFormatFloat,
 740      {LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 741       fpu_s28},
 742      nullptr,
 743      nullptr,
 744      nullptr,
 745      0},
 746     {"s29",
 747      NULL,
 748      4,
 749      FPU_OFFSET(29),
 750      eEncodingIEEE754,
 751      eFormatFloat,
 752      {LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 753       fpu_s29},
 754      nullptr,
 755      nullptr,
 756      nullptr,
 757      0},
 758     {"s30",
 759      NULL,
 760      4,
 761      FPU_OFFSET(30),
 762      eEncodingIEEE754,
 763      eFormatFloat,
 764      {LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 765       fpu_s30},
 766      nullptr,
 767      nullptr,
 768      nullptr,
 769      0},
 770     {"s31",
 771      NULL,
 772      4,
 773      FPU_OFFSET(31),
 774      eEncodingIEEE754,
 775      eFormatFloat,
 776      {LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 777       fpu_s31},
 778      nullptr,
 779      nullptr,
 780      nullptr,
 781      0},
 782     {"fpscr",
 783      NULL,
 784      4,
 785      FPU_OFFSET(32),
 786      eEncodingUint,
 787      eFormatHex,
 788      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 789       LLDB_INVALID_REGNUM, fpu_fpscr},
 790      nullptr,
 791      nullptr,
 792      nullptr,
 793      0},
 794
 795     {"exception",
 796      NULL,
 797      4,
 798      EXC_OFFSET(0),
 799      eEncodingUint,
 800      eFormatHex,
 801      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 802       LLDB_INVALID_REGNUM, exc_exception},
 803      nullptr,
 804      nullptr,
 805      nullptr,
 806      0},
 807     {"fsr",
 808      NULL,
 809      4,
 810      EXC_OFFSET(1),
 811      eEncodingUint,
 812      eFormatHex,
 813      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 814       LLDB_INVALID_REGNUM, exc_fsr},
 815      nullptr,
 816      nullptr,
 817      nullptr,
 818      0},
 819     {"far",
 820      NULL,
 821      4,
 822      EXC_OFFSET(2),
 823      eEncodingUint,
 824      eFormatHex,
 825      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 826       LLDB_INVALID_REGNUM, exc_far},
 827      nullptr,
 828      nullptr,
 829      nullptr,
 830      0},
 831
 832     {DEFINE_DBG(bvr, 0)},
 833     {DEFINE_DBG(bvr, 1)},
 834     {DEFINE_DBG(bvr, 2)},
 835     {DEFINE_DBG(bvr, 3)},
 836     {DEFINE_DBG(bvr, 4)},
 837     {DEFINE_DBG(bvr, 5)},
 838     {DEFINE_DBG(bvr, 6)},
 839     {DEFINE_DBG(bvr, 7)},
 840     {DEFINE_DBG(bvr, 8)},
 841     {DEFINE_DBG(bvr, 9)},
 842     {DEFINE_DBG(bvr, 10)},
 843     {DEFINE_DBG(bvr, 11)},
 844     {DEFINE_DBG(bvr, 12)},
 845     {DEFINE_DBG(bvr, 13)},
 846     {DEFINE_DBG(bvr, 14)},
 847     {DEFINE_DBG(bvr, 15)},
 848
 849     {DEFINE_DBG(bcr, 0)},
 850     {DEFINE_DBG(bcr, 1)},
 851     {DEFINE_DBG(bcr, 2)},
 852     {DEFINE_DBG(bcr, 3)},
 853     {DEFINE_DBG(bcr, 4)},
 854     {DEFINE_DBG(bcr, 5)},
 855     {DEFINE_DBG(bcr, 6)},
 856     {DEFINE_DBG(bcr, 7)},
 857     {DEFINE_DBG(bcr, 8)},
 858     {DEFINE_DBG(bcr, 9)},
 859     {DEFINE_DBG(bcr, 10)},
 860     {DEFINE_DBG(bcr, 11)},
 861     {DEFINE_DBG(bcr, 12)},
 862     {DEFINE_DBG(bcr, 13)},
 863     {DEFINE_DBG(bcr, 14)},
 864     {DEFINE_DBG(bcr, 15)},
 865
 866     {DEFINE_DBG(wvr, 0)},
 867     {DEFINE_DBG(wvr, 1)},
 868     {DEFINE_DBG(wvr, 2)},
 869     {DEFINE_DBG(wvr, 3)},
 870     {DEFINE_DBG(wvr, 4)},
 871     {DEFINE_DBG(wvr, 5)},
 872     {DEFINE_DBG(wvr, 6)},
 873     {DEFINE_DBG(wvr, 7)},
 874     {DEFINE_DBG(wvr, 8)},
 875     {DEFINE_DBG(wvr, 9)},
 876     {DEFINE_DBG(wvr, 10)},
 877     {DEFINE_DBG(wvr, 11)},
 878     {DEFINE_DBG(wvr, 12)},
 879     {DEFINE_DBG(wvr, 13)},
 880     {DEFINE_DBG(wvr, 14)},
 881     {DEFINE_DBG(wvr, 15)},
 882
 883     {DEFINE_DBG(wcr, 0)},
 884     {DEFINE_DBG(wcr, 1)},
 885     {DEFINE_DBG(wcr, 2)},
 886     {DEFINE_DBG(wcr, 3)},
 887     {DEFINE_DBG(wcr, 4)},
 888     {DEFINE_DBG(wcr, 5)},
 889     {DEFINE_DBG(wcr, 6)},
 890     {DEFINE_DBG(wcr, 7)},
 891     {DEFINE_DBG(wcr, 8)},
 892     {DEFINE_DBG(wcr, 9)},
 893     {DEFINE_DBG(wcr, 10)},
 894     {DEFINE_DBG(wcr, 11)},
 895     {DEFINE_DBG(wcr, 12)},
 896     {DEFINE_DBG(wcr, 13)},
 897     {DEFINE_DBG(wcr, 14)},
 898     {DEFINE_DBG(wcr, 15)}};
 899
 900 // General purpose registers
 901 static uint32_t g_gpr_regnums[] = {
 902     gpr_r0, gpr_r1,  gpr_r2,  gpr_r3,  gpr_r4, gpr_r5, gpr_r6, gpr_r7,  gpr_r8,
 903     gpr_r9, gpr_r10, gpr_r11, gpr_r12, gpr_sp, gpr_lr, gpr_pc, gpr_cpsr};
 904
 905 // Floating point registers
 906 static uint32_t g_fpu_regnums[] = {
 907     fpu_s0,  fpu_s1,  fpu_s2,  fpu_s3,  fpu_s4,    fpu_s5,  fpu_s6,
 908     fpu_s7,  fpu_s8,  fpu_s9,  fpu_s10, fpu_s11,   fpu_s12, fpu_s13,
 909     fpu_s14, fpu_s15, fpu_s16, fpu_s17, fpu_s18,   fpu_s19, fpu_s20,
 910     fpu_s21, fpu_s22, fpu_s23, fpu_s24, fpu_s25,   fpu_s26, fpu_s27,
 911     fpu_s28, fpu_s29, fpu_s30, fpu_s31, fpu_fpscr,
 912 };
 913
 914 // Exception registers
 915
 916 static uint32_t g_exc_regnums[] = {
 917     exc_exception, exc_fsr, exc_far,
 918 };
 919
 920 static size_t k_num_register_infos = llvm::array_lengthof(g_register_infos);
 921
 922 RegisterContextDarwin_arm::RegisterContextDarwin_arm(
 923     Thread &thread, uint32_t concrete_frame_idx)
 924     : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() {
 925   uint32_t i;
 926   for (i = 0; i < kNumErrors; i++) {
 927     gpr_errs[i] = -1;
 928     fpu_errs[i] = -1;
 929     exc_errs[i] = -1;
 930   }
 931 }
 932
 933 RegisterContextDarwin_arm::~RegisterContextDarwin_arm() {}
 934
 935 void RegisterContextDarwin_arm::InvalidateAllRegisters() {
 936   InvalidateAllRegisterStates();
 937 }
 938
 939 size_t RegisterContextDarwin_arm::GetRegisterCount() {
 940   assert(k_num_register_infos == k_num_registers);
 941   return k_num_registers;
 942 }
 943
 944 const RegisterInfo *
 945 RegisterContextDarwin_arm::GetRegisterInfoAtIndex(size_t reg) {
 946   assert(k_num_register_infos == k_num_registers);
 947   if (reg < k_num_registers)
 948     return &g_register_infos[reg];
 949   return NULL;
 950 }
 951
 952 size_t RegisterContextDarwin_arm::GetRegisterInfosCount() {
 953   return k_num_register_infos;
 954 }
 955
 956 const RegisterInfo *RegisterContextDarwin_arm::GetRegisterInfos() {
 957   return g_register_infos;
 958 }
 959
 960 // Number of registers in each register set
 961 const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums);
 962 const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums);
 963 const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums);
 964
 965 //----------------------------------------------------------------------
 966 // Register set definitions. The first definitions at register set index of
 967 // zero is for all registers, followed by other registers sets. The register
 968 // information for the all register set need not be filled in.
 969 //----------------------------------------------------------------------
 970 static const RegisterSet g_reg_sets[] = {
 971     {
 972         "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums,
 973     },
 974     {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums},
 975     {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}};
 976
 977 const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets);
 978
 979 size_t RegisterContextDarwin_arm::GetRegisterSetCount() {
 980   return k_num_regsets;
 981 }
 982
 983 const RegisterSet *RegisterContextDarwin_arm::GetRegisterSet(size_t reg_set) {
 984   if (reg_set < k_num_regsets)
 985     return &g_reg_sets[reg_set];
 986   return NULL;
 987 }
 988
 989 //----------------------------------------------------------------------
 990 // Register information definitions for 32 bit i386.
 991 //----------------------------------------------------------------------
 992 int RegisterContextDarwin_arm::GetSetForNativeRegNum(int reg) {
 993   if (reg < fpu_s0)
 994     return GPRRegSet;
 995   else if (reg < exc_exception)
 996     return FPURegSet;
 997   else if (reg < k_num_registers)
 998     return EXCRegSet;
 999   return -1;
1000 }
1001
1002 int RegisterContextDarwin_arm::ReadGPR(bool force) {
1003   int set = GPRRegSet;
1004   if (force || !RegisterSetIsCached(set)) {
1005     SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
1006   }
1007   return GetError(GPRRegSet, Read);
1008 }
1009
1010 int RegisterContextDarwin_arm::ReadFPU(bool force) {
1011   int set = FPURegSet;
1012   if (force || !RegisterSetIsCached(set)) {
1013     SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu));
1014   }
1015   return GetError(FPURegSet, Read);
1016 }
1017
1018 int RegisterContextDarwin_arm::ReadEXC(bool force) {
1019   int set = EXCRegSet;
1020   if (force || !RegisterSetIsCached(set)) {
1021     SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
1022   }
1023   return GetError(EXCRegSet, Read);
1024 }
1025
1026 int RegisterContextDarwin_arm::ReadDBG(bool force) {
1027   int set = DBGRegSet;
1028   if (force || !RegisterSetIsCached(set)) {
1029     SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg));
1030   }
1031   return GetError(DBGRegSet, Read);
1032 }
1033
1034 int RegisterContextDarwin_arm::WriteGPR() {
1035   int set = GPRRegSet;
1036   if (!RegisterSetIsCached(set)) {
1037     SetError(set, Write, -1);
1038     return KERN_INVALID_ARGUMENT;
1039   }
1040   SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr));
1041   SetError(set, Read, -1);
1042   return GetError(GPRRegSet, Write);
1043 }
1044
1045 int RegisterContextDarwin_arm::WriteFPU() {
1046   int set = FPURegSet;
1047   if (!RegisterSetIsCached(set)) {
1048     SetError(set, Write, -1);
1049     return KERN_INVALID_ARGUMENT;
1050   }
1051   SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu));
1052   SetError(set, Read, -1);
1053   return GetError(FPURegSet, Write);
1054 }
1055
1056 int RegisterContextDarwin_arm::WriteEXC() {
1057   int set = EXCRegSet;
1058   if (!RegisterSetIsCached(set)) {
1059     SetError(set, Write, -1);
1060     return KERN_INVALID_ARGUMENT;
1061   }
1062   SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc));
1063   SetError(set, Read, -1);
1064   return GetError(EXCRegSet, Write);
1065 }
1066
1067 int RegisterContextDarwin_arm::WriteDBG() {
1068   int set = DBGRegSet;
1069   if (!RegisterSetIsCached(set)) {
1070     SetError(set, Write, -1);
1071     return KERN_INVALID_ARGUMENT;
1072   }
1073   SetError(set, Write, DoWriteDBG(GetThreadID(), set, dbg));
1074   SetError(set, Read, -1);
1075   return GetError(DBGRegSet, Write);
1076 }
1077
1078 int RegisterContextDarwin_arm::ReadRegisterSet(uint32_t set, bool force) {
1079   switch (set) {
1080   case GPRRegSet:
1081     return ReadGPR(force);
1082   case GPRAltRegSet:
1083     return ReadGPR(force);
1084   case FPURegSet:
1085     return ReadFPU(force);
1086   case EXCRegSet:
1087     return ReadEXC(force);
1088   case DBGRegSet:
1089     return ReadDBG(force);
1090   default:
1091     break;
1092   }
1093   return KERN_INVALID_ARGUMENT;
1094 }
1095
1096 int RegisterContextDarwin_arm::WriteRegisterSet(uint32_t set) {
1097   // Make sure we have a valid context to set.
1098   if (RegisterSetIsCached(set)) {
1099     switch (set) {
1100     case GPRRegSet:
1101       return WriteGPR();
1102     case GPRAltRegSet:
1103       return WriteGPR();
1104     case FPURegSet:
1105       return WriteFPU();
1106     case EXCRegSet:
1107       return WriteEXC();
1108     case DBGRegSet:
1109       return WriteDBG();
1110     default:
1111       break;
1112     }
1113   }
1114   return KERN_INVALID_ARGUMENT;
1115 }
1116
1117 void RegisterContextDarwin_arm::LogDBGRegisters(Log *log, const DBG &dbg) {
1118   if (log) {
1119     for (uint32_t i = 0; i < 16; i++)
1120       log->Printf("BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } WVR%-2u/WCR%-2u = { "
1121                   "0x%8.8x, 0x%8.8x }",
1122                   i, i, dbg.bvr[i], dbg.bcr[i], i, i, dbg.wvr[i], dbg.wcr[i]);
1123   }
1124 }
1125
1126 bool RegisterContextDarwin_arm::ReadRegister(const RegisterInfo *reg_info,
1127                                              RegisterValue &value) {
1128   const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
1129   int set = RegisterContextDarwin_arm::GetSetForNativeRegNum(reg);
1130
1131   if (set == -1)
1132     return false;
1133
1134   if (ReadRegisterSet(set, false) != KERN_SUCCESS)
1135     return false;
1136
1137   switch (reg) {
1138   case gpr_r0:
1139   case gpr_r1:
1140   case gpr_r2:
1141   case gpr_r3:
1142   case gpr_r4:
1143   case gpr_r5:
1144   case gpr_r6:
1145   case gpr_r7:
1146   case gpr_r8:
1147   case gpr_r9:
1148   case gpr_r10:
1149   case gpr_r11:
1150   case gpr_r12:
1151   case gpr_sp:
1152   case gpr_lr:
1153   case gpr_pc:
1154   case gpr_cpsr:
1155     value.SetUInt32(gpr.r[reg - gpr_r0]);
1156     break;
1157
1158   case fpu_s0:
1159   case fpu_s1:
1160   case fpu_s2:
1161   case fpu_s3:
1162   case fpu_s4:
1163   case fpu_s5:
1164   case fpu_s6:
1165   case fpu_s7:
1166   case fpu_s8:
1167   case fpu_s9:
1168   case fpu_s10:
1169   case fpu_s11:
1170   case fpu_s12:
1171   case fpu_s13:
1172   case fpu_s14:
1173   case fpu_s15:
1174   case fpu_s16:
1175   case fpu_s17:
1176   case fpu_s18:
1177   case fpu_s19:
1178   case fpu_s20:
1179   case fpu_s21:
1180   case fpu_s22:
1181   case fpu_s23:
1182   case fpu_s24:
1183   case fpu_s25:
1184   case fpu_s26:
1185   case fpu_s27:
1186   case fpu_s28:
1187   case fpu_s29:
1188   case fpu_s30:
1189   case fpu_s31:
1190     value.SetUInt32(fpu.floats.s[reg], RegisterValue::eTypeFloat);
1191     break;
1192
1193   case fpu_fpscr:
1194     value.SetUInt32(fpu.fpscr);
1195     break;
1196
1197   case exc_exception:
1198     value.SetUInt32(exc.exception);
1199     break;
1200   case exc_fsr:
1201     value.SetUInt32(exc.fsr);
1202     break;
1203   case exc_far:
1204     value.SetUInt32(exc.far);
1205     break;
1206
1207   default:
1208     value.SetValueToInvalid();
1209     return false;
1210   }
1211   return true;
1212 }
1213
1214 bool RegisterContextDarwin_arm::WriteRegister(const RegisterInfo *reg_info,
1215                                               const RegisterValue &value) {
1216   const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
1217   int set = GetSetForNativeRegNum(reg);
1218
1219   if (set == -1)
1220     return false;
1221
1222   if (ReadRegisterSet(set, false) != KERN_SUCCESS)
1223     return false;
1224
1225   switch (reg) {
1226   case gpr_r0:
1227   case gpr_r1:
1228   case gpr_r2:
1229   case gpr_r3:
1230   case gpr_r4:
1231   case gpr_r5:
1232   case gpr_r6:
1233   case gpr_r7:
1234   case gpr_r8:
1235   case gpr_r9:
1236   case gpr_r10:
1237   case gpr_r11:
1238   case gpr_r12:
1239   case gpr_sp:
1240   case gpr_lr:
1241   case gpr_pc:
1242   case gpr_cpsr:
1243     gpr.r[reg - gpr_r0] = value.GetAsUInt32();
1244     break;
1245
1246   case fpu_s0:
1247   case fpu_s1:
1248   case fpu_s2:
1249   case fpu_s3:
1250   case fpu_s4:
1251   case fpu_s5:
1252   case fpu_s6:
1253   case fpu_s7:
1254   case fpu_s8:
1255   case fpu_s9:
1256   case fpu_s10:
1257   case fpu_s11:
1258   case fpu_s12:
1259   case fpu_s13:
1260   case fpu_s14:
1261   case fpu_s15:
1262   case fpu_s16:
1263   case fpu_s17:
1264   case fpu_s18:
1265   case fpu_s19:
1266   case fpu_s20:
1267   case fpu_s21:
1268   case fpu_s22:
1269   case fpu_s23:
1270   case fpu_s24:
1271   case fpu_s25:
1272   case fpu_s26:
1273   case fpu_s27:
1274   case fpu_s28:
1275   case fpu_s29:
1276   case fpu_s30:
1277   case fpu_s31:
1278     fpu.floats.s[reg] = value.GetAsUInt32();
1279     break;
1280
1281   case fpu_fpscr:
1282     fpu.fpscr = value.GetAsUInt32();
1283     break;
1284
1285   case exc_exception:
1286     exc.exception = value.GetAsUInt32();
1287     break;
1288   case exc_fsr:
1289     exc.fsr = value.GetAsUInt32();
1290     break;
1291   case exc_far:
1292     exc.far = value.GetAsUInt32();
1293     break;
1294
1295   default:
1296     return false;
1297   }
1298   return WriteRegisterSet(set) == KERN_SUCCESS;
1299 }
1300
1301 bool RegisterContextDarwin_arm::ReadAllRegisterValues(
1302     lldb::DataBufferSP &data_sp) {
1303   data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0));
1304   if (data_sp && ReadGPR(false) == KERN_SUCCESS &&
1305       ReadFPU(false) == KERN_SUCCESS && ReadEXC(false) == KERN_SUCCESS) {
1306     uint8_t *dst = data_sp->GetBytes();
1307     ::memcpy(dst, &gpr, sizeof(gpr));
1308     dst += sizeof(gpr);
1309
1310     ::memcpy(dst, &fpu, sizeof(fpu));
1311     dst += sizeof(gpr);
1312
1313     ::memcpy(dst, &exc, sizeof(exc));
1314     return true;
1315   }
1316   return false;
1317 }
1318
1319 bool RegisterContextDarwin_arm::WriteAllRegisterValues(
1320     const lldb::DataBufferSP &data_sp) {
1321   if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) {
1322     const uint8_t *src = data_sp->GetBytes();
1323     ::memcpy(&gpr, src, sizeof(gpr));
1324     src += sizeof(gpr);
1325
1326     ::memcpy(&fpu, src, sizeof(fpu));
1327     src += sizeof(gpr);
1328
1329     ::memcpy(&exc, src, sizeof(exc));
1330     uint32_t success_count = 0;
1331     if (WriteGPR() == KERN_SUCCESS)
1332       ++success_count;
1333     if (WriteFPU() == KERN_SUCCESS)
1334       ++success_count;
1335     if (WriteEXC() == KERN_SUCCESS)
1336       ++success_count;
1337     return success_count == 3;
1338   }
1339   return false;
1340 }
1341
1342 uint32_t RegisterContextDarwin_arm::ConvertRegisterKindToRegisterNumber(
1343     lldb::RegisterKind kind, uint32_t reg) {
1344   if (kind == eRegisterKindGeneric) {
1345     switch (reg) {
1346     case LLDB_REGNUM_GENERIC_PC:
1347       return gpr_pc;
1348     case LLDB_REGNUM_GENERIC_SP:
1349       return gpr_sp;
1350     case LLDB_REGNUM_GENERIC_FP:
1351       return gpr_r7;
1352     case LLDB_REGNUM_GENERIC_RA:
1353       return gpr_lr;
1354     case LLDB_REGNUM_GENERIC_FLAGS:
1355       return gpr_cpsr;
1356     default:
1357       break;
1358     }
1359   } else if (kind == eRegisterKindDWARF) {
1360     switch (reg) {
1361     case dwarf_r0:
1362       return gpr_r0;
1363     case dwarf_r1:
1364       return gpr_r1;
1365     case dwarf_r2:
1366       return gpr_r2;
1367     case dwarf_r3:
1368       return gpr_r3;
1369     case dwarf_r4:
1370       return gpr_r4;
1371     case dwarf_r5:
1372       return gpr_r5;
1373     case dwarf_r6:
1374       return gpr_r6;
1375     case dwarf_r7:
1376       return gpr_r7;
1377     case dwarf_r8:
1378       return gpr_r8;
1379     case dwarf_r9:
1380       return gpr_r9;
1381     case dwarf_r10:
1382       return gpr_r10;
1383     case dwarf_r11:
1384       return gpr_r11;
1385     case dwarf_r12:
1386       return gpr_r12;
1387     case dwarf_sp:
1388       return gpr_sp;
1389     case dwarf_lr:
1390       return gpr_lr;
1391     case dwarf_pc:
1392       return gpr_pc;
1393     case dwarf_spsr:
1394       return gpr_cpsr;
1395
1396     case dwarf_s0:
1397       return fpu_s0;
1398     case dwarf_s1:
1399       return fpu_s1;
1400     case dwarf_s2:
1401       return fpu_s2;
1402     case dwarf_s3:
1403       return fpu_s3;
1404     case dwarf_s4:
1405       return fpu_s4;
1406     case dwarf_s5:
1407       return fpu_s5;
1408     case dwarf_s6:
1409       return fpu_s6;
1410     case dwarf_s7:
1411       return fpu_s7;
1412     case dwarf_s8:
1413       return fpu_s8;
1414     case dwarf_s9:
1415       return fpu_s9;
1416     case dwarf_s10:
1417       return fpu_s10;
1418     case dwarf_s11:
1419       return fpu_s11;
1420     case dwarf_s12:
1421       return fpu_s12;
1422     case dwarf_s13:
1423       return fpu_s13;
1424     case dwarf_s14:
1425       return fpu_s14;
1426     case dwarf_s15:
1427       return fpu_s15;
1428     case dwarf_s16:
1429       return fpu_s16;
1430     case dwarf_s17:
1431       return fpu_s17;
1432     case dwarf_s18:
1433       return fpu_s18;
1434     case dwarf_s19:
1435       return fpu_s19;
1436     case dwarf_s20:
1437       return fpu_s20;
1438     case dwarf_s21:
1439       return fpu_s21;
1440     case dwarf_s22:
1441       return fpu_s22;
1442     case dwarf_s23:
1443       return fpu_s23;
1444     case dwarf_s24:
1445       return fpu_s24;
1446     case dwarf_s25:
1447       return fpu_s25;
1448     case dwarf_s26:
1449       return fpu_s26;
1450     case dwarf_s27:
1451       return fpu_s27;
1452     case dwarf_s28:
1453       return fpu_s28;
1454     case dwarf_s29:
1455       return fpu_s29;
1456     case dwarf_s30:
1457       return fpu_s30;
1458     case dwarf_s31:
1459       return fpu_s31;
1460
1461     default:
1462       break;
1463     }
1464   } else if (kind == eRegisterKindEHFrame) {
1465     switch (reg) {
1466     case ehframe_r0:
1467       return gpr_r0;
1468     case ehframe_r1:
1469       return gpr_r1;
1470     case ehframe_r2:
1471       return gpr_r2;
1472     case ehframe_r3:
1473       return gpr_r3;
1474     case ehframe_r4:
1475       return gpr_r4;
1476     case ehframe_r5:
1477       return gpr_r5;
1478     case ehframe_r6:
1479       return gpr_r6;
1480     case ehframe_r7:
1481       return gpr_r7;
1482     case ehframe_r8:
1483       return gpr_r8;
1484     case ehframe_r9:
1485       return gpr_r9;
1486     case ehframe_r10:
1487       return gpr_r10;
1488     case ehframe_r11:
1489       return gpr_r11;
1490     case ehframe_r12:
1491       return gpr_r12;
1492     case ehframe_sp:
1493       return gpr_sp;
1494     case ehframe_lr:
1495       return gpr_lr;
1496     case ehframe_pc:
1497       return gpr_pc;
1498     case ehframe_cpsr:
1499       return gpr_cpsr;
1500     }
1501   } else if (kind == eRegisterKindLLDB) {
1502     return reg;
1503   }
1504   return LLDB_INVALID_REGNUM;
1505 }
1506
1507 uint32_t RegisterContextDarwin_arm::NumSupportedHardwareBreakpoints() {
1508 #if defined(__APPLE__) && defined(__arm__)
1509   // Set the init value to something that will let us know that we need to
1510   // autodetect how many breakpoints are supported dynamically...
1511   static uint32_t g_num_supported_hw_breakpoints = UINT32_MAX;
1512   if (g_num_supported_hw_breakpoints == UINT32_MAX) {
1513     // Set this to zero in case we can't tell if there are any HW breakpoints
1514     g_num_supported_hw_breakpoints = 0;
1515
1516     uint32_t register_DBGDIDR;
1517
1518     asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR));
1519     g_num_supported_hw_breakpoints = Bits32(register_DBGDIDR, 27, 24);
1520     // Zero is reserved for the BRP count, so don't increment it if it is zero
1521     if (g_num_supported_hw_breakpoints > 0)
1522       g_num_supported_hw_breakpoints++;
1523     //        if (log) log->Printf ("DBGDIDR=0x%8.8x (number BRP pairs = %u)",
1524     //        register_DBGDIDR, g_num_supported_hw_breakpoints);
1525   }
1526   return g_num_supported_hw_breakpoints;
1527 #else
1528   // TODO: figure out remote case here!
1529   return 6;
1530 #endif
1531 }
1532
1533 uint32_t RegisterContextDarwin_arm::SetHardwareBreakpoint(lldb::addr_t addr,
1534                                                           size_t size) {
1535   // Make sure our address isn't bogus
1536   if (addr & 1)
1537     return LLDB_INVALID_INDEX32;
1538
1539   int kret = ReadDBG(false);
1540
1541   if (kret == KERN_SUCCESS) {
1542     const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints();
1543     uint32_t i;
1544     for (i = 0; i < num_hw_breakpoints; ++i) {
1545       if ((dbg.bcr[i] & BCR_ENABLE) == 0)
1546         break; // We found an available hw breakpoint slot (in i)
1547     }
1548
1549     // See if we found an available hw breakpoint slot above
1550     if (i < num_hw_breakpoints) {
1551       // Make sure bits 1:0 are clear in our address
1552       dbg.bvr[i] = addr & ~((lldb::addr_t)3);
1553
1554       if (size == 2 || addr & 2) {
1555         uint32_t byte_addr_select = (addr & 2) ? BAS_IMVA_2_3 : BAS_IMVA_0_1;
1556
1557         // We have a thumb breakpoint
1558         // We have an ARM breakpoint
1559         dbg.bcr[i] = BCR_M_IMVA_MATCH | // Stop on address mismatch
1560                      byte_addr_select | // Set the correct byte address select
1561                                         // so we only trigger on the correct
1562                                         // opcode
1563                      S_USER |    // Which modes should this breakpoint stop in?
1564                      BCR_ENABLE; // Enable this hardware breakpoint
1565                                  //                if (log) log->Printf
1566         //                ("RegisterContextDarwin_arm::EnableHardwareBreakpoint(
1567         //                addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x /
1568         //                0x%8.8x (Thumb)",
1569         //                        addr,
1570         //                        size,
1571         //                        i,
1572         //                        i,
1573         //                        dbg.bvr[i],
1574         //                        dbg.bcr[i]);
1575       } else if (size == 4) {
1576         // We have an ARM breakpoint
1577         dbg.bcr[i] =
1578             BCR_M_IMVA_MATCH | // Stop on address mismatch
1579             BAS_IMVA_ALL | // Stop on any of the four bytes following the IMVA
1580             S_USER |       // Which modes should this breakpoint stop in?
1581             BCR_ENABLE;    // Enable this hardware breakpoint
1582                            //                if (log) log->Printf
1583         //                ("RegisterContextDarwin_arm::EnableHardwareBreakpoint(
1584         //                addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x /
1585         //                0x%8.8x (ARM)",
1586         //                        addr,
1587         //                        size,
1588         //                        i,
1589         //                        i,
1590         //                        dbg.bvr[i],
1591         //                        dbg.bcr[i]);
1592       }
1593
1594       kret = WriteDBG();
1595       //            if (log) log->Printf
1596       //            ("RegisterContextDarwin_arm::EnableHardwareBreakpoint()
1597       //            WriteDBG() => 0x%8.8x.", kret);
1598
1599       if (kret == KERN_SUCCESS)
1600         return i;
1601     }
1602     //        else
1603     //        {
1604     //            if (log) log->Printf
1605     //            ("RegisterContextDarwin_arm::EnableHardwareBreakpoint(addr =
1606     //            %8.8p, size = %u) => all hardware breakpoint resources are
1607     //            being used.", addr, size);
1608     //        }
1609   }
1610
1611   return LLDB_INVALID_INDEX32;
1612 }
1613
1614 bool RegisterContextDarwin_arm::ClearHardwareBreakpoint(uint32_t hw_index) {
1615   int kret = ReadDBG(false);
1616
1617   const uint32_t num_hw_points = NumSupportedHardwareBreakpoints();
1618   if (kret == KERN_SUCCESS) {
1619     if (hw_index < num_hw_points) {
1620       dbg.bcr[hw_index] = 0;
1621       //            if (log) log->Printf
1622       //            ("RegisterContextDarwin_arm::SetHardwareBreakpoint( %u ) -
1623       //            BVR%u = 0x%8.8x  BCR%u = 0x%8.8x",
1624       //                    hw_index,
1625       //                    hw_index,
1626       //                    dbg.bvr[hw_index],
1627       //                    hw_index,
1628       //                    dbg.bcr[hw_index]);
1629
1630       kret = WriteDBG();
1631
1632       if (kret == KERN_SUCCESS)
1633         return true;
1634     }
1635   }
1636   return false;
1637 }
1638
1639 uint32_t RegisterContextDarwin_arm::NumSupportedHardwareWatchpoints() {
1640 #if defined(__APPLE__) && defined(__arm__)
1641   // Set the init value to something that will let us know that we need to
1642   // autodetect how many watchpoints are supported dynamically...
1643   static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX;
1644   if (g_num_supported_hw_watchpoints == UINT32_MAX) {
1645     // Set this to zero in case we can't tell if there are any HW breakpoints
1646     g_num_supported_hw_watchpoints = 0;
1647
1648     uint32_t register_DBGDIDR;
1649     asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR));
1650     g_num_supported_hw_watchpoints = Bits32(register_DBGDIDR, 31, 28) + 1;
1651     //        if (log) log->Printf ("DBGDIDR=0x%8.8x (number WRP pairs = %u)",
1652     //        register_DBGDIDR, g_num_supported_hw_watchpoints);
1653   }
1654   return g_num_supported_hw_watchpoints;
1655 #else
1656   // TODO: figure out remote case here!
1657   return 2;
1658 #endif
1659 }
1660
1661 uint32_t RegisterContextDarwin_arm::SetHardwareWatchpoint(lldb::addr_t addr,
1662                                                           size_t size,
1663                                                           bool read,
1664                                                           bool write) {
1665   //    if (log) log->Printf
1666   //    ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(addr = %8.8p, size
1667   //    = %u, read = %u, write = %u)", addr, size, read, write);
1668
1669   const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints();
1670
1671   // Can't watch zero bytes
1672   if (size == 0)
1673     return LLDB_INVALID_INDEX32;
1674
1675   // We must watch for either read or write
1676   if (read == false && write == false)
1677     return LLDB_INVALID_INDEX32;
1678
1679   // Can't watch more than 4 bytes per WVR/WCR pair
1680   if (size > 4)
1681     return LLDB_INVALID_INDEX32;
1682
1683   // We can only watch up to four bytes that follow a 4 byte aligned address
1684   // per watchpoint register pair. Since we have at most so we can only watch
1685   // until the next 4 byte boundary and we need to make sure we can properly
1686   // encode this.
1687   uint32_t addr_word_offset = addr % 4;
1688   //    if (log) log->Printf
1689   //    ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() -
1690   //    addr_word_offset = 0x%8.8x", addr_word_offset);
1691
1692   uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset;
1693   //    if (log) log->Printf
1694   //    ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - byte_mask =
1695   //    0x%8.8x", byte_mask);
1696   if (byte_mask > 0xfu)
1697     return LLDB_INVALID_INDEX32;
1698
1699   // Read the debug state
1700   int kret = ReadDBG(false);
1701
1702   if (kret == KERN_SUCCESS) {
1703     // Check to make sure we have the needed hardware support
1704     uint32_t i = 0;
1705
1706     for (i = 0; i < num_hw_watchpoints; ++i) {
1707       if ((dbg.wcr[i] & WCR_ENABLE) == 0)
1708         break; // We found an available hw breakpoint slot (in i)
1709     }
1710
1711     // See if we found an available hw breakpoint slot above
1712     if (i < num_hw_watchpoints) {
1713       // Make the byte_mask into a valid Byte Address Select mask
1714       uint32_t byte_address_select = byte_mask << 5;
1715       // Make sure bits 1:0 are clear in our address
1716       dbg.wvr[i] = addr & ~((lldb::addr_t)3);
1717       dbg.wcr[i] = byte_address_select |     // Which bytes that follow the IMVA
1718                                              // that we will watch
1719                    S_USER |                  // Stop only in user mode
1720                    (read ? WCR_LOAD : 0) |   // Stop on read access?
1721                    (write ? WCR_STORE : 0) | // Stop on write access?
1722                    WCR_ENABLE;               // Enable this watchpoint;
1723
1724       kret = WriteDBG();
1725       //            if (log) log->Printf
1726       //            ("RegisterContextDarwin_arm::EnableHardwareWatchpoint()
1727       //            WriteDBG() => 0x%8.8x.", kret);
1728
1729       if (kret == KERN_SUCCESS)
1730         return i;
1731     } else {
1732       //            if (log) log->Printf
1733       //            ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(): All
1734       //            hardware resources (%u) are in use.", num_hw_watchpoints);
1735     }
1736   }
1737   return LLDB_INVALID_INDEX32;
1738 }
1739
1740 bool RegisterContextDarwin_arm::ClearHardwareWatchpoint(uint32_t hw_index) {
1741   int kret = ReadDBG(false);
1742
1743   const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
1744   if (kret == KERN_SUCCESS) {
1745     if (hw_index < num_hw_points) {
1746       dbg.wcr[hw_index] = 0;
1747       //            if (log) log->Printf
1748       //            ("RegisterContextDarwin_arm::ClearHardwareWatchpoint( %u ) -
1749       //            WVR%u = 0x%8.8x  WCR%u = 0x%8.8x",
1750       //                    hw_index,
1751       //                    hw_index,
1752       //                    dbg.wvr[hw_index],
1753       //                    hw_index,
1754       //                    dbg.wcr[hw_index]);
1755
1756       kret = WriteDBG();
1757
1758       if (kret == KERN_SUCCESS)
1759         return true;
1760     }
1761   }
1762   return false;
1763 }