1 //===-- RegisterContextDarwin_arm64.cpp ---------------------------*- C++
4 // The LLVM Compiler Infrastructure
6 // This file is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "RegisterContextDarwin_arm64.h"
12 #include "RegisterContextDarwinConstants.h"
14 #include "lldb/Target/Process.h"
15 #include "lldb/Target/Thread.h"
16 #include "lldb/Utility/DataBufferHeap.h"
17 #include "lldb/Utility/DataExtractor.h"
18 #include "lldb/Utility/Endian.h"
19 #include "lldb/Utility/Log.h"
20 #include "lldb/Utility/RegisterValue.h"
21 #include "lldb/Utility/Scalar.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/Support/Compiler.h"
25 #include "Plugins/Process/Utility/InstructionUtils.h"
27 // Support building against older versions of LLVM, this macro was added
29 #ifndef LLVM_EXTENSION
30 #define LLVM_EXTENSION
33 #include "Utility/ARM64_DWARF_Registers.h"
36 using namespace lldb_private;
38 #define GPR_OFFSET(idx) ((idx)*8)
39 #define GPR_OFFSET_NAME(reg) \
40 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::GPR, reg))
42 #define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterContextDarwin_arm64::GPR))
43 #define FPU_OFFSET_NAME(reg) \
44 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::FPU, reg))
46 #define EXC_OFFSET_NAME(reg) \
47 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::EXC, reg) + \
48 sizeof(RegisterContextDarwin_arm64::GPR) + \
49 sizeof(RegisterContextDarwin_arm64::FPU))
50 #define DBG_OFFSET_NAME(reg) \
51 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::DBG, reg) + \
52 sizeof(RegisterContextDarwin_arm64::GPR) + \
53 sizeof(RegisterContextDarwin_arm64::FPU) + \
54 sizeof(RegisterContextDarwin_arm64::EXC))
56 #define DEFINE_DBG(reg, i) \
58 sizeof(((RegisterContextDarwin_arm64::DBG *) NULL)->reg[i]), \
59 DBG_OFFSET_NAME(reg[i]), eEncodingUint, eFormatHex, \
60 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
61 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
62 LLDB_INVALID_REGNUM }, \
64 #define REG_CONTEXT_SIZE \
65 (sizeof(RegisterContextDarwin_arm64::GPR) + \
66 sizeof(RegisterContextDarwin_arm64::FPU) + \
67 sizeof(RegisterContextDarwin_arm64::EXC))
69 //-----------------------------------------------------------------------------
70 // Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure.
71 //-----------------------------------------------------------------------------
72 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT
73 #include "RegisterInfos_arm64.h"
74 #undef DECLARE_REGISTER_INFOS_ARM64_STRUCT
76 // General purpose registers
77 static uint32_t g_gpr_regnums[] = {
78 gpr_x0, gpr_x1, gpr_x2, gpr_x3, gpr_x4, gpr_x5, gpr_x6,
79 gpr_x7, gpr_x8, gpr_x9, gpr_x10, gpr_x11, gpr_x12, gpr_x13,
80 gpr_x14, gpr_x15, gpr_x16, gpr_x17, gpr_x18, gpr_x19, gpr_x20,
81 gpr_x21, gpr_x22, gpr_x23, gpr_x24, gpr_x25, gpr_x26, gpr_x27,
82 gpr_x28, gpr_fp, gpr_lr, gpr_sp, gpr_pc, gpr_cpsr};
84 // Floating point registers
85 static uint32_t g_fpu_regnums[] = {
86 fpu_v0, fpu_v1, fpu_v2, fpu_v3, fpu_v4, fpu_v5, fpu_v6,
87 fpu_v7, fpu_v8, fpu_v9, fpu_v10, fpu_v11, fpu_v12, fpu_v13,
88 fpu_v14, fpu_v15, fpu_v16, fpu_v17, fpu_v18, fpu_v19, fpu_v20,
89 fpu_v21, fpu_v22, fpu_v23, fpu_v24, fpu_v25, fpu_v26, fpu_v27,
90 fpu_v28, fpu_v29, fpu_v30, fpu_v31, fpu_fpsr, fpu_fpcr};
92 // Exception registers
94 static uint32_t g_exc_regnums[] = {exc_far, exc_esr, exc_exception};
96 static size_t k_num_register_infos =
97 llvm::array_lengthof(g_register_infos_arm64_le);
99 RegisterContextDarwin_arm64::RegisterContextDarwin_arm64(
100 Thread &thread, uint32_t concrete_frame_idx)
101 : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() {
103 for (i = 0; i < kNumErrors; i++) {
110 RegisterContextDarwin_arm64::~RegisterContextDarwin_arm64() {}
112 void RegisterContextDarwin_arm64::InvalidateAllRegisters() {
113 InvalidateAllRegisterStates();
116 size_t RegisterContextDarwin_arm64::GetRegisterCount() {
117 assert(k_num_register_infos == k_num_registers);
118 return k_num_registers;
122 RegisterContextDarwin_arm64::GetRegisterInfoAtIndex(size_t reg) {
123 assert(k_num_register_infos == k_num_registers);
124 if (reg < k_num_registers)
125 return &g_register_infos_arm64_le[reg];
129 size_t RegisterContextDarwin_arm64::GetRegisterInfosCount() {
130 return k_num_register_infos;
133 const RegisterInfo *RegisterContextDarwin_arm64::GetRegisterInfos() {
134 return g_register_infos_arm64_le;
137 // Number of registers in each register set
138 const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums);
139 const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums);
140 const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums);
142 //----------------------------------------------------------------------
143 // Register set definitions. The first definitions at register set index of
144 // zero is for all registers, followed by other registers sets. The register
145 // information for the all register set need not be filled in.
146 //----------------------------------------------------------------------
147 static const RegisterSet g_reg_sets[] = {
149 "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums,
151 {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums},
152 {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}};
154 const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets);
156 size_t RegisterContextDarwin_arm64::GetRegisterSetCount() {
157 return k_num_regsets;
160 const RegisterSet *RegisterContextDarwin_arm64::GetRegisterSet(size_t reg_set) {
161 if (reg_set < k_num_regsets)
162 return &g_reg_sets[reg_set];
166 //----------------------------------------------------------------------
167 // Register information definitions for arm64
168 //----------------------------------------------------------------------
169 int RegisterContextDarwin_arm64::GetSetForNativeRegNum(int reg) {
172 else if (reg < exc_far)
174 else if (reg < k_num_registers)
179 int RegisterContextDarwin_arm64::ReadGPR(bool force) {
181 if (force || !RegisterSetIsCached(set)) {
182 SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
184 return GetError(GPRRegSet, Read);
187 int RegisterContextDarwin_arm64::ReadFPU(bool force) {
189 if (force || !RegisterSetIsCached(set)) {
190 SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu));
192 return GetError(FPURegSet, Read);
195 int RegisterContextDarwin_arm64::ReadEXC(bool force) {
197 if (force || !RegisterSetIsCached(set)) {
198 SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
200 return GetError(EXCRegSet, Read);
203 int RegisterContextDarwin_arm64::ReadDBG(bool force) {
205 if (force || !RegisterSetIsCached(set)) {
206 SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg));
208 return GetError(DBGRegSet, Read);
211 int RegisterContextDarwin_arm64::WriteGPR() {
213 if (!RegisterSetIsCached(set)) {
214 SetError(set, Write, -1);
215 return KERN_INVALID_ARGUMENT;
217 SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr));
218 SetError(set, Read, -1);
219 return GetError(GPRRegSet, Write);
222 int RegisterContextDarwin_arm64::WriteFPU() {
224 if (!RegisterSetIsCached(set)) {
225 SetError(set, Write, -1);
226 return KERN_INVALID_ARGUMENT;
228 SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu));
229 SetError(set, Read, -1);
230 return GetError(FPURegSet, Write);
233 int RegisterContextDarwin_arm64::WriteEXC() {
235 if (!RegisterSetIsCached(set)) {
236 SetError(set, Write, -1);
237 return KERN_INVALID_ARGUMENT;
239 SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc));
240 SetError(set, Read, -1);
241 return GetError(EXCRegSet, Write);
244 int RegisterContextDarwin_arm64::WriteDBG() {
246 if (!RegisterSetIsCached(set)) {
247 SetError(set, Write, -1);
248 return KERN_INVALID_ARGUMENT;
250 SetError(set, Write, DoWriteDBG(GetThreadID(), set, dbg));
251 SetError(set, Read, -1);
252 return GetError(DBGRegSet, Write);
255 int RegisterContextDarwin_arm64::ReadRegisterSet(uint32_t set, bool force) {
258 return ReadGPR(force);
260 return ReadFPU(force);
262 return ReadEXC(force);
264 return ReadDBG(force);
268 return KERN_INVALID_ARGUMENT;
271 int RegisterContextDarwin_arm64::WriteRegisterSet(uint32_t set) {
272 // Make sure we have a valid context to set.
273 if (RegisterSetIsCached(set)) {
287 return KERN_INVALID_ARGUMENT;
290 void RegisterContextDarwin_arm64::LogDBGRegisters(Log *log, const DBG &dbg) {
292 for (uint32_t i = 0; i < 16; i++)
293 log->Printf("BVR%-2u/BCR%-2u = { 0x%8.8" PRIu64 ", 0x%8.8" PRIu64
294 " } WVR%-2u/WCR%-2u "
295 "= { 0x%8.8" PRIu64 ", 0x%8.8" PRIu64 " }",
296 i, i, dbg.bvr[i], dbg.bcr[i], i, i, dbg.wvr[i], dbg.wcr[i]);
300 bool RegisterContextDarwin_arm64::ReadRegister(const RegisterInfo *reg_info,
301 RegisterValue &value) {
302 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
303 int set = RegisterContextDarwin_arm64::GetSetForNativeRegNum(reg);
308 if (ReadRegisterSet(set, false) != KERN_SUCCESS)
341 value.SetUInt64(gpr.x[reg - gpr_x0]);
344 value.SetUInt64(gpr.fp);
347 value.SetUInt64(gpr.sp);
350 value.SetUInt64(gpr.lr);
353 value.SetUInt64(gpr.pc);
356 value.SetUInt64(gpr.cpsr);
388 ProcessSP process_sp(m_thread.GetProcess());
389 if (process_sp.get()) {
390 DataExtractor regdata(&gpr.x[reg - gpr_w0], 8, process_sp->GetByteOrder(),
391 process_sp->GetAddressByteSize());
393 uint64_t retval = regdata.GetMaxU64(&offset, 8);
394 uint32_t retval_lower32 = static_cast<uint32_t>(retval & 0xffffffff);
395 value.SetUInt32(retval_lower32);
431 value.SetBytes(fpu.v[reg].bytes.buffer, reg_info->byte_size,
432 endian::InlHostByteOrder());
467 ProcessSP process_sp(m_thread.GetProcess());
468 if (process_sp.get()) {
469 DataExtractor regdata(&fpu.v[reg - fpu_s0], 4, process_sp->GetByteOrder(),
470 process_sp->GetAddressByteSize());
472 value.SetFloat(regdata.GetFloat(&offset));
508 ProcessSP process_sp(m_thread.GetProcess());
509 if (process_sp.get()) {
510 DataExtractor regdata(&fpu.v[reg - fpu_s0], 8, process_sp->GetByteOrder(),
511 process_sp->GetAddressByteSize());
513 value.SetDouble(regdata.GetDouble(&offset));
518 value.SetUInt32(fpu.fpsr);
522 value.SetUInt32(fpu.fpcr);
526 value.SetUInt32(exc.exception);
529 value.SetUInt32(exc.esr);
532 value.SetUInt64(exc.far);
536 value.SetValueToInvalid();
542 bool RegisterContextDarwin_arm64::WriteRegister(const RegisterInfo *reg_info,
543 const RegisterValue &value) {
544 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
545 int set = GetSetForNativeRegNum(reg);
550 if (ReadRegisterSet(set, false) != KERN_SUCCESS)
588 gpr.x[reg - gpr_x0] = value.GetAsUInt64();
623 ::memcpy(fpu.v[reg].bytes.buffer, value.GetBytes(), value.GetByteSize());
627 fpu.fpsr = value.GetAsUInt32();
631 fpu.fpcr = value.GetAsUInt32();
635 exc.exception = value.GetAsUInt32();
638 exc.esr = value.GetAsUInt32();
641 exc.far = value.GetAsUInt64();
647 return WriteRegisterSet(set) == KERN_SUCCESS;
650 bool RegisterContextDarwin_arm64::ReadAllRegisterValues(
651 lldb::DataBufferSP &data_sp) {
652 data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0));
653 if (data_sp && ReadGPR(false) == KERN_SUCCESS &&
654 ReadFPU(false) == KERN_SUCCESS && ReadEXC(false) == KERN_SUCCESS) {
655 uint8_t *dst = data_sp->GetBytes();
656 ::memcpy(dst, &gpr, sizeof(gpr));
659 ::memcpy(dst, &fpu, sizeof(fpu));
662 ::memcpy(dst, &exc, sizeof(exc));
668 bool RegisterContextDarwin_arm64::WriteAllRegisterValues(
669 const lldb::DataBufferSP &data_sp) {
670 if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) {
671 const uint8_t *src = data_sp->GetBytes();
672 ::memcpy(&gpr, src, sizeof(gpr));
675 ::memcpy(&fpu, src, sizeof(fpu));
678 ::memcpy(&exc, src, sizeof(exc));
679 uint32_t success_count = 0;
680 if (WriteGPR() == KERN_SUCCESS)
682 if (WriteFPU() == KERN_SUCCESS)
684 if (WriteEXC() == KERN_SUCCESS)
686 return success_count == 3;
691 uint32_t RegisterContextDarwin_arm64::ConvertRegisterKindToRegisterNumber(
692 RegisterKind kind, uint32_t reg) {
693 if (kind == eRegisterKindGeneric) {
695 case LLDB_REGNUM_GENERIC_PC:
697 case LLDB_REGNUM_GENERIC_SP:
699 case LLDB_REGNUM_GENERIC_FP:
701 case LLDB_REGNUM_GENERIC_RA:
703 case LLDB_REGNUM_GENERIC_FLAGS:
708 } else if (kind == eRegisterKindDWARF) {
710 case arm64_dwarf::x0:
712 case arm64_dwarf::x1:
714 case arm64_dwarf::x2:
716 case arm64_dwarf::x3:
718 case arm64_dwarf::x4:
720 case arm64_dwarf::x5:
722 case arm64_dwarf::x6:
724 case arm64_dwarf::x7:
726 case arm64_dwarf::x8:
728 case arm64_dwarf::x9:
730 case arm64_dwarf::x10:
732 case arm64_dwarf::x11:
734 case arm64_dwarf::x12:
736 case arm64_dwarf::x13:
738 case arm64_dwarf::x14:
740 case arm64_dwarf::x15:
742 case arm64_dwarf::x16:
744 case arm64_dwarf::x17:
746 case arm64_dwarf::x18:
748 case arm64_dwarf::x19:
750 case arm64_dwarf::x20:
752 case arm64_dwarf::x21:
754 case arm64_dwarf::x22:
756 case arm64_dwarf::x23:
758 case arm64_dwarf::x24:
760 case arm64_dwarf::x25:
762 case arm64_dwarf::x26:
764 case arm64_dwarf::x27:
766 case arm64_dwarf::x28:
769 case arm64_dwarf::fp:
771 case arm64_dwarf::sp:
773 case arm64_dwarf::lr:
775 case arm64_dwarf::pc:
777 case arm64_dwarf::cpsr:
780 case arm64_dwarf::v0:
782 case arm64_dwarf::v1:
784 case arm64_dwarf::v2:
786 case arm64_dwarf::v3:
788 case arm64_dwarf::v4:
790 case arm64_dwarf::v5:
792 case arm64_dwarf::v6:
794 case arm64_dwarf::v7:
796 case arm64_dwarf::v8:
798 case arm64_dwarf::v9:
800 case arm64_dwarf::v10:
802 case arm64_dwarf::v11:
804 case arm64_dwarf::v12:
806 case arm64_dwarf::v13:
808 case arm64_dwarf::v14:
810 case arm64_dwarf::v15:
812 case arm64_dwarf::v16:
814 case arm64_dwarf::v17:
816 case arm64_dwarf::v18:
818 case arm64_dwarf::v19:
820 case arm64_dwarf::v20:
822 case arm64_dwarf::v21:
824 case arm64_dwarf::v22:
826 case arm64_dwarf::v23:
828 case arm64_dwarf::v24:
830 case arm64_dwarf::v25:
832 case arm64_dwarf::v26:
834 case arm64_dwarf::v27:
836 case arm64_dwarf::v28:
838 case arm64_dwarf::v29:
840 case arm64_dwarf::v30:
842 case arm64_dwarf::v31:
848 } else if (kind == eRegisterKindEHFrame) {
850 case arm64_ehframe::x0:
852 case arm64_ehframe::x1:
854 case arm64_ehframe::x2:
856 case arm64_ehframe::x3:
858 case arm64_ehframe::x4:
860 case arm64_ehframe::x5:
862 case arm64_ehframe::x6:
864 case arm64_ehframe::x7:
866 case arm64_ehframe::x8:
868 case arm64_ehframe::x9:
870 case arm64_ehframe::x10:
872 case arm64_ehframe::x11:
874 case arm64_ehframe::x12:
876 case arm64_ehframe::x13:
878 case arm64_ehframe::x14:
880 case arm64_ehframe::x15:
882 case arm64_ehframe::x16:
884 case arm64_ehframe::x17:
886 case arm64_ehframe::x18:
888 case arm64_ehframe::x19:
890 case arm64_ehframe::x20:
892 case arm64_ehframe::x21:
894 case arm64_ehframe::x22:
896 case arm64_ehframe::x23:
898 case arm64_ehframe::x24:
900 case arm64_ehframe::x25:
902 case arm64_ehframe::x26:
904 case arm64_ehframe::x27:
906 case arm64_ehframe::x28:
908 case arm64_ehframe::fp:
910 case arm64_ehframe::sp:
912 case arm64_ehframe::lr:
914 case arm64_ehframe::pc:
916 case arm64_ehframe::cpsr:
919 } else if (kind == eRegisterKindLLDB) {
922 return LLDB_INVALID_REGNUM;
925 uint32_t RegisterContextDarwin_arm64::NumSupportedHardwareWatchpoints() {
926 #if defined(__APPLE__) && (defined(__arm64__) || defined(__aarch64__))
927 // autodetect how many watchpoints are supported dynamically...
928 static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX;
929 if (g_num_supported_hw_watchpoints == UINT32_MAX) {
933 if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0) {
934 g_num_supported_hw_watchpoints = n;
937 return g_num_supported_hw_watchpoints;
939 // TODO: figure out remote case here!
944 uint32_t RegisterContextDarwin_arm64::SetHardwareWatchpoint(lldb::addr_t addr,
948 // if (log) log->Printf
949 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint(addr = %8.8p,
950 // size = %u, read = %u, write = %u)", addr, size, read, write);
952 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints();
954 // Can't watch zero bytes
956 return LLDB_INVALID_INDEX32;
958 // We must watch for either read or write
960 return LLDB_INVALID_INDEX32;
962 // Can't watch more than 4 bytes per WVR/WCR pair
964 return LLDB_INVALID_INDEX32;
966 // We can only watch up to four bytes that follow a 4 byte aligned address
967 // per watchpoint register pair. Since we have at most so we can only watch
968 // until the next 4 byte boundary and we need to make sure we can properly
970 uint32_t addr_word_offset = addr % 4;
971 // if (log) log->Printf
972 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() -
973 // addr_word_offset = 0x%8.8x", addr_word_offset);
975 uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset;
976 // if (log) log->Printf
977 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() - byte_mask =
978 // 0x%8.8x", byte_mask);
979 if (byte_mask > 0xfu)
980 return LLDB_INVALID_INDEX32;
982 // Read the debug state
983 int kret = ReadDBG(false);
985 if (kret == KERN_SUCCESS) {
986 // Check to make sure we have the needed hardware support
989 for (i = 0; i < num_hw_watchpoints; ++i) {
990 if ((dbg.wcr[i] & WCR_ENABLE) == 0)
991 break; // We found an available hw breakpoint slot (in i)
994 // See if we found an available hw breakpoint slot above
995 if (i < num_hw_watchpoints) {
996 // Make the byte_mask into a valid Byte Address Select mask
997 uint32_t byte_address_select = byte_mask << 5;
998 // Make sure bits 1:0 are clear in our address
999 dbg.wvr[i] = addr & ~((lldb::addr_t)3);
1000 dbg.wcr[i] = byte_address_select | // Which bytes that follow the IMVA
1001 // that we will watch
1002 S_USER | // Stop only in user mode
1003 (read ? WCR_LOAD : 0) | // Stop on read access?
1004 (write ? WCR_STORE : 0) | // Stop on write access?
1005 WCR_ENABLE; // Enable this watchpoint;
1008 // if (log) log->Printf
1009 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint()
1010 // WriteDBG() => 0x%8.8x.", kret);
1012 if (kret == KERN_SUCCESS)
1015 // if (log) log->Printf
1016 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint():
1017 // All hardware resources (%u) are in use.",
1018 // num_hw_watchpoints);
1021 return LLDB_INVALID_INDEX32;
1024 bool RegisterContextDarwin_arm64::ClearHardwareWatchpoint(uint32_t hw_index) {
1025 int kret = ReadDBG(false);
1027 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
1028 if (kret == KERN_SUCCESS) {
1029 if (hw_index < num_hw_points) {
1030 dbg.wcr[hw_index] = 0;
1031 // if (log) log->Printf
1032 // ("RegisterContextDarwin_arm64::ClearHardwareWatchpoint( %u )
1033 // - WVR%u = 0x%8.8x WCR%u = 0x%8.8x",
1036 // dbg.wvr[hw_index],
1038 // dbg.wcr[hw_index]);
1042 if (kret == KERN_SUCCESS)