1 //===-- RegisterContextDarwin_arm64.cpp ---------------------------*- C++
4 // The LLVM Compiler Infrastructure
6 // This file is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #if defined(__APPLE__)
13 #include "RegisterContextDarwin_arm64.h"
16 #include <mach/mach_types.h>
17 #include <mach/thread_act.h>
18 #include <sys/sysctl.h>
21 // Other libraries and framework includes
22 #include "lldb/Core/RegisterValue.h"
23 #include "lldb/Core/Scalar.h"
24 #include "lldb/Target/Process.h"
25 #include "lldb/Target/Thread.h"
26 #include "lldb/Utility/DataBufferHeap.h"
27 #include "lldb/Utility/DataExtractor.h"
28 #include "lldb/Utility/Endian.h"
29 #include "lldb/Utility/Log.h"
30 #include "llvm/ADT/STLExtras.h"
31 #include "llvm/Support/Compiler.h"
33 #include "Plugins/Process/Utility/InstructionUtils.h"
35 // Support building against older versions of LLVM, this macro was added
37 #ifndef LLVM_EXTENSION
38 #define LLVM_EXTENSION
42 #include "ARM64_DWARF_Registers.h"
45 using namespace lldb_private;
47 #define GPR_OFFSET(idx) ((idx)*8)
48 #define GPR_OFFSET_NAME(reg) \
49 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::GPR, reg))
51 #define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterContextDarwin_arm64::GPR))
52 #define FPU_OFFSET_NAME(reg) \
53 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::FPU, reg))
55 #define EXC_OFFSET_NAME(reg) \
56 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::EXC, reg) + \
57 sizeof(RegisterContextDarwin_arm64::GPR) + \
58 sizeof(RegisterContextDarwin_arm64::FPU))
59 #define DBG_OFFSET_NAME(reg) \
60 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::DBG, reg) + \
61 sizeof(RegisterContextDarwin_arm64::GPR) + \
62 sizeof(RegisterContextDarwin_arm64::FPU) + \
63 sizeof(RegisterContextDarwin_arm64::EXC))
65 #define DEFINE_DBG(reg, i) \
67 sizeof(((RegisterContextDarwin_arm64::DBG *) NULL)->reg[i]), \
68 DBG_OFFSET_NAME(reg[i]), eEncodingUint, eFormatHex, \
69 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
70 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
71 LLDB_INVALID_REGNUM }, \
73 #define REG_CONTEXT_SIZE \
74 (sizeof(RegisterContextDarwin_arm64::GPR) + \
75 sizeof(RegisterContextDarwin_arm64::FPU) + \
76 sizeof(RegisterContextDarwin_arm64::EXC))
78 //-----------------------------------------------------------------------------
79 // Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure.
80 //-----------------------------------------------------------------------------
81 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT
82 #include "RegisterInfos_arm64.h"
83 #undef DECLARE_REGISTER_INFOS_ARM64_STRUCT
85 // General purpose registers
86 static uint32_t g_gpr_regnums[] = {
87 gpr_x0, gpr_x1, gpr_x2, gpr_x3, gpr_x4, gpr_x5, gpr_x6,
88 gpr_x7, gpr_x8, gpr_x9, gpr_x10, gpr_x11, gpr_x12, gpr_x13,
89 gpr_x14, gpr_x15, gpr_x16, gpr_x17, gpr_x18, gpr_x19, gpr_x20,
90 gpr_x21, gpr_x22, gpr_x23, gpr_x24, gpr_x25, gpr_x26, gpr_x27,
91 gpr_x28, gpr_fp, gpr_lr, gpr_sp, gpr_pc, gpr_cpsr};
93 // Floating point registers
94 static uint32_t g_fpu_regnums[] = {
95 fpu_v0, fpu_v1, fpu_v2, fpu_v3, fpu_v4, fpu_v5, fpu_v6,
96 fpu_v7, fpu_v8, fpu_v9, fpu_v10, fpu_v11, fpu_v12, fpu_v13,
97 fpu_v14, fpu_v15, fpu_v16, fpu_v17, fpu_v18, fpu_v19, fpu_v20,
98 fpu_v21, fpu_v22, fpu_v23, fpu_v24, fpu_v25, fpu_v26, fpu_v27,
99 fpu_v28, fpu_v29, fpu_v30, fpu_v31, fpu_fpsr, fpu_fpcr};
101 // Exception registers
103 static uint32_t g_exc_regnums[] = {exc_far, exc_esr, exc_exception};
105 static size_t k_num_register_infos =
106 llvm::array_lengthof(g_register_infos_arm64_le);
108 RegisterContextDarwin_arm64::RegisterContextDarwin_arm64(
109 Thread &thread, uint32_t concrete_frame_idx)
110 : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() {
112 for (i = 0; i < kNumErrors; i++) {
119 RegisterContextDarwin_arm64::~RegisterContextDarwin_arm64() {}
121 void RegisterContextDarwin_arm64::InvalidateAllRegisters() {
122 InvalidateAllRegisterStates();
125 size_t RegisterContextDarwin_arm64::GetRegisterCount() {
126 assert(k_num_register_infos == k_num_registers);
127 return k_num_registers;
131 RegisterContextDarwin_arm64::GetRegisterInfoAtIndex(size_t reg) {
132 assert(k_num_register_infos == k_num_registers);
133 if (reg < k_num_registers)
134 return &g_register_infos_arm64_le[reg];
138 size_t RegisterContextDarwin_arm64::GetRegisterInfosCount() {
139 return k_num_register_infos;
142 const RegisterInfo *RegisterContextDarwin_arm64::GetRegisterInfos() {
143 return g_register_infos_arm64_le;
146 // Number of registers in each register set
147 const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums);
148 const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums);
149 const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums);
151 //----------------------------------------------------------------------
152 // Register set definitions. The first definitions at register set index
153 // of zero is for all registers, followed by other registers sets. The
154 // register information for the all register set need not be filled in.
155 //----------------------------------------------------------------------
156 static const RegisterSet g_reg_sets[] = {
158 "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums,
160 {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums},
161 {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}};
163 const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets);
165 size_t RegisterContextDarwin_arm64::GetRegisterSetCount() {
166 return k_num_regsets;
169 const RegisterSet *RegisterContextDarwin_arm64::GetRegisterSet(size_t reg_set) {
170 if (reg_set < k_num_regsets)
171 return &g_reg_sets[reg_set];
175 //----------------------------------------------------------------------
176 // Register information definitions for arm64
177 //----------------------------------------------------------------------
178 int RegisterContextDarwin_arm64::GetSetForNativeRegNum(int reg) {
181 else if (reg < exc_far)
183 else if (reg < k_num_registers)
188 int RegisterContextDarwin_arm64::ReadGPR(bool force) {
190 if (force || !RegisterSetIsCached(set)) {
191 SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
193 return GetError(GPRRegSet, Read);
196 int RegisterContextDarwin_arm64::ReadFPU(bool force) {
198 if (force || !RegisterSetIsCached(set)) {
199 SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu));
201 return GetError(FPURegSet, Read);
204 int RegisterContextDarwin_arm64::ReadEXC(bool force) {
206 if (force || !RegisterSetIsCached(set)) {
207 SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
209 return GetError(EXCRegSet, Read);
212 int RegisterContextDarwin_arm64::ReadDBG(bool force) {
214 if (force || !RegisterSetIsCached(set)) {
215 SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg));
217 return GetError(DBGRegSet, Read);
220 int RegisterContextDarwin_arm64::WriteGPR() {
222 if (!RegisterSetIsCached(set)) {
223 SetError(set, Write, -1);
224 return KERN_INVALID_ARGUMENT;
226 SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr));
227 SetError(set, Read, -1);
228 return GetError(GPRRegSet, Write);
231 int RegisterContextDarwin_arm64::WriteFPU() {
233 if (!RegisterSetIsCached(set)) {
234 SetError(set, Write, -1);
235 return KERN_INVALID_ARGUMENT;
237 SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu));
238 SetError(set, Read, -1);
239 return GetError(FPURegSet, Write);
242 int RegisterContextDarwin_arm64::WriteEXC() {
244 if (!RegisterSetIsCached(set)) {
245 SetError(set, Write, -1);
246 return KERN_INVALID_ARGUMENT;
248 SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc));
249 SetError(set, Read, -1);
250 return GetError(EXCRegSet, Write);
253 int RegisterContextDarwin_arm64::WriteDBG() {
255 if (!RegisterSetIsCached(set)) {
256 SetError(set, Write, -1);
257 return KERN_INVALID_ARGUMENT;
259 SetError(set, Write, DoWriteDBG(GetThreadID(), set, dbg));
260 SetError(set, Read, -1);
261 return GetError(DBGRegSet, Write);
264 int RegisterContextDarwin_arm64::ReadRegisterSet(uint32_t set, bool force) {
267 return ReadGPR(force);
269 return ReadFPU(force);
271 return ReadEXC(force);
273 return ReadDBG(force);
277 return KERN_INVALID_ARGUMENT;
280 int RegisterContextDarwin_arm64::WriteRegisterSet(uint32_t set) {
281 // Make sure we have a valid context to set.
282 if (RegisterSetIsCached(set)) {
296 return KERN_INVALID_ARGUMENT;
299 void RegisterContextDarwin_arm64::LogDBGRegisters(Log *log, const DBG &dbg) {
301 for (uint32_t i = 0; i < 16; i++)
302 log->Printf("BVR%-2u/BCR%-2u = { 0x%8.8llx, 0x%8.8llx } WVR%-2u/WCR%-2u "
303 "= { 0x%8.8llx, 0x%8.8llx }",
304 i, i, dbg.bvr[i], dbg.bcr[i], i, i, dbg.wvr[i], dbg.wcr[i]);
308 bool RegisterContextDarwin_arm64::ReadRegister(const RegisterInfo *reg_info,
309 RegisterValue &value) {
310 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
311 int set = RegisterContextDarwin_arm64::GetSetForNativeRegNum(reg);
316 if (ReadRegisterSet(set, false) != KERN_SUCCESS)
354 value.SetUInt64(gpr.x[reg - gpr_x0]);
386 ProcessSP process_sp(m_thread.GetProcess());
387 if (process_sp.get()) {
388 DataExtractor regdata(&gpr.x[reg - gpr_w0], 8, process_sp->GetByteOrder(),
389 process_sp->GetAddressByteSize());
391 uint64_t retval = regdata.GetMaxU64(&offset, 8);
392 uint32_t retval_lower32 = static_cast<uint32_t>(retval & 0xffffffff);
393 value.SetUInt32(retval_lower32);
429 value.SetBytes(fpu.v[reg].bytes, reg_info->byte_size,
430 endian::InlHostByteOrder());
465 ProcessSP process_sp(m_thread.GetProcess());
466 if (process_sp.get()) {
467 DataExtractor regdata(&fpu.v[reg - fpu_s0], 4, process_sp->GetByteOrder(),
468 process_sp->GetAddressByteSize());
470 value.SetFloat(regdata.GetFloat(&offset));
506 ProcessSP process_sp(m_thread.GetProcess());
507 if (process_sp.get()) {
508 DataExtractor regdata(&fpu.v[reg - fpu_s0], 8, process_sp->GetByteOrder(),
509 process_sp->GetAddressByteSize());
511 value.SetDouble(regdata.GetDouble(&offset));
516 value.SetUInt32(fpu.fpsr);
520 value.SetUInt32(fpu.fpcr);
524 value.SetUInt32(exc.exception);
527 value.SetUInt32(exc.esr);
530 value.SetUInt64(exc.far);
534 value.SetValueToInvalid();
540 bool RegisterContextDarwin_arm64::WriteRegister(const RegisterInfo *reg_info,
541 const RegisterValue &value) {
542 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
543 int set = GetSetForNativeRegNum(reg);
548 if (ReadRegisterSet(set, false) != KERN_SUCCESS)
586 gpr.x[reg - gpr_x0] = value.GetAsUInt64();
621 ::memcpy(fpu.v[reg].bytes, value.GetBytes(), value.GetByteSize());
625 fpu.fpsr = value.GetAsUInt32();
629 fpu.fpcr = value.GetAsUInt32();
633 exc.exception = value.GetAsUInt32();
636 exc.esr = value.GetAsUInt32();
639 exc.far = value.GetAsUInt64();
645 return WriteRegisterSet(set) == KERN_SUCCESS;
648 bool RegisterContextDarwin_arm64::ReadAllRegisterValues(
649 lldb::DataBufferSP &data_sp) {
650 data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0));
651 if (data_sp && ReadGPR(false) == KERN_SUCCESS &&
652 ReadFPU(false) == KERN_SUCCESS && ReadEXC(false) == KERN_SUCCESS) {
653 uint8_t *dst = data_sp->GetBytes();
654 ::memcpy(dst, &gpr, sizeof(gpr));
657 ::memcpy(dst, &fpu, sizeof(fpu));
660 ::memcpy(dst, &exc, sizeof(exc));
666 bool RegisterContextDarwin_arm64::WriteAllRegisterValues(
667 const lldb::DataBufferSP &data_sp) {
668 if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) {
669 const uint8_t *src = data_sp->GetBytes();
670 ::memcpy(&gpr, src, sizeof(gpr));
673 ::memcpy(&fpu, src, sizeof(fpu));
676 ::memcpy(&exc, src, sizeof(exc));
677 uint32_t success_count = 0;
678 if (WriteGPR() == KERN_SUCCESS)
680 if (WriteFPU() == KERN_SUCCESS)
682 if (WriteEXC() == KERN_SUCCESS)
684 return success_count == 3;
689 uint32_t RegisterContextDarwin_arm64::ConvertRegisterKindToRegisterNumber(
690 RegisterKind kind, uint32_t reg) {
691 if (kind == eRegisterKindGeneric) {
693 case LLDB_REGNUM_GENERIC_PC:
695 case LLDB_REGNUM_GENERIC_SP:
697 case LLDB_REGNUM_GENERIC_FP:
699 case LLDB_REGNUM_GENERIC_RA:
701 case LLDB_REGNUM_GENERIC_FLAGS:
706 } else if (kind == eRegisterKindDWARF) {
708 case arm64_dwarf::x0:
710 case arm64_dwarf::x1:
712 case arm64_dwarf::x2:
714 case arm64_dwarf::x3:
716 case arm64_dwarf::x4:
718 case arm64_dwarf::x5:
720 case arm64_dwarf::x6:
722 case arm64_dwarf::x7:
724 case arm64_dwarf::x8:
726 case arm64_dwarf::x9:
728 case arm64_dwarf::x10:
730 case arm64_dwarf::x11:
732 case arm64_dwarf::x12:
734 case arm64_dwarf::x13:
736 case arm64_dwarf::x14:
738 case arm64_dwarf::x15:
740 case arm64_dwarf::x16:
742 case arm64_dwarf::x17:
744 case arm64_dwarf::x18:
746 case arm64_dwarf::x19:
748 case arm64_dwarf::x20:
750 case arm64_dwarf::x21:
752 case arm64_dwarf::x22:
754 case arm64_dwarf::x23:
756 case arm64_dwarf::x24:
758 case arm64_dwarf::x25:
760 case arm64_dwarf::x26:
762 case arm64_dwarf::x27:
764 case arm64_dwarf::x28:
767 case arm64_dwarf::fp:
769 case arm64_dwarf::sp:
771 case arm64_dwarf::lr:
773 case arm64_dwarf::pc:
775 case arm64_dwarf::cpsr:
778 case arm64_dwarf::v0:
780 case arm64_dwarf::v1:
782 case arm64_dwarf::v2:
784 case arm64_dwarf::v3:
786 case arm64_dwarf::v4:
788 case arm64_dwarf::v5:
790 case arm64_dwarf::v6:
792 case arm64_dwarf::v7:
794 case arm64_dwarf::v8:
796 case arm64_dwarf::v9:
798 case arm64_dwarf::v10:
800 case arm64_dwarf::v11:
802 case arm64_dwarf::v12:
804 case arm64_dwarf::v13:
806 case arm64_dwarf::v14:
808 case arm64_dwarf::v15:
810 case arm64_dwarf::v16:
812 case arm64_dwarf::v17:
814 case arm64_dwarf::v18:
816 case arm64_dwarf::v19:
818 case arm64_dwarf::v20:
820 case arm64_dwarf::v21:
822 case arm64_dwarf::v22:
824 case arm64_dwarf::v23:
826 case arm64_dwarf::v24:
828 case arm64_dwarf::v25:
830 case arm64_dwarf::v26:
832 case arm64_dwarf::v27:
834 case arm64_dwarf::v28:
836 case arm64_dwarf::v29:
838 case arm64_dwarf::v30:
840 case arm64_dwarf::v31:
846 } else if (kind == eRegisterKindEHFrame) {
848 case arm64_ehframe::x0:
850 case arm64_ehframe::x1:
852 case arm64_ehframe::x2:
854 case arm64_ehframe::x3:
856 case arm64_ehframe::x4:
858 case arm64_ehframe::x5:
860 case arm64_ehframe::x6:
862 case arm64_ehframe::x7:
864 case arm64_ehframe::x8:
866 case arm64_ehframe::x9:
868 case arm64_ehframe::x10:
870 case arm64_ehframe::x11:
872 case arm64_ehframe::x12:
874 case arm64_ehframe::x13:
876 case arm64_ehframe::x14:
878 case arm64_ehframe::x15:
880 case arm64_ehframe::x16:
882 case arm64_ehframe::x17:
884 case arm64_ehframe::x18:
886 case arm64_ehframe::x19:
888 case arm64_ehframe::x20:
890 case arm64_ehframe::x21:
892 case arm64_ehframe::x22:
894 case arm64_ehframe::x23:
896 case arm64_ehframe::x24:
898 case arm64_ehframe::x25:
900 case arm64_ehframe::x26:
902 case arm64_ehframe::x27:
904 case arm64_ehframe::x28:
906 case arm64_ehframe::fp:
908 case arm64_ehframe::sp:
910 case arm64_ehframe::lr:
912 case arm64_ehframe::pc:
914 case arm64_ehframe::cpsr:
917 } else if (kind == eRegisterKindLLDB) {
920 return LLDB_INVALID_REGNUM;
923 uint32_t RegisterContextDarwin_arm64::NumSupportedHardwareWatchpoints() {
924 #if defined(__arm64__) || defined(__aarch64__)
925 // autodetect how many watchpoints are supported dynamically...
926 static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX;
927 if (g_num_supported_hw_watchpoints == UINT32_MAX) {
931 if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0) {
932 g_num_supported_hw_watchpoints = n;
935 return g_num_supported_hw_watchpoints;
937 // TODO: figure out remote case here!
942 uint32_t RegisterContextDarwin_arm64::SetHardwareWatchpoint(lldb::addr_t addr,
946 // if (log) log->Printf
947 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint(addr = %8.8p,
948 // size = %u, read = %u, write = %u)", addr, size, read, write);
950 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints();
952 // Can't watch zero bytes
954 return LLDB_INVALID_INDEX32;
956 // We must watch for either read or write
957 if (read == false && write == false)
958 return LLDB_INVALID_INDEX32;
960 // Can't watch more than 4 bytes per WVR/WCR pair
962 return LLDB_INVALID_INDEX32;
964 // We can only watch up to four bytes that follow a 4 byte aligned address
965 // per watchpoint register pair. Since we have at most so we can only watch
966 // until the next 4 byte boundary and we need to make sure we can properly
968 uint32_t addr_word_offset = addr % 4;
969 // if (log) log->Printf
970 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() -
971 // addr_word_offset = 0x%8.8x", addr_word_offset);
973 uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset;
974 // if (log) log->Printf
975 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() - byte_mask =
976 // 0x%8.8x", byte_mask);
977 if (byte_mask > 0xfu)
978 return LLDB_INVALID_INDEX32;
980 // Read the debug state
981 int kret = ReadDBG(false);
983 if (kret == KERN_SUCCESS) {
984 // Check to make sure we have the needed hardware support
987 for (i = 0; i < num_hw_watchpoints; ++i) {
988 if ((dbg.wcr[i] & WCR_ENABLE) == 0)
989 break; // We found an available hw breakpoint slot (in i)
992 // See if we found an available hw breakpoint slot above
993 if (i < num_hw_watchpoints) {
994 // Make the byte_mask into a valid Byte Address Select mask
995 uint32_t byte_address_select = byte_mask << 5;
996 // Make sure bits 1:0 are clear in our address
997 dbg.wvr[i] = addr & ~((lldb::addr_t)3);
998 dbg.wcr[i] = byte_address_select | // Which bytes that follow the IMVA
999 // that we will watch
1000 S_USER | // Stop only in user mode
1001 (read ? WCR_LOAD : 0) | // Stop on read access?
1002 (write ? WCR_STORE : 0) | // Stop on write access?
1003 WCR_ENABLE; // Enable this watchpoint;
1006 // if (log) log->Printf
1007 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint()
1008 // WriteDBG() => 0x%8.8x.", kret);
1010 if (kret == KERN_SUCCESS)
1013 // if (log) log->Printf
1014 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint():
1015 // All hardware resources (%u) are in use.",
1016 // num_hw_watchpoints);
1019 return LLDB_INVALID_INDEX32;
1022 bool RegisterContextDarwin_arm64::ClearHardwareWatchpoint(uint32_t hw_index) {
1023 int kret = ReadDBG(false);
1025 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
1026 if (kret == KERN_SUCCESS) {
1027 if (hw_index < num_hw_points) {
1028 dbg.wcr[hw_index] = 0;
1029 // if (log) log->Printf
1030 // ("RegisterContextDarwin_arm64::ClearHardwareWatchpoint( %u )
1031 // - WVR%u = 0x%8.8x WCR%u = 0x%8.8x",
1034 // dbg.wvr[hw_index],
1036 // dbg.wcr[hw_index]);
1040 if (kret == KERN_SUCCESS)