contrib/llvm/tools/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_i386.cpp

   1 //===-- RegisterContextDarwin_i386.cpp --------------------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 // C Includes
  11 #include <stddef.h> // offsetof
  12
  13 // C++ Includes
  14 // Other libraries and framework includes
  15 #include "lldb/Core/RegisterValue.h"
  16 #include "lldb/Core/Scalar.h"
  17 #include "lldb/Utility/DataBufferHeap.h"
  18 #include "lldb/Utility/DataExtractor.h"
  19 #include "lldb/Utility/Endian.h"
  20 #include "lldb/Utility/Log.h"
  21 #include "llvm/ADT/STLExtras.h"
  22 #include "llvm/Support/Compiler.h"
  23
  24 // Support building against older versions of LLVM, this macro was added
  25 // recently.
  26 #ifndef LLVM_EXTENSION
  27 #define LLVM_EXTENSION
  28 #endif
  29
  30 // Project includes
  31 #include "RegisterContextDarwin_i386.h"
  32
  33 using namespace lldb;
  34 using namespace lldb_private;
  35
  36 enum {
  37   gpr_eax = 0,
  38   gpr_ebx,
  39   gpr_ecx,
  40   gpr_edx,
  41   gpr_edi,
  42   gpr_esi,
  43   gpr_ebp,
  44   gpr_esp,
  45   gpr_ss,
  46   gpr_eflags,
  47   gpr_eip,
  48   gpr_cs,
  49   gpr_ds,
  50   gpr_es,
  51   gpr_fs,
  52   gpr_gs,
  53
  54   fpu_fcw,
  55   fpu_fsw,
  56   fpu_ftw,
  57   fpu_fop,
  58   fpu_ip,
  59   fpu_cs,
  60   fpu_dp,
  61   fpu_ds,
  62   fpu_mxcsr,
  63   fpu_mxcsrmask,
  64   fpu_stmm0,
  65   fpu_stmm1,
  66   fpu_stmm2,
  67   fpu_stmm3,
  68   fpu_stmm4,
  69   fpu_stmm5,
  70   fpu_stmm6,
  71   fpu_stmm7,
  72   fpu_xmm0,
  73   fpu_xmm1,
  74   fpu_xmm2,
  75   fpu_xmm3,
  76   fpu_xmm4,
  77   fpu_xmm5,
  78   fpu_xmm6,
  79   fpu_xmm7,
  80
  81   exc_trapno,
  82   exc_err,
  83   exc_faultvaddr,
  84
  85   k_num_registers,
  86
  87   // Aliases
  88   fpu_fctrl = fpu_fcw,
  89   fpu_fstat = fpu_fsw,
  90   fpu_ftag = fpu_ftw,
  91   fpu_fiseg = fpu_cs,
  92   fpu_fioff = fpu_ip,
  93   fpu_foseg = fpu_ds,
  94   fpu_fooff = fpu_dp
  95 };
  96
  97 enum {
  98   ehframe_eax = 0,
  99   ehframe_ecx,
 100   ehframe_edx,
 101   ehframe_ebx,
 102   ehframe_ebp,
 103   ehframe_esp,
 104   ehframe_esi,
 105   ehframe_edi,
 106   ehframe_eip,
 107   ehframe_eflags
 108 };
 109
 110 enum {
 111   dwarf_eax = 0,
 112   dwarf_ecx,
 113   dwarf_edx,
 114   dwarf_ebx,
 115   dwarf_esp,
 116   dwarf_ebp,
 117   dwarf_esi,
 118   dwarf_edi,
 119   dwarf_eip,
 120   dwarf_eflags,
 121   dwarf_stmm0 = 11,
 122   dwarf_stmm1,
 123   dwarf_stmm2,
 124   dwarf_stmm3,
 125   dwarf_stmm4,
 126   dwarf_stmm5,
 127   dwarf_stmm6,
 128   dwarf_stmm7,
 129   dwarf_xmm0 = 21,
 130   dwarf_xmm1,
 131   dwarf_xmm2,
 132   dwarf_xmm3,
 133   dwarf_xmm4,
 134   dwarf_xmm5,
 135   dwarf_xmm6,
 136   dwarf_xmm7
 137 };
 138
 139 #define GPR_OFFSET(reg)                                                        \
 140   (LLVM_EXTENSION offsetof(RegisterContextDarwin_i386::GPR, reg))
 141 #define FPU_OFFSET(reg)                                                        \
 142   (LLVM_EXTENSION offsetof(RegisterContextDarwin_i386::FPU, reg) +             \
 143    sizeof(RegisterContextDarwin_i386::GPR))
 144 #define EXC_OFFSET(reg)                                                        \
 145   (LLVM_EXTENSION offsetof(RegisterContextDarwin_i386::EXC, reg) +             \
 146    sizeof(RegisterContextDarwin_i386::GPR) +                                   \
 147    sizeof(RegisterContextDarwin_i386::FPU))
 148
 149 // These macros will auto define the register name, alt name, register size,
 150 // register offset, encoding, format and native register. This ensures that the
 151 // register state structures are defined correctly and have the correct sizes
 152 // and offsets.
 153 #define DEFINE_GPR(reg, alt)                                                   \
 154   #reg, alt, sizeof(((RegisterContextDarwin_i386::GPR *) NULL)->reg),          \
 155                     GPR_OFFSET(reg), eEncodingUint, eFormatHex
 156 #define DEFINE_FPU_UINT(reg)                                                   \
 157   #reg, NULL, sizeof(((RegisterContextDarwin_i386::FPU *) NULL)->reg),         \
 158                      FPU_OFFSET(reg), eEncodingUint, eFormatHex
 159 #define DEFINE_FPU_VECT(reg, i)                                                \
 160   #reg #i, NULL,                                                               \
 161       sizeof(((RegisterContextDarwin_i386::FPU *) NULL)->reg[i].bytes),        \
 162               FPU_OFFSET(reg[i]), eEncodingVector, eFormatVectorOfUInt8,       \
 163                          {LLDB_INVALID_REGNUM, dwarf_##reg##i,                 \
 164                           LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,            \
 165                           fpu_##reg##i },                                      \
 166                           nullptr, nullptr, nullptr, 0
 167
 168 #define DEFINE_EXC(reg)                                                        \
 169   #reg, NULL, sizeof(((RegisterContextDarwin_i386::EXC *) NULL)->reg),         \
 170                      EXC_OFFSET(reg), eEncodingUint, eFormatHex
 171 #define REG_CONTEXT_SIZE                                                       \
 172   (sizeof(RegisterContextDarwin_i386::GPR) +                                   \
 173    sizeof(RegisterContextDarwin_i386::FPU) +                                   \
 174    sizeof(RegisterContextDarwin_i386::EXC))
 175
 176 static RegisterInfo g_register_infos[] = {
 177     //  Macro auto defines most stuff   eh_frame                DWARF
 178     //  GENERIC                    PROCESS PLUGIN       LLDB
 179     //  =============================== =======================
 180     //  ===================   =========================  ==================
 181     //  =================
 182     {DEFINE_GPR(eax, NULL),
 183      {ehframe_eax, dwarf_eax, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 184       gpr_eax},
 185      nullptr,
 186      nullptr,
 187      nullptr,
 188      0},
 189     {DEFINE_GPR(ebx, NULL),
 190      {ehframe_ebx, dwarf_ebx, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 191       gpr_ebx},
 192      nullptr,
 193      nullptr,
 194      nullptr,
 195      0},
 196     {DEFINE_GPR(ecx, NULL),
 197      {ehframe_ecx, dwarf_ecx, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 198       gpr_ecx},
 199      nullptr,
 200      nullptr,
 201      nullptr,
 202      0},
 203     {DEFINE_GPR(edx, NULL),
 204      {ehframe_edx, dwarf_edx, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 205       gpr_edx},
 206      nullptr,
 207      nullptr,
 208      nullptr,
 209      0},
 210     {DEFINE_GPR(edi, NULL),
 211      {ehframe_edi, dwarf_edi, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 212       gpr_edi},
 213      nullptr,
 214      nullptr,
 215      nullptr,
 216      0},
 217     {DEFINE_GPR(esi, NULL),
 218      {ehframe_esi, dwarf_esi, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 219       gpr_esi},
 220      nullptr,
 221      nullptr,
 222      nullptr,
 223      0},
 224     {DEFINE_GPR(ebp, "fp"),
 225      {ehframe_ebp, dwarf_ebp, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM,
 226       gpr_ebp},
 227      nullptr,
 228      nullptr,
 229      nullptr,
 230      0},
 231     {DEFINE_GPR(esp, "sp"),
 232      {ehframe_esp, dwarf_esp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM,
 233       gpr_esp},
 234      nullptr,
 235      nullptr,
 236      nullptr,
 237      0},
 238     {DEFINE_GPR(ss, NULL),
 239      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 240       LLDB_INVALID_REGNUM, gpr_ss},
 241      nullptr,
 242      nullptr,
 243      nullptr,
 244      0},
 245     {DEFINE_GPR(eflags, "flags"),
 246      {ehframe_eflags, dwarf_eflags, LLDB_REGNUM_GENERIC_FLAGS,
 247       LLDB_INVALID_REGNUM, gpr_eflags},
 248      nullptr,
 249      nullptr,
 250      nullptr,
 251      0},
 252     {DEFINE_GPR(eip, "pc"),
 253      {ehframe_eip, dwarf_eip, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM,
 254       gpr_eip},
 255      nullptr,
 256      nullptr,
 257      nullptr,
 258      0},
 259     {DEFINE_GPR(cs, NULL),
 260      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 261       LLDB_INVALID_REGNUM, gpr_cs},
 262      nullptr,
 263      nullptr,
 264      nullptr,
 265      0},
 266     {DEFINE_GPR(ds, NULL),
 267      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 268       LLDB_INVALID_REGNUM, gpr_ds},
 269      nullptr,
 270      nullptr,
 271      nullptr,
 272      0},
 273     {DEFINE_GPR(es, NULL),
 274      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 275       LLDB_INVALID_REGNUM, gpr_es},
 276      nullptr,
 277      nullptr,
 278      nullptr,
 279      0},
 280     {DEFINE_GPR(fs, NULL),
 281      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 282       LLDB_INVALID_REGNUM, gpr_fs},
 283      nullptr,
 284      nullptr,
 285      nullptr,
 286      0},
 287     {DEFINE_GPR(gs, NULL),
 288      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 289       LLDB_INVALID_REGNUM, gpr_gs},
 290      nullptr,
 291      nullptr,
 292      nullptr,
 293      0},
 294
 295     {DEFINE_FPU_UINT(fcw),
 296      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 297       LLDB_INVALID_REGNUM, fpu_fcw},
 298      nullptr,
 299      nullptr,
 300      nullptr,
 301      0},
 302     {DEFINE_FPU_UINT(fsw),
 303      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 304       LLDB_INVALID_REGNUM, fpu_fsw},
 305      nullptr,
 306      nullptr,
 307      nullptr,
 308      0},
 309     {DEFINE_FPU_UINT(ftw),
 310      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 311       LLDB_INVALID_REGNUM, fpu_ftw},
 312      nullptr,
 313      nullptr,
 314      nullptr,
 315      0},
 316     {DEFINE_FPU_UINT(fop),
 317      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 318       LLDB_INVALID_REGNUM, fpu_fop},
 319      nullptr,
 320      nullptr,
 321      nullptr,
 322      0},
 323     {DEFINE_FPU_UINT(ip),
 324      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 325       LLDB_INVALID_REGNUM, fpu_ip},
 326      nullptr,
 327      nullptr,
 328      nullptr,
 329      0},
 330     {DEFINE_FPU_UINT(cs),
 331      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 332       LLDB_INVALID_REGNUM, fpu_cs},
 333      nullptr,
 334      nullptr,
 335      nullptr,
 336      0},
 337     {DEFINE_FPU_UINT(dp),
 338      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 339       LLDB_INVALID_REGNUM, fpu_dp},
 340      nullptr,
 341      nullptr,
 342      nullptr,
 343      0},
 344     {DEFINE_FPU_UINT(ds),
 345      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 346       LLDB_INVALID_REGNUM, fpu_ds},
 347      nullptr,
 348      nullptr,
 349      nullptr,
 350      0},
 351     {DEFINE_FPU_UINT(mxcsr),
 352      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 353       LLDB_INVALID_REGNUM, fpu_mxcsr},
 354      nullptr,
 355      nullptr,
 356      nullptr,
 357      0},
 358     {DEFINE_FPU_UINT(mxcsrmask),
 359      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 360       LLDB_INVALID_REGNUM, fpu_mxcsrmask},
 361      nullptr,
 362      nullptr,
 363      nullptr,
 364      0},
 365     {DEFINE_FPU_VECT(stmm, 0)},
 366     {DEFINE_FPU_VECT(stmm, 1)},
 367     {DEFINE_FPU_VECT(stmm, 2)},
 368     {DEFINE_FPU_VECT(stmm, 3)},
 369     {DEFINE_FPU_VECT(stmm, 4)},
 370     {DEFINE_FPU_VECT(stmm, 5)},
 371     {DEFINE_FPU_VECT(stmm, 6)},
 372     {DEFINE_FPU_VECT(stmm, 7)},
 373     {DEFINE_FPU_VECT(xmm, 0)},
 374     {DEFINE_FPU_VECT(xmm, 1)},
 375     {DEFINE_FPU_VECT(xmm, 2)},
 376     {DEFINE_FPU_VECT(xmm, 3)},
 377     {DEFINE_FPU_VECT(xmm, 4)},
 378     {DEFINE_FPU_VECT(xmm, 5)},
 379     {DEFINE_FPU_VECT(xmm, 6)},
 380     {DEFINE_FPU_VECT(xmm, 7)},
 381
 382     {DEFINE_EXC(trapno),
 383      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 384       LLDB_INVALID_REGNUM, exc_trapno},
 385      nullptr,
 386      nullptr,
 387      nullptr,
 388      0},
 389     {DEFINE_EXC(err),
 390      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 391       LLDB_INVALID_REGNUM, exc_err},
 392      nullptr,
 393      nullptr,
 394      nullptr,
 395      0},
 396     {DEFINE_EXC(faultvaddr),
 397      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 398       LLDB_INVALID_REGNUM, exc_faultvaddr},
 399      nullptr,
 400      nullptr,
 401      nullptr,
 402      0}};
 403
 404 static size_t k_num_register_infos = llvm::array_lengthof(g_register_infos);
 405
 406 RegisterContextDarwin_i386::RegisterContextDarwin_i386(
 407     Thread &thread, uint32_t concrete_frame_idx)
 408     : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() {
 409   uint32_t i;
 410   for (i = 0; i < kNumErrors; i++) {
 411     gpr_errs[i] = -1;
 412     fpu_errs[i] = -1;
 413     exc_errs[i] = -1;
 414   }
 415 }
 416
 417 RegisterContextDarwin_i386::~RegisterContextDarwin_i386() {}
 418
 419 void RegisterContextDarwin_i386::InvalidateAllRegisters() {
 420   InvalidateAllRegisterStates();
 421 }
 422
 423 size_t RegisterContextDarwin_i386::GetRegisterCount() {
 424   assert(k_num_register_infos == k_num_registers);
 425   return k_num_registers;
 426 }
 427
 428 const RegisterInfo *
 429 RegisterContextDarwin_i386::GetRegisterInfoAtIndex(size_t reg) {
 430   assert(k_num_register_infos == k_num_registers);
 431   if (reg < k_num_registers)
 432     return &g_register_infos[reg];
 433   return NULL;
 434 }
 435
 436 size_t RegisterContextDarwin_i386::GetRegisterInfosCount() {
 437   return k_num_register_infos;
 438 }
 439
 440 const RegisterInfo *RegisterContextDarwin_i386::GetRegisterInfos() {
 441   return g_register_infos;
 442 }
 443
 444 // General purpose registers
 445 static uint32_t g_gpr_regnums[] = {
 446     gpr_eax, gpr_ebx,    gpr_ecx, gpr_edx, gpr_edi, gpr_esi, gpr_ebp, gpr_esp,
 447     gpr_ss,  gpr_eflags, gpr_eip, gpr_cs,  gpr_ds,  gpr_es,  gpr_fs,  gpr_gs};
 448
 449 // Floating point registers
 450 static uint32_t g_fpu_regnums[] = {
 451     fpu_fcw,   fpu_fsw,   fpu_ftw,   fpu_fop,       fpu_ip,    fpu_cs,
 452     fpu_dp,    fpu_ds,    fpu_mxcsr, fpu_mxcsrmask, fpu_stmm0, fpu_stmm1,
 453     fpu_stmm2, fpu_stmm3, fpu_stmm4, fpu_stmm5,     fpu_stmm6, fpu_stmm7,
 454     fpu_xmm0,  fpu_xmm1,  fpu_xmm2,  fpu_xmm3,      fpu_xmm4,  fpu_xmm5,
 455     fpu_xmm6,  fpu_xmm7};
 456
 457 // Exception registers
 458
 459 static uint32_t g_exc_regnums[] = {exc_trapno, exc_err, exc_faultvaddr};
 460
 461 // Number of registers in each register set
 462 const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums);
 463 const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums);
 464 const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums);
 465
 466 //----------------------------------------------------------------------
 467 // Register set definitions. The first definitions at register set index of
 468 // zero is for all registers, followed by other registers sets. The register
 469 // information for the all register set need not be filled in.
 470 //----------------------------------------------------------------------
 471 static const RegisterSet g_reg_sets[] = {
 472     {
 473         "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums,
 474     },
 475     {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums},
 476     {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}};
 477
 478 const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets);
 479
 480 size_t RegisterContextDarwin_i386::GetRegisterSetCount() {
 481   return k_num_regsets;
 482 }
 483
 484 const RegisterSet *RegisterContextDarwin_i386::GetRegisterSet(size_t reg_set) {
 485   if (reg_set < k_num_regsets)
 486     return &g_reg_sets[reg_set];
 487   return NULL;
 488 }
 489
 490 //----------------------------------------------------------------------
 491 // Register information definitions for 32 bit i386.
 492 //----------------------------------------------------------------------
 493 int RegisterContextDarwin_i386::GetSetForNativeRegNum(int reg_num) {
 494   if (reg_num < fpu_fcw)
 495     return GPRRegSet;
 496   else if (reg_num < exc_trapno)
 497     return FPURegSet;
 498   else if (reg_num < k_num_registers)
 499     return EXCRegSet;
 500   return -1;
 501 }
 502
 503 void RegisterContextDarwin_i386::LogGPR(Log *log, const char *title) {
 504   if (log) {
 505     if (title)
 506       log->Printf("%s", title);
 507     for (uint32_t i = 0; i < k_num_gpr_registers; i++) {
 508       uint32_t reg = gpr_eax + i;
 509       log->Printf("%12s = 0x%8.8x", g_register_infos[reg].name,
 510                   (&gpr.eax)[reg]);
 511     }
 512   }
 513 }
 514
 515 int RegisterContextDarwin_i386::ReadGPR(bool force) {
 516   int set = GPRRegSet;
 517   if (force || !RegisterSetIsCached(set)) {
 518     SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
 519   }
 520   return GetError(set, Read);
 521 }
 522
 523 int RegisterContextDarwin_i386::ReadFPU(bool force) {
 524   int set = FPURegSet;
 525   if (force || !RegisterSetIsCached(set)) {
 526     SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu));
 527   }
 528   return GetError(set, Read);
 529 }
 530
 531 int RegisterContextDarwin_i386::ReadEXC(bool force) {
 532   int set = EXCRegSet;
 533   if (force || !RegisterSetIsCached(set)) {
 534     SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
 535   }
 536   return GetError(set, Read);
 537 }
 538
 539 int RegisterContextDarwin_i386::WriteGPR() {
 540   int set = GPRRegSet;
 541   if (!RegisterSetIsCached(set)) {
 542     SetError(set, Write, -1);
 543     return -1;
 544   }
 545   SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr));
 546   SetError(set, Read, -1);
 547   return GetError(set, Write);
 548 }
 549
 550 int RegisterContextDarwin_i386::WriteFPU() {
 551   int set = FPURegSet;
 552   if (!RegisterSetIsCached(set)) {
 553     SetError(set, Write, -1);
 554     return -1;
 555   }
 556   SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu));
 557   SetError(set, Read, -1);
 558   return GetError(set, Write);
 559 }
 560
 561 int RegisterContextDarwin_i386::WriteEXC() {
 562   int set = EXCRegSet;
 563   if (!RegisterSetIsCached(set)) {
 564     SetError(set, Write, -1);
 565     return -1;
 566   }
 567   SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc));
 568   SetError(set, Read, -1);
 569   return GetError(set, Write);
 570 }
 571
 572 int RegisterContextDarwin_i386::ReadRegisterSet(uint32_t set, bool force) {
 573   switch (set) {
 574   case GPRRegSet:
 575     return ReadGPR(force);
 576   case FPURegSet:
 577     return ReadFPU(force);
 578   case EXCRegSet:
 579     return ReadEXC(force);
 580   default:
 581     break;
 582   }
 583   return -1;
 584 }
 585
 586 int RegisterContextDarwin_i386::WriteRegisterSet(uint32_t set) {
 587   // Make sure we have a valid context to set.
 588   if (RegisterSetIsCached(set)) {
 589     switch (set) {
 590     case GPRRegSet:
 591       return WriteGPR();
 592     case FPURegSet:
 593       return WriteFPU();
 594     case EXCRegSet:
 595       return WriteEXC();
 596     default:
 597       break;
 598     }
 599   }
 600   return -1;
 601 }
 602
 603 bool RegisterContextDarwin_i386::ReadRegister(const RegisterInfo *reg_info,
 604                                               RegisterValue &value) {
 605   const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
 606   int set = RegisterContextDarwin_i386::GetSetForNativeRegNum(reg);
 607
 608   if (set == -1)
 609     return false;
 610
 611   if (ReadRegisterSet(set, false) != 0)
 612     return false;
 613
 614   switch (reg) {
 615   case gpr_eax:
 616   case gpr_ebx:
 617   case gpr_ecx:
 618   case gpr_edx:
 619   case gpr_edi:
 620   case gpr_esi:
 621   case gpr_ebp:
 622   case gpr_esp:
 623   case gpr_ss:
 624   case gpr_eflags:
 625   case gpr_eip:
 626   case gpr_cs:
 627   case gpr_ds:
 628   case gpr_es:
 629   case gpr_fs:
 630   case gpr_gs:
 631     value = (&gpr.eax)[reg - gpr_eax];
 632     break;
 633
 634   case fpu_fcw:
 635     value = fpu.fcw;
 636     break;
 637
 638   case fpu_fsw:
 639     value = fpu.fsw;
 640     break;
 641
 642   case fpu_ftw:
 643     value = fpu.ftw;
 644     break;
 645
 646   case fpu_fop:
 647     value = fpu.fop;
 648     break;
 649
 650   case fpu_ip:
 651     value = fpu.ip;
 652     break;
 653
 654   case fpu_cs:
 655     value = fpu.cs;
 656     break;
 657
 658   case fpu_dp:
 659     value = fpu.dp;
 660     break;
 661
 662   case fpu_ds:
 663     value = fpu.ds;
 664     break;
 665
 666   case fpu_mxcsr:
 667     value = fpu.mxcsr;
 668     break;
 669
 670   case fpu_mxcsrmask:
 671     value = fpu.mxcsrmask;
 672     break;
 673
 674   case fpu_stmm0:
 675   case fpu_stmm1:
 676   case fpu_stmm2:
 677   case fpu_stmm3:
 678   case fpu_stmm4:
 679   case fpu_stmm5:
 680   case fpu_stmm6:
 681   case fpu_stmm7:
 682     // These values don't fit into scalar types,
 683     // RegisterContext::ReadRegisterBytes() must be used for these registers
 684     //::memcpy (reg_value.value.vector.uint8, fpu.stmm[reg - fpu_stmm0].bytes,
 685     //10);
 686     return false;
 687
 688   case fpu_xmm0:
 689   case fpu_xmm1:
 690   case fpu_xmm2:
 691   case fpu_xmm3:
 692   case fpu_xmm4:
 693   case fpu_xmm5:
 694   case fpu_xmm6:
 695   case fpu_xmm7:
 696     // These values don't fit into scalar types,
 697     // RegisterContext::ReadRegisterBytes() must be used for these registers
 698     //::memcpy (reg_value.value.vector.uint8, fpu.xmm[reg - fpu_xmm0].bytes,
 699     //16);
 700     return false;
 701
 702   case exc_trapno:
 703     value = exc.trapno;
 704     break;
 705
 706   case exc_err:
 707     value = exc.err;
 708     break;
 709
 710   case exc_faultvaddr:
 711     value = exc.faultvaddr;
 712     break;
 713
 714   default:
 715     return false;
 716   }
 717   return true;
 718 }
 719
 720 bool RegisterContextDarwin_i386::WriteRegister(const RegisterInfo *reg_info,
 721                                                const RegisterValue &value) {
 722   const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
 723   int set = GetSetForNativeRegNum(reg);
 724
 725   if (set == -1)
 726     return false;
 727
 728   if (ReadRegisterSet(set, false) != 0)
 729     return false;
 730
 731   switch (reg) {
 732   case gpr_eax:
 733   case gpr_ebx:
 734   case gpr_ecx:
 735   case gpr_edx:
 736   case gpr_edi:
 737   case gpr_esi:
 738   case gpr_ebp:
 739   case gpr_esp:
 740   case gpr_ss:
 741   case gpr_eflags:
 742   case gpr_eip:
 743   case gpr_cs:
 744   case gpr_ds:
 745   case gpr_es:
 746   case gpr_fs:
 747   case gpr_gs:
 748     (&gpr.eax)[reg - gpr_eax] = value.GetAsUInt32();
 749     break;
 750
 751   case fpu_fcw:
 752     fpu.fcw = value.GetAsUInt16();
 753     break;
 754
 755   case fpu_fsw:
 756     fpu.fsw = value.GetAsUInt16();
 757     break;
 758
 759   case fpu_ftw:
 760     fpu.ftw = value.GetAsUInt8();
 761     break;
 762
 763   case fpu_fop:
 764     fpu.fop = value.GetAsUInt16();
 765     break;
 766
 767   case fpu_ip:
 768     fpu.ip = value.GetAsUInt32();
 769     break;
 770
 771   case fpu_cs:
 772     fpu.cs = value.GetAsUInt16();
 773     break;
 774
 775   case fpu_dp:
 776     fpu.dp = value.GetAsUInt32();
 777     break;
 778
 779   case fpu_ds:
 780     fpu.ds = value.GetAsUInt16();
 781     break;
 782
 783   case fpu_mxcsr:
 784     fpu.mxcsr = value.GetAsUInt32();
 785     break;
 786
 787   case fpu_mxcsrmask:
 788     fpu.mxcsrmask = value.GetAsUInt32();
 789     break;
 790
 791   case fpu_stmm0:
 792   case fpu_stmm1:
 793   case fpu_stmm2:
 794   case fpu_stmm3:
 795   case fpu_stmm4:
 796   case fpu_stmm5:
 797   case fpu_stmm6:
 798   case fpu_stmm7:
 799     // These values don't fit into scalar types,
 800     // RegisterContext::ReadRegisterBytes() must be used for these registers
 801     ::memcpy(fpu.stmm[reg - fpu_stmm0].bytes, value.GetBytes(),
 802              value.GetByteSize());
 803     return false;
 804
 805   case fpu_xmm0:
 806   case fpu_xmm1:
 807   case fpu_xmm2:
 808   case fpu_xmm3:
 809   case fpu_xmm4:
 810   case fpu_xmm5:
 811   case fpu_xmm6:
 812   case fpu_xmm7:
 813     // These values don't fit into scalar types,
 814     // RegisterContext::ReadRegisterBytes() must be used for these registers
 815     ::memcpy(fpu.xmm[reg - fpu_xmm0].bytes, value.GetBytes(),
 816              value.GetByteSize());
 817     return false;
 818
 819   case exc_trapno:
 820     exc.trapno = value.GetAsUInt32();
 821     break;
 822
 823   case exc_err:
 824     exc.err = value.GetAsUInt32();
 825     break;
 826
 827   case exc_faultvaddr:
 828     exc.faultvaddr = value.GetAsUInt32();
 829     break;
 830
 831   default:
 832     return false;
 833   }
 834   return WriteRegisterSet(set) == 0;
 835 }
 836
 837 bool RegisterContextDarwin_i386::ReadAllRegisterValues(
 838     lldb::DataBufferSP &data_sp) {
 839   data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0));
 840   if (data_sp && ReadGPR(false) == 0 && ReadFPU(false) == 0 &&
 841       ReadEXC(false) == 0) {
 842     uint8_t *dst = data_sp->GetBytes();
 843     ::memcpy(dst, &gpr, sizeof(gpr));
 844     dst += sizeof(gpr);
 845
 846     ::memcpy(dst, &fpu, sizeof(fpu));
 847     dst += sizeof(gpr);
 848
 849     ::memcpy(dst, &exc, sizeof(exc));
 850     return true;
 851   }
 852   return false;
 853 }
 854
 855 bool RegisterContextDarwin_i386::WriteAllRegisterValues(
 856     const lldb::DataBufferSP &data_sp) {
 857   if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) {
 858     const uint8_t *src = data_sp->GetBytes();
 859     ::memcpy(&gpr, src, sizeof(gpr));
 860     src += sizeof(gpr);
 861
 862     ::memcpy(&fpu, src, sizeof(fpu));
 863     src += sizeof(gpr);
 864
 865     ::memcpy(&exc, src, sizeof(exc));
 866     uint32_t success_count = 0;
 867     if (WriteGPR() == 0)
 868       ++success_count;
 869     if (WriteFPU() == 0)
 870       ++success_count;
 871     if (WriteEXC() == 0)
 872       ++success_count;
 873     return success_count == 3;
 874   }
 875   return false;
 876 }
 877
 878 uint32_t RegisterContextDarwin_i386::ConvertRegisterKindToRegisterNumber(
 879     lldb::RegisterKind kind, uint32_t reg) {
 880   if (kind == eRegisterKindGeneric) {
 881     switch (reg) {
 882     case LLDB_REGNUM_GENERIC_PC:
 883       return gpr_eip;
 884     case LLDB_REGNUM_GENERIC_SP:
 885       return gpr_esp;
 886     case LLDB_REGNUM_GENERIC_FP:
 887       return gpr_ebp;
 888     case LLDB_REGNUM_GENERIC_FLAGS:
 889       return gpr_eflags;
 890     case LLDB_REGNUM_GENERIC_RA:
 891     default:
 892       break;
 893     }
 894   } else if (kind == eRegisterKindEHFrame || kind == eRegisterKindDWARF) {
 895     switch (reg) {
 896     case dwarf_eax:
 897       return gpr_eax;
 898     case dwarf_ecx:
 899       return gpr_ecx;
 900     case dwarf_edx:
 901       return gpr_edx;
 902     case dwarf_ebx:
 903       return gpr_ebx;
 904     case dwarf_esp:
 905       return gpr_esp;
 906     case dwarf_ebp:
 907       return gpr_ebp;
 908     case dwarf_esi:
 909       return gpr_esi;
 910     case dwarf_edi:
 911       return gpr_edi;
 912     case dwarf_eip:
 913       return gpr_eip;
 914     case dwarf_eflags:
 915       return gpr_eflags;
 916     case dwarf_stmm0:
 917       return fpu_stmm0;
 918     case dwarf_stmm1:
 919       return fpu_stmm1;
 920     case dwarf_stmm2:
 921       return fpu_stmm2;
 922     case dwarf_stmm3:
 923       return fpu_stmm3;
 924     case dwarf_stmm4:
 925       return fpu_stmm4;
 926     case dwarf_stmm5:
 927       return fpu_stmm5;
 928     case dwarf_stmm6:
 929       return fpu_stmm6;
 930     case dwarf_stmm7:
 931       return fpu_stmm7;
 932     case dwarf_xmm0:
 933       return fpu_xmm0;
 934     case dwarf_xmm1:
 935       return fpu_xmm1;
 936     case dwarf_xmm2:
 937       return fpu_xmm2;
 938     case dwarf_xmm3:
 939       return fpu_xmm3;
 940     case dwarf_xmm4:
 941       return fpu_xmm4;
 942     case dwarf_xmm5:
 943       return fpu_xmm5;
 944     case dwarf_xmm6:
 945       return fpu_xmm6;
 946     case dwarf_xmm7:
 947       return fpu_xmm7;
 948     default:
 949       break;
 950     }
 951   } else if (kind == eRegisterKindLLDB) {
 952     return reg;
 953   }
 954   return LLDB_INVALID_REGNUM;
 955 }
 956
 957 bool RegisterContextDarwin_i386::HardwareSingleStep(bool enable) {
 958   if (ReadGPR(false) != 0)
 959     return false;
 960
 961   const uint32_t trace_bit = 0x100u;
 962   if (enable) {
 963     // If the trace bit is already set, there is nothing to do
 964     if (gpr.eflags & trace_bit)
 965       return true;
 966     else
 967       gpr.eflags |= trace_bit;
 968   } else {
 969     // If the trace bit is already cleared, there is nothing to do
 970     if (gpr.eflags & trace_bit)
 971       gpr.eflags &= ~trace_bit;
 972     else
 973       return true;
 974   }
 975
 976   return WriteGPR() == 0;
 977 }