1 //===-- RegisterContextDarwin_i386.cpp --------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 #include <stddef.h> // offsetof
15 // Other libraries and framework includes
16 #include "lldb/Core/DataBufferHeap.h"
17 #include "lldb/Core/DataExtractor.h"
18 #include "lldb/Core/Log.h"
19 #include "lldb/Core/RegisterValue.h"
20 #include "lldb/Core/Scalar.h"
21 #include "lldb/Host/Endian.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/Support/Compiler.h"
25 // Support building against older versions of LLVM, this macro was added
27 #ifndef LLVM_EXTENSION
28 #define LLVM_EXTENSION
32 #include "RegisterContextDarwin_i386.h"
35 using namespace lldb_private;
144 #define GPR_OFFSET(reg) (LLVM_EXTENSION offsetof (RegisterContextDarwin_i386::GPR, reg))
145 #define FPU_OFFSET(reg) (LLVM_EXTENSION offsetof (RegisterContextDarwin_i386::FPU, reg) + sizeof (RegisterContextDarwin_i386::GPR))
146 #define EXC_OFFSET(reg) (LLVM_EXTENSION offsetof (RegisterContextDarwin_i386::EXC, reg) + sizeof (RegisterContextDarwin_i386::GPR) + sizeof (RegisterContextDarwin_i386::FPU))
148 // These macros will auto define the register name, alt name, register size,
149 // register offset, encoding, format and native register. This ensures that
150 // the register state structures are defined correctly and have the correct
151 // sizes and offsets.
152 #define DEFINE_GPR(reg, alt) #reg, alt, sizeof(((RegisterContextDarwin_i386::GPR *)NULL)->reg), GPR_OFFSET(reg), eEncodingUint, eFormatHex
153 #define DEFINE_FPU_UINT(reg) #reg, NULL, sizeof(((RegisterContextDarwin_i386::FPU *)NULL)->reg), FPU_OFFSET(reg), eEncodingUint, eFormatHex
154 #define DEFINE_FPU_VECT(reg, i) #reg#i, NULL, sizeof(((RegisterContextDarwin_i386::FPU *)NULL)->reg[i].bytes), FPU_OFFSET(reg[i]), eEncodingVector, eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, dwarf_##reg##i, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_##reg##i }, NULL, NULL
156 #define DEFINE_EXC(reg) #reg, NULL, sizeof(((RegisterContextDarwin_i386::EXC *)NULL)->reg), EXC_OFFSET(reg), eEncodingUint, eFormatHex
157 #define REG_CONTEXT_SIZE (sizeof (RegisterContextDarwin_i386::GPR) + sizeof (RegisterContextDarwin_i386::FPU) + sizeof (RegisterContextDarwin_i386::EXC))
159 static RegisterInfo g_register_infos[] =
161 // Macro auto defines most stuff eh_frame DWARF GENERIC PROCESS PLUGIN LLDB VALUE REGS INVALIDATE REGS
162 // =============================== ======================= =================== ========================= ================== ================= ========== ===============
163 { DEFINE_GPR(eax , NULL) , { ehframe_eax , dwarf_eax , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, gpr_eax }, NULL, NULL},
164 { DEFINE_GPR(ebx , NULL) , { ehframe_ebx , dwarf_ebx , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, gpr_ebx }, NULL, NULL},
165 { DEFINE_GPR(ecx , NULL) , { ehframe_ecx , dwarf_ecx , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, gpr_ecx }, NULL, NULL},
166 { DEFINE_GPR(edx , NULL) , { ehframe_edx , dwarf_edx , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, gpr_edx }, NULL, NULL},
167 { DEFINE_GPR(edi , NULL) , { ehframe_edi , dwarf_edi , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, gpr_edi }, NULL, NULL},
168 { DEFINE_GPR(esi , NULL) , { ehframe_esi , dwarf_esi , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, gpr_esi }, NULL, NULL},
169 { DEFINE_GPR(ebp , "fp") , { ehframe_ebp , dwarf_ebp , LLDB_REGNUM_GENERIC_FP , LLDB_INVALID_REGNUM, gpr_ebp }, NULL, NULL},
170 { DEFINE_GPR(esp , "sp") , { ehframe_esp , dwarf_esp , LLDB_REGNUM_GENERIC_SP , LLDB_INVALID_REGNUM, gpr_esp }, NULL, NULL},
171 { DEFINE_GPR(ss , NULL) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, gpr_ss }, NULL, NULL},
172 { DEFINE_GPR(eflags , "flags") , { ehframe_eflags , dwarf_eflags , LLDB_REGNUM_GENERIC_FLAGS , LLDB_INVALID_REGNUM, gpr_eflags }, NULL, NULL},
173 { DEFINE_GPR(eip , "pc") , { ehframe_eip , dwarf_eip , LLDB_REGNUM_GENERIC_PC , LLDB_INVALID_REGNUM, gpr_eip }, NULL, NULL},
174 { DEFINE_GPR(cs , NULL) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, gpr_cs }, NULL, NULL},
175 { DEFINE_GPR(ds , NULL) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, gpr_ds }, NULL, NULL},
176 { DEFINE_GPR(es , NULL) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, gpr_es }, NULL, NULL},
177 { DEFINE_GPR(fs , NULL) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, gpr_fs }, NULL, NULL},
178 { DEFINE_GPR(gs , NULL) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, gpr_gs }, NULL, NULL},
180 { DEFINE_FPU_UINT(fcw) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, fpu_fcw }, NULL, NULL},
181 { DEFINE_FPU_UINT(fsw) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, fpu_fsw }, NULL, NULL},
182 { DEFINE_FPU_UINT(ftw) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, fpu_ftw }, NULL, NULL},
183 { DEFINE_FPU_UINT(fop) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, fpu_fop }, NULL, NULL},
184 { DEFINE_FPU_UINT(ip) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, fpu_ip }, NULL, NULL},
185 { DEFINE_FPU_UINT(cs) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, fpu_cs }, NULL, NULL},
186 { DEFINE_FPU_UINT(dp) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, fpu_dp }, NULL, NULL},
187 { DEFINE_FPU_UINT(ds) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, fpu_ds }, NULL, NULL},
188 { DEFINE_FPU_UINT(mxcsr) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, fpu_mxcsr }, NULL, NULL},
189 { DEFINE_FPU_UINT(mxcsrmask) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, fpu_mxcsrmask}, NULL, NULL},
190 { DEFINE_FPU_VECT(stmm,0) },
191 { DEFINE_FPU_VECT(stmm,1) },
192 { DEFINE_FPU_VECT(stmm,2) },
193 { DEFINE_FPU_VECT(stmm,3) },
194 { DEFINE_FPU_VECT(stmm,4) },
195 { DEFINE_FPU_VECT(stmm,5) },
196 { DEFINE_FPU_VECT(stmm,6) },
197 { DEFINE_FPU_VECT(stmm,7) },
198 { DEFINE_FPU_VECT(xmm,0) },
199 { DEFINE_FPU_VECT(xmm,1) },
200 { DEFINE_FPU_VECT(xmm,2) },
201 { DEFINE_FPU_VECT(xmm,3) },
202 { DEFINE_FPU_VECT(xmm,4) },
203 { DEFINE_FPU_VECT(xmm,5) },
204 { DEFINE_FPU_VECT(xmm,6) },
205 { DEFINE_FPU_VECT(xmm,7) },
207 { DEFINE_EXC(trapno) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, exc_trapno }, NULL, NULL},
208 { DEFINE_EXC(err) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, exc_err }, NULL, NULL},
209 { DEFINE_EXC(faultvaddr) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, exc_faultvaddr }, NULL, NULL}
212 static size_t k_num_register_infos = llvm::array_lengthof(g_register_infos);
214 RegisterContextDarwin_i386::RegisterContextDarwin_i386 (Thread &thread, uint32_t concrete_frame_idx) :
215 RegisterContext(thread, concrete_frame_idx),
221 for (i=0; i<kNumErrors; i++)
229 RegisterContextDarwin_i386::~RegisterContextDarwin_i386()
235 RegisterContextDarwin_i386::InvalidateAllRegisters ()
237 InvalidateAllRegisterStates();
242 RegisterContextDarwin_i386::GetRegisterCount ()
244 assert(k_num_register_infos == k_num_registers);
245 return k_num_registers;
249 RegisterContextDarwin_i386::GetRegisterInfoAtIndex (size_t reg)
251 assert(k_num_register_infos == k_num_registers);
252 if (reg < k_num_registers)
253 return &g_register_infos[reg];
258 RegisterContextDarwin_i386::GetRegisterInfosCount ()
260 return k_num_register_infos;
264 RegisterContextDarwin_i386::GetRegisterInfos ()
266 return g_register_infos;
270 // General purpose registers
292 // Floating point registers
324 // Exception registers
334 // Number of registers in each register set
335 const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums);
336 const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums);
337 const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums);
339 //----------------------------------------------------------------------
340 // Register set definitions. The first definitions at register set index
341 // of zero is for all registers, followed by other registers sets. The
342 // register information for the all register set need not be filled in.
343 //----------------------------------------------------------------------
344 static const RegisterSet g_reg_sets[] =
346 { "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums, },
347 { "Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums },
348 { "Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums }
351 const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets);
355 RegisterContextDarwin_i386::GetRegisterSetCount ()
357 return k_num_regsets;
361 RegisterContextDarwin_i386::GetRegisterSet (size_t reg_set)
363 if (reg_set < k_num_regsets)
364 return &g_reg_sets[reg_set];
369 //----------------------------------------------------------------------
370 // Register information definitions for 32 bit i386.
371 //----------------------------------------------------------------------
373 RegisterContextDarwin_i386::GetSetForNativeRegNum (int reg_num)
375 if (reg_num < fpu_fcw)
377 else if (reg_num < exc_trapno)
379 else if (reg_num < k_num_registers)
386 RegisterContextDarwin_i386::LogGPR(Log *log, const char *title)
391 log->Printf ("%s", title);
392 for (uint32_t i=0; i<k_num_gpr_registers; i++)
394 uint32_t reg = gpr_eax + i;
395 log->Printf("%12s = 0x%8.8x", g_register_infos[reg].name, (&gpr.eax)[reg]);
403 RegisterContextDarwin_i386::ReadGPR (bool force)
406 if (force || !RegisterSetIsCached(set))
408 SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
410 return GetError(set, Read);
414 RegisterContextDarwin_i386::ReadFPU (bool force)
417 if (force || !RegisterSetIsCached(set))
419 SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu));
421 return GetError(set, Read);
425 RegisterContextDarwin_i386::ReadEXC (bool force)
428 if (force || !RegisterSetIsCached(set))
430 SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
432 return GetError(set, Read);
436 RegisterContextDarwin_i386::WriteGPR ()
439 if (!RegisterSetIsCached(set))
441 SetError (set, Write, -1);
444 SetError (set, Write, DoWriteGPR(GetThreadID(), set, gpr));
445 SetError (set, Read, -1);
446 return GetError(set, Write);
450 RegisterContextDarwin_i386::WriteFPU ()
453 if (!RegisterSetIsCached(set))
455 SetError (set, Write, -1);
458 SetError (set, Write, DoWriteFPU(GetThreadID(), set, fpu));
459 SetError (set, Read, -1);
460 return GetError(set, Write);
464 RegisterContextDarwin_i386::WriteEXC ()
467 if (!RegisterSetIsCached(set))
469 SetError (set, Write, -1);
472 SetError (set, Write, DoWriteEXC(GetThreadID(), set, exc));
473 SetError (set, Read, -1);
474 return GetError(set, Write);
478 RegisterContextDarwin_i386::ReadRegisterSet (uint32_t set, bool force)
482 case GPRRegSet: return ReadGPR(force);
483 case FPURegSet: return ReadFPU(force);
484 case EXCRegSet: return ReadEXC(force);
491 RegisterContextDarwin_i386::WriteRegisterSet (uint32_t set)
493 // Make sure we have a valid context to set.
494 if (RegisterSetIsCached(set))
498 case GPRRegSet: return WriteGPR();
499 case FPURegSet: return WriteFPU();
500 case EXCRegSet: return WriteEXC();
508 RegisterContextDarwin_i386::ReadRegister (const RegisterInfo *reg_info,
509 RegisterValue &value)
511 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
512 int set = RegisterContextDarwin_i386::GetSetForNativeRegNum (reg);
517 if (ReadRegisterSet(set, false) != 0)
538 value = (&gpr.eax)[reg - gpr_eax];
578 value = fpu.mxcsrmask;
589 // These values don't fit into scalar types,
590 // RegisterContext::ReadRegisterBytes() must be used for these
592 //::memcpy (reg_value.value.vector.uint8, fpu.stmm[reg - fpu_stmm0].bytes, 10);
603 // These values don't fit into scalar types, RegisterContext::ReadRegisterBytes()
604 // must be used for these registers
605 //::memcpy (reg_value.value.vector.uint8, fpu.xmm[reg - fpu_xmm0].bytes, 16);
617 value = exc.faultvaddr;
628 RegisterContextDarwin_i386::WriteRegister (const RegisterInfo *reg_info,
629 const RegisterValue &value)
631 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
632 int set = GetSetForNativeRegNum (reg);
637 if (ReadRegisterSet(set, false) != 0)
658 (&gpr.eax)[reg - gpr_eax] = value.GetAsUInt32();
662 fpu.fcw = value.GetAsUInt16();
666 fpu.fsw = value.GetAsUInt16();
670 fpu.ftw = value.GetAsUInt8();
674 fpu.fop = value.GetAsUInt16();
678 fpu.ip = value.GetAsUInt32();
682 fpu.cs = value.GetAsUInt16();
686 fpu.dp = value.GetAsUInt32();
690 fpu.ds = value.GetAsUInt16();
694 fpu.mxcsr = value.GetAsUInt32();
698 fpu.mxcsrmask = value.GetAsUInt32();
709 // These values don't fit into scalar types, RegisterContext::ReadRegisterBytes()
710 // must be used for these registers
711 ::memcpy (fpu.stmm[reg - fpu_stmm0].bytes, value.GetBytes(), value.GetByteSize());
722 // These values don't fit into scalar types, RegisterContext::ReadRegisterBytes()
723 // must be used for these registers
724 ::memcpy (fpu.xmm[reg - fpu_xmm0].bytes, value.GetBytes(), value.GetByteSize());
728 exc.trapno = value.GetAsUInt32();
732 exc.err = value.GetAsUInt32();
736 exc.faultvaddr = value.GetAsUInt32();
742 return WriteRegisterSet(set) == 0;
746 RegisterContextDarwin_i386::ReadAllRegisterValues (lldb::DataBufferSP &data_sp)
748 data_sp.reset (new DataBufferHeap (REG_CONTEXT_SIZE, 0));
750 ReadGPR (false) == 0 &&
751 ReadFPU (false) == 0 &&
752 ReadEXC (false) == 0)
754 uint8_t *dst = data_sp->GetBytes();
755 ::memcpy (dst, &gpr, sizeof(gpr));
758 ::memcpy (dst, &fpu, sizeof(fpu));
761 ::memcpy (dst, &exc, sizeof(exc));
768 RegisterContextDarwin_i386::WriteAllRegisterValues (const lldb::DataBufferSP &data_sp)
770 if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE)
772 const uint8_t *src = data_sp->GetBytes();
773 ::memcpy (&gpr, src, sizeof(gpr));
776 ::memcpy (&fpu, src, sizeof(fpu));
779 ::memcpy (&exc, src, sizeof(exc));
780 uint32_t success_count = 0;
787 return success_count == 3;
794 RegisterContextDarwin_i386::ConvertRegisterKindToRegisterNumber (lldb::RegisterKind kind, uint32_t reg)
796 if (kind == eRegisterKindGeneric)
800 case LLDB_REGNUM_GENERIC_PC: return gpr_eip;
801 case LLDB_REGNUM_GENERIC_SP: return gpr_esp;
802 case LLDB_REGNUM_GENERIC_FP: return gpr_ebp;
803 case LLDB_REGNUM_GENERIC_FLAGS: return gpr_eflags;
804 case LLDB_REGNUM_GENERIC_RA:
809 else if (kind == eRegisterKindEHFrame || kind == eRegisterKindDWARF)
813 case dwarf_eax: return gpr_eax;
814 case dwarf_ecx: return gpr_ecx;
815 case dwarf_edx: return gpr_edx;
816 case dwarf_ebx: return gpr_ebx;
817 case dwarf_esp: return gpr_esp;
818 case dwarf_ebp: return gpr_ebp;
819 case dwarf_esi: return gpr_esi;
820 case dwarf_edi: return gpr_edi;
821 case dwarf_eip: return gpr_eip;
822 case dwarf_eflags: return gpr_eflags;
823 case dwarf_stmm0: return fpu_stmm0;
824 case dwarf_stmm1: return fpu_stmm1;
825 case dwarf_stmm2: return fpu_stmm2;
826 case dwarf_stmm3: return fpu_stmm3;
827 case dwarf_stmm4: return fpu_stmm4;
828 case dwarf_stmm5: return fpu_stmm5;
829 case dwarf_stmm6: return fpu_stmm6;
830 case dwarf_stmm7: return fpu_stmm7;
831 case dwarf_xmm0: return fpu_xmm0;
832 case dwarf_xmm1: return fpu_xmm1;
833 case dwarf_xmm2: return fpu_xmm2;
834 case dwarf_xmm3: return fpu_xmm3;
835 case dwarf_xmm4: return fpu_xmm4;
836 case dwarf_xmm5: return fpu_xmm5;
837 case dwarf_xmm6: return fpu_xmm6;
838 case dwarf_xmm7: return fpu_xmm7;
843 else if (kind == eRegisterKindLLDB)
847 return LLDB_INVALID_REGNUM;
852 RegisterContextDarwin_i386::HardwareSingleStep (bool enable)
854 if (ReadGPR(false) != 0)
857 const uint32_t trace_bit = 0x100u;
860 // If the trace bit is already set, there is nothing to do
861 if (gpr.eflags & trace_bit)
864 gpr.eflags |= trace_bit;
868 // If the trace bit is already cleared, there is nothing to do
869 if (gpr.eflags & trace_bit)
870 gpr.eflags &= ~trace_bit;
875 return WriteGPR() == 0;