contrib/llvm/tools/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.cpp

   1 //===-- RegisterContextPOSIX_arm.cpp --------------------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #include <cstring>
  11 #include <errno.h>
  12 #include <stdint.h>
  13
  14 #include "lldb/Core/RegisterValue.h"
  15 #include "lldb/Core/Scalar.h"
  16 #include "lldb/Target/Target.h"
  17 #include "lldb/Target/Thread.h"
  18 #include "lldb/Utility/DataBufferHeap.h"
  19 #include "lldb/Utility/DataExtractor.h"
  20 #include "lldb/Utility/Endian.h"
  21 #include "llvm/Support/Compiler.h"
  22
  23 #include "Plugins/Process/elf-core/ProcessElfCore.h"
  24 #include "RegisterContextPOSIX_arm.h"
  25
  26 using namespace lldb;
  27 using namespace lldb_private;
  28
  29 // arm general purpose registers.
  30 const uint32_t g_gpr_regnums_arm[] = {
  31     gpr_r0_arm,         gpr_r1_arm,   gpr_r2_arm,  gpr_r3_arm, gpr_r4_arm,
  32     gpr_r5_arm,         gpr_r6_arm,   gpr_r7_arm,  gpr_r8_arm, gpr_r9_arm,
  33     gpr_r10_arm,        gpr_r11_arm,  gpr_r12_arm, gpr_sp_arm, gpr_lr_arm,
  34     gpr_pc_arm,         gpr_cpsr_arm,
  35     LLDB_INVALID_REGNUM // register sets need to end with this flag
  36
  37 };
  38 static_assert(((sizeof g_gpr_regnums_arm / sizeof g_gpr_regnums_arm[0]) - 1) ==
  39                   k_num_gpr_registers_arm,
  40               "g_gpr_regnums_arm has wrong number of register infos");
  41
  42 // arm floating point registers.
  43 static const uint32_t g_fpu_regnums_arm[] = {
  44     fpu_s0_arm,         fpu_s1_arm,  fpu_s2_arm,    fpu_s3_arm,  fpu_s4_arm,
  45     fpu_s5_arm,         fpu_s6_arm,  fpu_s7_arm,    fpu_s8_arm,  fpu_s9_arm,
  46     fpu_s10_arm,        fpu_s11_arm, fpu_s12_arm,   fpu_s13_arm, fpu_s14_arm,
  47     fpu_s15_arm,        fpu_s16_arm, fpu_s17_arm,   fpu_s18_arm, fpu_s19_arm,
  48     fpu_s20_arm,        fpu_s21_arm, fpu_s22_arm,   fpu_s23_arm, fpu_s24_arm,
  49     fpu_s25_arm,        fpu_s26_arm, fpu_s27_arm,   fpu_s28_arm, fpu_s29_arm,
  50     fpu_s30_arm,        fpu_s31_arm, fpu_fpscr_arm, fpu_d0_arm,  fpu_d1_arm,
  51     fpu_d2_arm,         fpu_d3_arm,  fpu_d4_arm,    fpu_d5_arm,  fpu_d6_arm,
  52     fpu_d7_arm,         fpu_d8_arm,  fpu_d9_arm,    fpu_d10_arm, fpu_d11_arm,
  53     fpu_d12_arm,        fpu_d13_arm, fpu_d14_arm,   fpu_d15_arm, fpu_d16_arm,
  54     fpu_d17_arm,        fpu_d18_arm, fpu_d19_arm,   fpu_d20_arm, fpu_d21_arm,
  55     fpu_d22_arm,        fpu_d23_arm, fpu_d24_arm,   fpu_d25_arm, fpu_d26_arm,
  56     fpu_d27_arm,        fpu_d28_arm, fpu_d29_arm,   fpu_d30_arm, fpu_d31_arm,
  57     fpu_q0_arm,         fpu_q1_arm,  fpu_q2_arm,    fpu_q3_arm,  fpu_q4_arm,
  58     fpu_q5_arm,         fpu_q6_arm,  fpu_q7_arm,    fpu_q8_arm,  fpu_q9_arm,
  59     fpu_q10_arm,        fpu_q11_arm, fpu_q12_arm,   fpu_q13_arm, fpu_q14_arm,
  60     fpu_q15_arm,
  61     LLDB_INVALID_REGNUM // register sets need to end with this flag
  62
  63 };
  64 static_assert(((sizeof g_fpu_regnums_arm / sizeof g_fpu_regnums_arm[0]) - 1) ==
  65                   k_num_fpr_registers_arm,
  66               "g_fpu_regnums_arm has wrong number of register infos");
  67
  68 // Number of register sets provided by this context.
  69 enum { k_num_register_sets = 2 };
  70
  71 // Register sets for arm.
  72 static const lldb_private::RegisterSet g_reg_sets_arm[k_num_register_sets] = {
  73     {"General Purpose Registers", "gpr", k_num_gpr_registers_arm,
  74      g_gpr_regnums_arm},
  75     {"Floating Point Registers", "fpu", k_num_fpr_registers_arm,
  76      g_fpu_regnums_arm}};
  77
  78 bool RegisterContextPOSIX_arm::IsGPR(unsigned reg) {
  79   return reg <= m_reg_info.last_gpr; // GPR's come first.
  80 }
  81
  82 bool RegisterContextPOSIX_arm::IsFPR(unsigned reg) {
  83   return (m_reg_info.first_fpr <= reg && reg <= m_reg_info.last_fpr);
  84 }
  85
  86 RegisterContextPOSIX_arm::RegisterContextPOSIX_arm(
  87     lldb_private::Thread &thread, uint32_t concrete_frame_idx,
  88     lldb_private::RegisterInfoInterface *register_info)
  89     : lldb_private::RegisterContext(thread, concrete_frame_idx) {
  90   m_register_info_ap.reset(register_info);
  91
  92   switch (register_info->m_target_arch.GetMachine()) {
  93   case llvm::Triple::arm:
  94     m_reg_info.num_registers = k_num_registers_arm;
  95     m_reg_info.num_gpr_registers = k_num_gpr_registers_arm;
  96     m_reg_info.num_fpr_registers = k_num_fpr_registers_arm;
  97     m_reg_info.last_gpr = k_last_gpr_arm;
  98     m_reg_info.first_fpr = k_first_fpr_arm;
  99     m_reg_info.last_fpr = k_last_fpr_arm;
 100     m_reg_info.first_fpr_v = fpu_s0_arm;
 101     m_reg_info.last_fpr_v = fpu_s31_arm;
 102     m_reg_info.gpr_flags = gpr_cpsr_arm;
 103     break;
 104   default:
 105     assert(false && "Unhandled target architecture.");
 106     break;
 107   }
 108
 109   ::memset(&m_fpr, 0, sizeof m_fpr);
 110
 111   // elf-core yet to support ReadFPR()
 112   lldb::ProcessSP base = CalculateProcess();
 113   if (base.get()->GetPluginName() == ProcessElfCore::GetPluginNameStatic())
 114     return;
 115 }
 116
 117 RegisterContextPOSIX_arm::~RegisterContextPOSIX_arm() {}
 118
 119 void RegisterContextPOSIX_arm::Invalidate() {}
 120
 121 void RegisterContextPOSIX_arm::InvalidateAllRegisters() {}
 122
 123 unsigned RegisterContextPOSIX_arm::GetRegisterOffset(unsigned reg) {
 124   assert(reg < m_reg_info.num_registers && "Invalid register number.");
 125   return GetRegisterInfo()[reg].byte_offset;
 126 }
 127
 128 unsigned RegisterContextPOSIX_arm::GetRegisterSize(unsigned reg) {
 129   assert(reg < m_reg_info.num_registers && "Invalid register number.");
 130   return GetRegisterInfo()[reg].byte_size;
 131 }
 132
 133 size_t RegisterContextPOSIX_arm::GetRegisterCount() {
 134   size_t num_registers =
 135       m_reg_info.num_gpr_registers + m_reg_info.num_fpr_registers;
 136   return num_registers;
 137 }
 138
 139 size_t RegisterContextPOSIX_arm::GetGPRSize() {
 140   return m_register_info_ap->GetGPRSize();
 141 }
 142
 143 const lldb_private::RegisterInfo *RegisterContextPOSIX_arm::GetRegisterInfo() {
 144   // Commonly, this method is overridden and g_register_infos is copied and
 145   // specialized.
 146   // So, use GetRegisterInfo() rather than g_register_infos in this scope.
 147   return m_register_info_ap->GetRegisterInfo();
 148 }
 149
 150 const lldb_private::RegisterInfo *
 151 RegisterContextPOSIX_arm::GetRegisterInfoAtIndex(size_t reg) {
 152   if (reg < m_reg_info.num_registers)
 153     return &GetRegisterInfo()[reg];
 154   else
 155     return NULL;
 156 }
 157
 158 size_t RegisterContextPOSIX_arm::GetRegisterSetCount() {
 159   size_t sets = 0;
 160   for (size_t set = 0; set < k_num_register_sets; ++set) {
 161     if (IsRegisterSetAvailable(set))
 162       ++sets;
 163   }
 164
 165   return sets;
 166 }
 167
 168 const lldb_private::RegisterSet *
 169 RegisterContextPOSIX_arm::GetRegisterSet(size_t set) {
 170   if (IsRegisterSetAvailable(set)) {
 171     switch (m_register_info_ap->m_target_arch.GetMachine()) {
 172     case llvm::Triple::arm:
 173       return &g_reg_sets_arm[set];
 174     default:
 175       assert(false && "Unhandled target architecture.");
 176       return NULL;
 177     }
 178   }
 179   return NULL;
 180 }
 181
 182 const char *RegisterContextPOSIX_arm::GetRegisterName(unsigned reg) {
 183   assert(reg < m_reg_info.num_registers && "Invalid register offset.");
 184   return GetRegisterInfo()[reg].name;
 185 }
 186
 187 lldb::ByteOrder RegisterContextPOSIX_arm::GetByteOrder() {
 188   // Get the target process whose privileged thread was used for the register
 189   // read.
 190   lldb::ByteOrder byte_order = lldb::eByteOrderInvalid;
 191   lldb_private::Process *process = CalculateProcess().get();
 192
 193   if (process)
 194     byte_order = process->GetByteOrder();
 195   return byte_order;
 196 }
 197
 198 bool RegisterContextPOSIX_arm::IsRegisterSetAvailable(size_t set_index) {
 199   return set_index < k_num_register_sets;
 200 }
 201
 202 // Used when parsing DWARF and EH frame information and any other
 203 // object file sections that contain register numbers in them.
 204 uint32_t RegisterContextPOSIX_arm::ConvertRegisterKindToRegisterNumber(
 205     lldb::RegisterKind kind, uint32_t num) {
 206   const uint32_t num_regs = GetRegisterCount();
 207
 208   assert(kind < lldb::kNumRegisterKinds);
 209   for (uint32_t reg_idx = 0; reg_idx < num_regs; ++reg_idx) {
 210     const lldb_private::RegisterInfo *reg_info =
 211         GetRegisterInfoAtIndex(reg_idx);
 212
 213     if (reg_info->kinds[kind] == num)
 214       return reg_idx;
 215   }
 216
 217   return LLDB_INVALID_REGNUM;
 218 }