1 //===-- RegisterContext_x86.h -----------------------------------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 #ifndef liblldb_RegisterContext_x86_H_
10 #define liblldb_RegisterContext_x86_H_
15 #include "llvm/ADT/BitmaskEnum.h"
16 #include "llvm/Support/Compiler.h"
18 namespace lldb_private {
19 // i386 ehframe, dwarf regnums
21 // Register numbers seen in eh_frame (eRegisterKindEHFrame) on i386 systems
30 // on Darwin esp & ebp are reversed in the eh_frame section for i386 (versus
31 // dwarf's reg numbering).
33 // i386+darwin eh_frame: 4 is ebp, 5 is esp
34 // i386+everyone else eh_frame: 4 is esp, 5 is ebp
35 // i386 dwarf: 4 is esp, 5 is ebp
36 // lldb will get the darwin-specific eh_frame reg numberings from debugserver,
38 // only encode the generally correct 4 == esp, 5 == ebp numbers in this
47 ehframe_st0_i386 = 12,
55 ehframe_xmm0_i386 = 21,
63 ehframe_mm0_i386 = 29,
73 // DWARF register numbers (eRegisterKindDWARF)
74 // Intel's x86 or IA-32
76 // General Purpose Registers.
87 // Floating Point Registers
114 dwarf_fctrl_i386 = 37, // x87 control word
115 dwarf_fstat_i386 = 38, // x87 status word
116 dwarf_mxcsr_i386 = 39,
124 // I believe the ymm registers use the dwarf_xmm%_i386 register numbers and
125 // then differentiate based on size of the register.
126 dwarf_bnd0_i386 = 101,
132 // AMD x86_64, AMD64, Intel EM64T, or Intel 64 ehframe, dwarf regnums
134 // EHFrame and DWARF Register numbers (eRegisterKindEHFrame &
135 // eRegisterKindDWARF)
136 // This is the spec I used (as opposed to x86-64-abi-0.99.pdf):
137 // http://software.intel.com/sites/default/files/article/402129/mpx-linux64-abi.pdf
140 dwarf_rax_x86_64 = 0,
148 // Extended GP Registers
157 // Return Address (RA) mapped to RIP
158 dwarf_rip_x86_64 = 16,
159 // SSE Vector Registers
160 dwarf_xmm0_x86_64 = 17,
176 // Floating Point Registers
177 dwarf_st0_x86_64 = 33,
186 dwarf_mm0_x86_64 = 41,
194 // Control and Status Flags Register
195 dwarf_rflags_x86_64 = 49,
196 // selector registers
197 dwarf_es_x86_64 = 50,
203 // Floating point control registers
204 dwarf_mxcsr_x86_64 = 64, // Media Control and Status
205 dwarf_fctrl_x86_64, // x87 control word
206 dwarf_fstat_x86_64, // x87 status word
207 // Upper Vector Registers
208 dwarf_ymm0h_x86_64 = 67,
225 dwarf_bnd0_x86_64 = 126,
229 // AVX2 Vector Mask Registers
230 // dwarf_k0_x86_64 = 118,
240 // Generic floating-point registers
248 uint8_t bytes[16]; // 128-bits for each XMM register
251 // i387_fxsave_struct
253 uint16_t fctrl; // FPU Control Word (fcw)
254 uint16_t fstat; // FPU Status Word (fsw)
255 uint16_t ftag; // FPU Tag Word (ftw)
256 uint16_t fop; // Last Instruction Opcode (fop)
259 uint64_t fip; // Instruction Pointer
260 uint64_t fdp; // Data Pointer
263 uint32_t fioff; // FPU IP Offset (fip)
264 uint32_t fiseg; // FPU IP Selector (fcs)
265 uint32_t fooff; // FPU Operand Pointer Offset (foo)
266 uint32_t foseg; // FPU Operand Pointer Selector (fos)
267 } i386_; // Added _ in the end to avoid error with gcc defining i386 in some
270 uint32_t mxcsr; // MXCSR Register State
271 uint32_t mxcsrmask; // MXCSR Mask
272 MMSReg stmm[8]; // 8*16 bytes for each FP-reg = 128 bytes
273 XMMReg xmm[16]; // 16*16 bytes for each XMM-reg = 256 bytes
274 uint8_t padding1[48];
276 uint8_t padding2[40];
279 // Extended floating-point registers
282 uint8_t bytes[16]; // 16 * 8 bits for the high bytes of each YMM register
286 uint8_t bytes[32]; // 16 * 16 bits for each YMM register
290 YMMReg ymm[16]; // assembled from ymmh and xmm registers
294 uint8_t bytes[16]; // MPX 128 bit bound registers
298 uint8_t bytes[8]; // MPX 64 bit bndcfgu and bndstatus registers (collectively
309 enum class XFeature : uint64_t {
314 BNDCSR = BNDREGS << 1,
315 OPMASK = BNDCSR << 1,
316 ZMM_Hi256 = OPMASK << 1,
317 Hi16_ZMM = ZMM_Hi256 << 1,
320 LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue*/ PKRU)
323 XFeature xstate_bv; // OS enabled xstate mask to determine the extended states
324 // supported by the processor
325 XFeature xcomp_bv; // Mask to indicate the format of the XSAVE area and of
326 // the XRSTOR instruction
327 uint64_t reserved1[1];
328 uint64_t reserved2[5];
330 static_assert(sizeof(XSAVE_HDR) == 64, "XSAVE_HDR layout incorrect");
333 // x86 extensions to FXSAVE (i.e. for AVX and MPX processors)
336 FXSAVE i387; // floating point registers typical in i387_fxsave_struct
337 XSAVE_HDR header; // The xsave_hdr_struct can be used to determine if the
338 // following extensions are usable
339 YMMHReg ymmh[16]; // High 16 bytes of each of 16 YMM registers (the low bytes
340 // are in FXSAVE.xmm for compatibility with SSE)
341 uint64_t reserved3[16];
342 MPXReg mpxr[4]; // MPX BNDREG state, containing 128-bit bound registers
343 MPXCsr mpxc[2]; // MPX BNDCSR state, containing 64-bit BNDCFGU and
344 // BNDSTATUS registers
348 // Floating-point registers
350 FXSAVE fxsave; // Generic floating-point registers.
351 XSAVE xsave; // x86 extended processor state.
354 LLVM_ENABLE_BITMASK_ENUMS_IN_NAMESPACE();
356 // Convenience function to combine YMM register data from XSAVE-style input.
357 inline YMMReg XStateToYMM(const void* xmm_bytes, const void* ymmh_bytes) {
360 ::memcpy(ret.bytes, xmm_bytes, sizeof(XMMReg));
361 ::memcpy(ret.bytes + sizeof(XMMReg), ymmh_bytes, sizeof(YMMHReg));
366 // Convenience function to copy YMM register data into XSAVE-style output.
367 inline void YMMToXState(const YMMReg& input, void* xmm_bytes, void* ymmh_bytes) {
368 ::memcpy(xmm_bytes, input.bytes, sizeof(XMMReg));
369 ::memcpy(ymmh_bytes, input.bytes + sizeof(XMMReg), sizeof(YMMHReg));
372 } // namespace lldb_private