1 //===-- RegisterContext_x86.h -----------------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef liblldb_RegisterContext_x86_H_
11 #define liblldb_RegisterContext_x86_H_
16 #include "llvm/ADT/BitmaskEnum.h"
17 #include "llvm/Support/Compiler.h"
19 namespace lldb_private {
20 //---------------------------------------------------------------------------
21 // i386 ehframe, dwarf regnums
22 //---------------------------------------------------------------------------
24 // Register numbers seen in eh_frame (eRegisterKindEHFrame) on i386 systems
33 // on Darwin esp & ebp are reversed in the eh_frame section for i386 (versus
34 // dwarf's reg numbering).
36 // i386+darwin eh_frame: 4 is ebp, 5 is esp
37 // i386+everyone else eh_frame: 4 is esp, 5 is ebp
38 // i386 dwarf: 4 is esp, 5 is ebp
39 // lldb will get the darwin-specific eh_frame reg numberings from debugserver,
41 // only encode the generally correct 4 == esp, 5 == ebp numbers in this
50 ehframe_st0_i386 = 12,
58 ehframe_xmm0_i386 = 21,
66 ehframe_mm0_i386 = 29,
76 // DWARF register numbers (eRegisterKindDWARF)
77 // Intel's x86 or IA-32
79 // General Purpose Registers.
90 // Floating Point Registers
100 dwarf_xmm0_i386 = 21,
117 dwarf_fctrl_i386 = 37, // x87 control word
118 dwarf_fstat_i386 = 38, // x87 status word
119 dwarf_mxcsr_i386 = 39,
127 // I believe the ymm registers use the dwarf_xmm%_i386 register numbers and
128 // then differentiate based on size of the register.
129 dwarf_bnd0_i386 = 101,
135 //---------------------------------------------------------------------------
136 // AMD x86_64, AMD64, Intel EM64T, or Intel 64 ehframe, dwarf regnums
137 //---------------------------------------------------------------------------
139 // EHFrame and DWARF Register numbers (eRegisterKindEHFrame &
140 // eRegisterKindDWARF)
141 // This is the spec I used (as opposed to x86-64-abi-0.99.pdf):
142 // http://software.intel.com/sites/default/files/article/402129/mpx-linux64-abi.pdf
145 dwarf_rax_x86_64 = 0,
153 // Extended GP Registers
162 // Return Address (RA) mapped to RIP
163 dwarf_rip_x86_64 = 16,
164 // SSE Vector Registers
165 dwarf_xmm0_x86_64 = 17,
181 // Floating Point Registers
182 dwarf_st0_x86_64 = 33,
191 dwarf_mm0_x86_64 = 41,
199 // Control and Status Flags Register
200 dwarf_rflags_x86_64 = 49,
201 // selector registers
202 dwarf_es_x86_64 = 50,
208 // Floating point control registers
209 dwarf_mxcsr_x86_64 = 64, // Media Control and Status
210 dwarf_fctrl_x86_64, // x87 control word
211 dwarf_fstat_x86_64, // x87 status word
212 // Upper Vector Registers
213 dwarf_ymm0h_x86_64 = 67,
230 dwarf_bnd0_x86_64 = 126,
234 // AVX2 Vector Mask Registers
235 // dwarf_k0_x86_64 = 118,
245 //---------------------------------------------------------------------------
246 // Generic floating-point registers
247 //---------------------------------------------------------------------------
255 uint8_t bytes[16]; // 128-bits for each XMM register
258 // i387_fxsave_struct
260 uint16_t fctrl; // FPU Control Word (fcw)
261 uint16_t fstat; // FPU Status Word (fsw)
262 uint16_t ftag; // FPU Tag Word (ftw)
263 uint16_t fop; // Last Instruction Opcode (fop)
266 uint64_t fip; // Instruction Pointer
267 uint64_t fdp; // Data Pointer
270 uint32_t fioff; // FPU IP Offset (fip)
271 uint32_t fiseg; // FPU IP Selector (fcs)
272 uint32_t fooff; // FPU Operand Pointer Offset (foo)
273 uint32_t foseg; // FPU Operand Pointer Selector (fos)
274 } i386_; // Added _ in the end to avoid error with gcc defining i386 in some
277 uint32_t mxcsr; // MXCSR Register State
278 uint32_t mxcsrmask; // MXCSR Mask
279 MMSReg stmm[8]; // 8*16 bytes for each FP-reg = 128 bytes
280 XMMReg xmm[16]; // 16*16 bytes for each XMM-reg = 256 bytes
281 uint8_t padding1[48];
283 uint8_t padding2[40];
286 //---------------------------------------------------------------------------
287 // Extended floating-point registers
288 //---------------------------------------------------------------------------
291 uint8_t bytes[16]; // 16 * 8 bits for the high bytes of each YMM register
295 uint8_t bytes[32]; // 16 * 16 bits for each YMM register
299 YMMReg ymm[16]; // assembled from ymmh and xmm registers
303 uint8_t bytes[16]; // MPX 128 bit bound registers
307 uint8_t bytes[8]; // MPX 64 bit bndcfgu and bndstatus registers (collectively
318 enum class XFeature : uint64_t {
323 BNDCSR = BNDREGS << 1,
324 OPMASK = BNDCSR << 1,
325 ZMM_Hi256 = OPMASK << 1,
326 Hi16_ZMM = ZMM_Hi256 << 1,
329 LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue*/ PKRU)
332 XFeature xstate_bv; // OS enabled xstate mask to determine the extended states
333 // supported by the processor
334 XFeature xcomp_bv; // Mask to indicate the format of the XSAVE area and of
335 // the XRSTOR instruction
336 uint64_t reserved1[1];
337 uint64_t reserved2[5];
339 static_assert(sizeof(XSAVE_HDR) == 64, "XSAVE_HDR layout incorrect");
342 // x86 extensions to FXSAVE (i.e. for AVX and MPX processors)
344 struct LLVM_ALIGNAS(64) XSAVE {
345 FXSAVE i387; // floating point registers typical in i387_fxsave_struct
346 XSAVE_HDR header; // The xsave_hdr_struct can be used to determine if the
347 // following extensions are usable
348 YMMHReg ymmh[16]; // High 16 bytes of each of 16 YMM registers (the low bytes
349 // are in FXSAVE.xmm for compatibility with SSE)
350 uint64_t reserved3[16];
351 MPXReg mpxr[4]; // MPX BNDREG state, containing 128-bit bound registers
352 MPXCsr mpxc[2]; // MPX BNDCSR state, containing 64-bit BNDCFGU and
353 // BNDSTATUS registers
357 // Floating-point registers
359 FXSAVE fxsave; // Generic floating-point registers.
360 XSAVE xsave; // x86 extended processor state.
363 LLVM_ENABLE_BITMASK_ENUMS_IN_NAMESPACE();
365 } // namespace lldb_private