contrib/llvm/tools/lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h

   1 //===-- RegisterInfos_arm.h -------------------------------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #ifdef DECLARE_REGISTER_INFOS_ARM_STRUCT
  11
  12 #include <stddef.h>
  13
  14 #include "lldb/lldb-defines.h"
  15 #include "lldb/lldb-enumerations.h"
  16 #include "lldb/lldb-private.h"
  17
  18 #include "Utility/ARM_DWARF_Registers.h"
  19 #include "Utility/ARM_ehframe_Registers.h"
  20
  21 using namespace lldb;
  22 using namespace lldb_private;
  23
  24 #ifndef GPR_OFFSET
  25 #error GPR_OFFSET must be defined before including this header file
  26 #endif
  27
  28 #ifndef FPU_OFFSET
  29 #error FPU_OFFSET must be defined before including this header file
  30 #endif
  31
  32 #ifndef FPSCR_OFFSET
  33 #error FPSCR_OFFSET must be defined before including this header file
  34 #endif
  35
  36 #ifndef EXC_OFFSET
  37 #error EXC_OFFSET_NAME must be defined before including this header file
  38 #endif
  39
  40 #ifndef DEFINE_DBG
  41 #error DEFINE_DBG must be defined before including this header file
  42 #endif
  43
  44 enum {
  45   gpr_r0 = 0,
  46   gpr_r1,
  47   gpr_r2,
  48   gpr_r3,
  49   gpr_r4,
  50   gpr_r5,
  51   gpr_r6,
  52   gpr_r7,
  53   gpr_r8,
  54   gpr_r9,
  55   gpr_r10,
  56   gpr_r11,
  57   gpr_r12,
  58   gpr_r13,
  59   gpr_sp = gpr_r13,
  60   gpr_r14,
  61   gpr_lr = gpr_r14,
  62   gpr_r15,
  63   gpr_pc = gpr_r15,
  64   gpr_cpsr,
  65
  66   fpu_s0,
  67   fpu_s1,
  68   fpu_s2,
  69   fpu_s3,
  70   fpu_s4,
  71   fpu_s5,
  72   fpu_s6,
  73   fpu_s7,
  74   fpu_s8,
  75   fpu_s9,
  76   fpu_s10,
  77   fpu_s11,
  78   fpu_s12,
  79   fpu_s13,
  80   fpu_s14,
  81   fpu_s15,
  82   fpu_s16,
  83   fpu_s17,
  84   fpu_s18,
  85   fpu_s19,
  86   fpu_s20,
  87   fpu_s21,
  88   fpu_s22,
  89   fpu_s23,
  90   fpu_s24,
  91   fpu_s25,
  92   fpu_s26,
  93   fpu_s27,
  94   fpu_s28,
  95   fpu_s29,
  96   fpu_s30,
  97   fpu_s31,
  98   fpu_fpscr,
  99
 100   fpu_d0,
 101   fpu_d1,
 102   fpu_d2,
 103   fpu_d3,
 104   fpu_d4,
 105   fpu_d5,
 106   fpu_d6,
 107   fpu_d7,
 108   fpu_d8,
 109   fpu_d9,
 110   fpu_d10,
 111   fpu_d11,
 112   fpu_d12,
 113   fpu_d13,
 114   fpu_d14,
 115   fpu_d15,
 116   fpu_d16,
 117   fpu_d17,
 118   fpu_d18,
 119   fpu_d19,
 120   fpu_d20,
 121   fpu_d21,
 122   fpu_d22,
 123   fpu_d23,
 124   fpu_d24,
 125   fpu_d25,
 126   fpu_d26,
 127   fpu_d27,
 128   fpu_d28,
 129   fpu_d29,
 130   fpu_d30,
 131   fpu_d31,
 132
 133   fpu_q0,
 134   fpu_q1,
 135   fpu_q2,
 136   fpu_q3,
 137   fpu_q4,
 138   fpu_q5,
 139   fpu_q6,
 140   fpu_q7,
 141   fpu_q8,
 142   fpu_q9,
 143   fpu_q10,
 144   fpu_q11,
 145   fpu_q12,
 146   fpu_q13,
 147   fpu_q14,
 148   fpu_q15,
 149
 150   exc_exception,
 151   exc_fsr,
 152   exc_far,
 153
 154   dbg_bvr0,
 155   dbg_bvr1,
 156   dbg_bvr2,
 157   dbg_bvr3,
 158   dbg_bvr4,
 159   dbg_bvr5,
 160   dbg_bvr6,
 161   dbg_bvr7,
 162   dbg_bvr8,
 163   dbg_bvr9,
 164   dbg_bvr10,
 165   dbg_bvr11,
 166   dbg_bvr12,
 167   dbg_bvr13,
 168   dbg_bvr14,
 169   dbg_bvr15,
 170
 171   dbg_bcr0,
 172   dbg_bcr1,
 173   dbg_bcr2,
 174   dbg_bcr3,
 175   dbg_bcr4,
 176   dbg_bcr5,
 177   dbg_bcr6,
 178   dbg_bcr7,
 179   dbg_bcr8,
 180   dbg_bcr9,
 181   dbg_bcr10,
 182   dbg_bcr11,
 183   dbg_bcr12,
 184   dbg_bcr13,
 185   dbg_bcr14,
 186   dbg_bcr15,
 187
 188   dbg_wvr0,
 189   dbg_wvr1,
 190   dbg_wvr2,
 191   dbg_wvr3,
 192   dbg_wvr4,
 193   dbg_wvr5,
 194   dbg_wvr6,
 195   dbg_wvr7,
 196   dbg_wvr8,
 197   dbg_wvr9,
 198   dbg_wvr10,
 199   dbg_wvr11,
 200   dbg_wvr12,
 201   dbg_wvr13,
 202   dbg_wvr14,
 203   dbg_wvr15,
 204
 205   dbg_wcr0,
 206   dbg_wcr1,
 207   dbg_wcr2,
 208   dbg_wcr3,
 209   dbg_wcr4,
 210   dbg_wcr5,
 211   dbg_wcr6,
 212   dbg_wcr7,
 213   dbg_wcr8,
 214   dbg_wcr9,
 215   dbg_wcr10,
 216   dbg_wcr11,
 217   dbg_wcr12,
 218   dbg_wcr13,
 219   dbg_wcr14,
 220   dbg_wcr15,
 221
 222   k_num_registers
 223 };
 224
 225 static uint32_t g_s0_invalidates[] = {fpu_d0, fpu_q0, LLDB_INVALID_REGNUM};
 226 static uint32_t g_s1_invalidates[] = {fpu_d0, fpu_q0, LLDB_INVALID_REGNUM};
 227 static uint32_t g_s2_invalidates[] = {fpu_d1, fpu_q0, LLDB_INVALID_REGNUM};
 228 static uint32_t g_s3_invalidates[] = {fpu_d1, fpu_q0, LLDB_INVALID_REGNUM};
 229 static uint32_t g_s4_invalidates[] = {fpu_d2, fpu_q1, LLDB_INVALID_REGNUM};
 230 static uint32_t g_s5_invalidates[] = {fpu_d2, fpu_q1, LLDB_INVALID_REGNUM};
 231 static uint32_t g_s6_invalidates[] = {fpu_d3, fpu_q1, LLDB_INVALID_REGNUM};
 232 static uint32_t g_s7_invalidates[] = {fpu_d3, fpu_q1, LLDB_INVALID_REGNUM};
 233 static uint32_t g_s8_invalidates[] = {fpu_d4, fpu_q2, LLDB_INVALID_REGNUM};
 234 static uint32_t g_s9_invalidates[] = {fpu_d4, fpu_q2, LLDB_INVALID_REGNUM};
 235 static uint32_t g_s10_invalidates[] = {fpu_d5, fpu_q2, LLDB_INVALID_REGNUM};
 236 static uint32_t g_s11_invalidates[] = {fpu_d5, fpu_q2, LLDB_INVALID_REGNUM};
 237 static uint32_t g_s12_invalidates[] = {fpu_d6, fpu_q3, LLDB_INVALID_REGNUM};
 238 static uint32_t g_s13_invalidates[] = {fpu_d6, fpu_q3, LLDB_INVALID_REGNUM};
 239 static uint32_t g_s14_invalidates[] = {fpu_d7, fpu_q3, LLDB_INVALID_REGNUM};
 240 static uint32_t g_s15_invalidates[] = {fpu_d7, fpu_q3, LLDB_INVALID_REGNUM};
 241 static uint32_t g_s16_invalidates[] = {fpu_d8, fpu_q4, LLDB_INVALID_REGNUM};
 242 static uint32_t g_s17_invalidates[] = {fpu_d8, fpu_q4, LLDB_INVALID_REGNUM};
 243 static uint32_t g_s18_invalidates[] = {fpu_d9, fpu_q4, LLDB_INVALID_REGNUM};
 244 static uint32_t g_s19_invalidates[] = {fpu_d9, fpu_q4, LLDB_INVALID_REGNUM};
 245 static uint32_t g_s20_invalidates[] = {fpu_d10, fpu_q5, LLDB_INVALID_REGNUM};
 246 static uint32_t g_s21_invalidates[] = {fpu_d10, fpu_q5, LLDB_INVALID_REGNUM};
 247 static uint32_t g_s22_invalidates[] = {fpu_d11, fpu_q5, LLDB_INVALID_REGNUM};
 248 static uint32_t g_s23_invalidates[] = {fpu_d11, fpu_q5, LLDB_INVALID_REGNUM};
 249 static uint32_t g_s24_invalidates[] = {fpu_d12, fpu_q6, LLDB_INVALID_REGNUM};
 250 static uint32_t g_s25_invalidates[] = {fpu_d12, fpu_q6, LLDB_INVALID_REGNUM};
 251 static uint32_t g_s26_invalidates[] = {fpu_d13, fpu_q6, LLDB_INVALID_REGNUM};
 252 static uint32_t g_s27_invalidates[] = {fpu_d13, fpu_q6, LLDB_INVALID_REGNUM};
 253 static uint32_t g_s28_invalidates[] = {fpu_d14, fpu_q7, LLDB_INVALID_REGNUM};
 254 static uint32_t g_s29_invalidates[] = {fpu_d14, fpu_q7, LLDB_INVALID_REGNUM};
 255 static uint32_t g_s30_invalidates[] = {fpu_d15, fpu_q7, LLDB_INVALID_REGNUM};
 256 static uint32_t g_s31_invalidates[] = {fpu_d15, fpu_q7, LLDB_INVALID_REGNUM};
 257
 258 static uint32_t g_d0_contains[] = {fpu_s0, fpu_s1, LLDB_INVALID_REGNUM};
 259 static uint32_t g_d1_contains[] = {fpu_s2, fpu_s3, LLDB_INVALID_REGNUM};
 260 static uint32_t g_d2_contains[] = {fpu_s4, fpu_s5, LLDB_INVALID_REGNUM};
 261 static uint32_t g_d3_contains[] = {fpu_s6, fpu_s7, LLDB_INVALID_REGNUM};
 262 static uint32_t g_d4_contains[] = {fpu_s8, fpu_s9, LLDB_INVALID_REGNUM};
 263 static uint32_t g_d5_contains[] = {fpu_s10, fpu_s11, LLDB_INVALID_REGNUM};
 264 static uint32_t g_d6_contains[] = {fpu_s12, fpu_s13, LLDB_INVALID_REGNUM};
 265 static uint32_t g_d7_contains[] = {fpu_s14, fpu_s15, LLDB_INVALID_REGNUM};
 266 static uint32_t g_d8_contains[] = {fpu_s16, fpu_s17, LLDB_INVALID_REGNUM};
 267 static uint32_t g_d9_contains[] = {fpu_s18, fpu_s19, LLDB_INVALID_REGNUM};
 268 static uint32_t g_d10_contains[] = {fpu_s20, fpu_s21, LLDB_INVALID_REGNUM};
 269 static uint32_t g_d11_contains[] = {fpu_s22, fpu_s23, LLDB_INVALID_REGNUM};
 270 static uint32_t g_d12_contains[] = {fpu_s24, fpu_s25, LLDB_INVALID_REGNUM};
 271 static uint32_t g_d13_contains[] = {fpu_s26, fpu_s27, LLDB_INVALID_REGNUM};
 272 static uint32_t g_d14_contains[] = {fpu_s28, fpu_s29, LLDB_INVALID_REGNUM};
 273 static uint32_t g_d15_contains[] = {fpu_s30, fpu_s31, LLDB_INVALID_REGNUM};
 274
 275 static uint32_t g_d0_invalidates[] = {fpu_q0, LLDB_INVALID_REGNUM};
 276 static uint32_t g_d1_invalidates[] = {fpu_q0, LLDB_INVALID_REGNUM};
 277 static uint32_t g_d2_invalidates[] = {fpu_q1, LLDB_INVALID_REGNUM};
 278 static uint32_t g_d3_invalidates[] = {fpu_q1, LLDB_INVALID_REGNUM};
 279 static uint32_t g_d4_invalidates[] = {fpu_q2, LLDB_INVALID_REGNUM};
 280 static uint32_t g_d5_invalidates[] = {fpu_q2, LLDB_INVALID_REGNUM};
 281 static uint32_t g_d6_invalidates[] = {fpu_q3, LLDB_INVALID_REGNUM};
 282 static uint32_t g_d7_invalidates[] = {fpu_q3, LLDB_INVALID_REGNUM};
 283 static uint32_t g_d8_invalidates[] = {fpu_q4, LLDB_INVALID_REGNUM};
 284 static uint32_t g_d9_invalidates[] = {fpu_q4, LLDB_INVALID_REGNUM};
 285 static uint32_t g_d10_invalidates[] = {fpu_q5, LLDB_INVALID_REGNUM};
 286 static uint32_t g_d11_invalidates[] = {fpu_q5, LLDB_INVALID_REGNUM};
 287 static uint32_t g_d12_invalidates[] = {fpu_q6, LLDB_INVALID_REGNUM};
 288 static uint32_t g_d13_invalidates[] = {fpu_q6, LLDB_INVALID_REGNUM};
 289 static uint32_t g_d14_invalidates[] = {fpu_q7, LLDB_INVALID_REGNUM};
 290 static uint32_t g_d15_invalidates[] = {fpu_q7, LLDB_INVALID_REGNUM};
 291 static uint32_t g_d16_invalidates[] = {fpu_q8, LLDB_INVALID_REGNUM};
 292 static uint32_t g_d17_invalidates[] = {fpu_q8, LLDB_INVALID_REGNUM};
 293 static uint32_t g_d18_invalidates[] = {fpu_q9, LLDB_INVALID_REGNUM};
 294 static uint32_t g_d19_invalidates[] = {fpu_q9, LLDB_INVALID_REGNUM};
 295 static uint32_t g_d20_invalidates[] = {fpu_q10, LLDB_INVALID_REGNUM};
 296 static uint32_t g_d21_invalidates[] = {fpu_q10, LLDB_INVALID_REGNUM};
 297 static uint32_t g_d22_invalidates[] = {fpu_q11, LLDB_INVALID_REGNUM};
 298 static uint32_t g_d23_invalidates[] = {fpu_q11, LLDB_INVALID_REGNUM};
 299 static uint32_t g_d24_invalidates[] = {fpu_q12, LLDB_INVALID_REGNUM};
 300 static uint32_t g_d25_invalidates[] = {fpu_q12, LLDB_INVALID_REGNUM};
 301 static uint32_t g_d26_invalidates[] = {fpu_q13, LLDB_INVALID_REGNUM};
 302 static uint32_t g_d27_invalidates[] = {fpu_q13, LLDB_INVALID_REGNUM};
 303 static uint32_t g_d28_invalidates[] = {fpu_q14, LLDB_INVALID_REGNUM};
 304 static uint32_t g_d29_invalidates[] = {fpu_q14, LLDB_INVALID_REGNUM};
 305 static uint32_t g_d30_invalidates[] = {fpu_q15, LLDB_INVALID_REGNUM};
 306 static uint32_t g_d31_invalidates[] = {fpu_q15, LLDB_INVALID_REGNUM};
 307
 308 static uint32_t g_q0_contains[] = {
 309     fpu_d0, fpu_d1, fpu_s0, fpu_s1, fpu_s2, fpu_s3, LLDB_INVALID_REGNUM};
 310 static uint32_t g_q1_contains[] = {
 311     fpu_d2, fpu_d3, fpu_s4, fpu_s5, fpu_s6, fpu_s7, LLDB_INVALID_REGNUM};
 312 static uint32_t g_q2_contains[] = {
 313     fpu_d4, fpu_d5, fpu_s8, fpu_s9, fpu_s10, fpu_s11, LLDB_INVALID_REGNUM};
 314 static uint32_t g_q3_contains[] = {
 315     fpu_d6, fpu_d7, fpu_s12, fpu_s13, fpu_s14, fpu_s15, LLDB_INVALID_REGNUM};
 316 static uint32_t g_q4_contains[] = {
 317     fpu_d8, fpu_d9, fpu_s16, fpu_s17, fpu_s18, fpu_s19, LLDB_INVALID_REGNUM};
 318 static uint32_t g_q5_contains[] = {
 319     fpu_d10, fpu_d11, fpu_s20, fpu_s21, fpu_s22, fpu_s23, LLDB_INVALID_REGNUM};
 320 static uint32_t g_q6_contains[] = {
 321     fpu_d12, fpu_d13, fpu_s24, fpu_s25, fpu_s26, fpu_s27, LLDB_INVALID_REGNUM};
 322 static uint32_t g_q7_contains[] = {
 323     fpu_d14, fpu_d15, fpu_s28, fpu_s29, fpu_s30, fpu_s31, LLDB_INVALID_REGNUM};
 324 static uint32_t g_q8_contains[] = {fpu_d16, fpu_d17, LLDB_INVALID_REGNUM};
 325 static uint32_t g_q9_contains[] = {fpu_d18, fpu_d19, LLDB_INVALID_REGNUM};
 326 static uint32_t g_q10_contains[] = {fpu_d20, fpu_d21, LLDB_INVALID_REGNUM};
 327 static uint32_t g_q11_contains[] = {fpu_d22, fpu_d23, LLDB_INVALID_REGNUM};
 328 static uint32_t g_q12_contains[] = {fpu_d24, fpu_d25, LLDB_INVALID_REGNUM};
 329 static uint32_t g_q13_contains[] = {fpu_d26, fpu_d27, LLDB_INVALID_REGNUM};
 330 static uint32_t g_q14_contains[] = {fpu_d28, fpu_d29, LLDB_INVALID_REGNUM};
 331 static uint32_t g_q15_contains[] = {fpu_d30, fpu_d31, LLDB_INVALID_REGNUM};
 332
 333 static RegisterInfo g_register_infos_arm[] = {
 334     //  NAME         ALT     SZ   OFFSET          ENCODING          FORMAT
 335     //  EH_FRAME             DWARF                GENERIC
 336     //  PROCESS PLUGIN       LLDB NATIVE      VALUE REGS      INVALIDATE REGS
 337     //  ===========  ======= ==   ==============  ================
 338     //  ====================    ===================  ===================
 339     //  ==========================  ===================  =============
 340     //  ==============  =================
 341     {"r0",
 342      nullptr,
 343      4,
 344      GPR_OFFSET(0),
 345      eEncodingUint,
 346      eFormatHex,
 347      {ehframe_r0, dwarf_r0, LLDB_REGNUM_GENERIC_ARG1, LLDB_INVALID_REGNUM,
 348       gpr_r0},
 349      nullptr,
 350      nullptr,
 351      nullptr,
 352      0},
 353     {"r1",
 354      nullptr,
 355      4,
 356      GPR_OFFSET(1),
 357      eEncodingUint,
 358      eFormatHex,
 359      {ehframe_r1, dwarf_r1, LLDB_REGNUM_GENERIC_ARG2, LLDB_INVALID_REGNUM,
 360       gpr_r1},
 361      nullptr,
 362      nullptr,
 363      nullptr,
 364      0},
 365     {"r2",
 366      nullptr,
 367      4,
 368      GPR_OFFSET(2),
 369      eEncodingUint,
 370      eFormatHex,
 371      {ehframe_r2, dwarf_r2, LLDB_REGNUM_GENERIC_ARG3, LLDB_INVALID_REGNUM,
 372       gpr_r2},
 373      nullptr,
 374      nullptr,
 375      nullptr,
 376      0},
 377     {"r3",
 378      nullptr,
 379      4,
 380      GPR_OFFSET(3),
 381      eEncodingUint,
 382      eFormatHex,
 383      {ehframe_r3, dwarf_r3, LLDB_REGNUM_GENERIC_ARG4, LLDB_INVALID_REGNUM,
 384       gpr_r3},
 385      nullptr,
 386      nullptr,
 387      nullptr,
 388      0},
 389     {"r4",
 390      nullptr,
 391      4,
 392      GPR_OFFSET(4),
 393      eEncodingUint,
 394      eFormatHex,
 395      {ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r4},
 396      nullptr,
 397      nullptr,
 398      nullptr,
 399      0},
 400     {"r5",
 401      nullptr,
 402      4,
 403      GPR_OFFSET(5),
 404      eEncodingUint,
 405      eFormatHex,
 406      {ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r5},
 407      nullptr,
 408      nullptr,
 409      nullptr,
 410      0},
 411     {"r6",
 412      nullptr,
 413      4,
 414      GPR_OFFSET(6),
 415      eEncodingUint,
 416      eFormatHex,
 417      {ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r6},
 418      nullptr,
 419      nullptr,
 420      nullptr,
 421      0},
 422     {"r7",
 423      nullptr,
 424      4,
 425      GPR_OFFSET(7),
 426      eEncodingUint,
 427      eFormatHex,
 428      {ehframe_r7, dwarf_r7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r7},
 429      nullptr,
 430      nullptr,
 431      nullptr,
 432      0},
 433     {"r8",
 434      nullptr,
 435      4,
 436      GPR_OFFSET(8),
 437      eEncodingUint,
 438      eFormatHex,
 439      {ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r8},
 440      nullptr,
 441      nullptr,
 442      nullptr,
 443      0},
 444     {"r9",
 445      nullptr,
 446      4,
 447      GPR_OFFSET(9),
 448      eEncodingUint,
 449      eFormatHex,
 450      {ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r9},
 451      nullptr,
 452      nullptr,
 453      nullptr,
 454      0},
 455     {"r10",
 456      nullptr,
 457      4,
 458      GPR_OFFSET(10),
 459      eEncodingUint,
 460      eFormatHex,
 461      {ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 462       gpr_r10},
 463      nullptr,
 464      nullptr,
 465      nullptr,
 466      0},
 467     {"r11",
 468      nullptr,
 469      4,
 470      GPR_OFFSET(11),
 471      eEncodingUint,
 472      eFormatHex,
 473      {ehframe_r11, dwarf_r11, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM,
 474       gpr_r11},
 475      nullptr,
 476      nullptr,
 477      nullptr,
 478      0},
 479     {"r12",
 480      nullptr,
 481      4,
 482      GPR_OFFSET(12),
 483      eEncodingUint,
 484      eFormatHex,
 485      {ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 486       gpr_r12},
 487      nullptr,
 488      nullptr,
 489      nullptr,
 490      0},
 491     {"sp",
 492      "r13",
 493      4,
 494      GPR_OFFSET(13),
 495      eEncodingUint,
 496      eFormatHex,
 497      {ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM,
 498       gpr_sp},
 499      nullptr,
 500      nullptr,
 501      nullptr,
 502      0},
 503     {"lr",
 504      "r14",
 505      4,
 506      GPR_OFFSET(14),
 507      eEncodingUint,
 508      eFormatHex,
 509      {ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM,
 510       gpr_lr},
 511      nullptr,
 512      nullptr,
 513      nullptr,
 514      0},
 515     {"pc",
 516      "r15",
 517      4,
 518      GPR_OFFSET(15),
 519      eEncodingUint,
 520      eFormatHex,
 521      {ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM,
 522       gpr_pc},
 523      nullptr,
 524      nullptr,
 525      nullptr,
 526      0},
 527     {"cpsr",
 528      "psr",
 529      4,
 530      GPR_OFFSET(16),
 531      eEncodingUint,
 532      eFormatHex,
 533      {ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM,
 534       gpr_cpsr},
 535      nullptr,
 536      nullptr,
 537      nullptr,
 538      0},
 539
 540     {"s0",
 541      nullptr,
 542      4,
 543      FPU_OFFSET(0),
 544      eEncodingIEEE754,
 545      eFormatFloat,
 546      {LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 547       fpu_s0},
 548      nullptr,
 549      g_s0_invalidates,
 550      nullptr,
 551      0},
 552     {"s1",
 553      nullptr,
 554      4,
 555      FPU_OFFSET(1),
 556      eEncodingIEEE754,
 557      eFormatFloat,
 558      {LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 559       fpu_s1},
 560      nullptr,
 561      g_s1_invalidates,
 562      nullptr,
 563      0},
 564     {"s2",
 565      nullptr,
 566      4,
 567      FPU_OFFSET(2),
 568      eEncodingIEEE754,
 569      eFormatFloat,
 570      {LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 571       fpu_s2},
 572      nullptr,
 573      g_s2_invalidates,
 574      nullptr,
 575      0},
 576     {"s3",
 577      nullptr,
 578      4,
 579      FPU_OFFSET(3),
 580      eEncodingIEEE754,
 581      eFormatFloat,
 582      {LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 583       fpu_s3},
 584      nullptr,
 585      g_s3_invalidates,
 586      nullptr,
 587      0},
 588     {"s4",
 589      nullptr,
 590      4,
 591      FPU_OFFSET(4),
 592      eEncodingIEEE754,
 593      eFormatFloat,
 594      {LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 595       fpu_s4},
 596      nullptr,
 597      g_s4_invalidates,
 598      nullptr,
 599      0},
 600     {"s5",
 601      nullptr,
 602      4,
 603      FPU_OFFSET(5),
 604      eEncodingIEEE754,
 605      eFormatFloat,
 606      {LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 607       fpu_s5},
 608      nullptr,
 609      g_s5_invalidates,
 610      nullptr,
 611      0},
 612     {"s6",
 613      nullptr,
 614      4,
 615      FPU_OFFSET(6),
 616      eEncodingIEEE754,
 617      eFormatFloat,
 618      {LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 619       fpu_s6},
 620      nullptr,
 621      g_s6_invalidates,
 622      nullptr,
 623      0},
 624     {"s7",
 625      nullptr,
 626      4,
 627      FPU_OFFSET(7),
 628      eEncodingIEEE754,
 629      eFormatFloat,
 630      {LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 631       fpu_s7},
 632      nullptr,
 633      g_s7_invalidates,
 634      nullptr,
 635      0},
 636     {"s8",
 637      nullptr,
 638      4,
 639      FPU_OFFSET(8),
 640      eEncodingIEEE754,
 641      eFormatFloat,
 642      {LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 643       fpu_s8},
 644      nullptr,
 645      g_s8_invalidates,
 646      nullptr,
 647      0},
 648     {"s9",
 649      nullptr,
 650      4,
 651      FPU_OFFSET(9),
 652      eEncodingIEEE754,
 653      eFormatFloat,
 654      {LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 655       fpu_s9},
 656      nullptr,
 657      g_s9_invalidates,
 658      nullptr,
 659      0},
 660     {"s10",
 661      nullptr,
 662      4,
 663      FPU_OFFSET(10),
 664      eEncodingIEEE754,
 665      eFormatFloat,
 666      {LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 667       fpu_s10},
 668      nullptr,
 669      g_s10_invalidates,
 670      nullptr,
 671      0},
 672     {"s11",
 673      nullptr,
 674      4,
 675      FPU_OFFSET(11),
 676      eEncodingIEEE754,
 677      eFormatFloat,
 678      {LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 679       fpu_s11},
 680      nullptr,
 681      g_s11_invalidates,
 682      nullptr,
 683      0},
 684     {"s12",
 685      nullptr,
 686      4,
 687      FPU_OFFSET(12),
 688      eEncodingIEEE754,
 689      eFormatFloat,
 690      {LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 691       fpu_s12},
 692      nullptr,
 693      g_s12_invalidates,
 694      nullptr,
 695      0},
 696     {"s13",
 697      nullptr,
 698      4,
 699      FPU_OFFSET(13),
 700      eEncodingIEEE754,
 701      eFormatFloat,
 702      {LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 703       fpu_s13},
 704      nullptr,
 705      g_s13_invalidates,
 706      nullptr,
 707      0},
 708     {"s14",
 709      nullptr,
 710      4,
 711      FPU_OFFSET(14),
 712      eEncodingIEEE754,
 713      eFormatFloat,
 714      {LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 715       fpu_s14},
 716      nullptr,
 717      g_s14_invalidates,
 718      nullptr,
 719      0},
 720     {"s15",
 721      nullptr,
 722      4,
 723      FPU_OFFSET(15),
 724      eEncodingIEEE754,
 725      eFormatFloat,
 726      {LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 727       fpu_s15},
 728      nullptr,
 729      g_s15_invalidates,
 730      nullptr,
 731      0},
 732     {"s16",
 733      nullptr,
 734      4,
 735      FPU_OFFSET(16),
 736      eEncodingIEEE754,
 737      eFormatFloat,
 738      {LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 739       fpu_s16},
 740      nullptr,
 741      g_s16_invalidates,
 742      nullptr,
 743      0},
 744     {"s17",
 745      nullptr,
 746      4,
 747      FPU_OFFSET(17),
 748      eEncodingIEEE754,
 749      eFormatFloat,
 750      {LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 751       fpu_s17},
 752      nullptr,
 753      g_s17_invalidates,
 754      nullptr,
 755      0},
 756     {"s18",
 757      nullptr,
 758      4,
 759      FPU_OFFSET(18),
 760      eEncodingIEEE754,
 761      eFormatFloat,
 762      {LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 763       fpu_s18},
 764      nullptr,
 765      g_s18_invalidates,
 766      nullptr,
 767      0},
 768     {"s19",
 769      nullptr,
 770      4,
 771      FPU_OFFSET(19),
 772      eEncodingIEEE754,
 773      eFormatFloat,
 774      {LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 775       fpu_s19},
 776      nullptr,
 777      g_s19_invalidates,
 778      nullptr,
 779      0},
 780     {"s20",
 781      nullptr,
 782      4,
 783      FPU_OFFSET(20),
 784      eEncodingIEEE754,
 785      eFormatFloat,
 786      {LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 787       fpu_s20},
 788      nullptr,
 789      g_s20_invalidates,
 790      nullptr,
 791      0},
 792     {"s21",
 793      nullptr,
 794      4,
 795      FPU_OFFSET(21),
 796      eEncodingIEEE754,
 797      eFormatFloat,
 798      {LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 799       fpu_s21},
 800      nullptr,
 801      g_s21_invalidates,
 802      nullptr,
 803      0},
 804     {"s22",
 805      nullptr,
 806      4,
 807      FPU_OFFSET(22),
 808      eEncodingIEEE754,
 809      eFormatFloat,
 810      {LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 811       fpu_s22},
 812      nullptr,
 813      g_s22_invalidates,
 814      nullptr,
 815      0},
 816     {"s23",
 817      nullptr,
 818      4,
 819      FPU_OFFSET(23),
 820      eEncodingIEEE754,
 821      eFormatFloat,
 822      {LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 823       fpu_s23},
 824      nullptr,
 825      g_s23_invalidates,
 826      nullptr,
 827      0},
 828     {"s24",
 829      nullptr,
 830      4,
 831      FPU_OFFSET(24),
 832      eEncodingIEEE754,
 833      eFormatFloat,
 834      {LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 835       fpu_s24},
 836      nullptr,
 837      g_s24_invalidates,
 838      nullptr,
 839      0},
 840     {"s25",
 841      nullptr,
 842      4,
 843      FPU_OFFSET(25),
 844      eEncodingIEEE754,
 845      eFormatFloat,
 846      {LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 847       fpu_s25},
 848      nullptr,
 849      g_s25_invalidates,
 850      nullptr,
 851      0},
 852     {"s26",
 853      nullptr,
 854      4,
 855      FPU_OFFSET(26),
 856      eEncodingIEEE754,
 857      eFormatFloat,
 858      {LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 859       fpu_s26},
 860      nullptr,
 861      g_s26_invalidates,
 862      nullptr,
 863      0},
 864     {"s27",
 865      nullptr,
 866      4,
 867      FPU_OFFSET(27),
 868      eEncodingIEEE754,
 869      eFormatFloat,
 870      {LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 871       fpu_s27},
 872      nullptr,
 873      g_s27_invalidates,
 874      nullptr,
 875      0},
 876     {"s28",
 877      nullptr,
 878      4,
 879      FPU_OFFSET(28),
 880      eEncodingIEEE754,
 881      eFormatFloat,
 882      {LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 883       fpu_s28},
 884      nullptr,
 885      g_s28_invalidates,
 886      nullptr,
 887      0},
 888     {"s29",
 889      nullptr,
 890      4,
 891      FPU_OFFSET(29),
 892      eEncodingIEEE754,
 893      eFormatFloat,
 894      {LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 895       fpu_s29},
 896      nullptr,
 897      g_s29_invalidates,
 898      nullptr,
 899      0},
 900     {"s30",
 901      nullptr,
 902      4,
 903      FPU_OFFSET(30),
 904      eEncodingIEEE754,
 905      eFormatFloat,
 906      {LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 907       fpu_s30},
 908      nullptr,
 909      g_s30_invalidates,
 910      nullptr,
 911      0},
 912     {"s31",
 913      nullptr,
 914      4,
 915      FPU_OFFSET(31),
 916      eEncodingIEEE754,
 917      eFormatFloat,
 918      {LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 919       fpu_s31},
 920      nullptr,
 921      g_s31_invalidates,
 922      nullptr,
 923      0},
 924     {"fpscr",
 925      nullptr,
 926      4,
 927      FPSCR_OFFSET,
 928      eEncodingUint,
 929      eFormatHex,
 930      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 931       LLDB_INVALID_REGNUM, fpu_fpscr},
 932      nullptr,
 933      nullptr,
 934      nullptr,
 935      0},
 936
 937     {"d0",
 938      nullptr,
 939      8,
 940      FPU_OFFSET(0),
 941      eEncodingIEEE754,
 942      eFormatFloat,
 943      {LLDB_INVALID_REGNUM, dwarf_d0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 944       fpu_d0},
 945      g_d0_contains,
 946      g_d0_invalidates,
 947      nullptr,
 948      0},
 949     {"d1",
 950      nullptr,
 951      8,
 952      FPU_OFFSET(2),
 953      eEncodingIEEE754,
 954      eFormatFloat,
 955      {LLDB_INVALID_REGNUM, dwarf_d1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 956       fpu_d1},
 957      g_d1_contains,
 958      g_d1_invalidates,
 959      nullptr,
 960      0},
 961     {"d2",
 962      nullptr,
 963      8,
 964      FPU_OFFSET(4),
 965      eEncodingIEEE754,
 966      eFormatFloat,
 967      {LLDB_INVALID_REGNUM, dwarf_d2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 968       fpu_d2},
 969      g_d2_contains,
 970      g_d2_invalidates,
 971      nullptr,
 972      0},
 973     {"d3",
 974      nullptr,
 975      8,
 976      FPU_OFFSET(6),
 977      eEncodingIEEE754,
 978      eFormatFloat,
 979      {LLDB_INVALID_REGNUM, dwarf_d3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 980       fpu_d3},
 981      g_d3_contains,
 982      g_d3_invalidates,
 983      nullptr,
 984      0},
 985     {"d4",
 986      nullptr,
 987      8,
 988      FPU_OFFSET(8),
 989      eEncodingIEEE754,
 990      eFormatFloat,
 991      {LLDB_INVALID_REGNUM, dwarf_d4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
 992       fpu_d4},
 993      g_d4_contains,
 994      g_d4_invalidates,
 995      nullptr,
 996      0},
 997     {"d5",
 998      nullptr,
 999      8,
1000      FPU_OFFSET(10),
1001      eEncodingIEEE754,
1002      eFormatFloat,
1003      {LLDB_INVALID_REGNUM, dwarf_d5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1004       fpu_d5},
1005      g_d5_contains,
1006      g_d5_invalidates,
1007      nullptr,
1008      0},
1009     {"d6",
1010      nullptr,
1011      8,
1012      FPU_OFFSET(12),
1013      eEncodingIEEE754,
1014      eFormatFloat,
1015      {LLDB_INVALID_REGNUM, dwarf_d6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1016       fpu_d6},
1017      g_d6_contains,
1018      g_d6_invalidates,
1019      nullptr,
1020      0},
1021     {"d7",
1022      nullptr,
1023      8,
1024      FPU_OFFSET(14),
1025      eEncodingIEEE754,
1026      eFormatFloat,
1027      {LLDB_INVALID_REGNUM, dwarf_d7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1028       fpu_d7},
1029      g_d7_contains,
1030      g_d7_invalidates,
1031      nullptr,
1032      0},
1033     {"d8",
1034      nullptr,
1035      8,
1036      FPU_OFFSET(16),
1037      eEncodingIEEE754,
1038      eFormatFloat,
1039      {LLDB_INVALID_REGNUM, dwarf_d8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1040       fpu_d8},
1041      g_d8_contains,
1042      g_d8_invalidates,
1043      nullptr,
1044      0},
1045     {"d9",
1046      nullptr,
1047      8,
1048      FPU_OFFSET(18),
1049      eEncodingIEEE754,
1050      eFormatFloat,
1051      {LLDB_INVALID_REGNUM, dwarf_d9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1052       fpu_d9},
1053      g_d9_contains,
1054      g_d9_invalidates,
1055      nullptr,
1056      0},
1057     {"d10",
1058      nullptr,
1059      8,
1060      FPU_OFFSET(20),
1061      eEncodingIEEE754,
1062      eFormatFloat,
1063      {LLDB_INVALID_REGNUM, dwarf_d10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1064       fpu_d10},
1065      g_d10_contains,
1066      g_d10_invalidates,
1067      nullptr,
1068      0},
1069     {"d11",
1070      nullptr,
1071      8,
1072      FPU_OFFSET(22),
1073      eEncodingIEEE754,
1074      eFormatFloat,
1075      {LLDB_INVALID_REGNUM, dwarf_d11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1076       fpu_d11},
1077      g_d11_contains,
1078      g_d11_invalidates,
1079      nullptr,
1080      0},
1081     {"d12",
1082      nullptr,
1083      8,
1084      FPU_OFFSET(24),
1085      eEncodingIEEE754,
1086      eFormatFloat,
1087      {LLDB_INVALID_REGNUM, dwarf_d12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1088       fpu_d12},
1089      g_d12_contains,
1090      g_d12_invalidates,
1091      nullptr,
1092      0},
1093     {"d13",
1094      nullptr,
1095      8,
1096      FPU_OFFSET(26),
1097      eEncodingIEEE754,
1098      eFormatFloat,
1099      {LLDB_INVALID_REGNUM, dwarf_d13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1100       fpu_d13},
1101      g_d13_contains,
1102      g_d13_invalidates,
1103      nullptr,
1104      0},
1105     {"d14",
1106      nullptr,
1107      8,
1108      FPU_OFFSET(28),
1109      eEncodingIEEE754,
1110      eFormatFloat,
1111      {LLDB_INVALID_REGNUM, dwarf_d14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1112       fpu_d14},
1113      g_d14_contains,
1114      g_d14_invalidates,
1115      nullptr,
1116      0},
1117     {"d15",
1118      nullptr,
1119      8,
1120      FPU_OFFSET(30),
1121      eEncodingIEEE754,
1122      eFormatFloat,
1123      {LLDB_INVALID_REGNUM, dwarf_d15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1124       fpu_d15},
1125      g_d15_contains,
1126      g_d15_invalidates,
1127      nullptr,
1128      0},
1129     {"d16",
1130      nullptr,
1131      8,
1132      FPU_OFFSET(32),
1133      eEncodingIEEE754,
1134      eFormatFloat,
1135      {LLDB_INVALID_REGNUM, dwarf_d16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1136       fpu_d16},
1137      nullptr,
1138      g_d16_invalidates,
1139      nullptr,
1140      0},
1141     {"d17",
1142      nullptr,
1143      8,
1144      FPU_OFFSET(34),
1145      eEncodingIEEE754,
1146      eFormatFloat,
1147      {LLDB_INVALID_REGNUM, dwarf_d17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1148       fpu_d17},
1149      nullptr,
1150      g_d17_invalidates,
1151      nullptr,
1152      0},
1153     {"d18",
1154      nullptr,
1155      8,
1156      FPU_OFFSET(36),
1157      eEncodingIEEE754,
1158      eFormatFloat,
1159      {LLDB_INVALID_REGNUM, dwarf_d18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1160       fpu_d18},
1161      nullptr,
1162      g_d18_invalidates,
1163      nullptr,
1164      0},
1165     {"d19",
1166      nullptr,
1167      8,
1168      FPU_OFFSET(38),
1169      eEncodingIEEE754,
1170      eFormatFloat,
1171      {LLDB_INVALID_REGNUM, dwarf_d19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1172       fpu_d19},
1173      nullptr,
1174      g_d19_invalidates,
1175      nullptr,
1176      0},
1177     {"d20",
1178      nullptr,
1179      8,
1180      FPU_OFFSET(40),
1181      eEncodingIEEE754,
1182      eFormatFloat,
1183      {LLDB_INVALID_REGNUM, dwarf_d20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1184       fpu_d20},
1185      nullptr,
1186      g_d20_invalidates,
1187      nullptr,
1188      0},
1189     {"d21",
1190      nullptr,
1191      8,
1192      FPU_OFFSET(42),
1193      eEncodingIEEE754,
1194      eFormatFloat,
1195      {LLDB_INVALID_REGNUM, dwarf_d21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1196       fpu_d21},
1197      nullptr,
1198      g_d21_invalidates,
1199      nullptr,
1200      0},
1201     {"d22",
1202      nullptr,
1203      8,
1204      FPU_OFFSET(44),
1205      eEncodingIEEE754,
1206      eFormatFloat,
1207      {LLDB_INVALID_REGNUM, dwarf_d22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1208       fpu_d22},
1209      nullptr,
1210      g_d22_invalidates,
1211      nullptr,
1212      0},
1213     {"d23",
1214      nullptr,
1215      8,
1216      FPU_OFFSET(46),
1217      eEncodingIEEE754,
1218      eFormatFloat,
1219      {LLDB_INVALID_REGNUM, dwarf_d23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1220       fpu_d23},
1221      nullptr,
1222      g_d23_invalidates,
1223      nullptr,
1224      0},
1225     {"d24",
1226      nullptr,
1227      8,
1228      FPU_OFFSET(48),
1229      eEncodingIEEE754,
1230      eFormatFloat,
1231      {LLDB_INVALID_REGNUM, dwarf_d24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1232       fpu_d24},
1233      nullptr,
1234      g_d24_invalidates,
1235      nullptr,
1236      0},
1237     {"d25",
1238      nullptr,
1239      8,
1240      FPU_OFFSET(50),
1241      eEncodingIEEE754,
1242      eFormatFloat,
1243      {LLDB_INVALID_REGNUM, dwarf_d25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1244       fpu_d25},
1245      nullptr,
1246      g_d25_invalidates,
1247      nullptr,
1248      0},
1249     {"d26",
1250      nullptr,
1251      8,
1252      FPU_OFFSET(52),
1253      eEncodingIEEE754,
1254      eFormatFloat,
1255      {LLDB_INVALID_REGNUM, dwarf_d26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1256       fpu_d26},
1257      nullptr,
1258      g_d26_invalidates,
1259      nullptr,
1260      0},
1261     {"d27",
1262      nullptr,
1263      8,
1264      FPU_OFFSET(54),
1265      eEncodingIEEE754,
1266      eFormatFloat,
1267      {LLDB_INVALID_REGNUM, dwarf_d27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1268       fpu_d27},
1269      nullptr,
1270      g_d27_invalidates,
1271      nullptr,
1272      0},
1273     {"d28",
1274      nullptr,
1275      8,
1276      FPU_OFFSET(56),
1277      eEncodingIEEE754,
1278      eFormatFloat,
1279      {LLDB_INVALID_REGNUM, dwarf_d28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1280       fpu_d28},
1281      nullptr,
1282      g_d28_invalidates,
1283      nullptr,
1284      0},
1285     {"d29",
1286      nullptr,
1287      8,
1288      FPU_OFFSET(58),
1289      eEncodingIEEE754,
1290      eFormatFloat,
1291      {LLDB_INVALID_REGNUM, dwarf_d29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1292       fpu_d29},
1293      nullptr,
1294      g_d29_invalidates,
1295      nullptr,
1296      0},
1297     {"d30",
1298      nullptr,
1299      8,
1300      FPU_OFFSET(60),
1301      eEncodingIEEE754,
1302      eFormatFloat,
1303      {LLDB_INVALID_REGNUM, dwarf_d30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1304       fpu_d30},
1305      nullptr,
1306      g_d30_invalidates,
1307      nullptr,
1308      0},
1309     {"d31",
1310      nullptr,
1311      8,
1312      FPU_OFFSET(62),
1313      eEncodingIEEE754,
1314      eFormatFloat,
1315      {LLDB_INVALID_REGNUM, dwarf_d31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1316       fpu_d31},
1317      nullptr,
1318      g_d31_invalidates,
1319      nullptr,
1320      0},
1321
1322     {"q0",
1323      nullptr,
1324      16,
1325      FPU_OFFSET(0),
1326      eEncodingVector,
1327      eFormatVectorOfUInt8,
1328      {LLDB_INVALID_REGNUM, dwarf_q0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1329       fpu_q0},
1330      g_q0_contains,
1331      nullptr,
1332      nullptr,
1333      0},
1334     {"q1",
1335      nullptr,
1336      16,
1337      FPU_OFFSET(4),
1338      eEncodingVector,
1339      eFormatVectorOfUInt8,
1340      {LLDB_INVALID_REGNUM, dwarf_q1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1341       fpu_q1},
1342      g_q1_contains,
1343      nullptr,
1344      nullptr,
1345      0},
1346     {"q2",
1347      nullptr,
1348      16,
1349      FPU_OFFSET(8),
1350      eEncodingVector,
1351      eFormatVectorOfUInt8,
1352      {LLDB_INVALID_REGNUM, dwarf_q2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1353       fpu_q2},
1354      g_q2_contains,
1355      nullptr,
1356      nullptr,
1357      0},
1358     {"q3",
1359      nullptr,
1360      16,
1361      FPU_OFFSET(12),
1362      eEncodingVector,
1363      eFormatVectorOfUInt8,
1364      {LLDB_INVALID_REGNUM, dwarf_q3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1365       fpu_q3},
1366      g_q3_contains,
1367      nullptr,
1368      nullptr,
1369      0},
1370     {"q4",
1371      nullptr,
1372      16,
1373      FPU_OFFSET(16),
1374      eEncodingVector,
1375      eFormatVectorOfUInt8,
1376      {LLDB_INVALID_REGNUM, dwarf_q4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1377       fpu_q4},
1378      g_q4_contains,
1379      nullptr,
1380      nullptr,
1381      0},
1382     {"q5",
1383      nullptr,
1384      16,
1385      FPU_OFFSET(20),
1386      eEncodingVector,
1387      eFormatVectorOfUInt8,
1388      {LLDB_INVALID_REGNUM, dwarf_q5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1389       fpu_q5},
1390      g_q5_contains,
1391      nullptr,
1392      nullptr,
1393      0},
1394     {"q6",
1395      nullptr,
1396      16,
1397      FPU_OFFSET(24),
1398      eEncodingVector,
1399      eFormatVectorOfUInt8,
1400      {LLDB_INVALID_REGNUM, dwarf_q6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1401       fpu_q6},
1402      g_q6_contains,
1403      nullptr,
1404      nullptr,
1405      0},
1406     {"q7",
1407      nullptr,
1408      16,
1409      FPU_OFFSET(28),
1410      eEncodingVector,
1411      eFormatVectorOfUInt8,
1412      {LLDB_INVALID_REGNUM, dwarf_q7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1413       fpu_q7},
1414      g_q7_contains,
1415      nullptr,
1416      nullptr,
1417      0},
1418     {"q8",
1419      nullptr,
1420      16,
1421      FPU_OFFSET(32),
1422      eEncodingVector,
1423      eFormatVectorOfUInt8,
1424      {LLDB_INVALID_REGNUM, dwarf_q8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1425       fpu_q8},
1426      g_q8_contains,
1427      nullptr,
1428      nullptr,
1429      0},
1430     {"q9",
1431      nullptr,
1432      16,
1433      FPU_OFFSET(36),
1434      eEncodingVector,
1435      eFormatVectorOfUInt8,
1436      {LLDB_INVALID_REGNUM, dwarf_q9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1437       fpu_q9},
1438      g_q9_contains,
1439      nullptr,
1440      nullptr,
1441      0},
1442     {"q10",
1443      nullptr,
1444      16,
1445      FPU_OFFSET(40),
1446      eEncodingVector,
1447      eFormatVectorOfUInt8,
1448      {LLDB_INVALID_REGNUM, dwarf_q10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1449       fpu_q10},
1450      g_q10_contains,
1451      nullptr,
1452      nullptr,
1453      0},
1454     {"q11",
1455      nullptr,
1456      16,
1457      FPU_OFFSET(44),
1458      eEncodingVector,
1459      eFormatVectorOfUInt8,
1460      {LLDB_INVALID_REGNUM, dwarf_q11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1461       fpu_q11},
1462      g_q11_contains,
1463      nullptr,
1464      nullptr,
1465      0},
1466     {"q12",
1467      nullptr,
1468      16,
1469      FPU_OFFSET(48),
1470      eEncodingVector,
1471      eFormatVectorOfUInt8,
1472      {LLDB_INVALID_REGNUM, dwarf_q12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1473       fpu_q12},
1474      g_q12_contains,
1475      nullptr,
1476      nullptr,
1477      0},
1478     {"q13",
1479      nullptr,
1480      16,
1481      FPU_OFFSET(52),
1482      eEncodingVector,
1483      eFormatVectorOfUInt8,
1484      {LLDB_INVALID_REGNUM, dwarf_q13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1485       fpu_q13},
1486      g_q13_contains,
1487      nullptr,
1488      nullptr,
1489      0},
1490     {"q14",
1491      nullptr,
1492      16,
1493      FPU_OFFSET(56),
1494      eEncodingVector,
1495      eFormatVectorOfUInt8,
1496      {LLDB_INVALID_REGNUM, dwarf_q14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1497       fpu_q14},
1498      g_q14_contains,
1499      nullptr,
1500      nullptr,
1501      0},
1502     {"q15",
1503      nullptr,
1504      16,
1505      FPU_OFFSET(60),
1506      eEncodingVector,
1507      eFormatVectorOfUInt8,
1508      {LLDB_INVALID_REGNUM, dwarf_q15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1509       fpu_q15},
1510      g_q15_contains,
1511      nullptr,
1512      nullptr,
1513      0},
1514
1515     {"exception",
1516      nullptr,
1517      4,
1518      EXC_OFFSET(0),
1519      eEncodingUint,
1520      eFormatHex,
1521      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1522       LLDB_INVALID_REGNUM, exc_exception},
1523      nullptr,
1524      nullptr,
1525      nullptr,
1526      0},
1527     {"fsr",
1528      nullptr,
1529      4,
1530      EXC_OFFSET(1),
1531      eEncodingUint,
1532      eFormatHex,
1533      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1534       LLDB_INVALID_REGNUM, exc_fsr},
1535      nullptr,
1536      nullptr,
1537      nullptr,
1538      0},
1539     {"far",
1540      nullptr,
1541      4,
1542      EXC_OFFSET(2),
1543      eEncodingUint,
1544      eFormatHex,
1545      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1546       LLDB_INVALID_REGNUM, exc_far},
1547      nullptr,
1548      nullptr,
1549      nullptr,
1550      0},
1551
1552     {DEFINE_DBG(bvr, 0)},
1553     {DEFINE_DBG(bvr, 1)},
1554     {DEFINE_DBG(bvr, 2)},
1555     {DEFINE_DBG(bvr, 3)},
1556     {DEFINE_DBG(bvr, 4)},
1557     {DEFINE_DBG(bvr, 5)},
1558     {DEFINE_DBG(bvr, 6)},
1559     {DEFINE_DBG(bvr, 7)},
1560     {DEFINE_DBG(bvr, 8)},
1561     {DEFINE_DBG(bvr, 9)},
1562     {DEFINE_DBG(bvr, 10)},
1563     {DEFINE_DBG(bvr, 11)},
1564     {DEFINE_DBG(bvr, 12)},
1565     {DEFINE_DBG(bvr, 13)},
1566     {DEFINE_DBG(bvr, 14)},
1567     {DEFINE_DBG(bvr, 15)},
1568
1569     {DEFINE_DBG(bcr, 0)},
1570     {DEFINE_DBG(bcr, 1)},
1571     {DEFINE_DBG(bcr, 2)},
1572     {DEFINE_DBG(bcr, 3)},
1573     {DEFINE_DBG(bcr, 4)},
1574     {DEFINE_DBG(bcr, 5)},
1575     {DEFINE_DBG(bcr, 6)},
1576     {DEFINE_DBG(bcr, 7)},
1577     {DEFINE_DBG(bcr, 8)},
1578     {DEFINE_DBG(bcr, 9)},
1579     {DEFINE_DBG(bcr, 10)},
1580     {DEFINE_DBG(bcr, 11)},
1581     {DEFINE_DBG(bcr, 12)},
1582     {DEFINE_DBG(bcr, 13)},
1583     {DEFINE_DBG(bcr, 14)},
1584     {DEFINE_DBG(bcr, 15)},
1585
1586     {DEFINE_DBG(wvr, 0)},
1587     {DEFINE_DBG(wvr, 1)},
1588     {DEFINE_DBG(wvr, 2)},
1589     {DEFINE_DBG(wvr, 3)},
1590     {DEFINE_DBG(wvr, 4)},
1591     {DEFINE_DBG(wvr, 5)},
1592     {DEFINE_DBG(wvr, 6)},
1593     {DEFINE_DBG(wvr, 7)},
1594     {DEFINE_DBG(wvr, 8)},
1595     {DEFINE_DBG(wvr, 9)},
1596     {DEFINE_DBG(wvr, 10)},
1597     {DEFINE_DBG(wvr, 11)},
1598     {DEFINE_DBG(wvr, 12)},
1599     {DEFINE_DBG(wvr, 13)},
1600     {DEFINE_DBG(wvr, 14)},
1601     {DEFINE_DBG(wvr, 15)},
1602
1603     {DEFINE_DBG(wcr, 0)},
1604     {DEFINE_DBG(wcr, 1)},
1605     {DEFINE_DBG(wcr, 2)},
1606     {DEFINE_DBG(wcr, 3)},
1607     {DEFINE_DBG(wcr, 4)},
1608     {DEFINE_DBG(wcr, 5)},
1609     {DEFINE_DBG(wcr, 6)},
1610     {DEFINE_DBG(wcr, 7)},
1611     {DEFINE_DBG(wcr, 8)},
1612     {DEFINE_DBG(wcr, 9)},
1613     {DEFINE_DBG(wcr, 10)},
1614     {DEFINE_DBG(wcr, 11)},
1615     {DEFINE_DBG(wcr, 12)},
1616     {DEFINE_DBG(wcr, 13)},
1617     {DEFINE_DBG(wcr, 14)},
1618     {DEFINE_DBG(wcr, 15)}};
1619
1620 #endif // DECLARE_REGISTER_INFOS_ARM_STRUCT