contrib/llvm/tools/lldb/source/Plugins/Process/Utility/lldb-arm64-register-enums.h

   1 //===-- lldb-arm64-register-enums.h -----------------------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #ifndef lldb_arm64_register_enums_h
  11 #define lldb_arm64_register_enums_h
  12
  13 namespace lldb_private
  14 {
  15     // LLDB register codes (e.g. RegisterKind == eRegisterKindLLDB)
  16
  17     //---------------------------------------------------------------------------
  18     // Internal codes for all ARM64 registers.
  19     //---------------------------------------------------------------------------
  20     enum
  21     {
  22         k_first_gpr_arm64,
  23         gpr_x0_arm64 = k_first_gpr_arm64,
  24         gpr_x1_arm64,
  25         gpr_x2_arm64,
  26         gpr_x3_arm64,
  27         gpr_x4_arm64,
  28         gpr_x5_arm64,
  29         gpr_x6_arm64,
  30         gpr_x7_arm64,
  31         gpr_x8_arm64,
  32         gpr_x9_arm64,
  33         gpr_x10_arm64,
  34         gpr_x11_arm64,
  35         gpr_x12_arm64,
  36         gpr_x13_arm64,
  37         gpr_x14_arm64,
  38         gpr_x15_arm64,
  39         gpr_x16_arm64,
  40         gpr_x17_arm64,
  41         gpr_x18_arm64,
  42         gpr_x19_arm64,
  43         gpr_x20_arm64,
  44         gpr_x21_arm64,
  45         gpr_x22_arm64,
  46         gpr_x23_arm64,
  47         gpr_x24_arm64,
  48         gpr_x25_arm64,
  49         gpr_x26_arm64,
  50         gpr_x27_arm64,
  51         gpr_x28_arm64,
  52         gpr_fp_arm64,
  53         gpr_lr_arm64,
  54         gpr_sp_arm64,
  55         gpr_pc_arm64,
  56         gpr_cpsr_arm64,
  57
  58         k_last_gpr_arm64 = gpr_cpsr_arm64,
  59
  60         k_first_fpr_arm64,
  61         fpu_v0_arm64 = k_first_fpr_arm64,
  62         fpu_v1_arm64,
  63         fpu_v2_arm64,
  64         fpu_v3_arm64,
  65         fpu_v4_arm64,
  66         fpu_v5_arm64,
  67         fpu_v6_arm64,
  68         fpu_v7_arm64,
  69         fpu_v8_arm64,
  70         fpu_v9_arm64,
  71         fpu_v10_arm64,
  72         fpu_v11_arm64,
  73         fpu_v12_arm64,
  74         fpu_v13_arm64,
  75         fpu_v14_arm64,
  76         fpu_v15_arm64,
  77         fpu_v16_arm64,
  78         fpu_v17_arm64,
  79         fpu_v18_arm64,
  80         fpu_v19_arm64,
  81         fpu_v20_arm64,
  82         fpu_v21_arm64,
  83         fpu_v22_arm64,
  84         fpu_v23_arm64,
  85         fpu_v24_arm64,
  86         fpu_v25_arm64,
  87         fpu_v26_arm64,
  88         fpu_v27_arm64,
  89         fpu_v28_arm64,
  90         fpu_v29_arm64,
  91         fpu_v30_arm64,
  92         fpu_v31_arm64,
  93         fpu_fpsr_arm64,
  94         fpu_fpcr_arm64,
  95         k_last_fpr_arm64 = fpu_fpcr_arm64,
  96
  97         exc_far_arm64,
  98         exc_esr_arm64,
  99         exc_exception_arm64,
 100
 101         dbg_bvr0_arm64,
 102         dbg_bvr1_arm64,
 103         dbg_bvr2_arm64,
 104         dbg_bvr3_arm64,
 105         dbg_bvr4_arm64,
 106         dbg_bvr5_arm64,
 107         dbg_bvr6_arm64,
 108         dbg_bvr7_arm64,
 109         dbg_bvr8_arm64,
 110         dbg_bvr9_arm64,
 111         dbg_bvr10_arm64,
 112         dbg_bvr11_arm64,
 113         dbg_bvr12_arm64,
 114         dbg_bvr13_arm64,
 115         dbg_bvr14_arm64,
 116         dbg_bvr15_arm64,
 117         dbg_bcr0_arm64,
 118         dbg_bcr1_arm64,
 119         dbg_bcr2_arm64,
 120         dbg_bcr3_arm64,
 121         dbg_bcr4_arm64,
 122         dbg_bcr5_arm64,
 123         dbg_bcr6_arm64,
 124         dbg_bcr7_arm64,
 125         dbg_bcr8_arm64,
 126         dbg_bcr9_arm64,
 127         dbg_bcr10_arm64,
 128         dbg_bcr11_arm64,
 129         dbg_bcr12_arm64,
 130         dbg_bcr13_arm64,
 131         dbg_bcr14_arm64,
 132         dbg_bcr15_arm64,
 133         dbg_wvr0_arm64,
 134         dbg_wvr1_arm64,
 135         dbg_wvr2_arm64,
 136         dbg_wvr3_arm64,
 137         dbg_wvr4_arm64,
 138         dbg_wvr5_arm64,
 139         dbg_wvr6_arm64,
 140         dbg_wvr7_arm64,
 141         dbg_wvr8_arm64,
 142         dbg_wvr9_arm64,
 143         dbg_wvr10_arm64,
 144         dbg_wvr11_arm64,
 145         dbg_wvr12_arm64,
 146         dbg_wvr13_arm64,
 147         dbg_wvr14_arm64,
 148         dbg_wvr15_arm64,
 149         dbg_wcr0_arm64,
 150         dbg_wcr1_arm64,
 151         dbg_wcr2_arm64,
 152         dbg_wcr3_arm64,
 153         dbg_wcr4_arm64,
 154         dbg_wcr5_arm64,
 155         dbg_wcr6_arm64,
 156         dbg_wcr7_arm64,
 157         dbg_wcr8_arm64,
 158         dbg_wcr9_arm64,
 159         dbg_wcr10_arm64,
 160         dbg_wcr11_arm64,
 161         dbg_wcr12_arm64,
 162         dbg_wcr13_arm64,
 163         dbg_wcr14_arm64,
 164         dbg_wcr15_arm64,
 165
 166         k_num_registers_arm64,
 167         k_num_gpr_registers_arm64 = k_last_gpr_arm64 - k_first_gpr_arm64 + 1,
 168         k_num_fpr_registers_arm64 = k_last_fpr_arm64 - k_first_fpr_arm64 + 1
 169     };
 170 }
 171
 172 #endif // #ifndef lldb_arm64_register_enums_h